Ic v924x

V924X Datasheet
Specifications are subject to change without notice.
© 2021 Vango Technologies, Inc.
This document contains information that is proprietary to Vango Technologies, Inc.
Unauthorized reproduction of this information in whole or in part is strictly prohibited.

ULTRALOW POWER, UART, SINGLE-PHASE, POWER MEASUREMENT IC
Revision History
Date Version Description
2017.07.06 1.0 Initial release
Delete raw data related descriptions and other unused descriptions. User
2017.10.18 1.1 can’t read raw data registers. Change register address of T8BAUD from
0x0186 to 0x00E0.
ch
2017-11-08 1.2 Modify the definition of V9260s package pin to support only crystal free
input.
Modify reference voltage to 1.210V.
In order to obtain the best metering performance and temperature
2018.03.12 3.0 performance during normal metering, Bandgap Circuit must be configured
e according to the calculated result. The calculation method, please refer to

Bandgap Circuit chapter.
Modify figure of Power, Clock and so on.

ot
2018.03.27 3.1 Modify formula of offset Calibration of RMS.
2018.05.31 3.2 Modifying the formula of Phase Compensation.

ng
Add the power consumption range: +-10%.
Modify 3.3V power supply to 2.9~3.6V
Modify the typical value of the power down threshold to 2.7V, range
2018.09.01 3.3
2.5V~2.9V
Modify the storage temperature to -55~150°C

Va
Add register AnaCtrl0 (0x182) and AnaCtrl1 (0x183).
2019.01.17 3.4 Remove the threshold for energy.
Add chip mark description.

2019.11.29 3.5
Modify the maximum baud rate to 19200bps.
2020.08.10 3.7 Add PN Junction Temperature.
2020.02.15 3.6 Modify the operating temperature to -40~125°C.
2021.04.15 3.8 Update IEC Standard
Vango Technologies, Inc. -1-

2021.04.30 3.9 Add V9243
2021.07.15 3.10 Modify revision history
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Va

V924X is a multifunction, ultralow power, single-phase power measurement IC with automatic baud rate
adaption UART serial interface.
Features
- 3.3V power supply: 2.9V to 3.6V.  Instantaneous /average current and
voltage RMS;
- Reference: 1.210V (typical drift 10ppm/°C).
 Instantaneous /average active/reactive
- Typical power dissipation in full operation:
power;
1.3mA (+-10%).
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 Line frequency;
- Supporting one current channel for active and
reactive energy metering simultaneously  Phase
- Highly metering accurate: - Automatic baud rate adaption UART interface,

supporting baud rate: 1200bps~19200bps
 Supporting Supports the requirements of

e
IEC 62053-21:2020/ IEC 62053-22:2020
and IEC 62053-23:2020;
Less than 0.1% error for active/reactive

-
-
No input crystal required.
Current input: Shunt resistor or CT

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- Operating temperature:
energy metering over a dynamic range of
5000:1; V9240: -40~+85°C
- 2 independent oversampling ∑/∆ ADCs: one V9243: -40~+105°C

for voltage and one for current.
- Storage temperature: -55~+150°C
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- Various measurements:
- Package: 8-SOP.
 DC components of voltage and current
signals;
Va

Pin Description
TX/RX
DVCC
VSS
REF
8
5
V924X
ch
1
4
VDD33
UP
IAP
IAN
No.
1
Mnemonic
VDD33
e
Type
Input
Description
3.3V power supply. This pin must be connected to a ≥ 0.1μF

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decoupling capacitor.
2 UP Input Positive input for Voltage Channel.
3 IAN Input Negative input for Current Channel A.

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4 IAP Input Positive input for Current Channel A.
Input On-chip reference. This pin must be connected to a 1μF capacitor,

5 REF
/Output and then grounded.
Receiver data input.

6 RX Input
Va
Hold low logic for at least 64ms to reset the chip.
6 TX Output Transmitter data output
Digital power output. Should be connected to a parallel circuit

7 DVCC Output combined by a ≥4.7uF capacitor and a 0.1uF decoupling capacitor,
and then connected to analog ground.
8 VSS Ground Analog/digital ground.

Specifications
All maximum/minimum specifications apply over the entire recommended operation range (T=-40°C
~+85°C, VDD33=3.3V±10%) unless otherwise noted. All typical specifications are at TA=25°C,
VDD33=3.3V unless otherwise noted.
Parameter Min. Typ. Max. Unit Remark
Phase Error Between Channels
PF=0.8 Capacitive ±0.05 Degree
PF=0.5 Inductive ±0.05 Degree
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Dynamic Range 5000:1 @ 25°C
Active Energy Metering
0.1 % Fundamental frequency deviation
Error
within ± 25%
Active Energy Metering

1.6 kHz
Bandwidth
Error
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Reactive Energy Metering
0.1 %
Fundamental frequency deviation

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within ± 25%
Reactive Energy Metering

1.6 kHz
Bandwidth

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VRMS Metering Error 1 % Fundamental frequency deviation

within ± 25%
VRMS Metering Bandwidth 1.6 kHz

IRMS Metering Error 1 % Fundamental frequency deviation
Va
within ± 25%
IRMS Metering Bandwidth 1.6 kHz
Frequency Measurement
Range 40 70 Hz
Error 0.01 Hz
Analog Input
Maximum Signal Level ±200 mV Peak value
ADC
DC Offset 10 mV

Parameter Min. Typ. Max. Unit Remark
Resolution 23 Bit Sign bit is included.
Bandwidth (-3dB) 1.6 kHz
On-chip Reference
Reference Error -18 18 mV @ 25˚C
Power Supply Rejection

80 dB
Ratio
ppm/°
Temperature Coefficient 10 30
C
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Output Voltage 1.210 V
Power Supply
VDD33 2.9 3.3 3.6 V
POR Detection Threshold 1.45 V Error: ±10%
Power-Down
Threshold
eDetection
2.5 2.7 2.9 V
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Digital Power Supply (DVCC)
Voltage 1.8 V Programmable. Error: ±10%
Current 35 mA
Logic Input RX
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Input High Voltage, VINH 2.0 3.6 V
Input Low Voltage, VINL -0.3 0.7 V
Input Current, IIN 1 μA
Input Capacitance, CIN 20 pF

Va
Baud Rate 1200 19200 bps Automatic baud rate adaption

Absolute Maximum Ratings

Operating circumstance exceeding Absolute Maximum Ratings may cause permanent damage to the
device.
Parameters Min. Typ. Max. Unit Description
Digital Power Supply -0.3 +3.6 V To ground.
Analog Power Supply -0.3 +3.6 V To ground.
Analog Input Voltage (IN/IP/UN/UP) -0.3 +3.3 V To ground.
ch
V9240 -40 +85 ˚C
Operating Temperature
V9243 -40 +105 ˚C
Storage Temperature -55 +150 ˚C
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PN Junction Temperature -40 +125 ˚C
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Va

Functional Block Diagram

REF
V924X 1.2V
RMSI_Inst.
REF
RMS RMSI_Avg.
Calculation RMSU_Inst.
DC RMSU_Avg.
BIAS LPF
UP
APGA ADC
U Phase compensation LPF
- HPF AC
DPGA
Active P_Inst.
Power P_Avg.
DC
BIAS LPF
ch
Reactive Q_Inst.
IAP
APGA ADC LPF
- HPF AC
DPGA Power Q_Avg.
IAN IA
Phase Measurement Freq. Measurement

VMA
e CLK_GEN INT LDO SysCtrl UART

ot DVCC
TX/RX
VDD33
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Va

Table of Contents
Revision History ..................................................................................................................... 1
Features ................................................................................................................................. 3
Pin Description ....................................................................................................................... 4
Specifications ......................................................................................................................... 5
Absolute Maximum Ratings .................................................................................................... 7
Functional Block Diagram ....................................................................................................... 8
Table of Contents ................................................................................................................... 0
ch
Figure List .............................................................................................................................. 2
Table List ............................................................................................................................... 3
1. Reset ............................................................................................................................. 5
1.1. Power-On Reset (POR) ................................................................................................ 5
1.2. RX Reset ................................................................................................................... 5
1.3.
1.4.
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Global Software Reset ................................................................................................. 6
Registers ................................................................................................................... 7
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2. Clock ............................................................................................................................. 8
2.1. 3.2768-MHz RC Oscillator ............................................................................................ 8
2.2. 32.768-kHz RC Oscillator ............................................................................................. 8
2.3. Registers ................................................................................................................... 9
3. Operation Mode ........................................................................................................... 10

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3.1. Metering Mode ......................................................................................................... 10
4. Power Supply .............................................................................................................. 11

4.1. Power Supply Monitoring Circuit ................................................................................. 11
4.2. Power on Reset Circuit .............................................................................................. 12
5. Bandgap Circuit ........................................................................................................... 13

Va
6. UART Interface ............................................................................................................ 14

6.1. Data Byte ................................................................................................................ 14
6.2. Communication Protocol ............................................................................................ 14
6.2.1. Write Operation ............................................................................................... 16
6.2.2. Read Operation ................................................................................................ 16
6.2.3. Broadcast Communication ................................................................................. 18
7. Signal Processing ........................................................................................................ 19

7.1. Analog Input ............................................................................................................ 19
7.2. Analog-to-Digital Conversion ...................................................................................... 21
7.3. Phase Compensation ................................................................................................. 21
7.4. Digital Input and DC Removal .................................................................................... 23
7.5. RMS Calculation ....................................................................................................... 24
7.5.1. RMS Calculation Equation.................................................................................. 25

7.5.2. Gain Calibration of RMS .................................................................................... 25
7.5.3. Offset Calibration of RMS .................................................................................. 26
7.6. Power Calculation ..................................................................................................... 26
7.6.1. Gain Calibration of Power .................................................................................. 27
7.6.2. Offset Calibration of Power ................................................................................ 28
7.7. Line Frequency and Phase Measurement ...................................................................... 28
7.7.1. Line Frequency Measurement ............................................................................ 28
7.7.2. Voltage Phase Measurement .............................................................................. 29
7.8. Calibration ............................................................................................................... 30
7.8.1. Registers for Meter Calibration ........................................................................... 30
7.8.2. Equations for Calibration ................................................................................... 31
7.8.3. Calibration Steps ............................................................................................. 34
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8. Interrupt ..................................................................................................................... 36
8.1. Configuration Verification Interrupt ............................................................................. 37
8.2. Zero-Crossing Interrupt ............................................................................................. 38
8.3. Registers ................................................................................................................. 39
9. Registers ..................................................................................................................... 40
9.1. System Control Register ............................................................................................ 40
9.2.
9.3.
9.4.
e
Calibration Parameter Registers .................................................................................. 43
Checksum Register ................................................................................................... 45
Software Reset Control Register ................................................................................. 45
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9.5. System Status Registers ............................................................................................ 46
9.6. Metering Control Registers ......................................................................................... 48
10. Outline Dimensions ..................................................................................................... 52

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Va

Figure List
Figure 1-1 Timing of POR ............................................................................................................................................. 5
Figure 1-2 Timing of RX Reset ................................................................................................................................... 6
Figure 1-3 Timing of Global Software Reset ....................................................................................................... 7
Figure 2-1 Clock Generation ....................................................................................................................................... 8
Figure 4-1 Power Supply Architecture ................................................................................................................. 11
Figure 4-2 Power-Down Interrupt ......................................................................................................................... 12
Figure 6-1 Structure of an 11-Bit Data Byte ..................................................................................................... 14
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Figure 6-2 Command Frame for Read/Write/Broadcast Operation ...................................................... 14
Figure 6-3 Timing of UART Communication ...................................................................................................... 15
Figure 7-1 Analog Input of Current Channel .................................................................................................... 19
Figure 7-2 Analog Input of Voltage Channel .................................................................................................... 20
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Figure 7-3 Phase Compensation ............................................................................................................................. 22
Figure 7-4 Digital Input and DC Removal (Current Signal is taken as an Example) .................... 23
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Figure 7-5 RMS Signal Processing ......................................................................................................................... 24
Figure 7-6 Active Power Calculation ..................................................................................................................... 26
Figure 7-7 Line Frequency Measurement Schematic Diagram ................................................................ 28
Figure 8-1 Zero-Crossing Interrupt ....................................................................................................................... 39

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Va

Table List
Table 1-1 Reset Related Registers ........................................................................................................................... 7
Table 2-1 Clock Generation Related Registers .................................................................................................. 9
Table 3-1 States of Functional Units in Default State .................................................................................. 10
Table 5-1 Configuration for Bandgap Circuit .................................................................................................... 13
Table 6-1 UART Communication Timing Parameters .................................................................................... 15
Table 6-2 Structure of Data Byte (B7:B0) From Master MCU to V924X on Write Operation .... 16
Table 6-3 Structure of Data Byte (B7:B0) From V924X to Master MCU on Write Operation .... 16
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Table 6-4 Structure of Data Byte (B7:B0) From Master MCU to V924X on Read Operation ..... 17
Table 6-5 Structure of Data Byte (B7:B0) From V924X to Master MCU on Read Operation ..... 17
Table 6-6 Structure of Data Byte (B7:B0) From Master MCU to V924X on Broadcast Operation
......................................................................................................................................................................................... 18
e
Table 7-1 Analog PGA Configuration .................................................................................................................... 20
Table 7-2 Analog Control Register 0 (0x0182, AnaCtrl0, R/W) ................................................................ 21

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Table 7-4 Enable/Disable ADCs of Each Channel ........................................................................................... 21
Table 7-5 Registers for phase compensation ................................................................................................... 22

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Table 7-6 fsmpl Determines Phase Compensation Resolution and Correction Range..................... 22
Table 7-7 DC Component Calculation Related Register ............................................................................... 24
Table 7-8 Digital Gain Configuration of Voltage Signal ............................................................................... 24
Table 7-9 RMS Related Registers ........................................................................................................................... 24

Va
Table 7-10 Power Related Registers..................................................................................................................... 27
Table 7-11 Bandpass Filter Parameters .............................................................................................................. 28
Table 7-12 Voltage Frequency Data Register ................................................................................................... 29
Table 7-13 Phase Measurement Related Register (R) ................................................................................... 29
Table 7-14 Meter Calibration Related Registers ............................................................................................. 30
Table 8-1 Interrupt Flag Bits .................................................................................................................................... 36
Table 8-2 Registers for Configuration Verification ........................................................................................ 37
Table 8-3 System Status Clr Register (0x019D, SysStsClr, R/W) ........................................................... 39

Table 9-1 System Control Register (0x0180, SysCtrl, R/W), ................................................................... 40
Table 9-4 Power/RMS/Low-Current Signal Calibration/Phase Calibration Register (R/W) ..... 43
Table 9-5 Checksum Register (0x0109, CKSUM, R/W) ............................................................................... 45
Table 9-6 Software Reset Control Register (0x01BF, SFTRST, W) ........................................................ 45
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Table 9-7 System Status Register (0x00CA, SysSts, R) ................................................................................ 46
Table 9-8 System Status Clr Register (0x019D, SysStsClr, R/W) ............................................................ 47
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Va

1.Reset
In the V924X, the chip will be reset to Default State when POR, RX reset or global software reset occurs.
1.1. Power-On Reset (POR)

In the V924X, the internal power-on reset circuit supervises the output voltage on pin DVCC all the
time. When the output voltage is lower than 1.45V, the reset signal is generated and forces the chip into
reset state. When the output voltage is higher than 1.45V, the reset signal is released and the chip will
get to Default State in 500μs.
ch
When POR event occurs, bit RSTSRC (bit[5:3] of SysSts, 0x00CA) is reset to 0b001.
In the reset state, the master MCU and the specific metering architecture cannot access the RAM.
When the chip exits from the reset state, the RAM will implement self-check in about 1.25ms. If no error
occurs, the RAM can be accessed.
e
In the reset state, the UART serial interface is idle. The interface starts to run immediately once the
chip exits from the reset state.
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DVCC
1.45 V
VSS
When the output voltage on pin “DVCC” is higher
than 1.45 V, the reset signal Will be released and the
500 μs chip will exit from the Reset State in 500 μs.
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Internal reset
signal
Reset state
RAM
self-checking
RAM access 1.25 ms
// When the output voltage on pin “DVCC" is
higher than 1.45 V, RAM can be
accessed in about
Va
1.75 ms 1.75 ms.
UART
communication
Figure 1-1 Timing of POR
1.2. RX Reset
The input on pin RX must be driven low for at least 70ms to force the chip into the reset state. Pull the
logic high, and 900μs later the chip exits from the reset state and gets back to Default State.
When RX reset occurs, bit RSTSRC (bit[5:3] of SysSts, 0x00CA) is reset to 0b011.

occurs, the RAM can be accessed in 30.9ms later after RX reset.
The input on pin RX must be dri ven low

for 70ms to force t he chi p i nto reset
state.
Input on
RX pin
//
900μs
Internal reset
signal When input on pin RX is pulled high, the
chip will exit from the res et s tat e in
900µs and get back to Defaul t State.
Reset st at e
ch
500μs
RAM
RAM Access self-check
1.25ms
//
30.9ms
When input on pin RX is pulled
high, the RAM c an be accessed in
30.9ms.
UART
e
communication
30ms
Baud rat e adaptive init ialization
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Figure 1-2 Timing of RX Reset
1.3. Global Software Reset

In the V924X, writing of 0x4572BEAF in the register SFTRST (0x01BF) can force the chip into the reset
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state, and the chip will exit and get back to Default State in 650μs.
When global software reset occurs, bit RSTSRC(bit[5:3]of SysSts, 0x00CA) is reset to 0b100.
occurs, the RAM can be accessed.
Va

Write of 0x4572BEAF to register
0x01BF to force the chip into reset
Writing of state, and the chip will exit from
the state in 650μs.
register 0x4572BEAF
0x01BF 650μs
Internal reset
signal
Reset state
500μs RAM
RAM Access self-check
1.25ms
//
Write of 0x4572BEAF to register 1.9ms

0x01BF, and 1.9ms later the
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RAM can be accessed.
UART
communication
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Figure 1-3 Timing of Global Software Reset
1.4. Registers
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Table 1-1 Reset Related Registers
Register Bit Description

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Flag bits to indicate the reset source.
Bit5 Bit4 Bit3 Description
0 0 1 A POR event occurred.

0x00CA Bit[5:3]
0 0 0 Reserved.
SysSts RSTSRC
0 1 1 An RX reset event occurred.
Va
0 1 0 Reserved.
1 0 0 A global software reset occurred.
0x01BF, SFTRST
Readable and writable, in the form of 32-bit 2’s complement.
Software Reset Control
Write 0x4572BEAF to the register to reset the system.
Register

2.Clock
There are 2 on-chip RC oscillation circuits (3.2MHz/32KHz) provide clocks for the V924X:
 On-chip 3.2768MHz RC oscillator generates the clock (CLK1) that works as a clock source for the
specific metering architecture (VMA), ADCs and UART serial interface. This circuit can be disabled.
After POR, RX reset or global software reset, this circuit will be enabled automatically.
 On-chip 32.768kHz RC oscillator generates the clock (CLK2) that works as the clock source for the
filters for some key IO ports. This circuit keeps on working until the system is powered off.
Metering clock
MDIV
ch
MEACLK
CLK1 UART clock

UDIV
3.2768MHz RC UARTCLK
ADC Oversampling
clock
ADIV
ADCCLK
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CLK2
IO port filter
32.768kHz RC
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Figure 2-1 Clock Generation
2.1. 3.2768-MHz RC Oscillator

In the V924X, an on-chip 3.2768MHz RC oscillator is designed to generate a 3.2768-MHz (The deviation
Va
is within ± 20% from chip to chip for mass production. The temperature deviation from -40~85(105)
degree for each specific chip is less than 3%.) clock (CLK1) to work as a clock source for the specific
metering architecture, ADCs and UART serial interface.
2.2. 32.768-kHz RC Oscillator

The on-chip 32.768-kHz RC oscillator can generate a 32.768kHz RC clock (CLK2) for the filters for
some key IO ports. This oscillator cannot be disabled until the system is powered off.

2.3. Registers
Table 2-1 Clock Generation Related Registers
Register Bit Default Description
To select the sampling frequency of the oversampling ADC

(ADC clock, ADCCLK). The sampling frequency of the ADCs
must be a quarter or one eighth of the metering clock
(MEACLK) frequency when the chip operates with full
Bit[21:20] functions in Metering Mode.
2’b00
ch
ADCCLKSEL<1:0> 00: 819.2kHz; 01: 409.6kHz; 10: 204.8kHz; 11: 102.4kHz.
When the chip operates with full functions in Metering Mode,

their default values are recommended to be used for the best
performance.
e
To select the clock frequency for the specific metering
architecture (MEACLK).
Bit19 0: 3.2768MHz; 1: 819.2kHz.
0
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MEACLKSEL The sampling frequency of the ADCs must be a quarter or one
0x0180 eighth of the metering clock (MEACLK) frequency when the
chip operates with full functions in Metering Mode.
SysCtrl
Adjust the internal high frequency RC clock frequency (Default

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value is 3.2768MHz.). The default 0b00000 is not adjusted.

For the normal metering, it is recommended to write default
Bit[11:7] values for best performance.
0
RCTRIM<4:0> From “0b00001” to “0b01111”, the RC clock frequency is
decreased by 2% per LSB.
From “0b11111” to “0b10000”, the RC clock frequency is

Va
increased by 2% per LSB.
Bit6 0 RC frequency adjustment. The default frequency of the

metering chip is 50Hz. When the 60Hz system is applied,
RCX12
users can increase the high frequency RC clock default
frequency of 3.2MHZ to 1.2 times of the original.
0: No adjustment
1: X1.2

3.Operation Mode
When the chip is working, it can be reset to Default State when POR, RX reset, or global software reset
occurs. Table 3-1 lists the states of functional units in the V924X in Default State.
In Default State, the typical load current is 500μA. Some easy configuration can drive the chip to work
in Metering Mode.
Table 3-1 States of Functional Units in Default State
Functional Unit Default State
ch
3.2MHz RC oscillator Enabled.
32kHz RC oscillator Enabled.
Bandgap circuit Enabled.
Biasing circuit Enabled.
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Power supply monitoring circuit Enabled.
POR circuit Enabled.

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LDO Enabled.
ADC Disabled.
Specific metering architecture Enabled, but for configuration verification only.
UART serial interface Enabled.

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3.1. Metering Mode

In Default State, the V924X will enter Metering Mode via some easy configuration:
 to enable or disable the ADCs, to configure the sampling frequency to 819.2kHz or 204.8kHz;
Va
 to configure MEACLK frequency to 3.2768MHz or 819.2kHz; the operating mode can be configured
to enable only the parameter configuration self-checking or to achieve all functions.
Vango Technologies, Inc. - 10 -

4.Power Supply
Analog
Oscillator
circuits
VDD33
0.1 μF
Power supply
POR
monitor monitor
ch
monitor
DVCCLDO DVCC
Digital circuits
4.7 μF 0.1 μF
e Figure 4-1 Power Supply Architecture

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The V924X supports a power input 3.3V.
The VDD33 is for the digital circuit power supply, and for the analog circuit power supply, oscillator,
power-on reset, and power-down detection circuit are integrated. The connection among the modules as
shown above.
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4.1. Power Supply Monitoring Circuit

In the V924X, an internal power supply monitoring circuit is designed to supervise the power input on
pin VDD33. When the input on pin VDD33 is less than Power-Down detection threshold, a power-down
Va
interrupt signal is triggered, and the flag bit PDN (bit7 of SysSts) and PDN_R(bit6 of SysSts) are set to
1. When the power down event disappears, the flag bit PDN will be cleared automatically and PDN_R(bit6
of SysSts) should be cleared manually

VDD33
Power-Down
detection
threshold
PDN flag
CLR operation
PDN_R flag
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Figure 4-2 Power-Down Interrupt
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4.2. Power on Reset Circuit
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In the V924X, the internal power-on reset circuit supervises the output voltage on pin DVCC all the
time. When the output voltage is lower than 1.45V, the reset signal is generated and forces the chip into
reset state. When the output voltage is higher than 1.45V, the reset signal is released. Please refer to
1.1 Power-On Reset (POR).
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Va

5.Bandgap Circuit
In the V924X, the Bandgap circuit outputs a reference voltage and bias voltage, about 1.210V with a
typical temperature coefficient of 10ppm/˚C, for ADCs and the 3.2MHz RC oscillator.
By default the Bandgap circuit is enabled.
Users can configure bit[18:16]( REST<2:0>) and bit[15:14]( RESTL<1:0>) of SysCtrl (0x0180) to
adjust the temperature coefficient to compensate the temperature coefficient error introduced by the
external components with the following steps:
1) Assume the current settings of relative bits are REST<2:0>=’010’ and RESTL<1:0>=’00’, which
ch
means an additional +20ppm for temperature coefficient of Bandgap.
2) Measure meter errors in high and low temperature conditions. Assume user has calibrated the meter
error to 0 at 20℃, and the measuring errors are 0.6% at 80℃ and -0.4% at -40℃ separately. Then a -
(0.6%-(-0.4%))/2=-0.5% measuring error needs to be compensated relative to high temperature
working condition, equivalent to -0.5%/(80-20)=-5000/60=-83ppm, rounding to -80ppm.
3) As measuring error is minus two times of REF temperature coefficient error, to compensate a -
e
80ppm error, an additional +40ppm of Bandgap REF temperature coefficient adjustment is needed.
Taking the initial +20ppm setting into consideration, the actual adjustment should be +60ppm. According
to the lookup table of RESTL<1:0> and REST<2:0>, user should set register RESTL<1:0> to ‘01’ and
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REST<2:0> to ‘111’, whose combination equals to a +60ppm temperature coefficient adjustment.
A temperature coefficient drift of x in the Bandgap circuit results in a drift of -2x in the measurement
error.
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Table 5-1 Configuration for Bandgap Circuit
Register bit Description
To finely adjust the temperature coefficient of the Bandgap circuit. In order

to obtain the best metering performance and temperature performance
Va
Bit[18:16] during normal metering, it must be configured according to the calculated

result. The calculation method, please refer to Bandgap Circuit chapter.
REST<2:0>
000: no adjustment; 001: +10ppm; 010: +20ppm; 011: +30ppm; 100:
SysCtrl -40ppm; 101: -30ppm; 110: -20ppm; 111: -10ppm.
0x0180 To roughly adjust the temperature coefficient of the Bandgap circuit. In

order to obtain the best metering performance and temperature
Bit[15:14] performance during normal metering, it must be configured according to
the calculated result. The calculation method, please refer to Bandgap
RESTL<1:0>
Circuit chapter.
00: 0; 01: +70ppm; 10: -140ppm; 11: -70ppm.

6.UART Interface
The V924X supports communication with the master MCU as a slave via UART serial interface. The
UART serial interface has features:
 Asynchronous, half-duplex communication;
 A 11-bit data byte, composed of 1-bit Start bit, 8-bit Data bits, 1-bit Parity bit (odd), and 1-bit Stop
bit;
 Least significant bit (LSB) shifted in or out firstly when the chip receives or transmits a byte;
 Automatic baud rate adaption: support 1200bps~19200bps, and typical baud rates are 1200bps,
2400bps, 4800bps, 9600bps, and 19200bps.
ch
When a reset event, such as POR, RX reset or global software reset, occurs, the UART serial interface
is reset.
6.1. Data Byte
e
The data byte received and transmitted via the UART serial interface of the V924X is composed of 11
bits, including 1-bit Start bit (logic low), 8-bit Data bits, 1-bit odd Parity bit and 1-bit Stop bit (logic
high), as shown in the following figure. When the V924X receives or sends a data byte, the least
ot
significant bit always is shifted in or out firstly.
START B0 B1 B2 B3 B4 B5 B6 B7 P STOP
Figure 6-1 Structure of an 11-Bit Data Byte

ng
6.2. Communication Protocol

In read, write or broadcast communication, the master MCU needs a command frame that is composed
of 8 data bytes to operate a 32-bit data in the V924X.
Va
Address
Head Byte Control Byte Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Check Byte
Byte
Figure 6-2 Command Frame for Read/Write/Broadcast Operation

In read or write operation, when the V924X receives the command frame from the master MCU, it will
reply to the master MCU with a respond frame of different structures. In broadcast communication, the
V924X will not reply to the master MCU to avoid communication conflict.
The following figure depicts the timing of UART communication.

V92xx receives a command frame and sends a respond frame Receive and send
the next frame
// //
START
RX START STOP START 8-bit data, 1-bit parity STOP
// //
tF tR
//
TX START 8-bit data, 1-bit parity STOP START STOP
//
1st to 7th bytes tRB
of the command frame
tRF tRTD tTB tTBD tTRD
tTF
Figure 6-3 Timing of UART Communication
ch
Table 6-1 UART Communication Timing Parameters
Parameter Description
Time to receive a data byte on pin RX.
11
tRB tRB=
baudrate
e
Where, baudrate is the actual baud rate.
The maximum time between two bytes when receiving a command frame on pin “RX”
ot
tRF tRF=20ms
After a timeout event, the UART interface is idle and waits for the next command frame.
The delay between command frame reception on pin RX and respond frame transmission
on pin TX.
ng
1ms≤tRTD≤20ms
tRTD
Please note no respond frame will be transmitted in broadcast communication, and at
least 1ms delay is recommended between two continuous command frames for broadcast
communications.
Time to transmit a respond frame in read or write operation, depending on the structure
Va
tTF
of the frame.
Time to transmit a data byte.
11
tTB tTB=
baudrate
Where baudrate is the actual baud rate.
Delay between two continuous data bytes in a respond frame.

TTBD
0ms≤tTBD≤20ms
The delay between respond frame transmission on pin TX and the next command frame
tTRD
reception on pin RX. More than 1ms is recommended.
tR Rise time of RX and TX, about 300ns.

Parameter Description
tF Fall time of RX and TX, about 300ns.
6.2.1. Write Operation
The master MCU needs a command frame, composed of 8 data bytes, to write of a 32-bit data to the
register of the V924X. When it receives the command frame, the V924X will transmit a respond frame,
composed of 4 data bytes, to reply to the master MCU. On both transmission and reception, the LSB is
shifted in or out firstly.
ch
Table 6-2 Structure of Data Byte (B7:B0) From Master MCU to V924X on Write Operation
Order Byte B7 B6 B5 B4 B3 B2 B1 B0
1 Head Byte 0 1 1 1 1 1 0 1
2 Control Byte The higher 4 bits of the target register address. 0 0 1 0
e
3 Address Byte The lower 8 bits of the target register address.
4 Data Byte 0 Bit[7:0] of the target data.

ot
The checksum. Add the above 7 data bytes, invert the sum, and then add it
8 Check Byte
ng
to 0x33 to obtain the checksum.
Table 6-3 Structure of Data Byte (B7:B0) From V924X to Master MCU on Write Operation
1 Head Byte 0 1 1 1 1 1 0 1
Va
2 Control Byte The higher 4 bits of the target register address. 0 0 1 0
4 Check Byte
6.2.2. Read Operation
The master MCU needs a command frame, composed of 8 data bytes, to read of a 32-bit data of a
register of the V924X. When it receives the command frame, the V924X will transmit a respond frame,
composed of 4×N+4 (1≤N≤255) data bytes, to reply to the master MCU. On both transmission and
reception, the LSB is shifted in or out firstly.

Table 6-4 Structure of Data Byte (B7:B0) From Master MCU to V924X on Read Operation
1 Head Byte 0 1 1 1 1 1 0 1
The higher 4 bits of the target register address

2 Control Byte 0 0 0 1
(D1).
3 Address Byte The lower 8 bits of the target register address (D1).
The length (N, in unit of Word) of the data to be read from the registers
located at the addresses beginning with the target address (D1) given by the
Control Byte and Address Byte. When Data Byte 0 is 0, it means 1 data word
(4 bytes) is read out.
ch
4 Data Byte 0 When the master MCU reads of the target address only, N is 1.
When more than one registers located at continuous addresses beginning

with the target address (D1), N is equal to the number of the address. The
maximum value of N is 255, which means no more than 255 continuous
registers can be read at a time.
6
Data Byte 1
Data Byte 2
e No actual function.
ot
7 Data Byte 3
8 Check Byte
Table 6-5 Structure of Data Byte (B7:B0) From V924X to Master MCU on Read Operation
ng
1 Head Byte 0 1 1 1 1 1 0 1
The higher 4 bits of the target register address

2 Control Byte 0 0 0 1
(D1).
Va
N, equal to Data Byte 0 sent from master MCU to V924X on read operation.
3 Length Byte
When Data Byte 0 is 0, N is equal to 1.
4 Data Byte 10 Bit[7:0] of the register located at target address (D1).
5 Data Byte 11 Bit[15:8] of the register located at target address (D 1).
6 Data Byte 12 Bit[23:16] of the register located at target address (D1).
7 Data Byte 13 Bit[31:24] of the register located at target address (D 1).
8 Data Byte 20 Bit[7:0] of the register located at address D 2 (D2=D1+1).
9 Data Byte 21 Bit[15:8] of the register located at address D2 (D2=D1+1).
… … …

4×N+0 Data Byte N0 Bit[7:0] of the register located at address D N (DN=D1+N-1).
4×N+1 Data Byte N1 Bit[15:8] of the register located at address DN (DN=D1+N-1).
The checksum. Add the above 4×N+3 data bytes, invert the sum, and then
4×N+4 Check Byte
add it to 0x33 to obtain the checksum.
6.2.3. Broadcast Communication
ch
The master MCU needs a command frame, composed of 8 data bytes, to write a 32-bit data to the
registers of more than one V924X in broadcast communication. When receiving a command frame, the
V924X should not transmit a respond frame to reply to the master MCU to avoid communication error.
On receiving a data frame, the LSB is shifted in or out firstly.
e
When the external MCU processes two consecutive broadcast write operations to the metering chip, it
is recommended to wait for at least 1ms.
ot
Table 6-6 Structure of Data Byte (B7:B0) From Master MCU to V924X on Broadcast Operation
1 Head Byte 0 1 1 1 1 1 0 1
2 Control Byte The higher 4 bits of the target register address. X* X* 0 0

ng
4 Data Byte 0 Bit [7:0] of the target data.

Va
8 Check Byte
*X can be 0 or 1.

7.Signal Processing
The metering clock (MEACLK) is sourced by CLK1, generated by the 3.2MHz RC oscillator. When circuit
stops running, the specific metering architecture stops working.
7.1. Analog Input

The V924X supports 1 analog input of current channel.
For the current channel, a current transformer (CT) or shunt resistor can be used for analog inputs.
The double-ended full differential input is adopted. The wiring is shown as below. The shunt resistor can
ch
also be used for the current input with AGND grounded.
CT R1
IP
C1
R3 C3
R4
C2
IN
e
R2
N L
CT
ot
Load R1
IP
C1
C3
Resistor
R2
Shunt
C2
IN
ng
N L Shunt Resistor
Figure 7-1 Analog Input of Current Channel

For voltage channel, a potential transformer (PT) or a resistor-divider network can be used for analog
Va
inputs. The current channel consists of 2 fully differential voltage inputs. And the voltage channel consists
of 2 pseudo differential voltage inputs: UP is positive input for voltage channel, and UN (inside the chip),
connected to ground, is negative input for voltage channel.

PT
UP
CF
RF
N L
Potential Transformer
UP
CF
Ra
RF
ch
L N
Resistor Divider Network
e
Figure 7-2 Analog Input of Voltage Channel
Each input has a maximum voltage of ±200mV, and each pair of a maximum differential voltage of ±
400mV. To match the output signal of the transformers to the measurement scale of the ADCs, analog
ot
programmable gain amplifiers (APGA) with possible gain selection of 1, 4, 16, and 32 for current input,
and of 1 and 4 for voltage input, are set. The analog PGA gain is determined by the output signal of the
transformer. The product of the output signal and PGA gain (including digital and analog PGA) must be
no higher than voltage reference. Equation 7-1 depicts the signal processing of current and voltage:
ng
U' = PGAu ×(Au ×sin ωt + DCu)

Equation 7-1
I' = PGAi ×[Ai ×sin(ωt + ψ) + DCi]
Where PGAu and PGAi is the analog PGA gain for voltage and current; Au and Ai are the amplitude of
the input signals (V); DCu and DCi are the DC components of the raw voltage and current.
Table 7-1 Analog PGA Configuration

Va
Bit26 To set analog PGA gain of analog input of Voltage Channel.

0
GU 0, ×4 (recommended); 1, ×1.
0x0180 To set analog PGA gain of analog input of Current Channel (IA).
SysCtrl The analog PGA gain is determined by the output signal of the
Bit[23:22]
0 sensor. The product of the output signal and PGA gain (both
GIA<1:0> analog and digital) must be no more than voltage reference.
00: ×32; 01: ×16; 10: ×4; 11: ×1.

Table 7-2 Analog Control Register 0 (0x0182, AnaCtrl0, R/W)
Adjust the global bias current. 00: -33%; 01: 1; 10: -66%; 11:
0x0182 -75%.
Bit[9:8] IT<1:0>
AnaCtrl0 Under the normal metering condition, this bit must hold the
default value for proper operation.
ch
Adjust the Miller capacitance of I channel ADC. 00: No

adjustment; 01: Increase 33%; 10: Increase 66%; 11:
0x0183
Bit[29:28] CSEL<1:0> Increase 100%.
AnaCtrl1
For normal metering, the recommended configuration is
e 0b01.
ot
7.2. Analog-to-Digital Conversion
Second-order Σ-ΔADCs are applied in the voltage and current channels in the V924X. In the default
ng
state, all ADCs are disabled.
Table 7-4 Enable/Disable ADCs of Each Channel
Bit29 Set this bit to 1 to enable U Channel ADC. This bit is cleared
Va
0 by default.
0x0180 ADCUPDN
SysCtrl Bit27 Set this bit to 1 to enable IA Channel ADC. This bit is set
0 to 0 by default.
ADCIAPDN
7.3. Phase Compensation

After the analog signal is converted to a digital signal by an ADC, it is subjected to the phase
compensation by the input phase compensation module to eliminate the phase error between the voltage
and current signals due to the mismatch of the sampling circuit and the ADC.
A phase compensation circuit composed of a chain of time-delay units is applied to correct the phase

error between the current and voltage signals. According to the phase lead or lag relationship between
the voltage and current, select one of the signals into the delay circuit for phase compensation. In register
0x00F7, users can configure the phase of IA.
I I
PHC_U_I
PHC_U_I
Time-delay circuit
U U
Figure 7-3 Phase Compensation
Table 7-5 Registers for phase compensation
ch
PHC(0x00F7) Bit[8:0] 0 Where Bit8 is the sign bit of IA channel phase compensation value.
PHCIA 1: Delay voltage signal; 0: Delay current signal.
Bit [8:0]: 9-bit 2’s complement.
e When the operating clock (fsmpl) of metering chip is 3.2768MHz, the

phase compensation resolution is 0.005°/bit, and the maximum
ot
phase error correction range is ±1.4°.
The sampling frequency (fsmpl) of the phase compensation circuit is 3.2768 MHz by default. The phase
compensation resolution is 0.005°/lsb, and the maximum phase error correction range is ±1.4°. The
sampling frequency (fsmpl) of the phase compensation circuit is determined by the configuration of the
MEACLKSEL bit (bit 19, SysCtrl, 0x0180).
ng
Compensate the phase error at power factor of 0.5L . The value (N) of the phase compensation control
register can be calculated by the following formula (rounded up to the result of the calculation):
3011 fsmpl
N = Round( × E× )
2 819200 Equation 7-2
Va
Where
N is the value to be set in bit[8:0] of register PHC (0x00F7);
E is the error displayed in LCD screen of the calibration equipment.
fsmpl is determined by the configuration of MEACLKSEL bits (Bit19, SysCtrl, 0x0180).
Table 7-6 fsmpl Determines Phase Compensation Resolution and Correction Range
Correction
N Configuration fsmpl (Hz) Resolution (°/lsb)
Range (°)
MEACLKSEL 0 3276800 0.005 1.4

[-255, +255]
bit19, 0x0180 1 819200 0.022 5.6

7.4. Digital Input and DC Removal
LPF2 DC
BIAS
from ADC LPF1 - HPF

AC
DPGA
Figure 7-4 Digital Input and DC Removal (Current Signal is taken as an Example)
The 1-bit code stream output from the oversampling Σ/ΔADC can be enabled to be sent to the
ch
decimation filter to suppress the high-frequency noise and to lower the sampling frequency to get the
raw waveform of each signal. And finally the original waveform of the 29-bit (bit[28:27] sign bit) is
received.
The signal input to the decimation filter is enabled or disabled via configuring bit[29:27] of SysCtrl,
0x0180. When this function is enabled, the code stream is accumulated to the filter; when this function
is disabled, a constant “0” is input for digital signal processing.
e
The raw waveform is transferred to a subtractor to remove the direct drift introduced by the external
components and ADCs, with the help of the DC bias preset in registers IAADCC (0x0104)and UADCC
ot
(0x0106). Then, the signals are processed as follows:
- The signals are transferred to low-pass filter LPF2 to obtain the DC components of the signals that
can be read out from registers for DC components;
- By default the signals are transferred to a high-pass filter (HPF) to remove the DC components of
the raw waveforms and obtain the AC components to calculate power and RMS;
ng
The method of obtaining the DC bias value of the oversampling ADC in the IA and U channels is:
- (1)Set Bit[13:12] of SysCtrl (0x0180), SHORTU, and SHORTI;
- (2)Read the values of DC measurement register UDCINST (0x00D9), IADCINST (0x00DA)and write
into the register IAADCC (0x0104)and UADCC (0x0106).
Va
- (3)Clear Bit[13:12] of SysCtrl (0x0180), SHORTU, and SHORTI;
In the DC metering application scenario, the users can disable the DC removal high-pass filter by
configuring the BPHPF bit (bit2, SysCtrl, 0x0180) and configure DC bias values in register IAADCC
(0x0104)and UADCC (0x0106) to eliminate the DC drift introduced by external devices and ADCs, so
that DC power can be calculated.
The data format of the DC component register of the voltage / current signal is 32-bit complement.
The read operation is valid and the write operation is meaningless.
When the energy metering clock frequency is 3.2768MHz, the DC component register data update time
is 160ms and the settling time is 320ms.
When the energy metering clock frequency is 819.2kHz, the DC component register data update time
is 640ms and the settling time is 1280ms.

Table 7-7 DC Component Calculation Related Register
Register Description
Configuration 0x0104 IAADCC IA channel ADC bias current calibration

Register
0x0106 UADCC Voltage ADC bias DC calibration
Data Output 0x00D9 UDCINST U channel Instantaneous DC component

Register
0x00DA IADCINST IA channel instantaneous DC component
The users can configure the digital gain of the voltage signal through the system control register
(SysCtrl, 0x0180) to amplify the AC component of the signal. It can be configured up to 4 times, but the
product of the maximum input signal and the total gain should be guaranteed to be less than the
reference voltage. It is recommended to use the analog gain for gain adjustment.
ch
Table 7-8 Digital Gain Configuration of Voltage Signal
0x0180 Bit1 Configure voltage (U) channel digital gain.

0
SysCtrl PGAU
7.5. RMS Calculation e 0: ×1; 1: ×4.

ot
Gain Cali. AVG IAAVG
AC of IA(t) x IAINST
LPF
ng
S
IADCC
IAC
Figure 7-5 RMS Signal Processing

Va
Table 7-9 RMS Related Registers
Address Register Description R/W Data Format
A channel R
0x00CE IAINST instantaneous current 32-bit 2’s complement
RMS
Instantaneous voltage R
0x00CF UINST 32-bit 2’s complement
RMS
A channel average R
0x00D3 IAAVG 32-bit 2’s complement
current RMS
0x00D4 UAVG Average voltage RMS R 32-bit 2’s complement

A channel current RMS R/W

0x00FD IAC 32-bit 2’s complement
gain calibration

0x00FE IADCC 32-bit 2’s complement
low-current calibration
Voltage RMS gain R/W

0x00FF UC 32-bit 2’s complement
calibration
Voltage RMS value low- R/W

0x0108 UDCC current signal 32-bit 2’s complement
calibration
ch
7.5.1. RMS Calculation Equation
e
In the metering chip design, the voltage/current RMS calculation equation (Take current as an example):
2 PGAi  Ai
Irms   0.99992  PGAdi  Equation 7-3
ot
2 1.210
Where,
PGAdi is the digital PGA gains of current;
PGAi is the analog PGA gains of current;

ng
Ai is the amplitude of current input;
1.210 is the reference voltage;
0.99992 is the gain introduced by the filters.
According to the above method, the raw RMS of each channel signal is obtained. After the gain
Va
calibration, the instantaneous RMS (U / I) is obtained, and then the average RMS (U / I) is obtained. All
of the above values are stored in the corresponding data registers.
When MEACLK frequency is 3.2768MHz, the data are updated in 10ms and settled in 160ms; the
update time for all voltage / current RMS values is 320ms and the settling time is 960ms.
When MEACLK frequency is 819.2kHz, the data are updated in 40ms and settled in 640ms; the update
time for all voltage / current RMS values is 1.28s and the settling time is 3.84s.
7.5.2. Gain Calibration of RMS
The current or voltage RMS calculated via the above equations must be gain calibrated, as depicted in
the following equation:

RMS = RMS’×(1 + S) Equation 7-4
Where,
RMS’ is the raw current or voltage RMS, calculated via the above equations;
RMS is the current or voltage RMS after calibration;
S is the gain calibration, set in registers (IAC、UC).
7.5.3. Offset Calibration of RMS
In order to eliminate the crosstalk noise, the metering chip supports the offset calibration of RMS, the
users can eliminate the noise power by setting the IADCC and UDCC.
ch
Take IA channel as an example, the implementation method is as follows:
Set the current input on the calibration equipment to 0. The average RMS IAAVG is read, and IAAVG
^ 2 is calculated. In the 64bit data, bit[39:8] is taken as the empirical value of the offset calibrated RMS
to write into register IADCC.
e
When the current is re-applied, the accuracy of the current RMS will be effectively improved.
7.6. Power Calculation

ot
Gain Cali. AVG PAAVG
AC of IA(t)
PAINST
ng
AC of U(t) LPF
S
PADCC
PAC
Va
Figure 7-6 Active Power Calculation

The active power is acquired via the following equation:
1 Ai × PGAi × PGAdi Au × PGAu × PGAdu

P= × × × cos  × 0.99985 Equation 7-5
2 1.210 1.210
where, PGAdi and PGAdu are digital PGA gains of current and voltage; PGAi and PGAu are analog PGA
gains of current and voltage; Ai and Au are the amplitude of current and voltage inputs; θ is the phase
difference between voltage and current signals; 0.99985 is the gain introduced by the filters.
When MEACLK frequency is 3.2768MHz, registers for instantaneous active power are updated in 160ms
and settled in 480ms; and registers for average active power are updated in 640ms and settled in 1.28s.
When MEACLK frequency is 819.2kHz, registers for instantaneous active power are updated in 640ms
and settled in 1920ms; and registers for average active power are updated in 2.56s and settled in 5.12s.

The reactive power calculation principle is the same as the active power’.
Table 7-10 Power Related Registers
A channel R
0x00CC PAINST instantaneous active 32-bit 2’s complement
power value
instantaneous reactive R
0x00CD QINST 32-bit 2’s complement
power value
A channel average R
0x00D0 PAAVG 32-bit 2’s complement
active power value
ch
Average reactive power R
0x00D1 QAVG 32-bit 2’s complement
value
To set gain calibration R/W

0x00F6 PAC of active power for A 32-bit 2’s complement
channel
0x00F8 PADCC
e Low-current
calibration of
signal
active
R/W
32-bit 2’s complement
ot
power for A channel

0x00F9 QAC of reactive power for A 32-bit 2’s complement
channel
A reactive power low- R/W

ng
0x00FB QADCC current signal 32-bit 2’s complement

calibration
7.6.1. Gain Calibration of Power

Va
In the metering chip design, in order to correct the system deviation between the various channels,
the calculated active power and reactive power are required to be processed with the gain calibration
first and then be stored into the corresponding data registers.
Assuming the raw active power is P', the RMS after calibration is P, and the gain calibration value is S,
the relationship among the three is as follows:
P  P’  1  S  Equation 7-6
The users can set the corresponding gain calibration values in the power gain registers (PAC, QC).

7.6.2. Offset Calibration of Power
In order to eliminate the crosstalk noise, the metering chip supports the offset calibration of power.
The users can eliminate the noise power by setting the PADCC and QDCC.
7.7. Line Frequency and Phase Measurement
BPF
u(t) From HPF ZERO
CROSSING FREQ
32
32
32
DETECTION
ch
Figure 7-7 Line Frequency Measurement Schematic Diagram
7.7.1. Line Frequency Measurement
e
The V924X supports line frequency measurement. In the line frequency measurement circuit, the
fundamental voltage signal is sampled at a frequency of 6400Hz for negative-to-positive zero-crossing
ot
detection. Each cycle (20ms) outputs a frequency measurement (ie, the number of samples between
two positive zero-crossing values), stored in the frequency instantaneous value register (FREQ, 0x00CB,
read only). In order to improve the frequency measurement accuracy, the average 16 cycles operation
is proceeded toward the instantaneous frequency to get the average frequency (FREQAVG, 0x00D2
readable and writable).
ng
In the V924X, a band-pass filter is applied to remove the direct component, the noise and the harmonic
wave of the voltage signal to obtain the fundamental voltage for line frequency measurement. The
performance of the band-pass filter is affected by the number of bits to be shifted and the filter coefficient.
When fewer bits are shifted, the filter needs less time to respond, is less sensitive to the frequency
deviation, and has less capability to depress the noise and harmonics.
The voltage frequency value can be calculated as follows:

Va
T8BAUD
𝑓 = 0.00390625 × K ′ × Equation 7-7
FREQAVG
Where:
F: Actual voltage frequency
T8BAUD: Value of the register (0x00E0)
FRQAVG: Value of the average frequency register (0x00D2)
K ': Actual baud rate, known by master MCU
When a POR reset, software reset, or RX reset occurs, the voltage frequency register will be reset.
Table 7-11 Bandpass Filter Parameters

Address Register R/W Description Default
Bandpass The filter is used to separate the 0

filter fundamental signal to allow for more
0x0107 BPFPARA coefficient R/W accurate frequency measurement and
phase measurement. At 3.2M clock, the
users need to write into 0x806764B6.
Table 7-12 Voltage Frequency Data Register
Register Description
Instantaneous frequency value register. Read only. When the energy metering
0x00CB FREQINST
clock frequency is 3.2768MHz, it will be updated every 20ms.
ch
Frequency average value per second register. Readable and writable. When the
0x00D2 FREQAVG
energy metering clock frequency is 3.2768MHz, it will be updated every 320ms.
e
7.7.2. Voltage Phase Measurement
The metering chip supports the voltage phase measurement function. The signal processing is shown
ot
in Figure 7-7. The working principle is that the master MCU broadcasts command via UART to write 1 to
the register PHS_STT (0x0198). When it is analyzed as the phase measurement command by the chip,
6.4kHz sampling frequency will be used (At normal operating frequency, the voltage signal sampling
points per cycle is 128 points, that is, 6.4kHz sampling frequency) for counting until the positive zero-
crossing event occurs. The counting value will be written into the phase register PHDAT (0x00DE), and
ng
the positive two voltage sampling values before and after zero-crossing, ZXDATREG (0x00DC), ZXDAT
(0x00DD), will be recorded to facilitate the users to do interpolation operations for more accurate phase
values.
In the multi-metering chip system, according to the values of this register, the phase relationship and
the phase difference among each metering chips can be determined.
Va
Table 7-13 Phase Measurement Related Register (R)
Address Register R/W Data format Default Description
32-bit 2’s 0 The previous sampling value of

0x00DC ZXDATREG R
complement zero-crossing
32-bit 2’s 0x80000000 The sampling value of zero-

0x00DD ZXDAT R
complement crossing
32-bit 2’s 1 Voltage phase data

0x00DE PHDAT R
complement

7.8. Calibration
7.8.1. Registers for Meter Calibration
Table 7-14 Meter Calibration Related Registers
A channel R
0x00CC PAINST instantaneous active 32-bit 2’s complement
power value
ch
instantaneous reactive R
0x00CD QINST 32-bit 2’s complement
power value
A channel R
0x00CE IAINST instantaneous current 32-bit 2’s complement
RMS
0x00CF UINST
e Instantaneous voltage
RMS
R
ot
A channel average R
0x00D0 PAAVG 32-bit 2’s complement
active power value
Average reactive power R

0x00D1 QAVG 32-bit 2’s complement
value
Average frequency R
ng
0x00D2 FREQAVG 32-bit 2’s complement

value
A channel average R
0x00D3 IAAVG 32-bit 2’s complement
current RMS
0x00D4 UAVG Average voltage RMS R 32-bit 2’s complement
To set gain calibration

Va
0x00F6 PAC of active power for A R/W 32-bit 2’s complement

channel
To set phase calibration R/W 32-bit 2’s complement

of active power
Where Bit8 is the sign bit of IA
channel phase compensation value.
1: Delay voltage signal; 0: Delay

0x00F7 PHC current signal.
When the operating clock (fsmpl) of

metering chip is 3.2768MHz, the
phase compensation resolution is

0.005°/bit, and the maximum phase
error correction range is ±1.4°.
Low-current signal R/W 32-bit 2’s complement

0x00F8 PADCC calibration of active
power for A channel

0x00F9 QAC of reactive power for A 32-bit 2’s complement
channel
A reactive power low- R/W

0x00FB QADCC current signal 32-bit 2’s complement
ch
calibration

0x00FD IAC 32-bit 2’s complement
gain calibration

0x00FE IADCC 32-bit 2’s complement
low-current calibration
0x00FF UC
e Voltage
calibration
RMS gain R/W
ot
A channel ADC bias
0x0104 IAADCC R/W 32-bit 2’s complement
current calibration
Voltage ADC bias DC

0x0106 UADCC R/W 32-bit 2’s complement
calibration
ng
Bandpass filter The filter is used to separate the

coefficient fundamental signal to allow for more
accurate frequency measurement
0x0107 BPFPARA R/W
and phase measurement. At 3.2M
clock, the users need to write into
0x806764B6.
Va
Voltage RMS value low-

0x0108 UDCC current signal R/W 32-bit 2’s complement
calibration
7.8.2. Equations for Calibration
1. Equation for current/voltage RMS registers
RMS  V  G  K Equation 7-8
Where, V is the RMS value of the input signal; G is the gain; and K is a coefficient, K=9.19495302×108.
Example 1: When the sampling signal of the voltage channel is 36.7mV and the gain is 4, the value of

the average voltage RMS register (0x00D4) should be
RMS=0.0367×4×9.19495302×108=0x80BA916
2. Equation for active/reactive power registers
Including: Average active power register (PAAVG, 0x00D0) and average reactive power register (QAVG,
0x00D1). The value of the active power register can be calculated according to the following equation:
P = Vi ×Gi ×Vv ×Gv ×Bp ×cosθ Equation 7-9
Q = Vi × Gi × Vv × Gv × Bp × sin Equation 7-10
Where, Vi and Vv are RMS of the input current and voltage; Gi and Gv are the analog PGA gains for
ch
current and voltage respectively; cosθ is the power factor; θ is the phase difference between the current
signal and the voltage signal ; Bp is a coefficient, Bp=7.09441×108.
Example: When Vv is 36.7mV; Gv is 4; Vi is 0.875mV; Gi is 32; cosθ is 1, the value of average

active power register (PAAVG, 0x00D0) should be:
e
Pvalue  0.000875  32  0.0367  4  7.09441 × 10 8  0x2C7EF6
3. Equation for ratio of RMS and power

ot
The value acquired by Equation 7-8, Equation 7-9 and Equation 7-10 is the theoretical value of the
register of RMS or power. It must be multiplied by a ratio to get the actual value as shown on the LCD
screen (Accurate to the second decimal place).
The data of the current/voltage RMS/power register can be calculated according to Equation 7-8,
ng
Equation 7-9 and Equation 7-10 (there is a difference between the calculated data and the direct reading
of the corresponding register data, but not much different). This data is only ADC sampling data, if users
want to convert it into intuitive RMS/power data, the users need to calculate a fixed ratio by the following
equation, and multiply the actual reading of the register and the ratio to get the correct voltage/current
RMS/power, that is, RMS and power data shown on the LCD screen.
Vn
D= Equation 7-11
Va
Value
Where, Value is the value of voltage/current RMS/power registers acquired by Equation 7-8, Equation
7-9 and Equation 7-10; D is the ratio; and Vn is the rated voltage/current/power.
4. Equation for registers for phase compensation
Phase compensation is to ensure that the low power factor can also maintain certain measurement
accuracy. Users must first complete the gain calibration, and then the phase compensation.
The values corresponding to the 9-bit 2’s complement of bit [8: 0] of the phase compensation register
(PHC, 0x00F7) are used to set the phase compensation values.
Compensate the phase error at power factor of 0.5L . The value (N) of the phase compensation control
register can be calculated by the following formula (rounded up to the result of the calculation):

3011 fsmpl
N = Round( × E× )
2 819200 Equation 7-12
Where
N is the value to be set in bit[8:0] of register PHC (0x00F7);
E is the error displayed in LCD screen of the calibration equipment.
fsmpl is determined by the configuration of MEACLKSEL bits (Bit19, SysCtrl, 0x0180).
5. Equation for gain calibration registers
ch
Including all gain registers of power and RMS.
The values of the gain registers can be calculated according to the following equation:
1 1
S = 231 ( - 1) + S1( ) Equation 7-13
1+ e 1+ e
Where,
e
S is the content to be set in the registers for gain calibration of power or RMS, in the form of 2’s
complement;
ot
S1 is the original gain value of the registers; ie the uncalibrated RMS values/the original values of
power gain calibration registers, in the form of 2’s complement;
e is the error: When this equation is used for the power gain calibration, e is the error displayed on
the LCD screen of the calibration equipment (E); when this equation is used for the current/voltage
RMS gain calibration, e is the error (Eu/Ei) calculated by Equation 7-16 or Equation 7-17.
ng
6. Equation for power offset calibration registers
Including: Active/Reactive power offset calibration value register.
The value of the power offset calibration value register (C) can be calculated from the following
Va
equation:
C = -E ×P ×a% Equation 7-14
Where,
E is the error displayed on the LCD screen when a% Ib are applied at power factor of 1.0;
P is value of power register, calculated via Equation 7-9 or Equation 7-10.

7.8.3. Calibration Steps
7.8.3.1. Parameters Configuration
Users must configure the following parameters when designing an energy meter:
- Parameters for a meter, including rated current, rated voltage, pulse constant, and accuracy class,
etc.
- Parameters for design, including the current and voltage RMS when rated current and rated voltage
are applied.
ch
- The analog PGA gains of the current and voltage channels.
- The ratio (D) of RMS and power calculated via Equation 7-11.
When the above parameters are set, no changes should be done to them.
7.8.3.2. Calibrating Power
e
The step of getting the gain calibration value of the power data (E):
ot
1. Read the Pn displayed on the LCD screen of the calibration equipment.
2. Read the power data P1 from the meter LCD (P1 is the product of the value of the average power
data register and the power data scale coefficient D).
3. Calculate the gain calibration value of the power data according to the following method
ng
P1 −Pn
EP = Equation 7-15.
Pn
1. Gain calibration (Take active power for example)
For example, at power fact of 1.0, apply 100% Ib and 100% Un to the calibration equipment.
Va
Get the gain calibration value of the power data (E), and read the value of the gain calibration register
(PAC, 0x00F6), (the raw value for gain calibration, S1) and then calculate the value for gain calibration
via Equation 7-13 and write it to the register PAC (0x00F6).
2. Phase compensation
After completing the power gain calibration, in the case of PF = 0.5L, apply 100% Ib and 100% Un to
the calibration equipment for the phase calibration.
During the gain calibration, the register PHC (0x00F7) must be cleared first. Get the gain calibration
value of the power data (E), calibrate the values of phase compensation according to Equation 7-12, and
write to the corresponding bit of the register.
3. Power offset calibration (optional)
PF = 1.0, 5% Ib (usually, 2% Ib) and 100% Un are applied to the calibration equipment. Get the gain
calibration value of the power data (E). The offset calibration values calculated according to Equation

7-14 must be written into the corresponding power offset calibration register.
7.8.3.3. Calibrating Current RMS
1. Write 0 to the current RMS gain calibration register;
2. When the power factor is 1.0, apply 100% Ib current to the calibration equipment;
3. Read the current RMS I1 from the LCD of meter (I1 is the product of the value of average current
RMS register and the current RMS scale coefficient D);
4. Calculate the value of gain calibration of current RMS according to the following equation:
ch
I - Ib
Calculate error first: Ei = 1 Equation 7-16, the unit of current is mA;
Ib
Calculate the value of gain calibration according to Equation 7-16, and then write to the current
RMS gain calibration register.
e
7.8.3.4. Offset Calibrating of Current RMS (optional)
Take IA channel as an example, the implementation method is as follows:

ot
Set the current input on the calibration equipment to 0. The average RMS IAAVG is read, and IAAVG
^ 2 is calculated. In the 64bit data, bit[39:8] is taken as the empirical value of the offset calibrated RMS
to write into register IADCC.
When the current is re-applied, the accuracy of the current RMS will be effectively improved.
ng
7.8.3.5. Calibrating Voltage RMS
1. Write 0 to the voltage RMS gain calibration register;
2. Apply 100% Un voltage to the calibration equipment;

Va
3. Read the voltage RMS U1 from the meter LCD (U1 is the product of the value of the average
voltage RMS register and the voltage RMS scale coefficient D)
4. Calculate the gain calibration value of the voltage RMS according to the following method
U1 - Un
Calculate error first: Eu = U Equation 7-17, the unit of voltage is mV.
n
Then, calculate the gain calibration value according to Equation 7-17 and write to voltage RMS gain
calibration register.

8.Interrupt
In the V924X, 3 events can trigger interrupt signals that will set the flag bits to 1.
 Configuration verification interrupt;
 zero-crossing interrupt: the voltage sign bit is output as the zero-crossing interrupt;
 Power down interrupt;
The interrupt management circuit keeps on working until it is powered off.
Table 8-1 Interrupt Flag Bits
ch
Voltage sign bit. 1: negative; 0: positive.

Bit11 Read this bit to detect the sign of the voltage. The
0
USIGN flag cannot be cleared. This bit toggles following the
e
sign of the voltage.
Power-down interrupt flag bit.

ot
Bit7 When input voltage on pin VDD33 is lower than
0 Power-Down detection threshold, this bit will be set
PDN
to 1. When the input is higher than Power-Down
detection threshold, this bit will be cleared.
Power-down interrupt flag latch value. This bit is read

ng
as 1 when the system is powered down, ie when the

level on the VDD33 pin is below Power-Down
Bit6 detection threshold. When the power-down event
0x00CA 0 disappears, the flag bit will remain 1 and needs to be
PDN_R
SysSts cleared manually. The flag bit can be cleared by
writing zero to the 0x019D Register to the PDN_CLR
bit.
Va
Bit[5:4] is read only, and bit3 is readable and

writable.
Read the Bit [5: 3] to determine the cause of the

reset.
Bit[5:3] Bit5 Bit4 Bit3 Description
0
RSTSRC 0 0 1 A POR occurs.
0 0 0 Reserved.
0 1 1 A RX reset occurs.
0 1 0 Reserved.

1 0 0 A software reset occurs.
Read this bit for the state of configuration

verification. The read value is refreshed every 5ms.
Read this bit to determine whether a parameter

configuration self-checking error occurs.
Add the content of the registers for calibration,

Bit2
0 metering control registers, analog control registers,
CHKERR and 3 reserved internal registers to the content of the
checksum register to ensure that all the important
ch
configurations are in their desired states. If the sum
is 0xFFFFFFFF, the verification passes, and this bit is
read out as 0; otherwise, the verification fails, and
this bit is read out as 1.
e
8.1. Configuration Verification Interrupt
The metering chip accumulates all the values of all the registers shown in the following table every
ot
5ms.
The configuration verification measure: add the content of the register CKSUM (0x0109) and that of
the other 23 registers listed in the following table. If the sum is 0xFFFFFFFF, it indicates all the
configurations are right; otherwise, it indicates some change has occurred to the registers, an interrupt
signal will be triggered, the flag bit CHKERR (bit2 of SysSts) will be set to 1. The configuration verification
ng
is executed all the time, and the sum is calculated once every 5ms. The flag bit will hold its state until
the sum of the content of 25 registers is 0xFFFFFFFF.
The register CKSUM should be written of the difference between 0xFFFFFFFF and the sum of the content
of the other 23 registers.
Va
Table 8-2 Registers for Configuration Verification
Defaul
No Register R/W
t value
To set gain calibration of active power for

1 0x00F6 PAC R/W 0
A channel
2 0x00F7 PHC To set phase calibration of active power R/W 0
Low-current signal calibration of active

3 0x00F8 PADCC R/W 0
power for A channel
To set gain calibration of reactive power for

4 0x00F9 QAC R/W 0
A channel

Defaul
No Register R/W
t value
A reactive power low-current signal

5 0x00FB QADCC R/W 0
calibration
6 0x00FD IAC A channel current RMS gain calibration R/W 0
A channel current RMS low-current

7 0x00FE IADCC R/W 0
calibration
8 0x00FF UC Voltage RMS gain calibration R/W 0
9 0x0104 IAADCC A channel ADC bias current calibration R/W 0
ch
10 0x0106 UADCC Voltage ADC bias DC calibration R/W 0
11 0x0107 BPFPARA Bandpass filter coefficients R/W 0
12 0x0108 UDCC Voltage RMS low-voltage signal calibration R.W 0
13 0x0109 checksum CKSUM R/W 0
14
15
0x0180
0x0182
e SysCtrl
AnaCtrl0
System configuration register
Analog control register 0

R/W
R/W
0
0
ot
16 0x0183 AnaCtrl1 Analog control register 1 R/W 0
0x00FA\0x00FC
17~
\0x0100~0x01 Keep the default value. R/W 0
23
03\0x0105
ng
8.2. Zero-Crossing Interrupt

The V924X supports voltage zero-crossing interrupt.
When the voltage signal crosses the zero point, a zero-crossing interrupt is triggered, the sign bit
USIGN (bit11, SysSts) toggles following the voltage signal.
Va

Voltage
USIGN_flag bit
ch
Figure 8-1 Zero-Crossing Interrupt
8.3. Registers
e
ot
Table 8-3 System Status Clr Register (0x019D, SysStsClr, R/W)
0x019D, System Status Clr Register, SysStsClr

ng
bit R/W Default Description
Bit[31:10] Reserved R/W N/A The read value is indeterminate and meaningless.
Bit9 PHSDONE_CLR R/W 0 The flag bit for whether the phase measurement ends or
not. 0: Not finished; 1: Finished. It can be cleared by
writing 0 to this bit.
Va
Bit6 PDN_CLR R/W 0 Power down interrupt flag. This bit is read as 1 when the
system is powered down, ie when the level on the VDD33
pin is below Power-Down detection threshold. When the
power-down event disappears, the flag is read as a value
of 1. It can be cleared by writing 0 to this bit.

9.Registers
9.1. System Control Register

When power-on reset (POR), RX reset or global software reset occurs, the system control register will
be reset to its default state. If not specifically noted, the default values in the tables of this section are
in format of hexadecimal. The system control register participates in the parameter configuration self-
checking.
ch
Table 9-1 System Control Register (0x0180, SysCtrl, R/W),
0x0180, R/W, System Control Register, SysCtrl
bit Default Description
These bits must hold their default values for proper

Bit[31:30] Reserved 0
operation.
Bit29
e
ADCUPDN 0
Set this bit to 1 to enable the voltage (U) channel ADC. U
channel ADC is disabled by default.
ot
Bit28 Reserved 0
Set this bit to 1 to enable the current (IA) channel ADC. IA

Bit27 ADCIAPDN 0
channel ADC is disabled by default.
U channel ADC analog gain control. 0: ×4; 1: ×1.

ng
Bit26 GU 0 For normal metering, it is recommended to write default

values for optimum metering performance.
Bit[25:24] Reserved 10
IA channel ADC analog gain control. The users should

determine the PGA according to the sensor’s output signal
Va
Bit[23:22] GIA<1:0> 00 size. It should ensure that the product of maximum signal
and PGA is less than the reference voltage.
00: ×32; 01: ×16; 10: ×4; 11: ×1.
Configure the oversampling ADC clock frequency (sampling

frequency). In the normal metering, it is necessary to
ensure that the ADC sampling frequency is one quarter or
one eighth of the energy metering clock frequency.
Bit[21:20] ADCCLKSEL<1:0> 00
00: 819.2kHz; 01: 409.6kHz; 10: 204.8kHz; 11: 102.4kHz.
In the normal metering, in order to obtain the best metering

performance, it is recommended to write the default values.

Select the energy metering clock frequency. 0: 3.2768MHz;

1: 819.2kHz.
Bit19 MEACLKSEL 0 In the normal metering, it is necessary to ensure that the
ADC sampling frequency is one quarter or one eighth of the
energy metering clock frequency.
The temperature coefficient of the voltage reference

(Bandgap) circuit is slightly adjusted. In order to obtain the
best metering performance and temperature performance
ch
during normal metering, it must be configured according to
Bit[18:16] REST<2:0> 0 the calculated result. The calculation method, please refer
to Bandgap Circuit chapter.
000: 0ppm; 001: +10ppm; 010: +20ppm; 011: +30ppm;

100: -40ppm; 101: -30ppm; 110: -20ppm; 111: -10ppm.
e
The temperature coefficient of the voltage reference
(Bandgap) circuit is roughly adjusted. In order to obtain the
best metering performance and temperature performance
ot
Bit[15:14] RESTL<1:0> 0 during normal metering, it must be configured according to
the calculated result. The calculation method, please refer
to Bandgap Circuit chapter.
00: 0ppm; 01: +70ppm; 10: -140ppm; 11: -70ppm.
When the U channel is input with a DC signal, this bit can

ng
be set to 1 to short the U channel amplifier to obtain the

Bit13 SHORTU 0 offset value of the ADC itself. This function is disabled by
default.
For normal metering, user must write default values.
When I channel is input with the DC signal, this bit can be

Va
set to 1 to short I channel amplifier to obtain the offset

Bit12 SHORTI 0 value of the ADC itself. This function is disabled by default.
For normal metering, user must write default values.

To adjust the internal high-frequency RC clock frequency.

(The ideal value is 3.2768MHz.)
Default: 0b000000, no adjustment is applied.
When the chip operates with full functions in Metering Mode,

it is recommended to hold their default values for the best
Bit[11:7] RCTRIM<4:0> 0 performance.
From “0b00001” to “0b01111”, the RC clock frequency

is decreased by 2% per LSB.
ch
From “0b11111” to “0b10000”, the RC clock frequency
is increased by 2% per LSB.
Bit6 RCX12 0 RC frequency adjustment. The default frequency of the

metering chip is 50Hz. When it is necessary to apply to the
e
60Hz system, users can increase the high frequency RC
clock default frequency of 3.2768MHZ to 1.2 times of the
original.
ot
0: No adjustment 1: X1.2
Bit5 IEHSE 0 This bit must hold the default value for proper operation.
Bit4 IEPDN 0 Enable power-down interrupt output. It is disabled by

default.
ng
0: Disable; 1: Enable.
Bit3 IESUL 0 Enable voltage sign bit output. It is disabled by default.
0: Disable; 1: Enable.
Bit2 BPHPF 0 Bypass high-pass filter. During the default signal

processing, the high-pass filter is enabled. It is necessary
Va
to enable this bit for the DC metering.
0: Enable high-pass filter. Only the voltage / current signal

AC component is involved in RMS / power calculation;
1: Bypass high-pass filter. The voltage / current signal DC

and AC components are involved in RMS / power
calculation.
Bit1 PGAU 0 Configure the voltage (U) channel digital gain.
0: ×1; 1: ×4.
Bit0 Reserved 0

0x0182，R/W，Analog Control Register 0，AnaCtrl0
Bit Default Description
Bit[31:10] Reserved 0 This bit must hold the default value for proper operation.
Adjust the global bias current. 00: -33%; 01: 1; 10: -66%; 11: -
75%.
Bit[9:8] IT<1:0> 0
Under the normal metering condition, this bit must hold the default
value for proper operation.
ch
0x0183，R/W，Analog Control Register 1，AnaCtrl1
Bit Default Description
Bit[31:30]
e
Reserved 0 This bit must hold the default value for proper operation.
Adjust the Miller capacitance of I channel ADC. 00: No adjustment;

ot
01: Increase 33%; 10: Increase 66%; 11: Increase 100%.
Bit[29:28] CSEL<1:0> 0
For normal metering, the recommended configuration is 0b01 for
optimum metering performance and temperature performance.
ng
9.2. Calibration Parameter Registers

When power-on reset (POR), RX reset or global software reset occurs, the calibration parameter
Va
registers will be reset to the default state. If not specifically noted, the default values in the tables of this
section are in format of hexadecimal.
The calibration parameter registers participate in the parameter configuration self-checking.
Table 9-4 Power/RMS/Low-Current Signal Calibration/Phase Calibration Register (R/W)
R/ Default
Address Register Description
W
To set gain 0
calibration of R/
0x00F6 PAC 32-bit 2’s complement
active power for W
A channel

R/ Default
W
To set phase R/ 32-bit 2’s complement 0

calibration of W
Where Bit8 is the sign bit of IA channel phase
active power
compensation value.
1: Delay voltage signal; 0: Delay current

signal.
0x00F7 PHC
When the operating clock (fsmpl) of metering

chip is 3.2768MHz, the phase compensation
ch
resolution is 0.005°/bit, and the maximum
phase error correction range is ±1.4°.
Low-current R/ 32-bit 2’s complement 0

signal W
PADC
0x00F8 calibration of
C
e
active power for
A channel
To set gain R/ 0
ot
calibration of W
0x00F9 QAC 32-bit 2’s complement
reactive power
for A channel
A reactive R/ 0
QADC power low- W
ng
0x00FB 32-bit 2’s complement

C current signal
calibration
A channel R/ 0
0x00FD IAC current RMS W 32-bit 2’s complement
gain calibration
Va
A channel R/ 0
IADC current RMS W
0x00FE 32-bit 2’s complement
C low-current
calibration
Voltage RMS R/ 0
0x00FF UC 32-bit 2’s complement
gain calibration W
A channel ADC 0
IAAD R/
0x0104 bias current 32-bit 2’s complement
CC W
calibration
Voltage ADC 0
UADC R/
0x0106 bias DC 32-bit 2’s complement
C W
calibration

R/ Default
W
Bandpass filter The filter is used to separate the fundamental 0

coefficient signal to allow for more accurate frequency
BPFPA R/
0x0107 measurement and phase measurement. At
RA W
3.2768M clock, the users need to write into
0x806764B6.
Voltage low- 0
R/
0x0108 UDCC current signal 32-bit 2’s complement
W
calibration
ch
9.3. Checksum Register
Table 9-5 Checksum Register (0x0109, CKSUM, R/W)
Register Default R/W Format Description
e Add the value of this register and other related

registers (including metering control registers,
ot
analog control registers, registers for calibration.) to
compute the checksum for configuration verification
32-bit 2’s to ensure the configuration of all the registers are in
0x0109 CKSUM 0 R/W
complement the desired states. If the sum is 0xFFFFFFFF, the
verification passes.
ng
This register should be set to the difference of

0xFFFFFFFF and the sum of the other 23 registers.
9.4. Software Reset Control Register

Va
Table 9-6 Software Reset Control Register (0x01BF, SFTRST, W)
Register Default R/W Format Description
Readable and writable, in the form of 32-bit 2’s

32-bit 2’s complement.
0x01BF SFTRST 0 R/W
complement Write 0x4572BEAF to the register to reset the
system.

9.5. System Status Registers
Table 9-7 System Status Register (0x00CA, SysSts, R)
0x00CA, System Status Register, SysSts
Bit R/W Default Description
Bit[31:12] Reserved R N/A These values are indeterminate and meaningless.
Bit11 USIGN R 0 Voltage sign bit. 1: negative; 0: positive.
Read this bit to detect the sign of the voltage. The flag
ch
cannot be cleared. This bit toggles following the sign of the
voltage.
Bit10 Reserved R N/A These values are indeterminate and meaningless.
Bit9 PHSDONE_R R 0 The latch value of flag bit for whether the phase
measurement ends or not. 0: Not finished; 1: Finished.
Bit8
e
BISTERR R 0 The internal RAM will be self-checked immediately after a
global reset event occurs. The self-checking will be finished
in 1.25 ms. After the self-checking, if this bit is read out as
ot
‘1’, it indicates that the self-checking of the internal RAM
fails. If this bit is read out as ‘0’, it indicates that the
internal RAM is ready to be accessed; but if this bit is read
out as ‘1’ again after another reset event, it indicates that
there is something wrong with RAM.
ng
Bit7 PDN R 0 Power-down interrupt flag bit.
When input voltage on pin VDD33 is lower than Power-

Down detection threshold, this bit is read out as 1. When
the input is higher than Power-Down detection threshold,
this bit is read out as 0.
Va
Bit6 PDN_R R 0 Power-down interrupt flag latch value. This bit is read as 1
when the system is powered down, ie when the level on the
VDD33 pin is below Power-Down detection threshold. When
the power-down event disappears, the flag bit will be read
out as 1.

0x00CA, System Status Register, SysSts
Bit[5:3] RSTSRC R 0
Read the Bit [5: 3] to determine the cause of the reset.
Bit5 Bit4 Bit3 Description
0 0 1 A POR occurs.
0 1 1 A RX reset occurs.
0 1 0 Reserved.
1 0 0 A software reset occurs.
ch
Bit2 CHKERR R 0 Read this bit for the state of configuration verification. The
read value is refreshed every 5ms.
Read this bit to determine whether a parameter

configuration self-checking error occurs.
e Add the content of the registers for calibration, metering

control registers, analog control registers, and 3 reserved
ot
internal registers to the content of the checksum register
to ensure that all the important configurations are in their
desired states. If the sum is 0xFFFFFFFF, the verification
passes, and this bit is read out as 0; otherwise, the
verification fails, and this bit is read out as 1.
ng
Bit1 PHSDONE R 0 The flag bit for whether the phase measurement ends or
not. 0: Not finished; 1: Finished.
Bit0 REF R 0 Set this bit to high when the REF external capacitor starts
to leak. Otherwise this bit is low. The read and write
operations do not change the level of this bit.
Va
Table 9-8 System Status Clr Register (0x019D, SysStsClr, R/W)
Bit[31:10] Reserved R/W N/A These values are indeterminate and meaningless.
Bit9 PHSDONE_CLR R/W 0 The flag bit for whether the phase measurement ends or
not. 0: Not finished; 1: Finished. It can be cleared.

Bit6 PDN_CLR R/W 0 Power-down interrupt flag bit.
When input voltage on pin VDD33 is lower than when the

level on the VDD33 pin is below Power-Down detection
threshold, this bit is read out as 1. When the input is
higher than when the level on the VDD33 pin is below
Power-Down detection threshold, this bit is read out as
1. It can be cleared.
ch
9.6. Metering Control Registers
e
When power-on reset, RX reset or global software reset occurs, all metering control registers will be
reset.
ot
Table 9-9 Data Register (R/W)
Data Default Description

Address Register R/W
format
Instantaneous R 32-bit 2’s 0 When the energy

ng
frequency complement metering clock

0x00CB FREQINST value frequency is
3.2768MHz, it will be
updated every 20ms.
A channel R 32-bit 2’s 0 When the energy

instantaneous complement metering clock
active power frequency is
Va
0x00CC PAINST value 3.2768MHz, the update

time for the register
value is 160ms and the
settling time is 480ms.
instantaneous R 0 When the energy

reactive power metering clock
value frequency is
32-bit 2’s
0x00CD QINST 3.2768MHz, the update
complement
0x00CE IAINST A channel R 32-bit 2’s 0 When the energy

format
instantaneous complement metering clock
current RMS frequency is
3.2768MHz, the update
Instantaneous R 0 When the energy

voltage RMS metering clock
frequency is
32-bit 2’s
0x00CF UINST 3.2768MHz, the update
ch
complement
A channel R 0 When the energy

average active metering clock
e
power value frequency is
32-bit 2’s 3.2768MHz, the update
0x00D0 PAAVG
complement time for the register
ot
settling time is
1280ms.
Average R 0 When the energy

reactive power metering clock
ng
value frequency is
32-bit 2’s 3.2768MHz, the update
0x00D1 QAVG
complement time for the register
settling time is
1280ms.
Va
Average R 0 When the energy

frequency metering clock
32-bit 2’s
0x00D2 FREQAVG value frequency is
complement
3.2768MHz, it will be
updated every 320ms.
A channel R 0 When the energy

average metering clock
current RMS frequency is
32-bit 2’s
0x00D3 IAAVG 3.2768MHz, the update
complement
0x00D4 UAVG Average R 32-bit 2’s 0 When the energy

format
voltage RMS complement metering clock
frequency is
3.2768MHz, the update
Voltage
instantaneous 32-bit 2’s
0x00D9 UDCINST R
DC component complement
value
ch
A channel
instantaneous 32-bit 2’s
0x00DA IADCINST R
DC component complement
value
The previous 0
0x00DC
e
ZXDATREG
sampling value
of
crossing
zero-
R
32-bit 2’s
complement
ot
The sampling 0x80000000
32-bit 2’s
0x00DD ZXDAT value of zero- R
complement
crossing
Voltage phase 32-bit 2’s 1

0x00DE PHDAT R
ng
data complement
The timing 0 This register needs to

data of current be involved in
baud rate measuring the offset of
communication the RC clock, and its
under value is used to
Va
consecutive compensate the

8bit falling frequency. Calculate
edge the internal RC clock
32-bit 2’s frequency according to
0x00E0 T8BAUD R
complement the following equation:
T8BAUD
𝑓𝑟𝑐 = K ′ ×
8
Where:
frc: Internal high
frequency RC clock

format
actual frequency;
T8BAUD: Value of the
register (0x00E0);
K’: Actual baud rate

known by host MCU
Voltage frequency:
ch
𝑓
= 0.00390625 × K ′
T8BAUD
×
FREQAVG
Where:
e f: Actual voltage
frequency
ot
T8BAUD: Value of the
register (0x00E0)
FREQAVG: Frequency
ng
average value per
second register
(0x00D2)
K’: Actual baud rate

Va
known by host MCU

10. Outline Dimensions
θ1
h
h
A3
R1
R
A2
A
L2
B θ2
A1
θ4
L
(L1)
D
ch
b
b1
V924X c1 c
YYWW E
E1
LLL...L Section B-B
LLL...L: Lot Number. The
e b
number of characters of Lot
Number varies between 8 to
11.
ot
YY: Year
WW: Week
ng
Va

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V924X Datasheet

Specifications are subject to change without notice.

© 2021 Vango Technologies, Inc.

This document contains information that is proprietary to Vango Technologies, Inc.

Unauthorized reproduction of this information in whole or in part is strictly prohibited.

2017.07.06 1.0 Initial release

Modify reference voltage to 1.210V.

In order to obtain the best metering performance and temperature

e according to the calculated result. The calculation method, please refer to

Modify figure of Power, Clock and so on.

2018.05.31 3.2 Modifying the formula of Phase Compensation.

Add the power consumption range: +-10%.

Modify 3.3V power supply to 2.9~3.6V

Modify the storage temperature to -55~150°C

Add register AnaCtrl0 (0x182) and AnaCtrl1 (0x183).

2019.01.17 3.4 Remove the threshold for energy.

Add chip mark description.

2020.08.10 3.7 Add PN Junction Temperature.

2020.02.15 3.6 Modify the operating temperature to -40~125°C.

2021.04.15 3.8 Update IEC Standard

Vango Technologies, Inc. -1-

2021.07.15 3.10 Modify revision history

Vango Technologies, Inc. -2-

- Highly metering accurate: - Automatic baud rate adaption UART interface,

Less than 0.1% error for active/reactive

Current input: Shunt resistor or CT

- 2 independent oversampling ∑/∆ ADCs: one V9243: -40~+105°C

Vango Technologies, Inc. -3-

3.3V power supply. This pin must be connected to a ≥ 0.1μF

2 UP Input Positive input for Voltage Channel.

3 IAN Input Negative input for Current Channel A.

4 IAP Input Positive input for Current Channel A.

Input On-chip reference. This pin must be connected to a 1μF capacitor,

Receiver data input.

Hold low logic for at least 64ms to reset the chip.

6 TX Output Transmitter data output

Digital power output. Should be connected to a parallel circuit

8 VSS Ground Analog/digital ground.

Vango Technologies, Inc. -4-

Parameter Min. Typ. Max. Unit Remark

Phase Error Between Channels

PF=0.8 Capacitive ±0.05 Degree

PF=0.5 Inductive ±0.05 Degree

Active Energy Metering

Fundamental frequency deviation

Reactive Energy Metering

Dynamic Range 2000:1 @ 25°C

VRMS Metering Error 1 % Fundamental frequency deviation

VRMS Metering Bandwidth 1.6 kHz

Dynamic Range 5000:1 @ 25°C

IRMS Metering Bandwidth 1.6 kHz

Maximum Signal Level ±200 mV Peak value

Vango Technologies, Inc. -5-

Resolution 23 Bit Sign bit is included.

Bandwidth (-3dB) 1.6 kHz

Reference Error -18 18 mV @ 25˚C

Power Supply Rejection

VDD33 2.9 3.3 3.6 V

POR Detection Threshold 1.45 V Error: ±10%