V98XX Datasheet: Specifications Are Subject To Change Without Notice

V98XX
Datasheet
Specifications are subject to change without notice.
Copyright © 2022 Vango Technologies, Inc.
This document contains information that is proprietary to Vango Technologies, Inc.
Unauthorized reproduction of this information in whole or in part is strictly prohibited.

V98XX Datasheet
Revision History
Date Version Description
2015.06.05 0.1 Initial release
 Modified typical current load in sleeping mode from 10μA to 12μA
 Modified “0b000” to “0b001” in Table 18-10
 Updated Table 4-3 Allocation of Info Area

2015.10.08 0.2
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 Modified “SPC_FNC” to “SPCFNC” in Table 4-2
 Modified function description of “FWC”
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 Modified description of “CFWKEN” in Table 5-5
2015.11.12 0.3  Updated Figure 4-2 Data Memory
 Set the bit of “BGPCHOPN” to ‘0’ in Table 18-10 BandGap Control

Register (CtrlBGP, 0x2862) to improve the temperature measurement
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performance.
 Modified the registers and related content of temperature

2016.01.06 0.4 measurement and temperature calibration.
 Updated Table 17-10 RTC Timing Registers

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 Emphasized the setting of time information in sequence and at one

time.
 Modified “IOP14” to “P14WK”, “PLLCNT” to “PLLCNTST”
2016.10.01 0.5  Added V98XX Resource Comparison
 Updated operating current in sleeping mode to 10μA and maximum

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current in sleeping mode to 14.5μA.
 Updated pin8 to NC
2016.12.02 0.6
 Updated 10.16.3 Measuring Battery Voltage and External Voltage
 Modify the formula of Phase Compensation

2018.05.31 3.0
 Add V9811S/V9811A/V9811B/V9821/V9821S/V9881D
 Modify storage temperature to - 55 ~ 150 C
 Modify the input range of current and voltage channels

2018.09.02 3.1
 Modify the maximum input voltage of analog comparator to LDO33
 Modify the LCD Drive Waveform
Hangzhou Vango Technologies, Inc. 2 / 264

V98XX Datasheet
2021.03.01 3.2  Modify V9811B Outline Dimensions
2021.04.15 3.3  Update IEC Standard·
2021.06.02 3.4  Update document format
2021.11.18 3.5  Delete V9881D
2022.01.22 3.6  Add part marking
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V98XX Datasheet
General Description
V98XX is a single-phase energy metering SoC chip, featuring very low power consumption and high
performance. It integrates Analog Front-End (AFE), energy metering architecture, enhanced 8052 MCU
core, RTC, WDT, Flash memory, RAM, and LCD driver. It can be used for the single-phase multi-functional
energy meter applications.
Features
- Optional power supply 3.3 V or 5 V, wide energy metering over dynamic
input range: 2.5 V to 5.5 V range of 3000:1
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- Reference voltage: 1.185 V (Typical drift  Less than 0.5% error on
10 ppm/°C), interrupt triggered by current/voltage RMS calculation
external capacitor leakage over dynamic range of 1000:1
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- Typical current load in full operation  Various measurements:
mode: 5.5 mA
 Raw waveform and DC
- Typical current load in sleeping mode: component of current and
10 μA voltage signals
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- Supporting anti-tampering energy  Instantaneous/Average and
metering application active/reactive power
- Operating temperature: -40 °C ~ +85 °C  Positive/Negative and

active/reactive energy
- Storage temperature: -55 °C ~ +150 °C
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 Average apparent power

- Energy metering features:
 Instantaneous/Average current
 Four independent oversampling Σ/Δ
and voltage RMS
ADCs
 Line frequency
 One voltage channel
 Temperature with measurement
 Two current channels, supporting
accuracy of ±1°C
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shunt or CT for current sensing

 Battery voltage and external
 One multifunctional channel for
voltage signals
various signal measurements
 Two current inputs for active energy
 High metering accuracy:
metering, or one current input for
 Exceeding requirements of IEC active and reactive energy metering
62053-21:2020/ IEC 62053-
 Programmable energy metering
22:2020 and IEC 62053-
modes:
23:2020
 Accumulating power, current
 Less than 0.1% error on active
RMS, or a constant for energy
energy metering over dynamic
metering
range of 5000:1
 Accumulating energy at a
 Less than 0.1% error on reactive

V98XX Datasheet
configurable frequency  128-KB Flash memory, ISP and IAP
supported, with write protection and
 Calibrating meters via software:
encryption function
 Phase compensation over a
 4-KB extended SRAM memory
range of ±1.4°(min.), resolution
of 0.0055°/lsb (min.).  Up to five UART serial interfaces, one
supporting IR communication
 Gain calibration of RMS and
power, and offset calibration of  Up to two enhanced UART (EUART)
power serial interfaces, ISO/IEC 7816-3
compliant
 Accelerating meter calibration
when low current is applied  One GPSI (General-Purpose Serial
Interface), I2C compliant
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 CF pulse output and interrupt with
configurable pulse width  Up to 54 programmable GPIOs, with
port interrupt
 Zero-crossing interrupt
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 Up to 16 fast IOs
 Speeding current detection to lower
power consumption  Up to 12 hardware timers
 Programmable threshold for no-load  Supporting PWM output

detection
 LCD driver:
- MCU and peripherals:
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 Up to 4×40, 6×38, or 8×36
 High performance 8-bit 8052 MCU segments
core, with programmable operation
 1/3 bias or 1/4 bias ratio
frequency, up to
26 MHz/6.5 mips  Configurable frame frequency
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 One additional comparator  Configurable drive voltage over a

range of 2.7 V ~ 3.3 V,
 Integrated oscillator, only one
resolution 100 mV/lsb
external 32768-Hz crystal is needed
to generate crystal frequency  Various sleep/wakeup methods,
configurable wakeup with reset
 Crystal supervised: Internal RC
oscillator as a replacement when Independent Watch-Dog Timer
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
crystal oscillator stops running (WDT)
 Integrated RTC and temperature  Debugging via JTAG interfaces in

sensor, digital crystal frequency real-time
compensation for calibration over
temperature variation

V98XX Datasheet
V98XX Resource Comparison
Peripherals V9801S V9811S V9811A V9811B V9821 V9821S
Package LQFP100 LQFP64 LQFP64 LQFP64(7*7) TQFP48 TQFP48
Flash
128KB 128KB 64KB 64KB 64KB 64KB
memory
SRAM 4KB 4KB 4KB 4KB 4KB 4KB
Up to 5
UART serial
interfaces,
Up to 4
one Up to 4 UART Up to 4 UART Up to 3 UART Up to 3 UART
UART serial
supporting serial serial serial serial
interfaces,
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IR interfaces, interfaces, interfaces, interfaces,
UART one
communica one one one one
supporting
tion; up to supporting IR supporting IR supporting IR supporting IR
IR
2 EUART, communicati communicati communicati communicati
communicat
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supporting on on on on
ion
ISO/IEC
7816-3
protocol
GPIO 54 43 43 43 32 32
Rapid IO
16 6 6 6 2 1
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port
Up to Up to
Up to Up to Up to Up to
4×40/6×38 4×24/6×22
4×24/6×22/ 4×24/6×22/ 4×17/6×15/ 4×19/6×17/
/8×36 /8×20
8×20 8×20 8×13 8×15
LCD segments, segments,
segments, segments, segments, segments,
1/3 bias or 1/3 bias or
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1/3 bias or 1/3 bias or 1/3 Bias or 1/3 Bias or

1/4 bias 1/4 bias
1/4 bias ratio 1/4 bias ratio 1/4 Bias ratio 1/4 Bias ratio
ratio ratio
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V98XX Datasheet
Table of Contents
Revision History ..................................................................................................................... 2
General Description ................................................................................................................ 4
Features ................................................................................................................................. 4
Table of Contents ................................................................................................................... 7
Figure List ............................................................................................................................ 11
Table List ............................................................................................................................. 14
1. Electrical Characteristics ............................................................................................. 22
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1.1. Absolute Maximum Ratings ........................................................................................ 22
1.2. Energy Metering Specifications ................................................................................... 22
1.3. Analog Specifications ................................................................................................ 23
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1.4. Digital Interface Specifications ................................................................................... 25
1.5. Memory Specifications ............................................................................................... 25
1.6. GPSI Timing Specifications......................................................................................... 26
1.7. Typical Operating Current .......................................................................................... 26
2. Pin Descriptions .......................................................................................................... 28

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3. Functional Block Diagram ............................................................................................ 43
4. 8052 MCU Core Architecture ........................................................................................ 47

4.1. Memory Map ............................................................................................................ 47
4.2. IRAM (Internal RAM) and SFRS (Special Function Registers) .......................................... 47
4.3. Data Memory ........................................................................................................... 51
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4.4. Program Memory ...................................................................................................... 56

4.5. Instruction Set ......................................................................................................... 59
4.5.1. Programmable MOVX Timing ............................................................................. 63
4.5.2. Dual Data Pointers ........................................................................................... 64
5. Reset ........................................................................................................................... 65
5.1. Level 3 .................................................................................................................... 67
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5.2. Level 2 .................................................................................................................... 67

5.2.1. Power Recovery (Power up) ............................................................................... 67
5.2.2. IO Wakeup Event ............................................................................................. 67
5.2.3. RTC Wakeup Event ........................................................................................... 68
5.2.4. CF Pulse Wakeup Event .................................................................................... 68
5.3. Level 1 .................................................................................................................... 68
5.3.1. RSTn Pin Reset ................................................................................................ 69
5.3.2. Power-On Reset (POR) and Brown-Out Reset (BOR) ............................................. 69
5.3.3. WDT Overflow Reset ......................................................................................... 70
5.4. Registers ................................................................................................................. 70
6. Clock ........................................................................................................................... 74
6.1. RC Clock .................................................................................................................. 75
6.2. OSC Clock ............................................................................................................... 75
6.3. PLL Clock ................................................................................................................. 76

V98XX Datasheet
6.4. Switching Source for CLK1 and CLK2 ........................................................................... 77
6.4.1. Normal Operation ............................................................................................ 77
6.4.2. Quick Operation ............................................................................................... 78
6.4.3. Normal Operation vs. Quick Operation ................................................................ 78
6.5. Registers ................................................................................................................. 80
7. Power Management ..................................................................................................... 87

7.1. Power Consumption .................................................................................................. 87
7.1.1. OSC State ....................................................................................................... 88
7.1.2. Working State ................................................................................................. 89
7.1.3. Sleeping State ................................................................................................. 90
7.2. Registers ................................................................................................................. 95
8. Power Supply .............................................................................................................. 98
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8.1. 3.3-V Regulator Circuit (LDO33) ................................................................................. 98
8.2. Digital Power Supply ................................................................................................. 99
8.3. Power Supply Supervisor ........................................................................................... 99
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8.4. Battery Supply ....................................................................................................... 100
9. Comparator ............................................................................................................... 101
10. Energy Metering ........................................................................................................ 103

10.1. Accessing to Registers for Vango Metering Architecture ............................................ 104
10.2. Metering Clock .................................................................................................... 105
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10.3. Reference Voltage ................................................................................................ 105
10.4. Analog Inputs...................................................................................................... 106
10.5. Analog-to-Digital Conversion ................................................................................. 109
10.6. Switch of Current Channels ................................................................................... 110
10.7. Phase Compensation ............................................................................................ 111
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10.8. Digital Input ........................................................................................................ 112

10.9. Current Detection ................................................................................................ 114
10.10. RMS Calculation and Calibration.......................................................................... 114
10.11. Apparent Power Calculation ................................................................................ 116
10.12. Power Calculation and Calibration ....................................................................... 116
10.12.1. Active Power Calculation and Calibration ........................................................ 117
10.12.2. Reactive Power and Calibration ..................................................................... 117
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10.13. Energy Accumulation and CF Pulse Output ........................................................... 118

10.13.1. Energy Accumulation ................................................................................... 118
10.13.2. Energy Pulse Generation and CF Pulse Output ................................................ 119
10.14. No-Load Detection ............................................................................................ 121
10.15. Line Frequency Measurement ............................................................................. 122
10.16. Measuring Various Signals in M Channel .............................................................. 123
10.16.1. Architecture of M Channel ............................................................................ 123
10.16.2. Measuring Temperature ............................................................................... 124
10.16.3. Measuring Battery Voltage and External Voltage ............................................. 125
10.17. Initializing Energy Metering Architecture .............................................................. 126
10.18. Calibration ....................................................................................................... 127
10.18.1. Registers for Meter Calibration...................................................................... 127
10.18.2. Equations for Calibration .............................................................................. 128
10.18.3. Steps for Calibration ................................................................................... 130

V98XX Datasheet
11. Interrupt ................................................................................................................... 132
11.1. Interrupt Sources ................................................................................................ 132
11.2. Interrupt Control Registers ................................................................................... 137
11.3. Interrupt Processing ............................................................................................. 141
11.4. Extended Interrupts ............................................................................................. 142
11.4.1. Interrupt 8 .................................................................................................. 142
11.4.2. Interrupt 9 .................................................................................................. 144
11.4.3. Interrupt 10 ................................................................................................. 146
11.4.4. Interrupt 11 ................................................................................................. 148
12. UART/Timers ............................................................................................................. 150

12.1. Timers/Counters .................................................................................................. 150
12.1.1. TimerA ........................................................................................................ 150
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12.1.2. Timer0/Timer1/Timer2 .................................................................................. 161
12.2. UART.................................................................................................................. 170
12.2.1. UART1......................................................................................................... 170
12.2.2. Extended UART Serial Interfaces .................................................................... 172
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12.3. Enhanced UART Serial Interfaces (EUART) .............................................................. 180
12.3.1. Registers ..................................................................................................... 181
12.3.2. EUART Communication Timing........................................................................ 183
12.3.3. EUART Baud Rate Generation ......................................................................... 184
12.3.4. Data Transmission and Reception.................................................................... 185
12.3.5. EUART for Smart Card Communication ............................................................ 186
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13. General-Purpose Serial Interface (GPSI) .................................................................. 188
13.1. Frame Structure .................................................................................................. 188
13.2. Serial Clock Generation ........................................................................................ 189
13.3. Receive and Transmit Data .................................................................................... 190
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13.4. GPSI Interrupt..................................................................................................... 190

13.5. For I2C Application ............................................................................................... 190
13.6. Registers ............................................................................................................ 192
14. LCD Driver ................................................................................................................. 195

14.1. Pins for LCD Driver .............................................................................................. 195
14.2. LCD Timing ......................................................................................................... 196
14.3. LCD Waveform Voltage ......................................................................................... 196
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14.4. Display RAM ........................................................................................................ 196

14.5. LCD Drive Waveform ............................................................................................ 202
14.6. Registers ............................................................................................................ 206
15. GPIO .......................................................................................................................... 210

15.1. P0...................................................................................................................... 210
15.2. P1...................................................................................................................... 212
15.3. P2...................................................................................................................... 215
15.4. P3...................................................................................................................... 217
15.5. P4...................................................................................................................... 219
15.6. P5...................................................................................................................... 220
15.7. P6...................................................................................................................... 222
15.8. P7...................................................................................................................... 223
15.9. P8...................................................................................................................... 225

V98XX Datasheet
15.10. P9 ................................................................................................................... 226
15.11. P10 ................................................................................................................. 229
16. Watchdog Timer (WDT) ............................................................................................. 233

16.1. Clock for WDT ..................................................................................................... 233
16.2. Clearing WDT ...................................................................................................... 233
16.3. WDT Overflow Reset ............................................................................................ 233
17. Real-Time Clock (RTC) ............................................................................................... 235

17.1. Reading and Writing of RTC Registers ..................................................................... 236
17.1.1. Writing of RTC .............................................................................................. 236
17.1.2. Reading of RTC ............................................................................................. 236
17.2. Timing................................................................................................................ 236
17.3. RTC Interrupts..................................................................................................... 236
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17.3.1. RTC Illegal Data Interrupt .............................................................................. 237
17.3.2. Pulse Output Interrupt per Second .................................................................. 237
17.4. PLL Counter ........................................................................................................ 237
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17.5. Calibrating RTC.................................................................................................... 238
17.5.1. Calibrating Pulse Frequency of PLL Counter ...................................................... 238
17.5.2. Calibrating Divided Pulse Frequency of PLL Counter .......................................... 238
17.5.3. Crystal Frequency-Temperature Curve ............................................................. 239
17.6. Registers ............................................................................................................ 240
18. Registers ................................................................................................................... 244

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18.1. Analog Control Registers ....................................................................................... 244
18.2. Metering Control Registers .................................................................................... 251
18.3. Metering Data Registers ....................................................................................... 256
18.4. Calibration Registers ............................................................................................ 259
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19. Outline Dimensions ................................................................................................... 262

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V98XX Datasheet
Figure List
Figure 2-1 Pin Assignment ........................................................................................................................................ 29
Figure 4-1 IRAM and SFR ........................................................................................................................................... 48
Figure 4-2 Data Memory ............................................................................................................................................. 52
Figure 4-3 Flash Memory and Program Memory Area .................................................................................. 57
Figure 5-1 Reset Unit Diagram ................................................................................................................................ 65
Figure 5-2 RSTn Pin Reset Timing.......................................................................................................................... 69
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Figure 5-3 POR/BOR Timing ..................................................................................................................................... 69
Figure 6-1 Clock System Architecture .................................................................................................................. 75
Figure 6-2 Enabling PLL Circuit and Clock Source Switchover to PLL in Quick Operation ......... 80
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Figure 6-3 Clock Source Switchover to OSC, Disabling PLL Circuit, Disabling CLK1 in Quick
Operation .................................................................................................................................................................... 80
Figure 7-1 Go to Sleeping State (Normal Method, Disable PLL Clock) ................................................ 92
Figure 7-2 Go to Sleeping State (Normal Method, PLL Clock Holds on) ............................................. 93
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Figure 7-3 Go to Sleep (Quick Method) ............................................................................................................... 94
Figure 8-1 Power Supply Architecture ................................................................................................................. 98
Figure 8-2 LDO33 Output and 5V Power Input ............................................................................................... 99

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Figure 8-3 LDO33 output and the Load Current .............................................................................................. 99
Figure 8-4 Relationship between VDCIN Input Signal and States of Flag Bits PWRUP and
PWRDN ....................................................................................................................................................................... 100
Figure 9-1 Comparator Architecture ................................................................................................................... 101
Figure 10-1 Digital Signal Processing in Vango Metering Architecture ............................................ 104
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Figure 10-2 The temperature characteristic curve of reference voltage.......................................... 106
Figure 10-3 CT for Current Analog Input .......................................................................................................... 107
Figure 10-4 Shunt Resistor Network for Current Analog Input ............................................................ 107
Figure 10-5 Analog Input of Voltage .................................................................................................................. 108
Figure 10-6 Exchange of Current Channels ..................................................................................................... 110
Figure 10-7 Phase Compensation Schematics ............................................................................................... 111
Figure 10-8 Digital Inputs ........................................................................................................................................ 112
Figure 10-9 RMS Calculation and Calibration ................................................................................................. 116
Figure 10-12 Energy Accumulation and CF Pulse Output ......................................................................... 118
Figure 10-13 Signal Processing for Line Frequency Measurement ..................................................... 122

V98XX Datasheet
Figure 10-14 M Channel Architecture................................................................................................................. 123
Figure 10-15 Signal Processing in M Channel ................................................................................................ 124
Figure 11-1 Interrupt Logic ..................................................................................................................................... 137
Figure 11-2 Interrupt Processing ......................................................................................................................... 141
Figure 12-1 TimerA Architecture .......................................................................................................................... 151
Figure 12-2 Operation Modes for TimerA ......................................................................................................... 154
Figure 12-3 Configuring Output Frequency in Continuous Mode ......................................................... 155
Figure 12-4 Output on Pin TA1 in Up Mode ..................................................................................................... 159
Figure 12-5 Output on Pin TA1 in Continuous Mode ................................................................................... 160
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Figure 12-6 Output on Pin TA1 in Up/Down Mode ...................................................................................... 161
Figure 12-7 Timer 0/1, Mode 0/1 ........................................................................................................................ 165
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Figure 12-8 Timer 0/1, Mode 2 ............................................................................................................................. 166
Figure 12-9 Timer 0, Mode 3 ................................................................................................................................... 167
Figure 12-10 Timer2, 16-bit Timer/ Counter in Capture Mode ............................................................. 169
Figure 12-11 Timer2, 16-Bit Timer/Counter in Auto-Reload Mode ..................................................... 170

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Figure 12-12 Data Frame in EUART Communication .................................................................................. 181
Figure 12-13 EUART Communication Timing .................................................................................................. 184
Figure 12-14 Data Transmission and Reception ........................................................................................... 186

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Figure 13-1 Frame Structure on SDA ................................................................................................................. 188
Figure 13-2 Receive and Transmit Data ............................................................................................................ 190
Figure 13-3 Read Operation .................................................................................................................................... 191
Figure 13-4 Write Operation ................................................................................................................................... 191
Figure 14-1 LCD Driver Block Diagram .............................................................................................................. 195

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Figure 14-2 LCD Drive Waveform When an LCD Panel of 1/4 Duty and 1/3 Bias is Applied . 203
Figure 15-1 Architecture of P0.0 .......................................................................................................................... 211
Figure 15-2 Architecture of P0.1/P0.2/P0.3 .................................................................................................. 211
Figure 15-3 Architecture of Each Port of Group P1 ..................................................................................... 212

V98XX Datasheet
Figure 15-10 Architecture of Each Port of Group P8 .................................................................................. 225
Figure 15-11 Architecture of Each Port of Group P9 .................................................................................. 227
Figure 15-12 Architecture of Each Port of Group P10 ................................................................................ 230
Figure 16-1 WDT Overflow Reset ......................................................................................................................... 234
Figure 17-1 Architecture of RTC ........................................................................................................................... 235
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Figure 17-2 Schematics of Calibrating Crystal Frequency over Temperature Variation ........... 239
Figure 17-3 Crystal Frequency-Temperature Curve .................................................................................... 240
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V98XX Datasheet
Table List
Table 1-1 Absolut Maximum Ratings .................................................................................................................... 22
Table 1-2 Energy Metering Specifications .......................................................................................................... 22
Table 1-3 Analog Specifications .............................................................................................................................. 23
Table 1-4 Digital Interface Specifications .......................................................................................................... 25
Table 1-5 Memory Specifications ............................................................................................................................ 25
Table 1-6 GPSI Timing Specifications .................................................................................................................. 26
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Table 1-7 Typical Operating Current ..................................................................................................................... 26
Table 2-1 Pin Descriptions (Pin type: “O”=Output, “I”= Input, “P”=Power, “G”=Ground) .... 30
Table 4-1 Select a Register Bank ............................................................................................................................ 47
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Table 4-2 Special Function Registers (SFR) ...................................................................................................... 48
Table 4-3 Allocation of Info Area ........................................................................................................................... 52
Table 4-4 Flash Control Register 1 (FCtrl1, 0x0402).................................................................................... 56

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Table 4-5 Code Bank Register (CBANK, SFR 0xA0) ....................................................................................... 57
Table 4-6 Programming Flash Memory ................................................................................................................ 58
Table 4-7 Instruction Set ........................................................................................................................................... 59
Table 4-8 Programmable MOVX Timing .............................................................................................................. 64

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Table 5-1 Circuits to Be Reset .................................................................................................................................. 65
Table 5-2 System State Register, Systate (SFR 0xA1) ................................................................................ 70
Table 5-3 P0 IO Wakeup Flag Register (IOWKDET, SFR 0xAF) ............................................................... 70
Table 5-4 IO Wakeup Edge Control Register (IOEDG, SFR 0xC7) .......................................................... 71
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Table 5-5 IO Wakeup Control Register (IOWK, SFR 0xC9) ....................................................................... 72
Table 5-6 Set RTC Wake-Up Interval .................................................................................................................... 72
Table 5-7 RTC Seconds Wake-up Interval Configuration Register (SECINT, SFR 0xDF) ............ 72
Table 6-1 Comparing Normal, Quick, and Combination Operation ........................................................ 79
Table 6-2 Clock Switchover Control Register (SysCtrl, SFR 0x80) ........................................................ 80
Table 6-3 Peripheral Control Register 0 (PRCtrl0, 0x2D00) ..................................................................... 82
Table 6-4 Peripheral Control Register 1 (PRCtrl1, 0x2D01) ..................................................................... 83
Table 6-5 Register 1 to Adjust OSC Clock Frequency ................................................................................... 83
Table 6-6 Register 2 to Adjust OSC Clock Frequency ................................................................................... 84
Table 6-7 PLL Clock State Register (PLLLCK, SFR 0xA3) ............................................................................ 84

V98XX Datasheet
Table 6-8 Register 1 to Adjust Clock Frequency of Specific Functional Blocks ............................... 85
Table 6-9 Register 2 to Adjust Clock Frequency of Specific Functional Blocks ............................... 86
Table 6-10 OSC Clock State Register .................................................................................................................... 86
Table 7-1 Factors Affecting Power Consumption of Each Unit ................................................................ 87
Table 7-2 OSC State of System ................................................................................................................................ 88
Table 7-3 Power Consumption When System Working at Full Speed .................................................. 89
Table 7-4 Configuration for Sleeping State ....................................................................................................... 93
Table 7-5 Power Consumption in Sleeping State ........................................................................................... 94
Table 7-6 Register for Clock Control ..................................................................................................................... 95
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Table 7-7 Register to Indicate Power Supply State ...................................................................................... 96
Table 9-1 Registers Related to Comparator CB ............................................................................................. 101
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Table 10-1 Buffer Registers and Data to Be Written or Read ................................................................ 104
Table 10-2 Configuration of CLK2 ........................................................................................................................ 105
Table 10-3 Analog PGA Gain Configuration for Current and Voltage Analog Input .................... 108
Table 10-4 Enable/Disable ADCs .......................................................................................................................... 109

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Table 10-5 Control Bit for Switching Current Signals ................................................................................ 110
Table 10-6 fsmpl Determines Phase Compensation Resolution and Correction Range ................ 112
Table 10-7 Registers for Phase Compensation .............................................................................................. 112

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Table 10-8 Enable/Disable Digital Inputs ........................................................................................................ 112
Table 10-9 DPGA Gain Selection for Digital Signals .................................................................................... 113
Table 10-10 Configuring for RMS Calculation and Calibration ............................................................... 115
Table 10-11 Functions of E2 Path ........................................................................................................................ 116
Table 10-12 Register Configuration for Energy Accumulation .............................................................. 119

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Table 10-13 Configurations for Energy Pulse Generation Rate and CF Pulse Output ................ 120
Table 10-14 Configure for No-Load Detection ............................................................................................... 122
Table 10-15 Registers for Meter Calibration ................................................................................................... 127
Table 11-1 Interrupt Sources ................................................................................................................................. 133
Table 11-2 IE (SFR 0xA8) ........................................................................................................................................ 137
Table 11-3 EIE (SFR 0xE8) ...................................................................................................................................... 138
Table 11-4 EXIF (SFR 0x91) ................................................................................................................................... 139
Table 11-5 EICON (SFR 0xD8) ............................................................................................................................... 139
Table 11-6 IP (SFR 0xB8) ........................................................................................................................................ 140

V98XX Datasheet
Table 11-7 EIP (SFR 0xF8) ...................................................................................................................................... 140
Table 11-8 Interrupt Events to Trigger Interrupt 8 .................................................................................... 142
Table 11-9 Extended Interrupt Flag (Request) Register (ExInt2IFG, 0x2840) ............................ 142
Table 11-10 Extended Interrupt Input Type Register (ExInt2IN, 0x2841) .................................... 143
Table 11-11 Extended Interrupt Output Type Register (ExInt2OUT, 0x2842) ............................. 143
Table 11-12 Extended Interrupt Enable Register (ExInt2IE, 0x2843) ............................................. 143
Table 11-13 Extended Interrupt Pending Register (ExInt2OV, 0x2844) ......................................... 143
Table 11-14 Interrupt Event to Trigger Interrupt 9 ................................................................................... 144
Table 11-15 Extended Interrupt Flag (Request) Register (ExInt3IFG, 0x2848) ......................... 144
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Table 11-17 Extended Interrupt Output Type Register (ExInt3OUT, 0x284A) ............................. 145
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Table 11-18 Extended Interrupt Enable Register (ExInt3IE, 0x284B) ............................................. 145
Table 11-19 Extended Interrupt Pending Register (ExInt3OV, 0x284C) ......................................... 145
Table 11-20 Interrupt Events to Trigger Interrupt 10 ............................................................................... 146
Table 11-21 Extended Interrupt Flag (Request) Register (ExInt4IFG, 0x2850) ......................... 146
ot
Table 11-23 Extended Interrupt Output Type Register (ExInt4OUT, 0x2852) ............................. 147
Table 11-24 Extended Interrupt Enable Register (ExInt4IE, 0x2853) ............................................. 147
ng
Table 11-25 Extended Interrupt Pending Register (ExInt4OV, 0x2854) ......................................... 147
Table 11-26 Interrupt Events to Trigger Interrupt 11 ............................................................................... 148
Table 11-27 Extended Interrupt Flag (Request) Register (ExInt5IFG, 0x28A2) ......................... 148
Table 11-28 Extended Interrupt Input Type Register (ExInt5IN, 0x28A3) ................................... 148
Table 11-29 Extended Interrupt Output Type Register (ExInt5OUT, 0x28A4) ............................. 148
Va
Table 11-30 Extended Interrupt Enable Register (ExInt5IE, 0x28A5) ............................................. 149
Table 11-31 Extended Interrupt Pending Register (ExInt5OV, 0x28A6) ......................................... 149
Table 12-1 TimerA-Related Registers ................................................................................................................ 151
Table 12-2 Timer A Counter/Timer Register (TAR, 0x2902~0x2903) .............................................. 152
Table 12-3 Timer A Control Register (TACTL, 0x2900) ............................................................................. 152
Table 12-4 Timer A Compare/Capture Control Registers (0x2904~0x2909) ................................ 155
Table 12-5 Bit Description of CKCON (SFR 0x8E) ........................................................................................ 161
Table 12-6 Timer0/1 Mode Control Special Function Register (TMOD, SFR 0x89) ..................... 162
Table 12-7 Timer0/1 Control Special Function Register (TCON, SFR 0x88)................................... 163

V98XX Datasheet
Table 12-8 Timer2 Control Special Function Register (T2CON, SFR 0xC8) ..................................... 167
Table 12-9 Timer 2 Mode .......................................................................................................................................... 168
Table 12-10 UART1 Control Special Function Register (SCON1, SFR 0xC0) ................................... 171
Table 12-11 Extended UART Serial Interfaces Registers ......................................................................... 172
Table 12-12 UARTx Control/Status Register (TCON2/TCON3/TCON4/TCON5) ........................... 173
Table 12-13 UARTx Timers Mode Control Register (TMOD2/TMOD3/TMOD4/TMOD5) ........... 174
Table 12-14 UARTx Control Register (SCON2/SCON3/SCON4/SCON5) ........................................... 175
Table 12-15 UARTx Buffer Register (SBUF2/SBUF3/SBUF4/SBUF5) ................................................ 176
Table 12-16 TXD2 Type Register (Txd2FS, 0x28CF) ................................................................................... 176
h
Table 12-17 Carrier Wave Generation Registers .......................................................................................... 177
Table 12-18 UART Modes .......................................................................................................................................... 177
ec
Table 12-19 EUART Baud Rate Generators ...................................................................................................... 181
Table 12-20 EUART Buffer Register (DATAA/DATAB, 0x2A03/0x2B03) .......................................... 181
Table 12-21 EUART Information Register (INFOA/INFOB, 0x2A04/0x2B04) .............................. 181
Table 12-22 EUART Configuration Register (CFGA/CFGB, 0x2A05/0x2B05) ................................ 182

ot
Table 12-23 Pulse Width Modulation Clock Generators ............................................................................ 187
Table 13-1 Description of Different Frame Structures .............................................................................. 189
Table 13-2 Register to Disable or Enable GPSI ............................................................................................. 192

ng
Table 13-3 GPSI Control Register (SICFG, 0x2F01) ................................................................................... 192
Table 13-4 GPSI Timer Divider Registers (SITHH/SITHL, 0x2F03/0x2F02) ................................. 193
Table 13-5 GPSI Data Register (SIDAT, 0x2F04) ......................................................................................... 193
Table 13-6 GPSI Communication Flag Register (SIFLG, 0x2F05) ........................................................ 193
Table 14-1 VLCD to Configuration of [LDO3SEL<2:0>] and [VLCD] .................................................. 196

Va
Table 14-2 RAM Byte Allocation for Segments of LCD Panel of 1/4 Duty ........................................ 197
Table 14-3 RAM Byte Allocation for Segments of LCD Panel of 1/6Duty When 6COMTYPE=0
....................................................................................................................................................................................... 197
Table 14-4 RAM Byte Allocation for Segments of LCD Panel of 1/6 Duty When 6COMTYPE=1
....................................................................................................................................................................................... 198
Table 14-5 RAM Byte Allocation for Segments of LCD Panel of 1/8 Duty ........................................ 200
Table 14-6 LCD Control Register (LCDCtrl, 0x2C1E) ................................................................................... 206
Table 14-7 Enable/Disable CLK3 .......................................................................................................................... 207
Table 14-8 Register to Select Bias Mode .......................................................................................................... 207
Table 14-9 LCD Waveform Voltage Configuration 1.................................................................................... 208

V98XX Datasheet
Table 14-10 LCD Waveform Voltage Configuration 2 ................................................................................. 208
Table 14-11 SEG Control Registers (R/W) ...................................................................................................... 209
Table 15-1 P0 Output Enable Register (P0OE, 0x28A8) ........................................................................... 211
Table 15-2 P0 Input Enable Register (P0IE, 0x28A9) ............................................................................... 211
Table 15-3 P0 Output Data Register (P0OD, 0x28AA) ............................................................................... 211
Table 15-4 P0 Input Data Register (P0ID, 0x28AB) ................................................................................... 211
Table 15-5 P1 Output Enable Register (P1OE, 0x28AC) ........................................................................... 212
Table 15-6 P1 Input Enable Register (P1IE, 0x28AD) ............................................................................... 213
Table 15-7 P1 Output Data Register (P1OD, 0x28AE) ............................................................................... 213
h
Table 15-8 P1 Input Data Register (P1ID, 0x28AF) ................................................................................... 213
Table 15-9 P1.0 Special Function Register (P10FS, 0x28C4, R/W) .................................................... 213
ec
Table 15-10 P1.1 Special Function Register (P11FS, 0x28C5, R/W) ................................................. 213
Table 15-13 P1.4 Special Function Register (P14FS, 0x28C8) .............................................................. 214
ot
Table 15-14 P2 Output Enable Register (P2OE, 0x28B0) ........................................................................ 215
Table 15-15 P2 Input Enable Register (P2IE, 0x28B1) ............................................................................ 215
Table 15-16 P2 Output Data Register (P2OD, 0x28B2) ............................................................................ 216

ng
Table 15-17 P2 Input Data Register (P2ID, 0x28B3) ................................................................................ 216
Table 15-19 P2.1 Special Function Register (P21FS, 0x28CA, R/W) ................................................. 216
Table 15-20 P2.2 Special Function Register (P22FS, 0x28CB, R/W) (V98XX) .............................. 217
Table 15-21 P2.3 Special Function Register (P23FS, 0x28CC, R/W) (V98XX) .............................. 217
Va
Table 15-22 P2.4 Special Function Register (P24FS, 0x28CD, R/W) ................................................. 217
Table 15-23 P2.5 Special Function Register (P25FS, 0x28CE, R/W) ................................................. 217
Table 15-26 P3 Output Data Register (P3OD, 0x28B6) ............................................................................ 218
Table 15-27 P3 Input Data Register (P3ID, 0x28B7) ................................................................................ 218
Table 15-30 P4 Output Data Register (P4OD, 0x28BA) ............................................................................ 220

V98XX Datasheet
Table 15-31 P4 Input Data Register (P4ID, 0x28BB) ................................................................................ 220
Table 15-32 P5 Output Enable Register (P5OE, 0x28BC) ........................................................................ 221
Table 15-33 P5 Input Enable Register (P5IE, 0x28BD) ............................................................................ 221
Table 15-34 P5 Output Data Register (P5OD, 0x28BE) ............................................................................ 221
Table 15-35 P5 Input Data Register (P5ID, 0x28BF) ................................................................................ 221
Table 15-36 P6 Output Enable Register (P6OE, 0x28C0) ......................................................................... 222
Table 15-37 P6 Input Enable Register (P6IE, 0x28C1) ............................................................................. 223
Table 15-38 P6 Output Data Register (P6OD, 0x28C2) ............................................................................ 223
Table 15-39 P6 Input Data Register (P6ID, 0x28C3) ................................................................................ 223
h
Table 15-40 P7 Output Enable Register (P7OE, 0x28D5) ........................................................................ 224
Table 15-41 P7 Input Enable Register (P7IE, 0x28D6) ............................................................................ 224
ec
Table 15-42 P7 Output Data Register (P7OD, 0x28D7) ............................................................................ 224
Table 15-43 P7 Input Data Register (P7ID, 0x28D8) ................................................................................ 225
Table 15-44 P8 Output Enable Register (P8OE, 0x28D9) ........................................................................ 225
Table 15-45 P8 Input Enable Register (P8IE, 0x28DA) ............................................................................ 226

ot
Table 15-46 P8 Output Data Register (P8OD, 0x28DB) ............................................................................ 226
Table 15-47 P8 Input Data Register (P8ID, 0x28DC) ................................................................................ 226
Table 15-48 P9 Output Enable Register (P9OE, SFR 0xA4) .................................................................... 227
ng
Table 15-49 P9 Input Enable Register (P9IE, SFR 0xA5) ........................................................................ 227
Table 15-50 P9 Output Data Register (P9OD, SFR 0xA6) ........................................................................ 228
Table 15-51 P9 Input Data Register (P9ID, SFR 0xA7) ............................................................................ 228
Table 15-52 P9 Special Function Register (P9FS, SFR 0xAD) ................................................................ 228
Table 15-53 P10 Output Enable Register (P10OE, SFR 0xA9) ............................................................... 230
Va
Table 15-54 P10 Input Enable Register (P10IE, SFR 0xAA) ................................................................... 230
Table 15-55 P10 Output Data Register (P10OD, SFR 0xAB)................................................................... 230
Table 15-56 P10 Input Data Register (P10ID, SFR 0xAC) ....................................................................... 230
Table 15-57 Configuration for EUART Communication .............................................................................. 231
Table 16-1 Enable/Disable CLK4 .......................................................................................................................... 233
Table 17-1 RTC Password Enable Register (RTCPEN, SFR 0x90) ......................................................... 240
Table 17-2 RTC Password Register (RTCPWD, SFR 0x97) ....................................................................... 240
Table 17-3 RTC Wakeup Interval Register (INTRTC, SFR 0x96) .......................................................... 240
Table 17-4 RTC Seconds Wake-up Interval Configuration Register (SECINT, SFR 0xDF) ....... 241

V98XX Datasheet
Table 17-5 Flag Bit of RTC Wakeup Event ........................................................................................................ 241
Table 17-6 RTC Calibration Registers (RTCCH/RTCCL, SFR 0x94/0x95) ......................................... 241
Table 17-7 RTC Data Reading Enable Register (RDRTC, SFR 0xDA) ................................................... 241
Table 17-8 PLL Clock Divider Registers (DIVTHH/DIVTHM/DIVTHL, SFR 0xDB/0xDC/0xDD)

....................................................................................................................................................................................... 242
Table 17-9 PLL Counter State Register (PLLCNTST, SFR 0xDE) ............................................................ 242
Table 17-10 RTC Timing Registers ....................................................................................................................... 242
Table 18-1 ADC Control Register 0 (CtrlADC0, 0x2858) ........................................................................... 244
Table 18-2 ADC Control Register 1 (CtrlADC1, 0x2859) ........................................................................... 244
h
Table 18-3 ADC Control Register 2 (CtrlADC2, 0x285A) ........................................................................... 245
Table 18-4 ADC Control Register 3 (CtrlADC3, 0x285B) ........................................................................... 245
ec
Table 18-5 Battery Discharge Control Register (CtrlBAT, 0x285C) .................................................... 246
Table 18-6 ADC Control Register 4 (CtrlADC4, 0x285D) .......................................................................... 246
Table 18-7 LCD Driver Voltage Control Register (CtrlLCDV, 0x285E) ................................................ 246
Table 18-8 Crystal Control Register 1 (CtrlCry1, 0x2860)....................................................................... 247

ot
Table 18-9 Crystal Control Register 2 (CtrlCry2, 0x2861)....................................................................... 247
Table 18-10 BandGap Control Register (CtrlBGP, 0x2862) ..................................................................... 247
Table 18-11 ADC Control Register 5 (CtrlADC5, 0x2863) ........................................................................ 248
Table 18-12 ADC Control Register 6 (CtrlADC6, 0x2864) ........................................................................ 249

ng
Table 18-13 Channel M Control Register (CtrlM, 0x2865) ....................................................................... 249
Table 18-14 LDO Control Register (CtrlLDO, 0x2866) ............................................................................... 250
Table 18-15 Clock Control Register (CtrlCLK, 0x2867) ............................................................................. 250
Table 18-16 PLL Control Register (CtrlPLL, 0x2868) ................................................................................. 250

Va
Table 18-17 Analog Circuits State Register (ANState, 0x286B) ........................................................... 251
Table 18-18 PM Control Register 1 (PMCtrl1, 0x2878) ............................................................................. 251
Table 18-19 PM Control Register 2 (PMCtrl2, 0x2879) ............................................................................. 252
Table 18-20 PM Control Register 3 (PMCtrl3, 0x287A) ............................................................................. 252
Table 18-21 Phase Compensation Control Register 1 (PHCCtrl1, 0x287B) ..................................... 253
Table 18-22 Phase Compensation Control Register 2 (PHCCtrl2, 0x287C) ..................................... 254
Table 18-23 PM Control Register 4 (PMCtrl4, 0x287D) ............................................................................. 254
Table 18-24 CF Pulse Output Control Register (CFCtrl, 0x287E) ......................................................... 254
Table 18-25 No-Load Detection Indication Register (CRPST, 0x287F) ............................................. 255
Table 18-26 Current Detection Control Register (IDET, 0x2886) ........................................................ 256

V98XX Datasheet
Table 18-27 Signal Waveform Registers (R/W) ........................................................................................... 257
Table 18-28 Power and RMS Registers (R/W) .............................................................................................. 257
Table 18-29 Energy Accumulators and Energy Pulse Counters (R/W) ............................................. 258
Table 18-30 Line Frequency Register (DATAFREQ, 0x10FD).................................................................. 259
Table 18-31 Data Registers for Channel M ...................................................................................................... 259
Table 18-32 Registers for Gain Calibration (R/W) ...................................................................................... 259
Table 18-33 Registers for Power Offset Calibration (R/W) .................................................................... 260
Table 18-34 Band-pass Filter Coefficient Register (0x10EF, R/W) ..................................................... 260
Table 18-35 Energy Threshold Registers and Constant Power Register (R/W) ........................... 260
h
Table 18-36 Threshold Register for Current Detection (R/W) .............................................................. 261
ec
ot
ng
Va

V98XX Datasheet
1.Electrical Characteristics
1.1. Absolute Maximum Ratings

Operating circumstance exceeding “Absolute Maximum Ratings” may cause the permanent damage
to the device.
Table 1-1 Absolut Maximum Ratings
Parameter Min. Max. Unit Description
Analog Power Supply -0.3 +8.0 V Relative to ground.
h
Analog Current Input -0.3 +5.0 V Relative to ground.
Analog Voltage Input -0.3 +5.0 V Relative to ground.
ec
Operating Temperature -40 +85 ˚C
Storage Temperature -40 +125 ˚C
Junction Temperature - 150 °C
Lead Temperature (Soldering, 10 s) - 300 °C

ot
1.2. Energy Metering Specifications
All typical specifications are at TA = 25 °C, VDD5 = 5.0 V ±10%, and fMTCLK = 3.2768 MHz, unless
ng
otherwise noted.
Table 1-2 Energy Metering Specifications
Parameter Typ. Unit Description
Phase Error Between Channels

Va
PF=0.8 Capacitive ±0.05 Degree 37°phase lead in current
PF=0.5 Inductive ±0.05 Degree 60°phase lag in current
Active Energy Metering
Error 0.1 % Dynamic range of 5000:1@25°C
Bandwidth 1.6 kHz
Reactive Energy Metering
Bandwidth 1.6 kHz
Apparent Power Metering

V98XX Datasheet
Parameter Typ. Unit Description
Voltage/Current RMS Metering
Bandwidth 1.6 kHz
CF Pulse Output
Maximum Output Frequency 6.4 kHz
Duty Cycle 50% When active high pulse width < 80 ms.
h
Active High Pulse Width 80 ms Configurable
Frequency Measurement Resolution 0.05 Hz/lsb Measurement range: 35 Hz ~ 75 Hz
ec
Temperature Measurement Error ±1 °C Measurement range: -40 °C ~ +85 °C
1.3. Analog Specifications

All maximum and minimum specifications apply over the entire recommended operation range
ot
(T = -40 °C ~ +85 °C, VDD5 = 3.3 V or 5.0 V), unless otherwise noted. All typical specifications are at
TA = 25 °C and VDD5 = 5.0 V ±10%, unless otherwise noted.
Table 1-3 Analog Specifications
Parameter Min. Typ. Max. Unit Description

ng
3.6 5.0 5.5 V 5 V powered

Analog Power Supply (VDD5)
2.5 3.3 3.6 V 3.3 V powered
LDO33 Output
VVDD5 ≥ 4 V; IL33 = 16
Voltage 2.8 3.3 3.5 V
Va
mA Programmable
Current dissipated on
IOs should not be over
Load Current (IL33) 30 mA
the maximum driving
capacity of LDO33.
Digital Power Supply
Voltage 1.3 1.8 2.0 V Programmable
Load Current (ILD) 35 mA
POR/BOR Detection Threshold

1.4 V Error: ±10%
(“DVCC”)
Power-Down Detection Threshold (“VDCIN”)

V98XX Datasheet
Maximum Signal Level 0 VDD V
Input Impedance (DC) 1.5 MΏ
Detection Threshold for “PWRDN” 1.0 V
Detection Threshold for “PWRUP” 1.1 V
Analog Inputs
Maximum Signal Levels -200 +200 mV Peak value
ADC Performance
h
DC Offset 15 mV
Effective Bits 20 BIT Sign bits are excluded.
ec
Bandwidth (-3dB) 1.6 kHz
ADC Operating Current
Voltage Channel 307 μA
Current Channel 485 μA fADC = 819.2 kHz

ot
Measurement Channel 238 μA
On-Chip Crystal Oscillator
Crystal Frequency 32.768 kHz
On-Chip Reference (BandGap)

ng
Reference Error -18 18 mV
Power Supply Rejection Ratio 80 dB
Temperature Coefficient 10 30 ppm/°C
Output Voltage 1.185 V

Va
Analog Comparator CB
VDD5
Input Voltage 0 V
-0.8
Load Current 186.2 nA Bias current = 20 nA
Delay Time 2.7 3.0 4.0 μs Square wave = 50 kHz
Load Current 664.6 nA Bias current = 200 nA
Delay Time 0.20 0.37 0.60 μs Square wave = 50 kHz

V98XX Datasheet
1.4. Digital Interface Specifications

(T = -40 °C ~ +85 °C, VDD5 = 3.3 V or 5.0 V), unless otherwise noted.
Table 1-4 Digital Interface Specifications
Digital IO, Output
Output High Voltage, VOH 2.4 V

12-mA current cannot damage the chip
ISOURCE 10 12 mA in a short period of time; Long duration
h
Output Low Voltage, VOL 0.4 V of 10-mA or above current may cause
damage to the chip.
ISINK 10 12 mA
ec
Digital IO, Input
Input High Voltage, VINH 2.0 V
Input Low Voltage, VINL 0.8 V

ot
1.5. Memory Specifications
(T = -40 °C ~ +85 °C, VDD5 = 3.3 V or 5.0 V), unless otherwise noted. All typical specifications are at
TA = 25 °C, VDD5 = 5.0 V ±10% or fMCU = 13.1072 MHz, unless otherwise noted.
ng
Table 1-5 Memory Specifications
Flash Memory
Read Pulse Width 76 ns

Va
Endurance 20000 cycle -40 °C ~ +85 °C
Data Retention 100 year 25°C
Data Retention 10 year 85°C
Write Time, per byte 40 μs
Page Erase Time (512 bytes) 40 ms
Mass Erase Time 40 ms
RAM
DVCC output
Data Retention Voltage 1.62 V
voltage

V98XX Datasheet
1.6. GPSI Timing Specifications

(T = -40 °C ~ +85 °C, VDD5 = 3.3 V or 5.0 V ±10%), unless otherwise noted.
Table 1-6 GPSI Timing Specifications
Parameter Min. Max. Unit
fSCL SCL frequency 400 kHz
tHD;STA START condition hold time (Then, the first SCL pulse is generated.) 1.875 μs
h
tLOW SCL low pulse width 1.25 μs
tHIGH SCL high pulse width 1.25 μs
ec
tSU;STA RESTART condition setup time 0.625 μs
tHD;DAT Data hold time 0.625 μs
tSU;DAT Data setup time 0.625 μs

ot
tr Rising time of both SDA and SCL 50 ns
tf Falling time of both SDA and SCL 50 ns
tSU;STO STOP condition setup time 0.625 μs

ng
tBUF Bus free time between STOP condition and START condition N/A
tSP Pulse width of spike suppressed N/A

Va
SDA
tf tLOW tr tSU;DAT tf tHD;STA tSP tr tBUF
SCL
tHD;STA tHD;DAT tHIGH tSU:STA tSU;STO
S Sr P S
1.7. Typical Operating Current

Table 1-7 Typical Operating Current

V98XX Datasheet
Mode Typ. Unit Description
Full- fMCU = 13.1072 MHz, fMTCLK = 3276.8 kHz, fADC = 819.2 kHz, 4 ADC channels
5.5 mA
operation are enabled.
Digital power supply is 1.8V; crystal oscillation circuit, RTC, system

monitoring circuit, voltage monitoring circuit, and reset circuit keep
Sleeping 10 μA
working. RAM memory holds the data. Maximum current in sleeping mode:
14.5μA.
h
ec
ot
ng
Va

V98XX Datasheet
2.Pin Descriptions
P5.1/SEG9/COM7
P5.0/SEG8/COM6
P7.2/SEG26
P7.1/SEG25
P6.7/SEG23
P7.0/SEG24
P6.6/SEG22
P6.5/SEG21
P6.4/SEG20
P6.3/SEG19
P6.2/SEG18
P6.0/SEG16
P5.7/SEG15
P5.6/SEG14
P5.4/SEG12
P5.3/SEG11
P5.2/SEG10
P6.1/SEG17
P5.5/SEG13
P4.7/SEG7
P4.6/SEG6
P4.5/SEG5
P4.4/SEG4
P4.3/SEG3
P4.2/SEG2
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P7.3/SEG27 76 50 P4.1/SEG1/COM5
P7.4/SEG28 77 49 P4.0/SEG0/COM4
P7.5/SEG29 78 48 P3.3/COM3
P7.6/SEG30 79 47 P3.2/COM2
P7.7/SEG31 80 46 P3.1/COM1
P8.0/SEG32 81 45 P3.0/COM0
P8.1/SEG33 82 44 CF1
P8.2/SEG34 83 43 P9.3/PLLDIV
h
P9.0/TA0/SEG35 84 42 P9.4/SP
SEG36 85 41 P9.5/CF2
SEG37/M0 86 40 P9.6/CF1
SEG38/M1/CMPB 87 39 P9.7/PWMCLK
SEG39/M2/CMPB 88 38 P10.0/E1RTX
P9.1/TA1/SDSP/SDA 89 37 P10.1/E2TX
ec
V9801S
P9.2/TA2/SCL 90 36 P10.2/E2RX
P2.5/TXD2 91 35 P10.3
P2.4/RXD2 92 34 P1.0/SP
P2.3/TXD3 93 33 P1.1/RXD1/T1/INT2
P2.2/RXD3 94 32 P1.2/TXD1/T2EX/INT3
P2.1/T0/TXD4 95 31 P1.3/RXD5/CFx/INT0/SP/PLLDIV/WAKEUP2
P2.0/T2/RXD4/OSC 96 30 P1.4/TXD5/INT1/PLLDIV/WAKEUP1
P10.4 97 29 P0.3/TCK/WAKEUP4
P10.5 98 28 P0.2/TMS/WAKEUP3
RSTN 99 27 P0.1/TDI
ot
CTI 100 26 P0.0/TDO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VSS
VSS
VSS
CTO
MODE1
MODE0
NC
VDCIN
BAT
NC
LDO33
UM
P10.7
NC
VDD5
REF
IAP
IAN
IBN
IBP
P10.6
NC
DVCC
UP
UN
P5.0/SEG8/COM6
P5.1/SEG9/COM7
P4.1/SEG1/COM5
ng P6.7/SEG23
P6.6/SEG22
P6.5/SEG21
P6.4/SEG20
P6.3/SEG19
P6.2/SEG18
P5.7/SEG15
P5.6/SEG14
P5.5/SEG13
P5.4/SEG12
P5.3/SEG11
P5.2/SEG10
VSS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P7.6/SEG30 49 32 P4.0/SEG0/COM4
P7.7/SEG31 50 31 P3.3/COM3
Va
P8.0/SEG32 51 30 P3.2/COM2
P8.1/SEG33 52 29 P3.1/COM1
P8.2/SEG34 53 28 P3.0/COM0
P9.0/TA0/SEG35 54 27 P9.3/PLLDIV
SEG38/M1/CMPB 55 26 P9.5/CF2
SEG39/M2/CMPB 56 25 P9.6/CF1
P9.1/TA1/SDSP/SDA
P9.2/TA2/SCL
57
58
V9811S/ 24
23
P1.1/RXD1/T1/INT2
P1.2/TXD1/T2EX/INT3
P2.5/TXD2
P2.4/RXD2
59
60
V9811A/ 22
21
P1.3/RXD5/INT0/CFx/SP/PLLDIV/WAKEUP2
P1.4/TXD5/INT1/PLLDIV/WAKEUP1
P2.1/T0/TXD4 61 V9811B 20
19
P0.3/TCK/WAKEUP4
P0.2/TMS/WAKEUP3
P2.0/T2/RXD4/OSC 62
RSTN 63 18 P0.1/TDI
CTI 64 17 P0.0/TDO
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
BAT
VDD5
LDO33
VSS
UP
IAP
UN
IAN
IBN
MODE1
CTO
VDCIN
NC
DVCC
REF
IBP

V98XX Datasheet
P5.1/SEG9/COM7
P5.0/SEG8/COM6
P4.1/SEG1/COM5
P7.2/SEG26
P7.1/SEG25
P7.0/SEG24
P6.3/SEG19
P6.2/SEG18
P6.1/SEG17
P6.0/SEG16
LDO33
DVCC
36
35
34
33
32
31
30
29
28
27
26
25
P7.3/SEG27 37 24 P4.0/SEG0/COM4
P7.4/SEG28 38 23 P3.3/COM3
P7.5/SEG29 39 22 P3.2/COM2
P8.2/SEG34 40 21 P3.1/COM1
P9.0/TA0/SEG35 41 20 P3.0/COM0
M2/SEG39 42 19 P9.6/CF
P2.5/TXD2 43 18 P1.3/RXD5/INT0/CFx/SPX/WAKEUP2
P2.4/RXD2 17 P1.4/TXD5/INT1/SPI/WAKEUP1
V9821
44
h
P2.1/TXD4/T0 45 16 P0.3/WAKEUP4/TCK
P2.0/RXD4/T2/OSC 46 15 P0.2/WAKEUP3/TMS
RSTn 47 14 P0.1/TDI
CTI 48 13 P0.0/TDO
ec
10
11
12
1
9
VSS
VDD5
UP
MODE1
VDCIN
CTO
IBN
IAN
UN
IBP
IAP
REF
P5.1/SEG9/COM7
P5.0/SEG8/COM6
P4.1/SEG1/COM5
P7.2/SEG26
P7.1/SEG25
P7.0/SEG24
P5.7/SEG15
P5.6/SEG14
P5.5/SEG13
P5.4/SEG12
P5.3/SEG11
P5.2/SEG10
ot
36
35
34
33
32
31
30
29
28
27
26
25
P7.3/SEG27 37 24 P4.0/SEG0/COM4
P7.4/SEG28 38 23 P3.3/COM3
P7.5/SEG29 39 22 P3.2/COM2
ng
P8.2/SEG34 40 21 P3.1/COM1
P9.0/TA0/SEG35 41 20 P3.0/COM0
M2/SEG39 42 19 P1.3/CFx/RXD5/INT0/SPx/WAKEUP2
P2.5/TXD2 43 18 P1.4/SP1/TDX5/INT1/WAKEUP1
P2.4/RXD2/WK 17 P0.3/TCK/WAKEUP4
V9821S
44
P2.1/TXD4/T0 45 16 P0.2/TMS/WAKEUP3
P2.0/RXD4/T2 46 15 P0.1/TDI
Va
RSTn 47 14 P0.0/TDO
CTI 48 13 MODE1
10
11
12
1
9
LDO33
REF
VDD5
AVSS
DVCC
IBN
UP
VDCIN
CTO
IAN
IBP
IAP
Figure 2-1 Pin Assignment

V98XX Datasheet
Table 2-1 Pin Descriptions (Pin type: “O”=Output, “I”= Input, “P”=Power, “G”=Ground)
V9801S
V9811B
V9811A/
V9811S/
V9821
V9821S
Mnemonic Type Description
1 1 1 1 CTO O 32768-Hz crystal output
Connect a crystal around this pin

and pin “CTI” to generate the
“OSC” clock.
2~3 NC - Not connected
4 AVSS G Analog ground
h
5 2 2 2 VDCIN I Power supply supervisor input
When the input voltage on this pin
ec
is higher than 1.1 V, the chip will be
powered by 5-V main power. When
the input voltage on this pin is
lower than 1.0 V, the chip will be
powered by batteries, or the power
supply will be switched from 5-V
ot
main power to batteries.
6 3 BAT I Analog input for battery voltage

measurement
The input voltage signal into this

pin to be measured must be over
ng
the range of -200 mV ~ 3.8 V.
When no battery is used, it is

mandatory to float this pin, but not
connect it to ground.
7~8 4 NC - Not connected

Va
9 5 28 DVCC P Digital power output
The internal power-on reset circuit

supervises the output voltage on
this pin: When the voltage is lower
than 1.4 V, a power-on reset will
occur.
Connect a ≥ 4.7-μF capacitor in

parallel with a 0.1-μF capacitor
around this pin, and then connect it
to the digital ground.

V98XX Datasheet
V9801S
V9811B
V9811A/
V9811S/
V9821
V9821S
10 6 29 4 LDO33 P Regulated 3.3-V analog voltage

output
Connect a ≥ 4.7-μF capacitor in

parallel with a 0.1-μF capacitor
around this pin, and then connect it
to the analog ground.
When the chip is 3.3 V powered, it

is recommended to directly
h
externally connect this pin to the
pin “VDD5”.
11 7 3 5 VDD5 P Power supply
ec
Connect a 10-μF capacitor to this
pin, and then connect it to the
ground.
When the chip is 3.3 V powered, it

ot
is recommended to directly
externally connect this pin to the
pin “LDO33”.
12 8 4 6 AVSS G Analog ground
13 9 5 7 REF I/O On-chip reference

ng
Connect a 1-μF capacitor to this

pin, and then connect it to analog
ground.
14 UM I Analog input for various signal

measurements in Measurement
Va
(M) Channel
The input voltage signal into this

pin to be measured must be over
the range of -200 mV ~ 3.4 V.
15 10 6 8 UP I Positive input for Voltage Channel
16 11 7 UN I Negative input for Voltage Channel
17 AVSS G Analog ground
18 12 8 9 IAP I Positive input for Current Channel

IA
19 13 9 10 IAN I Negative input for Current Channel

IA

V98XX Datasheet
V9801S
V9811B
V9811A/
V9811S/
V9821
V9821S
20 14 10 11 IBN I Negative input for Current Channel

IB
21 15 11 12 IBP I Positive input for Current Channel

IB
22 16 12 13 MODE1 I “Logic 0” is input to force the

system into the debugging mode.
“Logic 1” is input to force the
h
system into the metering mode.
23 MODE0 I Grounded/Float
ec
24 P10.7 I/O General-purpose input/output port
(Fast IO)
25 P10.6 I/O General-purpose input/output port

(Fast IO)
26 17 13 14 P0.0 I/O This pin is used as a general-

ot
purpose input/output port by
TDO
default. But when “logic 0” is input
to the pin “MODE1”, this pin will
be used as a JTAG port for the test
data output (“TDO”).
ng

TDI
default. But when “logic 0” is input
to the pin “MODE1”, this pin will
be used as a JTAG port for the test
data input (“TDI”).
Va

WAKEUP3
default.
TMS
When the bit “IOP0” (“bit1” of
“IOWK”, SFR 0xC9) is set to ‘1’,
this pin will be used for the IO
wakeup input, active on either
transition (Configurable).
When “logic 0” is input to the pin

“MODE1”, this pin will be used as
a JTAG port for the test mode
selection (“TMS”).

V98XX Datasheet
V9801S
V9811B
V9811A/
V9811S/
V9821
V9821S

purpose input/output port.
WAKEUP4
When the bit “IOP0” (“bit1” of
TCK
“IOWK”, SFR 0xC9) is set to ‘1’,
this pin will be used for the IO
wakeup input, active on either
transition (configurable).
When “logic 0” is input to the pin
h
“MODE1”, this pin will be used as
a JTAG port for the test clock input
(“TCK”).
ec
30 21 17 18 P1.4 I/O The function of this pin can be
configured by the register
TXD5
“P14FS” (0x28C8):
INT1
- General-purpose input/output
PLLDIV port;
ot
WAKEUP1 - Transmitter data output of
“UART5”;
- IO interrupt input 1, active on

high-to-low transition;
ng
- Pulse output proportional to

the divided PLL clock
frequency, which can be
configured to output pulses of
1s width from the PLL counter.
Besides, this pin can be used to

Va
wake up the system from the

sleeping state, active on either

V98XX Datasheet
V9801S
V9811B
V9811A/
V9811S/
V9821
V9821S

RXD5
“P13FS” (0x28C7):
INT0
CFx port;
SP - Receiver data input of

“UART5”;
PLLDIV
h
- IO interrupt input 0, active on
WAKEUP2
high-to-low transition;
- Configurable CF pulse output;
ec
- Pulse per second (PPS) output
from RTC. On calibrating RTC,
every 30 seconds, from the 1st
to 29th second, an un-
calibrated pulse is output
ot
every second, and in the 30th
second, a calibrated pulse is
output which averages the
cycle of each pulse in the 30
seconds to be 1s width;
ng

Besides, this pin can be used to

Va
wake up the system from the

sleeping state, active on either

V98XX Datasheet
V9801S
V9811B
V9811A/
V9811S/
V9821
V9821S
32 23 P1.2 I/O The function of this pin can be

TXD1
“P12FS” (0x28C6):
T2EX
INT3 port;
- Transmitter data output of

“UART1”;
h
- Timer2 capture or reload
trigger input;
IO interrupt input 3, active on
ec
high-to-low transition.

RXD1
“P11FS” (0x28C5):
T1
ot
INT2 port;
- Receiver data input of

“UART1”;
- Timer1 external input;

ng
IO interrupt input 2, active on

high-to-low transition.
34 P1.0 I/O The function of this pin can be

SP
“P10FS” (0x28C4):
Va
port;

from RTC. On calibrating RTC,
every 30 seconds, from the 1st
to 29th second, an un-
calibrated pulse is output every
second, and in the 30th second,
a calibrated pulse is output
which averages the cycle of
each pulse in the 30 seconds to
be 1s width.

V98XX Datasheet
V9801S
V9811B
V9811A/
V9811S/
V9821
V9821S
35 P10.3 I/O - General-purpose input/output

port (Fast IO).
36 P10.2 I/O - This pin is used as a general-

purpose input/output port
E2RX
(Fast IO) by default. When the
bit “ENABLE” (“bit0” of
“CFGB”, 0x2B05) is set to ‘1’,
this pin is used for the
h
receiver data input of
“EUART2”.
37 P10.1 I/O This pin is used as a general-
ec
purpose input/output port (Fast IO)
E2TX
by default. When the bit “ENABLE”
(“bit0” of “CFGB”, 0x2B05) is set
to ‘1’, this pin is used for the
transmitter data output of
“EUART2”.
ot
38 P10.0 I/O This pin is used as a general-
purpose input/output port (Fast IO)
E1RTX
by default. When the bit “ENABLE”
(“bit0” of “CFGA”, 0x2A05) is set
to ‘1’, this pin is used for the data
ng
input and output of “EUART1”.

configured by the register “P9FS”
PWMCLK
(SFR 0xAD):
Va
port (Fast IO);
PWM pulse output.

When the enhanced UART (EUART)
ports are used for smart card
communication, this pulse output is
used as the clock input into the
card for communication.

V98XX Datasheet
V9801S
V9811B
V9811A/
V9811S/
V9821
V9821S
40 25 19 P9.6 I/O The function of this pin can be

CF1
(SFR 0xAD):
port (Fast IO);
CF pulse output of E1 path.
h
CF2
(SFR 0xAD):
ec
port (Fast IO);
- CF pulse output of E2 path.

SP
(SFR 0xAD):
ot
port (Fast IO);

from RTC
ng
On calibrating RTC, every 30

seconds, from the 1st to 29th
second, an un-calibrated pulse
is output every second, and in
the 30th second, a calibrated
pulse is output which averages
the cycle of each pulse in the
Va
30 seconds to be 1 second.

PLLDIV
(SFR 0xAD):
port (Fast IO);

44 CF1 O - CF pulse of E1 path

V98XX Datasheet
V9801S
V9811B
V9811A/
V9811S/
V9821
V9821S
45~48 28~31 20~23 20~23 P3.0~P3.3 I/O - These pins are used as
general-purpose input/output
COM0~COM3
ports by default. And they also
can be used as backplanes of
the LCD driver.
49 32 24 24 P4.0 I/O This pin is used as general-purpose

input/output port by default, as
SEG0
SEG output for the LCD driver when
h
COM4 bits “LCDTYPE” (“bit[5:4]” of
“LCDCtrl”, 0x2C1E) are cleared,
or as backplanes of the LCD driver
when bits “LCDTYPE” are set to
ec
‘1’, ‘2’, or ‘3’.
50 33 25 25 P4.1 I/O This pin is used as general-purpose

input/output port by default, as
SEG1
SEG output for the LCD driver when
COM5 bits “LCDTYPE” (“bit[5:4]” of
ot
“LCDCtrl”, 0x2C1E) are cleared,
‘1’, ‘2’, or ‘3’.
51~56 P4.2~P4.7 I/O These pins are used as general-

ng
purpose input/output ports by

SEG2~SEG7
default; or SEG output for the LCD
driver when the corresponding bits
in SEG control registers are set to
1s.
57 34 26 26 P5.0 I/O This pin is used as general-

Va

SEG8
default, as SEG output for the LCD
COM6 driver when bits “LCDTYPE”
(“bit[5:4]” of “LCDCtrl”,
0x2C1E) are cleared or set to ‘1’,
‘2’ or ‘3’.

V98XX Datasheet
V9801S
V9811B
V9811A/
V9811S/
V9821
V9821S
58 35 27 27 P5.1 This pin is used as general-

SEG9
default, as SEG output for the LCD
COM7 driver when bits “LCDTYPE”
(“bit[5:4]” of “LCDCtrl”,
0x2C1E) are cleared or set to ‘1’,
‘2’ or ‘3’.
h
59~83 36~53 30-40 28~40 P5.2~P8.2 I/O These pins are used as general-
purpose input/output ports by
SEG10~SEG34
default; or SEG output for the LCD
ec
driver when the corresponding bits
in SEG control registers are set to
1s.

ot
TA0
(SFR 0xAD):
SEG35
port (Fast IO);
- TimerA port 0, to input/output

ng
the signals for TimerA

Compare/Capture Module 0.
Besides, this pin can be used for

SEG output for the LCD driver
85 SEG36 O This pin is used for SEG output for

the LCD driver.
Va

V98XX Datasheet
V9801S
V9811B
V9811A/
V9811S/
V9821
V9821S
86~88 55~56 42 42 SEG37~SEG39 I/O These pins are used for SEG output
for the LCD driver. And this pin also
M0~M2
can be used for analog input for
various measurements in Channel
M. Both M1 and M2 can be used for
analog signal input to the analog
comparator CB for comparison. The
input voltage signal into this pin to
be measured must be over the
h
range of -200 mV~3.4 V.
When these pins are used for

analog input to Channel M or the
ec
analog comparator CB, the SEG
output on these pins must be
disabled.

ot
TA1
(SFR 0xAD):
SDSP
SDA port (Fast IO);

ng

This pin can be used for reference

pulse input of exact 1s width.
When the bit “GPSI” (“bit6” of

“PRCtrl0”, 0x2D00) is set to ‘1’,
Va
this pin will be used for serial data

delivery for GPSI.

V98XX Datasheet
V9801S
V9811B
V9811A/
V9811S/
V9821
V9821S

TA2
(SFR 0xAD):
SCL
port (Fast IO);

h
When the bit “GPSI” (“bit6” of
“PRCtrl0”, 0x2D00) is set to ‘1’,
this pin is used for serial clock
ec
delivery for GPSI.

TXD2
“P25FS” (0x28CE):
ot
port;
Transmitter data output of UART2.

It can be configured to transmit 38-
kHz carrier wave.
ng

RXD2
“P24FS” (0x28CD):
port;
Va
Receiver data input of UART2.

When this pin is used for IR
communication, it should be
connected to a demodulator
externally.

TXD3
(0x28CC):
port;

UART3.

V98XX Datasheet
V9801S
V9811B
V9811A/
V9811S/
V9821
V9821S

RXD3
“P22FS” (0x28CB):
port;
- Receiver data input of UART3.
h
TXD4
“P21FS” (0x28CA):
T0
ec
port;

UART4;
- Timer0 external input.

ot
RXD4
“P20FS” (0x28C9):
T2
OSC port;
ng
- Receiver data input of UART4;
- Timer2 external input;
- OSC clock waveform output.
97~98 P10.4~P10.5 I/O - General-purpose input/output

port (Fast IO)
Va
99 63 47 47 RSTn I - Reset input, low active. Hold

“LOW” at least 5 ms to
generate a signal to reset the
system.
100 64 48 48 CTI I 32768-Hz crystal input

Connect a crystal around this pin
and pin “CTO” to generate a clock
signal “OSC”.

V98XX Datasheet
3.Functional Block Diagram
COMx
SEGx
CFx
V9801S
CTI CLK_RC
OSC PLL CLK_OSC phase
CTO compensation CLK_OSC
CLK_MCU 4COM× 40SEG
6COM× 38SEG
OSC CLK_MEA RMS calculation
monitor
RC 8COM× 36SEG
CLK_ADC LCD Driver

active/reactive/ ExTX
IAP apparent power
+
ADC calculation ISO/IEC 7816-3 ExRX
IAN -
CLK_RC
_int
active/reactive control TXD2
IBP + energy WDT IrDA
ADC accumulation RXD2
IBN -
energy-to-pulse TXDx
Buffer
32-bit data bus

UP conversion UART
+ RXDx
ADC
UN -
frequency UART_Timer _int
measurement 128KB 4KB
h
BAT Flash XRAM Tx
current detection Timer/PWM/
UM capture
no-load _int
AVSS detection CLK_MCU SDA
Interrupt
+ _int
MUX
M0 ADC GPSI SCL

- Vango Metering
enhanced _int
M1 Architecture
_int
8052 MCU core
ec
(VMA) JTAG P0
M2
1.185V Px
temp. GPIO/Fast IO
REF 8-bit data bus
_int
_ref
_ref
_int
+
CB
- _int digital power power CLK_OSC
SysCtrl 3.3V LDO RTC
supply monitor
_int _int
1.2V
REF_LP* _ref POR/BOR
REF
LDO33
VDCIN
SP
RSTN
DVCC
VDD5
ot
*1.2V REF_LP represents the low power reference voltage unit (not the BandGap circuit). This unit works all the time
until the chip is powered off. This unit provides the 3.3V LDO and digital power supply with 1.2V reference voltage, and it
can be the negative input for the comparator CB.
ng
Va

V98XX Datasheet
COMx
SEGx
CFx
V9811S
CTI CLK_RC
CLK_MCU 4COM×24SEG
RMS 6COM×22SEG
OSC CLK_MEA
monitor
RC calculation 8COM×20SEG
CLK_ADC active/ LCD Driver

reac tive/
IAP apparent
+
ADC power TXD2
IAN - IrDA
calculation CLK_RC RXD2
active/reac tive co ntrol
IBP + energy TXDx
ADC WDT UART
IBN - accumulation RXDx
energy-to-
UART_Timer _int
32-bit data bus

pulse Buffer
UP + conversion
ADC
- Timer/PWM/ Tx
UN frequency
measurement 128KB 4KB capture
Flash XRAM
current
detection SDA
BAT
GPSI SCL
no-load
h
AVSS detection
Interrupt CLK_MCU
+ _int
MUX
M1 ADC
- JTAG P0
Vango Metering
M2 enhanced
Architecture
_int
8052 MCU core
(VMA) Px
GPIO/Fast IO
temp.
ec
1.185V
+ REF 8-bit data bus
CB _int
-
_ref
_int
digital power power CLK_OSC

supply mo nitor
1.2V _int _int
REF_LP* _ref
POR/BOR
SP
REF
VDD5
VDCIN
LDO33
RSTN
DVCC
ot
COMx
SEGx
CFx
ng
V9811A
CTI CLK_RC
CLK_MCU 4COM×24SEG
RMS 6COM×22SEG
OSC CLK_MEA
monitor

reac tive/
IAP apparent
+
ADC power TXD2
IAN - IrDA
IBP + energy TXDx
ADC WDT UART
Va
energy-to-
UART_Timer _int
32-bit data bus
pulse Buffer
UP + conversion
ADC
- Timer/PWM/ Tx
UN frequency
Flash XRAM _int
current
detection SDA
BAT
GPSI SCL
no-load
AVSS detection
Interrupt CLK_MCU
+ _int
MUX
M1 ADC
- JTAG P0
Vango Metering
M2 enhanced
Architecture
_int
8052 MCU core

(VMA) Px
GPIO/Fast IO
temp.
1.185V
CB _int
-
_ref
_int

supply mo nitor
1.2V _int _int
REF_LP* _ref
POR/BOR
SP
REF
VDD5
VDCIN
LDO33
RSTN
DVCC

V98XX Datasheet
COMx
SEGx
CFx
V9821
CTI CLK_RC
CLK_MCU 4COM×17SEG
RMS 6COM×15SEG
OSC CLK_MEA
monitor

reac tive/
IAP apparent
+
ADC power TXD2
IAN - IrDA
IBP + energy TXDx
ADC WDT UART
energy-to-
UART_Timer _int
32-bit data bus

pulse Buffer
UP + conversion
ADC
- Timer/PWM/ Tx
UN frequency
Flash XRAM
current
detection SDA
BAT
GPSI
h
no-load SCL
AVSS detection
Interrupt CLK_MCU
+ _int
MUX
M1 ADC
- JTAG P0
Vango Metering
M2 enhanced
Architecture
_int
8052 MCU core
(VMA) Px
GPIO/Fast IO
temp.
ec
1.185V
CB _int
-
_ref
_int

supply mo nitor
1.2V _int _int
REF_LP* _ref
POR/BOR
SP
REF
VDD5
VDCIN
DVCC
LDO33
RSTN
ot
ng
Va

V98XX Datasheet
COMx
SEGx
CFx
V9821S
CTI CLK_RC
CLK_MCU 4COM×19SEG
RMS 6COM×17SEG
OSC CLK_MEA
monitor

reac tive/
IAP apparent
+
ADC power TXD2
IAN - IrDA
IBP + energy TXDx
ADC WDT UART
energy-to-
UART_Timer _int
32-bit data bus

pulse Buffer
UP + conversion
ADC
- Timer/PWM/ Tx
frequency
Flash XRAM
current
detection SDA
BAT
GPSI
h
no-load SCL
AVSS detection
Interrupt CLK_MCU
+ _int
MUX
M1 ADC
- JTAG P0
Vango Metering
M2 enhanced
Architecture
_int
8052 MCU core
(VMA) Px
GPIO/Fast IO
temp.
ec
1.185V
CB _int
-
_ref
_int
Digital power power CLK_OSC

supply mo nitor
1.2V _int _int
REF_LP* _ref
POR/BOR
SP
REF
VDD5
VDCIN
DVCC
LDO33
RSTN
ot
ng
Va

V98XX Datasheet
4.8052 MCU Core Architecture
4.1. Memory Map

V98XX contains three memory blocks:
- 256 bytes of internal SRAM (IRAM), sharing the upper 128 bytes of its addresses with Special
Function Registers (SFRs).
- 4-KB internal extended RAM (XRAM) and the memory of peripherals sharing the data memory area
at addresses “0000h” ~ “FFFFh”.
h
- 128-KB on-chip Flash memory mapping the program memory area at addresses “0000h” ~
“FFFFh”.
ec
4.2. IRAM (Internal RAM) and SFRS (Special
Function Registers)
The 256-byte internal SRAM (IRAM), located at addresses “00h” ~ “FFh”, is composed of two parts:
ot
the lower 128-byte RAM and the upper 128-byte RAM. When the output voltage of “DVCC” is higher
than
1.62 V, IRAM holds the data in it even when MCU is reset to its default state.
The lower 128-byte internal RAM contains three distinct blocks: Register Bank 0~3 (“00h” ~ “1Fh”),
Bit Address Area (“20h” ~ “2Fh”) and General RAM Area (“30h” ~ “7Fh”). All the lower 128-byte
ng
internal RAM can be accessed by direct or indirect addressing.
- Register Bank 0~3, 32 bytes from “00h” to “1Fh”, each is composed of 8 registers, R0~R7. Users
can configure “bit4” (“RS1”) and “bit3” (“RS0”) of the register “PSW” (SFR 0xD0, Program
Status Word SFR) to select the register bank to be used. By default Register Bank 0 is used.
Table 4-1 Select a Register Bank

Va
Register Bit Default Description
To select a register bank to be used
Program Status Word 00: Register Bank 0, located at addresses 00h~07h;

Bit[4:3]
PSW 0 01: Register Bank 1, located at addresses 08h~0Fh;
RS1/RS0
SFR 0xD0 10: Register Bank 2, located at addresses 10h~17h;
11: Register Bank 3, located at addresses 18h~1Fh.
- Bit Address Area (“20h” ~ “2Fh”), each with bit addresses from “00h” to “7Fh”, is bit addressable.
- General RAM, from “30h” to “7Fh”, can be addressed directly.
The upper 128-byte internal RAM, located at addresses “80h” ~ “FFh”, shares its addresses with a
group of specific internal registers (Special Function Registers, SFRs), but they are accessed in different

V98XX Datasheet
ways. SFRs are accessed via direct addressing, but the upper 128-byte internal RAM is accessed via
indirect addressing.
Lower 128 bytes
7Fh
Accessible by indirect
General RAM addressing ONLY
Direct Addressing FFh FFh
30h
Upper 128 bytes SFR
2Fh
Register Bank
Selection via Bit Address Area
Bit 4 and bit3 80h 80h
h
of PSW SFR Bit Addressable
7Fh
20h Accessible by direct

1Fh addressing ONLY
11 Register Bank 3 Lower 128 bytes
18h
ec
17h
10 Register Bank 2
10h
0Fh 00h
01 Register Bank 1
08h
07h
00 Register Bank 0 Accessible by
00h direct/indirect addressing
Figure 4-1 IRAM and SFR

ot
Table 4-2 Special Function Registers (SFR)
Addr. Register Bit 7 bit 6 bit 5 bit 4 bit 3 Bit 2 bit 1 bit 0
80h SysCtrl MEAFR FWC FSC PMG LCDG SLEEP1 SLEEP0 MCUFRQ
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81h SP - - - - - - - -
82h DPL0 - - - - - - - -
83h DPH0 - - - - - - - -
84h DPL1 - - - - - - - -
Va
85h DPH1 - - - - - - - -
86h DPS 0 0 0 0 0 0 0 SEL
87h PCON SMOD0 - 1 1 GF1 GF0 STOP IDLE
88h TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
89h TMOD GATE C/T M1 M0 GATE C/T M1 M0
8Ah TL0 - - - - - - - -
8Bh TL1 - - - - - - - -
8Ch TH0 - - - - - - - -
8Dh TH1 - - - - - - - -

V98XX Datasheet
8Eh CKCON - - T2M T1M T0M MD2 MD1 MD0
8Fh SPCFNC 0 0 0 0 0 0 0 WRS
90h RTCPEN - - - - - - - -
91h EXIF IE5 IE4 IE3 IE2 1 0 0 0
92h Reserve - - - - - - - -
d
93h RTCYC Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1
94h RTCCH - - C13 C12 C11 C10 C9 C8
h
95h RTCCL C7 C6 C5 C4 C3 C2 C1 C0
96h INTRTC - - - - - RTC2 RTC1 RTC0
ec
97h RTCPW - - - - - - WE
D
98h Rvd - - - - - - - -
99h Rvd - - - - - - - -
ot
9Ah RTCSC - S40 S20 S10 S8 S4 S2 S1
9Bh RTCMiC - M40 M20 M10 M8 M4 M2 M1
9Ch RTCHC - - H20 H10 H8 H4 H2 H1

ng
9Dh RTCDC - - D20 D10 D8 D4 D2 D1
9Eh RTCWC - - - - W8 W4 W2 W1
9Fh RTCMoC - - - Mo10 Mo8 Mo4 Mo2 Mo1
A0h CBANK - - - - - - B1 B0
A1h Systate - P14WK POR - IO RTC/CF PWRDN PWRUP

Va
A2h Rvd - - - - - - - -
A3h PLLLCK - - - - - - - PLLLCK
A4h P9OE P97OE P96OEN P95OEN P94OEN P93OEN P92OEN P91OEN P90OEN
N
A5h P9IE P97INE P96INEN P95INEN P94INEN P93INEN P92INEN P91INEN P90INEN
N
A6h P9OD - - - - - - - -
A7h P9ID - - - - - - - -
A8h IE EA ES1 ET2 ES0 ET1 EX1 ET0 EX0
A9h P10OE P107OE P106OEN P105OEN P104OEN P103OEN P102OEN P101OEN P100OEN

V98XX Datasheet
N
AAh P10IE P107IN P106INE P105INE P104INE P103INE P102INE P101INE P100INE
EN N N N N N N N
ABh P10OD
ACh P10ID
ADh P9FS P97FNC P96FNC P95FNC P94FNC P93FNC P92FNC P91FNC P90FNC
AEh Reserve - - - - - - - -
d
h
AFh IOWKDE - - - - CFWK P03WK P02WK P14WK
T
B8h IP 1 PS1 PT2 PS0 PT1 PX1 PT0 PX0
ec
C0h SCON1 SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1
C1h SBUF1 - - - - - - - -
C7h IOEDG P03ED P03EDG< P02EDG< P02EDG< P14EDG< P14EDG< P13EDG< P13EDG<
G<1> 0> 1> 0> 1> 0> 1> 0>
ot
C8h T2CON TF2 EXF2 - - EXEN2 TR2 C/T2 CP/RL2
C9h IOWK - - - - - CFWKEN IOP0 IORSTN
CAh RCAP2L - - - - - - - -
ng
CBh RCAP2H - - - - - - - -
CCh TL2 - - - - - - - -
CDh TH2 - - - - - - - -
CEh WDTEN - - - - - - - -
CFh WDTCLR - - - - - - - -
Va
D0h PSW CY AC - RS1 RS0 OV - P
D8h EICON SMOD1 1 - - PFI 0 0 0
D9h Reserve - - - - - - - -
d
DAh RDRTC - - - - - - - -
DBh DIVTHH DIV23 DIV22 DIV21 DIV20 DIV19 DIV18 DIV17 DIV16
DCh DIVTHM DIV15 DIV14 DIV13 DIV12 DIV11 DIV10 DIV9 DIV8
DDh DIVTHL DIV7 DIV6 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0
DEh PLLCNT - - - - - - STT1 STT0

ST

V98XX Datasheet
DFh SECINT - 1 SEC5 SEC4 SEC3 SEC2 SEC1 SEC0
E0h ACC - - - - - - - -
E8h EIE 1 1 1 EWDI EX5 EX4 EX3 EX2
F0h B - - - - - - - -
F8h EIP 1 1 1 PWDI PX5 PX4 PX3 PX2
4.3. Data Memory
h
4096 bytes of XRAM and peripherals registers can be mapped to the data storage space. XRAM is
located at addresses “0000h” ~ “0FFFh” that can be accessed limitless. The content of XRAM cannot
be reset by any reset event, and it will hold the data in it until the output voltage of “DVCC” is lower
ec
than
1.62 V.
The bytes located at addresses “0x3000” ~ “0x33FF”, (Info area, read) are designed to store
recommended configuration for analog registers , parameters for temperature measurement, and RTC
calibration that are pre-programmed by Vango when the chips are being manufactured, see Figure 4-2
ot
for details. The program can access the information within the address range in the same way as
accessing the peripheral registers.
In Data storage space, in addition to the contents of the XRAM and Info area, all of the peripherals
registers can be reset. Among them, the LCD/GPIO simulation control/registers related energy metering
can only be reset and are set to the default values by the Level 1 reset, other registers will be reset to
ng
the default values by the Level 1/2/3 reset. The contents of the Info area will not be reset, after a reset
event of Level 1, the content of these bytes will be settled in 2 ms, and then CPU can execute the
programs in Flash memory. These bytes are readable only, and MCU can read of these bytes as they are
peripherals.
Va

V98XX Datasheet
28FFh
...
FFFFh
2F05h 28DCh
GPSI
... 2F01h
...
2D01h
GPIO（P0~P8）/
Peripheral control registers
2D00h IR communication
33FFh ...
2C23h
Info（Read only） LCD
2C00h ... 28A8h
3000h ... Extended interrupts 28A6h
2FFFh
Enhanced UART (EUART)
2B05h … 28A2h
... 28A0h
2B01h XRAMPWD
...
h
IR communication/ 289Fh
2F05h
2A05h PWM
Enhanced UART (EUART) 2898h
2A01h
2800h 2A00h ...
... 287Eh
2900h
ec
Metering control registers
... 28FFh
...
2878h
2800h 2868h
2000h Analog control
1FFFh
registers
... 2858h
2854h
... Extended interrupts
ot
2840h
Extended UART
10FFh Metering data
1000h registers 2820h
0FFFh
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XRAM，Accessible ...
without limitation
0000h 2800h
Figure 4-2 Data Memory
Table 4-3 Allocation of Info Area

Va
Number
Starting Address Functional Description Endianness
of Byte
0x 401 Noted additionally 2 Little-endian
0x 40B Noted additionally 1 Little-endian
0x 40C Noted additionally 4 Little-endian

V98XX Datasheet
Number
of Byte
0x 41A Noted additionally 2 Little-endian
h
0x 41C Noted additionally 1 Little-endian
0x 41D Noted additionally 1 Little-endian
ec
0x 41E Noted additionally 2 Little-endian
0x420 a 4 Little-endian
0x 424 b 4 Little-endian
0x 428 c 4 Little-endian
ot
0x 42C d 4 Little-endian
0x 430 e 4 Little-endian
0x 434 ADD33 verification 2 Little-endian

ng
0x 436 Reserved 2 Little-endian
0x 438 a 4 Little-endian
0x 43C b 4 Little-endian
Va
0x 444 d 4 Little-endian
0x 44C ADD33 verification 2 Little-endian
0x 44E Reserved 2 Little-endian
0x 450 a 4 Little-endian
0x 454 b 4 Little-endian
0x 45C d 4 Little-endian
0x 464 ADD33 verification 2 Little-endian

V98XX Datasheet
Number
of Byte
0x 46C Reserved 2 Little-endian
h
0x 47C Reserved 2 Little-endian
ec
Backup 1 of temperature
0x 480 2 Big-endian
deviation
0x 482 ADD33 verification 2 Big-endian

ot
Backup 2 of temperature Big-endian
0x 484 2
deviation
Backup 3 of temperature Big-endian

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0x 488 2
deviation
0x 48A ADD33 verification 2 Big-endian
Backup 1 of RTC Big-endian

0x 48C 2
temperature deviation
0x 48E ADD33 verification 2 Big-endian

Va

0x 490 2

0x 494 2
Backup 1 of parabolic Big-endian

0x 498 20
coefficient Bpara of crystal
0x 4AC ADD33 verification 2 Big-endian
0x 4AE Backup 2 of parabolic 20 Big-endian

V98XX Datasheet
Number
of Byte
0x 4C2 ADD33 verification 2 Big-endian
Backup 3 of parabolic Big-endian

0x 4C4 20
0x 4D8 ADD33 verification 2 Big-endian
Backup 1 of crystal fixed- Big-endian

0x 4DA 2
point temperature
0x 4DC ADD33 verification 2 Big-endian
h
0x 4DE 2
point temperature
ec
0x 4E0 ADD33 verification 2 Big-endian

0x 4E2 2
point temperature
0x 4E4 ADD33 verification 2 Big-endian

ot
0x 4E6 Reserved 2 Big-endian
Standard RTC capturing Big-endian

0x 4E8 4
value
Target chip RTC capturing Big-endian

0x 4EC 4
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value
0x 4F0 Reserved 4 Big-endian
0x 4F4 SD502 version number 4 Big-endian
Ambient temperature Big-endian

0x 4F8 during temperature 4
calibration
Va
Temperature of target chip Big-endian

0x 4FC before temperature 4
calibration
0x 500 Reserved 256
*Users can read of these bytes and obtain the recommended configuration of the analog control registers,
and then write them to the analog control registers.
**See “Measuring Temperature” for details of parameter A, B, C, D, E, and temperature error.
***When users are using the crystals provided by Vango, they can read these addresses to obtain the
details of crystal frequency deviation Δ, parabolic coefficient Bpara, and turnover temperature of the
crystal, to calibrate RTC. See the corresponding application notes for details.

V98XX Datasheet
4.4. Program Memory

In V98XX, the 128-KB on-chip Flash memory (Including program encryption bytes) and the Flash
control registers are mapped to the MCU program memory at addresses “0000h” ~ “FFFFh”. The Flash
control registers mapped to the MCU program memory at addresses “0x0401” and “0x0402”,
determining the programming mode and power consumption mode of the Flash memory.
Table 4-4 Flash Control Register 1 (FCtrl1, 0x0402)
0x0402, R/W, Flash Control Register 1, FCtrl1
Bit Default Description
Bit7 - - Set this bit to ‘1’ to activate write operation of other bits.
h
When the MCU clock frequency (fMCU) is 3.2768 MHz, clear this bit to
enable programming, page erase, and mass erase of Flash memory.
Bit6 CKSL 0
ec
When fMCU is 13.1072 MHz, set this bit to ‘1’ to enable programming,
page erase, and mass erase of Flash memory.
Bit[5:0] Reserved 0 These bits must hold their default values for proper operation.
ot
ng
Va

V98XX Datasheet
01FFFFH
Bank3
018000H
017FFFH
Bank2
Bank3
010000H Bank2
00FFFFH FFFFH
h
Bank1 Bank1
008000H 8000H
ec
007FFFH 7FFFH
Common Area Common area

Flash Control Register 0402H
0401H
Program Encryption Bytes 000400H Program Encryption Bytes 0400H
000000H 0000H
ot
128KB Flash Memory Program Memory Area
The parts in grey represent “Flash memory” mapped in
the “Program Memory Area”.
ng
Figure 4-3 Flash Memory and Program Memory Area

The 128-KB on-chip Flash memory of V98XX is featured with write protection, program encryption,
and ISP (In-System Programming), and IAP (In-Application Programming) supported.
The 8052 MCU core of V98XX can address up to 64-KB program memory area, “0000h” ~ “FFFFh”,
but the Flash memory can store up to 128-KB codes. So to execute more than 64-KB program, the code
banking technique should be used. Using this technique, the program can be divided into no more than
Va
four parts with no more than 64-KB codes each, and is allocated in different parts of the Flash memory:
- “Common Area”, at addresses “0000h” ~ “7FFFh”: To allocate the common codes, such as
interrupt vectors, reset vectors, bank switching routines, interrupt service routines, and so on.
It is always mapped to the program memory area at addresses “0000h” ~ “7FFFh”.
- “Code Area”, at addresses “8000h” ~ “1FFFFh”: To allocate the application codes; Bank 1,
at addresses “8000h” ~ “FFFFh”; Bank2, at addresses “10000h” ~ “17FFFh”; Bank 3, at
addresses “18000h” ~ “1FFFFh”. Each bank can be mapped to the program memory
area at addresses “8000h” ~ “FFFFh”, and the processor can access the register “CBANK”
(SFR 0xA0) to switch the banks and execute the codes.
Table 4-5 Code Bank Register (CBANK, SFR 0xA0)

V98XX Datasheet
SFR 0xA0, R/W, Code Bank Register, CBANK
bit[7:2] Reserved 0
To select code bank to be mapped to the code area of the program

memory space at addresses “8000h” ~ “FFFFh”.
bit[1:0] B<1:0> 1 01: Bank 1;
10: Bank 2;
11: Bank 3.
h
In V98XX, the on-chip Flash memory is divided into 256 pages with 512 bytes each. The codes in the
Flash memory can be read, erased, or programmed in pages or mass erased.
ec
Notes: The third page of the Flash memory, at addresses “0400h” ~ “05FFh”, is pre-programmed with
codes by the manufacturer, so this part cannot be used for application codes.
When the low logic level is input on the pin “MODE1”, the chip will be in the debugging mode. In this
mode, the 4 pins of Group P0 work as JTAG interfaces. Users can use the DLL codes and simulators
provided by Vango to download and debug the applications in Keil μVision IDE or IAR IDE via the JTAG
ot
interfaces.
Notes:
Please comment the lines, like switching the system clock source from PLL clock to OSC clock,
and get to sleep, out of the codes.
ng
In the debugging mode, the system cannot get to “Sleep” or “Deep Sleep”, and the reset events,
POR/BOR and WDT overflow, are masked. In the sleeping state, a power recovery event will occur
immediately once the system goes to the debugging mode.
In the debugging mode, the TCK speed limit is 400 Kbps by default. The command “0x22” can increase
it to the current PLL clock frequency, and the command “0x23” can recover it.
No capacitors should be connected to the JTAG interfaces to avoid the download failure of codes.
Va
There is an encryption bit (“bit0” of byte located at address “0x0400”) in the Flash memory. The
configuration of this bit has effect on the access to the Flash memory. When the high logic level is input
on the pin “MODE1”, the chip will be in the metering mode. In this mode, the on-chip Flash memory is
IAP supportive, and the access to the Flash memory will not be affected by the encryption bit
configuration. When the low logic level is input on the pin “MODE1”, the chip will be in the metering
mode. In this mode, the on-chip Flash memory is IAP and ISP supportive, and the encryption bit
configuration will affect the access to the Flash memory.
Table 4-6 Programming Flash Memory

V98XX Datasheet
Write 0 to encryption bit Write 1 to encryption bit
Programming
Flash memory
method Mass Page Mass Page
Write Read Write Read
erase erase erase erase
In debugging 00000h~17FFFh X X X
mode（IAP or √ √ √ √ √
ISP） 18000h~1FFFFh X √ X
00000h~003FFh X √ X X √ X
IAP in metering
X X
mode
00400h~1FFFFh √ √ √ √ √ √
h
Note: After ISP, the input logic low to the pin “RSTn” or power on the chip again to activate the ISP
read encryption.
ec
4.5. Instruction Set
The instruction set of the enhanced 8052 core is compatible with the industry standard 8051 MCU in
binary code and the execution results are functionally equivalent. However, the number of clock cycles
that each instruction cycle needs is different from that of the standard 8051 instruction set. And the
ot
execution timing of each instruction is also different from that of standard 8051 MCU. Each instruction
cycle has four clock cycles.
Table 4-7 Instruction Set

ng
Symbol Description
A Accumulator
Rn Register R0 ~ R7
direct Internal direct addressable registers
@Ri Internal register pointed to by R0 or R1 (Except MOVX)

Va
rel Two’s complement offset byte
bit Direct bit address
#data 8-bit constant
#data 16 16-bit constant
addr 16 16-bit destination address
addr 11 11-bit destination address
Inst. Hex
Mnemonic Description Byte
Cycles Code
Arithmetic

V98XX Datasheet
ADD A, Rn Add register to A 1 1 28 – 2F
ADD A, direct Add direct byte to A 2 2 25
ADD A, @Ri Add data memory to A 1 1 26 – 27
ADD A, #data Add immediate to A 2 2 24
ADDC A, Rn Add register to A with carry 1 1 38 – 3F
ADDC A, direct Add direct byte to A with carry 2 2 35
ADDC A, @Ri Add data memory to A with carry 1 1 36 – 37
ADDC A, #data Add immediate to A with carry 2 2 34
h
SUBB A, Rn Subtract register from A with borrow 1 1 98 – 9F
SUBB A, direct Subtract direct byte from A with borrow 2 2 95
ec
SUBB A, @Ri Subtract data memory from A with borrow 1 1 96 – 97
SUBB A, #data Subtract immediate from A with borrow 2 2 94
INC A Increment A 1 1 04
INC Rn Increment register 1 1 08 – 0F

ot
INC direct Increment direct byte 2 2 05
INC @Ri Increment data memory 1 1 06 – 07
DEC A Decrement A 1 1 14
DEC Rn Decrement register 1 1 18 – 1F

ng
DEC direct Decrement direct byte 2 2 15
DEC @Ri Decrement data memory 1 1 16 – 17
INC DPTR Increment data pointer 1 3 A3
MUL AB Multiply A by B 1 5 A4
Va
DIV AB Divide A by B 1 5 84
DA A Decimal adjust A 1 1 D4
Logical
ANL A, Rn AND register to A 1 1 58 – 5F
ANL A, direct AND direct byte to A 2 2 35
ANL A, @Ri AND data memory to A 1 1 56 – 57
ANL A, #data AND immediate to A 2 2 54
ANL direct, A AND A to direct byte 2 2 52
ANL direct, #data AND immediate data to direct byte 3 3 53

V98XX Datasheet
ORL A, Rn OR register to A 1 1 48 – 4F
ORL A, direct OR direct byte to A 2 2 45
ORL A, @Ri OR data memory to A 1 1 46 – 47
ORL A, #data OR immediate to A 2 2 44
ORL direct, A OR A to direct byte 2 2 42
ORL direct, #data OR immediate data to direct byte 3 3 43
XRL A, Rn Exclusive-OR register to A 1 1 68 – 6F
XRL A, direct Exclusive-OR direct byte to A 2 2 65
h
XRL A, @Ri Exclusive-OR data memory to A 1 1 66 – 67
XRL A, #data Exclusive-OR immediate to A 2 2 64
ec
XRL direct, A Exclusive-OR A to direct byte 2 2 62
XRL direct, #data Exclusive-OR immediate to direct byte 3 3 63
CLR A Clear A 1 1 E4
CPL A Complement A 1 1 F4
ot
SWAP A Swap nibbles of A 1 1 C4
RL A Rotate A left 1 1 23
RLC A Rotate A left through carry 1 1 33
RR A Rotate A right 1 1 03
ng
RRC A Rotate A right through carry 1 1 13
Data Transfer
MOV A, Rn Move register to A 1 1 E8 – EF
MOV A, direct Move direct byte to A 2 2 E5

Va
MOV A, @Ri Move data memory to A 1 1 E6 – E7
MOV A, #data Move immediate to A 2 2 74
MOV Rn, A Move A to register 1 1 F8 – FF
MOV Rn, direct Move direct byte to register 2 2 A8 – AF
MOV Rn, #data Move immediate to register 2 2 78 – 7F
MOV direct, A Move A to direct byte 2 2 F5
MOV direct, Rn Move register to direct byte 2 2 88 – 8F
MOV direct, direct Move direct byte to direct byte 3 3 85
MOV direct, @Ri Move data memory to direct byte 2 2 86 – 87

V98XX Datasheet
MOV direct, #data Move immediate to direct byte 3 3 75
MOV @Ri, A MOV A to data memory 1 1 F6 – F7
MOV @Ri, direct Move direct byte to data memory 2 2 A6 – A7
MOV @Ri, #data Move immediate to data memory 2 2 76 – 77
MOV DPTR, #data Move immediate to data pointer 3 3 90
MOVC A, @A+DPTR Move code byte relative DPTR to A 1 3 93
MOVC A, @A+PC Move code byte relative PC to A 1 3 83
MOVX A, @Ri Move external data (A8) to A 1 2 – 9* E2 – E3
h
MOVX A, @DPTR Move external data (A16) to A 1 2 – 9* E0
MOVX @Ri, A Move A to external data (A8) 1 2 – 9* F2 – F3
ec
MOVX @DPTR, A Move A to external data (A16) 1 2 – 9* F0
PUSH direct Push direct byte onto stack 2 2 C0
POP direct Pop direct byte from stack 2 2 D0
XCH A, Rn Exchange A and register 1 1 C8 – CF

ot
XCH A, direct Exchange A and direct byte 2 2 C5
XCH A, @Ri Exchange A and data memory 1 1 C6 – C7
XCHD A, @Ri Exchange A and data memory nibble 1 1 D6 – D7
* Number of cycles is user-selectable.

ng
Boolean
CLR C Clear carry 1 1 C3
CLR bit Clear direct bit 2 2 C2
SETB C Set carry 1 1 D3

Va
SETB bit Set direct bit 2 2 D2
CPL C Complement carry 1 1 B3
CPL bit Complement direct bit 2 2 B2
ANL C, bit AND direct bit to carry 2 2 82
ANL C, /bit AND direct bit inverse to carry 2 2 B0
ORL C, bit OR direct bit to carry 2 2 72
ORL C, /bit OR direct bit inverse to carry 2 2 A0
MOV C, bit Move direct bit to carry 2 2 A2
MOV bit, C Move carry to direct bit 2 2 92

V98XX Datasheet
Branching
ACALL addr 11 Absolute call to subroutine 2 3 11 – F1
LCALL addr 16 Long call to subroutine 3 4 12
RET Return from subroutine 1 4 22
RETI Return from interrupt 1 4 32
AJMP addr 11 Absolute jump unconditional 2 3 01 – E1
LJMP addr 16 Long jump unconditional 3 4 02
SJMP rel Short jump (relative address) 2 3 80
h
JC rel Jump on carry = 1 2 3 40
JNC rel Jump on carry = 0 2 3 50
ec
JB bit, rel Jump on direct bit = 1 3 4 20
JNB bit, rel Jump on direct bit = 0 3 4 30
JBC bit, rel Jump on direct bit = 1 and clear 3 4 10
JMP @A + DPTR Jump indirect relative DPTR 1 3 73

ot
JZ rel Jump on accumulator = 0 2 3 60
JNZ rel Jump on accumulator ≠ 0 2 3 70
CJNE A, direct, rel Compare A, direct JNE relative 3 4 B5
CJNE A, #d, rel Compare A, immediate JNE relative 3 4 B4

ng
CJNE Rn, #d, rel Compare reg, immediate JNE relative 3 4 B8 – BF
CJNE @Ri, #d, rel Compare ind, immediate JNE relative 3 4 B6 – B7
DJNZ Rn, rel Decrement register, JNZ relative 2 3 D8 – DF
DJNZ direct, rel Decrement direct byte, JNZ relative 3 4 D5

Va
Miscellaneous
NOP No operation 1 1 00
There is an additional reserved opcode (A5) that performs the same function as NOP.
4.5.1. Programmable MOVX Timing
The programmable MOVX timing feature enables application to adjust the speed of the access to the
data memory. CPU can execute the MOVX instruction in as little as two instruction cycles. However, it is
sometimes desirable to stretch this value. “Bit2” ~ “bit0” (MD2~0) of “CKCON” (SFR 0x8E) control
the stretch value, which can set the stretch value from ‘0’ to ‘7’. A stretch value of ‘0’ means no extra
instruction cycles are added and the MOVX instructions will be executed in two instruction cycles. A
stretch value of ‘7’ means additional seven instruction cycles are added, and the MOVX instructions will

V98XX Datasheet
be executed in nine instruction cycles. The stretch value is programmable. The stretch value will affect
the width of the read/write strobe and all related timing. A higher stretch value results in a wider
read/write strobe. By default the stretch value is ‘1’, meaning three instruction cycles are needed to
execute the MOVX instruction.
Table 4-8 Programmable MOVX Timing
Configuring the stretch

value Cycles to access the Read/write strobe width
memory (clocks)
MD2 MD1 MD0
0 0 0 2 2
h
0 0 1 3 (default value) 4
0 1 0 4 8
ec
0 1 1 5 12
1 0 0 6 16
1 0 1 7 20
ot
1 1 0 8 24
1 1 1 9 28
ng
4.5.2. Dual Data Pointers
Dual data pointers, standard data pointer “DPTR0” located at addresses “SFR 0x82” and “SFR
0x83”, and the second data pointer “DPTR1” located at addresses “SFR 0x84” and “SFR 0x85”, can
improve the efficiency significantly when moving large blocks of data. The bit “SEL” (bit0) in the DPTR
Select Register (DPS, SFR 0x86) is configured to select the active pointer. When “SEL” is cleared, “DPL0”
Va
(SFR 0x82) and “DPH0” (SFR 0x83) are selected. When “SEL” is set to ‘1’, “DPL1” (SFR 0x84) and
“DPH1” (SFR 0x85) are selected.
All DPTR-related instructions use the selected data pointer. Rewrite of the bit “SEL” to switch the
pointer. The fastest way to do so is to use the increment instruction (INC DPS). Only one instruction is
required to switch from the source address to the target address. When doing a block move, it is no need
to save source and target addresses, which saves the number of application codes.

V98XX Datasheet
5.Reset
In V98XX, all circuits, except for the RTC calibration registers, RTC timing registers, IRAM, XRAM, and
Info area, can be reset to their default states by an event of a specific reset level. Three levels of events
are designed to reset different circuits of the system. They are:
 Level 3: The lowest level, including the debugging reset instruction.

When the event of this level occurs, CPU, interrupt management circuits, timers, UART interfaces,
and GPSI interfaces will be reset to their default states.
 Level 2: Including the power recovery (Power up), IO wakeup event, RTC wakeup event, and CF
pulse wakeup event.
When an event of this level occurs, “Clock Switchover Control Register” (“SysCtrl”, SFR 0x80),
h
“IO Wakeup Control Register” (“IOWK”, SFR 0xC9), “IO Wakeup Edge Control Register”
(“IOEDG”, SFR 0xC7), Flash control registers, watch-dog timer, and all the circuits that can be reset
by events of Level 3 will be reset to their default states.
ec
 Level 1: The highest level, including the RSTn pin input signal (RSTn pin reset), power-on reset
(POR), brown-out reset (BOR), and WDT overflow event.
When an event of this level occurs, the LCD driver, general-purpose I/O ports, “System State
Register” (“Systate”, SFR 0xA1), “P0 IO Wakeup Flag Register” (“IOWKDET”, SFR 0xAF),
analog control registers, the global energy metering architecture, and all the circuits that can be
reset by events of Level 2 will be reset to their default states.
ot
In V98XX, the reset management circuits are designed by following the rule that a reset event of higher
level can reset the circuits that can be reset by a reset event of lower level, but not vice versa.
Level 1: Level 2:
All circuits except SFR 0x80/0xC7/
registers for RTC 0xC9, Flash control
ng
calibration and registers, WDT, and

timing, and data circuits that can be
of IRAM and reset by events of
XRAM. Level 3.
RSTN
POR/BOR
WDT overflow
POR Level 3: CPU,
MODE1 Interrupts,
Timers, UART
and GPSI.
VDCIN
Power recovery (power up)
Va
CF pulse output
generate
signal?
CFWKEN
reset
Flag bits:
To
To wake up the system from POR, bit5 of SFR 0xA1;

RTC wakeup Sleep only. IO, bit3 of SFR 0xA1;
RTC/CF, bit2 of SFR 0xA1;
CFWK, bit3 of SFR 0xAF;
CFWK RTC/CF
IORSTN P03WK, bit2 of SFR 0xAF;
P02WK, bit1 of SFR 0xAF;
IO wake up event IOP14, bit0 of SFR 0xAF.
WAKEUP1
IOEDG, SFR 0xC7
To select active
edge for IO
WAKEUP2 Enable bits:

wakeup.
CFWKEN, bit2 of SFR 0xC9;

WAKEUP3 IOP0, bit1 of SFR 0xC9;
IORSTN, bit0 of SFR 0xC9.
WAKEUP4
Pins
IOP0
P02WK P03WK IOP14 IO
Debugging
Instruction
Figure 5-1 Reset Unit Diagram
Table 5-1 Circuits to Be Reset

V98XX Datasheet
Reset by
Unit
Events of Level 1 Events of Level 2 Events of Level 3
CPU √ √ √
Interrupts √ √ √
Timers √ √ √
UART √ √ √
GPSI √ √ √
h
Flash control registers √ √ X
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SysCtrl (SFR 0x80) √ √ X
IOEDG (SFR 0xC7) √ √ X
IOWK (SFR 0xC9) √ √ X
WDT √ √ X
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Systate (SFR 0xA1) √ X X
IOWKDET (SFR 0xAF) √ X X

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Global Energy Metering Architecture

√ X X
(VMA)
Analog control registers √ X X
Electricity metering all registers about

√ X X
VMA
Va
LCD driver √ X X
General-purpose I/O ports (GPIO) √ X X
Calibration registers X X X
RTC Timing registers X X X
Other registers √ X X
IRAM X X X
XRAM X X X

V98XX Datasheet
Reset by
Unit
Events of Level 1 Events of Level 2 Events of Level 3
Info area (0x3000~0x33FF) X X X
5.1. Level 3
In V98XX, only the debugging reset instruction is designed as the reset event of Level 3. It can reset
CPU, interrupt management circuits, timers, UART interfaces, and GPSI interfaces.
h
When “logic 0” is input to the pin “MODE1”, the system will enter the debugging mode. In this mode,
when the debugging operation is enabled or the tab “Reset” in IDE is clicked, a debugging reset
instruction will be executed to reset CPU and its peripherals.
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5.2. Level 2
In V98XX, power recovery, IO wakeup event, RTC wakeup event, and CF pulse wakeup event are
designed as the reset events of Level 2.
ot
By default, any event of this level can wake up the system from “Sleep” or “Deep Sleep” and reset
the system to OSC state. But if the bit “IORSTN” (“bit0” of “IOWK”, SFR 0xC9) is set to ‘1’, any event
of this level can wake up the system without reset, after wakeup, CPU keeps on executing programs; all
circuits go back where the system enters the sleeping state, but “bit[2:1]” (“SLEEP1” and “SLEEP0”)
and “bit[6:5]” (“FWC” and “FSC”) are cleared.
ng
When “IORSTN” (“bit0” of “IOWK”, SFR 0 xc9) is cleared, in addition to the reset circuit which
can be reset by Level 3 reset events, the wakeup events can reset the clock switch control register
(“SysCtrl”, SFR 0 x80), IO dormancy awakening edge selection register (“IOEDG”, SFR 0 xc7), IO
dormancy awakened control register (“IOWK”, SFR 0 xc9), FLASH control registers and WDT, please
refer to
Figure 5-1 for more detailed information.
Va
5.2.1. Power Recovery (Power up)
In V98XX, when the voltage on the pin “VDCIN” rises from lower than 1.0 V to higher than 1.1 V, or
when the voltage on the pin “VDCIN” is higher than 1.1 V after any reset event of Level 1, a power
recovery event will occur. By default, this event wakes up the chip and resets it to the OSC state, and
the reset signal holds 8 OSC clock cycles (About 244 μs). To lower the power consumption, users can set
the bit “IORSTN” (“bit0” of “IOWK”, SFR 0xC9) to ‘1’ to wake up the system without reset.
5.2.2. IO Wakeup Event
In V98XX, 4 pins, “WAKEUP1 (P1.4)”, “WAKEUP2 (P1.3)”, “WAKEUP3 (P0.2)”, and

V98XX Datasheet
“WAKEUP4 (P0.3)” can be used to wake up the chip from “Sleep” or “Deep Sleep”. Pins
“WAKEUP1” and “WAKEUP2” can be used for the wakeup input all the time, but pins “WAKEUP3”
and “WAKEUP4” can be used for the wakeup input only when the bit “IOP0” (“bit1” of “IOWK”,
SFR 0xC9) is set to ‘1’. The wakeup input on these four I/O ports are independent.
If the four I/O ports are set to “Input enabled” before the chip enters “Sleep” or “Deep Sleep”, a
transition (Either “high-to-low” or “low-to-high”, with more than four OSC clock cycles on both levels)
on the pin in “Sleep” or “Deep Sleep” can wake up the system. Users can configure the register
“IOEDG” (SFR 0xC7) to determine the active edge for the IO wakeup event. Any IO wakeup event can
set the bit “IO” (“bit3” of “Systate”, SFR 0xA1) to ‘1’. When the bit “IO” is set to ‘1’, users can read
bits “P14WK”, “P02WK”, and “P03WK” (“bit[0:2]” of “IOWKDET”, SFR 0xAF) to detect that the
system is woken up by the transition on which pin.
By default, a transition on any one of the four I/O ports can wake up the system and reset it to the
h
OSC state. To lower the power consumption, users can set the bit “IORSTN” (“bit0” of “IOWK”, SFR
0xC9) to ‘1’ to wake up the system without reset.
ec
5.2.3. RTC Wakeup Event
In V98XX, RTC can wake up the system from “Sleep” at an interval set in registers “INTRTC” (SFR
0x96) and “SECINT” (SFR 0xDF). When the system is woken up by an RTC event, the bit “RTC/CF”
(“bit2” of “Systate”, SFR 0xA1) will be set to ‘1’, but the bit “CFWK” (“bit3” of “IOWKDET”, SFR
ot
0xAF) will be cleared. Please refer to Figure 5-1 for more detailed information.
By default, RTC wakeup event can wake up the system from “Sleep” and reset it to the OSC state.
The reset signal holds 8 OSC clock cycles. To lower the power consumption, users can set the bit
“IORSTN” (“bit0” of “IOWK”, SFR 0xC9) to ‘1’ to wake up the system without reset.
ng
5.2.4. CF Pulse Wakeup Event
In V98XX, the system may be woken up from “Sleep” by CF pulse output, if CF pulse output is enabled
(“CFENR” = ‘1’ or “CFEN” = ‘1’, “bit[5:4]” of “PMCtrl4”, 0x287D), and CF pulse output is enabled
to be a wakeup event (“CFWKEN” = ‘1’, “bit2” of “IOWK”, SFR 0xC9) before the system enters
Va
“Sleep”. When a CF pulse wakeup event occurs, both bits “RTC/CF” (“bit2” of “Systate”, SFR 0xA1)
and “CFWK” (“bit3” of “IOWKDET”, SFR 0xAF) are set to 1s.
By default, a CF pulse wakeup event can wake up the system from “Sleep” and reset it to the OSC
state. To lower the power consumption, users can set the bit “IORSTN” (“bit0” of “IOWK”, SFR 0xC9)
to ‘1’ to wake up the system without reset.
5.3. Level 1
In V98XX, WDT overflow, RSTn pin input signal, Power-On Reset (POR), and Brown-Out Reset (BOR)
are designed as the reset events of Level 1. When any one of these reset events occurs, the bit “POR”
(“bit5” of “Systate”, SFR 0xA1) will be set to ‘1’.

V98XX Datasheet
5.3.1. RSTn Pin Reset
Holding logic low on the pin “RSTn” for more than 5 ms can trigger an RSTn pin reset signal to reset
the system. After the logic is pulled high, the reset signal holds four more OSC clock cycles (About 122
μs) and then is released.
To prevent from the static disturbance, the input signal on the pin “RSTn” is filtered basing on the RC
clock.
RSTn input
Internal reset
h
signal
5ms 122μs
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Figure 5-2 RSTn Pin Reset Timing
5.3.2. Power-On Reset (POR) and Brown-Out Reset

ot
(BOR)
In V98XX, the output voltage of the digital power supply (Via pin “DVCC”) is monitored by the
power-on/brown-out reset circuit.
ng
On power-up, a power-on reset signal will be generated to reset the system when the output voltage
of pin “DVCC” is lower than 1.4 V. The system will stay in the reset state for four OSC clock cycles
(About 122 μs) even when the voltage on the pin “DVCC” is higher than 1.4 V.
On power-down, when the output voltage on the pin “DVCC” is lower than 1.4 V, the brown-out
reset circuit will generate a reset signal to reset the system.
Va
When “logic 0” is input to the pin “MODE1”, POR/BOR will be masked.
1.4V 1.4V
DVCC
Internal reset
signal POR BOR
122μs
Figure 5-3 POR/BOR Timing

V98XX Datasheet
5.3.3. WDT Overflow Reset
In V98XX, when the WDT overflows, a reset signal will be generated and the system will be reset. The
system will exit from the reset state in eight RC clock cycles (About 250 μs).
When “logic 0” is input to the pin “MODE1”, WDT overflow reset will be masked.
5.4. Registers
Table 5-2 System State Register, Systate (SFR 0xA1)
SFR 0xA1, R, System State Register, Systate
h
ec
Bit[7:6] Reserved.
Bit5 When this bit is read out as ‘1’, it indicates the system is reset by an event of
0 Level 1: POR/BOR, RSTn pin reset, or WDT overflow reset. This bit will be cleared
POR when a reset event of other levels occurs.
ot
Bit4 0 Reserved
Bit3 When this bit is read out as ‘1’, it indicates the system is woken up from “Sleep”
0
IO or “Deep Sleep” by an IO wakeup event.
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When this bit is read out as ‘1’, but bit “CFWK” (“bit3” of “IOWKDET”, SFR
0xAF) is cleared, it indicates the system is woken up from “Sleep” by RTC wakeup
Bit2
0 event.
RTC/CF
If both this bit and bit “CFWK” are set to 1s, it indicates the system is woken up
from “Sleep” by CF pulse wakeup event.
Va
When the input voltage on pin “VDCIN” is lower than 1.0 V, this bit is read out
as ‘1’, indicating that the system is powered down. If the power down interrupt is
Bit1
0 enabled, an interrupt will be triggered when this bit is read out as ‘1’.
PWRDN
When the input voltage on pin “VDCIN” is higher than 1.1 V, this bit holds its
default value, indicating no power down event occurs.
When the input voltage on pin “VDCIN” is higher than 1.1 V, this bit is read out
Bit0 as ‘1’, indicating that the system is powered up by line power supply.
0
PWRUP When the input voltage on pin “VDCIN” is lower than 1.0 V, this bit holds its
default value, indicating the system is powered up by the battery.
Table 5-3 P0 IO Wakeup Flag Register (IOWKDET, SFR 0xAF)

V98XX Datasheet
SFR 0xAF, R, P0 IO Wakeup Flag Register, IOWKDET
Bit R/W Default Description
Bit[7:4] Reserved - -
If this bit is set to ‘1’ when bit “RTC/CF” (“bit2” of

bit3 CFWK R 0 “Systate”, SFR 0xA1) is read out as ‘1’, it indicates that
system is woken up from Sleep by CF pulse wakeup event.
If this bit is set to ‘1’ when bit “IO” (“bit3” of “Systate”, SFR
0xA1) is read out as ‘1’, it indicates the system is woken up
Bit2 P03WK R 0
from “Sleep” or “Deep Sleep” by a transition on pin
“WAKEUP4” (P0.3).
h
Bit1 P02WK R 0
ec
bit0 P14WK R 0
ot
When an event of reset Level 1 occurs, this register will be reset to its default state.
Table 5-4 IO Wakeup Edge Control Register (IOEDG, SFR 0xC7)
SFR 0xC7, R/W, IO Wakeup Edge Control Register, IOEDG

ng
To set the active edge for pin “WAKEUP4” (P0.3)
00/11: high-to-low transition;

bit[7:6] P03EDG R/W 0
01: low-to-high transition;
10: either transition.

Va


bit[1:0] P13EDG R/W 0 To set the active edge for pin “WAKEUP2” (P1.3)

V98XX Datasheet
SFR 0xC7, R/W, IO Wakeup Edge Control Register, IOEDG
Table 5-5 IO Wakeup Control Register (IOWK, SFR 0xC9)
SFR 0xC9, R/W, IO Wakeup Control Register, IOWK
h
Bit[7:3] Reserved - -
1: to enable CF pulse output to wake up the system from
ec
“Sleep”;
bit2 CFWKEN R/W 0
0: to disable CF pulse output to wake up the system from
“Sleep”.
1: to enable IO wakeup event on either pin “WAKEUP4” (P0.3)

or “WAKEUP3” (P0.2);
Bit1 IOP0 R/W 0
ot
0: to disable IO wakeup event on either pin “WAKEUP4”
(P0.3) or “WAKEUP3” (P0.2).
1: IO event wakes up but not reset the system. After wakeup,

CPU keeps on executing programs; all circuits go back where
the system entered the sleeping state, but “bit[2:1]”
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Bit0 IORSTN R/W 0 (“SLEEP1” and “SLEEP0”) and “bit[6:5]” (“FWC” and
“FSC”) are cleared.
0: IO event wakes up and reset the system. After wakeup, the

system goes to OSC state.
Table 5-6 Set RTC Wake-Up Interval

Va
SFR 0x96, RTC Wake-up Interval Register, INTRTC
Bit Default R/W Description
bit[7:3] 0 R/W
000: 1 second; 001: 1 minute; 010: 1 hour; 011: 1 day; 100:

bit[2:0] RTC<2:0> 0 R/W
500ms; 101: 250ms; 110: 125ms; 111: 62.5ms.
Table 5-7 RTC Seconds Wake-up Interval Configuration Register (SECINT, SFR 0xDF)
SFR 0xDF, R/W, RTC Seconds Wake-up Interval Configuration Register, SECINT
Bit7 R/W 0 Reserved

V98XX Datasheet
It is mandatory to set register “INTRTC” (SFR 0x96) to “0x07”, and then

Bit6 R/W 0 set this bit to ‘1’ to set interval in unit of second in “bit[5:0]” of this
register.
To set interval in unit of second for RTC to wake up the system from
“Sleep”. The actual wakeup interval is equal to (bit[5:0]+1) seconds, of
Bit[5:0] R/W 0 which “bit[5:0]” can be set to ‘1’ ~ ‘63’ (Decimal).
Setting these “bit[5:0]” to ‘0’ (Decimal) forces the interval to be 62.5

ms.
h
ec
ot
ng
Va

V98XX Datasheet
6.Clock
In V98XX, there are three clock generation circuits:
- RC oscillator circuit: To generate an RC clock (“RCCLK”). This circuit stops running only when
the chip is powered off.
- Crystal oscillator circuit: To generate an OSC clock (“OSCCLK”). Generally, this circuit stops
running only when the chip is powered off, but it also will stop running in some special
circumstances. This circuit is monitored by the OSC monitoring circuit that is sourced by RC clock.
When this crystal oscillator circuit stops running, the RC clock will replace the OSC clock to source
all circuits that are sourced by the OSC clock, and the monitoring circuit will stimulate the crystal
oscillator circuit until it runs again.
h
- Phase-locked loop (PLL) circuit: To generate a PLL clock (“PLLCLK”). The PLL locks onto a
multiple of the “OSCCLK” frequency to provide a stable clock: “PLLCLK”. This circuit can be
disabled.
ec
The above three clocks can work as the clock sources for the functional units:
- Clock 1 (“CLK1”, “MCUCLK”) provides clock pulses for MCU (Including CPU, RAM, Flash memory,
interrupt circuits, timers/UART serial interfaces, GPSI, and IO ports). The OSC clock and PLL clock
can be the optional source for “CLK1”. This clock is enabled by default, and it can be disabled.
ot
- Clock 2 (“CLK2”, “MTCLK”) provides clock pulses for the energy metering architecture. The OSC
clock and PLL clock can be the optional source for “CLK2”. This clock is enabled by default, and it
can be disabled.
- Clock 3 (“CLK3”, “LCDCLK”) provides clock pulses for the LCD driver. The OSC clock is the source
of this clock, and this clock is enabled by default, and it can be disabled only when PLL clock is
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selected as the source for “CLK1” and “CLK2”.
- Clock 4 (“CLK4”, “WDTCLK”) provides clock pulses for WDT. The RC clock is the source of this
clock. This clock is disabled and enabled together with “CLK1”.
- Clock 5 (“CLK5”, “RTCCLK”) provides clock pulses for RTC. The OSC clock is the source of this
clock. This clock cannot be disabled.
Va
Figure 6-1 illustrates the clock system architecture of V98XX.

V98XX Datasheet
Normal Operation: Sleep/Wakeup
CtrlCLK, 0x2867 SysCtrl, SFR 0x80
ADCLKSEL<1:0>
MCUCLKSEL<1:0>
MEACLKSEL<1:0>
PLLPDN MCUFRQ MEAFRQ
x1 819.2KHz
x2 1.6384MHz
x4 3.2768MHz
x8 6.5536MHz ON
CLK1: MCUCLK, clock
PLL MCUCLK
MCU_PLL source for MCU and its
1
OFF SLEEP1 – SFR 0x80.2 peripherals (including CPU,
SLEEP0 – SFR 0x80.1 RAM, Flash, interrupt
circuits, timers, UART,
0 GPSI and GPIO ports)
OSC x1 204.8KHz X4 x1 819.2KHz
x2 409.6KHz X8 x2 1.6384MHz
x4 819.2KHz x4 3.2768MHz
1 ON
Monitoring/
Stimulating MTCLK
Circuit
MT_PLL 1 CLK2: clock source for the
0 OFF PMG – SFR 0.80.4 energy metering
architecture (MTCLK).
RC 0
h
CLK3: clock source for the
LCDG – SFR 0.80.3 LCD driver (LCDCLK).
CLK5: clock source for the

RTC.
ec
SLEEP1 – SFR 0x80.2 CLK4: clock source for the
SLEEP0 – SFR 0x80.1 WDT.
FWC，SFR 0x80.6
FSC，SFR 0x80.5
Quick Operation: Sleep/Wakeup

ot
Figure 6-1 Clock System Architecture
6.1. RC Clock
ng
In V98XX, there is an embedded RC oscillator circuit. It can generate an independent 32-kHz RC clock.
It is the clock source for Clock 4 (“CLK4”) that provides clock pulses for WDT. The RC oscillator circuit
will not stop running until the chip is powered off, but “CLK4” can be enabled or disabled together with
“CLK1”.
There is a circuit monitoring the crystal oscillation and stimulating the oscillator to run again when it
stops working. This circuit is sourced by the RC clock. When the crystal oscillator circuit stops running,
Va
the RC clock will immediately replace it to be the clock source for all circuits that are sourced by OSC
clock. Users can read bit “OSC” (“bit7” of “ANState”, 0x286B) to detect whether the crystal stops
running and has been replaced by RC clock to source all circuits.
6.2. OSC Clock

In V98XX, there is an embedded oscillator circuit with fixed capacitance of 12.5 pF. Connect this circuit
to a 32768-Hz crystal around the pins “CTO” and “CTI” to compose a crystal oscillator circuit to generate
a 32768-Hz OSC clock, an optional clock source for “CLK1”, “CLK2”, “CLK3”, and “CLK5”. Users can
configure the register “P20FS” (0x28C9) to measure the OSC clock waveform via pin “P2.0”. The clock
frequency can be adjusted finely via configuring register “CtrlCry1” (0x2860) for the resistance and
capacitance in the embedded oscillator circuit or connecting some additional capacitors around pins “CTO”
and “CTI”. If RTC is used, bit “XTRSEL<2:0>” (“bit[2:0]” of “CtrlCry1”, 0x2860) must be set to

V98XX Datasheet
“0b011”. It consumes 0.6 μA by default.
Generally, this circuit will not stop running until the chip is powered off, but some factors may cause
the oscillator circuit to stop running. There is a circuit monitoring the crystal oscillation and stimulating
it to run again when it stops working. This circuit is sourced by the RC clock. When the crystal oscillator
circuit stops running, the RC clock will immediately replace it to be the clock source for all circuits that
are sourced by OSC clock. Users can read bit “OSC” (“bit7” of “ANState”, 0x286B) to detect whether
the crystal stops running and has been replaced with RC clock to source all circuits.
6.3. PLL Clock

The PLL circuit locks onto a multiple of the OSC clock frequency to provide some stable clock pulses,
h
“MEA_PLL”, “MCU_PLL”, and “ADC_PLL”, for the energy metering architecture, MCU and its
peripherals, and ADCs.
Start MCU and then enable the PLL circuit. When the PLL circuit is disabled, it will output the 32768-
ec
Hz OSC clock.
Users can enable the PLL circuit, and select the PLL clock as the source for “CLK1” and “CLK2” by
following the steps:
1. Access to the register “CtrlCLK” (0x2867) to enable the PLL circuit, and configure the frequency of
“MCUCLK” and “MTCLK”;
ot
2. Wait for the configuration till PLL has locked. MCU can access to the register “PLLLCK” (SFR 0xA3)
and read the bit “PLLLCK” to detect the state of the PLL circuit.
3. When the PLL circuit has locked, set the bit “MCUFRQ” or “MEAFRQ” (“bit0” or “bit7” of “SysCtrl”,
SFR 0x80) to ‘1’ to select the PLL clock as the source for “CLK1” or “CLK2”. This duration spends
ng
one PLL clock cycle only.
Users must follow the steps to reconfigure the “MTCLK” frequency or “MCUCLK” frequency when PLL
circuit is enabled:
1. Access to the register “SysCtrl” (SFR 0x80) to select the OSC clock as the source for “CLK1” or
“CLK2”;
Va
2. Access to the register “CtrlCLK” (0x2867) to adjust the frequency of “MTCLK” or “MCUCLK”;
3. Access to the register “SysCtrl” (SFR 0x80) to select the PLL clock as the source for “CLK1” or
“CLK2”.
V98XX is 50/60Hz-power-line supportive. By default the chip is applied for 50Hz-power-line. Users can
set the bit “PLLSEL” (“bit5” of “CtrlPLL”, 0x2868) to ‘1’ to configure the chip for the application in 60-
Hz power grid. The PLL clock frequency in 60-Hz power grid is 1.2 times of that in 50-Hz power grid. In
60-Hz power grid, the parameters related to the clock frequency, such as the baud rate and timers, must
be reconfigured. If not specifically noted, all information related to the clock frequency in this datasheet
will be applied to 50-Hz power grid only.
In the full-speed operation, the “MCUCLK” frequency is 13.1072 MHz, “MTCLK” frequency is 3.2768
MHz, and “ADCCLK” frequency is 819.2 kHz which is a quarter of “MTCLK” frequency. The typical load
current in the full-speed operation is 5.5 mA.

V98XX Datasheet
6.4. Switching Source for CLK1 and CLK2

In V98XX, there are two methods to switch the source for “CLK1”, and only one method to switch the
source for “CLK2”.
- Normal operation. In this mode, MCU needs to access some registers to select the clock source
for “CLK1” or “CLK2”, and/or to disable/enable the clock;
- Quick operation. In this mode, only one register is needed by MCU to access to trigger the hardware
to enable/disable the PLL circuit, select the source for “CLK1”, and/or enable/disable “CLK1”. If
this method is used to disable “CLK1”, the system will enter “Sleep” state, but not “Deep Sleep”
state. If the chip is used for a low-power application, this method will be recommended.
h
6.4.1. Normal Operation
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6.4.1.1. Switch Source for CLK1 and Disable CLK1
When the RSTn pin reset, POR/BOR, or WDT overflow reset occurs, the analog control registers and
the register “SysCtrl” (SFR 0x80) are reset to their default states, which means the PLL circuit is
disabled and “CLK1” is enabled and sourced by the OSC clock. After reset, access the analog control
ot
registers to enable the PLL circuit and configure the frequency of “MCUCLK”, and then set the bit
“MCUFRQ” (“bit0” of “SysCtrl”, SFR 0x80) to ‘1’ to select the PLL clock as the source for “CLK1”.
Only one OSC clock cycle is needed for all the above processes.
It is mandatory to enable the PLL circuit before writing ‘1’ to the bit “MCUFRQ” to select the source for
ng
“CLK1”. When “CLK1” is sourced by the PLL clock, the PLL clock frequency will change to 32768 Hz
automatically if the PLL circuit is disabled anomaly, but the bit “MCUFRQ” is still read out as ‘1’. In this
condition, MCU must read the bit “PLLLCK” (“bit0” of “PLLLCK”, SFR 0xA3) to detect the state of the
PLL circuit.
When “CLK1” is sourced by the PLL clock, clear the bit “MCUFRQ” (“bit0” of “SysCtrl”, SFR 0x80)
to select the OSC clock as the source for “CLK1”. This switchover needs no more than one OSC clock
Va
cycle. In this period, the write operation on the analog control registers is invalid. MCU can keep on
reading this bit immediately once it is cleared. If this bit is read out as ‘0’, it indicates the switchover is
finished.
When “CLK1” is sourced by the OSC clock, and the bit “PWRUP” (“bit0” of “Systate”, SFR 0xA1)
is read out as ‘0’, write ‘1’ to the bit “SLEEP0” or “SLEEP1” (“bit1” or “bit2” of “SysCtrl”, SFR 0x80)
to disable “CLK1” to force the system to enter “Deep Sleep” or “Sleep” state. When “CLK1” is disabled,
MCU, including CPU, RAM, Flash memory, interrupt circuits, timers, UART interfaces, and GPIO ports, will
stop working.
6.4.1.2. Switch Source for CLK2 and Disable CLK2
When the RSTn pin reset, POR/BOR, or WDT overflow reset occurs, the analog control registers and
the register “SysCtrl” (SFR 0x80) will be reset to their default states, which means the PLL circuit is

V98XX Datasheet
disabled; “CLK2” is enabled and sourced by the OSC clock. After the reset, access to the analog control
registers to enable the PLL circuit and configure the frequency of “MTCLK”, and then set the bit
“MEAFRQ” (“bit7” of “SysCtrl”, SFR 0x80) to ‘1’ to select PLL clock as the source for “CLK2”. Only
one OSC clock cycle is needed for all the above process.
It is mandatory to enable the PLL circuit and then to write ‘1’ to the bit “MEAFRQ” to select the source
for “CLK2”. When “CLK2” is sourced by the PLL clock, PLL clock frequency will change to 32768 Hz
automatically if the PLL circuit is disabled anomaly, but the bit “MEAFRQ” is still read out as ‘1’. In this
condition, MCU must read the bit “PLLLCK” (“bit0” of “PLLLCK”, SFR 0xA3) to detect the state of the
PLL circuit.
When “CLK2” is sourced by PLL clock, clear the bit “MEAFRQ” (“bit7” of “SysCtrl”, SFR 0x80) to
select the OSC clock as the source for “CLK2”. This switchover needs no more than one OSC clock
cycle. In this period, the write operation on the analog control registers is invalid. MCU can keep on
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reading this bit immediately once it is cleared. When this bit is read out as ‘0’, it indicates the switchover
is finished.
When “CLK2” is sourced by the OSC clock, write ‘1’ to the bit “PMG” (“bit4” of “SysCtrl”, SFR 0x80)
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to disable “CLK2”. When “CLK2” is disabled, the energy metering architecture will stop working.
6.4.2. Quick Operation

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This mode is applied to disable/enable the PLL circuit, select the source for “CLK1” and enable/disable
“CLK1”. In this mode, only the register “SysCtrl” (SFR 0x80) needs to be accessed.
When the RSTn pin reset, POR/BOR, WDT overflow reset, power recovery event, or IO/RTC wakeup
event occurs, the bits “FWC” and “FSC” (“bit6” and “bit5” of “SysCtrl”, SFR 0x80) are reset to 0s.
So the program determines the state of the system, including the PLL circuit and the clock source for
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“CLK1”.
Clear the bit “FSC”, and then write ‘1’ to the bit “FWC”, to enable the PLL circuit and select the PLL
clock as the source for “CLK1” automatically. In this condition, the PLL clock frequency is 3.2768 MHz.
The source for “CLK1” will be switched to PLL clock immediately once ‘1’ is written to the bit “FWC”.
When the bit “PWRUP” (“bit0” of “Systate”, SFR 0xA1) is read out as ‘0’, write ‘1’ to the bit “FSC”
whatever the bit “FWC” is, to select the OSC clock to be the source for “CLK1”, to disable the PLL
Va
circuit, to disable “CLK1”, and to force the system to enter the “Sleep” state.
6.4.3. Normal Operation vs. Quick Operation
When the RSTn pin reset, POR/BOR, WDT overflow reset, power recovery event, or IO/RTC wakeup
event occurs, the system will get into a temporary state in which the OSC clock is used as the clock
source for “CLK1” and the energy accumulation unit can accumulate a constant only. In this state, the
system consumes some power that should be diminished for the low-power-consumption applications.
In the power-down state, the process of disabling the circuits consumes some power that should be also
diminished.
In the normal operation, applications need to access analog control registers to get the system out of
the temporary state or to disable the circuits in the power-down state. But in the quick operation, only

V98XX Datasheet
the bits “FSC”/“FWC” need to be accessed. So, completing the above implementations in the quick
operation is preferred.
But, as stated above, the clock source switchover in the normal operation and quick operation may
affect each other:
- If the bits “FSC”/“FWC” are set to “0b01”, the configuration of the register “CtrlCLK” (0x2867)
and the bit “MCUFRQ” (“bit0” of “SysCtrl”, SFR 0x80) cannot be activated, and the PLL clock
frequency holds 3.2768 MHz.
- If the bit “MCUFRQ” is read out as ‘1’, clearing the bits “FSC”/“FWC” cannot switch the clock
source for “CLK1”.
To prevent MCU from the mis-operation, MCU can combine both methods, the combination operation:
To enable the PLL circuit and switch the source for “CLK1” in the quick operation to lower the power
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consumption; and then, to hold the PLL clock frequency in the normal operation.
FWC = 1; // Turn on PLL, and switch the clock source to PLL clock
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MCUFRQ = 1; // when PLL clock is the source for Clock 1
In the following table, the normal, quick, and combination operations are compared.
Table 6-1 Comparing Normal, Quick, and Combination Operation
Quick Combination
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Operation Normal Operation
Operation Operation
Access the analog control

Enable PLL, and switch the source registers, enable the PLL FWC = 1
circuit. FWC = 1
for CLK1 to PLL clock. MCUFRQ = 1
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MCUFRQ = 1;
MCUFRQ = 0;
Switch source for CLK1 to OSC clock, while(MCUFRQ == 1){;}

MCUFRQ = 0
disable PLL circuit, and disable access the analog control FSC = 1
CLK1. FSC = 1
registers, disable PLL circuit.
Va
SLEEP0 = 1;
The arrow in the following figure indicates the process from the IO wake-up event to completing the
clock source switchover of “CLK1” to the 3.2768-MHz PLL clock, in the quick operation or combination
operation, which lasts 800 μs ~ 900 μs, including the time to reset, to execute the initial long jump
instruction, and to write ‘1’ into “FWC”.

V98XX Datasheet
h
ec
Figure 6-2 Enabling PLL Circuit and Clock Source Switchover to PLL in Quick Operation
The arrows in the following figure indicate the process from the clock source switchover of “CLK1” to
“OSC” clock to disabling “CLK1”, in the quick or combination operation, which lasts less than 30 μs.
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Va
Figure 6-3 Clock Source Switchover to OSC, Disabling PLL Circuit, Disabling CLK1 in Quick
Operation
6.5. Registers
Table 6-2 Clock Switchover Control Register (SysCtrl, SFR 0x80)

V98XX Datasheet
SFR 0x80, R/W, Clock Switchover Control Register, SysCtrl
To select the clock source for “CLK2”
0: OSC clock;
bit7
0 1: PLL clock.
MEAFRQ
This bit is writable and readable. Configure this bit to switch the clock source for
“CLK2”, and read this bit to acquire the current clock source for “CLK2”.
Only when the bit “FSC” is cleared will the configuration of “FWC” be activated.
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When the bit “FSC” is cleared, write ‘1’ to this bit to enable the PLL circuit to
bit6 start running and output a 3.2768-MHz PLL clock, and to select this clock to be
0 the clock source for “CLK1”.
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FWC
When the bit “FSC” is cleared, write ‘1’ to the bit “FWC”, the clock setting will
be locked. Writing ‘0’ to the bit “FWC” will unlock the clock setting without
switching the clock.
Write ‘1’ to this bit to select the OSC clock as the clock source for “CLK1”, to
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disable the PLL clock, and to disable “CLK1”.
bit5
0 If the bit “PWRUP” is read out as ‘0’, setting this bit to ‘1’ will make the system
FSC
enter “Sleep” state, but not “Deep Sleep”. If the bit “PWRUP” is read out as
‘1’, setting this bit to ‘1’ cannot force the system enter the “Sleep” state.
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bit4
0 Set this bit to ‘1’ to stop “CLK2”. By default this clock is running.
PMG
Set this bit to ‘1’ to stop “CLK3”. By default this clock is running.
bit3
0 Only when the PLL clock is selected as the clock source for “CLK1” and “CLK2”,
LCDG
“CLK3” can be stopped.
Va
bit2 When the bit “PWRUP” is read out as ‘0’, write ‘0’ to the bit “MCUFRQ”, and
then:
SLEEP1
0 - Set “SLEEP1” and “SLEEP0” to “0b11” or “0b01” to stop “CLK1”

bit1 (Together with “CLK4”) and force the system entering the “Sleep” state.
SLEEP0 - Set “SLEEP1” and “SLEEP0” to “0b10” to stop “CLK1” (Together with
“CLK4”) and force the system entering the “Deep Sleep” state.

V98XX Datasheet
0: OSC clock;
bit0
0 1: PLL clock.
MCUFRQ
When bit “IORSTN” (“bit0” of “IOWK”, SFR 0xC9) is set to ‘1’, any wakeup event can wake up the
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system from the sleeping state but cannot reset the system. After wakeup, CPU keeps on executing
programs; all circuits hold their states where they were before sleeping; only “bit[2:1]” (“SLEEP1”
and “SLEEP0”) and “bit[6:5]” (“FWC” and “FSC”) are cleared.
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Table 6-3 Peripheral Control Register 0 (PRCtrl0, 0x2D00)
0x2D00, R/W, Peripheral Control Register 0, PRCtrl0

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Bit7 PWMCLK R/W 0 To enable or disable PWM clock generation circuit.
1: disable; 0: enable.
Bit6 GPSI R/W 0 To enable or disable GPSI.

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1: enable; 0: disable.
Bit5 P10 R/W 0 To enable or disable GPIOs Group P10.
Bit4 P9 R/W 0 To enable or disable GPIOs Group P9.

Va
Bit3 P0P8 R/W 0 To enable or disable GPIOs Group P0~P8.
Bit2 EUART2 R/W 0 To enable or disable EUART2.
Bit1 EUART1 R/W 0 To enable or disable EUART1.
Bit0 TimerA R/W 0 To enable or disable TimerA.

V98XX Datasheet
Table 6-4 Peripheral Control Register 1 (PRCtrl1, 0x2D01)
Bit7 UART5 R/W 0 To enable or disable UART5.
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Bit3 ExInt5 R/W 0 To enable or disable Interrupt 11.
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Table 6-5 Register 1 to Adjust OSC Clock Frequency
0x2860, R/W, Crystal Control Register 1, CtrlCry1

Va
The fixed capacitance in the crystal oscillator circuit is 12.5 pF.

Bit4 CSEL 0
Set this bit to ‘1’ to decrease the capacitance by 2.35 pF.
Bit3 Reserved 0 These bits must hold their default values for proper operation.

V98XX Datasheet
To adjust the resistance of the resistors in the internal crystal

oscillator circuit. When RTC is used, these bits must be set to
“0b011”, and the oscillation monitoring circuit must be enabled.
Set bit “XTRSEL<2>” to ‘1’ to increment the resistance to P end

by 400 kΩ.
Bit[2:0] XTRSEL<2:0> 0
“XTRSEL<2:0>” to adjust the resistance to N end:
00/01: Hold the resistance to N end.
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10: Increment by 128 kΩ.
11: Increment by 64 kΩ.
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Table 6-6 Register 2 to Adjust OSC Clock Frequency
Set this bit to ‘1’ to enable current leakage detection on

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BandGap circuit. When this bit is set to ‘1’, an interrupt will be
Bit7 REFLKEN 0
triggered when the reference voltage is lowered by more than
3% caused by the current leakage.
This bit must hold its default value for proper operation. By
Bit6 Reserved 0
default this function is disabled.
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bit5 XRESETEN 0 Set this bit to ‘1’ to enable the oscillation monitor.
To select the bias current input to the comparator CB
Bit4 CMPIT 0 0: 20 nA;
1: 200 nA.
Va
To select the analog input to the comparator CB
00: M2 for positive input; REF_LP for negative input;

bit[3:2] CMPSSELB<1:0> 0
10/11: M2 for positive input; M1 for negative input.
Table 6-7 PLL Clock State Register (PLLLCK, SFR 0xA3)
SFR 0xA3, R, PLL Clock State Register, PLLLCK
bit[7:1] Reserved 0

V98XX Datasheet
SFR 0xA3, R, PLL Clock State Register, PLLLCK
When this bit is read out as ‘1’, it indicates that the PLL has locked
bit0 PLLLCK 0
onto a certain frequency.
Table 6-8 Register 1 to Adjust Clock Frequency of Specific Functional Blocks
0x2867, R/W, Clock Control Register, CtrlCLK
To enable the PLL circuit
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0: disable;
bit7 PLLPDN 0
1: enable.
Enable the BandGap circuit, and then enable the PLL circuit.
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To enable the BandGap circuit
0: disable;
bit6 BGPPDN 0
1: enable.
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To configure the sampling frequency of the oversampling

ADCs (“ADCCLK”).
Base: 204.8 kHz.

bit[5:4] ADCLKSEL<1:0> 0
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00: ×1;
01: ×2;
10: ×4.
To configure the clock frequency for the energy metering

architecture (“MTCLK”).
Va
Base: 819.2 kHz.

bit[3:2] MEACLKSEL<1:0> 0
00: ×1;
01: ×2;
10: ×4.

V98XX Datasheet
To adjust the clock frequency for MCU (“MCUCLK”).
Base: 819.2 kHz.
00: ×1;
bit[1:0] MCUCLKSEL<1:0> 0
01: ×2;
10: ×4;
11: ×8.
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Table 6-9 Register 2 to Adjust Clock Frequency of Specific Functional Blocks
0x2868, R/W, PLL Control Register, CtrlPLL
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When the bit “MCU13M” is set to ‘1’, set this bit to ‘1’ to double
bit7 MCU26M 0
“MCUCLK” frequency further.
bit6 MCU13M 0 Set this bit to ‘1’ to double “MCUCLK” frequency.

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Table 6-10 OSC Clock State Register
0x286B, R, Analog Circuits State Register, ANState

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To indicate the state of the OSC clock
0: The crystal is working.

bit7 OSC 0
1: The crystal stops running, and all the circuits, including PLL circuit,
sourced by the OSC clock now is being sourced by the internal RC
Va
clock.
Bit6 Reserved -
To indicate the output of the comparator CB
bit5 COMPB 0 1: the positive input is higher than the negative input;
0: the negative input is higher than the positive input.
bit[4:2] Reserved 5 It is read out as “0x5”.
bit[1:0] Reserved -

V98XX Datasheet
7.Power Management
V98XX has three system states according to the state of Clock 1:
 OSC state: When a reset event of Level 1 or Level 2 occurs, the system will go to the OSC state, in
which Clock 1 runs and is sourced by the OSC clock.
 Working state: The PLL circuit is enabled, and the PLL clock is used as the source for Clock 1.
 Sleeping state: When the bit “PWRUP” (“bit0” of “Systate”, SFR 0xA1) is cleared, select the
OSC clock as the source for Clock 1 and disable Clock 1, and then the system will enter the sleeping
state. By default, the chip will be woken up with reset and be forced to go back to the OSC state.
But when the bit “IORSTN” (“bit0” of “IOWK”, SFR 0xC9) is set to ‘1’, the chip will be woken up
without reset, which means the chip is woken up and goes back where it entered the sleeping state
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except that bits “SLEEP1”, “SLEEP0”, “FWC”, and “FSC” (“bits” of “SysCtrl”, SFR 0x80) are
cleared to 0s. The sleeping state is classified to 2 states: “Sleep” and “Deep Sleep”. An IO/RTC
wakeup event, CF pulse output, or a power recovery event can wake up the system from “Sleep”.
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An IO wakeup event or a power recovery event can wake up the system from “Deep Sleep”.
7.1. Power Consumption

In V98XX, there are a lot of functional units, some of which can be disabled, but others cannot. The
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power consumption of these units may be affected by the digital power supply or the clock frequency as
shown in Table 7-1.
Table 7-1 Factors Affecting Power Consumption of Each Unit

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Factors Affecting Power Consumption.

State When
Unit Stoppable?
Powered On Clock Operation Voltage (DVCC
Frequency Output)
LDO33 On No No No
Va
Digital Power
On No No No
Supply Circuit
OSC On No No No
MCU On Yes Yes Yes
REF_LP On No No No
RTC On No No No
PLL Off Yes No No
BandGap Off Yes No No

V98XX Datasheet
Factors Affecting Power Consumption.
State When
Unit Stoppable?
Powered On Clock Operation Voltage (DVCC
Frequency Output)
Power
On No No No
Supervisor
Temperature
Measurement Off Yes No No
Circuit
Battery Voltage
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Measurement Off Yes No No
Circuit
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COM/SEG
driver circuit
LCD Driver is disabled, Yes No No
and CLK3 is
running.
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ADCs Off Yes Yes No
Digital signal
Energy inputs are
Metering disabled, and Yes Yes No
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Architecture CLK2 is
running.
7.1.1. OSC State

Va
When a reset event of Level 1 or Level 2 occurs, the system will be reset to the OSC state. In this
state, LDO33 is enabled, OSC clock is used as the source for “CLK1”, and MCU runs.
Table 7-2 OSC State of System
Module State When Powered On Stoppable? State in OSC State
LDO33 On No On
Digital Power Supply Circuit On No On
OSC On No On
MCU On Yes On

V98XX Datasheet
Module State When Powered On Stoppable? State in OSC State
REF_LP On No On
RTC On No On
7.1.2. Working State
In the OSC state, enable the PLL circuit, select the PLL clock to work as the source for “CLK1”, and
then the system will enter the working state.
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In the working state, users can configure the MCU clock (“CLK1”) frequency, and enable the required
ADCs, the energy metering architecture, the LCD driver, and CPU and its peripherals according to the
application.
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In the working state, when the frequency of “CLK1” is set to 13.1072 MHz, that of “CLK2” is set to
3276.8 kHz, and sampling frequency of ADCs (“ADCCLK”) is set to 819.2 kHz, the system will run at full
speed. When the system works normally, the power consumption of the global system will be determined
by the number of enabled ADCs, and the configuration of the metering architecture and the LCD driver.
Table 7-3 Power Consumption When System Working at Full Speed

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Module State When Powered on Stoppable? Current State
LDO33 On No On
Digital Power Supply

On No On
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Circuit
OSC On No On
REF_LP On No On
RTC On No On
Va
PLL Off Yes On
BandGap Off Yes On
Power Supervisor On No On
Temperature Measurement
Off Yes Off
Circuit
Battery Voltage
Off Yes Off
Measurement Circuit

V98XX Datasheet
Module State When Powered on Stoppable? Current State
4 ADCs are
ADC Off Yes
enabled.
Energy Metering Digital signal inputs are disabled, and 4 channels are
Yes
Architecture CLK2 is running. enabled.
COM/SEG driver circuit is disabled, On, no display

LCD Driver Yes
and CLK3 is running. screen
MCU On Yes On
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Power Consumption 5.5 mA
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7.1.3. Sleeping State
When the bit “PWRUP” (“bit0” of “Systate”, SFR 0xA1) is read out as ‘0’, switch the source for
“CLK1” to the OSC clock and then disable “CLK1”, then the system will go to the sleeping state.
There are two types of sleeping state: “Sleep” and “Deep Sleep”.
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In “Sleep” or “Deep Sleep”, RTC holds on; the memories, CPU and its peripherals stop working; but
the LCD driver and the energy metering architecture will not stop working until they are disabled. If
ADCs, PLL circuit, LCD driver, and energy metering architecture are disabled, and IOs are set to “output,
disabled; input, masked” before entering “Sleep” or “Deep Sleep”, the system consumes the lowest
power.
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In “Sleep”, if IO/RTC wakeup event, CF pulse output, or power recovery event occurs, the system will
be woken up and go back to the OSC state by default. In “Deep Sleep”, only an IO wakeup event or
power recovery event can wake up the system and reset it to the OSC state by default. When the bit
“IORSTN” (“bit0” of “IOWK”, SFR 0xC9) is set to ‘1’, any wakeup event can wake up the system from
“Sleep” or “Deep Sleep” only but cannot reset the system to the OSC state. In this condition, the chip
will go back where it entered the sleeping state, except that “bit[6:5]” (“FWC” and “FSC”) and
Va
“bit[2:1]” (“SLEEP1” and “SLEEP0”) will be cleared to 0s.
If the pin “WAKEUP1”, “WAKEUP2”, “WAKEUP3”, or “WAKEUP4” is set to “Input enabled”

before the system enters “Sleep” or “Deep Sleep”, a transition (Either high-to-low or low-to-high, with
more than 4 OSC clock cycles on both levels) on the pin in “Sleep” or “Deep Sleep” can wake up the
system. By default ports “P0.2” and “P0.3” are not used for the wakeup event input. Users must
configure bit “IOP0” (“bit1” of “IOWK”, SFR 0xC9) to ‘1’ to set both pins for the wakeup input. When
the bit “IO” (“bit3” of “Systate”, SFR 0xA1) is set to ‘1’, read states of bits “P14WK” (“bit0” of
“IOWKDET”, SFR 0xAF), “P02WK” (“bit1” of “IOWKDET”, SFR 0xAF) and “P03WK” (“bit2” of
“IOWKDET”, SFR 0xAF) to detect which IO wakeup event woke up the chip from the sleeping state.
If both bit “RTC” (“bit2” of “Systate”, SFR A1) and “CFWK” (“bit3” of “IOWKDET”, SFR 0xAF)
are set to 1s, it indicates that the system was woken up by the CF pulse output. If the bit “RTC” is set
to ‘1’, but “CFWK” is cleared, it indicates that an RTC wakeup event occurred.

V98XX Datasheet
7.1.3.1. Sleep/Wake-Up
In V98XX, there are two methods to wake up the system from the sleeping state or make the system
go to the sleeping state: Normal method and quick method.
1. Normal Method
The normal method for wakeup/sleep switchover is totally controlled by the program.
When the PLL clock is enabled and works as the source for the MCU clock (“CLK1”), users can follow
steps illustrated in Figure 7-1 to force both MCU and energy metering architecture to go to the sleeping
state, or force MCU to go to the sleeping state only but leave the energy metering architecture to
accumulate a constant for the energy metering.
h
ec
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Va

V98XX Datasheet
ON/OFF=0
(bit7, 0x2C1E)
LCDG=1
(bit3, SFR 0x80)
(Optional)
PREN=0 (bit4, 0x2878)
EGYEN=0 (bit3, 0x287D)

(Optional)
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Clear MEAFRQ Notes:
(bit7, SFR 0x80) Take the value of “MEAFRQ” as the condition for
the while loop, and count the while loop cycles to
≤1 OSCCLK period detect whether it Is the time to terminate the loop.
MEAFRQ=1 In this case, “CLK1” is sourced by PLL clock, so
ec
users can estimate a value based on the “MCUCLK”
frequency to detect the counts. When the “MCUCLK”
Read MEAFRQ frequency is 13.1072 MHz, about ‘50’ assembly
(bit7, SFR 0x80) instructions are needed to terminate the loop. If one
while loop cycle needs 5 instructions, the value to
detect the counts should be ‘10’.
MEAFRQ=0
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PMG=1
(bit4, SFR 0x80)
(Optional)
Notes:
Clear MCUFRQ
Take the value of “MCUFRQ” as the condition For
(bit0, SFR 0x80)
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the while loop, and count the while loop cycles to

detect whether it Is the time to terminate the loop.
≤1 OSCCLK period In this case, “CLK1” is sourced by PLL clock, so
MCUFRQ=1
frequency to detect the counts. When the
Read MCUFRQ “MCUCLK” frequency is 13.1072 MHz, about 50
(bit0, SFR 0x80) assembly instructions are needed to terminate the
loop. If one while loop cycle needs 5 instructions, the
value to detect the counts should be ‘10’.
MCUFRQ=0
Va
PLLPDN=0, BGPPDN=0
(bit7, bit6, 0x2867)
Write SLEEP1/SLEEP0
(bit2, bit1, SFR 0x80)
Sleeping
Figure 7-1 Go to Sleeping State (Normal Method, Disable PLL Clock)


V98XX Datasheet
steps illustrated in Figure 7-2 to force MCU to go to the sleeping state only but leave the energy metering
architecture work normally.
ON/OFF=0
(bit7, 0x2C1E)
LCDG=1
(bit3, SFR 0x80)
(Optional)
Notes:
Clear MCUFRQ Take the value of “MCUFRQ” as the condition For
(bit0, SFR 0x80) the while loop, and count the while loop cycles to
detect whether it is the time to terminate the loop.
≤1 OSCCLK period In this case, “CLK” 1 is sourced by PLL clock, so
MCUFRQ=1
users can estimate a value based on “MCUCLK”
h
frequency to detect the counts. When “MCUCLK”
frequency is 13.1072 MHz, about 50 assembly
Read MCUFRQ instructions are needed to terminate the loop. If one
(bit0, SFR 0x80) while loop cycle needs 5 instructions, the value to
detect the counts should be ‘10’.
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MCUFRQ=0
Write SLEEP1/SLEEP0
(bit2, bit1, SFR 0x80)
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Sleeping
Figure 7-2 Go to Sleeping State (Normal Method, PLL Clock Holds on)
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Table 7-4 Configuration for Sleeping State
Register SLEEP1 (Bit 2) SLEEP0 (Bit1) System State
0 1 Sleep
SysCtrl
1 1 Sleep
Va
SFR 0x80
1 0 Deep Sleep
In “Sleep” or “Deep Sleep”, when IO/RTC wakeup event, CF pulse output, or power recovery event
occurs, the system will be woken up from the sleeping state. If the wakeup with reset mode is applied,
after a reset, users should use the normal operation to enable the PLL circuit and select it as the source
for “CLK1” to make the system go to the working state.
2. Quick Method
In V98XX, the quick method can force the system to go to “Sleep”, but not “Deep Sleep”.
steps illustrated in Figure 7-3 to force both MCU and energy metering architecture to go to “Sleep”, or
force MCU to go to “Sleep” only but leave the energy metering architecture to accumulate a constant
for energy metering. In this case, PLL clock will be disabled definitely.

V98XX Datasheet
ON/OFF=0
(bit7, 0x2C1E)
LCDG=1
(bit3, SFR 0x80)
(Optional)
PREN=0(bit4, 0x2878)
EGYEN=0
(bit3, 0x287D)
(Optional)
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Notes:
Clear MEAFRQ Take the value of “MEAFRQ” as the condition For
(bit7, SFR 0x80) the while loop, and count the while loop cycles to
detect whether it is the time to terminate the loop.
ec
≤1 OSCCLK period In this case, “CLK1” is sourced by PLL clock, so
MEAFRQ=1
frequency to detect the counts. When the
“MCUCLK” frequency is 13.1072 MHz, about 50
Read MEAFRQ
assembly instructions are needed to terminate the
(bit7, SFR 0x80)
loop. If one while loop cycle needs 5 instructions, the
value to detect the counts should be ‘10’.
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MEAFRQ=0
PMG=1
(bit4, SFR 0x80)
(Optional)
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Notes:
Setting “FSC” to ‘1’ can force the hardware to
Set FSC to 1
complete the following steps automatically:
(bit5, SFR 0x80)
1. To switch the clock source for “CLK1” from PLL
clock to OSC clock;
≤2 OSCCLK periods 2. To disable PLL and BandGap circuits;
3. TO clear bits “MCUCLK”, “MEACLK” and
“ADCLK”;
Sleep
4. TO force the system to go to “Sleep”.
Va
Figure 7-3 Go to Sleep (Quick Method)

In “Sleep”, IO/RTC wakeup event, CF pulse output, or power recovery event can wake up the system.
If the wakeup with reset mode is applied, users should use the quick operation to enable the PLL circuit
and switch the source for “CLK1” to make the system go to the working state.
7.1.3.2. Power Consumption in Sleeping State
The following table shows the power consumption in the sleeping state when the LCD driver is disabled.
Table 7-5 Power Consumption in Sleeping State

V98XX Datasheet
Module State When Powered On Stoppable?
Digital Power Supply Circuit On No
OSC On No
REF_LP On No
RTC On No
Power Supervisor On No
RC Oscillator On No
h
Total 12 μA (Max. 16.2 μA; Min. 7.8 μA)
ec
7.2. Registers
Table 7-6 Register for Clock Control

ot
0: OSC clock;
ng
bit7
0 1: PLL clock.
MEAFRQ
Only when the bit “FSC” is cleared, the configuration of “FWC” is activated.
Va
When the bit “FSC” is cleared, write ‘1’ to the bit “FWC” to enable the PLL circuit
bit6 to start running and output a 3.2768-MHz PLL clock, and to source “CLK1”.
0
FWC When the bit “FSC” is cleared, write ‘1’ to the bit “FWC”, the clock setting will
be locked. Writing ‘0’ to the bit “FWC” will unlock the clock setting without
switching the clock.
Write ‘1’ to this bit to select the OSC clock as the clock source for “CLK1”, to
disable the PLL clock, and to disable “CLK1”.
bit5
0 If the bit “PWRUP” is read out as ‘0’, setting this bit to ‘1’ will make the system
FSC
enter the “Sleep” state, but not “Deep Sleep”. If the bit “PWRUP” is read out
as ‘1’, setting this bit to ‘1’ cannot force the system to enter the “Sleep” state.

V98XX Datasheet
bit4 Set this bit to ‘1’ to stop “CLK2”.

0
PMG By default this clock is running.
Set this bit to ‘1’ to stop “CLK3”. By default this clock is running.
bit3
0 Only when the PLL clock is selected as the clock source for “CLK1” and “CLK2”,
LCDG
“CLK3” can be stopped.
bit2 When the bit “PWRUP” is read out as ‘0’, write ‘0’ to the bit “MCUFRQ”, and
h
then:
SLEEP1
0 - Set “SLEEP1” and “SLEEP0” to “0b11” or “0b01” to stop “CLK1”

(Together with “CLK4”) and force the system entering the “Sleep” state.
ec
bit1
SLEEP0 - Set “SLEEP1” and “SLEEP0” to “0b10” to stop “CLK1” (Together with
“CLK4”) and force the system entering the “Deep Sleep” state.
0: OSC clock;
ot
bit0
0 1: PLL clock.
MCUFRQ
ng
When the bit “IORSTN” (“bit0” of “IOWK”, SFR 0xC9) is set to ‘1’, any wakeup event can wake up
the system from the sleeping state without resetting the system. After wakeup, CPU keeps on
executing programs; all circuits hold their states where they were before sleeping; only “bit[2:1]”
(“SLEEP1” and “SLEEP0”) and “bit[6:5]” (“FWC” and “FSC”) are cleared.
Table 7-7 Register to Indicate Power Supply State

Va
Bit[7:6] Reserved.
Bit5 When this bit is read out as ‘1’, it indicates the system is reset by an event of
0 Level 1: POR/BOR, RSTn pin reset, or WDT overflow event. This bit will be cleared
POR when a reset event of other levels occurs.
Bit4 0 Reserved.
Bit3 When this bit is read out as ‘1’, it indicates the system is woken up from “Sleep”
0
IO or “Deep Sleep” by an IO wakeup event.

V98XX Datasheet
When this bit is read out as ‘1’, but bit “CFWK” (“bit3” of “IOWKDET”, SFR
0xAF) is cleared, it indicates the system is woken up from “Sleep” by the RTC
Bit2
0 wakeup event.
RTC/CF
If both this bit and bit “CFWK” are set to 1s, it indicates the system is woken up
from “Sleep” by the CF pulse wakeup event.
When the input voltage on pin “VDCIN” is lower than 1.0 V, this bit is read out
as ‘1’, indicating that the system is powered down. If the power down interrupt is
Bit1
h
0 enabled, an interrupt will be triggered when this bit is read out as ‘1’.
PWRDN
When the input voltage on pin “VDCIN” is higher than 1.1 V, this bit holds its
default value, indicating no power down event occurs.
ec
When the input voltage on pin “VDCIN” is higher than 1.1 V, this bit is read out
Bit0 as ‘1’, indicating that the system is powered up by the line power supply.
0
PWRUP When the input voltage on pin “VDCIN” is lower than 1.0 V, this bit holds its
default value, indicating the system is powered up by battery.
ot
ng
Va

V98XX Datasheet
8.Power Supply
V98XX supports 5-V or 3.3-V power input on the pin “VDD5”. The power supply is supervised
continuously. The internal analog circuits and general-purpose I/O (GPIO) ports are powered by the 3.3V
regulator circuit (3.3V-LDO), and the peripheral circuits are powered by the LDO33 output voltage; the
Vango metering architecture and PLL circuit are powered by the digital power supply circuit.
There is an internal power detection circuit in V98XX. By default this circuit is enabled. When the chip
is 3.3 V powered, users must set bit “PDDET” (“bit7” of “CtrlLDO”, 0x2866) to ‘1’ to disable this
circuit to protect the battery from the current leakage when a battery is connected. When the chip is 5
V powered, this bit must hold its default value.
h
BAT M Channel
Digital Power DVCC
ec
PLL Digital circuits*
4.7μF 0.1μF
VDD5
5V/3.6V
GPIO Analog circuits**
Peripheral
3.3V-LDO LDO33
VDCIN circuits
ot
4.7μF 0.1μF
* Digital circuits: Include CPU and its peripherals (UART interfaces,

Timers, interrupts, RAM, Flash memory, and so on),
RTC, Vango metering architecture (VMA), and so on.
** Analog circuits: Include ADC, voltage reference, temperature sensor,
ng
LCD driver, POR/BOR, RC oscillator, crystal oscillator,

power supply supervisor, and so on.
Figure 8-1 Power Supply Architecture

Note:
V98XX has an internal power supply detection circuit. The circuit is turned on by default. When
Va
the system is powered by a 3.3-V power source, users must set “PDDET” (“bit7”, “CtrlLDO”,
0x2866) to ‘1’ to disable the power detection circuit, or when a battery is connected, the battery
leakage may occur. The bit must be cleared when it is powered by 5-V power supply. By this way the
battery leakage risk will not exist.
8.1. 3.3-V Regulator Circuit (LDO33)

In V98XX, the analog circuits and the GPIO ports are powered by the 3.3-V regulator circuit (“LDO33”),
and the peripheral circuits are powered by the LDO33 output voltage. This LDO33 will not stop working
until the chip is powered off. The LDO33 output voltage can be configurable via bits “LDO3SEL”
(“bit[5:3]” of “CtrlLDO”, 0x2866).
This LDO33 has a driving capability of 30 mA. When the load current through the analog circuits and

V98XX Datasheet
the GPIO ports is less than 30 mA, the LDO33 output voltage holds 3.3 V; when the load current is higher
than 30 mA, the higher the load current is, the lower voltage the LDO33 will output.
It is recommended to decouple the pin “LDO33” externally with a ≥ 4.7 μF capacitor in parallel with
a 0.1-μF capacitor.
5 2
Decrease of LDO33 Output Voltage
Decrease of LDO33 Output

0
-2
-4
-5
Voltage (%)
When the external voltage is -6
higher than 3.3V, the LDO33 When the load current through the
-10 -8
(%)
outputs 3.3V voltage to protect analog circuit and IOs is higher than
-10 30mA, the increase of loading
the analog circuit performance
-15 -12
from disturbance of 5-V main current leads to the decrease of the
supply. -14 LDO33 output voltage.
-20
-16
-25 -18
0 10 20 30 40 50 60
h
2.5 3 3.5 4 4.5 5
External Voltage Input (V) Load Current (mA)
Figure 8-2 LDO33 Output and 5V Power Figure 8-3 LDO33 output and the Load
ec
Input Current
8.2. Digital Power Supply

In V98XX, the PLL clock generation circuit and the Vango metering architecture (VMA) are powered by
ot
the digital power supply circuit. When the digital power supply output is 200 mA, being lower than the
power input on the pin “VDD5”, it will output a stable voltage, avoiding the digital power fluctuation
caused by the variation of the power input. The digital power supply output is configurable via the bit
“LDOV2SEL” (“bit[2:0]” of “CtrlLDO”, 0x2866).
The digital power supply circuit has a driving capability of 35 mA. When the load current through the
ng
circuits is less than 35 mA, the digital power supply will be stable; when the load current is higher than
35 mA, the higher the load current is, the lower the digital power supply will be.
This power supply circuit will not stop working until the system is powered off.
It is recommended to decouple the pin “DVCC” externally with a ≥4.7 μF capacitor in parallel with a
0.1-μF capacitor.
Va
8.3. Power Supply Supervisor

In V98XX, the 5-V main power is input into the pin “VDCIN” after a resistive divider. The input voltage
on the pin “VDCIN” is monitored continuously by the power supply supervisor.
When the input voltage on the pin “VDCIN” is lower than 1 V, a power-down event will occur, the bit
“PWRDN” (“bit1” of “Systate”, SFR 0xA1) will be set to ‘1’, and a power-down interrupt will be
generated to CPU.

V98XX Datasheet
1.1V
1.0V
VDCIN
PWRUP
h
PWRDN
ec
Figure 8-4 Relationship between VDCIN Input Signal and States of Flag Bits PWRUP and
PWRDN
ot
8.4. Battery Supply
V98XX can be powered by batteries. Users can read the value of the flag bit “PWRUP” (“bit0” of
“Systate”, SFR 0xA1) to get the state of the power supply. When this bit is read out as ‘0’, it indicates
the input voltage on the pin “VDCIN” is lower than 1.0 V, which means the system is powered by the
ng
battery, or the power supply has been switched from 5-V power to the battery.
When the chip is powered by batteries, please note that the battery will get passive when it is reactive
for a long time. So users should set the bit “BATDISC” (“bit0” of “CtrlBAT”, 0x285C) to ‘1’ at an
interval to discharge the battery to protect them from passivation. During the battery discharge, the load
current is 3 mA, and the period for battery discharge should not be too long to save power. After discharge,
the bit “BATDISC” must be cleared.
Va

V98XX Datasheet
9.Comparator
CMPPDNB
M1
M2 CMPSSELB<1:0>
+ CB Interrupt
-
1.2V REF_LP
h
Figure 9-1 Comparator Architecture
ec
V98XX integrates one additional comparator CB to compare the analog signals:
 Positive signal input on pin “M1” and negative signal input on pin “M2”;
 Positive signal input on pin “M1” and negative signal from internal low power reference circuit
(REF_LP);
ot
 Positive signal input on pin “M2” and negative signal from internal low power reference circuit
(REF_LP).
When the RSTn pin reset, POR/BOR, or WDT overflow reset occurs, or the system is in “Sleep” or
“Deep Sleep” state, this comparator will stop running.
ng
When IE6=1 (“bit6” of “0x28A5”), EIE.3=1 (“bit3” of “SFR 0xE8”), and IE.7=1 (“bit7” of “SFR
0xA8”), the comparator interrupt will be enabled. In this state, the interrupt flag “IR6” (“bit6” of
“0x28A2”) will be set to ‘1’ when the output of the comparator changes, and the comparator will
generate an interrupt to CPU. After the interrupt service, users can read bit “COMPB” (“bit5” of
“0x286B”) to detect the comparison result of the input signals.
Table 9-1 Registers Related to Comparator CB

Va
To select the bias current input to the comparator

Bit4 CMPIT 0 CB 0: 20 nA;
1: 200 nA.
To select the analog input to the comparator CB

0x2861
00: M2 for positive input; REF_LP for negative
CtrlCry2
input;
01: M1 for positive input; REF_LP for negative
input;

V98XX Datasheet
To enable the comparator CB.

0x2864
bit5 CMPPDNB 0 0: Disable;
CtrlADC6
1: Enable.
To indicate the output of the comparator CB
0x286B 1: the positive input is higher than the negative

bit5 COMPB 0 input;
ANState
0: the negative input is higher than the positive
input.
h
ec
ot
ng
Va

V98XX Datasheet
10. Energy Metering

The energy metering architecture in V98XX has features:
 Four independent oversampling Σ/Δ ADCs: One voltage channel (U), two current channels (I), and
one multifunctional channel for various signal measurements.
 High metering accuracy:
- Less than 0.1% error on active energy metering over dynamic range of 5000:1.
- Less than 0.1% error on reactive energy metering over dynamic range of 3000:1.
- Less than 0.5% error on current and voltage RMS calculation over dynamic range of 1000:1.
h
 Providing measurements:
- Raw waveform and DC component of current/voltage signals
ec
- Instantaneous/Average and active/reactive power
- Positive/Negative and active/reactive energy
- Average apparent power
- Instantaneous/average current/voltage RMS

ot
- Line frequency
- Temperature with measurement accuracy of ±1°C
- Battery voltage, system voltage, and external voltage signals
 Two current inputs for active energy, or one current input for active and reactive energy
ng
 Programmable energy metering modes:
- Accumulating power, current RMS, or a constant for energy metering
- Accumulating energy at a configurable frequency
 Current detection, to lower power consumption

Va
 CF pulse output and interrupt with configurable pulse width
 Zero-crossing interrupt
 Programmable threshold for no-load detection
 Calibrating meters via software:
- Phase compensation supported, resolution 0.005°/lsb (min.), over a range of ±1.4°(min.)
- Gain calibration of RMS and power, and offset calibration of power
- Accelerating meter calibration when low current is applied.

V98XX Datasheet
Sign
CNT
Energy Acc_N
E1 Path GAIN E1 PWR CF1

DATAOM
AVG CF1
E1 PWR/s
Constant
Energy Acc_P
PWR
M ADC Decimation DATADM
CNT
AVG DATAADM
Temperature
Sensor Positive power of E1 path, current RMS or the
preset power constant can be selected to be
accumulated into the positive E1 energy
accumulator (Energy Acc_P).
U
U ADC
Phase
Compensation
Decimation DPGA BPF
x GAIN U RMS
PMCtrl4, 0x287D
AVG U RMS/s Bit2 CFXCG
P13FS
IA I1 Phase Apparent CFx
IA ADC
Compensation
Decimation DPGA BPF
x GAIN I1 RMS
PWR
AVG I1 RMS/s
IB ADC
Phase
Decimation DPGA BPF
x GAIN I2 RMS
IB I2 Compensation Apparent
PWR
AVG I2 RMS/s
PMCtrl3, 0x287A
Current Detection ITG* Bit4 DBLEN CNT
1
0 Energy Acc_N
GAIN E2 PWR
E2 Path CF2
h
Frequency CF2
Measurement *ITG represents the digital integrator. It is used to shift
AVG E2 PWR/s Sign Energy Acc_P
the phase of the current signal by 90 degrees for
reactive power calculation. CNT
Figure 10-1 Digital Signal Processing in Vango Metering Architecture
ec
10.1. Accessing to Registers for Vango Metering
Architecture
ot
In V98XX, MCU must write or read of the metering control, data and calibration registers through the
buffer registers.
1. Buffer registers for write and read operation.
When a POR/BOR, RSTn pin reset, or WDT overflow reset event occurs, all buffer registers for the write
ng
and read operation on the registers for energy metering architecture will be reset to their default states.
Table 10-1 Buffer Registers and Data to Be Written or Read
Data ACK INVD DATA[31:24] DATA[23:16] DATA[15:8] DATA[7:0]
Buffer Register BUFF5 BUFF4 BUFF3 BUFF2 BUFF1 BUFF0

Va
Address 0x2885 0x2884 0x2883 0x2882 0x2881 0x2880
2. Read operation
MCU must read the registers for energy metering architecture following steps as illustrated:
a. Write “0xCC”, and then “0s” to the register “INVD” located at address “0x2884”;
b. Read the address of the target register;
c. When the flag bit “ACK” is read out as ‘0’, or in no more than 24 MTCLK clock periods, the
content (DATA) of the target register will be loaded into the buffer registers in sequence as
illustrated in the preceded table;
d. Read the buffer registers to acquire the content (DATA).
3. Write operation

V98XX Datasheet
MCU must write of the registers for energy metering architecture following steps as illustrated:
a. Write “0xCC”, and then “0s” to the register “INVD” located at address “0x2884”;
b. Write the data (DATA) to the buffer registers in sequence as illustrated in the preceded table;
c. Write of the address of the target register;
d. When the flag bit “ACK” is read out as ‘0’, or in no more than 24 MTCLK clock periods, the
content (DATA) in the buffer registers will be loaded into the target registers.
10.2. Metering Clock

“CLK2” provides clock pulse for the energy metering architecture, including ADCs. It is sourced by
h
OSC clock or PLL clock. When “CLK2” is disabled, the metering architecture stops running.
There is a specific bit (“GT”, “bit7” of “IDET”, 0x2886) to gate control the clock for the sampling
ec
circuits and RMS/power calculation circuits. When this bit is set to ‘1’, the circuits stop working, but the
energy accumulation unit keeps on running.
In working state, the PLL clock is enabled, and it is selected as the source for “CLK2”. In this condition,
the metering clock frequency (fMTCLK) and sampling frequency of ADCs (fADC) are configurable, and fMTCLK
must be 4 times of fADC.
ot
Table 10-2 Configuration of CLK2
Register Bit Description
To select the clock source for CLK2. 0: OSC clock; 1: PLL

clock.
bit7
ng
This bit is writable and readable. Configure this bit to switch

SysCtrl MEAFRQ
the clock source for CLK2, and read this bit to acquire the
SFR 0x80 current clock source for CLK2.
bit4 Set this bit to 1 to stop CLK2.
PMG By default this clock is running.

Va

Bit[5:4]
ADCs (ADCCLK). Base: 204.8kHz.
ADCLKSEL<1:0>
CtrlCLK 00: ×1; 01: ×2; 10: ×4.
0x2867 To configure the clock frequency for the energy metering

bit[3:2]
architecture (MTCLK). Base: 819.2kHz.
MEACLKSEL<1:0>
00: ×1; 01: ×2; 10: ×4.
10.3. Reference Voltage

In the V98XX, the BandGap circuit outputs a reference voltage (about 1.185V with a typical
temperature drift of 10ppm/˚C) and bias current for ADCs and PLL circuit. So users must enable the

V98XX Datasheet
BandGap circuit before enabling ADCs or PLL circuit.
Users can improve the BandGap performance via adjusting the temperature coefficient as follows:
1. Set bit BGPPDN (bit6 of CtrlCLK, 0x2867) to 1 to enable the BandGap circuit;
2. Ensure that the bit BGPCHOPN (bit0 of CtrlBGP, 0x2862) is cleared, which enables the chopper to
remove the DC component of the BandGap circuit. When the chopper is enabled, the output voltage
of the BandGap circuit varies over the range -50~+50mV, and the temperature coefficient is improved.
3. Configure bits REST<2:0> and RESTL<1:0> (bit[5:1] of CtrlBGP, 0x2862) to adjust the temperature
coefficient to eliminate the temperature coefficient introduced by external components. A
temperature coefficient drift of x in the BandGap circuit results in a drift of -2x in the meter
measurement error.
h
Ref(v)
ec
ot
ng
temperature(℃)
Va
4.
Figure 10-2 The temperature characteristic curve of reference voltage

In the V98XX, a circuit is designed to supervise the current leakage of the external decoupled capacitors
connected to the pin REF. When bit REFLKEN (bit7 of CtrlCry2, 0x2861) is set to 1, an interrupt, REF
leakage interrupt, will be triggered when the reference voltage is lowered by 3% caused by current
leakage, and flag bit IR4 (bit4 of ExInt4IFG, 0x2850) is set to 1. When IE4=1 (bit4 of ExInt4IE, 0x2853),
EIE.2=1 (bit2 of SFR 0xE8) and IE.7=1 (bit7 of SFR 0xA8), this circuit will generate an interrupt to CPU
when flag bit IR4 is set to 1.
10.4. Analog Inputs

The V98XX has three pairs of analog inputs forming two current channels and one voltage channel.
The current channels consist of two fully differential voltage inputs. And the voltage channel consists of

V98XX Datasheet
a pseudo differential voltage input: UP is positive input for the voltage channel, and UN, grounded, is
negative input for the voltage channel. Each input has a maximum voltage of ±200mV, and each pair
has a maximum differential voltage of ±400mV.
In a current channel, a current transformer (CT) or a shunt resistor can be used for analog inputs.
CT RF
IP +
R0 CF
R1 RF AGND
IN -
h
CF
P AGND
AGND
N L
ec
Figure 10-3 CT for Current Analog Input
Load R1
IP
ot
C1
Resistor
Shunt
C2
ng
IN
R2
Va
N L
Figure 10-4 Shunt Resistor Network for Current Analog Input

In the voltage channel, a potential transformer (PT) or a resistor-divider network can be used for
analog inputs.

V98XX Datasheet
PT UP +
RF CF
AGND
UN -
RF CF
N L AGND AGND
Potential Transformer (PT) Circuit
h
Ra
ec
RF UP +
CF
AGND
AGND UN -
CF
RF
AGND
AGND
ot
AGND
N L
Resistor-Divider Network
Figure 10-5 Analog Input of Voltage

ng
The full measurement scale of ADCs is ±1.1 V. To match the output signal of the sensors with the
measurement scale of ADCs, groups of Analog Programmable Gain Amplifiers (APGA) are set. The
product of the analog input and the set APGA should not be over ±1.1 V.
Table 10-3 Analog PGA Gain Configuration for Current and Voltage Analog Input

Va
Bit7
0 These bits must hold their default values for proper operation.
Reserved
CtrlADC0 To set analog PGA gain for voltage input to Voltage Channel
(U) ADC. It is mandatory to set this bit to its default value for
0x2858 bit6 proper operation.
0
ADCGU 0: ×1;
1: ×2.

V98XX Datasheet
To set analog PGA gain for current input to Current Channel B

(IB) ADC
bit[5:3] 000: ×1; 001: ×4; 010: ×8; 011: ×16; 100/101/110/111:
0 ×32.
ADCGB<2:0>
To match the output signal from the sensor to the
measurement scale of the ADC, the default value should not
be used.
To set analog PGA gain for current input to Current Channel A

(IA) ADC
h
bit[2:0] 000: ×1; 001: ×4; 010: ×8; 011: ×16; 100/101/110/111:
0 ×32.
ADCGA<2:0>
To match the output signal from the sensor to the
ec
measurement scale of the ADC, the default value should not
be used.
10.5. Analog-to-Digital Conversion

ot
Second-order Σ-ΔADCs are designed in three channels of V98XX for analog-to-digital conversion, and
their full measurement scale is ±1.1 V. By default, Σ-ΔADCs are disabled. Users can enable them via
configuring “CtrlADC6” register (0x2864).
Note: It is mandatory to clear bit “DCENN” (“bit7” of “CtrlLCDV”, 0x285E) to add 10-mV direct voltage
ng
offset to the current input to current channel ADCs.
Table 10-4 Enable/Disable ADCs
To enable Channel U ADC

Va
bit2 ADCUPDN 0 0: Disable.
1: Enable.
To enable Channel IB ADC

CtrlADC6
bit1 ADCBPDN 0 0: Disable;
0x2864
1: Enable.
To enable Channel IA ADC
bit0 ADCAPDN 0 0: Disable;
1: Enable.
After analog-to-digital conversion, the analog signals are converted to be 1-bit code streams of 22-bit
length with both “bit21” and “bit20” being the sign bits.

V98XX Datasheet
10.6. Switch of Current Channels

After analog-to-digital conversion, current IA or IB is sent to Current I1 or Channel I2, via configuring
the bit “SELI” (“bit5” of “PMCtrl1”, 0x0100), for different signal processing.
Phase
compensation
U U RMS
DPGA Calculation
Power
IA I1 I1 Calculation CF pulse
DPGA Energy output
Accumulation
IB I2 I2 Energy-Pulse
DPGA
h
Conversion
SELI
ec
Figure 10-6 Exchange of Current Channels
Table 10-5 Control Bit for Switching Current Signals

ot
To exchange the current channels. By default this bit is cleared.
0x2878 SELI 0: current IA is sent to Current I1 Channel for signal processing, and current IB is
sent to Current I2 Channel for signal processing;
PMCtrl1 Bit5
1: current IA is sent to Current I2 Channel for signal processing, and current IB is
ng
sent to Current I1 Channel for signal processing.
Then current (I1 and I2) and voltage signals must be input to a phase compensation circuit to correct
the phase angle error between the current and voltage signals introduced by the transformers.
Va

V98XX Datasheet
10.7. Phase Compensation
Sinc3 Filter
U
ADC D D D …… D D D
PHCx7~PHCx0
h
I1/I2
ec
ADC D D D …… D D D
Sinc3 Filter
ot
Figure 10-7 Phase Compensation Schematics
A phase compensation circuit composed of a time delay chain of fixed length is applied to correct the
phase angle error via delaying the selected signal. Either current or voltage signals can be delayed.
By default phase compensation is disabled. Users can enable this function via configuring the bit
ng
“PHCEN” (“bit6” of “PMCtrl1”, 0x2878). When phase compensation is enabled, the phase angle error
between I1 and U, and I2 and U, are corrected respectively. “Bit [7:0]” of register “PHCCtrl1” (0x287B)
together with “bit[1:0]” (IAPHC) of register “CRPST” (0x287F) or “bit[7:0]” of register “PHCCtrl2”
(0x287C) together with “bit[3:2]” (IBPHC) of register “CRPST” (0x287F) are used to calibrate the
phase angle error between signal I1 or I2 and the voltage signal, see Table 10-7 for details.
In 50-Hz power grid, when the sampling frequency of the phase compensation circuit (fsmpl) is
Va
3.2768 MHz, the calibration resolution is 0.0055°/lsb, and the maximum phase angle error to be
corrected is 1.4°. The value of fsmpl is determined by the configuration of bits “MEACLKSEL<1:0>”
(“bit[3:2]” of “CtrlCLK”, 0x2867).
At a lower power factor (PF), the phase angle error can cause greater energy metering error. So
generally, the phase angle error is calibrated at PF=0.5L to ensure the metering accuracy. When PF=0.5L,
users can use a simple equation as follows to calculate the value N.
3011 𝑓𝑠𝑚𝑝𝑙
𝑁 = 𝑅𝑜𝑢𝑛𝑑( ×𝐸× ) Equation 10-1where,
2 819200
N is the value, signed, to be set to the phase compensation control registers to correct the phase
angle error. A positive N indicates that current signal must be delayed, so “0” must be set to the sign
bit; a negative N indicates that the voltage signal must be delayed, so “1” must be set to the sign
bit;
E is the energy metering error displayed in LCD screen of the calibration equipment;

V98XX Datasheet
fsmpl is the sampling frequency of the phase compensation circuit, Hz.
Table 10-6 fsmpl Determines Phase Compensation Resolution and Correction Range
N MEACLKSEL<1:0> Configuration fsmpl (Hz) Resolution (°/lsb) Correction Range (°)
00 819200 0.022 5.6
[-255, +255] bit[3:2], 0x2867 01 1638400 0.011 2.8
10 3276800 0.0055 1.4
Table 10-7 Registers for Phase Compensation
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PHCCtrl1（0x287B）/PHCCtrl2（0x287C） CRPST（0x287F）
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit[3:2]/bit[1:0]
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PHCx7 PHCx6 PHCx5 PHCx4 PHCx3 PHCx2 PHCx1 PHCx0 IxPHC
x=A or B. “PHCx7” is the sign bit, “PHCx6” is not used, and the other 8 bits are used to set the
absolute value to correct the phase angle error.
10.8. Digital Input

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In V98XX, decimation filters are designed to reduce the noise of the 1-bit code stream output from the
oversampling Σ/ΔADC and to reduce the sampling frequency to 1/256 of fADC.
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CIC Filter HPF DPGA

IA/IB
ADC M PGA ∫
To power and RMS
calculation
Phase
Compensation
CIC Filter HPF DPGA

Va
U
ADC M PGA
To power and RMS
calculation
Figure 10-8 Digital Inputs

“Bit[2:0]” of the register “PMCtrl1” (0x2878) enables or disables the code stream input into the
decimation filter. When this function is enabled, the code stream will be input to the filter; otherwise, 0s
are input for digital signal processing.
Table 10-8 Enable/Disable Digital Inputs

V98XX Datasheet
To enable digital signal input to the I2 channel.

Bit2
0: disable; 0s are input to I2 channel.
ONI2
1: enable.
To enable digital signal input to the I1 channel.

0x2878 Bit1
0: disable; 0s are input to I1 channel.
PMCtrl1 ONI1
1: enable.
To enable digital signal input to the U channel.

Bit0
h
0: disable; 0s are input to U channel.
ONU
1: enable.
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As depicted in the above figure, the signal output from the decimation filter in each channel will be
sent to a high-pass filter (HPF) to remove the DC components introduced by the sensors and ADCs. In
the V98XX, this high-pass filter cannot be disabled. When the “ADCCLK” frequency is 819.2 kHz, this
filter will be settled in 60 ms in 50-Hz power grid, and in 50 ms in 60-Hz power grid.
Digital programmable gain amplifiers (DPGA) with possible gain selection via “PMCtrl2” (0x2879) and
“PMCtrl3” (0x287A) are applied to digital signals output from the high-pass filters to amplify their
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capability of depressing truncation noise when a low signal was input. Please note the product of the
analog input and the total PGA gains, including APGA and DPGA, should not be over the measurement
scales of the ADCs.
Table 10-9 DPGA Gain Selection for Digital Signals

ng
To set sign of the digital PGA gain for I2 signal.

PGANS
0: positive;
PMCtrl3 Bit3
1: negative.
0x287A
Va
PGAN2~PGAN0 To set the digital PGA gain for I2 signal. Gain=2PGANx.
Bit[2:0] PGANx is over the range of 0~5.
To set sign of the digital PGA gain for I1 signal.

PGACS
0: positive;
PMCtrl2 Bit7
1: negative.
0x2879
PGAC2~PGAC0 To set the digital PGA gain for I1 signal. Gain=2PGACx.
Bit[6:4] PGACx is over the range of 0~5.

V98XX Datasheet
To set sign of the digital PGA for U signal.

PGAUS
0: positive;
Bit3
1: negative.
To set the digital PGA gain for U signal. Gain=2PGAUx. PGAUx is over the
range of 0~5.
PGAU2~PGAU0
When bit LPFEN (bit5 of PMCtrl3, 0x287A) is set to 1, the digital PGA gain
Bit[2:0]
for U signal is lowered to 1/4 of its configuration. When bit LPFEN is
cleared, the digital PGA gain for U signal is what it is configured.
h
The following equations describe the digital signals processed by the digital programmable gain
amplifiers:
Aua
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Ua = PGAdua ×PGAua × ×sin ωt = DUa ×sin ωt
1.185
Aia
Equation 10-2
Ia = PGAdia ×PGAia × ×sin(ωt + ψ) = DIa×sin(ωt + ψ)
1.185
where, PGAdua and PGAdia are the DPGA gains; PGAua and PGAia are the APGA gains; Aua and Aia are
the amplitude of current and voltage inputs; and 1.185 is the reference voltage.
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10.9. Current Detection
To lower power consumption, a current detection circuit is designed in the V98XX to compare the AC
component of the instantaneous I1 current signal with the preset threshold in register IDETTH (0x1002).
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Set bit DETON (bit4 of IDET, 0x2886) to 1 to enable current detection, and configure bit[3:0] of IDET
(0x2886) for current detection window width ([IDLEN]+1). When ([IDLEN]+1) continuous current
samples are detected to be higher than the preset threshold, it is defined a current signal is caught, and
flag bit CST (bit6 of IDET, 0x2886) is set to 1. Users must set bit CLR (bit5 of IDET, 0x2886) to 1 or clear
bit DETON to clear bit CST.
The configuration of bit IDLEN (bit[3:0] of IDET, 0x2886) and the current detection period have a
Va
relationship as follows:
256 × ([𝐼𝐷𝐿𝐸𝑁] + 1)
𝑡𝐼𝐷𝑇 = × 1000 Equation 10-3
𝑓𝐴𝐷𝐶
where, 256 means the decimation filter (CIC) has reduced the sampling frequency to 1/256 of fADC,
the sampling frequency of the oversampling ADC; [IDLEN] is the configuration of bits IDLEN; tIDT is the
current detection period, in unit of ms. To perform current detection, it is mandatory to enable the
metering clock (MTCLK), and enable power/RMS calculation.
10.10. RMS Calculation and Calibration

The V98XX supports RMS calculation. By default this function is disabled. When RMS calculation is
enabled, users can enable the band-pass filter in the RMS calculation circuit via bit BPFEN (bit6 of PMCtrl3,

V98XX Datasheet
0x287A) and configure the filter coefficient via register PARABPF (0x10EF) to improve calculation
accuracy.
Table 10-10 Configuring for RMS Calculation and Calibration
Set this bit to 1 to disable the sampling circuits and power/RMS calculation circuits.
IDET GT In this case, the energy accumulation circuit keeps on working. So in an application
to accumulate a constant for energy accumulation, it is recommended to set this
0x2886 Bit7 bit to 1 to lower power consumption further. But please note the threshold for
energy-to-pulse conversion must be set before setting this bit to 1.
To enable active/reactive power calculation and RMS calculation, the apparent
h
power calculation in M Channel.
PMCtrl1 PREN
0: disable;
0x2878 Bit4
1: enable.
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By default this function is disabled.
To enable the band-pass filter in the voltage/current RMS calculation circuits.
0: disable (default);
PMCtrl3 BPFEN
1: enable.
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0x287A Bit6
This filter can improve the RMS calculation accuracy, but will lead to harmonics
loss. When a low signal is input, this filter will introduce greater truncation noise
and prolong the period for the system to be settled.
To set the coefficient for the band-pass filter in the RMS calculation circuits.
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PARABPF If MTCLK frequency is reduced to 819.2kHz, users must disable energy

accumulation, CF pulse output and no-load detection, and then configure this
0x10EF
register to 0x911D3C9C. When MTCLK frequency is reinstated to 3.2768MHz, this
register must be set to its default value.
As illustrated in Figure 10-9, the current or voltage signal output from the high-pass filter is multiplied
Va
with itself in the multiplier to get the product with the second harmonic which can be removed by the
low-pass filter, and then the signal processed output from the low-pass filter is sent to the circuit for
rooting processing that produces a 32-bit datum, the raw RMS value of current or voltage. The raw RMS
data will be gain calibrated and then stored in instantaneous RMS registers. Besides, the instantaneous
RMS data will be averaged to acquire the average RMS data that are stored in average RMS registers.
If the raw RMS value is represented as RMS’, the gain calibration value is represented as S, and the
instantaneous RMS is represented as RMS, then the above three values have the relationship:
RMS=RMS’×(1+S) Equation 10-4

V98XX Datasheet
Apparent
power
Gain calibration calculation
u(t)/i(t) From HPF 32
32 32 X 32 32 Average
32 U/ I
32 Urms/Irms
multiplier LPF
Figure 10-9 RMS Calculation and Calibration

The content of all the instantaneous and average RMS data registers are in the form of 32-bit 2’-
complement. When POR/BOR, RSTn pin reset or WDT overflow reset occurs, these registers are reset to
their default states.
h
10.11. Apparent Power Calculation
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The V98XX supports apparent power calculation. This function is enabled or disabled together with
RMS calculation.
In the V98XX, the average current and voltage RMS are multiplied to acquire the apparent power, as
described in the following equation:
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S=Irms × Urms Equation 10-5
where, S represents apparent power; Irms and Urms are the average current and voltage RMS.
The content of the apparent power registers are in the form of 32-bit 2’-complement. When POR/BOR,
RSTn pin reset or WDT overflow reset occurs, these registers are reset to their default states.
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10.12. Power Calculation and Calibration

The V98XX supports active/reactive power calculation. This function is enabled or disabled together
with the RMS calculation and apparent power calculation.
There are two paths for power calculation, energy accumulation and energy pulse generation: E1 path
Va
and E2 path. E1 path is used for active power calculation and energy accumulation only; but, E2 path
can be configured for active or reactive power calculation and energy accumulation which is determined
by bit DBLEN (bit4 of PMCtrl3, 0x287A). By default E2 path is used for reactive power calculation based
on current I1.
Table 10-11 Functions of E2 Path

V98XX Datasheet
Register Bit Function Description
To select the function of E2 path.
0: for reactive power calculation and energy metering based on current I1. If
0x287A DBLEN positive current I1 is input to the path, the reactive power is negative, and it is
accumulated to the negative energy accumulators; if negative current I1 is input
PMCtrl3 Bit4 to the path, the reactive power is positive, and it is accumulated to the positive
energy accumulators.
1: for active power calculation and energy metering based on current I2.
10.12.1. Active Power Calculation and Calibration
h
For energy
accumulation
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Gain P(t)
u(t) from HPF 32 Calibration
32 32 32 AVG 32 P
i(t) from HPF 32
Multiplier LPF
Offset
S Calibration
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Figure 10-10 Signal Processing for Active Power Calculation and Calibration
In the V98XX, E1 path always calculates active power based on current I1. And when DBLEN is set to
1, E2 path is also used to calculate active power based on current I2.
As illustrated in the above figure, after being filtered by the high-pass filter (HPF), the current and
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voltage multiply each other. Then, the product is input to the low-pass filter (LPF) to remove the
harmonics and the ripples caused by the noise, and the output of the LPF is the raw active power. This
raw power is gain calibrated and then offset calibrated to acquire the instantaneous active power that is
stored in the registers DATAIP (0x10D1, for active power calculated in E1 path) and DATAIQ (0x10D2,
for active power calculated in E2 path). The instantaneous active power will be averaged to get the
average active power that is stored in the registers DATAP (0x10D6, for active power in E1 path) and
DATAQ (0x10D7, for active power in E2 path). The content of all the registers are in the form of 32-bit
Va
2’-complement, and they will be reset to their default states when POR/BOR, RSTn pin reset or WDT
overflow reset occurs.
Users can configure the registers SCP (0x10E8) and SCQ (0x10E9) for gain calibration over the range
of -∞~+49.9%, and the registers PARAPC (0x10ED) and PARAQC (0x10EE) for offset calibration over
the range of -50%~+50%. The content of these registers are in the form of 32-bit 2’-complement. When
POR/BOR, RSTn pin reset or WDT overflow reset occurs, all the registers are reset to their default states.
10.12.2. Reactive Power and Calibration
By default the V98XX supports calculating active and reactive power based on current I1.

V98XX Datasheet
For Energy
Accumulation
∫ Gain
32
Q(t)
i(t) from HPF Calibration
32 AVG Q
32
32
32
32
u(t) from HPF Offset
Multiplier LPF S Calibration
Figure 10-11 Signal Processing for Reactive Power Calculation and Calibration
As illustrated in the above figure, current I1, filtered by the high-pass filter (HPF), is input into a digital
integrator to shift the phase by 90° (the integrator introduces an extra gain of 1.568 that can be
eliminated via gain calibration). The filtered current signal is sent to the multiplier together with voltage
to multiply each other. Then, the product is input to the low-pass filter (LPF) to remove the harmonics
and the ripples caused by the noise, and the output of the LPF is the raw reactive power. This raw power
h
is gain calibrated and offset calibrated to acquire the instantaneous reactive power, which is stored in
the register DATAIQ (0x10D2, for reactive power calculated in E2 path). The instantaneous reactive
power will be averaged to get the average reactive power, which is stored in the register DATAQ (0x10D7,
for reactive power in E2 path). The content of the registers are in the form of 32-bit 2’-complement, and
ec
they will be reset to their default states when POR/BOR, RSTn pin reset or WDT overflow reset occurs.
Users can configure register SCQ (0x10E9) for gain calibration over the range of -∞~+49.9%, and
register PARAQC (0x10EE) for offset calibration over the range of -50%~+50%. Both registers are in the
form of 32-bit 2’-complement. When POR/BOR, RSTn pin reset or WDT overflow reset occurs, both
registers are reset to their default states.
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10.13. Energy Accumulation and CF Pulse Output
The V98XX supports energy accumulation and energy-to-pulse conversion. By default this function is
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disabled. Users can set bit EGYEN (bit3 of PMCtrl4, 0x287D) to 1 to enable energy accumulation and
energy-to-pulse conversion.
ENERGY_ACC CNT
32
32
SIGN
32
P(t)/Q(t) Threshold CF
Va
1
32
32
0
32
ENERGY_ACC CNT
32
32
Figure 10-12 Energy Accumulation and CF Pulse Output
10.13.1. Energy Accumulation
In E1 path, positive and negative active powers are accumulated into the energy accumulators
according to their signs; for example, positive active power is accumulated into PPCNT (0x10F0), and
negative active power is accumulated into NPCNT (0x10F1). Besides, other data, such as I1 current RMS
or a constant (preset in the register DATACP, 0x10FC), also can be selected to be accumulated into PPCNT

V98XX Datasheet
via configuring bits PSEL1~PSEL0 (bit[1:0] of PMCtrl4, 0x287D) when the chip is used for low power
applications.
In E2 path, positive and negative active/reactive powers are accumulated into the energy accumulators
according to their signs; for example, positive power is accumulated into PQCNT (0x10F6), and negative
power is accumulated into NQCNT (0x10F7).
When MTCLK frequency is 3.2768MHz, 1.6384MHz or 819.2kHz, the energy accumulation frequency is
12.8kHz. When MTCLK frequency is 32768Hz, the energy accumulation frequency is 2979Hz.
The energy accumulators are of actual 42-bit length. But only the higher 32 bits are readable; and
only the higher 32 bits are valid for write operation and the 10 least significant bits are padded with 0s
in write operation. When POR/BOR, RSTn pin reset or WDT overflow reset occurs, all the energy
accumulators are reset to default values, 0s.
h
Table 10-12 Register Configuration for Energy Accumulation
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To enable energy accumulation and energy-to-pulse conversion.
Bit3
0: disable;
EGYEN
1: enable.
PMCtrl4
To select the source for positive active energy accumulation in E1 path.
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0x287D
Bit[1:0] 00/11: active power calculated based on current I1;
PSEL1~PSEL0 01: I1 current RMS;
10: a constant preset in the register DATACP (0x10FC).

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10.13.2. Energy Pulse Generation and CF Pulse Output
When energy accumulation and energy-to-pulse conversion is enabled, the energy will be accumulated
at a certain rate. Preset a threshold in the register GATEP (0x10F4, for active energy accumulation in E1
path) or GATEQ (0x10FA, for active/reactive energy accumulation in E2 path), and when the content of
Va
energy accumulators in E1 or E2 path is higher than the preset threshold, the energy accumulator
overflows, an energy pulse is generated, the energy pulse counter increments by 1, and a value equal
to the threshold is subtracted from the energy accumulator.
When a low signal is input, users can reduce the energy threshold to increase the pulse generation
rate to speed up energy calibration via configuring bits CFQR1~CFQR0 and CFQ1~CFQ0 (bit[7:4] of
CFCtrl, 0x287E).
When CF pulse output is enabled, one CF pulse will be output every 2 counts of the pulse counter.
When MTCLK frequency is 3.2768MHz, the maximum CF pulse output frequency is 6.4kHz, and the pulse
width is configurable via bits CFWD (bit[5:4] of CRPST, 0x287F) and by default the width is 80ms.
In the V98XX, four pins, CF1, P9.5/CF2, P9.6/CF1 and P1.3/CFx, are used for CF pulse output.
- The pin CF1 is used for pulse output of E1 path only;
- When bit5 and bit6 of the register P9FS (SFR 0xAD) are set to 1s, the ports P9.5 and P9.6 are used

V98XX Datasheet
for CF pulse output of E1 and E2 path respectively;
- When the register P13FS (0x28C7) is set to 0x01, the port P1.3 is used for CF pulse output of E2
path; when the register is set to 0x04, the port P1.3 is used for CF pulse output of E1 path.
When bit CFWKEN (bit2 of IOWK, SFR 0xC9) is set to 1, CF pulse output can wake up the system from
Sleep. By default CF pulse output can wake up and reset the system to OSC state. But when bit IORSTN
(bit0 of IOWK, SFR 0xC9) is set to 1, this event can wake the system only but not reset the system. In
this condition, after wakeup, the CPU keeps on executing the codes, and all circuits goes back where
they were before sleeping, except that bits of SysCtrl (SFR 0x80), SLEEP1, SLEEP0, FWC and FSC, are
cleared. When bits RTC/CF (bit2 of Systate, SFR 0xA1) and CFWK (bit3 of IOWKDET, SFR 0xAF) are read
out as 1s, it indicates the system was woken up by CF pulse output.
Table 10-13 Configurations for Energy Pulse Generation Rate and CF Pulse Output
h
To enable CF pulse output of E2 path.
ec
Bit5, CFENR 0: disable;
1: enable.
To enable CF pulse output of E1 path.

PMCtrl4
Bit4, CFEN 0: disable;
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0x287D
1: enable.
To select the pins for CF pulse output.

Bit2
0: CF1 pin for E1 path; CF2 pin for E2 path;
CFXCG
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1: CF2 pin for E1 path; CF1 pin for E2 path.
To adjust the energy pulse generation rate in E2 path.
00: ×1;
Bit[7:6],
01: ×4;
CFQR1~CFQR0
10: ×8;
Va
CFCtrl 11: ×16.
0x287E To adjust the energy pulse generation rate in E1 path.
00: ×1;
Bit[5:4],
01: ×4;
CFQ1~CFQ0
10: ×8;
11: ×16.

V98XX Datasheet
To select the energy in E2 path to be converted into pulse.
01: positive active or reactive energy in E2 path;

bit[3:2]
10: negative active or reactive energy in E2 path;
CFSELR1~CFSELR0
00/11: the sum of the absolute values of the positive and negative
active or reactive energy in E2 path.
01: positive active energy in E1 path;

Bit[1:0]
10: negative active energy in E1 path;
h
CFSEL1~CFSEL0
00/11: the sum of the absolute values of the positive and negative
active energy in E1 path.
ec
To adjust the CF pulse width.
00: 80ms;
CRPST bit[5:4]
01: 40ms;
0x287F CFWD
10: 20ms;
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11: 10ms.
10.14. No-Load Detection

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The V98XX supports no-load detection on both E1 and E2 paths. By default this function is disabled,
but users can enable it via configuring bits CRPENR and CRPEN (bit7 and bit6 of PMCtrl4, 0x287D).
There is an anti-creeping accumulator in the no-load detection circuit. When no-load detection is
enabled, 1s are accumulated in this register constantly. When MTCLK frequency is 3.2768MHz,
1.6384MHz or 819.2kHz, the accumulation frequency is 12800Hz; and when MTCLK frequency is
32768Hz, the accumulation frequency is 2979Hz.
Va
When no-load detection is enabled, constant 1s are accumulated into the embedded anti-creeping
accumulator, and the energy accumulator in E1 or E2 path accumulates active or reactive power or a
power constant. Preset a threshold for no-load detection in register GATECP (0x10F5) or GATECQ
(0x10FB), and a threshold for energy-to-pulse conversion in register GATEP (0x10F4) or GATEQ (0x10FA).
Compare the accumulation rate. If the energy accumulator overflows sooner, the anti-creeping
accumulator is cleared, and E1 or E2 path starts to meter energy. Otherwise, E1 or E2 path enters
creeping state. Users can read bit CRPST or CRPSTR (bit7 or bit6 of CRPST, 0x287F) to detect the state
of the path.
When POR/BOR, RSTN pin reset or WDT overflow reset occurs, the mentioned threshold registers are
reset to their default values, 0s.
The energy accumulators are of actual 42-bit length, but the threshold registers for energy-to-pulse
conversion are of 32-bit length. So, the threshold registers will be padded with a string of 10 0s on the
right to work as 42-bit registers.

V98XX Datasheet
Table 10-14 Configure for No-Load Detection
To enable no-load detection of E2 path.
CRPENR, Bit7 0: disable (default);
PMCtrl4 1: enable.
0x287D To enable no-load detection of E1 path.
CRPEN, Bit6 0: disable (default);
1: enable.
To indicate the state of E1 path.
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CRPST, Bit7 0: metering energy;
CRPST 1: creeping.
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0x287F To indicate the state of E2 path.
CRPSTR, Bit6 0: metering energy;
1: creeping.
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10.15. Line Frequency Measurement
The V98XX supports line frequency measurement.
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BPF
u(t) From HPF ZERO
0x10FD
32 32 CROSSING 16 DATAFREQ
DETECTION
Figure 10-13 Signal Processing for Line Frequency Measurement

In the line frequency measurement circuit, the voltage signal, filtered by the high-pass filter, is input
Va
to a band-pass filter (BPF), which has a 50Hz center frequency with 25dB attenuation at 150Hz, for signal
processing. The output signal from the BPF is detected for zero-crossing. The average number of the
samples of the signal in 16 cycles is equal to the value of the register DATAFREQ (0x10FD). Then, the
line frequency can be calculated via the following equation:
f
f = ADC Equation 10-6
FRQ
where, f is the line frequency to be measured; FRQ is the content of register DATAFREQ (0x10FD) in the
form of decimal.
The line frequency register is a 16-bit, unsigned register. When POR/BOR, RSTn pin reset or WDT
overflow reset occurs, this register is reset to its default state. The measurement resolution is 0.05Hz/lsb,
and the measurement range is over 35~75Hz. When MTCLK frequency is 3.2768MHz, this register is
updated in 320ms, and is settled in 500ms.

V98XX Datasheet
Note: When MTCLK frequency is lowered to 819.2kHz, the sampling frequency of the enabled band-pass
filter in the RMS calculation circuit is changed to 800Hz and the center frequency is changed to 12.5Hz,
which has a greater attenuation on 50Hz signals and will reduce the accuracy of the RMS calculation and
line frequency measurement. So, if MTCLK frequency is reduced to 819.2kHz, users must disable energy
accumulation, CF pulse output and no-load detection, and then configure this register to 0x911D3C9C.
10.16. Measuring Various Signals in M Channel
10.16.1. Architecture of M Channel
h
The M Channel can be used to measure the ground, temperature, battery voltage and external voltage
signals. As illustrated in the following figure, there is only one ADC in M Channel, so users must configure
registers to use this channel to measure one signal at a time.
ec
MEAS[2:0]
Temp. Resistive
Voltage
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AVSS Divider
BAT
V
ng
UM
RESDIV_N
MUX
M0 R1
M1 Vm M Channel
RESDIV ADC
Va
M2 R2
RESDIV
R1+R2=30kΩ
Figure 10-14 M Channel Architecture

V98XX Datasheet
ONM Instantaneous DC
component
M ADC 1 CIC filter Average
32
0 0
Average DC
component
Raw waveform
Figure 10-15 Signal Processing in M Channel

There are three data registers of M Channel, DATAOM (0x10CE) for raw waveform of the various signal
input, DATADM (0x10CF) for instantaneous DC component of the signal, and DATAADM (0x10D0) for
average DC component of the signal. The content of these registers are in the form of 32-bit 2’
h
complement. When POR/BOR, RSTn pin reset or WDT overflow reset occurs, these registers are reset to
In 50Hz power grid, when MTCLK frequency is 3.2768MHz, DATAOM is updated in 0.3ms and settled
ec
in 10ms; DATADM is updated in 20ms and settled in 70ms; DATAADM is updated in 1.28s and settled in
3s. If MTCLK frequency is divided by a coefficient K, the update and settle time is K times of that for
3.2768MHz MTCLK frequency.
10.16.2. Measuring Temperature

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M Channel is used to measure temperature. The temperature measurement range is over -40~+85˚C
with a measurement error of ±1°C.
It is recommended to measure temperature following steps:

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1. Enable M Channel ADC: ADCMPDN=1 (bit3 of CtrlADC6, 0x2864). It is mandatory to enable BandGap
circuit before M Channel ADC;
2. Configure the register CtrlADC5 (0x2863) as follows:
- To disable the internal resistive divider: RESDIV=0 (bit4);
- To enable M Channel to measure temperature: MEAS<2:0>= 001 (bit[2:0]).

Va
3. Set bit MADCHOPN (bit0 of CtrlM, 0x2865) to 1 to stop removing DC offset in M Channel ADC;
4. Enable the sampling circuits and power/RMS calculation circuits: GT=0 (bit7 of IDET, 0x2886);
5. Configure the register PMCtrl1 (0x2878) as follows:
- Set bit ONM (bit3) to 1 to enable digital signal input to M Channel for digital signal processing;
- Set bit PREN (bit4) to 1 to enable digital signal processing.
6. Wait for 70ms (fMTCLK=3.2768MHz) or 280ms (fMTCLK=819.2kHz), and then read the register DATADM
(0x10CF) and calculate the nominal temperature T’ (in unit of °C):
𝑥0 1
𝐵 × (𝐷 × + 𝐶)2 − A Equation
T = ′ 216
E 10-7

V98XX Datasheet
where x0 is the reading of register DATADM (in hexadecimal); A/B/C/D/E is the parameters of the
temperature curve, which can be read in bytes located at addresses 0x420~0x433 (in small endian
format). There are another two bytes used for the checksum.
7. Calibrate temperature:
- There is a constant error ΔT between the nominal temperature T’ and the actual temperature T:
x1 Equation
∆T =
10 10-8
where x1 is the content of bytes located at addresses 0x480~0x481 (There are another two bytes used
for the checksum.) (in hexadecimal, and in small endian format), 10 times of the actual temperature
error ΔT. The unit of ΔT is 0.1 °C.
h
- Calculate the actual temperature according to the following equation:
𝑇 = 𝑇’ + ∆𝑇
Equation 10-9
ec
10.16.3. Measuring Battery Voltage and External Voltage
In the V98XX, pin BAT can be used to input battery voltage or external voltage signals to be measured,
and the voltage signal must be over the range of -200mV~3.8V; pin UM, M0, M1 or M2 can be used to
ot
input external voltage signals to be measured, and the voltage signal must be over the range of -
200mV~3.4V.
It is recommended to measure the battery voltage or external voltage signals following steps:
1. Enable M Channel ADC: ADCMPDN=1 (bit3 of CtrlADC6, 0x2864). It is mandatory to enable BandGap
circuit before M Channel ADC;
ng
2. Configure the register CtrlADC5 (0x2863) as follows:
- To configure the internal resistive divider:
 When the input voltage signal is over the range of -200mV~1.1V, it is mandatory to set
RESDIV=0 (bit4);
Va
 When the input voltage signal is over the range of 1.1V~3.8V (for BAT) or 1.1V~3.4V (for
UM/M0/M1/M2), it is mandatory to set either bit GDE4 or bit RESDIV to 1;
- To enable M Channel to measure battery voltage or external voltage signals.
3. Set bit MADCHOPN (bit0 of CtrlM, 0x2865) to 1 to stop removing DC offset in M Channel ADC;
4. Enable the sampling circuits and power/RMS calculation circuits: GT=0 (bit7 of IDET, 0x2886);
5. Configure the register PMCtrl1 (0x2878) as follows:
- Set bit ONM (bit3) to 1 to enable digital signal input to M Channel for digital signal processing;
- Set bit PREN (bit4) to 1 to enable digital signal processing.
Wait for 10ms (fMTCLK=3.2768MHz) or 40ms (fMTCLK=819.2kHz), and then read the register DATAOM
(0x10CE) and RESDIV configuration,then calculate the amplitude of the voltage signal VDC (in unit of mV):

V98XX Datasheet
- When the voltage signal is over the range of -200mV~1.1V:
𝑥𝑅
216 + 198.42
𝑉𝐷𝐶 = Equation 10-10
27210
- When the voltage signal is over the range of 1.1V~3.8V (for BAT) or 3.4V (UM/M0/M1/M2), and
RESDIV=1:
𝑥𝑅
216 + 50.693
5959.9
Because there are 30kΩ resistors in the internal resistive divider network, this network consumes
power:
h
𝑉 𝑉2
𝑃 = 𝑈𝐷 × 𝐼𝐷 = 𝑉 × =
𝑅1 + 𝑅2 30 Equation 10-12
- When the voltage signal is over the range of 1.1V~3.8V (for BAT) or 3.4V (UM/M0/M1/M2), and
ec
RESDIV=0:
𝑥𝑅
216 + 21.034
7118.3
In the above equations, xR is the content of register DATAOM (0x10CE).

ot
10.17. Initializing Energy Metering Architecture
To ensure the performance of the energy metering architecture, it must be initialized as follows:
ng
1. Clear the bits CRPEN, CFEN and EGYEN (bit5~bit3 of PMCtrl4, 0x287D) to disable energy
accumulation, CF pulse output and no-load detection; clear the bit PREN (bit4 of PMCtrl1, 0x2878)
and bits ONx (bit3~bit0 of PMCtrl1, 0x2878) to disable the signal input to Channel I1/I2/U/M and
stop the digital signal processing.
2. Enable the ADCs.

Va
3. When fADC is 819.2kHz, write 0x889374BC to the register PARABPF (0x10EF); When fADC is 204.8kHz,
write 0x911D3C9C to the register PARABPF (0x10EF).
4. Write 1 to bit PREN (bit4 of PMCtrl1, 0x2878) to enable power and RMS calculation.
5. Wait for 70ms (fADC=819.2kHz) or 250ms (fADC=204.8kHz) until the registers for waveform registers
are read out as 0s, and then clear the read/write buffer registers located at addresses
0x2880~0x2885, and clear the registers located at addresses 0x1059~0x106A.
6. Configure the calibration registers (except the PARABPF and current detection threshold register).
7. Access to the energy metering control registers:
- Configure the bit SELI (bit5 of PMCtrl1, 0x2878) to switch the current channels.
- Configure the bit PHCEN (bit6 of PMCtrl1, 0x2878) to enable phase compensation, and configure
the registers PHCCtrl1 (0x287B), PHCCtrl2 (0x287C) and bits IBPHC and IAPHC (bit[3:0] of
CRPST, 0x287F) to set which and how the signal to be delayed.

V98XX Datasheet
- Configure the digital PGA gain for current and voltage signals.
- Configure the bit DBLEN (bit4 of PMCtrl3, 0x287A) to select the function of E2 path.
- Configure the bits LPFEN and BPFEN (bit5 and bit6 of PMCtrl3, 0x287A) to enable the low-pass
filter and band-pass filter.
- Configure the bits PSEL1 and PSEL0 (bit1 and bit0 of PMCtrl4, 0x287D) to select the signal to
be accumulated to the positive energy accumulator in E1 path.
- Configure the register CFCtrl (0x287E) for CF pulse output.
- Write 1s to bit6 and bit7 of PMCtrl4 (0x287D) to enable no-load detection in E1 and E2 paths.
8. Write 1s to the bits ONx (bit3~bit0 of PMCtrl1, 0x2878) to enable the signal input to Channel
I1/I2/U/M.
h
9. Wait for 250ms (fADC=819.2kHz), or 900ms (fADC=204.8kHz).
10. Write the stored values of the energy accumulators and energy pulse counters into themselves. If
ec
the values are 0s, it is equal to clearing the registers.
11. Read of the threshold registers for energy-to-pulse conversion and no-load detection. If the value is
anomaly, reconfigure the registers.
12. Configure registers to enable CF pulse interrupt (optional).
13. Write 1s to the bits CRPEN, CFEN and EGYEN (bit5~bit3 of PMCtrl4, 0x287D) to enable energy
ot
accumulation, CF pulse output and no-load detection.
10.18. Calibration
ng
10.18.1. Registers for Meter Calibration
Table 10-15 Registers for Meter Calibration
Address Register R/W Format

Va
To set a threshold for active energy-to-pulse conversion in

0x10F4 GATEP R/W Unsigned
E1 path.
0x10F5 GATECP To set a threshold for no-load detection in E1 path. R/W Unsigned
To set a threshold for active or reactive energy-to-pulse

0x10FA GATEQ R/W Unsigned
conversion in E2 path.
0x10FB GATECQ To set a threshold for no-load detection in E2 path. R/W Unsigned
2’
0x10E8 SCP To set a value to gain calibrate active power in E1 path. R/W
complement
2’
0x10EB SCI1 To set a value to gain calibrate current I1 RMS. R/W
complement

V98XX Datasheet
Address Register R/W Format
To set a value to gain calibrate active/reactive power in E2 2’

0x10E9 SCQ R/W
path. complement
2’
0x10EC SCI2 To set a value to gain calibrate current I2 RMS. R/W
complement
2’
0x10EA SCU To set a value to gain calibrate voltage RMS. R/W
complement
0x287B PHCCtrl1 Phase Compensation Control Register 1 R/W
0x287C PHCCtrl2 Phase Compensation Control Register 2 R/W
h
Bit[3:0] of CRPST: IBPHC and IAPHC, for phase
0x287F CRPST R/W
compensation
2’
ec
0x10ED PARAPC To set a value to offset calibrate active power in E1 path. R/W
complement
To set a value to offset calibrate active/reactive power in 2’

0x10EE PARAQC R/W
E2 path. complement
2’
0x10D6 DATAP Average active power in E1 path. R
complement
ot
2’
0x10D7 DATAQ Average active or reactive power calculated in E2 path. R
complement
2’
0x10D8 RMSU Average voltage RMS. R
complement
ng
2’
0x10D9 RMSI1 Average current I1 RMS. R
complement
2’
0x10DA RMSI2 Average current I2 RMS. R
complement
Va
10.18.2. Equations for Calibration
1. Equation for current/voltage RMS registers.
RMS = V × G × K Equation 10-14
where, V is the RMS value of the input signal (mV); G is the gain; and K is a constant, 1.8117×109.
2. Equation for power registers.
P = Vi × Gi × Vv × Gv × B × C Equation 10-15
where, Vi and Vv are the input current and voltage; Gi and Gv are the gains for current and voltage
respectively; C=cosθ for active power calculation, C=sinθ for reactive power calculation; B is a coefficient,
1.5413×109 for active power calculation or 2.4167×109 for reactive power calculation.
3. Equation for ratio factor of RMS and power.

V98XX Datasheet
The value acquired by Equation 10-14 or Equation 10-15 is the theoretical value of the register of the
RMS or power. It must be multiplied by a ratio factor to get the actual value (accurate to the second
decimal place).
Vn
D=
Value
Equation 10-16
where, Value is the theoretical value of the registers acquired by Equation 10-14 or Equation 10-15; D
is the ratio factor; and Vn is the rated voltage/current/power.
4. Equation for registers for phase compensation.
Please note that phase compensation must be executed after power calibration.
At a lower power factor (PF), the phase angle error can cause greater energy metering error. So
h
generally, the phase angle error is calibrated at PF=0.5L to ensure the metering accuracy. When PF=0.5L,
users can use a simple equation as follows to calculate the value N.
3011 𝑓𝑠𝑚𝑝𝑙
𝑁 = 𝑅𝑜𝑢𝑛𝑑( ×𝐸× ) Equation 10-17where,
ec
2 819200
N is the value, signed, to be set to the phase compensation control registers to correct the phase
angle error. A positive N indicates that current signal must be delayed, so “0” must be set to the sign
bit; a negative N indicates that the voltage signal must be delayed, so “1” must be set to the sign
bit;
ot
E is the energy metering error displayed in LCD screen of the calibration equipment;
fsmpl is the sampling frequency of the phase compensation circuit, Hz.
5. Equation for energy accumulation threshold.

ng
P ×T ×6400
PGAT = Equation 10-18
1024
where P is the power calculated by Equation 10-15; T is a time constant acquired via the equation:
3600 ×1000
T= Equation 10-19
PulseCons tan t ×Un ×In
Va
6. Equation for the gain calibration registers.
1 1
S = 231( - 1) + S1( ) Equation 10-20
1+ e 1+ e
where, S is the content to be set in the registers for gain calibration of active/reactive power or
current/voltage RMS, in the form of 2’-complement; S1 is the original value of the registers; e is the
error: when this equation is used for power gain calibration, e is equal to the error displayed in LCD
screen of the calibration equipment (E); when this equation is used for RMS gain calibration, e is equal
to the error (Eu/Ei) calculated by the following equations:
U -U
Eu = 1 n
Un
Equation 10-21
I -I
Ei = 1 b
Ib
Equation 10-22

V98XX Datasheet
where U1/I1 is the voltage/current RMS displayed in LCD screen of the meter to be calibrated, Un is the
rated voltage, and Ib is the base current.
7. Equation for power offset calibration registers.
C = a% × E1 × P Equation 10-23
where E1 is the error displayed in LCD screen of the calibration equipment when a%Ib is applied at power
factor 1.0; generally, a=1; and P is the power calculated by Equation 10-15.
8. Equation for no-load detection threshold registers.
Generally, the period for the first pulse output is used as the threshold for no-load detection, so the
threshold can be calculated as follows:
1 3600×1000 1
Equation 10-24where,
h
GATECP = T′ × × 𝑓𝑜𝑣𝑒𝑟𝑓𝑙𝑜𝑤 = 1 × × 𝑓𝑜𝑣𝑒𝑟𝑓𝑙𝑜𝑤
2 𝑃𝑢𝑙𝑠𝑒𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡×𝑈𝑛 × 𝐼𝑠 2
2
Un: rated voltage;
ec
1
Is: starting current. Generally, Is=0.4%Ib, and Is is used for no-load detection;
2
foverflow: accumulation frequency of the energy accumulator. When fMTCLK=3.2768MHz,

foverflow=12800Hz; when fMTCLK=32768Hz, foverflow=2979Hz.
ot
10.18.3. Steps for Calibration
10.18.3.1. Parameters Configuration

ng
Users must determine the following parameters when designing an energy meter:
- Parameters for a meter, including basic current, rated voltage, pulse constant and accuracy class.
- Parameters for design, including the current and voltage RMS when rated current and rated voltage
are applied.
Va
- The analog PGA gains of the current and voltage channels.
- The ratio factor (D) of RMS and power calculated via Equation 10-16.
- The threshold for energy-to-pulse conversion calculated via Equation 10-18.
- The threshold for no-load detection calculated via Equation 10-24.
When the above parameters are determined, no changes should be done to them.
10.18.3.2. Calibrating Active Energy
1. Gain calibration
At power fact of 1.0, apply 100% Un and 100% Ib to the calibration equipment.

V98XX Datasheet
Before calibration, read the error displayed in LCD screen of the calibration equipment (E), and read
the value of the gain calibration register (SCP, 0x10E8), S1, and then calculate the value for gain
calibration via Equation 10-20 and write it to the register SCP (0x10E8). After having written, if the error
displayed in LCD screen of the calibration equipment (E) is over the range of standard, indicating the difference
ratio correction is succeding.
2. Phase compensation
After gain calibration of power, apply 100%Ib and 100%Un to the calibration equipment when PF=0.5L,
to correct the phase angle error between the current and voltage signals.
Clear bit[5:0] of PHCCtrl1 (0x287B) and bit[2:1] of CRPST (0x287F) or bit[5:0] of PHCCtrl2 (0x287C)
and bit[4:3] of CRPST (0x287F), and then write the values calculated by Equation 10-17 to the register.
If N is positive, the sign bit is "0"; if N is negative, the sign bit is "1".
h
3. Offset calibration
Apply 5%Ib or 2% Ib and 100%Un to the calibration equipment when PF=1.0. Read the error (E)
displayed in LCD screen and calculate the value for power offset calibration by Equation 10-23, and write
ec
them to the registers for power offset calibration.
10.18.3.3. Calibrating Current RMS

ot
1. Clear the register SCI1 (0x10EB).
2. Apply 100%Ib to the calibration equipment at PF=1.0.
3. Read the current RMS I1 shown in the LCD screen of the calibration equipment (I1 is the product of
the value of the gain calibration register and the coefficient D).
ng
4. Calculate the value to gain calibrate the current signal of Channel I1 via Equation 10-20.
Note: When the current through the energy meter is less than the starting current, the current RMS I 1
is not shown in the LCD.
10.18.3.4. Calibrating Voltage RMS

Va
1. Clear the register SCU (0x10EA).
2. Apply 100% Un to the calibration equipment.
3. Read the voltage RMS U1 shown in the LCD screen of the calibration equipment (U 1 is the product of
the value of the gain calibration register and the coefficient D).
4. Calculate the value to gain calibrate the voltage signal of Channel U via Equation 10-20.

V98XX Datasheet
11. Interrupt
When POR/BOR, RSTn pin reset, WDT overflow event, power recovery event, IO/RTC wakeup event or
debugging event occurs, the interrupt control module is reset to its default state.
CLK1 provides clock pulses for the interrupt control module, so when the system enters Sleep or Deep
Sleep state, the interrupt control module stops running to save power. Each extended interrupt can be
gate controlled independently via configuring register PRCtrl1 (0x2D01).
11.1. Interrupt Sources
h
In the V98XX 41 events can trigger interrupts:
- 4 IO interrupts on low or high-to-low transitions;

- 4 transmitter data output interrupt of UART, and 2 transmitter data output interrupt of enhanced
ec
UART;
- 4 receiver data input interrupt of UART, and 2 receiver data input interrupt of enhanced UART;
- 4 timer overflow interrupts;
- 3 timer capture interrupts (TimerA);
- 2 overflow interrupt of enhanced UART;

ot
- 2 CF pulse output interrupts;
- 1 pulse per second (PPS) output interrupt;
- 1 RTC illegal data interrupt;
- 1 zero-crossing interrupt;
ng
- 1 power-down interrupt;
- 1 GPSI illegal data interrupt;
- 1 GPSI transmit interrupt;

- 1 comparator interrupt;
- 1 REF leakage interrupt.

Va
In the V98XX the interrupts triggered by peripheral events are called “Extended Interrupt”. They are
named after the polling sequence; for example, Interrupt 8 is named because the polling sequence of
the extended interrupt handler located at 43h is 8. Additionally, an extended interrupt may be triggered
by more than one event (interrupt sources); for example, both transmitter data output interrupt and
receiver data input interrupt of UART2 can trigger the program execution to service the interrupt handler
located at 43h (Interrupt 8).
Take Interrupt 8 as an example to introduce how to trigger an interrupt, service and clear the interrupt
flag, and detect the event that triggers an extended interrupt. Only when the global enable bit IE.7 and
the enable bit for Interrupt 8 (EIE.0) is set to 1, will Interrupt 8 be triggered if any one enabled peripheral
event occurs and the flag bits of Interrupt 8 and the interrupt event is set bit. The program has to detect
the interrupt source depending on the flags and enable bits of the peripheral event when the program
enters to the interrupt subroutine located at address 43h. The processor can respond to the interrupt
event by polling or interrupt handling. When an extended interrupt is responded, the program must clear
the flag of the peripheral event firstly, and then the flag of Interrupt 8.

V98XX Datasheet
In the V98XX, there are two tiers of interrupts: Interrupt Priority 1 and Interrupt Priority 0. Registers
IP (SFR 0xB8) and EIP (SFR 0xF8) can configure the priority of the interrupts. Interrupt Priority 1 takes
precedence over Interrupt Priority 0. In addition to an assigned priority level (1 or 0), each interrupt has
a polling sequence. An interrupt with a small polling sequence number means that it must be serviced
firstly when two interrupts of the same tier occur simultaneously. If two interrupts of different priority
occur, the one of Interrupt Priority 1 is serviced firstly. Only an interrupt of higher priority level can break
the service routine of the interrupt currently being serviced; when the new interrupt is serviced, the
program will go back where it was interrupted and serve the last interrupt.
Table 11-1 Interrupt Sources
Enable bit
Enable Flag of
Polling Vector Interrupt of Flag of
Description bit of peripheral
h
sequence address No.1 peripheral interrupt
interrupt event
event
0
33h 6 Reserved.
ec
(highest)
IO interrupt 0
(INT0), triggered
1 03h 0 on low level or IE.0 TCON.1
high-to-low
transition.
ot
Timer0 interrupt
2 0Bh 1 IE.1 TCON.5
(TF0).
IO interrupt 1
(INT1), triggered
ng
3 13h 2 on low level or IE.2 TCON.3

high-to-low
transition.
Timer1 interrupt
4 1Bh 3 IE.3 TCON.7
(TF1).
Va
5 23h 4 Reserved.
Timer2 interrupt
6 2Bh 5 IE.5 T2CON.7
(TF2, EXF2).
Receiver data input

interrupt of UART1 SCON1.0
(RI1).
7 3Bh 7 IE.6
Transmitter data
output interrupt of SCON1.1
UART1 (TI1).
8 43h 8 Transmitter data EIE.0 ExInt2IE.0 EXIF.4 ExInt2IFG.0
1 When Keil IDE is applied, users must use Interrupt No. to check the interrupts.

V98XX Datasheet
Enable bit
Enable Flag of
interrupt event
event
output interrupt of
UART2.
Receiver data input

ExInt2IE.1 ExInt2IFG.1
interrupt of UART2.
Transmitter data
output interrupt of ExInt2IE.2 ExInt2IFG.2
UART4.
h
Receiver data input
interrupt of UART4.
Timer overflow
ec
interrupt of UART2.
Timer overflow
interrupt of UART4.
Reserved.
ot
CF pulse output
interrupt of E1 path
Transmitter data
output interrupt of
UART3.
ng
Receiver data input

interrupt of UART3.
Transmitter data
output interrupt of ExInt3IE.2 ExInt3IFG.2
UART5.
Va
Receiver data input

interrupt of UART5.
9 4Bh 9 EIE.1 EXIF.5
Timer overflow
interrupt of UART3.
Timer overflow
interrupt of UART5.
Pulse per second

(PPS) output ExInt3IE.6 ExInt3IFG.6
interrupt of RTC.
CF pulse output
interrupt of E2 ExInt3IE.7 ExInt3IFG.7
path.

V98XX Datasheet
Enable bit
Enable Flag of
interrupt event
event
Illegal data
interrupt of RTC.
Transmitter data
output interrupt,
receiver data input RCIE
output, and
overflow interrupt SDIE ExInt4IFG.1
h
of EUART1 ExInt4IE.1
RIF/SIF/OVIF
(0x2A04)
ec
IO interrupt 2
(INT2), triggered
on high-to-low
transition.
IO interrupt 3
ot
(INT3), triggered
on high-to-low
10 53h 10 EIE.2 EXIF.6
transition.
REF leakage
interrupt.
ng
X0EN (bit7
Zero-crossing of
0x287A) ExInt4IFG.5
interrupt.
ExInt4IE.5
Transmitter data
Va
output interrupt,
receiver data input RCIE
output, and
overflow interrupt SDIE ExInt4IFG.6
of EUART2 ExInt4IE.6
RIF/SIF/OVIF
(0x2B04)
Reserved.
TimerA overflow
interrupt.
11 5Bh 11 EIE.3 EXIF.7
TimerA capture
interrupt 0.

V98XX Datasheet
Enable bit
Enable Flag of
interrupt event
event
TimerA capture
interrupt 1.
TimerA capture
interrupt 2.
Illegal data
interrupt of GPSI.
h
Transmit interrupt
of GPSI.
Comparator
ec
interrupt.
Reserved.
12 Power-down
63h 12 EIE.4 EICON.3
(lowest) interrupt.
ot
ng
Va

V98XX Datasheet
EIE SFR/
IE SFR EIP/IP SFR Priority
Extended interrupt enable registers
0 1
INT0 0 IT0
IO interrupt 0
1
IE0
IT0
Respond to the interrupt to clear the flag

bit.
Timer0 TF0
bit.
INT1 0 IT1
IO interrupt 1 1
IE1
IT1
bit.
Timer1 TF1
bit.
TF2
Timer2
EXF2
h
RI1
UART1
Polling sequence
TI1
RI
UART2
Interrupt 8
and
UART4
TI
EXIF.4
CPU
TF0
ec
CF1 IR7
RI
UART5
and TI
UART3
Interrupt 9 TF0 EXIF.5
RT
IR6
C
CF2 IR7
RTC IR0
EUART1 IR1
EUART2 IR6
ot
IO interrupt INT2
EXIF.6
Interrupt 10 2
IO interrupt INT3
3
REF leakage
IR4
interrupt
Zero-
IR5
crossing
IR0
IR1
TimerA
IR2
IR3 EXIF.7
Interrupt 11
IR4
ng
GPSI
IR5
Comparator IR6
Interrupt 12 PFI
Enable bit EIE SFR Enable bit Global enable bit

(EA)
Figure 11-1 Interrupt Logic

Va
11.2. Interrupt Control Registers

Table 11-2 IE (SFR 0xA8)
Bit Description
Global interrupt enable bit. EA overrides individual interrupt enable bit.
IE.7 EA 0: to disable all interrupts.
1: indicating that each interrupt is enabled or disabled by its individual enable bit.

V98XX Datasheet
Bit Description
UART1 interrupt enable bit.
1: to enable transmitter data output interrupt of UART1 triggered by the flag TI1 or
IE.6 ES1
receiver data interrupt of UART1 triggered by the flag RI1.
0: to disable the UART1 interrupt.
Timer2 interrupt enable bit.
IE.5 ET2 0: to disable Timer2 interrupt (TF2 or EXF2).
1: to enable the interrupt triggered by flag TF2 or EXF2.
IE.4 ES0 Reserved
h
IE.3 ET1 0: to disable Timer1 interrupt (TF1).
ec
1: to enable the interrupt generated by the flag TF1.
IO Interrupt 1 enable bit.
0: to disable IO Interrupt 1.
IE.2 EX1
1: to enable the interrupt triggered by high-to-low transition or low level on the port
ot
INT1.
IE.1 ET0 0: to disable Timer0 interrupt (TF0).
1: to enable the interrupt triggered by the flag TF0.

ng
IO Interrupt 0 enable bit.
0: to disable IO Interrupt 0.
IE.0 EX0
1: to enable the interrupt triggered by high-to-low transition or low level on the port
INT0.
Va
Table 11-3 EIE (SFR 0xE8)
Bit Description
EIE.7-5 Reserved. Read out as 1.
Interrupt 12 (Power-down Interrupt, PFI) enable bit.
EIE.4 0: disable;
1: enable.
Interrupt 11 enable bit.
EIE.3 0: disable;
1: enable.

V98XX Datasheet
Bit Description
EIE.2 0: disable;
1: enable.
EIE.1 0: disable;
1: enable.
h
EIE.0 0: disable;
1: enable.
ec
Table 11-4 EXIF (SFR 0x91)
Bit Description
Interrupt 11 flag. When this bit is set to 1, it indicates that Interrupt 11 was
EXIF.7 IE5 triggered. IE5 must be cleared by software. When Interrupt 11 was enabled,
setting IE5 by software can trigger an interrupt.
ot
ng
EXIF.3 Reserved Read out as 1.

Va
EXIF.2-
Reserved Read out as 0.
0
Table 11-5 EICON (SFR 0xD8)
Bit Description
UART1 baud rate double enable bit. Set this bit to 1 to double the baud rate
EICON.7 SMOD1
for UART1 serial interface.
EICON.6 Reserved Read out as 1.
EICON.5 Reserved.
EICON.4 Reserved.

V98XX Datasheet
Bit Description
Power-down Interrupt (Interrupt 12) flag. When this bit is set to 1, it indicates
that a power-down interrupt was triggered. This flag must be cleared by
EICON.3 PFI software before exiting the interrupt service routine. Otherwise, the interrupt
will occur again. When Interrupt 12 was enabled, setting this flag by software
can trigger a power-down interrupt.
EICON.2-
Reserved. Read out as 0.
0
Table 11-6 IP (SFR 0xB8)
Bit Description
h
IP.7 Reserved. Read out as 1.
Set this bit to 1 to configure UART1 transmit or receive interrupt (RI1 or TI1) to
IP.6 PS1
ec
Interrupt Priority 1. Clear this bit to configure it to Interrupt Priority 0.
Set this bit to 1 to configure Timer2 interrupt (TF2 or EXF2) to Interrupt Priority 1.
IP.5 PT2
Clear this bit to configure it to Interrupt Priority 0.
IP.4 PS0 Reserved

ot
Set this bit to 1 to configure Timer1 interrupt (TF1) to Interrupt Priority 1. Clear this
IP.3 PT1
bit to configure it to Interrupt Priority 0.
Set this bit to 1 to configure IO Interrupt 1 to Interrupt Priority 1. Clear this bit to
IP.2 PX1
configure it to Interrupt Priority 0.
Set this bit to 1 to configure Timer0 interrupt (TF0) to Interrupt Priority 1. Clear this
ng
IP.1 PT0
bit to configure it to Interrupt Priority 0.
Set this bit to 1 to configure IO Interrupt 0 to Interrupt Priority 1. Clear this bit to
IP.0 PX0
configure it to Interrupt Priority 0.
Table 11-7 EIP (SFR 0xF8)

Va
Bit Description
EIP.7-
Reserved. Read out as 1.
5
Set this bit to 1 to configure Interrupt 12 (Power-down interrupt) Interrupt Priority 1. Clear
EIP.4
this bit to configure it to Interrupt Priority 0.
Set this bit to 1 to configure Interrupt 11 Interrupt Priority 1. Clear this bit to configure it to
EIP.3
Interrupt Priority 0.
EIP.2
EIP.1

V98XX Datasheet
Bit Description
EIP.0
11.3. Interrupt Processing
Main Program
h
RETI RETI RETI
Interrupt
ISR ISR ISR
Priority 1
ec
RETI
Interrupt
ISR ISR ISR ISR ISR ISR
Priority 0
A B C D Polling sequence:
low to high
Figure 11-2 Interrupt Processing

ot
The preceding figure illustrates the interrupt processing in the V98XX. When an enabled interrupt
occurs,
- The program jumps to the interrupt vector address to execute the interrupt service routine (ISR) of
the interrupt. An ISR being executed can only be interrupted by one of the interrupt with higher
priority. Each ISR ends with an RETI (return from interrupt) instruction, as shown as A in the
ng
preceding figure.
- After executing the RETI, the program returns to the place where it was interrupted, as if it did not
leave off, to execute the next instruction that would have been executed if the interrupt had not
occurred. The program always completes an instruction in progress before servicing an interrupt. If
an instruction executed in progress is RETI, or a write operation to registers including IP SFR, IE
SFR, EIP SFR, and EIE SFR, the program will complete one additional instruction before servicing the
ISR.
In the V98XX, Interrupt Priority 1 has higher priority than Interrupt Priority 0. So, the ISR of Interrupt
Va
-
Priority 0 only can be interrupted by the ISR of Interrupt Priority 1, as shown as B and C in the
preceding figure.
- An ISR of Interrupt Priority 0 can be intruded by one of Interrupt Priority 1. When the latter one is
executed, the program will return to the place at the vector address of the former one where it was
interrupted to execute the ISR, and then, execute the instruction RETI to finish the ISR, as shown
as B in the preceding figure.
- When two interrupts of the same tier (Interrupt Priority 1 or Interrupt Priority 0) occur simultaneously,
the polling sequence of them is observed, as shown as D in the preceding figure.
- Interrupt latency depends on the current state of the MCU.

 The shortest interrupt latency is equal to five instruction cycles: one to detect the interrupt, and
four to perform the LCALL to the ISR.
 The longest latency (equal to thirteen instruction cycles) occurs when the MCU is currently
executing an RETI instruction followed by a MUL or DIV instruction. The thirteen instruction
cycles in this case are: one to detect the interrupt, three to complete the RETI, five to execute
the DIV or MUL, and four to execute the LCALL to the ISR. For an interrupt with the maximum
latency, the interrupt latency is 52 (13x4) clock cycles.

V98XX Datasheet
- To ensure that high-to-low-transition-triggered interrupts can be detected, such as IO Interrupt
0/1/2/3, the level on the corresponding ports should be held high for at least four clock cycles and
then low for no less than four clock cycles. If a level-triggered interrupt occurs when the flag has not
been set bit, or an interrupt with higher priority is in process which blocks the program jumping to
the interrupt vector address to execute its ISR, the interrupt signal will hold until it is to be serviced.
11.4. Extended Interrupts
11.4.1. Interrupt 8
Interrupt 8 can be triggered by 7 interrupt events which are listed in the following table. Bit ExInt2
h
(bit0 of PRCtrl1, 0x2D01) gate controls Interrupt 8.
Table 11-8 Interrupt Events to Trigger Interrupt 8
ec
Interrupt 8
Interrupt Event Enable bit Flag (R/W)
Vector Address Enable Bit Flag (R/W)
Transmitter data output

interrupt of UART2
ot
Receiver data input interrupt of
UART2
Transmitter data output

interrupt of UART4
IE.7 EXIF.4
43h Receiver data input interrupt of
ng
EIE.0 (IE2) ExInt2IE.3 ExInt2IFG.3

UART4
Timer overflow interrupt of

UART2

UART4
Va
CF pulse interrupt of E1 path ExInt2IE.7 ExInt2IFG.7
Table 11-9 Extended Interrupt Flag (Request) Register (ExInt2IFG, 0x2840)
0x2840, R/W, Extended Interrupt Flag (Request) Register, ExInt2IFG
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
IR7 - IR5 IR4 IR3 IR2 IR1 IR0
Default 0 X 0 0 0 0 0 0

V98XX Datasheet
1: an interrupt request occurred; 0: no interrupt request occurred; X: do not care.
A flag bit can be set to 1 only when the corresponding interrupt was enabled. When an interrupt was
enabled, writing 1 to the corresponding flag bit can trigger the interrupt. Otherwise, however, cannot.
Write 0 to a bit can clear the corresponding interrupt flag.
Table 11-10 Extended Interrupt Input Type Register (ExInt2IN, 0x2841)
0x2841, R/W, Extended Interrupt Input Type Register, ExInt2IN
h
EDG7I - EDG5I EDG4I EDG3I EDG2I EDG1I EDG0I
ec
Default 1 X 1 1 1 1 1 1
These bits must be set to their default values for proper operation.
Table 11-11 Extended Interrupt Output Type Register (ExInt2OUT, 0x2842)
0x2842, R/W, Extended Interrupt Output Type Register, ExInt2OUT

ot
- - - - - - - EDGO
Default - - - - - - - 1
ng
Table 11-12 Extended Interrupt Enable Register (ExInt2IE, 0x2843)
0x2843, R/W, Extended Interrupt Enable Register, ExInt2IE

Va
IE7 - IE5 IE4 IE3 IE2 IE1 IE0
Default 0 X 0 0 0 0 0 0
1: enable; 0: disable; X: do not care.
Table 11-13 Extended Interrupt Pending Register (ExInt2OV, 0x2844)
0x2844, R/W, Extended Interrupt Pending Register, ExInt2OV
IPND7 - IPND5 IPND4 IPND3 IPND2 IPND1 IPND0
Default 0 X 0 0 0 0 0 0

V98XX Datasheet
If an interrupt is triggered again when the corresponding flag in the register ExInt2IFG has not been
cleared yet, the corresponding pending bit of this register will be set to 1. The pending bit is just an
indication flag, nothing to do with the interrupt. It must be cleared by the program.
11.4.2. Interrupt 9
h
Table 11-14 Interrupt Event to Trigger Interrupt 9
Interrupt 9
ec
Vector Enable Interrupt Event Enable Bit Flag (R/W)
Flag (R/W)
Address Bit
Transmitter data output interrupt

of UART3(V98XX)
ot
Receiver data input interrupt of
UART3(V98XX)
Transmitter data output interrupt

of UART5
ng
IE.7 EXIF.5 Receiver data input interrupt of

4Bh ExInt3IE.3 ExInt3IFG.3
UART5
EIE.1 (IE3)
UART3(V98XX)

UART5
Va
Pulse per second interrupt of RTC ExInt3IE.6 ExInt3IFG.6
CF pulse interrupt of E2 path ExInt3IE.7 ExInt3IFG.7
IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0
Default 0 0 0 0 0 0 0 0

V98XX Datasheet
h
EDG7I EDG6I EDG5I EDG4I EDG3I EDG2I EDG1I EDG0I
ec
Default 1 1 1 1 1 1 1 1
Table 11-17 Extended Interrupt Output Type Register (ExInt3OUT, 0x284A)
0x284A, R/W, Extended Interrupt Output Type Register, ExInt3OUT

ot
- - - - - - - EDGO
Default - - - - - - - 1
ng
Table 11-18 Extended Interrupt Enable Register (ExInt3IE, 0x284B)
0x284B, R/W, Extended Interrupt Enable Register, ExInt3IE

Va
IE7 IE6 IE5 IE4 IE3 IE2 IE1 IE0
Default 0 0 0 0 0 0 0 0
Table 11-19 Extended Interrupt Pending Register (ExInt3OV, 0x284C)
0x284C, R/W, Extended Interrupt Pending Register, ExInt3OV
IPND7 IPND6 IPND5 IPND4 IPND3 IPND2 IPND1 IPND0
Default 0 0 0 0 0 0 0 0

V98XX Datasheet
0x284C, R/W, Extended Interrupt Pending Register, ExInt3OV
If an interrupt occurs again when the corresponding flag in the register ExInt3IFG has not been cleared
yet, the corresponding pending bit of this register will be set to 1. The pending bit is just an indication
flag, nothing to do with the interrupt. It must be cleared by the program.
11.4.3. Interrupt 10
Interrupt 10 can be triggered by 7 interrupt/ 5 interrupt events/which are listed in the following table.
Bit ExInt4 (bit2 of PRCtrl1, 0x2D01) gate controls Interrupt 10.
h
Interrupt 10
ec
Vector Enable Flag Interrupt Event Enable Bit Flag (R/W)
Address Bit (R/W）
RTC illegal data interrupt ExInt4IE.0 ExInt4IFG.0
Transmitter data output interrupt, receiver

ot
data input interrupt and timer overflow ExInt4IE.1 ExInt4IFG.1
interrupt of EUART1(V98XX)
IO Interrupt 2 (INT2), triggered on high-

to-low transition
IE.7 EXIF.6
ng
53h IO Interrupt 3 (INT3), triggered on high-

EIE.2 (IE4) ExInt4IE.3 ExInt4IFG.3
to-low transition
REF leakage interrupt ExInt4IE.4 ExInt4IFG.4
Zero-crossing interrupt ExInt4IE.5 ExInt4IFG.5
Transmitter data output interrupt, receiver

Va
data input interrupt and timer overflow ExInt4IE.6 ExInt4IFG.6

interrupt of EUART2
- IR6 IR5 IR4 IR3 IR2 IR1 IR0
Default X 0 0 0 0 0 0 0

V98XX Datasheet
- EDG6I EDG5I EDG4I EDG3I EDG2I EDG1I EDG0I
h
Default X 1 1 1 1 1 1 1
ec
Table 11-23 Extended Interrupt Output Type Register (ExInt4OUT, 0x2852)
- - - - - - - EDGO
ot
Default - - - - - - - 1
Table 11-24 Extended Interrupt Enable Register (ExInt4IE, 0x2853)

ng
0x2853, R/W, Extended Interrupt Enable Register, ExInt4IE
- IE6 IE5 IE4 IE3 IE2 IE1 IE0
Default X 0 0 0 0 0 0 0

Va
Table 11-25 Extended Interrupt Pending Register (ExInt4OV, 0x2854)
- IPND6 IPND5 IPND4 IPND3 IPND2 IPND1 IPND0
Default X 0 0 0 0 0 0 0

V98XX Datasheet
11.4.4. Interrupt 11
Interrupt 11
Interrupt Event Enable Bit Flag (R/W)
Vector Address Enable Bit Flag (R/W）
TimerA overflow interrupt ExInt5IE.0 ExInt5IFG.0
TimerA capture interrupt 0 ExInt5IE.1 ExInt5IFG.1
h
TimerA capture interrupt 1 ExInt5IE.2 ExInt5IFG.2
IE.7 EXIF.7
5Bh TimerA capture interrupt 2 ExInt5IE.3 ExInt5IFG.3
EIE.3 (IE5)
ec
Illegal data interrupt of GPSI* ExInt5IE.4 ExInt5IFG.4
Transmit interrupt of GPSI* ExInt5IE.5 ExInt5IFG.5
Comparator interrupt ExInt5IE.6 ExInt5IFG.6
*When bit GPSI (bit6 of PRCtrl0, 0x2D00) is set to 1, GPSI (general-purpose serial interface) is
ot
enabled. Writing of illegal data or transmit completion will trigger interrupt to CPU.
Table 11-27 Extended Interrupt Flag (Request) Register (ExInt5IFG, 0x28A2)
0x28A2, R/W, Extended Interrupt Flag (Request) Register, ExInt4IFG

ng
- IR6 IR5 IR4 IR3 IR2 IR1 IR0
Default X 0 0 0 0 0 0 0
Va
Table 11-28 Extended Interrupt Input Type Register (ExInt5IN, 0x28A3)
0x28A3, R/W, Extended Interrupt Input Type Register, ExInt5IN
- EDG6I EDG5I EDG4I EDG3I EDG2I EDG1I EDG0I
Default X 1 1 1 1 1 1 1
Table 11-29 Extended Interrupt Output Type Register (ExInt5OUT, 0x28A4)

V98XX Datasheet
- - - - - - - EDGO
Default - - - - - - - 1
Table 11-30 Extended Interrupt Enable Register (ExInt5IE, 0x28A5)
0x28A5, R/W, Extended Interrupt Enable Register, ExInt4IE
h
- IE6 IE5 IE4 IE3 IE2 IE1 IE0
Default X 0 0 0 0 0 0 0
ec
Table 11-31 Extended Interrupt Pending Register (ExInt5OV, 0x28A6)
0x28A6, R/W, Extended Interrupt Pending Register, ExInt5OV

ot
- IPND6 IPND5 IPND4 IPND3 IPND2 IPND1 IPND0
Default X 0 0 0 0 0 0 0
ng
Va

V98XX Datasheet
12. UART/Timers
When power-on or brown out reset (POR/BOR), RSTn pin reset, WDT overflow, power recovery event,
IO/RTC wakeup event or debugging reset occurs, all the timers and the UART serial interfaces are reset
to their default states. In Sleep or Deep Sleep, they stop working. Each extended UART serial interface
and TimerA can be gate controlled independently via configuring register PRCtrl0 (0x2D00) and PRCtrl1
(0x2D01).
12.1. Timers/Counters
The V98XX can provide users with timers listed as follows:
h
 TimerA, a 16-bit timer, with 3 compare/capture modules, gate controlled independently;
 Timer0, Timer1 and Timer2 of 8052 microcontroller. They work as general timers; furthermore,
ec
Timer1 can work as the baud rate generator of UART1;
 The general timer and specific baud rate generator of each extended UART serial interface
(UART2/UART3(V98XX)/UART4/UART5). Each interface can be gate controlled independently. The
general timer has the same function with Timer0, an overflow event of which will set the flag bit to
1, which will be cleared by executing interrupt service routine (ISR) or by polling interrupt sources,
and generate an interrupt to the CPU. The specific baud rate generator has the same function with
ot
Timer1: it can be used as a general timer, an overflow event of which can set the flag bit to 1 but
cannot generate an interrupt to the CPU.
In this section, only TimerA, Timer0, Timer1 and Timer2 are introduced. The general timers in extended
UART serial interfaces are introduced in “UART”.
ng
12.1.1. TimerA
TimerA is a 16-bit timer/counter, and has 4 operation modes. It has 3 compare/capture modules, and
3 configurable output units with 8 output modes. Bit TimerA (bit0 of PRCtrl0, 0x2D00) gate controls
TimerA.
Va

V98XX Datasheet
IDx Timer
MCx
1/128 00
16-bit TAR
0 TSEL 01
fMCU 15 0 Mode EQU0
1 10
1 11
TAIFG
CLR
TACCR0
TACCR1
TACCR2
h
Comparator2
CMx
COV
16-bit TACCR2
capture
TA2 15 0 EQU2
mode
ec
0
CCI CCIFG
1
SCCI Latch
CAP
ot
OUT
Output
Unit 2
EQU0
Logic OUT2 Signal
ng
OUTMODx
Figure 12-1 TimerA Architecture
Table 12-1 TimerA-Related Registers

Va
Address Description
0x2900 TACTL, Timer A Control Register R/W
0x2902 Low byte

TAR, TimerA Timer/Counter Register R
0x2903 High byte
0x2904 TACCTL0, low byte

Timer A Compare/Capture Control Register 0 R/W
0x2905 TACCTH0, high byte
0x2906 TACCTL1, low byte Timer A Compare/Capture Control Register 1 R/W

V98XX Datasheet
Address Description
0x2908 TACCTL2, low byte

Timer A Compare/Capture Control Register 2 R/W
0x290A~0x290B TACCR0, Timer A Compare/Capture Register 0 R/W
0x290C~0x290D TACCR1, Timer A Compare/Capture Register 1 R/W
0x290E~0x290F TACCR2, Timer A Compare/Capture Register 2 R/W
h
Table 12-2 Timer A Counter/Timer Register (TAR, 0x2902~0x2903)
ec
0x2902~0x2903, R, Timer A Timer/Counter Register, TAR
0x2903 Bit[7:0] The registers give the value of TimerA (TAR), of which the low byte is in
the register located at address 0x2902, and the high byte is in 0x2903.
0
ot
It is read-only, and can be reset by software. When TimerA overflows, an
0x2902 Bit[7:0]
interrupt is generated to the CPU.
Table 12-3 Timer A Control Register (TACTL, 0x2900)
0x2900, R/W, TimerA Control Register, TACTL

ng
These bits are used to select the divider for the input clock.
Bit7 ID1
ID1 ID0 Description
0 0 The input clock is divided by 2;

Va
0
Bit6 ID0
1 1 The input clock is divided by 16.
To select operation mode, as illustrated in figure “Operation Modes for TimerA”.
Bit5 MC1 0 MC1 MC0 Description
0 0 Stop Mode: the timer is halted.

V98XX Datasheet
0x2900, R/W, TimerA Control Register, TACTL
Up Mode: the timer counts up to the value of TACCR0, and

0 1
recount from 0000h.
Continuous Mode: the timer counts up to FFFFh, and recounts

Bit4 MC0 1 0
from 0000h.
Up/Down Mode: the timer counts up to the value of TACCR0,

1 1
and then, back down to 0000h.
Bit3 TSEL - To select the clock source for the timer. 0: fMCU /128; 1: fMCU.
h
Set the bit CLR to 1 to clear the register TAR, meanwhile, [ID1, ID0]=00; if
Bit2 CLR 0 the timer works in Up/Down mode, the timer rolls over to 0000h, and back up
to the value of TACCR0.
ec
When the bit EX3 (EIE.3) is set to 1, set this bit to 1 to enable TimerA overflow
Bit1 TAIE 0
interrupt. When this bit is cleared, the interrupt is disabled.
TimerA overflow interrupt flag.
In the Up Mode, when the timer rolls over to 0000h from the value of TACCR0,
TAIFG is set bit.
ot
Bit0 TAIFG 0 In the Continuous Mode, when the timer rolls over to 0000h from FFFFh, TAIFG
is set bit.
In the Up/Down Mode, when the timer counts down to 0000h from 0001h,
TAIFG is set bit.
ng
Va

V98XX Datasheet
FFFFh
Continuous Mode
Stop Mode Up to FFFFh, rolls over to 0000,
Timer is halted. back up to FFFFh, etc.
h
FFFFh FFFFh
TACCR0 TACCR0
Up Mode
Up to value specified by TACCR0,
rolls over to 0000, back up to
TACCR0 value, etc.
ec Up/Down Mode
Up to value specified by TACCR0,
counts down to 0000h, back up
to TACCR0 value, etc.
ot
Figure 12-2 Operation Modes for TimerA
When either bit MC1 or MC0 is not cleared, or the clock source is active, the timer starts counting. In
Up or Up/Down Mode, when the register TACCR0 is cleared, the timer stops running, and it may then be
restarted counting in the up direction from zero when a non-zero value is written into the register TACCR0.
ng
In Up Mode, when the value of the register TACCR0 is changed while the timer is running,
- if the new value is not less than the former value or current counts, the timer will count up to
the new TACCR0 value, and then rolls over to 0000h;
- if the new value is less than current counts, the timer will count to the former value firstly, rolls
over to 0000h, and then counts to the new TACCR0 value.
Va
In Up/Down Mode,
- when the value of the register TACCR0 is changed while the timer is counting in the down
direction, the timer continues its direction until it counts down to 0000h, and then it counts up
to the new value of TACCR0 from 0000h;
- when the value of the register TACCR0 is changed while the timer is counting in the up direction:
 if the new value is not less than the former value or current counts, the timer counts up to
the new TACCR0 value before counting down;
 if the new value is less than current counts, the timer will count to the former value firstly,
counts back to 0000h, and then counts up to the new TACCR0 value.
In Continuous Mode, the output frequency is configurable, as illustrated in the following figure. This
operation mode can be used to generate independent output frequencies.

V98XX Datasheet
TACCR0b
FFFFh
TACCR1b TACCR0c
TACCR1a TACCR1e
TACCR1d TACCR0d
TACCR0a TACCR1c
TACCR1f
h
t0 t0 t0
t1 t1 t1 t1 t1
ec
Figure 12-3 Configuring Output Frequency in Continuous Mode
As illustrated in the above figure, TACCR0a and TACCR1a are the values of the registers TACCR0 and
TACCR1 at the moment of Ta0 and Ta1, and TACCR0b and TACCR1b are the values of the registers
TACCR0 and TACCR1 at the moment of Tb0 (Tb0=Ta0+t0) and Tb1 (Tb1=Ta1+t1), and so forth. When
ot
the interrupt is enabled (CCIE=1, Bit4, TACCTLx), an interrupt will be generated at the moment of Ta0
and Ta1 independently and at an interval (t0 or t1). The interrupt flags CCIFG (Bit0 of TACCTLx, x=0 and
1) are set bit respectively. Up to 3 independent output frequencies can be generated using all
capture/compare registers. In this application, when the timer rolls over to 0000h from FFFFh, the bit
TAIFG is still set.
ng
Table 12-4 Timer A Compare/Capture Control Registers (0x2904~0x2909)
0x2904~0x2905/0x2906~0x2907/0x2908~0x2909, R/W, TimerA Compare/Capture

Control Register x , TACCTLx~TACCTHx
2
Byte Bit Default Description

Va
Bit15 CM1 To select the capture mode.
CM1 CM0 Description

High
byte 0 0 To disable capture mode.
0
TACCTHx Bit14 CM0 0 1 To capture signals on the rising edge.
0x2905 1 0 To capture signals on the falling edge.
0x2907 1 1 To capture signals on both edges.
0x2909 Bit[13:11] Reserved 0 Read only.
Bit10 SCCI 0 To latch the input signal (determined by bits CCISx)
2 x can be equal to 0/1/2 to represent the TimerA Capture/Compare Module 0/1/2 control register.

V98XX Datasheet
2

with the EQUx signal, and read it via the bit CCI.
Note: when the value of TAR is equal to the value of

TACCRx, TimerA output the EQUx signal, of which x can
be 0, 1 or 2.
Bit9 Reserved 0 Read-only. This bit is read out as 0 all the time.
To select capture or compare mode.
Bit8 CAP 0 0: Compare Mode;
h
1: Capture Mode.
Bit7 OUTMOD2 To select the output mode, see figure Output on Pin TA1
ec
in Up Mode for description of the pulse output.
Bit7 Bit6 Bit5 Mode Description

Bit6 OUTMOD1
To output the value of the
0 0 0 Output
bit OUT on the pin TAx.
ot
When TAR=TACCRx
(x=0~2), the output on
the corresponding pin TAx
0 0 1 Set is set bit. It remains the
state until a reset of the
timer, or until another
ng
output mode is selected.

Low byte
When TAR= TACCRx
TACCTLx
0x2904 0 the corresponding pin TAx
is toggled. When
0x2906 Toggle TAR=TACCR0, the output
Va
0 1 0
0x2908 Reset on the corresponding pin
Bit5 OUTMOD0
TAx is reset.
And this mode is not for

the output on the pin TA0.
When TAR= TACCRx

Set is set. When
0 1 1 TAR=TACCR0, the output
Reset
on the corresponding pin
TAx is reset.
This mode is not for the

V98XX Datasheet
2

output on the pin TA0.
When TAR= TACCRx

1 0 0 Toggle
is toggled.
When TAR= TACCRx

h
1 0 1 Reset
is reset. It remains reset
until another output
mode is selected.
ec
When TAR= TACCRx
is toggled. When
Toggle
ot
Set on the corresponding pin
TAx is set.

When TAR= TACCRx

ng

is reset. When
Reset
Set on the corresponding pin
TAx is set.
Va

Interrupt enable bit, to enable TimerA compare/capture

interrupt.
Bit4 CCIE 0
0: disable;
1: enable.
To read the captured input signal (via configuring the

Bit3 CCI 0
bits CCIS1/CCIS0).
When the bits OUTMOD2, OUTMOD1 and OUTMOD0 are

Bit2 OUT 0 cleared, the value of this is output on the pins TAx
(x=0~2).

V98XX Datasheet
2
Capture overflow flag.
In capture mode, when COV is read out as 0, the

capture signal is reset, and the capture event cannot
set this bit to 1.
Bit1 COV 0 In capture mode, when COV is read out as 1, if a
capture event occurs when the value of the last capture
has not been read out, COV is set bit.
h
This bit must be reset by program. Reading the
captured signal cannot reset this bit.
Compare / capture interrupt flag.
ec
In capture mode: when the value of the register TAR is
captured into the registers TACCR0/1/2, this flag bit will
be set bit.
In compare mode: when the value of the register TAR

is equal to that of the registers TACCR0/1/2 (EQUx
ot
signal), this flag bit will be set bit.
Bit0 CCIFG 0
In Compare/Capture Module 0, when the interrupt
request is responded, this flag bit will be reset
automatically.
ng
In Compare/Capture Module 1/2, when the interrupt

request is responded, the CCIFG flag is reset; if the
corresponding enable bit is cleared, this flag bit still will
be set bit, which must be cleared by program, but no
interrupt will be generated.
Va

V98XX Datasheet
FFFFh
TACCR0
TACCR1
0h
OUTMODx=1, Set
OUTMODx=2, Toggle/Reset
h
OUTMODx=3, Set/Reset
OUTMODx=4, Toggle
ec
OUTMODx=5, Reset
OUTMODx=6, Toggle/Set
OUTMODx=7, Reset/Set
TAIFG
ot
CCIFG
TAR=TACCR0 (EQU0)
CCIFG
TAR=TACCR1 (EQU1)
ng
Figure 12-4 Output on Pin TA1 in Up Mode

Va

V98XX Datasheet
FFFFh
TACCR0
TACCR1
0h
OUTMODx=1, Set
h
OUTMODx=4, Toggle
ec
OUTMODx=5, Reset
ot
TAIFG
CCIFG
TAR=TACCR0 (EQU0)
CCIFG
TAR=TACCR1 (EQU1)
ng
Figure 12-5 Output on Pin TA1 in Continuous Mode

Va

V98XX Datasheet
FFFFh
TACCR0
TACCR1
0h
OUTMODx=1, Set
h
OUTMODx=4, Toggle
ec
OUTMODx=5, Reset
ot
TAIFG
CCIFG
TAR=TACCR0 (EQU0)
CCIFG
TAR=TACCR1 (EQU1)
ng
Figure 12-6 Output on Pin TA1 in Up/Down Mode

As illustrated in the above figures, users can configure the bits OUTMOD2, OUTMOD1 and OUTMOD0
to select the output mode. When these bits are set to 0b010/011/100/110/111, the frequency and duty
cycle of the output pulse changes, generating PWM signals (pulse width modulation).
Va
12.1.2. Timer0/Timer1/Timer2
12.1.2.1. Timer Rate Control
When the bits in CKCON (SFR 0x8E), CKCON.5, CKCON.4 and CKCON.3, are set bit, the associated
timers increment by ones every clock cycle (clk). When they are cleared, the associated timers increment
by ones every 12 clock cycles (clk/12). The timers are independent of each other. By default the above
three bits are cleared.
Table 12-5 Bit Description of CKCON (SFR 0x8E)

V98XX Datasheet
Bit Description
T2M – to select the clock source for Timer2.

CKCON.5
When T2M = 0, clk/12 is used; when T2M = 1, clk is used.

CKCON.4

CKCON.3
h
12.1.2.2. Timer0/Timer1
ec
Timer0 and Timer1 are two of three embedded timers of 8052 microcontroller. Both timers can act as
a timer to count the MCU clock frequency, or act as a counter to count the input signals. Furthermore,
Timer1 also can act as a baud rate generator of UART1 for serial communication.
There are 4 operation modes for Timer0 and Timer1. They are determined by TMOD (SFR 0x89) and
TCON (SFR 0x88). The four modes are:
ot
- 13-bit timer/counter (Mode 0).
- 16-bit timer/counter (Mode 1).
- 8-bit timer/counter in auto-reload mode (Mode 2).

ng
- Split timer/counter mode (Mode 3, only for Timer0).
The SFRs associated with Timer0/Timer1 are:
- TL0 (SFR 0x8A) and TH0 (SFR 0x8C), the lower byte and higher byte of Timer0.
- TL1 (SFR 0x8B) and TH1 (SFR 0x8D), the lower byte and higher byte of Timer1.
Table 12-6 Timer0/1 Mode Control Special Function Register (TMOD, SFR 0x89)
Va
Bit Description
Bit7 Timer1 gate control bit. If the bit TR1 (TCON.6) is set bit and the signal on the pin
GATE INT1 is high, Timer1 runs when this bit is set to 1. If this bit is cleared, Timer1 runs
TMOD.7 when TR1 is set to 1, regardless of the state of the pin INT1.
When this bit is cleared, Timer1 acts as a timer to count the clock pulse (clk or clk/12,
Bit6 depending on the bit T1M, CKCON.4). When this bit is set bit, Timer1 acts as a
C/T
TMOD.6 counter driven by the input signal on the pin T1 and counts the 1-0 transitions of the
input signal.

V98XX Datasheet
Bit Description
To determine the operation mode for Timer1.

Bit5
M1 M1 M0 Mode
TMOD.5
0 0 Mode 0: 13-bit timer/counter.

Bit4
M0 1 0 Mode 2: 8-bit timer/counter in auto-reload mode.
TMOD.4
1 1 Mode 3: Split timer/counter.
Bit3 Timer0 gate control bit. If the bit TR0 (TCON.4) is set bit and the signal on the pin
h
GATE INT0 is high, Timer0 runs when this bit is set bit. If this bit is cleared, Timer0 runs
TMOD.3 when TR0 is set bit, regardless of the state of the pin INT0.
ec
Timer or counter select bit. When this bit is cleared, Timer0 acts as a timer to count
Bit2 the clock pulse (clk or clk/12, depending on the bit T0M, CKCON.3). When this bit is
C/T
TMOD.2 set bit, Timer0 acts as a counter driven by the input signal on the pin T0 and counts
the 1-0 transitions of the input signal.
Bit1 M1 M0 Mode
M1
ot
TMOD.1 0 0 Mode 0: 13-bit timer/counter.

Bit0
1 0 Mode 2: 8-bit timer/counter in auto-reload mode.
M0
TMOD.0
1 1 Mode 3: Split timer/counter mode.
ng
Table 12-7 Timer0/1 Control Special Function Register (TCON, SFR 0x88)
Bit Description
Bit7 Timer 1 overflow flag. It is set bit when Timer1 overflows. It is cleared when the
Va
TF1 processor vectors to execute interrupt service routine located at program address
TCON.7 0x001B (“Interrupt Resources”).
Bit6 Timer1 run control bit.

TR1
TCON.6 Set this bit to 1 to enable Timer1 to run.
Bit5 Timer0 overflow flag. It is set bit when Timer0 overflows. It is cleared when the
TF0 processor vectors to execute interrupt service routine located at program address
TCON.5 0x000B (“Interrupt Resources”).
Bit4 Timer0 run control bit.

TR0
TCON.4 Set this bit to 1 to enable Timer0 to run.

V98XX Datasheet
Bit Description
IO Interrupt 1 edge flag. If IO Interrupt 1 is configured to be edge-sensitive (IT1 is set

bit), IE1 is set bit when a 1-to-0 transition is detected on the input signal on the pin
INT1, but automatically cleared when the processor vectors to execute the
Bit3 corresponding interrupt service routine located at program address 0x0013 (“Interrupt
IE1 Resources”). In edge-sensitive mode, IE1 also can be cleared by program.
TCON.3
If IO Interrupt 1 is configured to be level-sensitive (IT1 is cleared), IE1 is set bit when
the level on the pin INT1 is low, but cleared when the level on the pin INT1 is high. In
level-sensitive mode, the program cannot write of IE1.
IO Interrupt 1 signal type control bit. When IT1 is set bit, IO Interrupt 1 is triggered
h
Bit2 when a 1-to-0 transition of the input signal is detected on the pin INT1. When IT1 is
IT1
TCON.2 cleared, IO Interrupt 1 is triggered when a low level input signal is detected on the pin
INT1.
ec
IO Interrupt 0 edge flag. If IO Interrupt 0 is configured to be edge-sensitive (IT0 is set
to 1), IE0 is set bit when a 1-to-0 transition is detected on the input signal on the pin
INT0, but is automatically cleared when the processor vectors to execute the
Bit1 corresponding interrupt service routine located at program address 0x0003 (“Interrupt
IE0 Resources”). In edge-sensitive mode, IE0 also can be cleared by program.
TCON.1
ot
If IO Interrupt 0 is configured to be level-sensitive (IT0 is cleared), IE0 is set bit when
the level on the pin INT0 is low, but cleared when the level on the pin INT0 is high. In
level-sensitive mode, the program cannot write of IE0.
IO Interrupt 0 signal type control bit. When IT0 is set bit, IO Interrupt 0 is triggered
ng
Bit0 when a 1-to-0 transition of the input signal is detected on the pin INT0. When IT0 is
IT0
TCON.0 cleared, IO Interrupt 0 is triggered when a low level input signal is detected on the pin
INT0.
12.1.2.2.1. Timer0/1, Mode 0

Va
In Mode 0, Timer0 and Timer1 act as a 13-bit timer/counter. In this mode, the lower byte of
Timer0/Timer1 (TLx, SFR 0x8A or SFR 0x8B) counts from 0 to 31. When it increments from 31, TLx SFR
(x=0~1) is cleared, and the higher byte of the timer (THx, SFR 0x8C or SFR 0x8D) increments by 1. In
this mode, only 13 bits of Timer0/Timer1, Bit0~Bit4 of TLx SFR and all 8 bits of THx SFR, are active. The
upper three bits of TLx SFR are indeterminate in Mode 0 and must be masked when the software
evaluates the register.
Users can configure the bit (TR0 or TR1, Bit4 or Bit6 of TCON SFR) to run Timer0 or Timer1. In the
V98XX, according to the value of the bit C/T (Bit6 or Bit2 of TMOD SFR), Timer0 or Timer1 can act as a
timer or a counter.
When the bit GATE (Bit7 or Bit3 of TMOD SFR) is cleared or set bit, and the input signal on the pin
INT0 or INT1 is active, Timer0 or Timer1 runs when TRx (x=0~1, TCON.4 or TCON.6) is set bit.
When the 13-bit timer increments from 0x1FFF, it rolls over to all zeros, and then the bit TF0 (TCON.5)

V98XX Datasheet
or TF1 (TCON.7) is set bit, and an interrupt is generated to CPU.
12.1.2.2.2. Timer0/1, Mode 1
In Mode 1, Timer0 and Timer1 act as 16-bit timers/counters. In this mode, all eight bits of the lower
byte of the timers, TL0 (SFR 0x8A) or TL1 (SFR 0x8B), are active, so, TLx SFR increments from 0 to 255.
When the TLx SFR increments from 255, it is cleared, and the higher byte of the timer, THx SFR (TH0
SFR or TH1 SFR), increments by 1. The timer will roll over to all zeros when the timer/counter increments
from 0xFFFF.
T0M (or T1M)

clk/12
h
clk 0 TL0 (or TL1)
C/T
0 4 7
1 0 clk
ec
clk
1
MODE0
T0 (or T1)
MODE1
TR0 (or TR1)
0 TH0 (or TH1) 7
GATE
ot
INT0
(or INT1)
INT
TF0 (or TF1)
ng
To serial port (only timer 1)
Figure 12-7 Timer 0/1, Mode 0/1
12.1.2.2.3. Timer0/1, Mode 2

Va
In Mode 2, only the lower byte of Timer0/Timer1 (TLx SFR, x=0~1) acts as an 8-bit timer/counter,
while the higher byte of it (THx SFR, x=0~1) holds a value that will be loaded into TLx SFR every time
TLx SFR overflows. When the value is loaded into the TLx SFR, the timer will increment from the loaded
value.
For example, TH1 SFR is set to 200, and when TL1 SFR increments from 255, it rolls to 200, and
recounts from 200 to 255, and then to 200, and repeats.

V98XX Datasheet
T0M (or T1M)

clk/12
clk 0 TL0 (or TL1)

C/T
0 4 7
1 0 clk RELOAD
clk
1
T0 (or T1)
TR0 (or TR1)
GATE
INT0 (or INT1)

0 TH0 (or TH1) 7
h
INT
TF0 (or TF1)
ec
To serial port (only timer 1)
Figure 12-8 Timer 0/1, Mode 2

ot
12.1.2.2.4. Timer0/1, Mode 3
In Mode 3, Timer0 becomes two completely separate 8-bit timers/counters. When Timer0 is set to
work in this mode, TR0 (TCON.4) and TF0 (TCON.5) are used by TL0 SFR, but TR1 (TCON.6) and TF1
(TCON.7) are used by TH0 SFR, so Timer1 stops running as a general timer but still can be used as a
ng
baud rate generator.
When Timer0 works in Mode3, Timer1 still can be enabled via configuring its operation mode to Mode
0/1/2, but no interrupt will be generated by it, because the flag TF1 is used by Timer0. When Timer1 is
configured to work in Mode 3, it stops running, but holds its counts.
Va

V98XX Datasheet
T0M
clk/12
clk 0
C/T TL0
0 7
1 0 clk
clk
1
T0
TF0 INT
TR0
GATE
h
INT0
INT1 TF1 INT
ec
TR1
0 TH0 7
Figure 12-9 Timer 0, Mode 3

ot
12.1.2.3. Timer2
Besides Timer0 and Timer1, there is a third timer, Timer2, in 8052 microcontroller, a 16-bit timer, has
ng
a number of new functions. The modes for Timer2 are:
- 16-bit timer/counter.
- 16-bit timer/counter in capture mode.
- 16-bit timer/counter in auto-reload mode.

Va
The SFRs associated with Timer 2 are:
- T2CON (SFR 0xC8).
- TL2 (SFR 0xCC) – Lower byte of Timer2.
- TH2 (SFR 0xCD) – Higher byte of Timer2.
- RCAP2L (SFR 0xCA) – To capture the value of TL2 SFR when Timer 2 is configured in capture
mode, or, to hold the lower byte of the loaded value when Timer 2 is configured in auto-reload
mode.
- RCAP2H (SFR 0xCB) –To capture the value of TH2 SFR when Timer 2 is configured in capture
mode, or, to hold the higher byte of the loaded value when Timer 2 is configured in auto-reload
mode.
Table 12-8 Timer2 Control Special Function Register (T2CON, SFR 0xC8)

V98XX Datasheet
Bit Description
Timer2 overflow flag.

Bit7
TF2 The bit TF2 is set bit when Timer2 overflows from FFFFh. TF2 must be cleared by
T2CON.7 the program. Only when both RCLK and TCLK are cleared, TF2 will be set bit.
Writing 1 to TF2 can force the Timer2 interrupt if it is enabled.
Timer2 external interrupt flag.
Bit6 When EXEN2 is set bit, EXF2 will be set bit when a 1-to-0 transition of the input
EXF2 signal on the pin T2EX is detected, which can trigger an auto-reload or capture
T2CON.6
event. EXF2 must be cleared by the program. Writing 1 to EXF2 can force the
Timer 2 external interrupt if it is enabled.
h
Bit5 Reserved.
RCLK
ec
T2CON.5 By default it is 0.
Bit4 Reserved.
TCLK
T2CON.4 By default it is 0.
Timer2 external interrupt enable bit.

ot
Bit3 When EXEN2 is set bit, an auto-reload or capture event will be triggered when a
EXEN2 1-to-0 transition of the input signal on the pin T2EX is detected. When EXEN2 is
T2CON.3
cleared, no interrupt will be generated whatever the input signal on the pin T2EX
is.
ng
Timer2 run control flag.

Bit2
TR2 1: Timer2 runs.
T2CON.2
0: Timer2 stops.
Timer or counter select bit. When C/T2 is cleared, Timer2 acts as a timer to count
Bit1 the clock pulses (clk or clk/12, depending on the bit T2M, CKCON.5). When C/T2
Va
C/T2
T2CON.1 is set bit, Timer2 acts as a counter driven by the input signal on the pin T2 and
counts the 1-to-0 transitions of the input signals.
Capture/reload flag.
When CP/RL2 and EXEN2 are set bit, the current counts will be captured into the
Bit0 registers RCAP2L SFR and RCAP2H SFR when a 1-to-0 transition of the input signal
CP/RL2 on the pin T2EX is detected. When CP/RL2 is cleared, but EXEN2 is set bit, an
T2CON.0
auto-reload event will occur when a 1-to-0 transition of the input signal on the pin
T2EX is detected. If either RCLK or TCLK is set bit, CP/RL2 cannot work, and
Timer2 can operate in auto-reload mode on overflow.
Table 12-9 Timer 2 Mode

V98XX Datasheet
RCLK TCLK CP/RL2 TR2 Mode
0 0 1 1 16-bit timer/counter in capture mode.
0 0 0 1 16-bit timer/counter in auto-reload mode.
1 X X 1 Reserved.
X 1 X 1 Reserved.
X X X 0 Stop working
h
12.1.2.3.1. Timer2, 16-Bit Timer/Counter Mode
ec
In this mode, users can configure the register T2CON SFR to enable Timer2 to act as a 16-bit timer or
a 16-bit counter (C/T2, T2CON.1), and to enable Timer2 to run (TR2, T2CON.2). In this mode, Timer2
increments from 0000h to FFFFh, and then rolls over to all zeros, setting the flag TF2 (T2CON.7) to 1,
which generate an interrupt to CPU.
12.1.2.3.2. Timer2, 16-Bit Timer/Counter in Capture Mode

ot
When CP/RL2 (T2CON.0) and EXEN2 (T2CON.3) are set bit, the values of TH2 SFR and TL2 SFR are
captured and loaded into the registers RCAP2L SFR and RCAP2H SFR when a 1-to-0 transition of the
input signal on the pin T2EX is detected. At the same time, the flag EXF2 (T2CON.6) is set bit, which will
ng
generate an interrupt to the processor if it is enabled.
T2M
clk/12
clk 0
C/T2
0 7 8 15
1 0
clk
clk TL2 TH2
1
T2
Va
TR2
EXEN2 RCAP2L RCAP2H

CAPTURE 0 7 8 15
T2EX EXF2 TF2
INT
Figure 12-10 Timer2, 16-bit Timer/ Counter in Capture Mode

V98XX Datasheet
12.1.2.3.3. Timer2, 16-Bit Timer/Counter in Auto-Reload Mode
When CP/RL2 (T2CON.0) is cleared, Timer2 acts as a 16-bit counter/timer in auto-reload mode.
In this mode, the CPU must write the reload value to the registers RCAP2L (SFR 0xCA) and RCAP2H
(SFR 0xCB). When the timer increments from FFFFh, the value stored in RCAP2L will be reloaded into
the register TL2 (SFR 0xCC), and the value stored in RCAP2H will be reloaded into the register TH2 (SFR
0xCD), at the same time, TF2 is set bit, which will generate an interrupt to the processor if it is enabled.
When CP/RL2 is cleared, but EXEN2 (T2CON.3) is set bit, an auto-reload event occurs when a 1-to-0
transition of the input signal on the pin T2EX is detected, at the same time, the flag EXF2 (T2CON.6) is
set bit, which will generate an external interrupt to the processor if it is enabled.
T2M
h
clk/12
clk 0
C/T2
0 7 8 15
1 0 clk
ec
clk TL2 TH2
1
T2
TR2
EXEN2 RCAP2L RCAP2H

ot
0 7 8 15
T2EX EXF2 TF2
INT
ng
Figure 12-11 Timer2, 16-Bit Timer/Counter in Auto-Reload Mode
12.2. UART
Va
In V98XX, there are 5 active UART serial interfaces on the chip, including UART1 of 8052 microcontroller
and the extended UART2 /UART3/UART4/ UART5 serial interfaces. Bits UART2 (bit4)/ UART3(bit5),
UART4(bit6) and UART5(bit7) (bit4~bit7 of PRCtrl1, 0x2D01) gate controls the corresponding UART serial
interfaces.
The UART serial interfaces can work in 4 modes. In Mode 0, the serial interface can only receive data
on the RXD port and output shifting clock on the TXD port. In other modes, the extended UART serial
interfaces can work like UART1 serial interfaces of 8052 microcontroller.
It is recommended to use extended UART interfaces for serial communication.
12.2.1. UART1
UART1 uses Timer1 to generate baud rate, and the bit SMOD1 (EICON.7) controls doubling the baud

V98XX Datasheet
rate of UART1.
The SFRs associated with UART1 are:
- SCON1 (SFR 0xC0) – UART1 Control Register.
- SBUF1 (SFR 0xC1) – UART1 Buffer Register.
Table 12-10 UART1 Control Special Function Register (SCON1, SFR 0xC0)
Bit Description
To determine the mode for UART1.

Bit7
SM0_1 SM0_1 SM1_1 Mode
SCON1.7
h
0 0 0: 8-bit shift register; baud rate=clk or clk/12.
0 1 1: 8-bit UART; baud rate, determined by Timer1.

Bit6
ec
SM1_1 1 0 2: 9-bit UART; baud rate = clk/32 or clk/64.
SCON1.6
1 1 3: 9-bit UART; baud rate, determined by Timer1.
Multiprocessor communication enable bit. In Mode2 and Mode3, SM2_1 enables

the multiprocessor communication. In Mode2 and Mode3, when SM2_1 is set bit,
Bit5 RI_1 cannot be set bit in case that the received 9 th bit is 0. In Mode1, when SM2_1
ot
SM2_1
SCON1.5 is set bit, RI_1 will be set bit only if a valid stop bit is received. In Mode0, SM2_1
establishes the baud rate: when SM2_1 is cleared, the baud rate is clk/12; when
SM2_1 is set to 1, the baud rate is clk.
Bit4 Receive enable bit.

ng
REN_1
SCON1.4 When REN_1 is set bit, data reception is enabled.
Bit3
TB8_1 To define the 9th bit to be transmitted in Mode2 or Mode3.
SCON1.3
Bit2 In Mode2 and Mode3, RB8_1 is to store the received 9 th bit. In Mode1, the stop
Va
RB8_1
SCON1.2 bit is stored as the RB8_1. In Mode0, RB8_1 is not used.
Transmit interrupt flag. If this bit is set bit, it indicates that the transmit data has
Bit1 been shifted out. In Mode0, TI_1 is set bit at the end of the 8 th bit. In other modes,
TI_1
SCON1.1 TI_1 is set bit when the stop bit is placed on the pin TXD1. TI_1 must be cleared
by the program.
Receive interrupt flag. If this bit is set bit, it indicates that a serial data has been
Bit0 received. In Mode 0, RI_1 is set bit at the end of the 8 th data bit. In Mode1,
RI_1 according to the state of SM2_1, RI_1 is set bit after the last sample of the
SCON1.0 incoming stop bit. In Mode2 and Mode3, RI_1 is set bit at the end of the last
sample of the 9th bit. RI_1 must be cleared by the program.

V98XX Datasheet
12.2.2. Extended UART Serial Interfaces
All the extended UART serial interfaces have the same architecture, but only UART2 has an optional
38-kHz carrier wave modulator.
In each extended UART serial interface, there are a general timer (compatible with Timer0) and a baud
rate generator (compatible with Timer1). The overflow of general timer can set a flag bit which will be
cleared by executing interrupt service routine (ISR) or by polling interrupt sources, and generate an
interrupt to the CPU. When the baud rate generator is used as a general timer, it can set the related
overflow flag to 1, but cannot generate an overflow interrupt. As an extended peripheral, there is a
specific control/status register for each UART interface, which can control the baud rate, select the clock
sources for the timers, disable or enable the timers, and show the overflow state of the timers.
h
12.2.2.1. Registers
ec
Table 12-11 Extended UART Serial Interfaces Registers
0x2820, R/W TCON2, UART2 Control / Status Register
0x2821, R/W TMOD2, UART2 Timers Mode Control Register

ot
0x2822, R/W TH20, Higher Byte of General Timer of UART2
0x2823, R/W TH21, Higher Byte of Baud Rate Generator of UART2
0x2824, R/W TL20, Lower Byte of General Timer of UART2

ng
0x2825, R/W TL21, Lower Byte of Baud Rate Generator of UART2
0x2826, R/W SCON2, UART2 Control Register
0x2827, R/W SBUF2, UART2 Buffer Register

Va
0x2828,
TCON3, UART3 Control / Status Register
R/W(V98XX)
0x2829,
TMOD3, UART3 Timers Mode Control Register
R/W(V98XX)
0x282A,
TH30, Higher Byte of General Timer of UART3
R/W(V98XX)
0x282B,
TH31, Higher Byte of Baud Rate Generator of UART3
R/W(V98XX)
0x282C,
TL30, Lower Byte of General Timer of UART3
R/W(V98XX)

V98XX Datasheet
0x282D,
TL31, Lower Byte of Baud Rate Generator of UART3
R/W(V98XX)
0x282E,
SCON3, UART3 Control Register
R/W(V98XX)
0x282F,
SBUF3, UART3 Buffer Register
R/W(V98XX)
h
0x2832, R/W TH40, Higher Byte of General Timer of UART4
0x2833, R/W TH41, Higher Byte of Baud Rate Generator of UART4
ec
0x2834, R/W TL40, Lower Byte of General Timer of UART4
0x2835, R/W TL41, Lower Byte of Baud Rate Generator of UART4
0x2836, R/W SCON4, UART4 Control Register

ot
0x2837, R/W SBUF4, UART4 Buffer Register

ng
0x283A, R/W TH50, Higher Byte of General Timer of UART5
0x283B, R/W TH51, Higher Byte of Baud Rate Generator of UART5
0x283C, R/W TL50, Lower Byte of General Timer of UART5

Va
0x283D, R/W TL51, Lower Byte of Baud Rate Generator of UART5
0x283E, R/W SCON5, UART5 Control Register
0x283F, R/W SBUF5, UART5 Buffer Register
Table 12-12 UARTx Control/Status Register (TCON2/TCON3/TCON4/TCON5)
Bit7 SMOD 0 When this bit is set to 1, the baud rate of UARTx is doubled.
Bit6 Reserved

V98XX Datasheet
To select the clock source for the baud rate generator.
Bit5 T1M 0 0: clk/12;
1: clk.
To select the clock source for the general timer.
Bit4 T0M 0 0: clk/12;
1: clk.
Overflow flag of the baud rate generator.

Bit3 TF1 0
h
When an overflow occurs to the baud rate generator, this bit will be set bit,
but no overflow interrupt will be generated.
Overflow flag of the general timer.
ec
Bit2 TF0 0 When an overflow occurs to the general timer, this bit will be set bit, and
an overflow interrupt will be generated to CPU if the interrupt is enabled.
Baud rate generator run control bit.
Bit1 TR1 0 1: to run;

ot
0: to stop.
General timer run control bit.
Bit0 TR0 0 1: to run;
0: to stop.
ng
Table 12-13 UARTx Timers Mode Control Register (TMOD2/TMOD3/TMOD4/TMOD5)
Bit Description
Bit7 This bit must be cleared for proper operation. In this case, the baud rate generator
GATE1
runs when TR1 (Bit1 of TCONx) is set.
Va
TMOD2.7
Bit6 This bit must be cleared for proper operation. In this case, the clock source for the
C/T1
TMOD2.6 baud rate generator is determined by the bit T1M (bit5 of TCONx).
Bit5 To select the mode for the baud rate generator.

T1M1
TMOD2.5 T1M1 T1M0 Mode
0 0 Mode0: 13-bit timer.
Bit4 0 1 Mode1: 16-bit timer.

T1M0
TMOD2.4 1 0 Mode2: 8-bit timer in auto-reload mode.
1 1 Mode3: Split timer mode.

V98XX Datasheet
Bit Description
Bit3 This bit must be cleared for proper operation. In this case, the general timer runs
GATE0
TMOD2.3 when TR0 (Bit0 of TCONx) is set.
Bit2 This bit must be cleared for proper operation. In this case, the clock source for the
C/T0
TMOD2.2 baud rate generator is determined by the bit T0M (bit4 of TCONx).
To select the mode for the general timer.

Bit1
T0M1 T0M1 T0M0 Mode
TMOD2.1
h
Bit0
T0M0 1 0 Mode2: 8-bit timer in auto-reload mode.
ec
TMOD2.0
1 1 Mode3: Split timer mode.
Table 12-14 UARTx Control Register (SCON2/SCON3/SCON4/SCON5)
Bit Description
ot
Bit7 To select the mode for UARTx.
SM0
SCON2.7 SM0 SM1 Mode
0 0 Mode0: 8-bit shift register; baud rate =clk or clk/12.

ng
0 1 Mode1: 8-bit UART; baud rate, determined by the baud rate generator.
Bit6
SM1
1 0 Mode2: 9-bit UART; baud rate =clk/32 or clk/64.
SCON2.6
1 1 Mode3: 9-bit UART; baud rate, determined by the baud rate generator.
Multiprocessor communication enable bit. In Mode2 and Mode3, SM2 enables the
multiprocessor communication. In Mode2 or Mode3, when SM2 is set bit, RI cannot
Va
Bit5 be set bit in case that the received 9th bit is 0. In Mode1, when SM2 is set bit, RI will
SM2
SCON2.5 be set bit only if a valid stop bit is received. In Mode0, SM2 determines the baud
rate: when SM2 is cleared, the baud rate is clk/12; when SM2 is set bit, the baud
rate is clk.
Bit4 Receive enable bit.

REN
SCON2.4 When REN is set bit, data reception is enabled.
Bit3
TB8 To define the 9th bit transmitted in Mode2 and Mode3.
SCON2.3
Bit2 In Mode2 and Mode3, RB8 stores the received 9th bit. In Mode 1, RB8 stores the
RB8
SCON2.2 received stop bit. In Mode0, RB8 is not used.

V98XX Datasheet
Bit Description
Bit1 Transmit interrupt flag. If this flag is set bit, it indicates that the transmit data has
TI been shifted out. In Mode0, TI is set at the end of the 8 th bit. In other modes, TI is
SCON2.1 set when the stop bit is placed on the pin TXD2. TI must be cleared by the program.
Receive interrupt flag. If this flag is set, it indicates that a serial data has been
Bit0 received. In Mode0, RI is set at the end of the 8th bit. In Mode1, according to the
RI state of SM2, RI is set after the last sample of the incoming stop bit. In Mode2 and
SCON2.0 Mode3, RI is set at the end of the last sample of the 9 th bit. RI must be cleared by
the program.
h
Table 12-15 UARTx Buffer Register (SBUF2/SBUF3/SBUF4/SBUF5)
Register R/W Bit Default Description
ec
SBUFx is physically two registers. One is written only and is used
to hold data to be transmitted out of the MCU via the pin TXD2.
The other is read only and is used to hold received data from
SBUFx R/W Bit[7:0] 0 external sources via the pin RXD2. Both mutually exclusive
registers use one address. When UARTx works in the
asynchronous and full-duplex communication mode, it can be
ot
used for “read” and “write” simultaneously.
12.2.2.2. Carrier Wave Modulation on UART2

ng
UART2 has a 38 kHz carrier wave modulator controlled by TXD2 Type Register (Txd2FS). When bit
TXD2CARRY (bit0 of Txd2FS, 0x28CF) is cleared, pin TXD2 will output modulated signals. Users can write
of the carrier wave generation registers to configure the carrier wave frequency and its duty cycle:
𝑓𝑀𝐶𝑈
𝑓𝐶𝐴𝑅𝑅 = Equation 12-1
𝐶𝐴𝑅𝑅𝐻 + 𝐶𝐴𝑅𝑅𝐿
Va
𝐶𝐴𝑅𝑅𝐻
𝐷𝑢𝑡𝑦𝐶𝐴𝑅𝑅 = Equation 12-2
𝐶𝐴𝑅𝑅𝐿
where, fCARR is the carrier wave frequency; fMCU is MCU clock frequency; DutyCARR is the duty cycle of the
carrier wave; CARRH is the value of registers CARRHH and CARRHL; CARRL is the value of registers
CARRLH and CARRLL.
When the level on the pin TXD2 is low, the modulated signal is output.
Table 12-16 TXD2 Type Register (Txd2FS, 0x28CF)
0x28CF, R/W, TXD2 Type Register, Txd2FS
Bit[7:1] Reserved X

V98XX Datasheet
0: with 38-kHz carrier wave;
Bit0 TXD2CARRY 0
1: without 38-kHz carrier wave.
Table 12-17 Carrier Wave Generation Registers
Register Description R/W Bit Default
Higher byte of Carrier Wave Generation Register 1:

0x2898 CARRHH R/W Bit[7:0] 0
Duty Cycle Control, High Pulse Duration
Lower byte of Carrier Wave Generation Register 1:

0x2899 CARRHL R/W Bit[7:0] 0
Duty Cycle Control, High Pulse Duration
Higher Byte of Carrier Wave Generation Register 2:
h
0x289A CARRLH R/W Bit[7:0] 0
Duty Cycle Control, Low Pulse Duration
Lower Byte of Carrier Wave Generation Register 2:

0x289B CARRLL R/W Bit[7:0] 0
Duty Cycle Control, Low Pulse Duration
12.2.2.3. UART Modes
ec
The UART serial interfaces can work in 4 modes via configuring the mode select bits, for example, SM1
ot
and SM2 of the register SCON2 (0x2826).
ng
Table 12-18 UART Modes
Sync. Or
Mode Baud rate Data Start or Stop Bit The 9th Bit
Async.
Va
8-bit shift
0 Sync. clk or clk/12 8-bit None None
register
Determined by baud
1 8-bit UART Async. 8-bit 1 start, 1 stop None
rate generator
2 9-bit UART Async. clk/32 or clk/64 9-bit 1 start, 1 stop Parity bit
Determined by baud
3 9-bit UART Async. 9-bit 1 start, 1 stop Parity bit
rate generator
All the UART serial interfaces have the same architecture and functions except that:
- Only UART2 has 38-kHz carrier wave with its TXD.

V98XX Datasheet
- UART1 uses Timer1 as its baud rate generator.
So take UART2 for an example to introduce the work modes for UART serial interfaces.
12.2.2.3.1. Mode0
In Mode0, UART2 receives data on the pin RXD2, and outputs shift clock on the pin TXD2. Data can be
received as soon as the bit REN (bit4 of SCON2, 0x2826) is set bit and the bit RI (bit0 of SCON2, 0x2826)
is cleared. The shift clock is activated and the UART shifts data in on each rising edge of the shift clock
until eight bits have been received. The 8th bit was shifted in, and one machine cycle later, the bit RI is
set bit and the reception stops until the bit RI is cleared by the program.
h
12.2.2.3.2. Mode1
ec
Mode1 provides standard asynchronous and full-duplex communication. In this mode, a data frame
contains ten bits: one start bit, eight bits of data, and one stop bit. When a data frame is received, the
stop bit is stored in the bit RB8 (bit2 of SCON2, 0x2826). On receive and transmit operation, start with
the LSB.
In Mode1, the baud rate is determined by the baud rate generator overflow frequency. UART2 uses a
dedicated baud rate generator, which is compatible with Timer 1. When the baud rate generator overflows,
ot
it generates a clock which is then divided by 16 to generate the baud rate.
2 SMODx
BaudRate = ×Overflow Equation 12-3
32
Where,
ng
Overflow is the baud rate generator overflow frequency. As for UART1, Timer1 is the baud rate
generator; as for the extended UART serial interfaces, the specific baud rate generator is used. SMODx,
the value of the bit SMOD0/1, determines to double the baud rate or not.
Generally, the baud rate generator works in the mode of 8-bit timer with auto-reload. The reload value
is stored in the register TH21 (0x2823), which makes the above equation for baud rate (clk/12 is used
as the clock source):
Va
2SMODx clk
BaudRate = × Equation 12-4
32 12 ×(256 - TH21)
where, clk is the MCU clock, and TH21 is the reload value of the register TH21 (0x2823).
The bit T1M (TCON2.5) determines the clock source for the baud rate generator of UART2. When T1M
is set bit, clk is used as the clock source:
2SMODx clk
BaudRate = × Equation 12-5
32 (256 - TH21)
Users can obtain the value of TH21 via the equation:
2SMODx ×clk
TH21 = 256 - Equation 12-6
32 ×BaudRate

V98XX Datasheet
When T1M is cleared, and the baud rate is known, users can obtain the value of TH21 via the following
equation:
2SMODx ×clk
TH21 = 256 - Equation 12-7
384 ×BaudRate
In Mode1, UART2 begins to transmit data after the program writing data into the register SBUF2
(0x2827). UART2 transmits data on the pin TXD2 in the following order: start bit, eight data bits (LSB
first), stop bit. The bit TI (bit1 of SCON2, 0x2826) will be set bit two clock cycles after the stop bit is
transmitted.
In Mode1, UART2 starts to receive data at the falling edge of a start bit received on the pin RXD2,
when the REN (bit4 of SCON2, 0x2826) bit is set. To achieve this, every bit on the pin RXD2 should be
sampled sixteen times at any baud rate. When a falling edge of a start bit is detected, the timer used to
h
generate the receive clock is reset to synchronize with the received bits. To reject noise, the serial port
detects the values of the three consecutive samples in the middle of each bit. Only more than two same
values can decide the received data bit to be valid. This is especially true for the start bit. If the falling
edge on the pin RXD2 is not verified by a majority decision of three consecutive samples, then the serial
ec
port stops receiving data and waits for another falling edge on RXD2.
When RI (bit0 of SCON2, 0x2826) is cleared, SM2 (bit5 of SCON2, 0x2826) is set bit, and the stop bit
is 1 (if SM2 is cleared, the state of stop bit does not matter), the serial port will write the received byte
to the register SBUF2 (0x2827), load the stop bit into RB8 (bit2 of SCON2, 0x2826), and set the bit RI
to 1. Otherwise, the received data lose; they cannot load data into the register SBUF2 and the bit RB8;
ot
and the bit RI cannot be set bit.
12.2.2.3.3. Mode2
ng
Mode2 provides asynchronous and full-duplex communication. In this mode, the data frame contains
eleven bits: one start bit, eight data bits, one programmable 9th bit, and one stop bit.
When data bits are received or transmitted, start with LSB. As to the transmitting operation, the 9 th
bit is determined by the value of the bit TB8 (bit3 of SCON2, 0x2826). If the 9 th bit is used as a parity
bit, the value of the P bit (Bit 0 of PSW SFR) should be moved to TB8.
In Mode2, the baud rate is either clk/32 or clk/64, determined by the bit SMOD (Bit7 of TCON2, 0x2820).
Va
It can be calculated as follows:
2 SMODx ×clk
BaudRate = Equation 12-8
64
In Mode2, UART2 starts transmitting data after the software writing data into the register SBUF2
(0x2827). UART2 transmits data on the pin TXD2 in the following order: the start bit, eight data bits
(LSB first), the 9th bit, then the stop bit. The bit TI (bit1 of SCON2, 0x2826) is set bit when the stop bit
has been transmitted.
In Mode2, receiving data begins at the falling edge of a start bit received on the pin RXD2, when the
bit REN=1 (bit4 of SCON2, 0x2826). To achieve it, every bit on the pin RXD2 should be sampled sixteen
times at any baud rate. When a falling edge of a start bit is detected, the timer used to generate the
receive clock is reset to synchronize with the received bits. To reject noise, the serial port detects the
values of the three consecutive samples in the middle of every bit. Only more than two same values can
decide the received data bit to be valid. This is especially true for the start bit. If the falling edge on the

V98XX Datasheet
pin RXD2 is not verified by a majority decision of three consecutive samples, then the serial port stops
receiving data and waits for another falling edge on RXD2.
When RI (bit0 of SCON2) is cleared, SM2 (bit5 of SCON2) is set bit, and the stop bit is 1 (if SM2 is
cleared, the state of stop bit does not matter), the serial port will write the received byte to the register
SBUF2 (0x2827), load the stop bit into RB8 (bit2 of SCON2), and set the bit RI. Otherwise, the received
data lose; they cannot load data into the register SBUF2 and the bit RB8; and the bit RI cannot be set
bit.
12.2.2.3.4. Mode3
Mode3 provides asynchronous and full-duplex communication. In this mode, the data frame contains
h
eleven bits: one start bit, eight data bits, one programmable 9 th bit, and one stop bit. When data bits
are received and transmitted, start with LSB.
In Mode3, the data is transmitted or received in the same way that in Mode2. In Mode3, the baud rate
ec
generation is identical to that in Mode1. That is, Mode3 is a combination of the communication protocol
in Mode2 and the baud rate generation in Mode1.
12.2.2.3.5. Multiprocessor Communication

ot
The multiprocessor communication is enabled in Mode2 and Mode3 when the bit SM2 (bit5 of SCON2,
0x2826) is set bit. In the multiprocessor communication mode, the received 9 th bit is stored in the bit
RB8 (bit2 of SCON2, 0x2826), and, after the stop bit has been received, UART2 receive interrupt is
activated if RB8 is set bit.
ng
The multiprocessor communication is used to send a block of data from a master to one slave. The
master first transmits an address byte that identifies the target slave. When transmitting an address
byte, the master sets the 9th bit to 1; when transmitting data bytes, the master clears the 9th bit.
When SM2 is set bit, no slave can generate an interrupt when a data byte has been received. However,
all slaves can generate interrupts when an address byte is received. Every slave can examine the received
address byte to determine whether it is the slave being addressed. Address decoding must be done by
the program during the interrupt service routine. The slave being addressed clears the bit SM2 and
Va
prepares to receive the data bytes. The slaves that are not being addressed leave the bit SM2 set and
ignore the incoming data bytes.
12.3. Enhanced UART Serial Interfaces (EUART)

Besides the above general UART serial interfaces, there are two enhanced UART serial interfaces
(EUART1 and EUART2) which have features as follows:
- ISO/IEC 7816-3 compliant;
- asynchronous and half-duplex communication;
- programmable baud rate;
- re-transmitting automatically.

V98XX Datasheet
The EUART interface receives and transmits a data frame composed of 10 bits: 1-bit start bit (START,
low level), 8-bit data (DATA, from MSB to LSB) and 1-bit check bit (CK). When the 8-bit DATA are
received and transmitted, the MSB is first. Bits EUART1 and EUART2 (bit1~bit2 of PRCtrl0, 0x2D00) gate
controls the corresponding enhanced UART serial interfaces.
D7 D0
START D6 D5 D4 D3 D2 D1 CK
MSB LSB
Figure 12-12 Data Frame in EUART Communication
12.3.1. Registers
In the V98XX, the EUART related registers are located at addresses 0x2A00~0x2A05 (for EUART1) and
h
0x2B00~0x2B05 (for EUART2).
Table 12-19 EUART Baud Rate Generators
ec
0x2A01 Lower byte of EUART1/2 DIVLA bit[7:0]

0
0x2B01 baud rate generator DIVLB DIV<7:0>
See “EUART Baud Rate
ot
Generation” for details
0x2A02 Higher byte of EUART1/2 DIVHA bit[7:0]
0
0x2B02 baud rate generator DIVHB DIV<15:8>
Table 12-20 EUART Buffer Register (DATAA/DATAB, 0x2A03/0x2B03)

ng
0x2A03/0x2B03, R/W, EUART1/2 Buffer Register, DATAA/DATAB
The buffer register is physically two registers.
One register is read-only. When an EUART receive interrupt was triggered, the
Va
read-only register holds the received data, which will be read out via reading
bit[7:0] operation of this register. When the bit OVIE (bit7 of CFGA/CFGB, 0x2A05/0x2B05)
0 is set bit, an overflow interrupt will be triggered if another data is received when
D<7:0> the former received data has not been read out.
The other register is write-only. Writing of the write-only register will activate data
transmission. Writing of this register cannot overlap the received data stored in
the read-only buffer register.
Table 12-21 EUART Information Register (INFOA/INFOB, 0x2A04/0x2B04)

V98XX Datasheet
0x2A04/0x2B04, R/W, EUART1/2 Information Register, INFOA/INFOB
Overflow interrupt flag.

bit7
0 When another byte is received before the former one was read out, this bit will be
OVIF
set to 1 and an overflow interrupt will be generated to CPU.
bit6 Transmit interrupt flag.

0
SIF A transmit interrupt will be generated to CPU at the end of reading the bit CKACK.
Receive interrupt flag.
h
bit5
0 A receive interrupt will be generated to CPU at the end of transmission of the
RIF
signal CKACK.
ec
bit4 0 Reserved.
Transmit error flag.

bit3
0 On data transmission, if the signal CKACK received by the transmitter is low, a
SERR
transmit error will be triggered and this bit will be set to 1.
ot
Receive error flag.
bit2
0 On data receiving, if the received checksum bit (CK) is not equal to that
RERR automatically computed by the system, a receive error will be triggered and this
bit will be set to 1.
ng
bit1 The automatically computed checksum based on the received or transmitted 8-bit
0
CHKSUM data (DATA).
CKACK signal transmitted by the receiver at the end of data frame transmission.
If the receiver cannot start receiving data automatically at the end of data frame
Va
bit0 transmission, this bit is read out as 1.

0
CKACK If the receiver can start receiving data automatically at the end of data frame
transmission, this bit will be set bit if the data are valid, or cleared if the data are
invalid.
Table 12-22 EUART Configuration Register (CFGA/CFGB, 0x2A05/0x2B05)
0x2A05/0x2B05, R/W, EUART1/2 Configuration Register, CFGA/CFGB
bit7 Set this bit to 1 to enable receive overflow interrupt.

0
OVIE By default the interrupt is disabled.

V98XX Datasheet
bit6 Set this bit to 1 to enable transmit interrupt.

0
SDIE By default the interrupt is disabled.
bit5 Set this bit to enable receive interrupt.

0
RCIE By default the interrupt is disabled.
bit4 When the V98XX works as a slave, this bit gives the period the bit CKACK stays 0
0
h
ACKLEN when a receive error occurs. 0: 1-byte length; 1: 2-byte length.
bit3 If this bit is set to 1 and the V98XX works as a mater, the master will automatically
0 transmit another character when a low level CKACK was received at the end of the
ec
AUTOSD former character. By default this function is disabled.
bit2 If this bit is set to 1 and the V98XX works as a slave, when the slave received
0 invalid data, it will automatically transmit a low level CKACK to the master to ask
AUTORC it to transmit the data again.
ot
bit1 Parity bit.
0
CHKP 0: even; 1: odd.
Set the bit ENABLE of CFGA to 1 to enable the port P10.0 for EUART1 data
transmission and receive.
ng
bit0
0 Set the bit ENABLE of CFGB to 1 to enable the port P10.1 for EUART2 data
ENABLE transmission, and P10.2 for EUART2 data receive.
By default the EURAT interfaces are idle.
According to the ISO/IEC 7816-3 protocol, the data should not be automatically re-transmitted more
Va
than three times. For example, the program must disable the automatic re-transmitting after two
failures of re-transmitting.
12.3.2. EUART Communication Timing
On EUART communication, the period for transmitting or receiving 1 bit is defined as the elementary
time unit (ETU). When a data frame was transmitted, a period is needed by the receiver to check the
received data before the transmitter sends another data frame. This period is defined as the guard time
(GT). Generally, 1 GT is equal to 3 ETU.

V98XX Datasheet
Time
MSB LSB
A
Communication: succeed
START Parity ACK=1 START
ETU
1 GT=3 ETU
To transmit the
The transmitted data frame is checked right.
next data frame
ACK=0
MSB LSB
h
B
Communication: fail START Parity START
ETU
1 GT=3 ETU
ec
To re-transmit the
The transmitted data frame is checked wrong. former data frame
Figure 12-13 EUART Communication Timing

As shown in A, the transmitter sends a 10-bit data frame to the receiver, including 1-bit START, 8-bit
DATA and 1-bit CK. At the end of transmission, the receiver sends a check signal CKACK of 1 to 2 ETU
ot
length. If a high level CKACK is transmitted, it indicates the received data frame is valid; in this condition,
the transmitter and receiver will remain at high state for at least 1 ETU, and then the transmitter will
send the next data frame.
As shown in B, the transmitter sends a 10-bit data frame to the receiver, including 1-bit START, 8-bit
DATA and 1-bit CK. At the end of the transmission, the receiver sends a check signal CKACK of 1 to 2
ng
ETU length. If a low level CKACK is transmitted, the signal will be driven to low from high at the moment
of 9.5 ETU, and then pulled high at the moment of 11.5 or 12.5 ETU, which is determined by the
configuration of the bit ACKLEN (bit4 of CFG), and holds high for 0.5 ETU. Then the transmitter will send
the data frame again.
EUART interfaces support half-duplex communication. When the transmitter is sending a data frame,
the receive port of the transmitter receives logic “1” all the time; when the receiver sent a signal CKACK
Va
to the transmitter at the end of the data frame transmission, the receive port of the transmitter receives
the CKACK.
12.3.3. EUART Baud Rate Generation
In the V98XX, each EUART has a 16-bit timer for baud rate generation, DIVLA/DIVHA and DIVLB/DIVHB.
The timer counts the MCU clock cycles. When the timer overflows, the transmitter is enabled to transmit
1-bit data. The baud rate can be calculated as follows:
fMCU 1
Baudrate = = Equation 12-9
10000h - DIV ETU
where, fMCU is the MCU clock frequency, DIV is the preset value of the timer (DIVLA/DIVHA or
DIVLB/DIVHB).

V98XX Datasheet
To ensure that the receiver can receive reliable data, the data receive is enabled at the moment of 0.5
ETU after the transmission started.
12.3.4. Data Transmission and Reception
By default the EUART serial interfaces stay IDLE.
12.3.4.1. Data Transmission
In the state IDLE, writing of the buffer register DATAA/DATAB (0x2A03/0x2B03) will enable data
h
transmission. The transmission has 7 steps, each lasting 1 ETU:
1. transmitting the bit START (0);
2. transmiting 8-bit DATA, from MSB to LSB;
ec
3. transmitting 1-bit CK;
4. reading the CKACK signal transmitted by the receiver, and then generating a transmit interrupt if
the bit SDIE was set bit;
5. waiting state 1 (1 ETU);

ot
6. waiting state 2 (1 ETU);
7. if a high level CKACK is transmitted by the receiver, or the automatic re-transmitting is disabled
(AUTOSD is cleared, bit3 of CFGA/B, 0x2A05/0x2B05), the EUART interface gets back to IDLE state;
if a low level CKACK is transmitted by the receiver, and the automatic re-transmitting is enabled, the
ng
EUART interface starts to transmit the start bit (START) of the former data frame again.
12.3.4.2. Data Reception
When the V98XX works as a slave, the EUART interface starts to receive a data frame when a 1-to-0
transition of the signal was detected. The data reception includes steps as follows, each lasting 1 ETU:
Va
1. receiving the bit START (0);
2. receiving 8-bit DATA, from MSB to LSB;
3. receiving 1-bit CK;
4. transmitting a CKACK signal to the transmitter. If the received CK is equal to that automatically
computed by the chip, or the automatic re-receiving is disabled (AUTORC is cleared, bit2 of
CFGA/CFGB, 0x2A05/0x2B05), CKACK is high level; otherwise, CKACK is low level.
5. Transmitting the CKACK signal to the transmitter again. If the received CK is equal to that
automatically computed by the chip, or the automatic re-receiving is disabled (AUTORC is cleared,
bit2 of CFGA/CFGB, 0x2A05/0x2B05), CKACK is high level; otherwise, CKACK is low level. After this
step, an interrupt is generated to CPU.
6. getting back to the IDLE state.

V98XX Datasheet
IDLE
Writing of The falling edge is detected.
0x2A03/0x2B03
Transmit Receive
START START
Transmit Receive
8-bit DATA 8-bit DATA
NO NO
h
8 bits？ 8 bits？
NO NO
YES YES
ec
Transmit Receive
CK CK
Receive Transmit
CKACK CKACK
ot
SIF RIF
Re-transmit
1 ETU
CKACK
ng
1 ETU
Match?
YES
YES
Va
Re-transmit?
Figure 12-14 Data Transmission and Reception
12.3.5. EUART for Smart Card Communication
Both EUART interfaces are ISO/IEC 7816-3 compliant, so they can be used for smart card
communication.
When the EUART interface is used for smart card communication, the pulse width modulation clock
(PWM clock) output from the pin P9.7 will be used as the smart card clock input. The pulse width can be
configured via the registers listed in the following table. Bit PWMCLK (bit7 of PRCtrl0, 0x2D00) gate
controls the PWM clock generator.

V98XX Datasheet
Users can write of pulse width modulation clock generators to configure the PWM clock frequency and
its duty cycle:
𝑓𝑀𝐶𝑈
𝑓𝑃𝑊𝑀𝐶𝐿𝐾 = Equation 12-10
𝑃𝑊𝑀𝐶𝐿𝐾1 + 𝑃𝑊𝑀𝐶𝐿𝐾2
𝑃𝑊𝑀𝐶𝐿𝐾1
𝐷𝑢𝑡𝑦𝑃𝑊𝑀 = Equation 12-11
𝑃𝑊𝑀𝐶𝐿𝐾2
where, fPWMCLK is PWM clock frequency; fMCU is MCU clock frequency; DutyPWM is the duty cycle of PWM
clock; PWMCLK1 is the value of registers PWMCLK1H and PWMCLK1L; PWMCLK2 is the value of registers
PWMCLK2H and PWMCLK2L.
Table 12-23 Pulse Width Modulation Clock Generators
h
Register Address R/W Bit Default Description
Higher byte of pulse width modulation clock
ec
PWMCLK1H 0x289C R/W bit[7:0] 0 generator 1, to control duration of state high in the
duty cycle
Lower byte of pulse width modulation clock

PWMCLK1L 0x289D R/W bit[7:0] 0 generator 1, to control duration of state high in the
duty cycle
ot
Higher byte of pulse width modulation clock
PWMCLK2H 0x289E R/W bit[7:0] 0 generator 2 , to control duration of state low in the
duty cycle
ng
Lower byte of pulse width modulation clock

PWMCLK2L 0x289F R/W bit[7:0] 0 generator 2, to control duration of state low in the
duty cycle
Va

V98XX Datasheet
13. General-Purpose Serial Interface

(GPSI)
V98XX integrates a general-purpose serial interface (GPSI) that is compliant with the I2C protocol.
When the bit “GPSI” (“bit6” of “PRCtrl0”, 0x2D00) is set to ‘1’, pins “P9.1” and “P9.2” work as the
two wires of the general-purpose serial interface: “P9.1” for serial data (“SDA”), and “P9.2” for serial
clock (“SCL”). When pins “P9.1” and “P9.2” is used for GPSI wires, “P9.1” must be configured to
“Input enabled”, but no mandatory requirement on the output enable register of “P9.1”; and “P9.2”
is “Output enabled” automatically.
h
13.1. Frame Structure
1 2 3 4 5 6 7 8 9
ec
SCL
//
START
STOP or
SDA D0 D1 D2 D3 D4 D5 D6 D7 ACK ACK
RESTART
ot
8-bit DATA byte
START by 1-bit ACK by Slave: 1-bit ACK by receiver STOP or RESTART

Master 0: acknowledged; (Master or Slave): by Master:
1: not acknowledged. 0: acknowledged; 0: RESTART;
1: not acknowledged. 1: STOP.
Figure 13-1 Frame Structure on SDA

ng
As illustrated in Figure 13-1, a frame through the wire “SDA” is composed of some of the following
parts.
- 1-bit START: A falling edge on “SDA” when “SCL” holding “HIGH” sets up a START condition.
This bit must be sent by Master.
- 8-bit DATA byte: 1 bit DATA transferred on 1 SCL clock. A DATA bit is prepared on the falling edge
of each SCL clock, and sampled on the rising edge of each SCL clock. The endian of byte transfer is
Va
defined by the bit “Endian” (“bit4” of “SICFG”, 0x2F01). 8-bit DATA byte must be followed by 1-
bit “ACK”.
- 1-bit ACK: The “ACK” bit is prepared on the falling edge of an “SCL” clock, and sampled on the
rising edge of an “SCL” clock. Only the “ACK” bit transferred by the receiver is valid. “HIGH”
indicates “Not acknowledged”; “LOW” indicates “Acknowledged”. 1-bit ACK must be preceded
by 8-bit DATA.
- 1-bit STOP or RESTART, when “SCL” holds “HIGH”, the SDA signal will generate a rising edge
(“STOP”) or falling edge (“RESTART”). Preparing “SDA” data in the “SCL” falling edge, Sampling
“SDA” data in a “SCL” rising edge. So, Before “STOP” or “RESTART”, SCL signal must produce a
falling edge, while ensuring the SDA level on the rising edge of “SCL”: If users want to generate
“STOP”, users should ensure that the SDA signal is low; If you want to generate RESTART, should
ensure that the SDA is high level. STOP or RESTART must be issued by by Master device.
Bit[3:0] of register SICFG (0x2F01) defines the structure of the frame to be transmitted or received.

V98XX Datasheet
Table 13-1 Description of Different Frame Structures
# START DATA+ACK STOP/RESTART Description
0 ○ ○ ○ Not valid.
1 ○ ○ X To receive or transmit the starting frame.
2 ○ X ○ Not valid.
3 ○ X X To receive or transmit START bit only.
To receive or transmit the last frame composed of 8-bit

4 X ○ ○
DATA, 1-bit ACK and 1-bit STOP.
h
5 X ○ X To receive or transmit 8-bit DATA and 1-bit ACK only.
ec
6 X X ○ To receive or transmit 1-bit STOP only.
7 X X X Not valid.
○: to receive or transmit; X: not to receive or transmit.

ot
13.2. Serial Clock Generation
When a START condition is set up, the 16-bit timer embedded in the GPSI unit starts to count the MCU
clock pulses to generate the serial clock (fSCL). The fSCL is defined by the following equation:
ng
fMCU
fSCL = Equation 13-1
4 ×(TH + 1)
where fMCU is the clock frequency for MCU operation; TH is the threshold preset in registers SITHH
(0x2F03) and SITHL (0x2F02); fSCL is the serial clock (SCL) frequency, and the maximum fSCL is 400kHz.
Va

V98XX Datasheet
13.3. Receive and Transmit Data
Interrupt service
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL
ACK=0 ACK=0
by slave by master
bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit
SDA 1
1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
R /W
START bit 8-bit target DATA 8-bit target DATA
by master by master by slave
h
Data Output bit bit bit bit bit bit bit bit
0xFF
by Master 0 1 2 3 4 5 6 7
ec
by Slave 0 1 2 3 4 5 6 7
Figure 13-2 Receive and Transmit Data

When the V98XX communicate with other devices via GPSI, it transmits and receives data
simultaneously.
ot
The data on the wire SDA is in the format of Wire-AND, which means the data is the data from receiver
and transmitter in “AND” logic, but not the state of either. The MCU can read the register SIDAT (0x2F04)
and bit ACK (bit0 of SIFLG, 0x2F05) to acquire the data of the SDA. When GPSI is idle (BUSY, bit1 of
SIFLG, 0x2F05, is cleared), writing of register SIDAT (0x2F04) triggers data receive and transmit.
When bit BUSY (bit1 of SIFLG, 0x2F05) is cleared, writing 0xFF or a specific data byte to be transmitted
ng
to register SIDAT (0x2F04) triggers data receive and transmit. Then bit BUSY is set to 1. After data
transmit and receive, bit BUSY is cleared again, and read register SIDAT and bit ACK (bit0 of SIFLG,
0x2F05) to acquire the data from SDA.
13.4. GPSI Interrupt

Va
When IE4=1 (bit4 of ExInt5IE, 0x28A5), EIE.3=1 (SFR 0xE8) and IE.7=1 (SFR 0xA8), a transmit
interrupt will be triggered every time a frame (structure defined by register SICFG) is transmitted, and
CPU will service the interrupt, read bit ACK, and prepares for the next frame transmission.
When IE5=1 (bit5 of ExInt5IE, 0x28A5), EIE.3=1 (SFR 0xE8) and IE.7=1 (SFR 0xA8), writing of
registers located at addresses 0x2F01~0x2F04 when bit BUSY (bit1 of SIACK, 0x2F05) is set to 1, an
illegal data interrupt will be triggered and the write operation is invalid.
SCL holds LOW on interrupt service.
13.5. For I2C Application

The GPSI is I2C compliant. When it is used for I2C application, the V98XX works as Master device to

V98XX Datasheet
communicate with other devices connected to the I2C bus. In this case, the starting frame is to select
the target slave, of which bit[7:1] of 8-bit DATA is slave address byte, and bit0 is read/write control bit
(“1” read; “0” write).
Read Operation Transmit interrupt Transmit interrupt Transmit interrupt

in master in master in master
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 9 10
//
SCL
ACK=0 ACK=0 ACK=1

by slave by master by master
bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit //
SDA 1
1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0
//
R /W
START bit 8-bit address byte of slave 8-bit target DATA STOP or RESTART
by master by master by slave by master
0xFF 0xFF
by Master 0 1 2 3 4 5 6 7
h
Data Output bit bit bit bit bit bit bit bit bit //
by Slave 0 1 2 3 4 5 6 7 0
//
Figure 13-3 Read Operation
ec
Transmit interrupt Transmit interrupt Transmit interrupt
Write Operation in master in master in master
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 9 9 9
//
SCL
ACK=0 ACK=0 ACK ACK

by slave by slave by slave by slave
//
bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit
SDA 0
1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0
//
ot
R /W
STOP or RESTART
START bit 8-bit address byte of slave 8-bit target DATA by master
by master by master by master
//
bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit
Data Output 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0
by Master //
Data Output
by Slave
ng
Figure 13-4 Write Operation

Figure 13-3 and Figure 13-4 depict read and write operation on I2C application when interrupt is
enabled. For example, when the V98XX writes or reads a slave device connected on I2C bus via GPSI, it
could be done following the procedure:
1. Write of registers SITHH/SITHL (0x2F03/0x2F02) to configure fSCL;

Va
2. Write of register SICFG (0x2F01) to enable transmitting START, and clear bit Endian to 0;
3. Write anything to register SIDAT (0x2F04) to trigger to transmit START. During transmission, bit
BUSY is set to 1;
4. When BUSY is cleared, write of register SICFG (0x2F01) to enable transmitting DATA and ACK; write
0x01 to register SIACK (0x2F05); and then write target slave address to bit[7:1] of register SIDAT
(0x2F04) and write 1 (to read) or 0 (to write) to bit0 to trigger transmitting the slave address frame.
During transmission, bit BUSY is set to 1;
5. When BUSY is cleared, read of register SIACK (0x2F05). If it is read out as 0, the target slave device
is selected;
6. Write of register SICFG (0x2F01) to enable transmitting DATA and ACK; write of 0x01 to register
SIACK (0x2F05); and then write the content to be transmitted to register SIDAT (0x2F04) to trigger
transmitting data frame. During transmission, bit BUSY is set to 1;

V98XX Datasheet
7. Repeat step 5 and 6 until all data have been transmitted;
8. Write of register SICFG (0x2F01) to enable transmitting STOP or RESTART;
9. Write anything to register SIDAT (0x2F04) to trigger transmitting bit STOP or RESTART.
The bit STOP ends a serial communication.
13.6. Registers
Table 13-2 Register to Disable or Enable GPSI
h
1: Disable the clock for PWM；

Bit7 PWMCLK R/W 0
ec
0: Enable the clock for PWM
To enable or disable GPSI.
Bit6 GPSI R/W 0 1: enable;
0: disable.
ot
1: Disabe IO P10；
Bit5 P10 R/W 0
0: Enable IO P10。
To enable or disable the fast IOs Group P9.
Bit4 P9 R/W 0 1: disable;

ng
0: enable.
Bit3 P0P8 R/W 0 1: Disable all IO P0~P8；
0: Enable all IO P0~P8
Bit2 EUART2 R/W 0 1: Disable EUART2block；

Va
0: Enable EUART2block
Bit1 EUART1 R/W 0 1: Disable EUART1block；
0: Enable EUART1block。
Bit0 TimerA R/W 0 1: Disable TimerA；
0: Enable TimerA。
Table 13-3 GPSI Control Register (SICFG, 0x2F01)
0x2F01, R/W, GPSI Control Register, SICFG
Bit[7:5] Reserved R/W 0

V98XX Datasheet
0x2F01, R/W, GPSI Control Register, SICFG
To configure the DATA endian for transmission and reception.
Bit4 Endian R/W 0 1: LSB first;
0: MSB first.
Bit3 TXS R/W 0 Set this bit to 1 to enable receiving or transmitting START bit.
Set this bit to 1 to enable receiving or transmitting 8-bit DATA

Bit2 TXD R/W 0
byte and 1-bit ACK.
Bit1 TXP R/W 0 Set this bit to 1 to enable receiving or transmitting STOP bit.
h
Set this bit to 1 to enable receiving or transmitting RESTART
Bit0 TXRS R/W 0
bit.
ec
Table 13-4 GPSI Timer Divider Registers (SITHH/SITHL, 0x2F03/0x2F02)
Register Bit R/W Default Description
0x2F03 SITHH Bit[7:0] TH[15:8] R/W 0 Set a threshold for serial clock (SCL)
generation.
ot
0x2F02 SITHL Bit[7:0] TH[7:0] R/W 0 fMCU
fSCL =
4 ×(TH[15 : 0] + 1)
Table 13-5 GPSI Data Register (SIDAT, 0x2F04)
0x2F04, R/W, GPSI Data Register, SIDAT

ng
Endian=0 D0 D1 D2 D3 D4 D5 D6 D7
Endian=1 D7 D6 D5 D4 D3 D2 D1 D0
Va
The content of this register is the 8-bit DATA byte received or to be transmitted. Writing of this register
triggers receiving or transmitting data.
Table 13-6 GPSI Communication Flag Register (SIFLG, 0x2F05)
0x2F05, R/W, GPSI Communication Flag Register (SIFLG)
Bit[7:2] Reserved R/W 0
When the interface is receiving or transmitting data, this bit is

set to 1. In this case, writing of registers located at addresses
Bit1 BUSY R 0
0x2F01~0x2F04 will trigger illegal data interrupt when this
interrupt is enabled.

V98XX Datasheet
0x2F05, R/W, GPSI Communication Flag Register (SIFLG)
When Master works as the receiver, writing of this bit and

transmit it to acknowledge the transmitter or not.
When Master works as the transmitter, writing 1 to this bit to

Bit0 ACK R/W 0 transmit it, and read this bit after the transmission to check
whether the receiver acknowledge the transmitter or not.
1: not acknowledged.
0: acknowledged.
h
ec
ot
ng
Va

V98XX Datasheet
14. LCD Driver

V98XX has the LCD driver which can drive the LCD panel of 4×40 or 6×38 segments (1/3 bias) or
8×36 segments (1/3 bias or 1/4 bias). “CLK3”, sourced by the 32.768-kHz OSC clock, provides the LCD
driver with the clock pulse. The driver is powered by the regulated voltage output from the 3.3-V LDO;
the LCD bias generator composed of an internal resistor ladder generates the LCD waveform voltage;
and the LCD waveform voltage level can be adjusted over the range of 2.7 V ~ 3.3 V with a resolution
of 0.1 V/lsb.
When a POR/BOR, RSTn pin reset, or WDT overflow reset occurs, the LCD driver will be reset to its
default state.
h
ON/OFF
VDD5 LDO33 VLCD

COM0
COM1
LCD Bias Generator
ec
R COM2
COM/SEG Driver
COM3
3/4 VLCD
R COM4/SEG0
VLCD
COM5/SEG1
2/3 VLCD
IO
COM6/SEG8
R Or
2/4 VLCD COM7/SEG9
SEG2
1/3 VLCD
Or
ot
R
1/4 VLCD
...
AVSS SEG39
Frame Display
LCD SEG control
OSC CLK CLK3 Frequency
fLCD timing registers
buffer
ng
Config. registers
LCDG FRQ0 FRQ1 LCDTYPE

SFR 0x80.3
Figure 14-1 LCD Driver Block Diagram

Va
14.1. Pins for LCD Driver

In V98XX, some pins are multiplexed by SEG/COM signal output, general-purpose input/output (GPIO),
and analog input of M Channel or comparator CB.
When some bits of SEG Control Registers (R/W) are set to 1s, the corresponding pins are used for SEG
output. In this condition, it is mandatory to configure the GPIO ports as “Input disabled” and “Output
disabled” in the corresponding input and output enabled registers.
When the pins work as GPIO or analog input of M Channel or comparator CB, the corresponding bits
of SEG Control Registers (R/W) must be cleared to disable SEG output.

V98XX Datasheet
14.2. LCD Timing

In the V98XX, the CLK3, sourced by the 32.768kHz OSC clock, provides the LCD driver with clock pulse
for timing generation. Generally, the crystal oscillator keeps on running until it is powered off, so the LCD
driver keeps on working even in Sleep or Deep Sleep state unless CLK3 is disabled. When the crystal
stops running anomaly when power is still on, the internal RC clock will become the replacement of the
OSC clock to source the LCD driver until the crystal is stimulated to run again.
The CLK3 frequency is divided to generate frame frequency for the waveform. The MCU can configure
bit[1:0] of LCDCtrl (0x2C1E) to select the appropriate frame frequency. By default it is 64Hz.
14.3. LCD Waveform Voltage
h
In the V98XX, the LCD driver is powered by the 3.3V LDO output voltage, and an internal resistor
ladder is designed to generate LCD waveform voltage (VLCD). Users can adjust the waveform voltage
ec
via bits VLCD (bit2 of CtrlLCDV, 0x285E) and LDO3SEL<2:0> configurations.
[LDO3SEL < 2: 0 >]

VLCD = [VLCD] × Equation 14-1
3.3
where,
ot
VLCD is the LCD waveform voltage;
[LDO3SEL<2:0>] is the output voltage of 3.3V LDO (LDO33). [LDO3SEL<2:0>] is equal to

configuration of bits LDO3SEL<2:0> (bit[5:3] of CtrlLDO, 0x2866);
[VLCD] is the configuration of bit VLCD (bit2 of CtrlLCDV, 0x285E).

ng
Table 14-1 VLCD to Configuration of [LDO3SEL<2:0>] and [VLCD]
[LDO3SEL<2:0>] 3.5V 3.4V 3.3V 3.2V 3.1V 3.0V
3.3V 3.5V 3.4V 3.3V 3.2V 3.1V 3.0V

[VLCD]
3.0V 3.2V 3.1V 3.0V 2.9V 2.8V 2.7V
Va
Users can adjust the resistance value of each resistor in the resistor ladder of the bias voltage
generation circuits via bits DRV1/DRV0 (bit[3:2] of LCDCtrl, 0x2C1E) to adjust the current through the
circuits to change the lightness of the display panel. By default the resistance value is 300 kΩ.
14.4. Display RAM

In the V98XX, the display RAM located at addresses of 0x2C00~0x2C1D and 0x2C28~0x2C31 stores
the LCD data. When the SEG/COM driver is enabled (setting bit7 of LCDCtrl to 1), the LCD panel displays
the data immediately they are updated in the RAM. When the SEG/COM driver is disabled (clearing bit7
of LCDCtrl), the LCD panel displays nothing. When POR/BOR, RSTn pin reset or WDT overflow event
occurs, the SEG/COM driver will be reset and the RAM will be cleared.
The LCD driver supports LCD panel of 1/4 duty, 1/6 duty or 1/8 duty. When bits LCDTYPE (bit[5:4] of

V98XX Datasheet
LCDCtrl, 0x2C1E) are cleared, an LCD panel of 1/4 Duty should be used. In this application, each byte
of display RAM stores content of 2 LCD segments: lower 4 bits for Seg (n), and higher 4 bits for Seg
(n+1).
Table 14-2 RAM Byte Allocation for Segments of LCD Panel of 1/4 Duty
D7 D6 D5 D4 D3 D2 D1 D0
Register Segment
COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
0x2C00 LCDM0 S01 S00 SEG01 SEG00
h
ec

ot
0x2C0A LCDM10 S21 S20 SEG21 SEG20
0x2C0B LCDM11 S23 S22 SEG23 SEG22

ng
0x2C0C LCDM12 S25 S24 SEG25 SEG24
0x2C0D LCDM13 S27 S26 SEG27 SEG26
0x2C0E LCDM14 S29 S28 SEG29 SEG28
0x2C0F LCDM15 S31 S30 SEG31 SEG30

Va
When bits LCDTYPE (bit[5:4] of LCDCtrl, 0x2C1E) are set to 1, an LCD panel of 1/6 Duty should be
used. In this application, by default every 3 bytes of display RAM store content of 4 LCD segments. But
when bit 6COMTYPE (bit6 of LCDCtrl, 0x2C1E) is set to 1, each byte of display RAM stores content of one
LCD segment.
Table 14-3 RAM Byte Allocation for Segments of LCD Panel of 1/6Duty When 6COMTYPE=0
Register SEG D7 D6 D5 D4 D3 D2 D1 D0
0x2C01 LCDM1 S02 -- SEG02

V98XX Datasheet
Register SEG D7 D6 D5 D4 D3 D2 D1 D0
h
ec
0x2C0D LCDM13 S18 S17 S18 S17
0x2C0E LCDM14 S19 S18 SEG19 SEG18

ot
0x2C0F LCDM15 S21 S20 SEG21 SEG20

ng

Va
0x2C1D LCDM29 S39 S38 SEG39 SEG38
Table 14-4 RAM Byte Allocation for Segments of LCD Panel of 1/6 Duty When 6COMTYPE=1

V98XX Datasheet
Register D7 D6 D5 D4 D3 D2 D1 D0
0x2C02 LCDM2 - - SEG02
h
ec
0x2C0A LCDM10 - - SEG10
0x2C0B LCDM11 - - SEG11
0x2C0C LCDM12 - - SEG12

ot
0x2C0D LCDM13 - - SEG13
0x2C0E LCDM14 - - SEG14

ng
0x2C0F LCDM15 - - SEG15
0x2C10 LCDM16 - - SEG16
0x2C11 LCDM17 - - SEG17
0x2C12 LCDM18 - - SEG18

Va
0x2C13 LCDM19 - - SEG19
0x2C14 LCDM20 - - SEG20
0x2C15 LCDM21 - - SEG21
0x2C16 LCDM22 - - SEG22
0x2C17 LCDM23 - - SEG23
0x2C18 LCDM24 - - SEG24
0x2C19 LCDM25 - - SEG25

V98XX Datasheet
0x2C28 LCDM30 - - SEG30
0x2C29 LCDM31 - - SEG31
h
ec
0x2C2E LCDM36 - - SEG36

ot
0x2C2F LCDM37 - - SEG37
0x2C30 LCDM38 - - SEG38

ng
0x2C31 LCDM39 - - SEG39
When bits LCDTYPE (bit[5:4] of LCDCtrl, 0x2C1E) are set to 2 or 3, an LCD panel of 1/8 Duty should
be used. In this application, each byte of display RAM stores content of one LCD segment.
Table 14-5 RAM Byte Allocation for Segments of LCD Panel of 1/8 Duty
Va
0x2C02 LCDM2 SEG02
0x2C03 LCDM3 SEG03
0x2C04 LCDM4 SEG04
0x2C05 LCDM5 SEG05
0x2C06 LCDM6 SEG06
0x2C07 LCDM7 SEG07
0x2C0A LCDM10 SEG10

V98XX Datasheet
0x2C0B LCDM11 SEG11
0x2C0C LCDM12 SEG12
0x2C0D LCDM13 SEG13
0x2C0E LCDM14 SEG14
0x2C0F LCDM15 SEG15
0x2C10 LCDM16 SEG16
h
0x2C11 LCDM17 SEG17
ec
0x2C12 LCDM18 SEG18
0x2C13 LCDM19 SEG19
0x2C14 LCDM20 SEG20
0x2C15 LCDM21 SEG21

ot
0x2C16 LCDM22 SEG22
0x2C17 LCDM23 SEG23

ng
0x2C18 LCDM24 SEG24
0x2C19 LCDM25 SEG25
0x2C1A LCDM26 SEG26
0x2C1B LCDM27 SEG27

Va
0x2C1C LCDM28 SEG28
0x2C1D LCDM29 SEG29
0x2C28 LCDM30 SEG30
0x2C29 LCDM31 SEG31
0x2C2A LCDM32 SEG32
0x2C2B LCDM33 SEG33
0x2C2C LCDM34 SEG34

V98XX Datasheet
0x2C2D LCDM35 SEG35
0x2C2E LCDM36 SEG36
0x2C2F LCDM37 SEG37
0x2C30 LCDM38 SEG38
0x2C31 LCDM39 SEG39
h
14.5. LCD Drive Waveform
ec
There are 4 resistors in series in the bias voltage generation circuit, which can be configured to work
in 1/3 bias mode or 1/4 bias mode.
When an LCD panel of 1/4 or 1/6 duty is applied, only 1/3 bias mode can be used.
When an LCD panel of 1/8 duty is applied, users can configure bit LCDBMOD (bit3 of CtrlBAT, 0x285C)
to disable or enable one resistor in the bias voltage generation circuit to enable the LCD driver to work
ot
in 1/3 bias mode or 1/4 bias mode.
When an LCD panel of 1/4 duty is applied, the LCD drive waveform is depicted in the following figure.
ng
Va

V98XX Datasheet
OFF ON
LCD Seg State 1 Frame
VLCD-
2/3 VLCD-
COM0
1/3 VLCD-
GND-
VLCD-
2/3 VLCD-
COM1
1/3 VLCD-
GND-
VLCD-
2/3 VLCD-
COM2
h
1/3 VLCD-
GND-
VLCD-
ec
2/3 VLCD-
COM3
1/3 VLCD-
GND-
VLCD-
2/3 VLCD-
SEGn
1/3 VLCD-
GND-
ot
VLCD-
2/3 VLCD-
SEGn+1
1/3 VLCD-
GND-
ng
VLCD-
2/3 VLCD-
1/3 VLCD-
COM0_SEGn
GND-
-1/3 VLCD-
-2/3 VLCD-
-VLCD-
Va
VLCD-
2/3 VLCD-
1/3 VLCD-
COM0_SEGn+1
GND-
-1/3 VLCD-
-2/3 VLCD-
-VLCD-
Figure 14-2 LCD Drive Waveform When an LCD Panel of 1/4 Duty and 1/3 Bias is Applied
When an LCD panel of 1/6 duty is applied, the LCD drive waveform is depicted in the following figure.

V98XX Datasheet
OFF ON
LCD SEG State 1 Frame
VLCD-
2/3 VLCD-
COM0
1/3 VLCD-
GND-
VLCD-
2/3 VLCD-
COM1
1/3 VLCD-
GND-
VLCD-
2/3 VLCD-
COM2
1/3 VLCD-
GND-
VLCD-
h
2/3 VLCD-
COM3
1/3 VLCD-
GND-
VLCD-
ec
2/3 VLCD-
COM4
1/3 VLCD-
GND-
VLCD-
2/3 VLCD-
COM5
1/3 VLCD-
GND-
ot
VLCD-
2/3 VLCD-
SEGn
1/3 VLCD-
GND-
VLCD-
2/3 VLCD-
SEGn+1
1/3 VLCD-
ng
GND-
VLCD-
2/3 VLCD-
1/3 VLCD-
COM0_SEGn
GND-
-1/3 VLCD-
-2/3 VLCD-
-VLCD-
Va
VLCD-
2/3 VLCD-
1/3 VLCD-
COM0_SEGn+1
GND-
-1/3 VLCD-
-2/3 VLCD-
-VLCD-
When an LCD panel of 1/8 duty is applied, the LCD drive waveform is depicted in the following figures.

V98XX Datasheet
OFF ON
LCD SEG State

1 Frame
VLCD-
2/3 VLCD-
COM0
1/3 VLCD-
GND-
VLCD-
2/3 VLCD-
COM1
1/3 VLCD-
GND-
VLCD-
2/3 VLCD-
COM2
1/3 VLCD-
GND-
VLCD-
2/3 VLCD-
COM3
1/3 VLCD-
GND-
h
VLCD-
2/3 VLCD-
COM4
1/3 VLCD-
GND-
ec
VLCD-
2/3 VLCD-
COM5
1/3 VLCD-
GND-
VLCD-
2/3 VLCD-
COM6
1/3 VLCD-
GND-
VLCD-
ot
2/3 VLCD-
COM7
1/3 VLCD-
GND-
VLCD-
SEGn 2/3 VLCD-
1/3 VLCD-
GND-
ng
VLCD-
2/3 VLCD-
SEGn+1
1/3 VLCD-
GND-
VLCD-
2/3 VLCD-
1/3 VLCD-
COM0_SEGn
GND-
-1/3 VLCD-
-2/3 VLCD-
-VLCD-
Va
VLCD-
2/3 VLCD-
1/3 VLCD-
COM0_SEGn+1
GND-
-1/3 VLCD-
-2/3 VLCD-
-VLCD-

V98XX Datasheet
OFF ON
1 Frame
LCD SEG State VLCD-
3/4 VLCD-
COM0
1/4 VLCD-
GND-
VLCD-
3/4 VLCD-
COM1
1/4 VLCD-
GND-
VLCD-
3/4 VLCD-
COM2
1/4 VLCD-
GND-
VLCD-
3/4 VLCD-
COM3
1/4 VLCD-
GND-
VLCD-
3/4 VLCD-
h
COM4
1/4 VLCD-
GND-
VLCD-
3/4 VLCD-
COM5
ec
1/4 VLCD-
GND-
VLCD-
3/4 VLCD-
COM6
1/4 VLCD-
GND-
VLCD-
3/4 VLCD-
COM7
1/4 VLCD-
ot
GND-
VLCD-
SEGn 1/2 VLCD-
GND-
VLCD-
SEGn+1 1/2 VLCD-

ng
GND-
VLCD-
3/4 VLCD-
1/2 VLCD-
1/4 VLCD-
GND-
COM0_SEGn -1/4 VLCD-
-1/2 VLCD-
-3/4 VLCD-
-VLCD-
VLCD-
Va
3/4 VLCD-
1/2 VLCD-
1/4 VLCD-
COM0_SEGn+1 GND-
-1/4 VLCD-
-1/2 VLCD-
-3/4 VLCD-
-VLCD-
14.6. Registers
Table 14-6 LCD Control Register (LCDCtrl, 0x2C1E)

V98XX Datasheet
0x2C1E, R/W, LCD Control Register, LCDCtrl
To enable or disable the COM/SEG driver of the LCD driver.
Bit7 ON/OFF 0 Set this bit to 1 to enable the COM/SEG driver to output COM and SEG
signals to the LCD panel. Otherwise, this circuit outputs high
impedance.
When 1/6 Duty is applied, set this bit to 1 to enable each byte of
display RAM to store content of one LCD segment. By default, every
Bit6 6COMTYPE 0
6 bits of display RAM store content of 1 LCD segments in 1/6 Duty
mode.
h
To define LCD duty.
00: 1/4 Duty;

Bit[5:4] LCDTYPE 0
ec
01: 1/6 Duty;
10/11: 1/8 Duty.
Bit3 DRV1 0 To set the resistance value of each resistor in the internal resistor
ladder for bias voltage generation.
ot
00: 300kΩ;
01: 600kΩ;
Bit2 DRV0 0
10: 150kΩ;
11: 200kΩ.
ng
Bit1 FRQ1 0 To configure the frame frequency.
11: 512Hz;
10: 256Hz;
Bit0 FRQ0 0
01: 128Hz;
Va
00: 64Hz.
Table 14-7 Enable/Disable CLK3
Set this bit to 1 to stop CLK3. By default this clock is running.

bit3
LCDG 0 Only when the PLL clock is selected as the clock source for CLK1 and CLK2
can CLK3 be disabled.
Table 14-8 Register to Select Bias Mode

V98XX Datasheet
0x285C, R/W, Battery Discharge Control Register, CtrlBAT
bit[7:4] Reserved 0 These bits must hold their default values for proper operation.
When the LCD driver works in 1/8 duty mode, set this bit to select
the bias ratio.
0: 1/3 Bias;
bit3 LCDBMOD 0
1: 1/4 Bias.
When the LCD driver works in 1/4 or 1/6 duty mode, 1/3 Bias ratio
is used whatever this bit is set.
h
To adjust the bias current of the amplifier of the voltage channel
ADC.
00: 0%;
ec
bit[2:1] IITU<1:0> 0
01: -33%;
11:+33%;
10: 100%.
ot
bit0 BATDISC 0 To enable discharging the battery. 1: enable; 0: disable.
Table 14-9 LCD Waveform Voltage Configuration 1
0x285E, R/W, LCD Driver Voltage Control Register, CtrlLCDV

ng
By default additional 10mV direct voltage offset is applied to the

Bit7 DCENN 0 current input. Set this bit to 1 to disable this function. This bit must
hold its default value for proper operation.
To adjust the LCD waveform voltage.

Va
bit2 VLCD 0 0: 3.3V;
1: 3.0V.
Table 14-10 LCD Waveform Voltage Configuration 2

V98XX Datasheet
0x2866, R/W, LDO Control Register, CtrlLDO
Set this bit to 1 to disable the internal power detection circuit.

By default this circuit is enabled.
When the chip is 3.3V powered, users must set this bit to 1 to
Bit7 PDDET 0 disable the power detection circuit, to prevent current leakage
of the battery when a battery is connected to the device.
When the chip is 5V powered, this bit must hold its default
value.
Bit6 LDO3IT 0 Set this bit to 1 to increase bias current of LDO33 by 100%.
h
To adjust output voltage of LDO33.
Bit[5:3] LDO3SEL 0 000: 3.3V; 001: 3.2V; 010/100/101: 3.5V; 011: 3.4V; 110:
ec
3.1V; 111: 3.0V.
To adjust output voltage of digital power circuit.

Bit[2:0] LDOV2SEL<2:0> 0 000: +0V; 001: -0.1V; 010: +0.2V; 011: +0.1V; 100: -0.4V;
101: -0.5V; 110: -0.2V; 111: -0.3V.
ot
Table 14-11 SEG Control Registers (R/W)
Register bit7 bit6 bit5 Bit4 bit3 bit2 bit1 bit0
0x2C1F SegCtrl0 SEGON7 SEGON6 SEGON5 SEGON4 SEGON3 SEGON2 SEGON1 SEGON0
0x2C20 SegCtrl1 SEGON15 SEGON14 SEGON13 SEGON12 SEGON11 SEGON10 SEGON9 SEGON8
ng
Default 0 0 0 0 0 0 0 0
Va
0: to disable SEG signal output.
1: to enable SEG signal Output.
In the V98XX, the pins for SEG output are multiplexed by GPIO and analog input of M Channel. When
these pins are configured for SEG output, they must be set to “input and output are disabled” for GPIO
purpose. When the pins work as GPIO ports or for analog input of M Channel, they must be set to
“disable SEG signal output” in these registers.
When bits LCDTYPE (bit[5:4] of LCDCtrl, 0x2C1E) are cleared, bit[1:0] of SegCtrl0 and SegCtrl1 are
valid.
When bits LCDTYPE is set to 1, bit[1:0] of SegCtrl1 is valid, but bit[1:0] of SegCtrl0 is invalid.
When bits LCDTYPE is set to 2 or 3, bit[1:0] of SegCtrl1 and SegCtrl0 are invalid.

V98XX Datasheet
15. GPIO
In the V98XX there are 11 groups, P0~P10, 70 general-purpose input/output ports (GPIO) in total
of which:
 Ports of Group P0 are multiplexed by general input/output and JTAG interfaces. When the chip
operates in metering mode, besides for general input/output, both P0.2 and P0.3 can be used to
wake up the system from sleeping state. When the chip operates in debugging mode, these ports
work as JTAG interfaces;
 Ports of Group P1 and P2 are multiplexed by general input/output and special functions. Both P1.3
and P1.4 can be used to wake up the system from sleeping state;
 Ports of Group P3 are multiplexed by general input/output and COM of the LCD driver;
h
 Ports of Group P4 and P5 are multiplexed by general input/output and COM or SEG output of the LCD
driver;
 Ports of Group P6~P8 are multiplexed by general input/output and SEG output of the LCD driver;
ec
 Ports of Group 9 are general-purpose input/output ports which has a communication rate of 200kbps
when CLK1 frequency is 13.1072MHz. These ports are named Fast IO in this datasheet. These ports
are multiplexed by general input/output and special functions;
 Ports of Group 10 are general-purpose input/output ports which has a communication rate of 200kbps
when CLK1 frequency is 13.1072MHz. These ports are named Fast IO in this datasheet. These ports
can be configured for transmitter data output and receiver data input of enhanced UART ports.
ot
All the I/O ports have features:
 Ports of Group P0~P8 can be gate controlled simultaneously; Ports of Group P9 and P10 can be gate
controlled independently;
 When POR/BOR, RSTn pin reset or WDT overflow event occurs, all ports will be reset to their default
states: both input and output are disabled;
ng
 In Sleep or Deep Sleep state, all ports hold their states;
 No pull-up or pull-down resistors are connected internally in all I/O ports.
15.1. P0
Va
In Group P0 there are 4 ports, which are multiplexed by general-purpose input/output and JTAG
interfaces.
When the level on the pin MODE1 is driven low, all ports of this group will work as JTAG interfaces. In
this state, Port P0.0 is used for test data output (TDO); Port P0.1 is used for test data input (TDI); Port
P0.2 is used for test mode select (TMS); Port P0.3 is used for test clock input (TCK).
When the level on the pin MODE1 is pulled high, all ports of this group will work as general-purpose
input/output ports, and the input and output enable registers determine the state of each port. Set bit
P0P8 (bit3 of PRCtrl0, 0x2D00) to 1 to gate control ports of Group P0~P8 to lower power consumption
when these ports are not used. Besides, bit IOP0 (bit1 of IOWK, SFR 0xC9) determines both P0.2 and
P0.3 to be used for IO wakeup inputs. See “IO Wakeup ” for details.

V98XX Datasheet
MODE MODE
0 0 1
1 P0 input enable 1 P0 input enable
P0 input data 1
P0 input data
0 0
0
TCK, TMS or TDI
P0.0 P0 output enable P0.1/P0.2/P0.3 1
0 1 P0 output enable
0 1
0 TDO
P0 output data
1 P0 output data
Figure 15-1 Architecture of P0.0 Figure 15-2 Architecture of P0.1/P0.2/P0.3
h
Table 15-1 P0 Output Enable Register (P0OE, 0x28A8)
0x28A8, R/W, P0 Output Enable Register, P0OE
ec
- - - - P03OEN P02OEN P01OEN P00OEN
Default X X X X 1 1 1 1
1: disable; 0: enable; X: do not care.

ot
Table 15-2 P0 Input Enable Register (P0IE, 0x28A9)
0x28A9, R/W, P0 Input Enable Register, P0IE

ng
- - - - P03INEN P02INEN P01INEN P00INEN
Table 15-3 P0 Output Data Register (P0OD, 0x28AA)

Va
0x28AA, R/W, P0 Output Data Register, P0OD
bit7 Bit6 bit5 bit4 bit3 bit2 bit1 bit0
X: do not care.
Table 15-4 P0 Input Data Register (P0ID, 0x28AB)
0x28AB, R/W, P0 Input Data Register, P0ID

V98XX Datasheet
X: do not care.
the state change of an I/O port will lead to value variation of this register, which consumes more power.
So to lower power consumption, it is recommended to disable data input if no need to read the input
data.
15.2. P1
In Group P1 there are 5 ports, which are multiplexed by general-purpose input/output and special
functions.
The function of each port can be configured via the dedicated special function register. When a port
h
works as a general-purpose input/output port, the input and output enable registers determine its state.
Set bit P0P8 (bit3 of PRCtrl0, 0x2D00) to 1 to gate control ports of Group P0~P8 to lower power
consumption when these ports are not used. However, setting this bit to 1 after configuring these ports
ec
to work for special functions has no effect on its functions.
P1 input enable
P1 input data
ot
0
Special function
1 (input)
P1 special function
configuration
ng
P1 output data
Special function
(output)
P1 output enable
Va
Figure 15-3 Architecture of Each Port of Group P1

If port P1.3 and/or P1.4 is set to “input enabled” before the system enters Sleep or Deep Sleep, the
system will be woken up when a transition occurs to either port (either high-to-low or low-to-high,
holding high and low level for at least 4 OSC clock cycles). See “IO Wakeup ” for details.
Table 15-5 P1 Output Enable Register (P1OE, 0x28AC)
0x28AC, R/W, P1 Output Enable Register, P1OE
- - - P14OEN P13OEN P12OEN P11OEN P10OEN
Default X X X 1 1 1 1 1

V98XX Datasheet
Table 15-6 P1 Input Enable Register (P1IE, 0x28AD)
0x28AD, R/W, P1 Input Enable Register, P1IE
- - - P14INEN P13INEN P12INEN P11INEN P10INEN
Table 15-7 P1 Output Data Register (P1OD, 0x28AE)
h
0x28AE, R/W, P1 Output Data Register, P1OD
ec
X: do not care.
Table 15-8 P1 Input Data Register (P1ID, 0x28AF)

ot
0x28AF, R/W, P1 Input Data Register, P1ID
X: do not care.
ng
When input is enabled, users can read the state of each I/O port via this register all the time, which is
not affected by the special function of the port. But the state change of an I/O port will lead to value
variation of this register, which consumes more power. So to lower power consumption, it is
recommended to disable data input if no need to read the input data.
Table 15-9 P1.0 Special Function Register (P10FS, 0x28C4, R/W)

Va
Bit[7:2] Reserved. 0
00: GPIO, general-purpose input/output port;
01: SP, pulse per second (PPS) output from the RTC. On calibrating the
P10FNC1
Bit[1:0] 0 RTC, every 30 seconds, from the 1st to 29th second, an un-calibrated
P10FNC0 pulse is output every second, and in the 30th second, a calibrated pulse
is output that averages the period of each pulse in the 30 seconds to
be 1s.

V98XX Datasheet

P11FNC2
010: RXD1, receiver data input of UART1;
Bit[2:0] P11FNC1 0
011: T1, Timer1 external input;
P11FNC0
100: IO interrupt input 2.
h
ec
P12FNC2 001: reserved;
Bit[2:0] P12FNC1 0 010: TXD1, transmitter data output of UART1;
P12FNC0 011: T2EX, Timer2 capture or reload trigger input;

ot
ng
001: CF2, CF pulse output of E2 path;
010: RXD5, receiver data input of UART5;
011: IO interrupt input 0;
P13FNC2 100: CF1, CF pulse output of E1 path;

Va
Bit[2:0] P13FNC1 0 101: SP, pulse per second (PPS) output from the RTC. On calibrating
the RTC, every 30 seconds, from the 1st to 29th second, an un-
P13FNC0
calibrated pulse is output every second, and in the 30th second, a
calibrated pulse is output that averages the period of each pulse in the
30 seconds to be 1s.
110: PLLDIV, pulse output proportional to the divided PLL clock

frequency, can be configured to output pulses of 1s width from the PLL
counter.
Table 15-13 P1.4 Special Function Register (P14FS, 0x28C8)

V98XX Datasheet
001: PLLDIV, pulse output proportional to the divided PLL clock

P14FNC1 frequency, can be configured to output pulses of 1s width from the PLL
Bit[1:0] 0 counter;
P14FNC0
010: TXD5, transmitter data output of UART5;
15.3. P2
h
In Group P2 there are 6, which are multiplexed by general-purpose input/output and special functions.
The function of each port can be configured via the dedicated special function register. When a port
ec
works as a general-purpose input/output port, the input and output enable registers determine its state.
Set bit P0P8 (bit3 of PRCtrl0, 0x2D00) to 1 to gate control ports of Group P0~P8 to lower power
consumption when these ports are not used. However, setting this bit to 1 after configuring these ports
to work for special functions has no effect on its functions.
P2 input enable
ot
P2 input data
0
Special function
1 (input)
P2 special function
ng
P2 output data
Special function
(output)
P2 output enable
Va
Table 15-14 P2 Output Enable Register (P2OE, 0x28B0)
0x28B0, R/W, P2 Output Enable Register, P2OE
- - P25OEN P24OEN P23OEN P22OEN P21OEN P20OEN
Default X X 1 1 1 1 1 1
Table 15-15 P2 Input Enable Register (P2IE, 0x28B1)
0x28B1, R/W, P2 Input Enable Register, P2IE

V98XX Datasheet
- - P25INEN P24INEN P23INEN P22INEN P21INEN P20INEN
Default X X 0 0 0 0 0 0
Table 15-16 P2 Output Data Register (P2OD, 0x28B2)
0x28B2, R/W, P2 Output Data Register, P2OD
Default X X 1 1 1 1 1 1
h
X: do not care.
Table 15-17 P2 Input Data Register (P2ID, 0x28B3)
ec
0x28B3, R/W, P2 Input Data Register, P2ID
Default X X 0 0 0 0 0 0
X: do not care.
ot
ng

Va
P20FNC1 01: OSC, OSC clock waveform output;

Bit[1:0] 0
P20FNC0 10: RXD4, receiver data input of UART4;
11: T2, Timer2 external input.
Table 15-19 P2.1 Special Function Register (P21FS, 0x28CA, R/W)

P21FNC1
Bit[1:0] 0 01: reserved;
P21FNC0
10: TXD4, transmitter data output of UART4;

V98XX Datasheet
11: T0, Timer0 external input.
Table 15-20 P2.2 Special Function Register (P22FS, 0x28CB, R/W) (V98XX)

P22FNC1
Bit[1:0] 0 10: RXD3, receiver data input of UART3;
P22FNC0
01/11: reserved.
Table 15-21 P2.3 Special Function Register (P23FS, 0x28CC, R/W) (V98XX)
h
ec
P23FNC1 00: GPIO, general-purpose input/output port;
Bit[1:0] 0
P23FNC0 10: TXD3, transmitter data output of UART3.
Table 15-22 P2.4 Special Function Register (P24FS, 0x28CD, R/W)

ot
Bit[7:2] Reserved 0
P24FNC1 00: GPIO, general-purpose input/output port;

Bit[1:0] 0
P24FNC0 10: RXD2, receiver data input of UART2.
ng
Table 15-23 P2.5 Special Function Register (P25FS, 0x28CE, R/W)
Bit[7:2] Reserved 0

P25FNC1
Va
Bit[1:0] 0 10: TXD2, transmitter data output of UART2. This port can be
P25FNC0
configured to transmit 38kHz carrier wave.
15.4. P3
In Group P3 there are 4 ports, which are multiplexed by general-purpose input/output andCOM.
When a port works as COM, in input and output enable registers the corresponding bit must be
configured “input disabled, output disabled”.
When a port works as a general-purpose input/output port, the SEG/COM driver in the LCD driver must
be disabled (bit7 of LCDCtrl, 0x2C1E). Set bit P0P8 (bit3 of PRCtrl0, 0x2D00) to 1 to gate control ports
of Group P0~P8 to lower power consumption when these ports are not used.

V98XX Datasheet
COMx
P3 input enable
LCDON
P3 input data
P3 output data
h
P3 output enable
ec

ot
- - - - P33OEN P32OEN P31OEN P30OEN

ng
- - - - P33INEN P32INEN P31INEN P30INEN

Va
Table 15-26 P3 Output Data Register (P3OD, 0x28B6)
0x28B6, R/W, P3 Output Data Register, P3OD
X: do not care.
Table 15-27 P3 Input Data Register (P3ID, 0x28B7)
0x28B7, R/W, P3 Input Data Register, P3ID

V98XX Datasheet
X: do not care.
15.5. P4
In Group P4 there are 8 ports, which are multiplexed by General-Purpose Input/Output (GPIO) and
signal output of the LCD driver.
When LCDTYPE=0 Ports P4.0~P4.7 can be configured to be multiplexed by SEG output and general-
purpose input/output. When LCDTYPE=1/2/3, P4.0~ P4.7 are multiplexed by COM output and general-
h
purpose input/output.
When a port works as backplanes or SEG output of the LCD driver, in input and output enable registers,
ec
P4OE (0x28B8) and P4IE (0x28B9), the corresponding bit must be configured “input disabled, output
disabled”.
When a port works as a general-purpose input/output port, the SEG output on the corresponding port
must be disabled and input and output enable registers determine its state. Set bit P0P8 (bit3 of PRCtrl0,
0x2D00) to 1 to gate control ports of Group P0~P8 to lower power consumption when these ports are
not used.
ot
SEGx COMx
LCDON LCDTYPE
P4 input enable
ng
SEGxON P4 input data
P4 output data
Va
P4 output enable
P47OEN P46OEN P45OEN P44OEN P43OEN P42OEN P41OEN P40OEN
Default 1 1 1 1 1 1 1 1

V98XX Datasheet
P47IN P46INE P45INE P44INE P43INE P42INE P41INE P40INE

EN N N N N N N N
Default 0 0 0 0 0 0 0 0
h
Table 15-30 P4 Output Data Register (P4OD, 0x28BA)
0x28BA, R/W, P4 Output Data Register, P4OD
ec
Default 1 1 1 1 1 1 1 1
X: do not care.
Table 15-31 P4 Input Data Register (P4ID, 0x28BB)

ot
0x28BB, R/W, P4 Input Data Register, P4ID
Default X X X X X X X X
ng
X: do not care.
Va
15.6. P5
In Group P5 there are 8 ports, which are multiplexed by general-purpose input/output and COM of the
LCD driver.
Ports P5.0 and P5.1 can be configured to be multiplexed by SEG output and general-purpose
input/output; when LCDTYPE=0 or 1, when LCDTYPE=2or3, and ports P5.2-P5.7 are multiplexed by SEG
output and general-purpose input/output.
When a port works as COM or SEG output of the LCD driver, in input and output enable registers, the
corresponding bit must be configured “input disabled, output disabled”.
When a port works as a general-purpose input/output port, SEG or COM output on the corresponding
port must be disabled, and input and output enable registers determine its state. Set bit P0P8 (bit3 of
PRCtrl0, 0x2D00) to 1 to gate control ports of Group P0~P8 to lower power consumption when these

V98XX Datasheet
ports are not used.
SEGx
LCDON P5 input enable
P5 output data
h
ec
P5 output enable
Table 15-32 P5 Output Enable Register (P5OE, 0x28BC)
0x28BC, R/W, P5 Output Enable Register, P5OE

ot
Default 1 1 1 1 1 1 1 1
ng
Table 15-33 P5 Input Enable Register (P5IE, 0x28BD)
0x28BD, R/W, P5 Input Enable Register, P5IE

Va
P57INEN P56INEN P55INEN P54INEN P53INEN P52INEN P51INEN P50INEN
Default 0 0 0 0 0 0 0 0
Table 15-34 P5 Output Data Register (P5OD, 0x28BE)
0x28BE, R/W, P5 Output Data Register, P5OD
Default 1 1 1 1 1 1 1 1
Table 15-35 P5 Input Data Register (P5ID, 0x28BF)
0x28BF, R/W, P5 Input Data Register, P5ID

V98XX Datasheet
Default 0 0 0 0 0 0 0 0
15.7. P6
In Group P6 there are 8 ports, which are multiplexed by general-purpose input/output and SEG output
h
of the LCD driver.
When a port works as SEG output of the LCD driver, in input and output enable registers, the
ec
When a port works as a general-purpose input/output port, SEG output on the corresponding port must
be disabled, and input and output enable registers determine its state. Set bit P0P8 (bit3 of PRCtrl0,
not used.
ot
SEGx

ng
P6 output data
Va
P6 output enable
Table 15-36 P6 Output Enable Register (P6OE, 0x28C0)
0x28C0, R/W, P6 Output Enable Register, P6OE

V98XX Datasheet
Default 1 1 1 1 1 1 1 1
Table 15-37 P6 Input Enable Register (P6IE, 0x28C1)
0x28C1, R/W, P6 Input Enable Register, P6IE

EN N N N N N N N
h
Default 0 0 0 0 0 0 0 0
ec
Table 15-38 P6 Output Data Register (P6OD, 0x28C2)
0x28C2, R/W, P6 Output Data Register, P6OD
Default 1 1 1 1 1 1 1 1
ot
X: do not care.
Table 15-39 P6 Input Data Register (P6ID, 0x28C3)
0x28C3, R/W, P6 Input Data Register, P6ID

ng
Default 0 0 0 0 0 0 0 0
X: do not care.
Va
15.8. P7
of the LCD driver.
When a port works as SEG output of the LCD driver, in input and output enable registers the
When a port works as a general-purpose input/output port, the SEG output on the corresponding ports
must be disabled and input and output enable registers determine its state. Set bit P0P8 (bit3 of PRCtrl0,

V98XX Datasheet
not used.
SEGx
h
P7 output data
ec
P7 output enable
Table 15-40 P7 Output Enable Register (P7OE, 0x28D5)

ot
0x28D5, R/W, P7 Output Enable Register, P7OE

ng
Default 1 1 1 1 1 1 1 1
Table 15-41 P7 Input Enable Register (P7IE, 0x28D6)
0x28D6, R/W, P7 Input Enable Register, P7IE

Va

EN N N N N N N N
Default 0 0 0 0 0 0 0 0
Table 15-42 P7 Output Data Register (P7OD, 0x28D7)
0x28D7, R/W, P7 Output Data Register, P7OD
Default 1 1 1 1 1 1 1 1

V98XX Datasheet
Table 15-43 P7 Input Data Register (P7ID, 0x28D8)
0x28D8, R/W, P7 Input Data Register, P7ID
Default 0 0 0 0 0 0 0 0
15.9. P8
h
of the LCD driver.
ec
When a port works as SEG output of the LCD driver, in input and output enable registers, the
When a port works as a general-purpose input/output port, the SEG output on the corresponding port
must be disabled, and input/output enable registers determine its state. Set bit P0P8 (bit3 of PRCtrl0,
ot
not used.
SEGx

ng
P8 output data
Va
P8 output enable
Table 15-44 P8 Output Enable Register (P8OE, 0x28D9)
0x28D9, R/W, P8 Output Enable Register, P8OE
- - - - - P82OEN P81OEN P80OEN
Default X X X X X 1 1 1

V98XX Datasheet
Table 15-45 P8 Input Enable Register (P8IE, 0x28DA)
0x28DA, R/W, P8 Input Enable Register, P8IE
- - - - - P82INEN P81INEN P80INEN
Table 15-46 P8 Output Data Register (P8OD, 0x28DB)
h
0x28DB, R/W, P8 Output Data Register, P8OD
ec
X: do not care.
Table 15-47 P8 Input Data Register (P8ID, 0x28DC)

ot
0x28DC, R/W, P8 Input Data Register, P8ID
X: do not care.
ng
Va
15.10. P9
In Group P9 there are 8 ports, which are multiplexed by general-purpose input/output, special functions
and, P1.2 and P1.3 can be used GPSI.
When the ports work as general-purpose input/output ports, When CLK1 frequency is 13.1072MHz,
the communication rate of these ports is 200kbps; input and output enable registers determine their
states. But when a reference pulse of exact one second width is input to the port P9.1, the input of this
port is enabled automatically.
The function of each port can be configured via the register P9FS (SFR 0xAD).
When bit GPSI (bit6 of PRCtrl0, 0x2D00) is set to 1, port P9.1 and P9.2 are used for serial data and
clock delivery for general-purpose serial interface (GPSI). In this condition, P9.1 must be set to “input
enabled” The P9.1 output is determined by the data on SDA; and P9.2 is set to “output enabled” automatically，

V98XX Datasheet
Don’t need to configure P9.1 and P9.2 output register.
The port P9.0 can be used for SEG output of the LCD driver. When the port works as SEG output of the
LCD driver, in input and output enable registers, the corresponding bit must be configured “input disabled,
output disabled”.
Set bit P9 (bit4 of PRCtrl0, 0x2D00) to 1 to gate control ports of Group P9 to lower power consumption.
P9输入使能寄存器
P9输入数据寄存器
0
特殊功能（输入）
1
h
P9特殊功能选择寄存器
ec
P9输出数据寄存器
特殊功能（输出）
P9输出使能寄存器
ot
Table 15-48 P9 Output Enable Register (P9OE, SFR 0xA4)
SFR 0xA4, R/W, P9 Output Enable Register, P9OE

ng
Default 1 1 1 1 1 1 1 1

Va
Table 15-49 P9 Input Enable Register (P9IE, SFR 0xA5)
SFR 0xA5, R/W, P9 Input Enable Register, P9IE

EN N N N N N N N
Default 0 0 0 0 0 0 0 0

V98XX Datasheet
Table 15-50 P9 Output Data Register (P9OD, SFR 0xA6)
SFR 0xA6, R/W, P9 Output Data Register, P9OD
Default 1 1 1 1 1 1 1 1
Table 15-51 P9 Input Data Register (P9ID, SFR 0xA7)
SFR 0xA7, R/W, P9 Input Data Register, P9ID
Default 0 0 0 0 0 0 0 0
h
ec
Table 15-52 P9 Special Function Register (P9FS, SFR 0xAD)
SFR 0xAD, R/W, P9 Special Function Register, P9FS
Bit Description
ot
Bit7 P97FNC To configure the function of the port P9.7.
1: PWMCLK, PWM pulse output; 0: general-purpose input/output port in fast

mode.

ng
1: CF1, CF pulse output of E1 path; 0: general-purpose input/output port in

fast mode.
1: CF2, CF pulse output of E2 path; 0: general-purpose input/output port in

fast mode.
Va
1: SP, Pulse per second (PPS) output from the RTC. On calibrating the RTC,
every 30 seconds, from the 1st to 29th second, an un-calibrated pulse is
output every second, and in the 30 th second, a calibrated pulse is output
that averages the period of each pulse in the 30 seconds to be 1s;
0: general-purpose input/output port in fast mode.
1: PLLDIV, pulse output proportional to the divided PLL clock frequency, can
be configured to output pulses of 1s width from the PLL counter;

V98XX Datasheet
Bit Description
1: TA2, to input/output the signals for Timer A Compare/Capture Module 2;
h
15.11. P10
ec
In Group P10 there are 8 ports, which are multiplexed by general-purpose input/output and enhanced
UART interfaces. the port P10.0 is used for data input and output of EUART1. the port P10.1 is used for
data output of EUART2, and the port P10.2 is used for data input of EUART2.
When the ports work as general-purpose input/output ports, the ports of Group P10 have the same
ot
feature with those of Group P9. They are accessed in a fast mode. When CLK1 frequency is 13.1072MHz,
the communication rate of these ports is 200kbps. Input and output enable registers determine their
states.
When the bit ENABLE (bit0 of CFGA, 0x2A05) is set to 1, the port P10.0 is used for data input and
output of EUART1. In this condition, the output of this port is enabled automatically, and the input of this
ng
port is determined by the register P10IE (SFR 0xAA). When the bit ENABLE (bit0 of CFGB, 0x2B05) is
set to 1, the port P10.1 is used for data output of EUART2, and the port P10.2 is used for data input of
EUART2.In this condition, the output or input of the ports are determined by registers P10OE (SFR 0xA9)
and P10IE (SFR 0xAA).
Set bit P10 (bit5 of PRCtrl0, 0x2D00) to 1 to gate control ports of Group P10 to lower power
consumption when these ports are not used.
Va

V98XX Datasheet
P10输入使能寄存器
P10输入数据寄存器
0
特殊功能（输入）
1
P10特殊功能
选择寄存器
P10输出数据寄存器
特殊功能（输出）
h
P10输出使能寄存器
ec
Table 15-53 P10 Output Enable Register (P10OE, SFR 0xA9)
SFR 0xA9, R/W, P10 Output Enable Register, P10OE

ot
Default 1 1 1 1 1 1 1 1

ng
Table 15-54 P10 Input Enable Register (P10IE, SFR 0xAA)
SFR 0xAA, R/W, P10 Input Enable Register, P10IE
P107INEN P106INEN P105INEN P104INEN P103INEN P102INEN P101INEN P100INEN
Default 0 0 0 0 0 0 0 0
Va
Table 15-55 P10 Output Data Register (P10OD, SFR 0xAB)
SFR 0xAB, R/W, P10 Output Data Register, P10OD
Default 1 1 1 1 1 1 1 1
Table 15-56 P10 Input Data Register (P10ID, SFR 0xAC)
SFR 0xAC, R/W, P10 Input Data Register, P10ID

V98XX Datasheet
Default 0 0 0 0 0 0 0 0
Table 15-57 Configuration for EUART Communication
h
Bit7 1, Enable the interrupt for Rx overflow。
OVIE 0
ec
1, Ebable the Tx interrupt；
Bit6
SDIE 0 0, Disable the Tx interrupt。
ot
Bit5 1, Enable the Rx interrupt；
RCIE 0
0, Disbale the Rx interrupt。
When working in slave mode, ACKLEN means the duration of CKACK=0

Bit4
ng
ACKLEN 0 when data receiving error happened.
0, 1byte；1, 2bytes。
Bit3 When working in Master mode, Auto re-transmiting mechnaims will be

AUTOSD 0 enabled if AUTOSD=1. When CKACK is low, the UART will resend the
data automatically.
Va
Bit2 When working in slave mode, Auto re-receving mechanism will be

AUTORC 0 enabled if AUTORC=1. When error data is received, CKACK will be set
as low acked to the transmitter to request the data be resend.
Bit1
CHKP 0 0, Even Parity Check；1, Odd Parity Check。
ENABLE=0，Stay in IDLE state always.
bit0 WhenENABLE bit of CFGA =1，P10.0 is used as EUART1data transmitter

ENABLE 0 and receiver；
When ENABLE bit of CFGB =1，P10.1is used as EUART2data transmitter，

P10.2is used as EUART2data recevier。

V98XX Datasheet
In ISO/IEC 7816-3protocol，the resend tries should not be greated than 3 ，For example, if the
transmitting failed twice ， the resend mechanism will be stopped.User could use the software
implementation to fulfill this requirement.
h
ec
ot
ng
Va

V98XX Datasheet
16. Watchdog Timer (WDT)

In the V98XX the embedded 16-bit watchdog timer (WDT) counting pulses of the 32kHz RC clock.
When the program gets stuck somewhere, the timer overflows and reset the system to cause the program
restart from the beginning.
16.1. Clock for WDT

In the V98XX, CLK4, sourced by the 32kHz RC clock, provides clock pulse for the WDT. RC clock cannot
be disabled until the chip is powered off, but CLK4 is enabled or disabled together with CLK1. When CLK4
(together with CLK1) is disabled, which means the system enters Sleep or Deep Sleep state, the WDT
h
stops running. When the system is woken up by IO/RTC wakeup event or power recovery, the WDT
restarts counting from zero.
ec
Table 16-1 Enable/Disable CLK4
SFR 0x80, R/W, Clock Switchover Control Register, SysCtrl SFR
Bit2 When the bit PWRUP is read out as 0, write 0 to the bit MCUFRQ, and then:
ot
SLEEP1 - set SLEEP1 and SLEEP0 to 0b11 or 0b01 to stop CLK1 (together with CLK4) and
0 force the system entering the Sleep state.
Bit1
- set SLEEP1 and SLEEP0 to 0b10 to stop CLK1 (together with CLK4) and force
SLEEP0 the system entering the Deep Sleep state.
ng
16.2. Clearing WDT

When IO/RTC wakeup event, power recovery event, POR/BOR or RSTn pin reset occurs, the WDT is
reset, and its counts are cleared. When the reset signal is released, the WDT starts counting from zero
Va
again.
Users can write a program to clear the WDT counts to prevent the WDT from resetting the system
when its counts overflow: write 0xA5 to the register WDTEN (SFR 0xCE) and then 0x5A to the register
WDTCLR (SFR 0xCF) continuously to clear the WDT counts. Immediately the WDT is cleared, it will restart
counting pulses from zero.
SFR 0xCE, W, WDTEN SFR 0xA5
SFR 0xCF, W, WDTCLR SFR 0x5A
16.3. WDT Overflow Reset

Initially, the WDT starts counting pulses from 0. If the counts are not cleared when the WDT counts to

V98XX Datasheet
(3×214), that is about 1.5s, the WDT overflows, a reset pulse of 8 RC clock periods (8/fRC) width is output,
and the system is reset to default state. After the reset, the WDT starts counting from (-214), and then,
if the WDT is still not cleared, the WDT will overflow again when it counts to (3×214), that is about 2s.
When the WDT overflow reset occurs, the flag bit POR (bit5 of Systate, SFR 0xA1) is set to 1. When
other reset events, not POR/BOR or RSTn pin reset, occurs, this bit will be cleared. In debugging mode,
this reset event is masked.
A WDT overflow event can reset all circuits except the RTC calibration registers, RTC timing registers,
IRAM and XRAM.
WDT counts
3 ×214
h
Feed dog
ec
0 t
-214
1.5s
8/fRC
WDT
ot
overflow reset
pulse
Figure 16-1 WDT Overflow Reset

ng
Va

V98XX Datasheet
17. Real-Time Clock (RTC)

In the V98XX, the RTC has features as follows:
 counting the pulses of the 32.768kHz OSC clock;
 calibrating crystal frequency over temperature variation;

 calibrated pulse output every exact one second;
 timing error less than 5ppm over operating temperature range;

 providing real-time clock and calendar, and adjusting the date for leap year automatically.
In the RTC, the registers for calibration and timing cannot be reset by any reset event; and the other
registers will be reset to their default states when POR/BOR, RSTn pin reset or WDT overflow event
h
occurs.
In Sleep state, the RTC keeps running and can be configured to wake up the system at an
programmable interval of 1 day, 1 hour, 1 minute, 1~64 seconds, 500ms, 250ms, 125ms or 62.5ms.
ec
The wakeup signal will hold 8 OSC clock periods.
32.768kHz
Pulse per PLL OSC Second

second/pulse
ot
proportional to Minute
divided PLL clock
PLL counter Hour
OSC counter
Day
Calibration
Days of week
ng
Month
Write protection Year

Data protection
Pulse per second /

interrupt
To configure
wakeup interval Wakeup signal
Va
Load, configure
Bus
Figure 17-1 Architecture of RTC

V98XX Datasheet
17.1. Reading and Writing of RTC Registers
17.1.1. Writing of RTC
In the V98XX, the registers INTRTC (SFR 0x96), RTC calibration registers and RTC timing registers are
protected from writing.
The MCU must write of these registers following exact steps as:
1. writing 0x96 to the register RTCPEN to enable writing of the register RTCPWD;
2. writing 0x57 to the register RTCPWD to enable writing of INTRTC (SFR 0x96), RTC calibration
registers and RTC timing registers;
h
3. After 5 OSC clock cycles, configuring the registers INTRTC (SFR 0x96), RTC calibration registers and
RTC timing registers;
4. After 5 OSC clock cycles, writing 0x96 to the register RTCPEN to enable writing of the register
ec
RTCPWD;
5. Writing 0x56 to the register RTCPWD to disable writing of the registers INTRTC (SFR 0x96), RTC
calibration registers and RTC timing registers. 5 OSC clock cycles later, the contents of the registers
are activated. A second write operation can be done to these registers only when the last
configuration is completed.
ot
17.1.2. Reading of RTC
To read the timing registers, the MCU must read the register RDRTC (SFR 0xDA) firstly, waits no less
than 5 OSC clock cycles till the contents of the RTC timing registers are latched, and then read the timing
ng
registers for the time information.
But the MCU can read the calibration registers directly.
17.2. Timing
Va
When the chip is powered on, the RTC starts to run, and it keeps on running until the system is powered
off.
If the timing registers are not configured, the RTC runs from a random time; otherwise, the RTC runs
from the preset time.
17.3. RTC Interrupts

In the V98XX, the RTC can trigger two interrupt events if they are enabled: illegal data interrupt and
pulse output interrupt per second.

V98XX Datasheet
17.3.1. RTC Illegal Data Interrupt
When the RTC illegal data interrupt is enabled (EA=1, EIE.2=1 and ExInt4IE.0=1), an illegal data
interrupt will be triggered when:
 The MCU writes of the registers INTRTC (SFR 0x96), RTC calibration registers and RTC timing
registers when they are still being protected from writing;
 The MCU writes the contents in an illegal format into the registers INTRTC (SFR 0x96), RTC calibration
registers and RTC timing registers when the writing operation is enabled;
The contents of the timing registers are in binary-coded decimal (BCD) format, so 0xF is not considered
as an illegal data.
In both circumstances, the RTC timing registers will hold the contents.
h
 Data error caused by the system error occurs during the operation. In this circumstance, the MCU
must configure all RTC timing registers consecutively immediately the writing operation is enabled,
and then disable the writing operation to activate the correction.
ec
17.3.2. Pulse Output Interrupt per Second
When EA=1, EIE.1=1 and ExInt3IE.6=1, the pulse output interrupt per second is enabled, and the RTC
will output pulses of 1 second width to the MCU to trigger interrupts.
ot
17.4. PLL Counter
There is a 24-bit PLL counter in the V98XX. It can work as a PLL clock divider or a counter, which is
ng
determined by the register PLLCNTST (SFR 0xDE).
When the register PLLCNTST (SFR 0xDE) is set to 0x00, the PLL counter works as a divider. In this
mode, the PLL counter counts from 0 and increments by 1 every OSC clock cycle. When it counts to the
pre-set value of the PLL clock divider registers, this counter will be cleared, output pulses at a frequency
proportional to the divided PLL clock frequency from Pin31/Pin30/Pin43, and then the counter will start
recounting. The frequency of the pulse can be calculated as follows:
Va
fMCU
fDIV = Equation 17-1
2 ×(TH + 1)
where,
 fDIV, the frequency of the pulse, Hz;

 fMCU, the MCU clock frequency (Hz), which has a relationship with the OSC clock frequency (f OSC)as
follows:
fMCU = K ×fOSC Equation 17-2
where, K is a coefficient, equal to 100/200/400; when the theoretical fMCU is 13.1072MHz, K is 400.
 TH, the preset value of the PLL divider registers (DIVTHH/DIVTHM/DIVTHL). In the default state, the
value of TH is 0, so the MCU clock frequency is divided by 2. The MCU clock frequency can be divided
by up to 225.
When the register PLLCNTST (SFR 0xDE) is configured to 0x01, the PLL counter works as a counter.

V98XX Datasheet
When the first low-to-high transition of a reference pulse of exact 1 second width input on Pin89 (SDSP)
is detected, which will configure the register to 0x02 automatically, the counter starts counting from zero.
And then, when the second low-to-high transition of the reference pulse input is detected, the register
PLLCNTST (SFR 0xDE) is configured to 0x03 automatically, the PLL counter stops running, and the current
counts is transferred to the PLL clock divider registers to calculate the actual frequency of the pulse.
17.5. Calibrating RTC

In the V98XX, the MCU can use the PLL counter or the internal counter of the RTC to calibrate the RTC.
17.5.1. Calibrating Pulse Frequency of PLL Counter
h
The internal counter of the RTC counts the clock pulse provided by the OSC clock. From the 1 st to 29th
second, the RTC outputs pulses every 32768 counts; in the 30 th second, the RTC outputs a pulse when
ec
the counts are [32768-(C-1)] (C is the value of the calibration register in decimal) to average the width
of pulses in 30 seconds to be 1 second each. So the RTC cannot calibrate timing error in real time by
itself. But when the PLLCNTST is used to output a pulse of exact 1 second width (PPS) every second, the
error of the pulse width can be corrected in real time. Because both RTC and PLLCNTST are pulsed by
the OSC clock, so users can calibrate the RTC timing via correcting the PPS width error.
ot
The relationship of the value of C (in decimal) and actual OSC clock frequency (fOSC) is as follows:
C - 1 = 30 × (32768 - fOSC ) Equation 17-3
According to Equation 17-1 and Equation 17-2, to calibrate the pulse frequency of the PLL counter (f DIV)
to be 1Hz, the nominal TH and actual TH’ has a relationship as follows:
ng
K
TH - TH'= ΔTH = × (32768 - fOSC ) = 200 × (32768 - fOSC ) Equation 17-4
2
where, TH is the value for nominal fOSC, namely 32768Hz; TH’ is the value for actual fOSC.
According to Equation 17-3 and Equation 17-4, a relationship between ΔTH and C is obtained:
ΔTH 200
Equation 17-5
Va
=
C -1 30
According to Equation 17-5, users can calibrate the RTC timing via correcting the PPS width error.
17.5.2. Calibrating Divided Pulse Frequency of PLL

Counter
When Pin89 is used to input a reference pulse of exact 1 second width, the PLL counter is used to
capture and measure the width of this input signal, which can be used to calibrate the RTC. The calibration
steps are as follows:
1. The MCU writes 0x01 to the register PLLCNTST (SFR 0xDE) to clear the PLL counter, and the PLL
counter works as a counter;

V98XX Datasheet
2. When the first high-to-low transition of the reference pulse of exact 1 second width is detected, which
will configure the register to 0x02 automatically, the counter starts counting from zero.
3. When the second low-to-high transition of the reference pulse is detected, the register PLLCNTST
(SFR 0xDE) is configured to 0x03 automatically, the PLL counter stops running, and the current
counts are transferred to the PLL clock divider registers as the value of TH to generate pulses of
exact 1 second width to calibrate the crystal frequency using the following equation:
2
fOSC = ×(TH + 1) Equation 17-6
K
When the theoretical frequency of the MCU (fMCU) is 13.1072MHz, the relationship of C, the value to be
written to the calibration register, and TH in the preceding equation is as follows:
30
C -1 = ×(TH + 1) - 32768 ×30 Equation 17-7
200
h
17.5.3. Crystal Frequency-Temperature Curve
ec
The crystal frequency is affected by the ambient temperature. In the V98XX there is a temperature
measurement circuit. Users can measure the crystal frequency in different ambient temperatures and
calculate the values to be written to the calibration register (C) according to the following steps to
calibrate the crystal frequency to be exact 32768Hz at different temperatures, and then tabulate them
according to the relationship for table look-at:
ot
4. Set the reference crystal frequencies in different ambient temperature, such as 32768Hz;
5. Write 0x01 to the calibration registers and measure the actual crystal frequency (f OSC) using a
frequency meter via Pin96 in different ambient temperature, and calculate the value of C’ (C’=C-1)
using the following equation:
f - 32768 1 1
ng
C' = OSC ×1000000 /( × ×1000000 ) = 30 ×(fOSC - 32768) Equation 17-8

32768 32768 30
1 1
Where, × ×1000000 , equal to 1.02ppm, represents the calibration accuracy of the RTC of
32768 30
fOSC - 32768
average one second in the 30 seconds; and ×1000000 represents the quantity of the crystal
32768
frequency to be calibrated in unit of ppm.

Va
calculate C according to
Crystal Frequency- write C to
measure
Temperature curve calibration
temperature
register
Figure 17-2 Schematics of Calibrating Crystal Frequency over Temperature Variation

V98XX Datasheet
32,769.00
32,768.50
Crystal Frequency (Hz)

32,768.00
32,767.50
32,767.00
32,766.50
32,766.00
32,765.50
32,765.00
32,764.50
Temperature (°C)
h
Figure 17-3 Crystal Frequency-Temperature Curve
17.6. Registers
ec
In the RTC, the registers for calibration and timing cannot be reset by any reset event; and the other
registers will be reset when POR/BOR, RSTn pin reset or WDT overflow event occurs.
Table 17-1 RTC Password Enable Register (RTCPEN, SFR 0x90)

ot
SFR 0x90, RTC Password Enable Register, RTCPEN
Only 0x96 is the valid value.
Only when this register is configured to 0x96 can the register RTCPWD
ng
bit[7:0] 0 W
(SFR 0x97) be configured validly. The write operation of both registers
must be consecutive without interruption.
Table 17-2 RTC Password Register (RTCPWD, SFR 0x97)
SFR 0x97, RTC Password Register, RTCPWD

Va
Bit[7:1] are writable only, but bit0 is writable and readable.

bit[7:1] 0 W
Only 0x57 and 0x56 are valid for this register.
Write 0x57 to this register to enable write operation on the registers

INTRTC (SFR 0x96), RTC calibration registers and RTC timing registers.
bit0 WE 0 R/W
Write 0x56 to this register to disable the write operation.
Table 17-3 RTC Wakeup Interval Register (INTRTC, SFR 0x96)
SFR 0x96, RTC Wakeup Interval Register, INTRTC
bit[7:3] 0 R/W

V98XX Datasheet
SFR 0x96, RTC Wakeup Interval Register, INTRTC
000: 1 second; 001: 1 minute; 010: 1 hour; 011: 1 day; 100:

bit[2:0] RTC<2:0> 0 R/W
500ms; 101: 250ms; 110: 125ms; 111: 62.5ms.
Configure this register for the interval at which the RTC will wake up the system from Sleep state. The
wakeup signal holds 8 OSC clock periods.
Table 17-4 RTC Seconds Wake-up Interval Configuration Register (SECINT, SFR 0xDF)
h
Bit7 R/W 0 Reserved
It is mandatory to set register INTRTC (SFR 0x96) to 0x07, and then set this
ec
Bit6 R/W 0
bit to 1 to enable writing of bit[5:0] of this register.
To set interval in unit of second for RTC to wake up the system from Sleep.
The actual wakeup interval is equal to (bit[5:0]+1) seconds, of which
Bit[5:0] R/W 0 bit[5:0] can be set to 1~63 (decimal).
Setting these bits to 0 (decimal) forces the interval to be 62.5ms.

ot
Table 17-5 Flag Bit of RTC Wakeup Event

ng
When this bit is read out as 1, but bit CFWK (bit3 of IOWKDET, SFR 0xAF) is cleared,
Bit2 it indicates the system was woken up from Sleep by RTC wakeup event.
0
RTC/CF If both this bit and bit CFWK are set to 1s, it indicates the system was woken up
from Sleep by CF pulse wakeup event.
Table 17-6 RTC Calibration Registers (RTCCH/RTCCL, SFR 0x94/0x95)

Va
Register Bit R/W Description
SFR bit[7:6] R/W Reserved.

0x94 bit[5:0] To set a value (C) to calibrate the crystal frequency. The register is in the
R/W format of 2’-complement.
RTCCH C<13:8>
The internal counter of the RTC counts the clock pulse provided by the
OSC clock. From the 1st to 29th second, the RTC outputs a pulse every
SFR
bit[7:0] 32768 counts; in the 30th second, the RTC outputs a pulse when the counts
0x95 R/W is up to [32768-(C-1)) to average each pulse width in the 30 seconds to
C<7:0>
RTCCL be 1s. The average calibration resolution is 1.02ppm, and the adjustment
range is over ±8332.3ppm (±12 min/day).
Table 17-7 RTC Data Reading Enable Register (RDRTC, SFR 0xDA)

V98XX Datasheet
SFR 0xDA, RTC Data Reading Enable Register, RDRTC
The MCU must read this register to enable read operation on the RTC timing
bit[7:0] 0 R
registers. This register is read out as 0x00.
Table 17-8 PLL Clock Divider Registers (DIVTHH/DIVTHM/DIVTHL, SFR 0xDB/0xDC/0xDD)
Register Bit Default R/W Description
SFR 0xDB, DIVTHH bit[7:0] DIV<23:16> 0 R/W High byte of the PLL clock divider.
SFR 0xDC, DIVTHM bit[7:0] DIV<15:8> 0 R/W Middle byte of the PLL clock divider.
h
SFR 0xDD, DIVTHL bit[7:0] DIV<7:0> 0 R/W Low byte of the PLL clock divider.
Table 17-9 PLL Counter State Register (PLLCNTST, SFR 0xDE)
ec
SFR 0xDE, PLL Counter State Register, PLLCNTST, R/W
bit[7:2] 0 R/W When this register is cleared to 0x00, the PLL counter works as a divider.
When the PLL counter increments from 0 to the value of the PLL clock
divider registers, this counter is cleared, outputs a pulse at a frequency
ot
proportional to the divided PLL clock frequency, and then starts
recounting.
When this register is set to 0x01, the PLL counter works as a counter.
bit[1:0] When the first low-to-high transition of the reference pulse of exact 1
0 R/W second width input on Pin89 (SDSP) is detected, which will set this
ng
STT<1:0> register to 0x02 automatically, the counter starts counting from zero. And
then, when the second low-to-high transition of the reference pulse input
is detected, the register is configured to 0x03 automatically, the PLL
counter stops running, and the current counts is transferred to the PLL
clock divider registers to calculate the actual frequency of the pulse per
second.
Va
The time and calendar information is obtained by reading the appropriate register bytes. The contents
of the timing registers, except the register for day of week configuration, are in binary-coded decimal
(BCD) format, of which bit7~bit4 represents the tens digit of the time and calendar, and bit3~bit0
represents the units digit of the time and calendar; for example, 0b1000011 in the register RTCSC
represents 43 seconds. The RTC can provide second, hour, day, week, month and year information. As
such, both RTCSC (seconds) and RTCMiC (minutes) range 0~59, RTCHC (hour) ranges 00~24, RTCDC
(day) ranges 1~31, RTCMoC (month) ranges 1~12 and RTCYC (year) ranges 0~99.
Table 17-10 RTC Timing Registers
Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR RTCSC, to set the second

- S40 S20 S10 S8 S4 S2 S1
0x9A information, 0~59.

V98XX Datasheet
Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR RTCMiC, to set the minute

- M40 M20 M10 M8 M4 M2 M1
0x9B information, 0~59.
SFR RTCHC, to set the hour

- - H20 H10 H8 H4 H2 H1
0x9C information, 0~23.
SFR RTCDC, to set the day

- - D20 D10 D8 D4 D2 D1
0x9D information, 1~31.
SFR RTCWC, to set the day of

- - - - - W4 W2 W1
0x9E week information.
SFR RTCMoC, to set the month
h
- - - Mo10 Mo8 Mo4 Mo2 Mo1
0x9F information, 1~12.
SFR RTCYC, to set the year

Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1
0x93 information, 00~99.
ec
Default X X X X X X X X
Users must set the day of week information for one date; for example, set the date 1st Jan. 2010 to
be Friday, and the RTC will determine the date 2nd, Jan., 2010 to be Saturday automatically. 0b000:
Sunday; 0b001: Monday; 0b010: Tuesday; 0b011: Wednesday; 0b100: Thursday; 0b101: Friday;
ot
0b110: Saturday; 0b111: Invalid data.
For the year information, only the tens and units digits of the year need to be configured in the register
RTCYC; for example, 0b00010000 represents the year 2010.
Users should set the information of year, month, day, hour, minute, second, and week according to
certain sequence at one time. It will fail if set up separately.
ng
Va

V98XX Datasheet
18. Registers
18.1. Analog Control Registers

In the V98XX, analog control registers are located at addresses 0x2858~0x2868. The registers are
readable and writable. When POR/BOR, RSTn pin reset or WDT overflow reset occurs, the analog control
registers will be reset to their default states. In this section, the default values are in decimal form unless
otherwise noted.
The register located at address 0x285F must be configured to its default values for proper operation.
Users can read of bytes located at addresses 0x300C~0x3059 to obtain the recommended
h
configuration of the analog registers, and write them to the analog registers.
Table 18-1 ADC Control Register 0 (CtrlADC0, 0x2858)
ec
0x2858, R/W, ADC Control Register 0, CtrlADC0
Bit7 Reserved 0 This bit must hold its default value for proper operation.
To set analog PGA gain for voltage input to Voltage Channel (U)
ot
ADC. This bit must hold its default value for proper operation（×1
Bit6 ADCGU 0 倍）.
0: ×1; 1: ×2.
To set analog PGA gain for current input to Current Channel B (IB)
ng
ADC.
Bit[5:3] ADCGB<2:0> 0 000: ×1; 001: ×4; 010: ×8; 011: ×16; 100/101/110/111: ×32.
To match the output signal from the sensor to the measurement

scale of the ADC, the default value should not be used.
To set analog PGA gain for current input to Current Channel A (IA)
Va
ADC.
Bit[2:0] ADCGA<2:0> 0 000: ×1; 001: ×4; 010: ×8; 011: ×16; 100/101/110/111: ×32.
To match the output signal from the sensor to the measurement

scale of the ADC, the default value should not be used.
To adjust the 2nd order bias current of the ADCs. 00: ×1

bit[3:2] ADIT2<1:0> 0
(recommended); 01: ×1.33; 10: ×2; 11: ×2.67.

V98XX Datasheet
To adjust the 1st order bias current of the ADCs. 00: ×1

bit[1:0] ADIT1<1:0> 0
(recommended); 01: ×1.33; 10: ×2; 11: ×2.67.
Table 18-3 ADC Control Register 2 (CtrlADC2, 0x285A)
0x285A, R/W, ADC Control Register 2, CtrlADC2
h
To adjust the bias current of the amplifier of voltage channel. It is
bit4 DITAMP 0 recommended to hold its default value for proper operation.
0: ×1; 1: ×0.67.
ec
To reset the integrator in the modulator in the ADC of Channel M.
bit3 ADRSTM 0 When some errors occur to the data output from the ADC, set this bit
to 1 to reset the integrator.
To reset the integrator in the modulator in the ADC of Channel U.

ot
bit2 ADRSTU 0 When some errors occur to the data output from the ADC, set this bit
To reset the integrator in the modulator in the ADC of Channel IB.

bit1 ADRSTB 0 When some errors occur to the data output from the ADC, set this bit
ng
To reset the integrator in the modulator in the ADC of Channel IA.

bit0 ADRSTA 0 When some errors occur to the data output from the ADC, set this bit
Table 18-4 ADC Control Register 3 (CtrlADC3, 0x285B)

Va
0x285B, R/W, ADC Control Register 3, CtrlADC3
Set this bit to 1 to increment the bias current in the comparator

bit4 ADQIT 0
by 50%. By default this function is disabled.
Set this bit to 1 to short the voltage channel ADC 2internally. By

bit3 SHORTV2 0
bit2 Reserved 0 This bit must hold its default value for proper operation.
Set this bit to 1 to short the current channel ADCs2internally. By

bit1 SHORTI2 0

V98XX Datasheet
0x285B, R/W, ADC Control Register 3, CtrlADC3
Table 18-5 Battery Discharge Control Register (CtrlBAT, 0x285C)
0x285C, R/W, Battery Discharge Control Register, CtrlBAT
When the LCD driver works in 1/8 duty mode, set this bit to select
h
the bias ratio.
bit3 LCDBMOD 0 0: 1/3 Bias; 1: 1/4 Bias.
ec
When the LCD driver works in 1/4 or 1/6 duty mode, 1/3 Bias ratio
is used whatever this bit is set.
To adjust the bias current of the amplifier of the voltage channel

bit[2:1] IITU<1:0> 0 ADC.
00: 0%; 01: -33%; 11:+33%; 10: 100%.

ot
bit0 BATDISC 0 To enable discharging the battery. 1: enable; 0: disable.
Table 18-6 ADC Control Register 4 (CtrlADC4, 0x285D)
0x285D, R/W, ADC Control Register 4, CtrlADC4

ng
Set this bit to 1 to increase operating current to the Channel IB ADC

bit5 IAMPITB 0
by 50%.
Set this bit to 1 to increase operating current to the Channel IA ADC

bit4 IAMPITA 0
Va
by 50%.
Table 18-7 LCD Driver Voltage Control Register (CtrlLCDV, 0x285E)
0x285E, R/W, LCD Driver Voltage Control Register, CtrlLCDV
Bit7 DCENN
bit2 VLCD 0 To adjust the LCD waveform voltage. 0: 3.3V; 1: 3.0V.

V98XX Datasheet
Table 18-8 Crystal Control Register 1 (CtrlCry1, 0x2860)
The fixed capacitance in the crystal oscillator circuit is 12.5pF. Set

Bit4 CSEL 0
this bit to 1 to decrease the capacitance by 2.35pF.
Bit3 Reserved 0 These bits must hold their default values for proper operation.
To adjust the resistance of the resistors in the internal crystal

oscillator circuit. When the RTC is used, these bits must be set to
0b011, and the oscillation monitoring circuit must be enabled.
h
Set bit XTRSEL<2> to 1 to increment the resistance to P end by
400kΩ.
Bit[2:0] XTRSEL<2:0> 0
ec
XTRSEL<1:0> to adjust the resistance to N end:
00/01: hold the resistance to N end.
10: increment by 128kΩ.
11: increment by 64kΩ.

ot
Table 18-9 Crystal Control Register 2 (CtrlCry2, 0x2861)

ng
Set this bit to 1 to enable current leakage detection on BandGap

Bit7 REFLKEN 0 circuit. When this bit is set to 1, an interrupt will be triggered
when reference voltage is lowered by more than 3%.
This bit must hold its default value for proper operation. By
Bit6 Reserved 0
bit5 XRESETEN 0 Set this bit to 1 to enable the oscillation monitor.

Va
To select the bias current input to the comparator CB. 0: 20nA;

Bit4 CMPIT 0
1: 200nA.
To select the analog input to the comparator CB.

Table 18-10 BandGap Control Register (CtrlBGP, 0x2862)

V98XX Datasheet
0x2862, R/W, BandGap Control Register, CtrlBGP
To adjust the global bias current of the ADC.
00: -33%; 01: 1; 10: -75%; 11: -66%.

bit[7:6] CURRIT<1:0> 0
It is recommended to set these bits to 0b00 for full operation, and
to 0b11 for metering energy at a lower frequency.
To roughly adjust the temperature coefficient of the BandGap

Bit[5:4] RESTL<1:0> 0 circuit.
00: 0ppm; 01: -70ppm; 10: +140ppm; 11: +70ppm.
h
To finely adjust the temperature coefficient of the BandGap circuit.
The recommended configuration for 0b001, but the user should

correct according to actual measured temperature coefficient of
ec
Bit[3:1] REST<2:0> 0
the whole table.
000: 0ppm; 001: +10ppm; 010: +20ppm; 011: +30ppm; 100: -

40ppm; 101: -30ppm; 110: -20ppm; 111: -10ppm.
By default the chopper in the BandGap circuit is enabled to remove

ot
the DC offset.
bit0 BGPCHOPN 0
Set this bit to ‘0’ to disable this function In order to improve the
temperature performance.

ng
Bit[7] Reserved 0 These bits must hold value1for proper operation.
Bit[6] Reserved 0 These bits must hold their default values for proper operation.
Va
To set analog PGA gain for signal input to various Measurement

Bit5 GDE4 0 Channel (M) ADC.
0: ×1; 1: ×1/4.
To set bit1 and the division coefficient1/4 of the resistor divider

bit4 RESDIV 0 network in M Channel. The circuit is turned off by default
Bit3 Reserved 0 This bit must hold its default value for proper operation.

V98XX Datasheet
To select the analog input to be measured in Channel M.
000: ground;
001: temperature;
010: battery voltage or other external DC voltage via pin BAT.
Bit[2:0] MEAS<2:0> 0 011: reserved;
100: external DC voltage via pin UM;
h
101: external DC voltage via pin M0;
110: external DC voltage via pin M1;
111: external DC voltage via pin M2.
ec
Note: When the pins M0, M1 and M2 are used for analog input for Channel M, bit[7:5] of the register
SegCtrl4 (0x2C23) must be cleared to disable the SEG output on the pins.

ot
bit5 CMPPDNB 0 To enable the comparator CB. 0: disable; 1: enable.

ng
bit3 ADCMPDN 0 To enable Channel M ADC. 0: disable; 1: enable.
bit2 ADCUPDN 0 To enable Channel U ADC. 0: disable. 1: enable.
bit1 ADCBPDN 0 To enable Channel IB ADC. 0: disable; 1: enable.

Va
bit0 ADCAPDN 0 To enable Channel IA ADC. 0: disable; 1: enable.
Table 18-13 Channel M Control Register (CtrlM, 0x2865)
0x2865, R/W, Channel M Control Register, CtrlM
the DC offset of the input signal into the M Channel

bit0 MADCHOPN 0
When M Channel is used to measure temperature, it is recommended
to set this bit to 1 to disable this function to improve the
measurement accuracy.

V98XX Datasheet
Table 18-14 LDO Control Register (CtrlLDO, 0x2866)
0x2866, R/W, LDO Control Register, CtrlLDO
Set this bit to 1 to disable the internal power detection circuit.

When the chip is 3.3V powered, users must set this bit to 1 to
Bit7 PDDET 0 disable the power detection circuit, to prevent current leakage
of the battery when a battery is connected to the device.
When the chip is 5V powered, this bit must hold its default
value.
h
Bit6 LDO3IT 0 Set this bit to 1 to increase bias current of LDO33 by 100%.
To adjust output voltage of LDO33.
ec
Bit[5:3] LDO3SEL 0 000: 3.3V; 001: 3.2V; 010/100/101: 3.5V; 011: 3.4V; 110:
3.1V; 111: 3.0V.
To adjust output voltage of digital power circuit.

Bit[2:0] LDOV2SEL<2:0> 0 000: +0V; 001: -0.1V; 010: +0.2V; 011: +0.1V; 100: -0.4V;
101: -0.5V; 110: -0.2V; 111: -0.3V.
ot
Table 18-15 Clock Control Register (CtrlCLK, 0x2867)

ng
To enable the PLL circuit. 0: disable; 1: enable.

bit7 PLLPDN 0
To enable the BandGap circuit. 0: disable; 1: enable.

bit6 BGPPDN 0
Va

bit[5:4] ADCLKSEL<1:0> 0 ADCs (ADCCLK). Base: 204.8kHz.
00: ×1; 01: ×2; 10: ×4.
To configure the clock frequency for the energy metering

bit[3:2] MEACLKSEL<1:0> 0 architecture (MTCLK). Base: 819.2kHz.
00: ×1; 01: ×2; 10: ×4.
To adjust the clock frequency for the MCU (MCUCLK). Base:

bit[1:0] MCUCLKSEL<1:0> 0 819.2kHz.
00: ×1; 01: ×2; 10: ×4; 11: ×8.
Table 18-16 PLL Control Register (CtrlPLL, 0x2868)

V98XX Datasheet
0x2868, R/W, PLL Control Register, CtrlPLL
When the bit MCU13M is set to 1, set this bit to 1 to double MCUCLK
bit7 MCU26M 0
frequency further.
bit6 MCU13M 0 Set this bit to 1 to double MCUCLK frequency.
bit5 PLLSEL 0 To apply the chip to 50Hz or 60Hz power grid. 0: 50Hz; 1: 60Hz.
Table 18-17 Analog Circuits State Register (ANState, 0x286B)
h
0x286B, R, Analog Circuits State Register, ANState
ec
To indicate the state of the OSC clock.
0: the crystal is working.

bit7 OSC 0
1: the crystal stops running, and all the circuits, including PLL circuit,
sourced by the OSC clock now is being sourced by the internal RC clock.
Bit6 Reserved -
ot
To indicate the output of the comparator CB.
bit5 COMPB 0 1: the positive input is higher than the negative input;
0: the negative input is higher than the positive input.

ng
bit[4:2] Reserved 5 It is read out as 0x5.
bit[1:0] Reserved -
18.2. Metering Control Registers

Va
When POR/BOR, RSTn pin reset or WDT overflow reset occurs, all metering control registers are reset
to their default states.
All the default values in this section are in decimal form if not specifically noted.
Table 18-18 PM Control Register 1 (PMCtrl1, 0x2878)
0x2878, R/W, PM Control Register 1, PMCtrl1
Only for test.
To disable the power/RMS calculation circuits to access to the energy metering

bit7 PVA 0
data registers.
0: enable; 1: disable.

V98XX Datasheet
To enable phase compensation. 0: disable; 1: enable.

bit6 PHCEN 0 When phase compensation is enabled, the phase angle errors between U and
IA, and U and IB, are corrected respectively.
To exchange the current channels.
0: current IA is sent to Current I1 Channel for signal processing, and current

bit5 SELI 0 IB is sent to Current I2 Channel for signal processing;
1: current IA is sent to Current I2 Channel for signal processing, and current
h
IB is sent to Current I1 Channel for signal processing.
To enable power and RMS calculation, and digital signal processing in M

bit4 PREN 0
Channel. 0: disable; 1: enable.
ec
To enable digital signal input to M channel.
bit3 ONM 0
0: disable; 0 is input to M channel. 1: enable.
To enable digital signal input to the I2 channel. 0: disable; 0s are input to I2

Bit2 ONI2 0
channel. 1: enable.
ot
To enable digital signal input to the I1 channel. 0: disable; 0s are input to I1
Bit1 ONI1 0
channel. 1: enable.
To enable digital signal input to the U channel. 0: disable; 0s are input to U

Bit0 ONU 0
channel. 1: enable.
ng
Table 18-19 PM Control Register 2 (PMCtrl2, 0x2879)
To set sign of the digital PGA gain for I1 signal. 0: positive; 1:

bit7 PGACS 0
negative.
Va
To set the digital PGA gain for I1 signal. Gain=2PGACx. PGACx is

bit[6:4] PGAC2~PGAC0 0
over the range of 0~5.
bit3 PGAUS 0 To set sign of the digital PGA for U signal. 0: positive; 1: negative.
To set the digital PGA gain for U signal. Gain=2PGAUx. PGAUx is

bit[2:0] PGAU2~PGAU0 0 When bit LPFEN (bit5 of PMCtrl3, 0x287A) is set to 1, the digital
PGA gain for U signal is lowered to 1/4 of its configuration. When
bit LPFEN is cleared, the digital PGA gain for U signal is what it is
configured.
Table 18-20 PM Control Register 3 (PMCtrl3, 0x287A)

V98XX Datasheet
0x287A, R/W, PM Control Register 3, PMCtrl3
Set this bit to 1 to enable zero-crossing interrupt to CPU. By

bit7 X0EN 0
default this interrupt is masked.
To enable the band-pass filter in the voltage/current RMS

calculation circuits. 0: disable; 1: enable.
bit6 BPFEN 0 This filter can improve the RMS calculation accuracy, but it will
lead to harmonics loss. When a low signal is input, this filter will
introduce greater truncation noise and prolong the period for the
system to be settled.
h
When this bit is set to 1, the digital PGA gain for U signal is
bit5 LPFEN 0 lowered to 1/4 of its configuration. When this bit is cleared, the
digital PGA gain for U signal is what it is configured.
ec
To select the function of E2 path.
0: for reactive power calculation and energy metering based on

current I1. If positive current I1 is input to the path, the reactive
power is negative, and it is accumulated to the negative energy
bit4 DBLEN 0 accumulators; if negative current I1 is input to the path, the
ot
reactive power is positive, and it is accumulated to the positive
energy accumulators.
1: for active power calculation and energy metering based on

current I2.
ng
To set sign of the digital PGA gain for I2 signal. 0: positive; 1:

bit3 PGANS 0
negative.
To set the digital PGA gain for I2 signal. Gain=2PGANx. PGANx is

bit[2:0] PGAN2~PGAN0 0
Table 18-21 Phase Compensation Control Register 1 (PHCCtrl1, 0x287B)

Va
0x287B, R/W, Phase Compensation Control Register 1, PHCCtrl1
To select the signal to be delayed. 1: to delay voltage; 0: to delay

bit7 PHCA7 0
current I1.
bit6 PHCA6 0 Not used.
Together with bit IAPHC (bit[1:0] of CRPST, 0x287F) as the right 2

bits, these 8 bits are to set the time to be delayed. When the
sampling frequency of phase compensation circuit (fsmpl) is
Bit[5:0] PHCA<5:0> 0
3.2768MHz, the resolution of the phase compensation is
0.0055°/lsb, and 1.4° in total of the phase angle error can be
calibrated.

V98XX Datasheet
Table 18-22 Phase Compensation Control Register 2 (PHCCtrl2, 0x287C)
0x287C, R/W, Phase Compensation Control Register 2, PHCCtrl2
To select the signal to be delayed. 1: to delay voltage; 0: to delay

bit7 PHCB7 0
current I2.
bit6 PHCB6 0 Not used.
Together with bit IBPHC (bit[3:2] of CRPST, 0x287F) as the right 2

bits, these 8 bits are to set the time to be delayed. When the
sampling frequency of phase compensation circuit (fsmpl) is
Bit[5:0] PHCB<5:0> 0
h
calibrated.
Table 18-23 PM Control Register 4 (PMCtrl4, 0x287D)
ec
0x287D, R/W, PM Control Register 4, PMCtrl4
bit7 CRPENR 0 To enable no-load detection of E2 path. 0: disable; 1: enable.

ot
bit6 CRPEN 0 To enable no-load detection of E1 path. 0: disable; 1: enable.
bit5 CFENR 0 To enable CF pulse output of E2 path. 0: disable; 1: enable.
bit4 CFEN 0 To enable CF pulse output of E1 path. 0: disable; 1: enable.
To enable energy accumulation and energy-to-pulse conversion. 0:

bit3 EGYEN 0
ng
disable; 1: enable.
To select the pins for CF pulse output.
bit2 CFXCG 0 0: CF1 pin for E1 path, CF2 pin for E2 path;
1: CF2 pin for E1 path, CF1 pin for E2 path.

Va
To select the source for positive active energy accumulation in E1

path.
bit[1:0] PSEL1/PSEL0 0 00/11: active power calculated based on current I1; 01: I1 current
RMS;
10: a constant preset in the register DATACP (0x10FC).
Table 18-24 CF Pulse Output Control Register (CFCtrl, 0x287E)

V98XX Datasheet
0x287E, R/W, CF Pulse Output Control Register, CFCtrl
To adjust the energy pulse generation rate in E2 path. 00: ×1;

01: ×4; 10: ×8; 11: ×16.
bit[7:6] CFQR1/CFQR0 0
When low current signal is applied, configure these bits to
accelerate meter calibration.
To adjust the energy pulse generation rate in E1 path. 00: ×1;

01: ×4; 10: ×8; 11: ×16.
bit[5:4] CFQ1/CFQ0 0
When low current signal is applied, configure these bits to
accelerate meter calibration.
h
01: positive active or reactive energy in E2 path; 10: negative
ec
bit[3:2] CFSELR1/CFSELR0 0 active or reactive energy in E2 path;
00/11: the sum of the absolute values of the positive and

negative active or reactive energy in E2 path.

ot
01: positive active energy in E1 path; 10: negative active
bit[1:0] CFSEL1/CFSEL0 0 energy in E1 path;
00/11: the sum of the absolute values of the positive and

negative active energy in E1 path.
ng
Table 18-25 No-Load Detection Indication Register (CRPST, 0x287F)
0x287F, No-Load Detection Indication Register, CRPST
Bit7 CRPST R 0 To indicate the state of E1 path. 0: metering energy; 1: creeping.
Bit6 CRPSTR R 0 To indicate the state of E2 path. 0: metering energy; 1: creeping.

Va
To adjust the CF pulse width.

Bit[5:4] CFWD 0
00: 80ms; 01: 40ms; 10: 20ms; 11: 10ms.
Together with bits PHCB<5:0> (bit[5:0] of PHCCtrl2, 0x287C) as

the left 6 bits, these 8 bits are to set the time to be delayed. When
the sampling frequency of phase compensation circuit (fsmpl) is
Bit[3:2] IBPHC R/W 0
calibrated.

V98XX Datasheet
0x287F, No-Load Detection Indication Register, CRPST
Together with bits PHCA<5:0> (bit[5:0] of PHCCtrl1, 0x287B) as

the left 6 bits, these 8 bits are to set the time to be delayed. When
the sampling frequency of phase compensation circuit (fsmpl) is
Bit[1:0] IAPHC R/W 0
calibrated.
Table 18-26 Current Detection Control Register (IDET, 0x2886)
0x2886, R/W, Current Detection Control Register, IDET
h
ec
Set this bit to 1 to disable the sampling circuits and power/RMS
calculation circuits. In this case, the energy accumulation circuit
keeps on working. So, in an application to accumulate a constant
Bit7 GT R/W 0
for energy accumulation, it is recommended to set this bit to 1 to
lower power consumption further. But please note the threshold for
energy-to-pulse conversion must be set before setting this bit to 1.
ot
When current signal is detected, this bit is set to 1 and holds until
Bit6 CST R 0
bit CLR is set to 1 or DETON is cleared.
After a cycle of current detection, set this bit to 1 and then clear it
Bit5 CLR R/W 0
to clear bit CST.
ng
Bit4 DETON R/W 0 1: enable current detection; 0: disable current detection.
To set the number of current samples for current detection.
If continuous ([IDLEN]+1) samples of the AC component of

instantaneous I1 current are higher than the threshold for current
Va
Bit[3:0] IDLEN R/W 0 detection (IDETTH, 0x1002), it indicates a current signal is caught.
[IDLEN] is over the range of 0~15. See “Current Detection” for the
relationship between IDLEN configuration and the period for current
detection.
18.3. Metering Data Registers

When POR/BOR, RSTn pin reset or WDT overflow reset occurs, all metering data registers are reset to
All metering data registers are readable and writable (R/W). But users must not write of these registers
to avoid unexpected results.

V98XX Datasheet
All the default values in this section are in decimal form if not specifically noted. All the time for
updating and settling listed in the tables is appropriate for 50Hz power grid and fMTCLK=3.2768MHz. When
the frequency for metering architecture (fMTCLK) is divided by K, the time for updating and settling must
be K times of that for 3.2768MHz. In 60Hz power grid, the time for updating and settling is 1.2 times of
that for 50Hz power grid.
Table 18-27 Signal Waveform Registers (R/W)
Update Settle
Address Register R/W Default Format
in in
32-bit 2’
0x1005 DATAOIU Raw waveform of voltage. R/W 0 0.3ms 10ms
complement
h
32-bit 2’
0x100A DATAOII1 Raw waveform of Current I1. R/W 0 0.3ms 10ms
complement
32-bit 2’
0x100F DATAOII2 Raw waveform of Current I2. R/W 0 0.3ms 10ms
ec
complement
DC component of 32-bit 2’
0x103A DATAIDU R/W 0 20ms 70ms
instantaneous voltage. complement
0x1041 DATAIDI1 R/W 0 20ms 70ms
instantaneous Current I1. complement
ot
0x1048 DATAIDI2 R/W 0 20ms 70ms
AC component of 32-bit 2’
0x1051 DATAIAU R/W 0 0.3ms 70ms
instantaneous voltage. complement
ng
0x1052 DATAIAI1 R/W 0 0.3ms 70ms
0x1053 DATAIAI2 R/W 0 0.3ms 70ms
Table 18-28 Power and RMS Registers (R/W)

Va
Update
Address Register R/W Default Format Settle in
in
Instantaneous active 32-bit 2’

0x10D1 DATAIP R/W 0 80ms 250ms
power in E1 path. complement
Instantaneous
32-bit 2’
0x10D2 DATAIQ active/reactive power in R/W 0 80ms 250ms
complement
E2 path.
Instantaneous voltage 32-bit 2’

0x10D3 RMSIU R/W 0 10ms 100ms
RMS. complement
Instantaneous current I1 32-bit 2’

0x10D4 RMSII1 R/W 0 10ms 100ms
RMS. complement

V98XX Datasheet
Update
Address Register R/W Default Format Settle in
in
Instantaneous current I2 32-bit 2’

0x10D5 RMSII2 R/W 0 10ms 100ms
RMS. complement
Average active power in 32-bit 2’

0x10D6 DATAP R/W 0 1.28s 3s
E1 path. complement
Average active/reactive 32-bit 2’

0x10D7 DATAQ R/W 0 1.28s 3s
power in E2 path. complement
32-bit 2’
0x10D8 RMSU Average voltage RMS. R/W 0 1.28s 3s
complement
h
32-bit 2’
0x10D9 RMSI1 Average current I1 RMS. R/W 0 1.28s 3s
complement
32-bit 2’
ec
0x10DA RMSI2 Average current I2 RMS. R/W 0 1.28s 3s
complement
Average apparent power

calculated based on 32-bit 2’
0x10DB DATAAP1 R/W 0 1.28s 3s
average current I1 and complement
voltage RMS.
ot
Average apparent power
calculated based on 32-bit 2’
0x10DC DATAAP2 R/W 0 1.28s 3s
average current I2 and complement
voltage RMS.
ng
Table 18-29 Energy Accumulators and Energy Pulse Counters (R/W)
32-bit,
0x10F0 PPCNT Positive active energy accumulator in E1 path. R/W 0
unsigned
Negative active energy accumulator in E1 32-bit,

Va
0x10F1 NPCNT R/W 0

path. unsigned
32-bit,
0x10F2 PPCFCNT Positive active energy pulse counter in E1 path. R/W 0
unsigned
Negative active energy pulse counter in E1 32-bit,

0x10F3 NPCFCNT R/W 0
path. unsigned
Positive active/reactive energy accumulator in 32-bit,

0x10F6 PQCNT R/W 0
E2 path. unsigned
Negative active/reactive energy accumulator 32-bit,

0x10F7 NQCNT R/W 0
in E2 path. unsigned
Positive active/reactive energy pulse counter 32-bit,

0x10F8 PQCFCNT R/W 0

V98XX Datasheet
Negative active/reactive energy pulse counter 32-bit,

0x10F9 NQCFCNT R/W 0
The energy accumulators are of actual 42-bit length. But only the higher 32 bits are readable; and
only the higher 32 bits are valid for write operation and the 10 least significant bits are padded with
0s in write operation.
When MTCLK frequency is 3.2768MHz, 1.6384MHz or 819.2kHz, the energy accumulation frequency is
12800Hz; when MTCLK frequency is 32768Hz, the energy accumulation frequency is 2979Hz.
When CF pulse output is enabled, the overflow frequency of the energy accumulators is twice of CF
pulse output frequency. The reading of the energy pulse counter is twice of the number of the output
h
CF pulses.
Table 18-30 Line Frequency Register (DATAFREQ, 0x10FD)
ec
0x10FD, R, Line Frequency Register, DATAFREQ
Value bit15 bit14 …… …… bit1 bit0
Default 0x0000 0 0 0 0 0 0
This register is in the form of 16-bit unsigned.

ot
When MTCLK frequency is 3.2768MHz, the content is updated in 320ms and settled in 500ms. The
frequency measurement resolution is up to 0.05Hz/lsb, and the measurement scale is over the range
of 35~75Hz.
Table 18-31 Data Registers for Channel M

ng
Update Settle
in in
Raw waveform of Channel 32-bit 2’

0x10CE DATAOM R/W 0 0.3ms 10ms
M. complement
DC component of the 32-bit 2’

0x10CF DATADM R/W 0 20ms 70ms
Va
measurement of Channel M. complement
Average DC component of
32-bit 2’
0x10D0 DATAADM the measurement of R/W 0 1.28s 3s
complement
Channel M.
18.4. Calibration Registers

When POR/BOR, RSTn pin reset or WDT overflow reset occurs, all calibration registers are reset to their
default states.
All the default values in this section are in decimal form if not specifically noted.
Table 18-32 Registers for Gain Calibration (R/W)

V98XX Datasheet
Address Register R/W Format Default Description
To set a value to gain

32-bit 2’
0x10E8 SCP calibrate active power in E1 R/W 0
complement
path.
To set a value to gain 32-bit 2’

0x10EB SCI1 R/W 0
calibrate current I1 RMS. complement
The gain
To set a value to gain calibration range
32-bit 2’
0x10E9 SCQ calibrate active/reactive R/W 0 is from -∞ to
complement
power in E2 path. +49.9%.

0x10EC SCI2 R/W 0
h
calibrate current I2 RMS. complement

0x10EA SCU R/W 0
calibrate voltage RMS. complement
ec
Table 18-33 Registers for Power Offset Calibration (R/W)
Address Register R/W Format Default Description
To set a value to
offset calibrate 32-bit 2’
ot
0x10ED PARAPC R/W 0
active power in E1 complement
path. The gain calibration range
To set a value to is from -50% to +50%.
offset calibrate 32-bit 2’
0x10EE PARAQC R/W 0
active/reactive complement
ng
power in E2 path.
Table 18-34 Band-pass Filter Coefficient Register (0x10EF, R/W)
Address Register R/W Format Default
To set the coefficient for the band-pass 32-bit 2’

0x10EF PARABPF R/W 0x889374BC
Va
filter in the RMS calculation circuits. complement
When MTCLK frequency is lowered to 819.2kHz, the sampling frequency of the enabled band-pass
filter in the RMS calculation circuit is changed to 800Hz and the center frequency is changed to 12.5Hz,
which has a greater attenuation on 50Hz signals and will reduce the accuracy of the RMS calculation
and line frequency measurement. So, if MTCLK frequency is reduced to 819.2kHz, users must disable
energy accumulation, CF pulse output and no-load detection, and then configure this register to
0x911D3C9C. When MTCLK frequency is reinstated to 3.2768MHz, this register must be set to its
default value.
Table 18-35 Energy Threshold Registers and Constant Power Register (R/W)
To set a threshold for active energy-to-pulse 32-bit,

0x10F4 GATEP R/W 0
conversion in E1 path. unsigned

V98XX Datasheet
32-bit,
0x10F5 GATECP To set a threshold for no-load detection in E1 path. R/W 0
unsigned
To set a threshold for active or reactive energy-to- 32-bit,

0x10FA GATEQ R/W 0
pulse conversion in E2 path. unsigned
32-bit,
0x10FB GATECQ To set a threshold for no-load detection in E2 path. R/W 0
unsigned
To set a constant for active energy accumulation in 32-bit 2’

0x10FC DATACP R/W 0
E1 path. complement
The energy accumulators are of actual 42-bit length, but the threshold registers for energy-to-pulse
h
conversion are of 32-bit length. So, the threshold registers will be padded with a string of 10 0s on
the right to work as 42-bit registers for computation.
There is an anti-creeping accumulator in the no-load detection circuit. When no-load detection is
ec
enabled, 1s are accumulated in this register constantly. When MTCLK frequency is 3.2768MHz,
1.6384MHz or 819.2kHz, the accumulation frequency is 12800Hz; and when MTCLK frequency is
32768Hz, the accumulation frequency is 2979Hz.
When no-load detection is enabled, the circuit compares the rate at which the anti-creeping
accumulator increments by 1s to that at which the energy accumulators accumulate E1/E2 power or
ot
the preset constant. If the energy accumulator overflows sooner, the anti-creeping accumulator is
cleared, and E1 or E2 path starts to metering energy. Otherwise, the energy accumulator in E1 or E2
path is cleared, and the path enters creeping state. Users can read bit7 or bit6 of register CRPST
(0x287F) to detect the state of the path.
ng
Table 18-36 Threshold Register for Current Detection (R/W)
To set a threshold for 32-bit 2’ complement, both bit31 and

0x1002 IDETTH R/W 0
current detection. bit30 are sign bits.
Va

V98XX Datasheet
19. Outline Dimensions

16.20
16.00 SQ
15.80
14.10 单位：mm
14.00 SQ
13.90 0.177
1.60 0.127
1.50 0.077
1.40
75 51
76 50
h
12.00 REF
V9801S
ec
0.70
LLLLLLLLYYWW 0.50
0.30
0~10 °
100 26
ot
1 25
0.20
0.10
0.30 0.00
0.20 0.50 TYP
0.10
V9801S
ng
1.60MAX
1.45
1.40
10.10
10.00 SQ
1.35 Unit: mm
0.75
0.60
0.45
9.690 0.69
0.64
0.59
48 33
Va
49 32
1.00 REF
13°
12°
11°
0.08
12.00 SQ
12.20
11.80
V9811A/S
0.20
0.08
LLLLLLLLYYWW
0.15
0.05
64 17
1 16
0.50 BSC 0.27

0.18
V9811S/V9811A

V98XX Datasheet
9.20
9.00 SQ 1.60 max
8.80
单位：mm
1.45
7.10 1.40
1.35 0.17
7.00 SQ
0.13
6.90
0.69
0.64
48 33 0.59
49 32 0.24
0.16
0.21
0.18
0.15
0.14 0.17
0.13 0.13
0.12
V9811B
BASE METAL
LLLLLLLLYYWW
WITH PLATING
h
SECTION B-B
64 17
1 16
0.4BSC 0.24
ec
0.16
V9811B
Unit：mm
9.20
9.00 SQ
0.15
8.80 1.05 0.05
ot
7.10 1.00
7.00 0.95 0.61
6.90 0.56
0.51
36 25
0.08
37 24
0.08
ng
0.20
7.0°
3.5°
0.0°
0.15
0.05
0.26
0.18
V9821(S) 0.23
0.20
0.17
LLLLLLLLYYWW
Va
0.14 0.17
0.13 0.13
0.12
48 13
0.15 BASE METAL
1 12 0.05
0.26
0.18
WITH PLATING
0.50 BSC
SECTION B-B
V9821/V9821S
Table 19-1. Chip Marking Definitions
NO. Marking Description
1 Vango Logo

V98XX Datasheet
2 V98XX Part number
3 LLLLLLLL Lot Number. The number of characters of Lot Number varies between
8 to 11
YY: Year
4 YYWW WW: Week
h
ec
ot
ng
Va

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V98XX

Specifications are subject to change without notice.

Copyright © 2022 Vango Technologies, Inc.

This document contains information that is proprietary to Vango Technologies, Inc.

Unauthorized reproduction of this information in whole or in part is strictly prohibited.

2015.06.05 0.1 Initial release

 Modified typical current load in sleeping mode from 10μA to 12μA

 Modified “0b000” to “0b001” in Table 18-10

 Updated Table 4-3 Allocation of Info Area

 Modified function description of “FWC”

2015.11.12 0.3  Updated Figure 4-2 Data Memory

 Set the bit of “BGPCHOPN” to ‘0’ in Table 18-10 BandGap Control

 Modified the registers and related content of temperature

 Updated Table 17-10 RTC Timing Registers

 Emphasized the setting of time information in sequence and at one

 Modified “IOP14” to “P14WK”, “PLLCNT” to “PLLCNTST”

2016.10.01 0.5  Added V98XX Resource Comparison

 Updated operating current in sleeping mode to 10μA and maximum

current in sleeping mode to 14.5μA.

 Modify the formula of Phase Compensation

 Modify storage temperature to - 55 ~ 150 C

 Modify the input range of current and voltage channels

 Modify the LCD Drive Waveform

Hangzhou Vango Technologies, Inc. 2 / 264

2021.04.15 3.3  Update IEC Standard·

2021.06.02 3.4  Update document format

2021.11.18 3.5  Delete V9881D

2022.01.22 3.6  Add part marking

Hangzhou Vango Technologies, Inc. 3 / 264

- Operating temperature: -40 °C ~ +85 °C  Positive/Negative and

 Average apparent power

shunt or CT for current sensing

Hangzhou Vango Technologies, Inc. 4 / 264

 Programmable threshold for no-load  Supporting PWM output

 One additional comparator  Configurable drive voltage over a

 Integrated RTC and temperature  Debugging via JTAG interfaces in

Hangzhou Vango Technologies, Inc. 5 / 264

Peripherals V9801S V9811S V9811A V9811B V9821 V9821S

Package LQFP100 LQFP64 LQFP64 LQFP64(7*7) TQFP48 TQFP48

SRAM 4KB 4KB 4KB 4KB 4KB 4KB

1/3 bias or 1/3 bias or 1/3 Bias or 1/3 Bias or

Hangzhou Vango Technologies, Inc. 6 / 264

General Description ................................................................................................................ 4

Table of Contents ................................................................................................................... 7

Figure List ............................................................................................................................ 11

Table List ............................................................................................................................. 14

1. Electrical Characteristics ............................................................................................. 22

2. Pin Descriptions .......................................................................................................... 28

4. 8052 MCU Core Architecture ........................................................................................ 47

4.4. Program Memory ...................................................................................................... 56

5.2. Level 2 .................................................................................................................... 67

Hangzhou Vango Technologies, Inc. 7 / 264

7. Power Management ..................................................................................................... 87

8. Power Supply .............................................................................................................. 98

9. Comparator ............................................................................................................... 101

10. Energy Metering ........................................................................................................ 103

10.8. Digital Input ........................................................................................................ 112

10.13. Energy Accumulation and CF Pulse Output ........................................................... 118

Hangzhou Vango Technologies, Inc. 8 / 264