TC7660

Charge Pump DC-to-DC Voltage Converter

Features Package Types
• Wide Input Voltage Range: +1.5V to +10V
PDIP/CERDIP/SOIC
• Efficient Voltage Conversion (99.9%, typ)
• Excellent Power Efficiency (98%, typ) NC 1 8 V+
• Low Power Consumption: 80 µA (typ) @ VIN = 5V
CAP+ 2 7 OSC
• Low Cost and Easy to Use TC7660 LOW
- Only Two External Capacitors Required GND 3 6
VOLTAGE (LV)
• Available in 8-Pin Small Outline (SOIC), 8-Pin CAP- 4 5 VOUT
PDIP and 8-Pin CERDIP Packages
• Improved ESD Protection (3 kV HBM)
• No External Diode Required for High-Voltage General Description
Operation
The TC7660 device is a pin-compatible replacement
Applications for the industry standard 7660 charge pump voltage
converter. It converts a +1.5V to +10V input to a corre-
• RS-232 Negative Power Supply
sponding -1.5V to -10V output using only two low-cost
• Simple Conversion of +5V to ±5V Supplies capacitors, eliminating inductors and their associated
• Voltage Multiplication VOUT = ± n V+ cost, size and electromagnetic interference (EMI).
• Negative Supplies for Data Acquisition Systems The on-board oscillator operates at a nominal fre-
and Instrumentation quency of 10 kHz. Operation below 10 kHz (for lower
supply current applications) is possible by connecting
an external capacitor from OSC to ground.
The TC7660 is available in 8-Pin PDIP, 8-Pin Small
Outline (SOIC) and 8-Pin CERDIP packages in
commercial and extended temperature ranges.
Functional Block Diagram

V+ CAP+

8 2

7 RC Voltage
OSC 2 Level 4
Oscillator CAP-
Translator
6
LV
5 VOUT
Internal
Internal
Voltage
Voltage
Regulator
Regulator

Logic
Network
TC7660
3

GND

 2002-2011 Microchip Technology Inc. DS21465C-page 1

TC7660
1.0 ELECTRICAL * Notice: Stresses above those listed under “Maximum Rat-
ings” may cause permanent damage to the device. This is a
CHARACTERISTICS stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
Absolute Maximum Ratings* operational sections of this specification is not intended. Expo-
Supply Voltage .............................................................+10.5V sure to maximum rating conditions for extended periods may
affect device reliability.
LV and OSC Inputs Voltage: (Note 1)
.............................................. -0.3V to VSS for V+ < 5.5V
..................................... (V+ – 5.5V) to (V+) for V+ > 5.5V IS
Current into LV ......................................... 20 µA for V+ > 3.5V 1 8
Output Short Duration (VSUPPLY  5.5V)............... Continuous 2 7 V+
IL
Package Power Dissipation: (TA  70°C) C1 + TC7660 (+5V)
3 6 COSC
8-Pin CERDIP ....................................................800 mW 10 µF
8-Pin PDIP .........................................................730 mW 4 5 RL
8-Pin SOIC .........................................................470 mW
Operating Temperature Range: VOUT
C Suffix.......................................................0°C to +70°C
I Suffix .....................................................-25°C to +85°C C2
E Suffix ....................................................-40°C to +85°C + 10 µF
M Suffix .................................................-55°C to +125°C
Storage Temperature Range .........................-65°C to +160°C
ESD protection on all pins (HBM) ................... .............. 3 kV FIGURE 1-1: TC7660 Test Circuit.
Maximum Junction Temperature ........... ....................... 150°C

ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise noted, specifications measured over operating temperature range with V+ = 5V,
COSC = 0, refer to test circuit in Figure 1-1.
Parameters Sym Min Typ Max Units Conditions

Supply Current I+ — 80 180 µA RL = 

Supply Voltage Range, High V+H 3.0 — 10 V Min TAMax, RL = 10 k, LV Open
Supply Voltage Range, Low V+L 1.5 — 3.5 V Min TAMax, RL = 10 k, LV to GND
Output Source Resistance ROUT — 70 100  IOUT=20 mA, TA = +25°C
— — 120 IOUT=20 mA, TA  +70°C (C Device)
— — 130 IOUT=20 mA, TA  +85°C (E and I Device)
— 104 150 IOUT=20 mA, TA  +125°C (M Device)
— 150 300 V+ = 2V, IOUT = 3 mA, LV to GND
0°C  TA  +70°C
— 160 600 V+ = 2V, IOUT = 3 mA, LV to GND
-55°C  TA  +125°C (M Device)
Oscillator Frequency fOSC — 10 — kHz Pin 7 open

Power Efficiency PEFF 95 98 — % RL = 5 k

Voltage Conversion Efficiency VOUTEFF 97 99.9 — % RL = 

Oscillator Impedance ZOSC — 1.0 — M V+ = 2V

— 100 — k V+ = 5V
Note 1: Destructive latch-up may occur if voltages greater than V+ or less than GND are supplied to any input pin.

DS21465C-page 2  2002-2011 Microchip Technology Inc.

 TC7660
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, C1 = C2 = 10 µF, ESRC1 = ESRC2 = 1 , TA = 25°C. See Figure 1-1.

12 100

POWER CONVERSION EFFICIENCY (%)

98
10 IOUT = 1 mA
96
SUPPLY VOLTAGE (V)

8 94
92
6 IOUT = 15 mA
90

SUPPLY VOLTAGE RANGE 88

4
86

2 84
82
V+ = +5V
0 80
-55 -25 0 +25 +50 +75 +100 +125 100 1k 10k
TEMPERATURE (°C) OSCILLATOR FREQUENCY (Hz)

FIGURE 2-1: Operating Voltage vs. FIGURE 2-4: Power Conversion

Temperature. Efficiency vs. Oscillator Frequency.

10k 500
OUTPUT SOURCE RESISTANCE (Ω) IOUT = 1 mA
OUTPUT SOURCE RESISTANCE (Ω)

450

400
1k
200

150
100Ω V + = +2V
100
V + = +5V
50

10Ω 0
0 1 2 3 4 5 6 7 8 -55 -25 0 +25 +50 +75 +100 +125
SUPPLY VOLTAGE (V) TEMPERATURE (°C)

FIGURE 2-2: Output Source Resistance FIGURE 2-5: Output Source Resistance
vs. Supply Voltage. vs. Temperature.

10k 20
V+ = +5V V+ = +5V
OSCILLATOR FREQUENCY (kHz)
OSCILLATOR FREQUENCY (Hz)

18

16
1k

14

12
100
10

10 6
1 10 100 1000 10k -55 -25 0 +25 +50 +75 +100 +125
OSCILLATOR CAPACITANCE (pF) TEMPERATURE (°C)

FIGURE 2-3: Frequency of Oscillation vs. FIGURE 2-6: Unloaded Oscillator

Oscillator Capacitance. Frequency vs. Temperature.

 2002-2011 Microchip Technology Inc. DS21465C-page 3

TC7660
Note: Unless otherwise indicated, C1 = C2 = 10 µF, ESRC1 = ESRC2 = 1 , TA = 25°C. See Figure 1-1.

0 5
V+ = +5V
-1 4

-2 3

OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

-3 2

-4 1

-5 0

-6 -1

-7 -2

-8 -3
-4 SLOPE 55Ω
-9
LV OPEN
-10 -5
0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80
OUTPUT CURRENT (mA) LOAD CURRENT (mA)

FIGURE 2-7: Output Voltage vs. Output FIGURE 2-10: Output Voltage vs. Load
Current. Current.

100 20 100 100

POWER CONVERSION EFFICIENCY (%)

POWER CONVERSION EFFICIENCY (%)

90 V+ = 2V 18 90 90
80 16 80 80

SUPPLY CURRENT (mA)

SUPPLY CURRENT (mA)

70 14 70 70
60 12 60 60
50 10 50 50

40 8 40 40
30 6 30 30
20 4 20 20

10 2 10 10
V+ = +5V
0 0
0 1.5 3.0 4.5 6.0 7.5 9.0 0 10 20 30 40 50 60
LOAD CURRENT (mA) LOAD CURRENT (mA)

FIGURE 2-8: Supply Current and Power FIGURE 2-11: Supply Current and Power
Conversion Efficiency vs. Load Current. Conversion Efficiency vs. Load Current.

2
V+ = +2V

1
OUTPUT VOLTAGE (V)

-1

SLOPE 150Ω
-2
0 1 2 3 4 5 6 7 8
LOAD CURRENT (mA)

FIGURE 2-9: Output Voltage vs. Load

Current.

DS21465C-page 4  2002-2011 Microchip Technology Inc.

 TC7660
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

Pin No. Symbol Description
1 NC No connection
2 CAP+ Charge pump capacitor positive terminal
3 GND Ground terminal
4 CAP- Charge pump capacitor negative terminal
5 VOUT Output voltage
6 LV Low voltage pin. Connect to GND for V+ < 3.5V
7 OSC Oscillator control input. Bypass with an external capacitor to slow the oscillator
8 V+ Power supply positive voltage input

3.1 Charge Pump Capacitor (CAP+) 3.5 Low Voltage Pin (LV)
Positive connection for the charge pump capacitor, or The low voltage pin ensures proper operation of the
flying capacitor, used to transfer charge from the input internal oscillator for input voltages below 3.5V. The low
source to the output. In the voltage-inverting configura- voltage pin should be connected to ground (GND) for
tion, the charge pump capacitor is charged to the input input voltages below 3.5V. Otherwise, the low voltage
voltage during the first half of the switching cycle. Dur- pin should be allowed to float.
ing the second half of the switching cycle, the charge
pump capacitor is inverted and charge is transferred to 3.6 Oscillator Control Input (OSC)
the output capacitor and load.
The oscillator control input can be utilized to slow down
It is recommended that a low ESR (equivalent series or speed up the operation of the TC7660. Refer to
resistance) capacitor be used. Additionally, larger Section 5.4 “Changing the TC7660 Oscillator Fre-
values will lower the output resistance. quency”, for details on altering the oscillator
frequency.
3.2 Ground (GND)
Input and output zero volt reference.
3.7 Power Supply (V+)
Positive power supply input voltage connection. It is
3.3 Charge Pump Capacitor (CAP-) recommended that a low ESR (equivalent series resis-
Negative connection for the charge pump capacitor, or tance) capacitor be used to bypass the power supply
flying capacitor, used to transfer charge from the input input to ground (GND).
to the output. Proper orientation is imperative when
using a polarized capacitor.

3.4 Output Voltage (VOUT)

Negative connection for the charge pump output
capacitor. In the voltage-inverting configuration, the
charge pump output capacitor supplies the output load
during the first half of the switching cycle. During the
second half of the switching cycle, charge is restored to
the charge pump output capacitor.
It is recommended that a low ESR (equivalent series
resistance) capacitor be used. Additionally, larger
values will lower the output ripple.

 2002-2011 Microchip Technology Inc. DS21465C-page 5

TC7660
4.0 DETAILED DESCRIPTION EQUATION
1
4.1 Theory of Operation R OUT = ----------------------------- + 8R SW + 4ESR C1 + ESR C2
fPUMP  C1
The TC7660 charge pump converter inverts the voltage
applied to the V + pin. The conversion consists of a two- Where:
phase operation (Figure 4-1). During the first phase, f OSC
switches S2 and S4 are open and switches S1 and S3 f PUMP = -----------
are closed. C1 charges to the voltage applied to the V + 2
R SW = on-resistance of the switches
pin, with the load current being supplied from C2. Dur-
ing the second phase, switches S2 and S4 are closed ESR C1 = equivalent series resistance of C 1
and switches S1 and S3 are open. Charge is trans- ESR C2 = equivalent series resistance of C 2
ferred from C1 to C2, with the load current being
supplied from C1.
4.2 Switched Capacitor Inverter
Power Losses
S1 S2
V+ The overall power loss of a switched capacitor inverter
+ is affected by four factors:
C1
1. Losses from power consumed by the internal
oscillator, switch drive, etc. These losses will
+ vary with input voltage, temperature and
GND C2
S3 S4 oscillator frequency.
VOUT = -VIN 2. Conduction losses in the non-ideal switches.
3. Losses due to the non-ideal nature of the
external capacitors.
4. Losses that occur during charge transfer from
C1 to C2 when a voltage difference between the
capacitors exists.
FIGURE 4-1: Ideal Switched Capacitor
Figure 4-3 depicts the non-ideal elements associated
Inverter.
with the switched capacitor inverter power loss.
In this manner, the TC7660 performs a voltage inver-
sion, but does not provide regulation. The average out-
put voltage will drop in a linear manner with respect to S1 S2
RSW RSW
load current. The equivalent circuit of the charge pump
inverter can be modeled as an ideal voltage source in
series with a resistor, as shown in Figure 4-2.
+ +
V+ IDD C1 C2
+
-
IOUT LOAD
ROUT ESRC1 ESRC2
VOUT
S3 S4
- RSW RSW
V+
+
FIGURE 4-3: Non-Ideal Switched
Capacitor Inverter.
FIGURE 4-2: Switched Capacitor Inverter
The power loss is calculated using the following
Equivalent Circuit Model.
equation:
The value of the series resistor (ROUT) is a function of
the switching frequency, capacitance and equivalent EQUATION
series resistance (ESR) of C1 and C2 and the on-resis-
tance of switches S1, S2, S3 and S4. A close 2 +
P LOSS = I OUT  R OUT + I DD  V
approximation for ROUT is given in the following
equation:

DS21465C-page 6  2002-2011 Microchip Technology Inc.

 TC7660
5.0 APPLICATIONS INFORMATION 5.2 Paralleling Devices
To reduce the value of ROUT, multiple TC7660 voltage
5.1 Simple Negative Voltage
converters can be connected in parallel (Figure 5-2).
Converter The output resistance will be reduced by approximately
Figure 5-1 shows typical connections to provide a a factor of n, where n is the number of devices
negative supply where a positive supply is available. A connected in parallel.
similar scheme may be employed for supply voltages EQUATION
anywhere in the operating range of +1.5V to +10V,
keeping in mind that pin 6 (LV) is tied to the supply R OUT  of TC7660 
R OUT = ---------------------------------------------------------
negative (GND) only for supply voltages below 3.5V. n  number of devices 

V+ While each device requires its own pump capacitor

(C1), all devices may share one reservoir capacitor
1 8
(C2). To preserve ripple performance, the value of C2
+
2 7 VOUT* should be scaled according to the number of devices
C1 TC7660 C2 connected in parallel.
10 µF 3 6
+ 10 µF
4 5 5.3 Cascading Devices
* VOUT = -V+ for 1.5V  V+  10V A larger negative multiplication of the initial supply volt-
age can be obtained by cascading multiple TC7660
FIGURE 5-1: Simple Negative Converter. devices. The output voltage and the output resistance
will both increase by approximately a factor of n, where
The output characteristics of the circuit in Figure 5-1
n is the number of devices cascaded.
are those of a nearly ideal voltage source in series with
a 70resistor. Thus, for a load current of -10 mA and EQUATION
a supply voltage of +5V, the output voltage would be +
-4.3V. VOUT = – n  V 

ROUT = n  R OUT  of TC7660 

V+
1 8
2 7 1 8
+ TC7660
C1 3 6 2 7 RL
+ TC7660
4 “1” 5 C1 3 6
4 “n” 5

C2
+

FIGURE 5-2: Paralleling Devices Lowers Output Impedance.

V+
1 8
2 7 1 8
+ TC7660
10 µF 3 6 2 7
+ TC7660
4 “1” 5 10 µF 3 6
4 “n” 5 VOUT *
10 µF
+
10 µF
+
* VOUT = -n V+ for 1.5V  V+  10V
FIGURE 5-3: Increased Output Voltage By Cascading Devices.

 2002-2011 Microchip Technology Inc. DS21465C-page 7

TC7660
5.4 Changing the TC7660 Oscillator 5.5 Positive Voltage Multiplication
Frequency Positive voltage multiplication can be obtained by
The operating frequency of the TC7660 can be employing two external diodes (Figure 5-6). Refer to
changed in order to optimize the system performance. the theory of operation of the TC7660 (Section 4.1
The frequency can be increased by over-driving the “Theory of Operation”). During the half cycle when
OSC input (Figure 5-4). Any CMOS logic gate can be switch S2 is closed, capacitor C1 of Figure 5-6 is
utilized in conjunction with a 1 k series resistor. The charged up to a voltage of V+ - VF1, where VF1 is the
resistor is required to prevent device latch-up. While forward voltage drop of diode D1. During the next half
TTL level signals can be utilized, an additional 10 k cycle, switch S1 is closed, shifting the reference of
pull-up resistor to V+ is required. Transitions occur on capacitor C1 from GND to V+. The energy in capacitor
the rising edge of the clock input. The resultant output C1 is transferred to capacitor C2 through diode D2, pro-
voltage ripple frequency is one half the clock input. ducing an output voltage of approximately:
Higher clock frequencies allow for the use of smaller
pump and reservoir capacitors for a given output volt- EQUATION
age ripple and droop. Additionally, this allows the
+
TC7660 to be synchronized to an external clock, V OUT = 2  V –  V F1 + V F2 
eliminating undesirable beat frequencies.
where:
At light loads, lowering the oscillator frequency can VF1 is the forward voltage drop of diode D1
increase the efficiency of the TC7660 (Figure 5-5). By and
lowering the oscillator frequency, the switching losses VF2 is the forward voltage drop of diode D2.
are reduced. Refer to Figure 2-3 to determine the typi-
cal operating frequency based on the value of the
external capacitor. At lower operating frequencies, it V+
may be necessary to increase the values of the pump
and reservoir capacitors in order to maintain the 1 8
desired output voltage ripple and output impedance. 2 7 VOUT =
TC7660 D1
D2 (2 V+) - (2 VF)
V+ 3 6
V+
4 5 + +
1 8 C1 C2
1 k CMOS
2 7 GATE
+ TC7660
10 µF 3 6 FIGURE 5-6: Positive Voltage Multiplier.
4 “1” 5 VOUT
10 µF
5.6 Combined Negative Voltage
+ Conversion and Positive Supply
Multiplication
FIGURE 5-4: External Clocking.
Simultaneous voltage inversion and positive voltage
multiplication can be obtained (Figure 5-7). Capacitors
C1 and C3 perform the voltage inversion, while capaci-
1 8 V+ tors C2 and C4, plus the two diodes, perform the posi-
tive voltage multiplication. Capacitors C1 and C2 are
2 7 the pump capacitors, while capacitors C3 and C4 are
+ TC7660
C1 3 6 COSC the reservoir capacitors for their respective functions.
Both functions utilize the same switches of the TC7660.
4 5 VOUT As a result, if either output is loaded, both outputs will
C2 drop towards GND.
+

FIGURE 5-5: Lowering Oscillator

Frequency.

DS21465C-page 8  2002-2011 Microchip Technology Inc.

 TC7660

V+
VOUT
1 8
= -V+
2 7 C3
+
TC7660 D1
3 6
4 5 VOUT =
+ D2 (2 V+) - (2 VF)
C1
+
C2 +
C4

FIGURE 5-7: Combined Negative

Converter and Positive Multiplier.

5.7 Efficient Positive Voltage

Multiplication/Conversion
Since the switches that allow the charge pumping
operation are bidirectional, the charge transfer can be
performed backwards as easily as forwards.
Figure 5-8 shows a TC7660 transforming -5V to +5V
(or +5V to +10V, etc.). The only problem here is that the
internal clock and switch-drive section will not operate
until some positive voltage has been generated. An ini-
tial inefficient pump, as shown in Figure 5-7, could be
used to start this circuit up, after which it will bypass the
other (D1 and D2 in Figure 5-7 would never turn on), or
else the diode and resistor shown dotted in Figure 5-8
can be used to “force” the internal regulator on.

VOUT = -V -

1 8
+
2 7 10 µF
C1 + 1 M
TC7660
10 µF 3 6
4 5

V - input

FIGURE 5-8: Positive Voltage

Conversion.

 2002-2011 Microchip Technology Inc. DS21465C-page 9

TC7660
6.0 PACKAGING INFORMATION
6.1 Package Marking Information

8-Lead PDIP (300 mil) Example Example

XXXXXXXX TC7660 TC7660

XXXXXNNN CPA e3 256 CPA256
YYWW 1208 1208

8-Lead CERDIP (.300”) Example Example

XXXXXXXX TC7660 TC7660

XXXXXNNN MJA e3 256 MJA256
YYWW 1208 1208

8-Lead SOIC (3.90 mm) Example Example

TC7660C TC7660C
OA e3 1208 OA1208
NNN 256 256

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.

DS21465C-page 10  2002-2011 Microchip Technology Inc.

 TC7660

        

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&& 366***' '6 5 

NOTE 1
E1

1 2 3

D
E

A A2

A1 L
c

e
b1 eB
b

7&! 8,9.
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# # 5 5 !!  1 - 1
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  !" # $% &" '  ()"&'"!&)  & #*&&  & #  
 + % &,  & !&
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 ' !  #&    .01
2,32 !' !  &  $ & " !**&"&&   !

     * , =2

 2002-2011 Microchip Technology Inc. DS21465C-page 11

TC7660

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS21465C-page 12  2002-2011 Microchip Technology Inc.

 TC7660

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2002-2011 Microchip Technology Inc. DS21465C-page 13

TC7660

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS21465C-page 14  2002-2011 Microchip Technology Inc.

 TC7660
  ! " "##$%&'!"(
  4& '!&" & 5 # * !(  ! ! &   5   % & & # &
&& 366***' '6 5 

 2002-2011 Microchip Technology Inc. DS21465C-page 15

TC7660
APPENDIX A: REVISION HISTORY

Revision C (March 2012)

The following is the list of modifications.
1. Updated Figure 5-5.
2. Added Appendix A.

Revision B (March 2003)

Undocumented changes.

Revision A (May 2002)

Original release of this document.

DS21465C-page 16  2002-2012 Microchip Technology Inc.

 TC7660
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X /XX Examples:

a) TC7660COA: Commercial Temp., SOIC
Device Temperature Package package.
Range b) TC7660COA713:Tape and Reel, Commercial
Temp., SOIC package.
c) TC7660CPA: Commercial Temp., PDIP
Device: TC7660: DC-to-DC Voltage Converter package.
d) TC7660EOA: Extended Temp., SOIC
package.
Temperature Range: C = 0°C to +70°C e) TC7660EOA713: Tape and Reel, Extended
E = -40°C to +85°C Temp., SOIC package.
I = -25°C to +85°C (CERDIP only) f) TC7660EPA: Extended Temp., PDIP
M = -55°C to +125°C (CERDIP only) package.
g) TC7660IJA: Industrial Temp., CERDIP
package
Package: PA = Plastic DIP, (300 mil body), 8-lead
h) TC7660MJA: Military Temp., CERDIP
JA = Ceramic DIP, (300 mil body), 8-lead
package.
OA = SOIC (Narrow), 8-lead
OA713 = SOIC (Narrow), 8-lead (Tape and Reel)

 2002-2012 Microchip Technology Inc. DS21465C-page 17

TC7660
NOTES:

DS21465C-page 18  2002-2012 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of
MICROCHIP MAKES NO REPRESENTATIONS OR
Microchip Technology Incorporated in the U.S.A. and other
WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control
QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip
FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, chipKIT,
devices in life support and/or safety applications is entirely at chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
hold harmless Microchip from any and all damages, claims, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
suits, or expenses resulting from such use. No licenses are Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
conveyed, implicitly or otherwise, under any Microchip MPLINK, mTouch, Omniscient Code Generation, PICC,
intellectual property rights. PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002-2012, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.

ISBN: 978-1-62076-089-5

QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
== ISO/TS 16949 == devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

 2002-2012 Microchip Technology Inc. DS21465C-page 19

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DS21465C-page 20  2002-2012 Microchip Technology Inc.