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Application Note 53
Implementing an RC5051 DC-DC Converter on
Pentium® II Motherboards

Introduction Intel Pentium II Processor Power

This document describes how to implement a switching volt- Requirements
age regulator using an RC5051 high speed controller, a Refer to Intel’s AP-587 Application Note, Slot 1 Processor
power inductor, a Schottky diode, appropriate capacitors, Power Distribution Guidelines, May 1997 (order number
and external power MOSFETs. This regulator forms a step 243332-001), as a basic reference.
down DC-DC converter that can deliver up to 14.5A of
continuous load current at voltages ranging from 1.3V to Input Voltages
3.5V. A specific application circuit, design considerations,
Available inputs are +12V ±5% and +5V ±5%. Either one or
component selection, PCB layout guidelines, and per-
both of these inputs can be used by the DC-DC converter.
formance evaluations are covered in detail.
The input voltage requirements for Fairchild’s RC5051 DC-
DC converter are listed in Table 1. See below for detailed
In the past 10 years, microprocessors have evolved at such a
information on how to apply these.
rate that a modern chip can rival the computing power of a
mainframe computer. Such evolution has been possible
because of the increasing numbers of transistors that proces-
Table 1. Input Voltage Requirements
sors integrate. Pentium CPUs, for example, integrate well MOSFET
over 5 million transistors on a single piece of silicon. Part # Vcc for IC Drain
RC5051 +5V ±5% +5V ±5% or 12V ±5%
To integrate so many transistors on a piece of silicon, their
physical geometry has been reduced to the sub-micron level.
As a result of each geometry reduction, the corresponding
Pentium II DC Power Requirements
operational voltage for each transistor has also been reduced. Refer to Table 2, Intel Pentium II Processor Power Specifica-
This changing CPU voltage demands the design of a pro- tions. For standard motherboard designs , the on-board DC-DC
grammable power supply–a design that is not completely converter must supply a minimum of 14.2A at 2.8V for Klamath
re-engineered with every change in CPU voltage. or 2.0V for Deschutes. For a Deschutes Flexible Motherboard
design, the on-board DC-DC converter must supply 18.9A.
The voltage range of the CPU has shown a downwards trend
for the past 5 years: from 3.3V for the Pentium, to 3.1V for DC Voltage Regulation
the Pentium Pro, to 2.8V for the Klamath, and to 2.0V for As indicated in Table 2, the voltage level supplied to the
the Deschutes processors. With this trend in mind, Fairchild CPU must be within ±3% of its nominal setting. Voltage reg-
Semiconductor has designed the RC5051 controller. This ulation limits must include:
controller integrates the necessary programmability to
address the changing power supply requirements of lower • Output load ranges specified in Table 2
voltage CPUs. • Output ripple/noise
• DC output initial voltage set point
Previous generations of DC-DC converter controllers were • Temperature and warm up drift (Ambient +0°C to +70°C
designed with fixed output voltages adjustable only by at full load with a maximum rate of change of 5°C per 10
means of a set of external resistors. In a high volume produc- minutes but no more than 10°C per hour)
tion environment (such as with personal computers), how- • Output load transient with:
ever, a CPU voltage change would require a CPU board re- • Slew rate >30A/ms at converter pins Range:
design to accommodate the new voltage requirement. The 0.3A - ICCP Max (as defined in Table 2).
5-bit DAC in the RC5051 reads the voltage ID code that is
programmed into modern processors and provides the appro-
priate CPU voltage. In this manner, the PC board does not
have to be re-designed each time the CPU voltage changes.
The CPU can thus automatically configure its own required
supply voltage.

Pentium is a registered trademark of Intel Corporation. Rev. 1.0.0

AN53 APPLICATION NOTE

Table 2. Intel Pentium II® Processor Power Specifications

Voltage Specification,
CPU Model, Features VCC CORE (VDC) Maximum Current, ICC CORE (A)
Klamath 2.8V +100mV/-60mV
233MHz 11.8
266MHz 12.7
300MHz 14.2
Deschutes
266MHz 2.0V +100mV/-60mV 8.5
300MHz 2.0V +100mV/-60mV 9.6
333MHz 2.0V +100mV/-60mV 10.6
350MHz 2.0V +/-60mV 11.1
400MHz 2.0V +/-60mV 12.1
450MHz 2.0V +/-60mV 14.2
500MHz 2.0V +/-60mV 16.0
Deschutes Flexible Motherboard 2.0V +/-60mV 18.9
NOTES:
1. Maximum power values are measured at typical VCCP to take into account the thermal time constant of the CPU package.
2. Flexible motherboard specifications are recommendations only. Actual specifications are subject to change.

Output Ripple and Noise Table 3. Output Voltage Programming

Ripple and noise are defined as periodic or random signals Codes (continued)
over the frequency band of 0–20MHz at the output pins.
Output ripple and noise must be consistent with voltage VID4 VID3 VID2 VID1 VID0 VOUT to CPU
requirements throughout the full load range and under all 0 1 0 0 0 1.65V
specified input voltage conditions. 0 0 1 1 1 1.70V
0 0 1 1 0 1.75V
Efficiency 0 0 1 0 1 1.80V
The efficiency of the DC-DC converter must be greater than 0 0 1 0 0 1.85V
80% at maximum output current and greater than 40% at low
0 0 0 1 1 1.90V
current draw.
0 0 0 1 0 1.95V
Processor Voltage Identification 0 0 0 0 1 2.00V
There are five Voltage Identification Pins, VID4-VID0, on the 0 0 0 0 0 2.05V
Pentium II processor package which can be used to support 1 1 1 1 1 No CPU
automatic selection of the power supply voltage. These pins are 1 1 1 1 0 2.1V
internally unconnected or are shorted to ground (VSS ). The 1 1 1 0 1 2.2V
logic status of the VID pins defines the voltage required by the 1 1 1 0 0 2.3V
processor. In order to address future low voltage microproces-
1 1 0 1 1 2.4V
sors, the RC5051 includes a VID4 input bit to extend the output
voltage range as low as 1.3V. The output voltage programming 1 1 0 1 0 2.5V
codes are presented in Table 3. A ‘1’ refers to an open pin and a 1 1 0 0 1 2.6V
‘0’ refers to a short to ground. 1 1 0 0 0 2.7V
1 0 1 1 1 2.8V
Table 3. Output Voltage Programming 1 0 1 1 0 2.9V
Codes 1 0 1 0 1 3.0V
VID4 VID3 VID2 VID1 VID0 VOUT to CPU 1 0 1 0 0 3.1V
0 1 1 1 1 1.30V 1 0 0 1 1 3.2V
0 1 1 1 0 1.35V 1 0 0 1 0 3.3V
0 1 1 0 1 1.40V 1 0 0 0 1 3.4V
0 1 1 0 0 1.45V 1 0 0 0 0 3.5V
0 1 0 1 1 1.50V Note:
0 1 0 1 0 1.55V 1. 0 = processor pin is tied to GND
1 = processor pin is open.
0 1 0 0 1 1.60V

2
APPLICATION NOTE AN53

I/O Controls The RC5051 Controller

In addition to the Voltage Identification, there are several sig- The RC5051 is a programmable synchronous DC-DC
nals that control the DC-DC converter or provide feedback from controller IC. When designed around the appropriate exter-
the DC-DC converter to the CPU. They are Power-Good nal components, this device can be configured to deliver
(PWRGD), and Output Enable (OUTEN). These signals will be
more than 14.5A of output current. The RC5051 utilizes both
discussed later.
current-mode and voltage-mode PWM control to create an
integrated step-down voltage regulator.
RC5051 Description
Main Control Loop
Simple Step-Down Converter
Refer to the RC5051 Block Diagram illustrated in Figure 2.
S1 L1 The control loop of the regulator contains two main sections:
+ the analog control block and the digital control block. The
analog section consists of signal conditioning amplifiers
VIN D1 C1 RL Vout
feeding into a set of comparators which provide the inputs to
the digital control block. The signal conditioning section
accepts inputs from the IFB (current feedback) and VFB
–
65-AP53-03 (voltage feedback) pins and sets up two controlling signal
paths. The voltage control path amplifies the difference
Figure 1. Simple Buck DC-DC Converter between the VFB signal and the voltage reference and pre-
sents the output to one of the summing amplifier inputs. The
For the purpose of understanding a buck converter, Figure 1 current control path takes the difference between the IFB and
illustrates a step-down DC-DC converter with no feedback con- VFB pins and presents the resulting signal to another input
trol. The operation of the basic step-down converter is the basis of the summing amplifier. These two signals are then
for the design equations for the RC5051. Referring to Figure 1, summed together with the slope compensation input from
the basic operation begins by closing the switch S1. When S1 is the oscillator. This output is then presented to a comparator,
closed, the input voltage VIN is applied to inductor L1. The cur- which provides the main PWM control signal to the digital
rent flowing in this inductor increases, and the increase is given control block.
by the following equation:
The additional comparators in the analog control section set
( V IN – V OUT )T ON
DI L = ---------------------------------------------- the point at which the current limit comparator disables the
L1 output drive signals to the external power MOSFETs.
where TON is the time S1 is closed (the duty cycle is TON / TS,
The digital control block takes the comparator inputs and the
with TS the switching period). When S1 opens, the diode D1
main clock signal from the oscillator to provide the appropri-
conducts the inductor current and the output current is delivered
ate pulses to the HIDRV and LODRV output pins. These
to the load; the inductor current decrease is given by:
pins control the external power MOSFETs. The digital sec-
V OUT ( T S – T ON ) tion utilizes high speed Schottky transistor logic, allowing
DI L = ------------------------------------------
- the RC5051 to operate at clock speeds as high as 1MHz.
L1

where (TS - TON ) is the time during which S1 is open. High Current Output Drivers
The RC5051 contains two identical high current output
By solving these two equations, we can arrive at the basic rela- drivers that utilize high speed bipolar transistors in a push-
tionship for the output voltage of a step-down converter: pull configuration. Each driver is capable of delivering 1A of
T ON current in less than 100ns. Each driver’s power and ground
V OUT = V IN ----------- are separated from the chip’s power and ground for addi-
TS
tional switching noise immunity.
In order to obtain a more accurate approximation for VOUT , we
must also include the forward voltage VD across diode D1 and
the voltage across the switch , VSW . After taking into account
these factors, the new relationship becomes:

T ON
V OUT = ( V IN + V D – V SW ) ----------- – V D
TS

where VSW = is the voltage across the MOSFET in the on state,

I L * R DS,ON.

3
AN53 APPLICATION NOTE

+12V

RC5051 +5V

5
–
1 4
OSC +

– 13
+
12

– DIGITAL +5V
– + CONTROL 7 VO
+
9

16 5-BIT 1.24V
VREF REFERENCE
DAC POWER 3
GOOD PWRGD
65-5051-01
20 19 18 17 8 2

VID0 VID2 VID4 ENABLE

VID1 VID3

Figure 2. RC5051 Block Diagram

The HIDRV driver has a power supply, VCCQP, supplied from a Output Enable (OUTEN)
12V source as illustrated in Figure 2. The resulting voltage is The DC-DC converter accepts an open collector signal for
sufficient to provide the gate to source voltage to the external controlling the output voltage. The low state disables the
MOSFET that is required to achieve a low R DS,ON . Since the output voltage. When disabled, the PWRGD output is in the
low side synchronous FET is referenced to ground, there is no low state.
need to boost the gate drive voltage, and its VCCP power pin can
be tied to VCC. Over-Voltage Protection
Internal Voltage Reference The RC5051 constantly monitors the output voltage for pro-
tection against over voltage conditions. If the voltage at the
The reference included in the RC5051 is a precision band- VFB pin exceeds 20% of the selected program voltage, an
gap voltage reference. The internal resistors are precisely over-voltage condition is assumed and the chip disables the
trimmed to provide a near zero temperature coefficient (TC). output drive signal to the external MOSFETs.
Added to the reference input is the resulting output from an
integrated 5-bit DAC–provided in accordance with the Pen- Over-current Protection
tium II specification guidelines. These guidelines require the
DC-DC converter output to be directly programmable via a A current sense methodology is implemented to disable the
5-bit voltage identification (VID) code. This code scales the output drive signal to the MOSFETs when an over-current
reference voltage from 2.0V (no CPU) to 3.5V in 100mV condition is detected. The voltage drop created by the output
increments, and between 1.3V and 2.05V in 50mV incre- current flowing across a sense resistor is presented to an
ments. For guaranteed stable operation under all operating internal comparator. When the voltage developed across the
conditions, 0.1mF of decoupling capacitance should be sense resistor exceeds the comparator threshold voltage, the
connected to the VREF pin. No load should be imposed on chip reduces the output drive signal to the MOSFETs.
this pin.
The DC-DC converter returns to normal operation after the
Power Good (PWRGD) fault has been removed, for either an over-voltage or an over-
current condition.
The RC5051 Power Good function is designed in accordance
with the Pentium II DC-DC converter specification to pro- Oscillator
vide a constant voltage monitor on the VFB pin. The circuit
compares the VFB signal to the VREF voltage and outputs an The RC5051 oscillator section uses a fixed current capacitor
active-low interrupt signal to the CPU when the power sup- charging configuration. An external capacitor (C EXT ) is used to
ply voltage differs more than ±12% from nominal. The preset the oscillator frequency between 80KHz and 1MHz.
Power Good flag provides no other control function to the This scheme allows maximum flexibility in choosing external
RC5051. components.

4
APPLICATION NOTE AN53

In general, a higher operating frequency decreases the peak An operating frequency of 300 kHz was chosen in this
ripple current flowing in the output inductor, thus allowing Application Note to optimize efficiency while maintaining
the use of a smaller inductor value. operation at higher fre- excellent regulation and transient performance under all
quencies also decreases the amount of energy storage that operating conditions.
must be provided by the bulk output capacitors during load
transients. Design Considerations and Component
Selection
Unfortunately, the efficiency losses due to switching of the Figure 3 illustrates a synchronous application using the
MOSFETs increase as the operating frequency is increased. RC5051.
Thus, efficiency is optimized at lower operating frequencies.

+12V
L1
+5V
2.5mH
C1 0.1mF CIN* C2 0.1mF D1
R1
47½ 1N4735A

C6
0.1mF

C5
1mF
R2
Q1
L2 R SENSE*
4.7½
C4 VO
11 10 1mF R3 2.3µH
12 9 Q2
D2 COUT*
13 8 4.7½ 1N5820
14 7
15 6
RC5051
16 5
VREF
17 4
18 3
C3 0.1mF
19 2
20 1

CEXT
100pF

VID4
ENABLE VCC
VID3 *Refer to Table 3 for values of
R4 10K½ RSENSE, COUT, and CIN.
VID2 C7
0.1mF PWRGD
VID1
C8 0.1mF
VID0

65-5051-03

Figure 3. Synchronous DC-DC Converter Application Schematic Using the RC5051

5
AN53 APPLICATION NOTE

Table 4. RC5051 Application Bill of Materials for Intel Pentium II Processors

Reference Manufacturer’s Part # Quantity Description Requirements/Comments
C1-3, C6-8 6 100nF, 50V Capacitor
C4-5 2 1mF 16V Capacitor
Cext 1 100pF Capacitor 5%, C0G
CIN Sanyo * 1200mF, 10V electrolytic IRMS = 2A
10MV1200GX *See Table 5
COUT Sanyo * 1500mF, 6.3V electrolytic ESR < 44mW
6MV1500GX *See Table 5
D1 Motorola 1 6.2V Zener Diode 5%
1N4735A
D2 Motorola 1 3A Schottky Diode
IN5820
L1 1 2.5mH Inductor DCR < 6mW1
L2 Elytone 1 1.3mH Inductor DCR < 3mW
YT-6542
Q1-2 Fairchild 2 N-channel MOSFET RDS, ON = 20mW @
FDP6030L or FDB6030L VGS = 4.5V2
R1 1 47W 1/10W
R2-3 2 4.7W 1/10W
RSENSE Fairchild 1 CuNi Alloy Wire Resistor *See Table 5
RC10-XX
U1 Fairchild 1 DC/DC Controller
RC5051M
Notes:
1. Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply
with Intel dI/dt requirements. If used, it must be sized to avoid saturation at maximum input current. L1 may be omitted if
desired.
2. For 14.2A designs using the FDP6030L MOSFETs, heatsinks with thermal resistance QSA <20°C/W should be used. For de-
tails and a spreadsheet on MOSFET selections, refer to Applications Bulletin AB-8.

Table 5. Recommended Values for CPU-based Applications

Application Output CIN COUT COUT Maximum RSENSE
Current ESR
300MHz AMD K6 13A 3 x 1200mF, 10V 7 x 1500mF, 6.3V 6.1mW 5.8mW
Motherboard Sanyo Sanyo
10MV1200GX 6MV1500GX
300MHz Intel Pentium II 14.2A 3 x 1200mF, 10V 7 x 1500mF, 6.3V 6.8mW 5.2mW
Klamath Motherboard Sanyo Sanyo
10MV1200GX 6MV1500GX
300MHz Intel Pentium II 12.6A 3 x 1200mF, 10V 7 x 1500mF, 6.3V 5.3mW 5.8mW
Deschutes Motherboard Sanyo Sanyo
10MV1200GX 6MV1500GX

6
APPLICATION NOTE AN53

MOSFET Selection Cosiderations The on-resistance (RDS,ON ) is the primary parameter for
MOSFET selection. It determines the power dissipation
MOSFET Selection within the MOSFET and, therefore, significantly affects the
This application requires N-channel Logic Level Enhance- efficiency of the DC-DC converter. Table 6 is a selection
ment Mode Field Effect Transistors. Desired characteristics table for MOSFETs.
are as follows:

• Low Static Drain-Source On-Resistance, RDS,ON < 40 mW

(lower is better)
• Low gate drive voltage, VGS £ 4.5V
• Power package with low Thermal Resistance
• Drain current rating of 20A minimum
• Drain-Source voltage > 15V.

Table 6. MOSFET Selection Table

Manufacturer RDS, ON (mW) Thermal

and Part # Conditions Typ. Max. Package Resistance (°C/W)
Fairchild VGS = 4.5V, ID = 21A TJ = 25°C 15 20 TO-220 QJA = 62.5
FDP6030L
Fairchild VGS = 4.5V, ID = 21A TJ = 25°C 15 20 D2-PAK QJA = 62.5
FDB6030L
Fairchild VGS = 4.5V, ID = 10A TJ = 25°C 30 36 TO-220 QJA = 62.5
FDP603AL
Fairchild VGS = 4.5V, ID = 10A TJ = 25°C 30 36 D2-PAK QJA = 62.5
FDB603AL
Fairchild VGS = 5V, ID = 40A TJ = 25°C 9 10 TO-220 QJA = 62.5
FDP7030L
Fairchild VGS = 5V, ID = 40A TJ = 25°C 9 10 D2-PAK QJA = 62.5
FDB7030L
IR VGS = 4.5V, ID = 50A TJ = 25°C 10 TO-220 QJA = 62
IRL2203N
IR VGS = 4.5V, ID = 50A TJ = 25°C 10 D2-PAK0 QJA = 40
IRL2203S

7
AN53 APPLICATION NOTE

Two MOSFETs in parallel.

+5V
If output current is high, We recommend two MOSFETs
used in parallel instead of one single MOSFET. The follow- D1
VCCQP
ing significant advantages are realized using two MOSFETs
in parallel: Q1
HIDRV
CP
• Significant reduction of Power dissipation. L2 RS
PWM/PFM VO
Example: RC5051 with Maximum output current of 14A
Control COUT
at 2.8V with one MOSFET on the high side:
LODRV
PMOSFET = (I2 RDS,ON)(Duty Cycle) = Q2
(14A)2 (0.050W)(2.8V / 5V) = 5.5W GNDP D2

With two MOSFETs in parallel: 65-5051-06

2R
Figure 4. Charge Pump Configuration
PMOSFET = (I DS,ON )(Duty Cycle) =
(14A/2)2 (0.037W) (2.8V / 5V) = 1.0W/FET • Method 2. 12V Gate Bias.
*Note: RDS,ON increases with temperature. Assume RDS,ON = Figure 5 illustrates how a 12V source can be used to bias the
25mW at 25°C. RDS, ON can easily increase to 50mW at high tempera- VCCQP. A 47W resistor is used to limit the transient current
ture when using a single MOSFET. When using two MOSFETs in par- into the VCCQP pin and a 1mF capacitor filter is used to filter
allel, the temperature effects should not cause the RDS, ON to rise as
the VCCQP supply. This method provides a higher gate bias
much.
voltage (VGS ) to the MOSFET than the charge-pump method
• Smaller heat sink required. does, and therefore reduces the RDS, ON of the MOSFET and
With power dissipation down to around one watt, thus reduces the power loss due to the MOSFET. Figure 6
considerably less heat sink is required. shows how RDS, ON reduces dramatically with VGS increases.
• Reliability. A 6.2V Zener diode (D1) is placed from VCCQP to 5V to
With thermal management under control, this DC-DC clamp the voltage at VCCQP to a maximum of 12V and
converter is able to deliver load currents up to 14.5A with ensure that the absolute maximum voltage of the IC will not
no performance or reliability concerns. be exceeded.
+5V
• MOSFET Gate Bias. +12V
As already discussed, the low-side MOSFET on the 47½ D1
RC5051 needs only 5V for its gate drive supply. The high-
side MOSFET can be biased by one of two methods: VCCQP
Charge Pump or 12V Gate Bias. Q1
HIDRV
• Method 1. Charge pump (or Bootstrap) method. 1µF
Figure 4 displays the use of a charge pump to provide gate L2 RS
PWM/PFM VO
bias to the high-side MOSFET with the RC5051. Control COUT
Capacitor CP is the charge pump deployed to boost the
voltage of the RC5051 output driver. When the MOSFET LODRV
Q2
switches off, the source of the MOSFET is at D2
GNDP
approximately 0V. VCCQP is charged through the
Schottky diode D1 to approximately 4.5V. Thus, the 65-5051-07

capacitor CP is charged to approximately 4.5V. When the Figure 5. 12V Gate Bias Configuration
MOSFET turns on, the source of the MOSFET voltage is
equal to 5V. The capacitor voltage follows, and hence
provides a voltage at VCCQP equal to approximately 10V.
The Schottky diode D1 is required to provide the charge
path when the MOSFET is off, and reverses bias when the
VCCQP goes to 10V. The charge pump capacitor, CP,
Rds, on (W)

IRL2203NS

needs to be a high Q, high frequency capacitor. A 1mF NDP6030L

FDP7030L
ceramic capacitor is recommended here. NDB603AL

Figure 6. RDS,ON vs. VGS for Selected MOSFETs

8
APPLICATION NOTE AN53

Converter Efficiency • Sense Resistor losses

Losses due to parasitic resistance in the switches, coil, and • Input Capacitor losses
sense resistor dominate at high load-current level. The major • Coil Losses
loss mechanisms under heavy loads, in typical order of • Losses due to the operating supply current of the IC.
importance, are: • Diode-conduction losses
• Gate-charge losses
• MOSFET I 2 R losses
• Transition losses
Formulae for Calculation of Converter Efficiency

P OUT V OUT I OUT

Efficiency = ------------- = -------------------------------------------------
-
p IN V OUT I OUT + P LOSS
P LOSS = P RDS + ( P RISE + P FALL ) + P INDUCTOR + P SENSE + P GATE + P DIODE + P CAPS + P IC
2
P RDS = I OUT R DS,ON DC for the high-side MOSFET
2
P RDS = I OUT R DS,ON ( 1 – DC ) for the low-side MOSFET
V IN I OUT t RISE F S V IN I OUT t FALL F S
- + -------------------------------------------- for the high-side MOSFET
P RISE + P FALL = -----------------------------------------
2 2
V f I OUT t RISE F S V f I OUT t FALL F S
P RISE + P FALL = --------------------------------------- + ---------------------------------------- for the low-side MOSFET
2 2
2
P INDUCTOR = I OUT R INDUCTOR
2
P SENSE = I OUT R SENSE
2
P GATE = CV F S for each MOSFET

P DIODE = I OUT V F T DT F S , with TDT the deadtime

2
P CAPS = ESR ´ I OUT ´ DC ´ ( 1 – DC )

P IC = 25mA* V CC

Example Efficiency Calculation

As an example, the efficiency of a synchronous 14A converter based on the RC5051 will be calculated. The converter produces
2.8V output from a 5V input, switches at 300kHz, has MOSFETs with a 4nF gate capacitance, RDS,on = 10mW for both MOS-
FETS and a rise and fall time of 50nsec. The inductor has a winding resistance of 3mW, and the sense resistor used is 5.2mW. The
schottky paralleled with the synchronous rectifier has a forward voltage of 400mV at 14A. The input capacitors have a total ESR
of 15mW.
2
P RDS = ( 14A ) 10mW = 1.96W

5V ´ 14A ( 50nsec + 50nsec )300kHz

P RISE + P FALL = ------------------------------------------------------------------------------------------- = 1.05W
2
400mV ´ 14A ( 50nsec + 50nsec )300kHz
P RISE + P FALL = ------------------------------------------------------------------------------------------------------ = 84mW
2
2
P INDUCTOR = ( 14A ) 3mW = 590mW

2
P SENSE = ( 14A ) 5.2mW = 1.02W
2
P GATE = 4nF ( 5V ) 300kHz ´ 2 = 60mW
P DIODE = 14A ´ 400mV ´ 50nsec ´ 300kHz = 84mW
2
P CAPS = 15mW ´ ( 14A ) ´ 0.56 ´ ( 1 – 0.56 ) = 724mW

P IC = 25mA ´ 5V ´ 125mW

P LOSS = 1.96W + 1.05W + 0.084W + 0.59W + 1.02W + 0.06W + 0.084W + 0.724W + 0.125W = 5.70W

2.8V ´ 14A
Efficiency = ---------------------------------------------------- = 87%
2.8V ´ 14A + 5.70W

9
AN53 APPLICATION NOTE

When using these formulae, special care must be taken When designing the external current sense circuitry, pay
regarding the MOSFETs’ transition times: the rise and fall careful attention to the output limitations during normal
refer to the MOSFETs’ drain-source voltage, NOT the gate- operation and during a fault condition. If the over-current
source. Using the datasheet values (rather than measured val- protection threshold current is set too low, the DC-DC con-
ues) can also result in serious overestimation of the losses, verter may not be able to continuously deliver the maximum
since the transition is being driven by an inductive source, CPU load current. If the threshold level is too high, the out-
not a resistor. put driver may not be disabled at a safe limit and the result-
ing power dissipation within the MOSFETs may rise to
Selecting the Inductor destructive levels. The following is the design equation used
The inductor is one of the most critical components to be to set the over-current threshold limit:
selected for a DC-DC converter application. The critical param- I RIPPLE
eters of the inductor are its inductance (L), maximum DC cur- I PK = I LOAD, MAX + ------------------
-
2
rent (IO ), and DC coil resistance (Rl ).
Where I pk is defined as in Figure 7, and Iload, max = maximum
The inductor’s inductance helps determine two key parame- output load current. Figure 7 illustrates the inductor current
ters of a converter, its ripple current and its transient waveform for the RC5051 DC-DC converter at maximum load.
response. On the one hand, making the inductance large IPK
reduces the ripple current, and thus the output ripple voltage.
On the other hand, a large inductance provides a slow I
response to load transients. For Pentium II supplies, the tran-
ILOAD, MAX
sient response is paramount, and thus the inductance is typi- IMIN
cally chosen to be in the 1-5mH range.
TON TOFF t

Most inductors’ inductance also depends on current, that is, Ts

65-AP53-04
increasing the current through the inductor decreases the
inductance. It is thus vital to specify the DC current when Figure 7. Typical DC-DC Converter Inductor
procuring an inductor. The one type of inductor which does Current Waveform
not change inductance with current is the rod-core inductor,
but this type may have significant EMI (noise) problems. For The calculation of the ripple current is as follows:
further information, refer to Applications Bulletin AB-12. I RIPPLE V IN – V OUT V OUT
- = ------------------------------T S --------------
------------------
2 2L V IN
The resistance of the winding of the inductor is also impor-
tant, as it is directly responsible for much of the losses in the where:
inductor. Minimizing the resistance will help improve the
converter’s efficiency. VIN = input voltage to converter,

TS = the switching period of the converter = 1/fS, and

Implementing Over-current Protection
Intel currently requires all power supply manufacturers to fS = switching frequency.
provide continuous protection against short circuit condi-
tions that may damage the CPU. To address this requirement, As an example, for an input voltage of 5V, output voltage of
Fairchild Semiconductor has implemented a current sense 2.8V @ 14A, L equal to 1.3mH and a switching frequency of
methodology to limit the power delivered to the load in the 285KHz (using CEXT = 100pF), the peak inductor current can
event of over-current. The voltage drop created by the output be calculated as :
current across a sense resistor is presented to one terminal of
an internal comparator with hysteresis. The other comparator 5V – 2.8V 1 2.8V
I PK = 14A + ------------------------- ´ -------------------- ´ ------------ = 15.7A
terminal has the threshold voltage, nominally of 120mV. 2 ´ 1.3mH 285kHz 5V
Table 7 states the limits for the comparator threshold of the
Switching Regulator. Therefore, the over-current detection threshold must be at
least 16A. The next step is to determine the value of the
Table 7. RC5051 Over-current Comparator sense resistor. Including sense resistor tolerance, the sense
Threshold Voltage resistor value can be determined as
Short Circuit Comparator V th,min
R SENSE = -----------------------------
-
Vthreshold (mV) I SC ( 1 + TF )
Typical 120 Where TF = Tolerance Factor for the sense resistor. Table 8
Minimum 100 describes tolerance, size, power capability, temperature coef-
ficient and cost of various type of sense resistors.
Maximum 140

10
AN53 APPLICATION NOTE

Table 8. Comparison of Sense Resistors

Discrete Metal Discrete
Discrete Iron Strip Surface Discrete MnCu CuNi Alloy
Motherboard Alloy Mount Resistor Alloy Wire Wire Resistor
Description Trace Resistor Resistor (IRC) (Dale) Resistor (Copel)
Tolerance Factor ±20% ±5% ±1% ±10% ±10%
(TF) (±1% available)
Size (L x W x H) 2" x 0.2" x 0.001" 0.45" x 0.065" x 0.25" x 0.125" x 0.200" x 0.04" x 0.200" x 0.04" x
(1 oz Cu trace) 0.200" 0.025" 0.160" 0.100"
Power capability >50A/in 1 watt 1 watt >1 watt >1 watt
(3W and 5W (2W available)
available)
Temperature +3900 ppm +390 ppm ±75 ppm ±50 ppm ±20 ppm
Coefficient
Cost @10,000 Low---included in $0.31 $0.47 $0.09 $0.09
piece motherboard
Continuing with the example, based on the Tolerance Factor Comment on Discrete Sense Resistors
in the above table, for an embedded PC trace resistor and for Discrete Iron Alloy resistors come in a variety of tolerances
ISC set 1A greater than Ipk: and power ratings, and are ideal for precision implementa-
100mV tion, minimizing stress on the MOSFETs. MnCu Alloy wire
R SENSE = ----------------------------------------------------------- = 5.0mW resistors or CuNi Alloy wire resistors are ideal for low cost
( 15.7A + 1A ) ( 1 + 0.20 )
implementations.
For a discrete Cuni resistor:
100mV Designing an Embedded Sense Resistor (PC Trace
R SENSE = ----------------------------------------------------------- = 5.7mW Resistor)
( 15.7A + 1A ) ( 1 + 0.10 )
Embedded PC trace resistors have the advantage of near zero
For user convenience, Table 9 lists the recommended values cost implementation. However, the value of the PC trace
for sense resistors for various load currents using embedded resistance has large variations. To start with, traces on the
trace resistors and discrete resistors and assuming (Ipk- Imin) / outside layers have far more variation than those on inside
2 = 10% IOUT and ISC set 1A greater than Ipk layers; for this reason, embedded resistors should always be
designed on inside layers. Embedded resistors have 3 error
Table 9. Rsense for Various Load Currents sources: the sheet resistivity of the layer, the tolerance of the
RSENSE PC Trace RSENSE Discrete width and length of the trace, and the temperature variation
ILoad,max (A) Resistor (mW) Resistor (mW) of the copper. Only two of the error sources must be consid-
ered for laying out embedded sense resistors.
6.9 9.7 10.6
7.8 8.7 9.5 • Sheet resistivity.
8.5 8.1 8.8 For 1 ounce copper, the thickness is nominally 1.3mils,
8.7 7.9 8.6 and the toleranace is typically ±.1 mil. Therefore error due
to sheet resistivity is 0.1 mil / 1.3mil = +/-8%
9.6 7.2 7.9
10.6 6.6 7.2 • Tolerance of width and length.
The width and length of traces also have tolerances;
11.1 6.3 6.9 typical numbers might be ±3/4 mil. A typical width to
12.6 5.6 6.1 obtain a 5.2mW resistor might be 300mils, and so the
14.2 5.0 5.5 length would have to be:
17.2 4.2 4.6 t´w´R 1.3mil ´ 300mil ´ 5.2mW
L = ---------------------- = ---------------------------------------------------------------- = 2996mils
r 6.77 ´ 10 W – mil
–4
18.5 3.9 4.3
18.9 3.8 4.2 or 3 inches. The tolerance is thus negligible.

11
AN53 APPLICATION NOTE

• Thermal Consideration. Refer to Figure 8.

Due to I2R power losses the temperature of the resistor will 1 Each
increase, leading to a higher resistance value. In addition, W = 300 mils
ambient temperature variation will add to the change in
resistor value: L = 3000mils
T – 20
R = R 20C ´ 1.00393 65-AP53-05

Figure 8. 5.20mW Sense Resistor (10 ■ )

where: R20C is the resistance at 20°C, T is the trace’s
temperature, and R is the actual resistance. For example,
You can also implement the sense resistor in the following
for temperature T = 50°C, the %R change = 12%. Table
manner. Each corner square is counted as 0.6 square since
10 is the summary of the tolerance for the Embedded PC
current flowing through the corner square does not flow
Trace Resistor.
uniformly and it is concentrated towards the inside edge,
as shown in Figure 9.
Table 10. Summary PC Trace Resistor
Tolerance 1 Each

Tolerance due to Sheet Resistivity variation 8% .6 .6

Tolerance due to temperature variation 12%

.8 65-AP53-06
Total Tolerance for PC Trace Resistor 20%

Figure 9. 5.30mW Sense Resistor (10 ■)

Design Rules for Using an Embedded Resistor
The basic equation for the resistance of an embedded A Design Example Combining an Embedded Resistor
resistor is: and a Discrete Resistor
L For low cost implementation, the embedded PC trace resistor
R = r ´ -------------
W´t is most desirable. However, its wide tolerance (20%) can
present a problem. In addition, requirements for the CPU
where: change frequently, and, thus, the maximum load current may
r = Resistivity(mW-mil), be subject to change. Combining embedded resistors with
L = Length(mils), discrete resistors may be a desirable option. Figure 10 shows
W = Width(mils), and a design that provides flexibility with a solution to address
t = Thickness(mils). wide tolerances. In this design, you have the option to
choose an embedded or a discrete sense resistor. To use the
For 1oz copper, t = 1.3 mils, r = 677mW-mil, discrete sense resistor, populate R21 with a shorting bar
1 L/1 W = 1 Square ( ■ ). (zero Ohm resistor) for proper Kelvin connection and add
For example, you can layout a 5.20mW embedded sense the MnCu sense resistor. To use the embedded sense resistor,
resistor using the example above on the other hand, populate R22 with a shorting bar for
Kelvin connection. The embedded sense resistor allows the
L/W = 300mils user to choose a plus or a minus delta resistance tap to offset
any large sheet resistivity change. In this design, the center
RWt 0.0052 ´ 300 ´ 1.3 tap yields 6mW, the left tap yields 6.8mW, and the right tap
L = ------------ = --------------------------------------------- = 3000mils
r 677 yields 5.3mW.
L/W = 10 ■

IFB

MnCu Discrete
R21 R22
Resistor
VFB
Output Power

Plane (Vout)
R-Dr
R
R+Dr

65-AP53-07

Figure 10. Short Circuit Sense Resistor Design Using a PC Trace Resistor and an Optional Discrete Sense Resistor

12
APPLICATION NOTE AN53

RC5051 over-current Characteristics These calculations show that the high-side MOSFET is not
The RC5051 over-current characteristic includes a hysteresis being over-stressed during an over-current condition.
function that prevents the DC-DC converter from oscillating
in the event of an over-current. Figure 11 shows the typical
characteristic of the DC-DC converter circuit with a 6mW
sense resistor. The converter exhibits a normal load regula-
tion characteristic until the voltage across the resistor
exceeds the internal over-current threshold of 120mV. At this
point, the internal comparator trips and signals the controller
to reduce the duty cycle of the high-side MOSFET. This
causes a drastic reduction in output voltage as the load
regulation collapses into the over-current control mode.
The output voltage does not return to its nominal value until
the output current is reduced to a value within the safe range
for the DC-DC converter.
Output Voltage vs. Output Current
RSENSE = 6m½
3.5

3.0
Figure 12A. HIDRV Output Waveform for Normal
2.5 Operation Condition with Vout = 2.8V@10A
OUT (V)

2.0

1.5
1.0
65-5051-08

0.5
0
0 5 10 15 20 25
Output Current (A)

Figure 11. RC5051 Over-current Characteristic

Power Dissipation Consideration During an

Over-current Condition
The RC5051 controller responds to an output over-current by
drastically reducing the duty cycle of the gate drive signal to
the high-side MOSFET. In doing this, the high-side MOS-
FET is protected from stress and from eventual failure. Fig- Figure 12B. HIDRV Output Waveform for
ure 12A shows the gate drive signal of a typical RC5051 Over-current Condition
operating in continuous mode with a load current of 10A.
The duty cycle is set by the ratio of the input voltage to the Power dissipation in the low-side MOSFET during an over-
output voltage. If the input voltage is 5V, and the output volt- current condition must also be considered. The low-side
age is 2.8V, the ratio of Vout/ Vin is 56% (64% measured). MOSFET dissipates power while the high-side MOSFET is
Figure 12B shows the result of a RC5051 going into its over- off. The power dissipated in the low-side MOSFET during
current mode with a duty cycle of approximately 47%. Cal- normal operation, is given by:
culating the power in each MOSFET at each condition on the
graph (Figure 11) shows how the protection works. The = 2 2
I ´ R RDS, ON ´ ( 1 – DC ) = ( 14.2 ) ´ .01 ´ .36 = 0.73
power dissipated in the high-side MOSFET at normal opera-
tion for a load current of 14.2A, is given by: During an over-current , the duty cycle reduces to around
47%. The power dissipated in the low-side MOSFET during
PD = 2 2
I ´ R DS, ON ´ DC = ( 14.2 ) ´ .01 ´ .64 = 1.29W
short circuit condition, is given by:
ignoring switching losses. 2
P D = ( 20 ) ´ .01 ´ .53 = 2.1W
The power dissipated in the MOSFET at an over-current
condition of 20A, is given by: Thus, for the low-side MOSFET, the thermal dissipation dur-
ing over-current is greatly magnified. This requires that the
2
P D = ( 20 ) ´ .01 ´ .47 = 1.88W thermal dissipation of the low-side MOSFET be properly
managed by an appropriate heat sink. To protect the low-side
again ignoring switching losses. MOSFET from being destroyed in the event of an over-cur-

13
AN53 APPLICATION NOTE

rent , you should limit the junction temperature to less than the total ESR of the capacitors used and the parasitic resis-
130°C. You can find the required thermal resistance using the tance of the output traces. For a detailed analysis of capacitor
equation for maximum junction temperature: requirements in a high-end microprocessor system, please
refer to Application Bulletin 14.
T J ( max ) – T A
P D = -------------------------------
R QJA Input Filter
Assuming that the ambient temperature is 50°C, The DC-DC converter may include an input inductor
between the system +5V supply and the converter input
T J ( max ) – T A 130 – 50 as described below. This inductor serves to isolate the +5V
R QJA = ------------------------------- = --------------------- = 38°C ¤ W
PD 2.1 supply from the noise in the switching portion of the DC-DC
converter, and to limit the inrush current into the input capac-
Thus, you need to provide a heat sink that gives the low-side itors during power up. A value of 2.5mH is typical, as illus-
MOSFET a thermal resistance of 38°C/W or lower to protect trated in Figure 13; details on selection of an input inductor
the device during an indefinite short. may be found in Applications Bulletin AB-16.

In summary, with proper heat sink, the low-side MOSFET is The number of input capacitors required for a converter is
not over-stressed during an over-current condition. determined by the capacitors’ ripple current rating. The
ripple current is given by:
Schottky Diode Selection
2
The application circuit diagram of Figure 3 shows a Schottky I rms = I OUT DC – DC
diode, D2. D2 is used as a flyback diode to provide a current
path for the inductor current during the dead-time when both Thus, for example, a Deschutes processor running at 2.0V
the high-side and low-side MOSFETs are briefly both turned out from 5.0V in has a DC = 2.0/5.0 = .4; if it pulls 14.2A, its
off. Table 11 shows the characteristics of several Schottky Irms = 7A.
diodes. Note that MBRB2515L has a very low
forward voltage drop even at high current. Although it is not Table 12 shows some typical input capacitors’ current rat-
necessary to use a high-current diode for this application, ings; the current rating increases as temperature decreases.
selecting a higher current schottky will provide improved Although exceeding these ratings will not cause capacitor
efficiency at slightly higher cost. damage, it will reduce their life, and thus the converter’s
MTBF.
Table 11. Schottky Diode Selection Table
5V Vin
Manufacturer Forward
Model # Conditions Voltage VF 1000µF, 10V
0.1µF
Motorola IF = 1A; Tj = 25°C <.45v Electrolytic
1N5817
Motorola IF = 3A; Tj = 25°C <.475v 65-5051-09
1N5820
Motorola IF = 20A; Tj = 25°C < 0.58v
Figure 13. Typical Input Filter
MBR2015CTL IF = 20A;Tj = 150°C < 0.48v
Motorola IF = 19A; Tj = 70°C < 0.28v Table 12. Input Capacitor Selection Guide
MBRB2515L
Manufacturer Part # Irms
Output Filter Capacitors Sanyo 10MV1200GX 2.0A @
65°C
Correct calculation of the output capacitance is crucial to the
performance of the DC-DC converter. The output capacitor United LXZ10VB122M10X20 1.2A @
determines the overall loop stability, output voltage ripple, Chemicon 105°C
and, most importantly, load transient response. Because the Panasonic EEUFA10122 1.2A @
control loop response of the controller is not instantaneous, 105°C
the initial load transient must be supplied entirely by the out-
put capacitors. The initial voltage deviation is determined by

14
AN53 APPLICATION NOTE

Q1 Q2

Good layout Problem layout

11 RC505 10
12 9
13 8
14 7
15 6
16 5
17 4
18 3
19 2
20 1

Q2
= “Quiet" Pins
Q1

65-AP53-08

Figure 14. Placement of the MOSFETs

PCB Layout Guidelines and capacitor for further noise isolation to provide additional
Considerations shielding to the oscillator pin 1 from the noise on the PCB.
In addition, place this capacitor as close to the RC5051
PCB Layout Guidelines pin 1 as possible.
• Place the MOSFETs, inductor and Schottky as close
• Placement of the MOSFETs relative to the RC5051 is
together as possible for the same reasons as on the first
critical. Place the MOSFETs (Q1 & Q2) so that the trace
bullet above. Place the input bulk capacitors as close to the
length from the RC5051 HIDRV and LODRV pins to the
drains of MOSFETs as possible. In addition, placement of
FET gates is minimized. A long lead length on this pin
a 0.1mF decoupling capacitor right on the drain of each
would cause high amounts of ringing due to the
MOSFET helps to suppress some of the high frequency
inductance of the trace and the large gate capacitance of
switching noise on the input of the DC-DC converter.
the FET. This noise radiates all throughout the board, and,
• Place the output bulk capacitors as close to the CPU as
because it is switching at such a high voltage and
possible to optimize their ability to supply instantaneous
frequency, it is very difficult to suppress.
current to the load in the event of a current transient.
Additional space between the output capacitors and the
Figure 14 shows an example of good placement for the
CPU allows the parasitic resistance of the board traces to
MOSFETs in relation to the RC5051. In addition, this
degrade the DC-DC converter’s performance under load
figure shows an example of problematic placement for the
transient conditions, causing higher voltage deviation. For
MOSFETs.
more detailed information regarding capacitor placement,
refer to Application Bulletin AB-5.
In general, all of the noisy switching lines should be kept
• The traces that run from the RC5051 IFB (pin 4) and VFB
away from the quiet analog section of the RC5051. That is,
(pin 5) pins should be run next to each other and Kelvin
traces that connect to pins 9, 12 and 13 (LODRV, HIDRV
connected to the sense resistor. Running these lines
and VCCQP) should be kept far away from the traces that
together prevents some of the common mode noise that is
connect to pins 1, 2, 4 and 5, and pin 16.
presented to the RC5051 feedback input. Try, as much as
possible, to run the noisy switching signals (LODRV,
• Place the 0.1mF decoupling capacitors as close to the
HIDRV & VCCQP) on one layer, but use the inner layers
RC5051 pins as possible. Extra lead length degrades their
for power and ground only. If the top layer is being used to
ability to suppress noise.
route all of the noisy switching signals, use the bottom
• Each VCC and GND pin should have its own via to the
layer to route the analog sensing signals VFB and IFB.
appropriate plane. This helps to provide isolation between
pins.
• Surround the CEXT timing capacitor with a ground trace.
Be sure to place a ground or power plane under the

15
AN53 APPLICATION NOTE

Example of a PC Motherboard Layout and 7. Next check the oscillator pin. You should see a saw tooth
Gerber File. wave at the frequency set by the external capacitor.
This section shows a reference design for motherboard
8. When the VREF and CEXT pins are checked and
implementation of the RC5051 along with the Layout Gerber
correct and the output voltage is incorrect, look at the
File and Silk Screen. The actual PCAD Gerber File can be
waveform at VCCQP. This pin should be +12V (in the
obtained from Fairchild Semiconductor local Sales Office .
+12V application), and should be swinging from
slightly below +5V to about +10V (in the charge pump
Guidelines for Debugging and application). If the VCCQP pin is noisy, with ripples/
Performance Evaluations over-shoots riding on it this may make the converter
function incorrectly.
Debugging Your First Design Implementation
9. Next, look at HIDRV pin. This pin directly drives the
1. Note the setting of the VID pins to know what voltage is
gate of the high-side FET. It should provide a gate drive
to be expected.
(measured gate to ground) of about 10V when turning
2. Do not connect any load to the circuit. While monitoring the FET on. A careful study of the layout is recom-
the output voltage, apply power to the circuit with cur- mended. Refer to the “PCB Layout Guidelines” section.
rent limiting at the power source. This ensures that no
10. Past experience shows that the most frequent errors are
catastrophic shorts are present.
incorrect components, improper connections, and poor
3. If proper voltage is not achieved go to “Procedures” layout.
below.
Performance Evaluation
4. When you have proper voltage, increase the current This section shows sample evaluation results as a reference
limiting of the power source to 16A. guide for evaluating a DC-DC Converter using the RC5051
on a Pentium II motherboard.
5. Apply load in 1A increments. An active load (HP6060B
or equivalent) is suggested. DC Regulation
6. In case of poor regulation refer to “Procedures” below. VID(2.0V)
43210 Iload (A) Vout (V)
Procedures 2.0V 00001 0.5 2.019
1. If there is no voltage at the output and the circuit is not 1 2.018
drawing current look for opens in the connections,
check the circuitry versus schematic, and check the 2 2.017
power supply pins of the RC5051 to make sure that volt- 3 2.016
age(s) are applied. 4 2.014
2. If there is no voltage at the output and the circuit is 5 2.013
drawing excessive current (>100mA) with no load, 6 2.012
check for possible shorts. Determine the path of the
7 2.010
excessive current and which device is drawing it–this
current may be drawn by peripheral components. 8 2.009
9 2.007
3. If the output voltage comes close to the expected value,
check the VID inputs at the device pins. The part is fac- 10 2.006
tory set to respond properly to the VID inputs. 11 2.005

4. Shut down at too low a current can be caused by an 12 2.004

inappropriate value of the sense resistor. See the “Sense 13 2.003
Resistor” section. 14 2.001
5. Poor load regulation can be due to many causes. Check 14.5 2.001
the voltages and signals at the critical pins. Load Regulation 0.5-14.5A 0.90%

6. The VREF pin should be at the voltage set by the VID

pins. If the power supply pins and the VID pins are cor-
rect the VREF should have the correct voltage.

16
APPLICATION NOTE AN53

The DC output voltage is measured from minimum to maxi-

mum load current. Ideally, the RC5051 should show about
20mV droop between these two limits. Note that the mea-
surement must be taken directly on the leads of the output
capacitors, since there may otherwise be parasitic resistances
causing additional droop.

Output voltage load transients due to load

current step
Test
Condition Measured Comment
Low to high 0.5A-14.5A 96mV Limit =
Current Step 130mV
(Vout = PASS
2.00V) Figure 15
High to Low 14.5A-0.5A 109mV Limit =
Current Step 130mV
(Vout = PASS Figure 16. High to Low Current Transiet Response
2.00V) Figure 16
The output voltage transient response to the worst-case step
current load is measured using an Intel EMT tool. Again, the
measurement must be taken directly on the leads of the out-
put capacitors, since there may otherwise be parasitic resis-
tances and inductances causing additional droop.

Over-Current Limit
Using an electronic load, the output current should be slowly
increased until the converter hits over-current limit. Reach-
ing this limit will be evident because the output voltage
quickly drops out of regulation as the current is increased.

Component Case Temperature

Each of the major components should be measured for
excessive temperature, which can be indicative of a problem.
At the least, the RC5051, the MOSFETs and the schottky
diode should all be measured. The converter should be run at
its maximum load current until it reaches thermal stability, at
Figure 15. Low to High Current Transiet Response least 20 minutes, before the temperature measurements are
taken.

17
AN53 APPLICATION NOTE

Notes

18
APPLICATION NOTE AN53

Notes

19
AN53 APPLICATION NOTE

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support
which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be
or (b) support or sustain life, and (c) whose failure to reasonably expected to cause the failure of the life support
perform when properly used in accordance with device or system, or to affect its safety or effectiveness.
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.

www.fairchildsemi.com

7/21/98 0.0m 001

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