Analog Engineer's Circuit: Data

Converters
SBAA374 – June 2019

Noninverting circuit for high-to-low voltage level

translation to drive ADC

Art Kay

Input ADC Input Digital Output ADS8860

–10V 0.2V 0A3DH or 2621d
10V 4.8V F5C3H or 62915d

Power Supplies
Vref AVDD DVDD
5V 3.0V 3.0V

Design Description
This circuit document describes how to translate a high-voltage signal (for example, ±10V) to a low
voltage ADC input (for example, 0V to 5V). This circuit does not require any high-voltage supply to
operate, but rather uses a voltage divider and level shift to translate the input signal. This circuit shows the
OPA320 op amp and ADS8860 SAR ADC, but the topology could be applied to many different ADCs. This
design can be used in a wide range of applications where a high-voltage input needs to be translated such
as analog input modules for PLCs, lab instrumentation, and factory automation.

Vref
5V
5V +3.0V

Ra - Rflt1 24.9Ÿ REF AVDD DVDD

10kŸ AINP
+
OPA320 Cfilt ADS8860
+ 1.1nF
Rc
Vin Rb AINN
8.56kŸ 4.59kŸ GND
Rflt1 24.9Ÿ
Vref
5V

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Specifications

Specification Goal Calculated Simulated

Bandwidth > 1MHz 2.9MHz 4.06MHz
Noise < 1/2LSB = 38.1µV 23.56µVRMS 21.04NµVRMS
Transient settling error < 1/2 LSB = 38.1µV 35µV

Design Notes
1. Select a C0G type capacitor for Cfilt to minimize distortion.
2. Use 0.1% 20ppm/°C film resistors or better to minimize gain error and drift.
3. The input impedance of this circuit is Rin = Ra + Rb||Rc. For a high-impedance input, use a high-voltage
amplifier buffer (for example, Vcc = +15V and Vee = –15V). Alternatively, increase the input
impedance by multiplying Ra, Rb, and Rc by the same factor. However, increasing the resistance on all
the resistors will impact the system noise.

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Component Selection
1. The first step is to select the amplifier input and output range. In this example, the input range is –10V
to +10V. The amplifier output range is set according to the ADC input and the amplifier linear output
range. The ADC input range in this example is set by the reference voltage and is 5V. The amplifier
supply is set to 5V to match the ADC input range. The output of the amplifier cannot swing to the
power supply rails because of output swing limitations (that is, linear range for OPA320 0.1V < VOUT <
4.9V). For this example, an output swing of 0.2V to 4.8V is selected for the input signal of –10V to 10V.
The output range could have been set as 0.1V to 4.9V to match the linear range, but in this example
design margin is added to account for power supply variation.
2. Use the Analog Engineer's Calculator in the next step to select component values. Enter the input and
output voltages and reference voltage (–10V < VIN < +10V, and 0.2V < VOUT < 4.8V). The range of
acceptable reference voltages is given at the bottom of the tool (3.35V to 12V, in this example). A
reference of 5V is selected as this reference voltage is available elsewhere in the circuit. The tool
outputs the 0.1% resistors required to map the voltages (Ra = 10kΩ, Rb = 8.56kΩ, Rc = 4.59kΩ).

3. The following equations show the transfer function for the non-inverting level-shift topology. It is
possible to use these equations to solve for the different component values rather than the calculator.
To do this, choose a reference value and fix the value of Ra to 10kΩ. Once this is done, solve for Rb
and Rc for two different values of output signal. The algebra for this problem is a little complex, so the
calculator is the suggested method. Use the equations to verify the transfer function as the equation
following shows.
(R b || R c ) (R a || R b )
VO = × VIN + × Vref
R a + (R b || R c ) R c + (R a || R b )

where
R b ×R c R a ×R b
R b || R c = and R a || R b =
Rb +Rc Rb +Rc

Using the values from the calculator:

Ra = 10kΩ, Rb = 8.56kΩ, Rc = 4.59kΩ
VO = 0.23005V • VIN + 2.506V
VO(–10V) = 0.2055V
VO(+10V) = 4.8065V
4. Find Rfilt and Cfilt to allow for settling at 1Msps. The Refine the Rfilt and Cfilt Values video from the TI
Precision Labs - ADCs video series shows the algorithm for selecting Rfilt and Cfilt. The final value of
24.9Ω and 1.1nF proved to settle to well below ½ of a least significant bit (LSB).

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DC Transfer Characteristics
The following graph shows the linear output response for a –10-V to 10-V input. In this case, the amplifier
output is approximately 0.2V for a –10-V input and 4.8V for a +10-V input. This design was scaled so that
the output range avoids the nonlinear power supply rails by 0.2V. See the TI Precision Labs - ADCs
Determining a SAR ADC's Linear Range when using Operational Amplifiers video for detailed theory on
this subject.
5.00

3.75 VIN = 10.0V

Voltage (V)

VOUT = 4.8065V

2.50
VIN = í10.0V
VOUT = 0.2055V
1.25

0.00
-15.0 -10.0 -5.0 0.0 5.0 10.0 15.0
Input Voltage (V)
AC Transfer Characteristics
The bandwidth is limited by the RC charge bucket circuit. The calculated and simulated bandwidth
compare well (calculated fc = 2.9MHz, simulated fc = 4.06MHz). The small discrepancy in the bandwidth is
due to gain peaking on the OPA320 device. See the Op Amps Bandwidth video series for more details on
this subject.
1
fc = = 2.9 MHz
2 p × (2 × 24.9 W ) × (1.1nF)

-12.76
Gain (dB)

fc = 4.06MHz
-48.73

-84.69
0
Phase [deg]

-90
-180
-270
-360
10 100 1k 10k 100k 1M 10M 100M
Frequency (Hz)

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Transient ADC Input Settling Simulation

The following simulation shows settling to a +10-V DC input signal. This type of simulation shows that the
sample and hold kickback circuit is properly selected. See the Final SAR ADC Drive Simulations for
detailed theory on this subject.
1.00
Vacq

0.00
100u
Verror = 35 V
Verror 0

-100u
1.00u 1.50u 2.00u
Time (s)
Noise Simulation
The following noise calculation takes into account the thermal noise of the resistor network, the amplifier
noise, and the bandwidth limit from the RC filter. The calculated total noise is 23.5µVRMS and the simulated
total noise is 21.04µVRMS. See the Op Amp Noise Calculation video for detailed theory on amplifier noise
calculations, and the Calculating the Total Noise for ADC Systems video for data converter noise.
Noise equivalent input resistor network:
1 1
R eq = = = 2.3 k W
1 1 1 1 1 1
+ + + +
R a Rb R c 10 k W 8.56 k W 4.59 k W

Resistor network noise:

nV
e n Re q = 4 kTR = 4 × (1.381 × 10 - 23 ) × (273 + 25) × 2.3 k W = 6.164
Hz
OPS320 noise density:
nV
e nOPA 320 = 7
Hz
Total noise:
2 2
enTOT = enOPA320 + enRe q × K n × fc

2 2
æ nV ö æ nV ö
enTOT = ç 7 ÷ + ç 6.164 ÷ × 1.57 × 4.06MHz = 23.56 mVRMS
è Hz ø è Hz ø

21.04u
Total Noise (V)

10.52u

0.00
100 1k 10k 100k 1M 10M 100M
Frequency (Hz)

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Design Featured Devices and Alternative Parts

Device Key Features Link Other Possible Devices

ADS8860 16-bit resolution, SPI, 1-Msps sample rate, single-ended input, Vref http://www.ti.com/product/ADS8860 http://www.ti.com/adcs
input range 2.5V to 5.0V.
OPA320 20-MHz bandwidth, rail-to-rail with zero crossover distortion, http://www.ti.com/product/OPA320 http://www.ti.com/opamps
VOS(MAX) = 150μV, VOS(DriftMAX) = 5μV/°C, en = 7nV/√Hz

Link to Key Files

TINA source files – http://www.ti.com/lit/zip/SBAC250.
Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.

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