Adsp-21483 21486 21487 21488 21489

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SHARC Processor

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
FEATURES
High performance 32-bit/40-bit floating-point processor The ADSP-2148x processors are available with unique audio-
optimized for high performance audio processing centric peripherals, such as the digital applications
Single-instruction, multiple-data (SIMD) computational interface, serial ports, precision clock generators, S/PDIF
architecture transceiver, asynchronous sample rate converters, input
On-chip memory—5 Mbits on-chip RAM, 4 Mbits on-chip data port, and more
ROM For complete ordering information, see Ordering Guide
Up to 450 MHz operating frequency AEC-Q100 qualified for automotive applications
Code compatible with all other members of the SHARC family

Internal Memory

SIMD Core Block 0 Block 1 Block 2 Block 3


RAM/ROM RAM/ROM RAM RAM
Instruction 5 Stage
Cache Sequencer
S B0D B1D B2D B3D
Core 64-BIT 64-BIT 64-BIT 64-BIT
DAG1/2 Timer
DMD DMD
64-BIT 64-BIT
PEx PEy Core Bus Internal Memory I/F
Cross Bar
PMD PMD 64-BIT
64-BIT
FLAGx/IRQx/ THERMAL EPD BUS 64-BIT IOD0 32-BIT
JTAG
TMREXP DIODE PERIPHERAL BUS
32-BIT
IOD1
32-BIT

IOD0 BUS FFT


DTCP/
FIR
MTM
IIR
PERIPHERAL BUS
EP
SPEP BUS
CORE
PCG TIMER S/PDIF PCG ASRC PDAP/ SPORT CORE PWM SDRAM
FLAGS/ TWI SPI/B UART IDP WDT AMI
C-D 1-0 Tx/Rx A-D 3-0 7-0 FLAGS 3-0 CTL
PWM3-1 7-0

DPI Routing/Pins DAI Routing/Pins External Port Pin MUX

External
DPI Peripherals DAI Peripherals Peripherals Port

Figure 1. Functional Block Diagram

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. I Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication One Analog Way, Wilmington, MA 01887 U.S.A.
or otherwise under any patent or patent rights of Analog Devices. Trademarks and ©2024 Analog Devices, Inc. All rights reserved.
registered trademarks are the property of their respective companies. Technical Support www.analog.com
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
TABLE OF CONTENTS
Features ................................................................. 1 ESD Sensitivity ................................................... 22
Table of Contents ..................................................... 2 Maximum Power Dissipation ................................. 22
Revision History ...................................................... 2 Timing Specifications ........................................... 23
General Description ................................................. 3 Output Drive Currents ......................................... 56
Family Core Architecture ........................................ 4 Test Conditions .................................................. 56
Family Peripheral Architecture ................................ 8 Capacitive Loading .............................................. 56
I/O Processor Features ......................................... 11 Thermal Characteristics ........................................ 57
System Design .................................................... 12 88-Lead LFCSP_VQ Lead Assignment ......................... 59
Development Tools ............................................. 13 100-Lead LQFP_EP Lead Assignment ......................... 61
Additional Information ........................................ 14 176-Lead LQFP_EP Lead Assignment ......................... 63
Related Signal Chains .......................................... 14 Outline Dimensions ................................................ 67
Pin Function Descriptions ....................................... 15 Surface-Mount Design .......................................... 68
Specifications ........................................................ 19 Automotive Products .............................................. 69
Operating Conditions .......................................... 19 Ordering Guide ..................................................... 70
Electrical Characteristics ....................................... 20
Absolute Maximum Ratings .................................. 22

REVISION HISTORY
2/2024—Rev. H to Rev. I
Added Table 3, Internal Memory Space (2 MBits—ADSP-21488
Automotive Products Only) ........................................6
Removed obsolete models AD21487WBSWZ4Axx and
AD21487WBSWZ4Bxx in Automotive Products ............ 69

Rev. I | Page 2 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
GENERAL DESCRIPTION
The ADSP-2148x SHARC® processors are members of the Table 1. Processor Benchmarks
SIMD SHARC family of DSPs that feature Analog Devices’
Super Harvard Architecture. The processors are source code Speed Speed
compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x, Benchmark Algorithm (at 400 MHz) (at 450 MHz)
ADSP-2146x, ADSP-2147x and ADSP-2116x DSPs, as well as 1024 Point Complex FFT 23 μs 20.44 μs
with first generation ADSP-2106x SHARC processors in SISD (Radix 4, with Reversal)
(single-instruction, single-data) mode. The ADSP-2148x pro- FIR Filter (per Tap)1 1.25 ns 1.1 ns
cessors are 32-bit/40-bit floating point processors optimized for IIR Filter (per Biquad)1 5 ns 4.43 ns
high performance audio applications with large on-chip SRAM,
Matrix Multiply (Pipelined)
multiple internal buses to eliminate I/O bottlenecks, and an
[3 × 3] × [3 × 1] 11.25 ns 10.0 ns
innovative digital applications interface (DAI).
[4 × 4] × [4 × 1] 20 ns 17.78 ns
Table 1 shows performance benchmarks for the ADSP-2148x Divide (y/×) 7.5 ns 6.67 ns
processors. Table 2 shows the features of the individual product
offerings. Inverse Square Root 11.25 ns 10.0 ns
1
Assumes two files in multichannel SIMD mode

Table 2. ADSP-2148x Family Features

Feature ADSP-21483 ADSP-21486 ADSP-21487 ADSP-21488 ADSP-21489


Maximum Instruction Rate 400 MHz 400 MHz 450 MHz 400 MHz 450 MHz
RAM 3 Mbits 5 Mbits 2/3 Mbits1 5 Mbits
ROM 4 Mbits No
Audio Decoders in ROM2 Yes No
Pulse-Width Modulation 4 Units (3 Units on 100-Lead Packages)
DTCP Hardware Accelerator Contact Analog Devices
External Port Interface (SDRAM, AMI)3 Yes (16-bit) AMI Only Yes (16-bit)
Serial Ports 8
Direct DMA from SPORTs to Yes
External Port (External Memory)
FIR, IIR, FFT Accelerator Yes
Watchdog Timer Yes (176-Lead Package Only)
MediaLB Interface Automotive Models Only
IDP/PDAP Yes
UART 1
DAI (SRU)/DPI (SRU2) Yes
S/PDIF Transceiver Yes
SPI Yes
TWI 1
SRC Performance4 –128 dB
Thermal Diode Yes
VISA Support Yes
Package3 176-Lead LQFP EPAD 176-Lead LQFP EPAD 176-Lead LQFP EPAD 176-Lead LQFP EPAD
100-Lead LQFP EPAD 88-Lead LFCSP5 100-Lead LQFP EPAD 100-Lead LQFP EPAD5
88-Lead LFCSP5 88-Lead LFCSP5
1
See Ordering Guide.
2
ROM is factory programmed with latest multichannel audio decoding and post-processing algorithms from Dolby® Labs and DTS®. Decoder/post-processor algorithm
combination support varies depending upon the chip version and the system configurations. Visit www.analog.com for complete information.
3
The 100-lead and 88-lead packages do not contain an external port. The SDRAM controller pins must be disabled when using this package. For more information, see Pin
Function Descriptions. The ADSP-21486 processor in the 176-lead package also does not contain a SDRAM controller. For more information, see 176-Lead LQFP_EP Lead
Assignment.
4
Some models have –140 dB performance. For more information, see Ordering Guide.
5
Only available up to 400 MHz. See Ordering Guide for details.

Rev. I | Page 3 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
The diagram on Page 1 shows the two clock domains that make SIMD Computational Engine
up the ADSP-2148x processors. The core clock domain contains
The ADSP-2148x contains two computational processing ele-
the following features:
ments that operate as a single-instruction, multiple-data
• Two processing elements (PEx, PEy), each of which com- (SIMD) engine. The processing elements are referred to as PEX
prises an ALU, multiplier, shifter, and data register file and PEY and each contains an ALU, multiplier, shifter, and reg-
• Data address generators (DAG1, DAG2) ister file. PEx is always active, and PEy may be enabled by
setting the PEYEN mode bit in the MODE1 register. SIMD
• Program sequencer with instruction cache mode allows the processor to execute the same instruction in
• PM and DM buses capable of supporting 2x64-bit data both processing elements, but each processing element operates
transfers between memory and the core at every core pro- on different data. This architecture is efficient at executing math
cessor cycle intensive DSP algorithms.
• One periodic interval timer with pinout SIMD mode also affects the way data is transferred between
• On-chip SRAM (5 Mbit) and mask-programmable ROM memory and the processing elements because twice the data
(4 Mbit) bandwidth is required to sustain computational operation in the
processing elements. Therefore, entering SIMD mode also dou-
• JTAG test access port for emulation and boundary scan. bles the bandwidth between memory and the processing
The JTAG provides software debug through user break- elements. When using the DAGs to transfer data in SIMD
points which allows flexible exception handling. mode, two data values are transferred with each memory or reg-
The block diagram of the ADSP-2148x on Page 1 also shows the ister file access.
peripheral clock domain (also known as the I/O processor)
which contains the following features: Independent, Parallel Computation Units
• IOD0 (peripheral DMA) and IOD1 (external port DMA) Within each processing element is a set of computational units.
buses for 32-bit data transfers The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera-
• Peripheral and external port buses for core connection tions in a single cycle and are arranged in parallel, maximizing
• External port with an AMI and SDRAM controller computational throughput. Single multifunction instructions
execute parallel ALU and multiplier operations. In SIMD mode,
• 4 units for PWM control
the parallel ALU and multiplier operations occur in both pro-
• 1 memory-to-memory (MTM) unit for internal-to-internal cessing elements. These computation units support IEEE 32-bit
memory transfers single-precision floating-point, 40-bit extended precision float-
• Digital applications interface that includes four precision ing-point, and 32-bit fixed-point data formats.
clock generators (PCG), an input data port (IDP/PDAP)
Timer
for serial and parallel interconnects, an S/PDIF
receiver/transmitter, four asynchronous sample rate con- The processor contains a core timer that can generate periodic
verters, eight serial ports, and a flexible signal routing unit software interrupts. The core timer can be configured to use
(DAI SRU). FLAG3 as a timer expired signal.
• Digital peripheral interface that includes two timers, a Data Register File
2-wire interface (TWI), one UART, two serial peripheral
interfaces (SPI), 2 precision clock generators (PCG), pulse Each processing element contains a general-purpose data regis-
width modulation (PWM), and a flexible signal routing ter file. The register files transfer data between the computation
unit (DPI SRU2). units and the data buses, and store intermediate results. These
10-port, 32-register (16 primary, 16 secondary) register files,
As shown in the SHARC core block diagram on Page 5, the combined with the processor’s enhanced Harvard architecture,
processor uses two computational units to deliver a significant allow unconstrained data flow between computation units and
performance increase over the previous SHARC processors on a internal memory. The registers in PEX are referred to as
range of DSP algorithms. With its SIMD computational hard- R0–R15 and in PEY as S0–S15.
ware, the processors can perform 2.7 GFLOPS running at
450 MHz. Context Switch
FAMILY CORE ARCHITECTURE Many of the processor’s registers have secondary registers that
can be activated during interrupt servicing for a fast context
The ADSP-2148x is code compatible at the assembly level with switch. The data registers in the register file, the DAG registers,
the ADSP-2147x, ADSP-2146x, ADSP-2137x, ADSP-2136x, and the multiplier result registers all have secondary registers.
ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first The primary registers are active at reset, while the secondary
generation ADSP-2106x SHARC processors. The ADSP-2148x registers are activated by control bits in a mode control register.
shares architectural features with the ADSP-2126x, ADSP-
2136x, ADSP-2137x, ADSP-2146x and ADSP-2116x SIMD
SHARC processors, as shown in Figure 2 and detailed in the fol-
lowing sections.

Rev. I | Page 4 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

S JTAG FLAG TIMER INTERRUPT CACHE


SIMD Core

PM ADDRESS 24
DMD/PMD 64 5 STAGE
PROGRAM SEQUENCER
PM DATA 48

DAG1 DAG2
16x32 16x32

PM ADDRESS 32
SYSTEM
I/F
DM ADDRESS 32
USTAT
PM DATA 64 4x32-BIT

PX
DM DATA 64
64-BIT

RF DATA RF
ALU Rx/Fx SWAP Sx/SFx
MULTIPLIER SHIFTER ALU SHIFTER MULTIPLIER
PEx PEy
16x40-BIT 16x40-BIT

MRF MRB MSB MSF


80-BIT 80-BIT ASTATx ASTATy 80-BIT 80-BIT

STYKx STYKy

Figure 2. SHARC Core Block Diagram

Universal Registers fetches conflict with PM bus data accesses are cached. This
cache allows full speed execution of core, looped operations
These registers can be used for general-purpose tasks. The
such as digital filter multiply-accumulates, and FFT butterfly
USTAT (4) registers allow easy bit manipulations (Set, Clear,
processing.
Toggle, Test, XOR) for all peripheral registers (control/status).
The data bus exchange register (PX) permits data to be passed Data Address Generators With Zero-Overhead Hardware
between the 64-bit PM data bus and the 64-bit DM data bus, or Circular Buffer Support
between the 40-bit register file and the PM/DM data bus. These The two data address generators (DAGs) are used for indirect
registers contain hardware to handle the data width difference. addressing and implementing circular data buffers in hardware.
Single-Cycle Fetch of Instruction and Four Operands Circular buffers allow efficient programming of delay lines and
other data structures required in digital signal processing, and
The ADSP-2148x features an enhanced Harvard architecture in are commonly used in digital filters and Fourier transforms.
which the data memory (DM) bus transfers data and the pro- The two DAGs contain sufficient registers to allow the creation
gram memory (PM) bus transfers both instructions and data. of up to 32 circular buffers (16 primary register sets, 16 second-
With the its separate program and data memory buses and on- ary). The DAGs automatically handle address pointer
chip instruction cache, the processor can simultaneously fetch wraparound, reduce overhead, increase performance, and sim-
four operands (two over each data bus) and one instruction plify implementation. Circular buffers can start and end at any
(from the cache), all in a single cycle. memory location.
Instruction Cache Flexible Instruction Set
The processor includes an on-chip instruction cache that The 48-bit instruction word accommodates a variety of parallel
enables three-bus operation for fetching an instruction and four operations, for concise programming. For example, the
data values. The cache is selective—only the instructions whose processor can conditionally execute a multiply, an add, and a

Rev. I | Page 5 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
subtract in both processing elements while branching and fetch- asynchronous memory interface (AMI). Source modules need
ing up to four 32-bit values from memory, all in a single to be built using the VISA option, in order to allow code genera-
instruction. tion tools to create these more efficient opcodes.
Variable Instruction Set Architecture (VISA) On-Chip Memory
In addition to supporting the standard 48-bit instructions from The ADSP-21488 automotive products contain 2 Mbits of inter-
previous SHARC processors, the ADSP-2148x supports new nal RAM (Table 3), the ADSP-21483 and the ADSP-21488
instructions of 16 and 32 bits. This feature, called Variable processors contain 3 Mbits of internal RAM (Table 4), and the
Instruction Set Architecture (VISA), drops redundant/unused ADSP-21486, ADSP-21487, and ADSP-21489 processors con-
bits within the 48-bit instruction to create more efficient and tain 5 Mbits of internal RAM (Table 5). Each memory block
compact code. The program sequencer supports fetching these supports single-cycle, independent accesses by the core proces-
16-bit and 32-bit instructions from both internal and external sor and I/O processor.
SDRAM memory. This support is not extended to the

Table 3. Internal Memory Space (2 MBits—ADSP-21488 Automotive Products Only)1

IOP Registers 0x0000 0000–0x0003 FFFF


Extended Precision Normal or
Long Word (64 Bits) Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)
Block 0 ROM (Reserved) Block 0 ROM (Reserved) Block 0 ROM (Reserved) Block 0 ROM (Reserved)
0x0004 0000–0x0004 7FFF 0x0008 0000–0x0008 AAA9 0x0008 0000–0x0008 FFFF 0x0010 0000–0x0011 FFFF
Reserved Reserved Reserved Reserved
0x0004 8000–0x0004 8FFF 0x0008 AAAA–0x0008 BFFF 0x0009 0000–0x0009 1FFF 0x0012 0000–0x0012 3FFF
Block 0 SRAM Block 0 SRAM Block 0 SRAM Block 0 SRAM
0x0004 9000–0x0004 BFFF 0x0008 C000–0x0008 FFFF 0x0009 2000–0x0009 7FFF 0x0012 4000–0x0012 FFFF
Reserved Reserved Reserved Reserved
0x0004 C000–0x0004 FFFF 0x0009 0000–0x0009 FFFF 0x0009 8000–0x0009 FFFF 0x0013 0000–0x0013 FFFF
Block 1 ROM (Reserved) Block 1 ROM (Reserved) Block 1 ROM (Reserved) Block 1 ROM (Reserved)
0x0005 0000–0x0005 7FFF 0x000A 0000–0x000A AAA9 0x000A 0000–0x000AFFFF 0x0014 0000–0x0015 FFFF
Reserved Reserved Reserved Reserved
0x0005 8000–0x0005 8FFF 0x000A AAAA–0x000A BFFF 0x000B 0000–0x000B 1FFF 0x0016 0000–0x0016 3FFF
Block 1 SRAM Block 1 SRAM Block 1 SRAM Block 1 SRAM
0x0005 9000–0x0005 BFFF 0x000A C000–0x000A FFFF 0x000B 2000–0x000B 7FFF 0x0016 4000–0x0016 FFFF
Reserved Reserved Reserved Reserved
0x0005 C000–0x0005 FFFF 0x000B 0000–0x000B FFFF 0x000B 8000–0x000B FFFF 0x0017 0000–0x0017 FFFF
Block 2 SRAM Block 2 SRAM Block 2 SRAM Block 2 SRAM
0x0006 0000–0x0006 0FFF 0x000C 0000–0x000C 1554 0x000C 0000–0x000C 1FFF 0x0018 0000–0x0018 3FFF
Reserved Reserved Reserved Reserved
0x0006 1000– 0x0006 FFFF 0x000C 1555–0x000D FFFF 0x000C 2000–0x000D FFFF 0x0018 4000–0x001B FFFF
Block 3 SRAM Block 3 SRAM Block 3 SRAM Block 3 SRAM
0x0007 0000–0x0007 0FFF 0x000E 0000–0x000E 1554 0x000E 0000–0x000E 1FFF 0x001C 0000–0x001C 3FFF
Reserved Reserved Reserved Reserved
0x0007 1000–0x0007 FFFF 0x000E 1555–0x000F FFFF 0x000E 2000–0x000F FFFF 0x001C 4000–0x001F FFFF
1
Some ADSP-2148x processors include a customer-definable ROM block. ROM addresses on these models are not reserved as shown in this table. Contact your Analog Devices
sales representative for additional details.

Rev. I | Page 6 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Table 4. Internal Memory Space (3 MBits—ADSP-21483/ADSP-21488)1

IOP Registers 0x0000 0000–0x0003 FFFF


Extended Precision Normal or
Long Word (64 Bits) Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)
Block 0 ROM (Reserved) Block 0 ROM (Reserved) Block 0 ROM (Reserved) Block 0 ROM (Reserved)
0x0004 0000–0x0004 7FFF 0x0008 0000–0x0008 AAA9 0x0008 0000–0x0008 FFFF 0x0010 0000–0x0011 FFFF
Reserved Reserved Reserved Reserved
0x0004 8000–0x0004 8FFF 0x0008 AAAA–0x0008 BFFF 0x0009 0000–0x0009 1FFF 0x0012 0000–0x0012 3FFF
Block 0 SRAM Block 0 SRAM Block 0 SRAM Block 0 SRAM
0x0004 9000–0x0004 CFFF 0x0008 C000–0x0009 1554 0x0009 2000–0x0009 9FFF 0x0012 4000–0x0013 3FFF
Reserved Reserved Reserved Reserved
0x0004 D000–0x0004 FFFF 0x0009 1555–0x0009 FFFF 0x0009 A000–0x0009 FFFF 0x0013 4000–0x0013 FFFF
Block 1 ROM (Reserved) Block 1 ROM (Reserved) Block 1 ROM (Reserved) Block 1 ROM (Reserved)
0x0005 0000–0x0005 7FFF 0x000A 0000–0x000A AAA9 0x000A 0000–0x000A FFFF 0x0014 0000–0x0015 FFFF
Reserved Reserved Reserved Reserved
0x0005 8000–0x0005 8FFF 0x000A AAAA–0x000A BFFF 0x000B 0000–0x000B 1FFF 0x0016 0000–0x0016 3FFF
Block 1 SRAM Block 1 SRAM Block 1 SRAM Block 1 SRAM
0x0005 9000–0x0005 CFFF 0x000A C000–0x000B 1554 0x000B 2000–0x000B 9FFF 0x0016 4000–0x0017 3FFF
Reserved Reserved Reserved Reserved
0x0005 D000–0x0005 FFFF 0x000B 1555–0x000B FFFF 0x000B A000–0x000B FFFF 0x0017 4000–0x0017 FFFF
Block 2 SRAM Block 2 SRAM Block 2 SRAM Block 2 SRAM
0x0006 0000–0x0006 1FFF 0x000C 0000–0x000C 2AA9 0x000C 0000–0x000C 3FFF 0x0018 0000–0x0018 7FFF
Reserved Reserved Reserved Reserved
0x0006 2000– 0x0006 FFFF 0x000C 2AAA–0x000D FFFF 0x000C 4000–0x000D FFFF 0x0018 8000–0x001B FFFF
Block 3 SRAM Block 3 SRAM Block 3 SRAM Block 3 SRAM
0x0007 0000–0x0007 1FFF 0x000E 0000–0x000E 2AA9 0x000E 0000–0x000E 3FFF 0x001C 0000–0x001C 7FFF
Reserved Reserved Reserved Reserved
0x0007 2000–0x0007 FFFF 0x000E 2AAA–0x000F FFFF 0x000E 4000–0x000F FFFF 0x001C 8000–0x001F FFFF
1
Some ADSP-2148x processors include a customer-definable ROM block. ROM addresses on these models are not reserved as shown in this table. Contact your Analog Devices
sales representative for additional details.

The processor’s SRAM can be configured as a maximum of ROM Based Security


160k words of 32-bit data, 320k words of 16-bit data, 106.7k
The ADSP-2148x has a ROM security feature that provides
words of 48-bit instructions (or 40-bit data), or combinations of
hardware support for securing user software code by preventing
different word sizes up to 5 megabits. All of the memory can be
unauthorized reading from the internal code. When using this
accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit
feature, the processor does not boot-load any external code, exe-
floating-point storage format is supported that effectively dou-
cuting exclusively from internal ROM. Additionally, the
bles the amount of data that may be stored on-chip. Conversion
processor is not freely accessible via the JTAG port. Instead, a
between the 32-bit floating-point and 16-bit floating-point
unique 64-bit key, which must be scanned in through the JTAG
formats is performed in a single instruction. While each mem-
or Test Access Port will be assigned to each customer. The
ory block can store combinations of code and data, accesses are
device will ignore a wrong key. Emulation features are available
most efficient when one block stores data using the DM bus for
after the correct key is scanned.
transfers, and the other block stores instructions and data using
the PM bus for transfers. On-Chip Memory Bandwidth
Using the DM bus and PM buses, with one bus dedicated to a The internal memory architecture allows programs to have four
memory block, assures single-cycle execution with two data accesses at the same time to any of the four blocks (assuming
transfers. In this case, the instruction must be available in the there are no block conflicts). The total bandwidth is realized
cache. using the DMD and PMD buses (2 × 64-bits, CCLK speed) and
The memory maps in Table 3, Table 4, and Table 5 display the the IOD0/1 buses (2 × 32-bit, PCLK speed).
internal memory address space of the processors. The 48-bit
space section describes what this address range looks like to an
instruction that retrieves 48-bit memory. The 32-bit section
describes what this address range looks like to an instruction
that retrieves 32-bit memory.

Rev. I | Page 7 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Table 5. Internal Memory Space (5 MBits—ADSP-21486/ADSP-21487/ADSP-21489)1

IOP Registers 0x0000 0000–0x0003 FFFF


Extended Precision Normal or
Long Word (64 Bits) Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)
Block 0 ROM (Reserved) Block 0 ROM (Reserved) Block 0 ROM (Reserved) Block 0 ROM (Reserved)
0x0004 0000–0x0004 7FFF 0x0008 0000–0x0008 AAA9 0x0008 0000–0x0008 FFFF 0x0010 0000–0x0011 FFFF
Reserved Reserved Reserved Reserved
0x0004 8000–0x0004 8FFF 0x0008 AAAA–0x0008 BFFF 0x0009 0000–0x0009 1FFF 0x0012 0000–0x0012 3FFF
Block 0 SRAM Block 0 SRAM Block 0 SRAM Block 0 SRAM
0x0004 9000–0x0004 EFFF 0x0008 C000–0x0009 3FFF 0x0009 2000–0x0009 DFFF 0x0012 4000–0x0013 BFFF
Reserved Reserved Reserved Reserved
0x0004 F000–0x0004 FFFF 0x0009 4000–0x0009 FFFF 0x0009 E000–0x0009 FFFF 0x0013 C000–0x0013 FFFF
Block 1 ROM (Reserved) Block 1 ROM (Reserved) Block 1 ROM (Reserved) Block 1 ROM (Reserved)
0x0005 0000–0x0005 7FFF 0x000A 0000–0x000A AAA9 0x000A 0000–0x000A FFFF 0x0014 0000–0x0015 FFFF
Reserved Reserved Reserved Reserved
0x0005 8000–0x0005 8FFF 0x000A AAAA–0x000A BFFF 0x000B 0000–0x000B 1FFF 0x0016 0000–0x0016 3FFF
Block 1 SRAM Block 1 SRAM Block 1 SRAM Block 1 SRAM
0x0005 9000–0x0005 EFFF 0x000A C000–0x000B 3FFF 0x000B 2000–0x000B DFFF 0x0016 4000–0x0017 BFFF
Reserved Reserved Reserved Reserved
0x0005 F000–0x0005 FFFF 0x000B 4000–0x000B FFFF 0x000B E000–0x000B FFFF 0x0017 C000–0x0017 FFFF
Block 2 SRAM Block 2 SRAM Block 2 SRAM Block 2 SRAM
0x0006 0000–0x0006 3FFF 0x000C 0000–0x000C 5554 0x000C 0000–0x000C 7FFF 0x0018 0000–0x0018 FFFF
Reserved Reserved Reserved Reserved
0x0006 4000– 0x0006 FFFF 0x000C 5555–0x000D FFFF 0x000C 8000–0x000D FFFF 0x0019 0000–0x001B FFFF
Block 3 SRAM Block 3 SRAM Block 3 SRAM Block 3 SRAM
0x0007 0000–0x0007 3FFF 0x000E 0000–0x000E 5554 0x000E 0000–0x000E 7FFF 0x001C 0000–0x001C FFFF
Reserved Reserved Reserved Reserved
0x0007 4000–0x0007 FFFF 0x000E 5555–0x0000F FFFF 0x000E 8000–0x000F FFFF 0x001D 0000–0x001F FFFF
1
Some ADSP-2148x processors include a customer-definable ROM block and are not reserved as shown on this table. Contact your Analog Devices sales representative for
additional details.

FAMILY PERIPHERAL ARCHITECTURE • Arbitration logic to coordinate core and DMA transfers
between internal and external memory over the external
The ADSP-2148x family contains a rich set of peripherals that
port.
support a wide variety of applications including high quality
audio, medical imaging, communications, military, test equip- Non-SDRAM external memory address space is shown in
ment, 3D graphics, speech recognition, motor control, imaging, Table 6.
and other applications.
Table 6. External Memory for Non-SDRAM Addresses
External Memory
Size in
The external port interface supports access to the external mem-
Bank Words Address Range
ory through core and DMA accesses. The external memory
address space is divided into four banks. Any bank can be pro- Bank 0 6M 0x0020 0000–0x007F FFFF
grammed as either asynchronous or synchronous memory. The Bank 1 8M 0x0400 0000–0x047F FFFF
external ports are comprised of the following modules. Bank 2 8M 0x0800 0000–0x087F FFFF
• An Asynchronous Memory Interface which communicates Bank 3 8M 0x0C00 0000–0x0C7F FFFF
with SRAM, FLASH, and other devices that meet the stan-
dard asynchronous SRAM access protocol. The AMI External Port
supports 6M words of external memory in bank 0 and 8M The external port provides a high performance, glueless inter-
words of external memory in bank 1, bank 2, and bank 3. face to a wide variety of industry-standard memory devices. The
• A SDRAM controller that supports a glueless interface with external port, available on the 176-lead LQFP, may be used to
any of the standard SDRAMs. The SDC supports 62M interface to synchronous and/or asynchronous memory devices
words of external memory in bank 0, and 64M words of through the use of its separate internal memory controllers. The
external memory in bank 1, bank 2, and bank 3. NOTE: first is an SDRAM controller for connection of industry-stan-
This feature is not available on the ADSP-21486 product. dard synchronous DRAM devices while the second is an

Rev. I | Page 8 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
asynchronous memory controller intended to interface to a VISA and ISA Access to External Memory
variety of memory devices. Four memory select pins enable up The SDRAM controller on the ADSP-2148x processors sup-
to four separate devices to coexist, supporting any desired com- ports VISA code operation which reduces the memory load
bination of synchronous and asynchronous device types. since the VISA instructions are compressed. Moreover, bus
Asynchronous Memory Controller fetching is reduced because, in the best case, one 48-bit fetch
contains three valid instructions. Code execution from the tra-
The asynchronous memory controller provides a configurable ditional ISA operation is also supported. Note that code
interface for up to four separate banks of memory or I/O execution is only supported from bank 0 regardless of
devices. Each bank can be independently programmed with dif- VISA/ISA. Table 8 shows the address ranges for instruction
ferent timing parameters, enabling connection to a wide variety fetch in each mode.
of memory devices including SRAM, flash, and EPROM, as well
as I/O devices that interface with standard memory control
lines. Bank 0 occupies a 6M word window and banks 1, 2, and 3 Table 8. External Bank 0 Instruction Fetch
occupy a 8M word window in the processor’s address space but,
if not fully populated, these windows are not made contiguous Size in
by the memory controller logic. Access Type Words Address Range
ISA (NW) 4M 0x0020 0000–0x005F FFFF
SDRAM Controller
VISA (SW) 10M 0x0060 0000–0x00FF FFFF
The SDRAM controller provides an interface of up to four sepa-
rate banks of industry-standard SDRAM devices at speeds up to
fSDCLK. Fully compliant with the SDRAM standard, each bank has Pulse-Width Modulation
its own memory select line (MS0–MS3), and can be configured
The PWM module is a flexible, programmable, PWM waveform
to contain between 4M bytes and 256M bytes of memory.
generator that can be programmed to generate the required
SDRAM external memory address space is shown in Table 7.
switching patterns for various applications related to motor and
NOTE: This feature is not available on the ADSP-21486 model.
engine control or audio power control. The PWM generator can
generate either center-aligned or edge-aligned PWM wave-
Table 7. External Memory for SDRAM Addresses
forms. In addition, it can generate complementary signals on
Size in two outputs in paired mode or independent signals in non-
Bank Words Address Range paired mode (applicable to a single group of four PWM
Bank 0 62M 0x0020 0000–0x03FF FFFF
waveforms).
Bank 1 64M 0x0400 0000–0x07FF FFFF The entire PWM module has four groups of four PWM outputs
generating 16 PWM outputs in total. Each PWM group pro-
Bank 2 64M 0x0800 0000–0x0BFF FFFF
duces two pairs of PWM signals on the four PWM outputs.
Bank 3 64M 0x0C00 0000–0x0FFF FFFF
The PWM generator is capable of operating in two distinct
A set of programmable timing parameters is available to config- modes while generating center-aligned PWM waveforms:
ure the SDRAM banks to support slower memory devices. Note single-update mode or double-update mode. In single-update
that 32-bit wide devices are not supported on the SDRAM and mode the duty cycle values are programmable only once per
AMI interfaces. PWM period. This results in PWM patterns that are symmetri-
cal about the midpoint of the PWM period. In double-update
The SDRAM controller address, data, clock, and control pins mode, a second updating of the PWM registers is implemented
can drive loads up to distributed 30 pF. For larger memory sys- at the midpoint of the PWM period. In this mode, it is possible
tems, the SDRAM controller external buffer timing should be to produce asymmetrical PWM patterns that produce lower
selected and external buffering should be provided so that the harmonic distortion in three-phase PWM inverters.
load on the SDRAM controller pins does not exceed 30 pF.
PWM signals can be mapped to the external port address lines
Note that the external memory bank addresses shown are for or to the DPI pins.
normal-word (32-bit) accesses. If 48-bit instructions as well as
32-bit data are both placed in the same external memory bank, MediaLB
care must be taken while mapping them to avoid overlap. The automotive models of the ADSP-2148x processors have an
SIMD Access to External Memory MLB interface which allows the processor to function as a
media local bus device. It includes support for both 3-pin as well
The SDRAM controller on the processor supports SIMD access as 5-pin media local bus protocols. It supports speeds up to
on the 64-bit EPD (external port data bus) which allows access 1024 FS (49.25 Mbits/sec, FS = 48.1 kHz) and up to 31 logical
to the complementary registers on the PEy unit in the normal channels, with up to 124 bytes of data per media local bus frame.
word space (NW). This removes the need to explicitly access the For a list of automotive models, see Automotive Products.
complimentary registers when the data is in external SDRAM
memory.

Rev. I | Page 9 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Digital Applications Interface (DAI) Asynchronous Sample Rate Converter (SRC)
The digital applications interface (DAI) allows the connection The asynchronous sample rate converter contains four SRC
of various peripherals to any of the DAI pins (DAI_P20–1). blocks and is the same core as that used in the AD1896 192 kHz
Programs make these connections using the signal routing unit stereo asynchronous sample rate converter and provides up to
(SRU). 128 dB SNR. The SRC block is used to perform synchronous or
asynchronous sample rate conversion across independent stereo
The SRU is a matrix routing unit (or group of multiplexers) that
channels, without using internal processor resources. The four
enables the peripherals provided by the DAI to be intercon-
SRC blocks can also be configured to operate together to
nected under software control. This allows easy use of the DAI
convert multichannel audio data without phase mismatches.
associated peripherals for a much wider variety of applications
Finally, the SRC can be used to clean up audio data from jittery
by using a larger set of algorithms than is possible with noncon-
clock sources such as the S/PDIF receiver.
figurable signal paths.
The DAI includes eight serial ports, four precision clock genera- Input Data Port
tors (PCG), a S/PDIF transceiver, four ASRCs, and an input The IDP provides up to eight serial input channels—each with
data port (IDP). The IDP provides an additional input path to its own clock, frame sync, and data inputs. The eight channels
the SHARC core, configurable as either eight channels of serial are automatically multiplexed into a single 32-bit by eight-deep
data, or a single 20-bit wide synchronous parallel data acquisi- FIFO. Data is always formatted as a 64-bit frame and divided
tion port. Each data channel has its own DMA channel that is into two 32-bit words. The serial protocol is designed to receive
independent from the processor’s serial ports. audio channels in I2S, left-justified sample pair, or right-justified
mode.
Serial Ports (SPORTs)
The IDP also provides a parallel data acquisition port (PDAP),
The ADSP-2148x features eight synchronous serial ports that
which can be used for receiving parallel data. The PDAP port
provide an inexpensive interface to a wide variety of digital and
has a clock input and a hold input. The data for the PDAP can
mixed-signal peripheral devices such as Analog Devices’
be received from DAI pins or from the external port pins. The
AD183x family of audio codecs, ADCs, and DACs. The serial
PDAP supports a maximum of 20-bit data and four different
ports are made up of two data lines, a clock, and frame sync. The
packing modes to receive the incoming data.
data lines can be programmed to either transmit or receive and
each data line has a dedicated DMA channel. Precision Clock Generators
Serial ports can support up to 16 transmit or 16 receive DMA The precision clock generators (PCG) consist of four units, each
channels of audio data when all eight SPORTs are enabled, or of which generates a pair of signals (clock and frame sync)
four full duplex TDM streams of 128 channels per frame. derived from a clock input signal. The units, A B, C, and D, are
Serial port data can be automatically transferred to and from identical in functionality and operate independently of each
on-chip memory/external memory via dedicated DMA chan- other. The two signals generated by each unit are normally used
nels. Each of the serial ports can work in conjunction with as a serial bit clock/frame sync pair.
another serial port to provide TDM support. One SPORT pro- The outputs of PCG A and B can be routed through the DAI
vides two transmit signals while the other SPORT provides the pins and the outputs of PCG C and D can be driven on to the
two receive signals. The frame sync and clock are shared. DAI as well as the DPI pins.
Serial ports operate in five modes:
Digital Peripheral Interface (DPI)
• Standard serial mode
The ADSP-2148x SHARC processors have a digital peripheral
• Multichannel (TDM) mode interface that provides connections to two serial peripheral
• I2S mode interface ports (SPI), one universal asynchronous receiver-
transmitter (UART), 12 flags, a 2-wire interface (TWI), three
• Packed I2S mode
PWM modules (PWM3–1), and two general-purpose timers.
• Left-justified mode
Serial Peripheral (Compatible) Interface (SPI)
S/PDIF-Compatible Digital Audio Receiver/Transmitter
The SPI is an industry-standard synchronous serial link,
The S/PDIF receiver/transmitter has no separate DMA chan- enabling the SPI-compatible port to communicate with other
nels. It receives audio data in serial format and converts it SPI compatible devices. The SPI consists of two data pins, one
into a biphase encoded signal. The serial data input to the device select pin, and one clock pin. It is a full-duplex synchro-
receiver/transmitter can be formatted as left-justified, I2S or nous serial interface, supporting both master and slave modes.
right-justified with word widths of 16, 18, 20, or 24 bits. The SPI port can operate in a multimaster environment by
The serial data, clock, and frame sync inputs to the S/PDIF interfacing with up to four other SPI-compatible devices, either
receiver/transmitter are routed through the signal routing unit acting as a master or slave device. The SPI-compatible periph-
(SRU). They can come from a variety of sources, such as the eral implementation also features programmable baud rate and
SPORTs, external pins, or the precision clock generators
(PCGs), and are controlled by the SRU control registers.

Rev. I | Page 10 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
clock phase and polarities. The SPI-compatible port uses open I/O PROCESSOR FEATURES
drain drivers to support a multimaster configuration and to
The I/O processors provide up to 65 channels of DMA, as well
avoid data contention.
as an extensive set of peripherals.
UART Port
DMA Controller
The processors provide a full-duplex Universal Asynchronous
Receiver/Transmitter (UART) port, which is fully compatible The processor’s on-chip DMA controller allows data transfers
with PC-standard UARTs. The UART port provides a simpli- without processor intervention. The DMA controller operates
fied UART interface to other peripherals or hosts, supporting independently and invisibly to the processor core, allowing
full-duplex, DMA-supported, asynchronous transfers of serial DMA operations to occur while the core is simultaneously exe-
data. The UART also has multiprocessor communication capa- cuting its program instructions. DMA transfers can occur
bility using 9-bit address detection. This allows it to be used in between the ADSP-2148x’s internal memory and its serial ports,
multidrop networks through the RS-485 data interface the SPI-compatible (serial peripheral interface) ports, the IDP
standard. The UART port also includes support for 5 to 8 data (input data port), the PDAP, or the UART. The DMA channel
bits, 1 or 2 stop bits, and none, even, or odd parity. The UART summary is shown in Table 9.
port supports two modes of operation: Programs can be downloaded to the ADSP-2148x using DMA
• PIO (programmed I/O)—The processor sends or receives transfers. Other DMA features include interrupt generation
data by writing or reading I/O-mapped UART registers. upon completion of DMA transfers and DMA chaining for
The data is double-buffered on both transmit and receive. automatic linked DMA transfers.

• DMA (direct memory access)—The DMA controller trans- Table 9. DMA Channels
fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer Peripheral DMA Channels
data to and from memory. The UART has two dedicated SPORTs 16
DMA channels, one for transmit and one for receive. These IDP/PDAP 8
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates. SPI 2
UART 2
Timers External Port 2
The ADSP-2148x has a total of three timers: a core timer that Accelerators 2
can generate periodic software interrupts and two general- Memory-to-Memory 2
purpose timers that can generate periodic interrupts and be
independently set to operate in one of three modes: MLB1 31
1
Automotive models only.
• Pulse waveform generation mode
• Pulse width count/capture mode Delay Line DMA
• External event watchdog mode The processor provides delay line DMA functionality. This
The core timer can be configured to use FLAG3 as a timer allows processor reads and writes to external delay line buffers
expired signal, and the general-purpose timers have one bidirec- (and hence to external memory) with limited core interaction.
tional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register, Scatter/Gather DMA
a 32-bit period register, and a 32-bit pulse width register. A sin- The processor provides scatter/gather DMA functionality. This
gle control and status register enables or disables the general- allows processor DMA reads/writes to/from non contiguous
purpose timer. memory blocks.
2-Wire Interface Port (TWI) FFT Accelerator
The TWI is a bidirectional 2-wire, serial bus used to move 8-bit The FFT accelerator implements a radix-2 complex/real input,
data while maintaining compliance with the I2C bus protocol. complex output FFT with no core intervention. The FFT accel-
The TWI module incorporates the following features: erator runs at the peripheral clock frequency.
• 7-bit addressing FIR Accelerator
• Simultaneous controller and target operation on multiple
The FIR (finite impulse response) accelerator consists of a 1024
device systems with support for multimedia data
word coefficient memory, a 1024 word deep delay line for the
arbitration
data, and four MAC units. A controller manages the accelerator.
• Digital filtering and timed event processing The FIR accelerator runs at the peripheral clock frequency.
• 100 kbps and 400 kbps data rates
• Low interrupt rate

Rev. I | Page 11 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
IIR Accelerator extended to also act as the input for initiating a Running Reset.
For more information, see the ADSP-214xx SHARC Processor
The IIR (infinite impulse response) accelerator consists of a
Hardware Reference.
1440 word coefficient memory for storage of biquad coeffi-
cients, a data memory for storing the intermediate data, and one Power Supplies
MAC unit. A controller manages the accelerator. The IIR accel-
erator runs at the peripheral clock frequency. The processors have separate power supply connections for the
internal (VDD_INT) and external (VDD_EXT) power supplies. The
Watchdog Timer internal supply must meet the VDD_INT specifications. The
external supply must meet the VDD_EXT specification. All exter-
The watchdog timer is used to supervise the stability of the sys-
nal supply pins must be connected to the same power supply.
tem software. When used in this way, software reloads the
watchdog timer in a regular manner so that the downward To reduce noise coupling, the PCB should use a parallel pair of
counting timer never expires. An expiring timer then indicates power and ground planes for VDD_INT and GND.
that system software might be out of control.
Static Voltage Scaling (SVS)
The 32-bit watchdog timer that can be used to implement a soft-
ware watchdog function. A software watchdog can improve Some models of the ADSP-2148x feature Static Voltage Scaling
system reliability by forcing the processor to a known state (SVS) on the VDD_INT power supply. (See the Ordering Guide
through generation of a system reset, if the timer expires before for model details.) This voltage specification technique can pro-
being reloaded by software. Software initializes the count value vide significant performance benefits including 450 MHz core
of the timer, and then enables the timer. The watchdog timer frequency operation without a significant increase in power.
resets both the core and the internal peripherals. Note that this SVS optimizes the required VDD_INT voltage for each individual
feature is available on the 176-lead package only. device to enable enhanced operating frequency up to 450 MHz.
The optimized SVS voltage results in a reduction of maximum
SYSTEM DESIGN IDD_INT which enables 450 MHz operation at the same or lower
The following sections provide an introduction to system design maximum power than 400 MHz operation at a fixed voltage
options and power supply issues. supply. Implementation of SVS requires a specific voltage regu-
lator circuit design and initialization code.
Program Booting
Refer to the Engineer-to-Engineer Note Static Voltage Scaling
The internal memory of the ADSP-2148x boots at system for ADSP-2148x SHARC Processors (EE-357) for further infor-
power-up from an 8-bit EPROM via the external port, an SPI mation. The EE-Note details the requirements and process to
master, or an SPI slave. Booting is determined by the boot con- implement a SVS power supply system to enable operation up
figuration (BOOT_CFG2–0) pins in Table 10 for the 176-lead to 450 MHz. This applies only to specific products within the
package and Table 11 for the 100-lead package. ADSP-2148x family which are capable of supporting 450 MHz
operation.
Table 10. Boot Mode Selection, 176-Lead Package
Details on power consumption and Static and Dynamic current
BOOT_CFG2–0 Booting Mode consumption can be found at Total Power Dissipation. Also see
Operating Conditions for more information.
000 SPI Slave Boot
001 SPI Master Boot The following are SVS features.
010 AMI User Boot (for 8-bit Flash Boot) • SVS is applicable only to 450 MHz models (not applicable
011 No boot (processor executes from internal to 400 MHz or lower frequency models).
ROM after reset) • Each individual SVS device includes a register (SVS_DAT)
1xx Reserved containing the unique SVS voltage set at the factory, known
as SVSNOM.
Table 11. Boot Mode Selection, 100-Lead Package • The SVSNOM value is the intended set voltage for the
VDD_INT voltage regulator.
BOOT_CFG1–0 Booting Mode
00 SPI Slave Boot • No dedicated pins are required for SVS. The TWI serial bus
is used to communicate SVSNOM to the voltage regulator.
01 SPI Master Boot
10 Reserved
• Analog Devices recommends a specific voltage regulator
design and initialization code sequence that optimizes the
11 No boot (processor executes from internal power-up sequence.
ROM after reset)
The Engineer-to-Engineer Note Static Voltage Scaling for
The “Running Reset” feature allows a user to perform a reset of ADSP-2148x SHARC Processors (EE-357) contains the
the processor core and peripherals, but without resetting the details of the regulator design and the initialization
PLL and SDRAM controller, or performing a boot. The requirements.
functionality of the RESETOUT/RUNRSTIN pin has now been

Rev. I | Page 12 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
• Any differences from the Analog Devices recommended EZ-KIT Lite Evaluation Kits
programmable regulator design must be reviewed by Ana-
For a cost-effective way to learn more about developing with
log Devices to ensure that it meets the voltage accuracy and
Analog Devices processors, Analog Devices offer a range of EZ-
range requirements.
KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT
Target Board JTAG Emulator Connector Lite evaluation board, directions for downloading an evaluation
version of the available IDE(s), a USB cable, and a power supply.
Analog Devices DSP Tools product line of JTAG emulators uses The USB controller on the EZ-KIT Lite board connects to the
the IEEE 1149.1 JTAG test access port of the ADSP-2148x pro- USB port of the user’s PC, enabling the chosen IDE evaluation
cessors to monitor and control the target board processor suite to emulate the on-board processor in-circuit. This permits
during emulation. Analog Devices DSP Tools product line of the customer to download, execute, and debug programs for the
JTAG emulators provides emulation at full processor speed, EZ-KIT Lite system. It also supports in-circuit programming of
allowing inspection and modification of memory, registers, and the on-board Flash device to store user-specific boot code,
processor stacks. The processor’s JTAG interface ensures that enabling standalone operation. With the full version of Cross-
the emulator will not affect target system loading or timing. Core Embedded Studio or VisualDSP++ installed (sold
For complete information on Analog Devices’ SHARC DSP separately), engineers can develop software for supported EZ-
Tools product line of JTAG emulator operation, see the appro- KITs or any custom system utilizing supported Analog Devices
priate emulator hardware user’s guide. processors.

DEVELOPMENT TOOLS Software Add-Ins for CrossCore Embedded Studio


Analog Devices supports its processors with a complete line of Analog Devices offers software add-ins which seamlessly inte-
software and hardware development tools, including integrated grate with CrossCore Embedded Studio to extend its capabilities
development environments (which include CrossCore® Embed- and reduce development time. Add-ins include board support
ded Studio and/or VisualDSP++®), evaluation products, packages for evaluation hardware, various middleware pack-
emulators, and a wide variety of software add-ins. ages, and algorithmic modules. Documentation, help,
configuration dialogs, and coding examples present in these
Integrated Development Environments (IDEs) add-ins are viewable through the CrossCore Embedded Studio
For C/C++ software writing and editing, code generation, and IDE once the add-in is installed.
debug support, Analog Devices offers two IDEs.
Board Support Packages for Evaluation Hardware
CrossCore Embedded Studio is based on the EclipseTM frame-
Software support for the EZ-KIT Lite evaluation boards and EZ-
work. Supporting most Analog Devices processor families, it is
Extender daughter cards is provided by software add-ins called
the IDE of choice for future processors, including multicore
Board Support Packages (BSPs). The BSPs contain the required
devices. CrossCore Embedded Studio seamlessly integrates
drivers, pertinent release notes, and select example code for the
available software add-ins to support real time operating
given evaluation hardware. A download link for a specific BSP is
systems, file systems, TCP/IP stacks, USB stacks, algorithmic
located on the web page for the associated EZ-KIT or EZ-
software modules, and evaluation hardware board support
Extender product. The link is found in the Product Download
packages. For more information visit www.analog.com/cces.
area of the product web page.
The other Analog Devices IDE, VisualDSP++, supports proces-
sor families introduced prior to the release of CrossCore Middleware Packages
Embedded Studio. This IDE includes the Analog Devices VDK Analog Devices separately offers middleware add-ins such as
real time operating system and an open source TCP/IP stack. real time operating systems, file systems, USB stacks, and
For more information visit www.analog.com/visualdsp. Note TCP/IP stacks. For more information, see Operating Systems
that VisualDSP++ will not support future Analog Devices and Middleware.
processors.
Algorithmic Modules
EZ-KIT Lite Evaluation Board
To speed development, Analog Devices offers add-ins that per-
For processor evaluation, Analog Devices provides wide range form popular audio and video processing algorithms. These are
of EZ-KIT Lite® evaluation boards. Including the processor and available for use with both CrossCore Embedded Studio and
key peripherals, the evaluation board also supports on-chip VisualDSP++. For more information visit www.analog.com and
emulation capabilities and other evaluation and development search on “Blackfin software modules” or “SHARC software
features. Also available are various EZ-Extenders®, which are modules”.
daughter cards delivering additional specialized functionality,
including audio and video processing. For more information Designing an Emulator-Compatible DSP Board (Target)
visit www.analog.com and search on “ezkit” or “ezextender”. For embedded system test and debug, Analog Devices provides
a family of emulators. On each JTAG DSP, Analog Devices sup-
plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit
emulation is facilitated by use of this JTAG interface. The emu-
lator accesses the processor’s internal features via the

Rev. I | Page 13 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
processor’s TAP, allowing the developer to load code, set break-
points, and view variables, memory, and registers. The
processor must be halted to send data and commands, but once
an operation is completed by the emulator, the DSP system is set
to run at full speed with no impact on system timing. The emu-
lators require the target board to include a header that supports
connection of the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal ter-
mination, and emulator pod logic, see Analog Devices JTAG
Emulation Technical Reference (EE-68). This document is
updated regularly to keep pace with improvements to emulator
support.

ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSP-2148x
architecture and functionality. For detailed information on the
ADSP-2148x family core architecture and instruction set, refer
to the SHARC Processor Programming Reference.

RELATED SIGNAL CHAINS


A signal chain is a series of signal-conditioning electronic com-
ponents that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena.
Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together well. A tool for viewing relationships between
specific applications and related components is available on the
www.analog.com website.
The application signal chains page in the Circuits from the Lab®
site (www.analog.com\circuits) provides:
• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
• Drill down links for components in each chain to selection
guides and application information
• Reference designs applying best practice design techniques

Rev. I | Page 14 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
PIN FUNCTION DESCRIPTIONS
Table 12. Pin Descriptions

State
During/
Name Type After Reset Description
ADDR23–0 I/O/T (ipu) High-Z/ External Address. The processor outputs addresses for external memory and periph-
driven low erals on these pins. The ADDR pins can be multiplexed to support the external memory
(boot) interface address, and FLAGS15–8 (I/O) and PWM (O). After reset, all ADDR pins are in
external memory interface mode and FLAG(0–3) pins are in FLAGS mode (default).
When configured in the IDP_PDAP_CTL register, IDP channel 0 scans the ADDR23–4 pins
for parallel input data.
DATA15–0 I/O/T (ipu) High-Z External Data. The data pins can be multiplexed to support the external memory
interface data (I/O), and FLAGS7–0 (I/O).
AMI_ACK I (ipu) Memory Acknowledge. External devices can deassert AMI_ACK (low) to add wait
states to an external memory access. AMI_ACK is used by I/O devices, memory
controllers, or other peripherals to hold off completion of an external memory access.
MS0–1 O/T (ipu) High-Z Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corre-
sponding banks of external memory. The MS1-0 lines are decoded memory address lines
that change at the same time as the other address lines. When no external memory
access is occurring the MS1-0 lines are inactive; they are active however when a condi-
tional memory access instruction is executed, when the condition evaluates as true.
The MS1 pin can be used in EPORT/FLASH boot mode. For more information, see the
ADSP-214xx SHARC Processor Hardware Reference.
AMI_RD O/T (ipu) High-Z AMI Port Read Enable. AMI_RD is asserted whenever the processor reads a word from
external memory.
AMI_WR O/T (ipu) High-Z AMI Port Write Enable. AMI_WR is asserted when the processor writes a word to
external memory.
FLAG0/IRQ0 I/O (ipu) FLAG[0] FLAG0/Interrupt Request0.
INPUT
FLAG1/IRQ1 I/O (ipu) FLAG[1] FLAG1/Interrupt Request1.
INPUT
FLAG2/IRQ2/MS2 I/O (ipu) FLAG[2] FLAG2/Interrupt Request2/Memory Select2.
INPUT
FLAG3/TMREXP/MS3 I/O (ipu) FLAG[3] FLAG3/Timer Expired/Memory Select3.
INPUT
The following symbols appear in the Type column of this table: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,
O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic
levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot
be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The
range of an ipd resistor can be between 31 kΩ–85 kΩ. The three-state voltage of ipu pads will not reach to the full VDD_EXT level; at typical
conditions the voltage is in the range of 2.3 V to 2.7 V.
In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.

Rev. I | Page 15 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Table 12. Pin Descriptions (Continued)

State
During/
Name Type After Reset Description
SDRAS O/T (ipu) High-Z/ SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other
driven high SDRAM command pins, defines the operation for the SDRAM to perform.
SDCAS O/T (ipu) High-Z/ SDRAM Column Address Select. Connect to SDRAM’s CAS pin. In conjunction with
driven high other SDRAM command pins, defines the operation for the SDRAM to perform.
SDWE O/T (ipu) High-Z/ SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin. In conjunction with
driven high other SDRAM command pins, defines the operation for the SDRAM to perform.
SDCKE O/T (ipu) High-Z/ SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK
driven high signal. For details, see the data sheet supplied with the SDRAM device.
SDA10 O/T (ipu) High-Z/ SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with non-SDRAM
driven high accesses. This pin replaces the DSP’s ADDR10 pin only during SDRAM accesses.
SDDQM O/T (ipu) High-Z/ DQM Data Mask. SDRAM Input mask signal for write accesses and output mask signal
driven high for read accesses. Input data is masked when DQM is sampled high during a write cycle.
The SDRAM output buffers are placed in a High-Z state when DQM is sampled high
during a read cycle. SDDQM is driven high from reset de-assertion until SDRAM initial-
ization completes. Afterwards it is driven low irrespective of whether any SDRAM
accesses occur or not.
SDCLK O/T (ipd) High-Z/ SDRAM Clock Output. Clock driver for this pin differs from all other clock drivers. See
driving Figure 40. For models in the 100-lead package, the SDRAM interface should be disabled
to avoid unnecessary power switching by setting the DSDCTL bit in SDCTL register. For
more information, see the ADSP-214xx SHARC Processor Hardware Reference.
DAI _P20–1 I/O/T (ipu) High-Z Digital Applications Interface. These pins provide the physical interface to the DAI
SRU. The DAI SRU configuration registers define the combination of on-chip audio-
centric peripheral inputs or outputs connected to the pin and to the pin’s output enable.
The configuration registers of these peripherals then determines the exact behavior of
the pin. Any input or output signal present in the DAI SRU may be routed to any of these
pins.
DPI _P14–1 I/O/T (ipu) High-Z Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU.
The DPI SRU configuration registers define the combination of on-chip peripheral
inputs or outputs connected to the pin and to the pin’s output enable. The configu-
ration registers of these peripherals then determines the exact behavior of the pin. Any
input or output signal present in the DPI SRU may be routed to any of these pins.
WDT_CLKIN I Watchdog Timer Clock Input. This pin should be pulled low when not used.
WDT_CLKO O Watchdog Resonator Pad Output.
WDTRSTO O (ipu) Watchdog Timer Reset Out.
THD_P I Thermal Diode Anode. When not used, this pin can be left floating.
THD_M O Thermal Diode Cathode. When not used, this pin can be left floating.
The following symbols appear in the Type column of this table: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,
O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic
levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot
be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The
range of an ipd resistor can be between 31 kΩ–85 kΩ. The three-state voltage of ipu pads will not reach to the full VDD_EXT level; at typical
conditions the voltage is in the range of 2.3 V to 2.7 V.
In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.

Rev. I | Page 16 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Table 12. Pin Descriptions (Continued)

State
During/
Name Type After Reset Description
MLBCLK1 I Media Local Bus Clock. This clock is generated by the MLB controller that is synchro-
nized to the MOST network and provides the timing for the entire MLB interface at
49.152 MHz at FS=48 kHz. When the MLB controller is not used, this pin should be
grounded.
1
MLBDAT I/O/T in 3 High-Z Media Local Bus Data. The MLBDAT line is driven by the transmitting MLB device and
pin mode. I is received by all other MLB devices including the MLB controller. The MLBDAT line
in 5 pin carries the actual data. In 5-pin MLB mode, this pin is an input only. When the MLB
mode. controller is not used, this pin should be grounded.
MLBSIG1 I/O/T in 3 High-Z Media Local Bus Signal. This is a multiplexed signal which carries the Channel/Address
pin mode. I generated by the MLB Controller, as well as the Command and RxStatus bytes from
in 5 pin MLB devices. In 5-pin mode, this pin is input only. When the MLB controller is not used,
mode this pin should be grounded.
1
MLBDO O/T High-Z Media Local Bus Data Output (in 5 pin mode). This pin is used only in 5-pin MLB mode.
This serves as the output data pin in 5-pin mode. When the MLB controller is not used,
this pin should be connected to ground.
1
MLBSO O/T High-Z Media Local Bus Signal Output (in 5 pin mode). This pin is used only in 5-pin MLB
mode. This serves as the output signal pin in 5-pin mode. When the MLB controller is
not used, this pin should be connected to ground.
TDI I (ipu) Test Data Input (JTAG). Provides serial data for the boundary scan logic.
TDO O/T High-Z Test Data Output (JTAG). Serial scan output of the boundary scan path.
TMS I (ipu) Test Mode Select (JTAG). Used to control the test state machine.
TCK I Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the device.
TRST I (ipu) Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the processor.
EMU O (O/D, ipu) High-Z Emulation Status. Must be connected to the ADSP-2148x Analog Devices DSP Tools
product line of JTAG emulators target board connector only.
The following symbols appear in the Type column of this table: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,
O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic
levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot
be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The
range of an ipd resistor can be between 31 kΩ–85 kΩ. The three-state voltage of ipu pads will not reach to the full VDD_EXT level; at typical
conditions the voltage is in the range of 2.3 V to 2.7 V.
In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.

Rev. I | Page 17 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Table 12. Pin Descriptions (Continued)

State
During/
Name Type After Reset Description
CLK_CFG1–0 I Core to CLKIN Ratio Control. These pins set the start up clock frequency.
Note that the operating frequency can be changed by programming the PLL multiplier
and divider in the PMCTL register at any time after the core comes out of reset. The
allowed values are:
00 = 8:1
01 = 32:1
10 = 16:1
11 = reserved
CLKIN I Local Clock In. Used in conjunction with XTAL. CLKIN is the clock input. It configures
the processors to use either its internal clock generator or an external clock source.
Connecting the necessary components to CLKIN and XTAL enables the internal clock
generator. Connecting the external clock to CLKIN while leaving XTAL unconnected
configures the processors to use the external clock source such as an external clock
oscillator. CLKIN may not be halted, changed, or operated below the specified
frequency.
XTAL O Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external
crystal.
RESET I Processor Reset. Resets the processor to a known state. Upon deassertion, there is a
4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program
execution from the hardware reset vector address. The RESET input must be asserted
(low) at power-up.
RESETOUT/ I/O (ipu) Reset Out/Running Reset In. The default setting on this pin is reset out. This pin also
RUNRSTIN has a second function as RUNRSTIN which is enabled by setting bit 0 of the RUNRSTCTL
register. For more information, see the ADSP-214xx SHARC Processor Hardware
Reference.
BOOT_CFG2–0 I Boot Configuration Select. These pins select the boot mode for the processor (see
Table 10). The BOOT_CFG pins must be valid before RESET (hardware and software) is
asserted.
The following symbols appear in the Type column of this table: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,
O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic
levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot
be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The
range of an ipd resistor can be between 31 kΩ–85 kΩ. The three-state voltage of ipu pads will not reach to the full VDD_EXT level; at typical
conditions the voltage is in the range of 2.3 V to 2.7 V.
In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.
1
The MLB pins are only available on the automotive models.

Table 13. Pin List, Power, Ground and Other

Name Type Description


VDD_INT P Internal Power Supply
VDD_EXT P I/O Power Supply
GND1 G Ground
VDD_THD P Thermal Diode Power Supply. When not used, this pin can be left floating.
DNC DNC Do Not Connect. Do not make any electrical connection to this pin.
1
The exposed pad is required to be electrically and thermally connected to GND. Implement this by soldering the exposed pad to a GND PCB land that is the same size as the
exposed pad. The GND PCB land should be robustly connected to the GND plane in the PCB for best electrical and thermal performance. No separate GND pins are provided
in the package.

Rev. I | Page 18 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
SPECIFICATIONS
Specifications are subject to change without notice. For information about product specifications, contact your Analog Devices, Inc.,
representative.
OPERATING CONDITIONS
All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.

266 MHz / 300 MHz / 350 MHz / 400 MHz 450 MHz

Parameter1 Description Min Nominal Max Min Nominal Max Unit


2
VDD_INT Internal (Core) Supply Voltage 1.05 1.10 1.15 SVSNOM – 25 mV 1.00 – 1.15 SVSNOM + 25 mV V
VDD_EXT External (I/O) Supply Voltage 3.13 3.47 3.13 3.47 V
VDD_THD Thermal Diode Supply Voltage 3.13 3.47 3.13 3.47 V
3
VIH High Level Input Voltage at 2.0 3.6 2.0 3.6 V
VDD_EXT = Max
VIL3 Low Level Input Voltage at –0.3 +0.8 –0.3 +0.8 V
VDD_EXT = Min
VIH_CLKIN4 High Level Input Voltage at 2.2 VDD_EXT 2.2 VDD_EXT V
VDD_EXT = Max
VIL_CLKIN Low Level Input Voltage at –0.3 +0.8 –0.3 +0.8 V
VDD_EXT = Min
CONSUMER GRADE
TJ Junction Temperature 0 115 N/A5 N/A5 °C
88-Lead LFCSP_VQ
TJ Junction Temperature 0 110 N/A5 N/A5 °C
100-Lead LQFP_EP
TJ Junction Temperature 0 110 0 115 °C
176-Lead LQFP_EP
INDUSTRIAL GRADE
TJ Junction Temperature –40 +125 N/A5 N/A5 °C
100-Lead LQFP_EP
TJ Junction Temperature –40 +125 N/A5 N/A5 °C
176-Lead LQFP_EP
AUTOMOTIVE GRADE6
TJ Junction Temperature –40 +125 N/A5 N/A5 °C
88-Lead LFCSP_VQ
TJ Junction Temperature –40 +125 N/A5 N/A5 °C
100-Lead LQFP_EP
TJ Junction Temperature –40 +125 N/A5 N/A5 °C
176-Lead LQFP_EP
1
Specifications subject to change without notice.
2
SVSNOM refers to the nominal SVS voltage which is set between 1.0 V and 1.15 V at the factory for each individual device. Only the unique SVSNOM value in each chip may be used
for 401 MHz to 450 MHz operation of that chip. This spec lists the possible range of the SVSNOM values for all devices. The initial VDD_INT voltage at power on is 1.1 V nominal
and it transitions to SVS programmed voltage as outlined in Engineer-to-Engineer Note Static Voltage Scaling for ADSP-2148x SHARC Processors (EE-357).
3
Applies to input and bidirectional pins: ADDR23–0, DATA15–0, FLAG3–0, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RUNRSTIN, RESET, TCK, TMS, TDI, TRST, AMI_ACK,
MLBCLK, MLBDAT, MLBSIG.
4
Applies to input pins CLKIN, WDT_CLKIN.
5
N/A means not applicable.
6
Automotive application use profile only. Not supported for nonautomotive use. Contact Analog Devices for more information.

Rev. I | Page 19 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
ELECTRICAL CHARACTERISTICS
All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.

266 MHz / 300 MHz / 350 MHz / 400 MHz / 450 MHz

Parameter1 Description Conditions Min Typ Max Unit


2
VOH High Level Output @ VDD_EXT = Min, 2.4 V
Voltage IOH = –1.0 mA3
VOL2 Low Level Output @ VDD_EXT = Min, 0.4 V
Voltage IOL = 1.0 mA3
IIH4, 5 High Level Input Current @ VDD_EXT = Max, 10 μA
VIN = VDD_EXT Max
IIL4 Low Level Input Current @ VDD_EXT = Max, VIN = 0 V 10 μA
5
IILPU Low Level Input Current @ VDD_EXT = Max, VIN = 0 V 200 μA
Pull-up
IOZH6, 7 Three-State Leakage @ VDD_EXT = Max, 10 μA
Current VIN = VDD_EXT Max
IOZL6 Three-State Leakage @ VDD_EXT = Max, VIN = 0 V 10 μA
Current
IOZLPU7 Three-State Leakage @ VDD_EXT = Max, VIN = 0 V 200 μA
Current Pull-up
IOZHPD8 Three-State Leakage @ VDD_EXT = Max, 200 μA
Current Pull-down VIN = VDD_EXT Max
IDD_INT9 Supply Current (Internal) fCCLK > 0 MHz Table 15 + Table 16 mA
× ASF
IDD_INT Supply Current (Internal) VDDINT = 1.1 V, ASF = 1, 385 / 410 / 450 / 500 / 550 mA
TJ = 25°C
CIN10, 11 Input Capacitance TJ = 25°C 5 pF
1
Specifications subject to change without notice.
2
Applies to output and bidirectional pins: ADDR23–0, DATA15–0, AMI_RD, AMI_WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO, RESETOUT MLBSIG, MLBDAT, MLBDO,
MLBSO, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, MS0-1.
3
See Output Drive Currents for typical drive current capabilities.
4
Applies to input pins: BOOT_CFGx, CLK_CFGx, TCK, RESET, CLKIN.
5
Applies to input pins with internal pull-ups: TRST, TMS, TDI.
6
Applies to three-statable pin: TDO.
7
Applies to three-statable pins with pull-ups: DAI_Px, DPI_Px, EMU.
8
Applies to three-statable pin with pull-down: SDCLK.
9
See Engineer-to-Engineer Note Estimating Power for ADSP-214xx SHARC Processors (EE-348) for further information.
10
Applies to all signal pins.
11
Guaranteed, but not tested.

Rev. I | Page 20 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Total Power Dissipation
The information in this section should be augmented with the Table 14. Activity Scaling Factors (ASF)1
Engineer-to-Engineer Note Estimating Power for ADSP-214xx
SHARC Processors (EE-348). Activity Scaling Factor (ASF)
Total power dissipation has two components: Idle 0.29
Low 0.53
1. Internal power consumption is additionally comprised of
two components: Medium Low 0.61
Medium High 0.77
• Static current due to leakage. Table 15 shows the static
current consumption (IDD_INT_STATIC) as a function of Peak Typical (50:50)2 0.85
junction temperature (TJ) and core voltage (VDD_INT). Peak Typical (60:40)2 0.93
• Dynamic current (IDD_INT_DYNAMIC), due to transistor Peak Typical (70:30)2 1.00
switching characteristics and activity level of the pro- High Typical 1.16
cessor. The activity level is reflected by the Activity High 1.25
Scaling Factor (ASF), which represents the activity Peak 1.31
level of the application code running on the processor 1
See the Engineer-to-Engineer Note Estimating Power for ADSP-214xx SHARC
core and having various levels of peripheral and exter- Processors (EE-348) for more information on the explanation of the power
nal port activity (Table 14). vectors specific to the ASF table.
2
Dynamic current consumption is calculated by select- Ratio of continuous instruction loop (core) to SDRAM control code reads and
writes.
ing the ASF that corresponds most closely with the
user application and then multiplying that with the
dynamic current consumption (Table 16).
2. External power consumption is due to the switching activ-
ity of the external pins.

Table 15. Static Current—IDD_INT_STATIC (mA)1

VDD_INT (V)
TJ (°C) 0.975 V 1.0 V 1.025 V 1.05 V 1.075 V 1.10 V 1.125 V 1.15 V 1.175 V
–45 68 77 86 96 107 118 131 144 159
–35 74 83 92 103 114 126 140 154 170
–25 82 92 101 113 125 138 153 168 185
–15 94 104 115 127 140 155 171 187 205
–5 109 121 133 147 161 177 194 212 233
+5 129 142 156 171 188 206 225 245 268
+15 152 168 183 201 219 240 261 285 309
+25 182 199 216 237 257 280 305 331 360
+35 217 237 256 279 303 329 358 388 420
+45 259 282 305 331 359 389 421 455 492
+55 309 334 361 391 423 458 495 533 576
+65 369 398 429 464 500 539 582 626 675
+75 437 471 506 547 588 633 682 731 789
+85 519 559 599 645 693 746 802 860 926
+95 615 662 707 761 816 877 942 1007 1083
+105 727 779 833 897 958 1026 1103 1179 1266
+115 853 914 975 1047 1119 1198 1285 1372 1473
+125 997 1067 1138 1219 1305 1397 1498 1601 1716
1
Valid temperature and voltage ranges are model-specific. See Operating Conditions.

Rev. I | Page 21 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Table 16. Dynamic Current in CCLK Domain—IDD_INT_DYNAMIC (mA, with ASF = 1.0)1, 2

fCCLK VDD_INT (V)


(MHz) 0.975 V 1.0 V 1.025 V 1.05 V 1.075 V 1.10 V 1.125 V 1.15 V 1.175 V
100 76 77 81 84 87 88 90 92 95
150 117 119 123 126 130 133 136 139 144
200 153 156 161 165 170 174 179 183 188
250 190 195 201 207 212 217 223 229 235
300 227 233 240 246 253 260 266 273 280
350 263 272 278 286 294 302 309 318 325
400 300 309 317 326 335 344 352 361 370
450 339 349 356 365 374 385 394 405 415
1
The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics.
2
Valid frequency and voltage ranges are model-specific. See Operating Conditions.

ABSOLUTE MAXIMUM RATINGS ESD SENSITIVITY


Stresses at or above those listed in Table 17 may cause perma-
nent damage to the product. This is a stress rating only;
functional operation of the product at these or any other condi- ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
tions above those indicated in the operational section of this without detection. Although this product features
specification is not implied. Operation beyond the maximum patented or proprietary protection circuitry, damage
operating conditions for extended periods may affect product may occur on devices subjected to high energy ESD.
reliability. Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
Table 17. Absolute Maximum Ratings

Parameter Rating MAXIMUM POWER DISSIPATION


Internal (Core) Supply Voltage (VDD_INT) –0.3 V to +1.32 V See Engineer-to-Engineer Note Estimating Power for ADSP-
External (I/O) Supply Voltage (VDD_EXT) –0.3 V to +3.6 V 214xx SHARC Processors (EE-348) for detailed thermal and
Thermal Diode Supply Voltage –0.3 V to +3.6 V
power information regarding maximum power dissipation. For
(VDD_THD)
information on package thermal specifications, see Thermal
Characteristics.
Input Voltage –0.5 V to +3.6 V
Output Voltage Swing –0.5 V to VDD_EXT +0.5 V
Storage Temperature Range –65°C to +150°C
Junction Temperature While Biased 125°C

Rev. I | Page 22 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
TIMING SPECIFICATIONS Timing requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
All specifications and characteristics apply across the entire
operation. Timing requirements guarantee that the processor
operating conditions range unless otherwise noted.
operates correctly with other devices.
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others. Core Clock Requirements
While addition or subtraction would yield meaningful results The processor’s internal clock (a multiple of CLKIN) provides
for an individual device, the values given in this data sheet the clock signal for timing internal memory, the processor core,
reflect statistical variations and worst cases. Consequently, it is and the serial ports. During reset, program the ratio between the
not meaningful to add parameters to derive longer times. See processor’s internal clock frequency and external (CLKIN)
Figure 42 for voltage reference levels. clock frequency with the CLK_CFG1–0 pins.
Switching characteristics specify how the processor changes its The processor’s internal clock switches at higher frequencies
signals. Circuitry external to the processor must be designed for than the system input clock (CLKIN). To generate the internal
compatibility with these signal characteristics. Switching char- clock, the processor uses an internal phase-locked loop (PLL,
acteristics describe what the processor will do in a given see Figure 3). This PLL-based clocking minimizes the skew
circumstance. Use switching characteristics to ensure that any between the system clock (CLKIN) signal and the processor’s
timing requirement of a device connected to the processor (such internal clock.
as memory) is satisfied.

PMCTL
(SDCKR)
PMCTL
PLL (PLLBP)

BYPASS
fINPUT fVCO CCLK SDRAM

MUX
CLKIN CLKIN LOOP PLL
DIVIDER VCO DIVIDER DIVIDER
FILTER

BYPASS
fCCLK

MUX
XTAL SDCLK
BUF
CLK_CFGx/ PMCTL
PMCTL PMCTL (2 × PLLM) (PLLD) DIVIDE PCLK
PMCTL
(INDIV) BY 2
(PLLBP)

fVCO ÷ (2 × PLLM)
PCLK

CCLK

CLKOUT (TEST ONLY)*


MUX
PIN

DELAY OF RESETOUT BUF RESETOUT


RESET 4096 CLKIN
CYCLES

CORESRST
*CLKOUT (TEST ONLY) FREQUENCY IS THE SAME AS fINPUT.
THIS SIGNAL IS NOT SPECIFIED OR SUPPORTED FOR ANY DESIGN.

Figure 3. Core Clock and System Clock Relationship to CLKIN

Voltage Controlled Oscillator (VCO) where:


In application designs, the PLL multiplier value should be fVCO = VCO output
selected in such a way that the VCO frequency never exceeds PLLM = Multiplier value programmed in the PMCTL register.
fVCO specified in Table 20. During reset, the PLLM value is derived from the ratio selected
• The product of CLKIN and PLLM must never exceed 1/2 of using the CLK_CFG pins in hardware.
fVCO (max) in Table 20 if the input divider is not enabled PLLD = 2, 4, 8, or 16 based on the divider value programmed on
(INDIV = 0). the PMCTL register. During reset this value is 2.
• The product of CLKIN and PLLM must never exceed fVCO fINPUT = is the input frequency to the PLL.
(max) in Table 20 if the input divider is enabled
(INDIV = 1). fINPUT = CLKIN when the input divider is disabled or
The VCO frequency is calculated as follows: fINPUT = CLKIN ÷ 2 when the input divider is enabled
fVCO = 2 × PLLM × fINPUT
fCCLK = (2 × PLLM × fINPUT) ÷ PLLD

Rev. I | Page 23 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Note the definitions of the clock periods that are a function of Power-Up Sequencing
CLKIN and the appropriate ratio control shown in Table 18. All
The timing requirements for processor startup are given in
of the timing specifications for the ADSP-2148x peripherals are
Table 19. While no specific power-up sequencing is required
defined in relation to tPCLK. See the peripheral specific section
between VDD_EXT and VDD_INT, there are some considerations
for each peripheral’s timing information.
that system designs should take into account.
Table 18. Clock Periods • No power supply should be powered up for an extended
period of time (> 200 ms) before another supply starts to
Timing ramp up.
Requirements Description
• If the VDD_INT power supply comes up after VDD_EXT, any
tCK CLKIN Clock Period pin, such as RESETOUT and RESET, may actually drive
tCCLK Processor Core Clock Period momentarily until the VDD_INT rail has powered up.
tPCLK Peripheral Clock Period = 2 × tCCLK Systems sharing these signals on the board must determine
tSDCLK SDRAM Clock Period = (tCCLK) × SDCKR if there are any issues that need to be addressed based on
this behavior.
Figure 3 shows core to CLKIN relationships with external oscil- Note that during power-up, when the VDD_INT power supply
lator or crystal. The shaded divider/multiplier blocks denote comes up after VDD_EXT, a leakage current of the order of three-
where clock ratios can be set through hardware or software state leakage current pull-up, pull-down may be observed on
using the power management control register (PMCTL). For any pin, even if that is an input only (for example the RESET
more information, see ADSP-214xx SHARC Processor Hard- pin) until the VDD_INT rail has powered up.
ware Reference.

Table 19. Power-Up Sequencing Timing Requirements (Processor Startup)

Parameter Min Max Unit


Timing Requirements
tRSTVDD RESET Low Before VDD_EXT or VDD_INT On 0 ms
tIVDDEVDD VDD_INT On Before VDD_EXT –200 +200 ms
1
tCLKVDD CLKIN Valid After VDD_INT and VDD_EXT Valid 0 200 ms
2
tCLKRST CLKIN Valid Before RESET Deasserted 10 μs
3
tPLLRST PLL Control Setup Before RESET Deasserted 20 μs
Switching Characteristic
tCORERST4, 5 Core Reset Deasserted After RESET Deasserted 4096 × tCK + 2 × tCCLK
1
Valid VDD_INT and VDD_EXT assumes that the supplies are fully ramped to their nominal values (it does not matter which supply comes up first). Voltage ramp rates can vary
from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's data sheet for startup time. Assume
a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3
Based on CLKIN cycles.
4
Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
5
The 4096 cycle count depends on tSRST specification in Table 21. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097
cycles maximum.

Rev. I | Page 24 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
tRSTVDD
RESET

VDDINT
tIVDDEVDD

VDDEXT
tCLKVDD

CLKIN
tCLKRST

CLK_CFG1–0

tPLLRST tCORERST

RESETOUT

Figure 4. Power-Up Sequencing

Clock Input

Table 20. Clock Input

266 MHz 300 MHz 350 MHz 400 MHz 450 MHz
Parameter Min Max Min Max Min Max Min Max Min Max Unit
Timing Requirements
tCK CLKIN Period 301 1002 26.661 1002 22.81 1002 201 1002 17.751 1002 ns
tCKL CLKIN Width Low 15 45 13 45 11 45 10 45 8.875 45 ns
tCKH CLKIN Width High 15 45 13 45 11 45 10 45 8.875 45 ns
tCKRF3 CLKIN Rise/Fall (0.4 V to 2.0 V) 3 3 3 3 3 ns
tCCLK4 CCLK Period 3.75 10 3.33 10 2.85 10 2.5 10 2.22 10 ns
fVCO5 VCO Frequency 200 800 200 800 200 800 200 800 200 900 MHz
tCKJ6, 7 CLKIN Jitter Tolerance –250 +250 –250 +250 –250 +250 –250 +250 –250 +250 ps
1
Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL.
2
Applies only for CLK_CFG1–0 = 01 and default values for PLL control bits in PMCTL.
3
Guaranteed by simulation but not tested on silicon.
4
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK.
5
See Figure 3 for VCO diagram.
6
Actual input jitter should be combined with ac specifications for accurate timing analysis.
7
Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.

tCK tCKJ

CLKIN
tCKH tCKL

Figure 5. Clock Input

Rev. I | Page 25 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Clock Signals
The ADSP-2148x can use an external clock or a crystal. See the CLKIN pin description in Table 12. Programs can configure the processor
to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. Figure 6 shows the component connec-
tions used for a crystal operating in fundamental mode. Note that the clock rate is achieved using a 25 MHz crystal and a PLL multiplier
ratio 16:1 (CCLK:CLKIN achieves a clock speed of 400 MHz). To achieve the full core clock rate, programs need to configure the multi-
plier bits in the PMCTL register.

ADSP-2148x

CLKIN R1 XTAL
0ȍ

R2
47ȍ CHOOSE C1 AND C2 BASED ON THE CRYSTAL Y1.
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL DRIVE
C1 C2 POWER. REFER TO CRYSTAL MANUFACTURER’S
22pF Y1 22pF SPECIFICATIONS.

25 MHz

TYPICAL VALUES

Figure 6. Recommended Circuit for


Fundamental Mode Crystal Operation

Rev. I | Page 26 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Reset

Table 21. Reset

Parameter Min Max Unit


Timing Requirements
tWRST1 RESET Pulse Width Low 4 × tCK ns
tSRST RESET Setup Before CLKIN Low 8 ns
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μ while RESET is low, assuming stable
VDD and CLKIN (not including start-up time of external clock oscillator).

CLKIN

tWRST tSRST

RESET

Figure 7. Reset

Running Reset
The following timing specification applies to RESETOUT/RUNRSTIN pin when it is configured as RUNRSTIN.

Table 22. Running Reset

Parameter Min Max Unit


Timing Requirements
tWRUNRST Running RESET Pulse Width Low 4 × tCK ns
tSRUNRST Running RESET Setup Before CLKIN High 8 ns

CLKIN

tWRUNRST tSRUNRST

RUNRSTIN

Figure 8. Running Reset

Rev. I | Page 27 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Interrupts
The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2
interrupts, as well as the DAI_P20–1 and DPI_P14–1 pins when they are configured as interrupts.

Table 23. Interrupts

Parameter Min Max Unit


Timing Requirement
tIPW IRQx Pulse Width 2 × tPCLK +2 ns

INTERRUPT
INPUTS

tIPW

Figure 9. Interrupts

Core Timer
The following timing specification applies to FLAG3 when it is configured as the core timer (TMREXP).

Table 24. Core Timer

Parameter Min Max Unit


Switching Characteristic
tWCTIM TMREXP Pulse Width 4 × tPCLK – 1 ns

tWCTIM

FLAG3
(TMREXP)

Figure 10. Core Timer

Rev. I | Page 28 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Timer PWM_OUT Cycle Timing
The following timing specification applies to timer0 and timer1 in PWM_OUT (pulse-width modulation) mode. Timer signals are routed
to the DPI_P14–1 pins through the DPI SRU. Therefore, the timing specifications provided below are valid at the DPI_P14–1 pins.

Table 25. Timer PWM_OUT Timing

Parameter Min Max Unit


Switching Characteristic
tPWMO Timer Pulse Width Output 2 × tPCLK – 1.2 2 × (231 – 1) × tPCLK ns

tPWMO

PWM
OUTPUTS

Figure 11. Timer PWM_OUT Timing

Timer WDTH_CAP Timing


The following timing specification applies to timer0 and timer1, and in WDTH_CAP (pulse-width count and capture) mode. Timer sig-
nals are routed to the DPI_P14–1 pins through the SRU. Therefore, the timing specification provided below is valid at the DPI_P14–1
pins.

Table 26. Timer Width Capture Timing

Parameter Min Max Unit


Timing Requirement
tPWI Timer Pulse Width 2 × tPCLK 2 × (231 – 1) × tPCLK ns

tPWI
TIMER
CAPTURE
INPUTS

Figure 12. Timer Width Capture Timing

Rev. I | Page 29 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Watchdog Timer Timing

Table 27. Watchdog Timer Timing

Parameter Min Max Unit


Timing Requirement
tWDTCLKPER 100 1000 ns
Switching Characteristics
tRST WDT Clock Rising Edge to Watchdog Timer 3 6.4 ns
RESET Falling Edge
tRSTPW Reset Pulse Width 64 × tWDTCLKPER ns

tWDTCLKPER

WDT_CLKIN

tRST
tRSTPW

WDTRSTO

Figure 13. Watchdog Timer Timing

Pin to Pin Direct Routing (DAI and DPI)


For direct pin connections only (for example DAI_PB01_I to DAI_PB02_O).

Table 28. DAI/DPI Pin to Pin Routing

Parameter Min Max Unit


Timing Requirement
tDPIO Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid 1.5 12 ns

DAI_Pn
DPI_Pn

tDPIO

DAI_Pm
DPI_Pm

Figure 14. DAI Pin to Pin Direct Routing

Rev. I | Page 30 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Precision Clock Generator (Direct Pin Routing)
This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI
pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG’s inputs and outputs are not
directly routed to/from DAI pins (via pin buffers), there is no timing data available. All timing parameters and switching characteristics
apply to external DAI pins (DAI_P01 – DAI_P20).

Table 29. Precision Clock Generator (Direct Pin Routing)

Parameter Min Max Unit


Timing Requirements
tPCGIW Input Clock Period tPCLK × 4 ns
tSTRIG PCG Trigger Setup Before Falling Edge of PCG Input 4.5 ns
Clock
tHTRIG PCG Trigger Hold After Falling Edge of PCG Input 3 ns
Clock
Switching Characteristics
tDPCGIO PCG Output Clock and Frame Sync Active Edge 2.5 10 ns
Delay After PCG Input Clock
tDTRIGCLK PCG Output Clock Delay After PCG Trigger 2.5 + (2.5 × tPCGIP) 10 + (2.5 × tPCGIP) ns
tDTRIGFS PCG Frame Sync Delay After PCG Trigger 2.5 + ((2.5 + D – PH) × tPCGIP) 10 + ((2.5 + D – PH) × tPCGIP) ns
tPCGOW1 Output Clock Period 2 × tPCGIP – 1 ns
D = FSxDIV, PH = FSxPHASE. For more information, see the “Precision Clock Generators” chapter in the ADSP-214xx SHARC Processor
Hardware Reference.
1
Normal mode of operation.

tSTRIG tHTRIG

DAI_Pn
DPI_Pn
PCG_TRIGx_I

DAI_Pm
DPI_Pm
PCG_EXTx_I
(CLKIN)
tDPCGIO tPCGIP
DAI_Py
DPI_Py
PCG_CLKx_O

tDTRIGCLK tDPCGIO tPCGOW

DAI_Pz
DPI_Pz
PCG_FSx_O

tDTRIGFS

Figure 15. Precision Clock Generator (Direct Pin Routing)

Rev. I | Page 31 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Flags
The timing specifications provided below apply to the DPI_P14–1, ADDR7–0,ADDR23–8, DATA7–0, and FLAG3–0 pins when
configured as FLAGS. See Table 12 for more information on flag use.

Table 30. Flags

Parameter Min Max Unit


Timing Requirement
tFIPW1 FLAGs IN Pulse Width 2 × tPCLK + 3 ns
Switching Characteristic
tFOPW1 FLAGs OUT Pulse Width 2 × tPCLK – 3 ns
1
This is applicable when the Flags are connected to DPI_P14–1, ADDR7–0, ADDR23–8, DATA7–0 and FLAG3–0 pins.

FLAG
INPUTS

tFIPW

FLAG
OUTPUTS

tFOPW

Figure 16. Flags

Rev. I | Page 32 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
SDRAM Interface Timing (166 MHz SDCLK)
The maximum frequency for SDRAM is 166 MHz. For information on SDRAM frequency and programming, see the ADSP-214xx
SHARC Processor Hardware Reference, Engineer-to-Engineer Note Interfacing SDRAM Memories to SHARC Processors (EE-286), and
the SDRAM vendor data sheet.

Table 31. SDRAM Interface Timing

Parameter Min Max Unit


Timing Requirements
tSSDAT DATA Setup Before SDCLK 0.7 ns
tHSDAT DATA Hold After SDCLK 1.23 ns
Switching Characteristics
tSDCLK1 SDCLK Period 6 ns
tSDCLKH SDCLK Width High 2.2 ns
tSDCLKL SDCLK Width Low 2.2 ns
2
tDCAD Command, ADDR, Data Delay After SDCLK 4 ns
tHCAD2 Command, ADDR, Data Hold After SDCLK 1 ns
tDSDAT Data Disable After SDCLK 5.3 ns
tENSDAT Data Enable After SDCLK 0.3 ns
1
Systems should use the SDRAM model with a speed grade higher than the desired SDRAM controller speed. For example, to run the SDRAM controller at 166 MHz the
SDRAM model with a speed grade of 183 MHz or above should be used. See Engineer-to-Engineer Note Interfacing SDRAM Memories to SHARC Processors (EE-286) for
more information on hardware design guidelines for the SDRAM interface.
2
Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE.

tSDCLK tSDCLKH

SDCLK

tSSDAT tHSDAT tSDCLKL

DATA (IN)
tDCAD
tDSDAT
tENSDAT
tHCAD

DATA (OUT)

tDCAD tHCAD
COMMAND/ADDR
(OUT)

Figure 17. SDRAM Interface Timing

Rev. I | Page 33 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
AMI Read
Use these specifications for asynchronous interfacing to memories. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR,
and strobe timing parameters only apply to asynchronous access mode.

Table 32. AMI Read

Parameter Min Max Unit


Timing Requirements
tDAD1, 2, 3 Address Selects Delay to Data Valid W + tSDCLK –5.4 ns
tDRLD1, 3 AMI_RD Low to Data Valid W – 3.2 ns
tSDS Data Setup to AMI_RD High 2.5 ns
tHDRH4, 5 Data Hold from AMI_RD High 0 ns
tDAAK2, 6 AMI_ACK Delay from Address, Selects tSDCLK –9.5 + W ns
tDSAK4 AMI_ACK Delay from AMI_RD Low W–7 ns
Switching Characteristics
tDRHA Address Selects Hold After AMI_RD High RHC + 0.20 ns
tDARL4 Address Selects to AMI_RD Low tSDCLK – 3.8 ns
tRW AMI_RD Pulse Width W – 1.4 ns
tRWR AMI_RD High to AMI_RD Low HI + tSDCLK – 1 ns
W = (number of wait states specified in AMICTLx register) × tSDCLK.
RHC = (number of Read Hold Cycles specified in AMICTLx register) × tSDCLK
Where PREDIS = 0
HI = RHC (if IC=0): Read to Read from same bank
HI = RHC + tSDCLK (if IC>0): Read to Read from same bank
HI = RHC + IC: Read to Read from different bank
HI = RHC + Max (IC, (4 × tSDCLK)): Read to Write from same or different bank
Where PREDIS = 1
HI = RHC + Max (IC, (4 × tSDCLK)): Read to Write from same or different bank
HI = RHC + (3 × tSDCLK): Read to Read from same bank
HI = RHC + Max (IC, (3 × tSDCLK): Read to Read from different bank
IC = (number of idle cycles specified in AMICTLx register) × tSDCLK
H = (number of hold cycles specified in AMICTLx register) × tSDCLK
1
Data delay/setup: System must meet tDAD, tDRLD, or tSDS.
2
The falling edge of MSx, is referenced.
3
The maximum limit of timing requirement values for tDAD and tDRLD parameters are applicable for the case where AMI_ACK is always high and when the ACK feature is not
used.
4
Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode.
5
Data hold: User must meet tHDRH in asynchronous access mode. See Test Conditions for the calculation of hold times given capacitive and dc loads.
6
AMI_ACK delay/setup: User must meet tDAAK, or tDSAK, for deassertion of AMI_ACK (low).

Rev. I | Page 34 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
AMI_ADDR
AMI_MSx

tDARL tRW tDRHA

AMI_RD

tDRLD tSDS
tDAD tHDRH

AMI_DATA

tDSAK tRWR
tDAAK

AMI_ACK

AMI_WR

Figure 18. AMI Read

Rev. I | Page 35 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
AMI Write
Use these specifications for asynchronous interfacing to memories. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR,
and strobe timing parameters only apply to asynchronous access mode.

Table 33. AMI Write

Parameter Min Max Unit


Timing Requirements
tDAAK1, 2 AMI_ACK Delay from Address, Selects tSDCLK – 9.7 + W ns
tDSAK1, 3 AMI_ACK Delay from AMI_WR Low W–6 ns
Switching Characteristics
tDAWH2 Address Selects to AMI_WR Deasserted tSDCLK – 3.1+ W ns
tDAWL2 Address Selects to AMI_WR Low tSDCLK – 3 ns
tWW AMI_WR Pulse Width W – 1.3 ns
tDDWH Data Setup Before AMI_WR High tSDCLK – 3.7+ W ns
tDWHA Address Hold After AMI_WR Deasserted H + 0.15 ns
tDWHD Data Hold After AMI_WR Deasserted H ns
4
tDATRWH Data Disable After AMI_WR Deasserted tSDCLK – 4.3 + H tSDCLK + 4.9 + H ns
tWWR5 AMI_WR High to AMI_WR Low tSDCLK – 1.5+ H ns
tDDWR Data Disable Before AMI_RD Low 2 × tSDCLK – 6 ns
tWDE Data Enabled to AMI_WR Low tSDCLK – 3.7 ns
W = (number of wait states specified in AMICTLx register) × tSDCLK
H = (number of hold cycles specified in AMICTLx register) × tSDCLK
1
AMI_ACK delay/setup: System must meet tDAAK, or tDSAK, for deassertion of AMI_ACK (low).
2
The falling edge of MSx is referenced.
3
Note that timing for AMI_ACK, AMI_RD, AMI_WR, and strobe timing parameters only applies to asynchronous access mode.
4
See Test Conditions for calculation of hold times given capacitive and dc loads.
5
For Write to Write: tSDCLK + H, for both same bank and different bank. For Write to Read: 3 × tSDCLK + H, for the same bank and different banks.

AMI_ADDR
AMI_MSx

tDAWH tDWHA
tDAWL tWW

AMI_WR

tWWR
tWDE
tDATRWH
tDDWH tDDWR

AMI_DATA

tDSAK tDWHD
tDAAK

AMI_ACK

AMI_RD

Figure 19. AMI Write

Rev. I | Page 36 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Serial Ports
In slave transmitter mode and master receiver mode, the maximum serial port frequency is fPCLK/8. In master transmitter mode and slave
receiver mode, the maximum serial port clock frequency is fPCLK/4. To determine whether communication is possible between two
devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold; 2) data delay
and data setup and hold; and 3) SCLK width.
Serial port signals (SCLK, frame sync, Data Channel A, Data Channel B) are routed to the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided below are valid at the DAI_P20–1 pins.

Table 34. Serial Ports—External Clock

Parameter Min Max Unit


Timing Requirements
tSFSE1 Frame Sync Setup Before SCLK 2.5
(Externally Generated Frame Sync in either Transmit or Receive ns
Mode)
1
tHFSE Frame Sync Hold After SCLK 2.5
(Externally Generated Frame Sync in either Transmit or Receive ns
Mode)
1
tSDRE Receive Data Setup Before Receive SCLK 1.9 ns
tHDRE1 Receive Data Hold After SCLK 2.5 ns
tSCLKW SCLK Width (tPCLK × 4) ÷ 2 – 1.5 ns
tSCLK SCLK Period tPCLK × 4 ns
Switching Characteristics
tDFSE2 Frame Sync Delay After SCLK 10.25
(Internally Generated Frame Sync in either Transmit or Receive Mode) ns
tHOFSE2 Frame Sync Hold After SCLK 2
(Internally Generated Frame Sync in either Transmit or Receive Mode) ns
tDDTE2 Transmit Data Delay After Transmit SCLK 9 ns
2
tHDTE Transmit Data Hold After Transmit SCLK 2 ns
1
Referenced to sample edge.
2
Referenced to drive edge.

Table 35. Serial Ports—Internal Clock


Parameter Min Max Unit
Timing Requirements
tSFSI1 Frame Sync Setup Before SCLK 7
(Externally Generated Frame Sync in either Transmit or Receive Mode) ns
tHFSI1 Frame Sync Hold After SCLK 2.5
(Externally Generated Frame Sync in either Transmit or Receive Mode) ns
tSDRI1 Receive Data Setup Before SCLK 7 ns
tHDRI1 Receive Data Hold After SCLK 2.5 ns
Switching Characteristics
tDFSI2 Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode) 4 ns
tHOFSI2 Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode) –1 ns
tDFSIR2 Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode) 9.75 ns
2
tHOFSIR Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode) –1 ns
tDDTI2 Transmit Data Delay After SCLK 3.25 ns
tHDTI2 Transmit Data Hold After SCLK –2 ns
tSCKLIW Transmit or Receive SCLK Width 2 × tPCLK – 1.5 2 × tPCLK + 1.5 ns
1
Referenced to the sample edge.
2
Referenced to drive edge.

Rev. I | Page 37 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

DATA RECEIVE—INTERNAL CLOCK DATA RECEIVE—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE


tSCLKIW tSCLKW

DAI_P20–1 DAI_P20–1
(SCLK) (SCLK)

tDFSI tDFSE
tHOFSI tSFSI tHFSI tHOFSE tSFSE tHFSE

DAI_P20–1 DAI_P20–1
(FS) (FS)

tSDRI tHDRI tSDRE tHDRE


DAI_P20–1 DAI_P20–1
(DATA (DATA
CHANNEL A/B) CHANNEL A/B)

DATA TRANSMIT—INTERNAL CLOCK DATA TRANSMIT—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE


tSCLKIW tSCLKW

DAI_P20–1 DAI_P20–1
(SCLK) (SCLK)

tDFSI tDFSE
tHOFSI tSFSI tHFSI tHOFSE tSFSE tHFSE

DAI_P20–1 DAI_P20–1
(FS) (FS)

tDDTI tDDTE
tHDTI tHDTE
DAI_P20–1 DAI_P20–1
(DATA (DATA
CHANNEL A/B) CHANNEL A/B)

Figure 20. Serial Ports

Rev. I | Page 38 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Table 36. Serial Ports—External Late Frame Sync

Parameter Min Max Unit


Switching Characteristics
tDDTLFSE1 Data Delay from Late External Transmit Frame Sync or External 8.5
Receive Frame Sync with MCE = 1, MFD = 0 ns
tDDTENFS1 Data Enable for MCE = 1, MFD = 0 0.5 ns
1
The tDDTLFSE and tDDTENFS parameters apply to left-justified, as well as DSP serial mode, and MCE = 1, MFD = 0.

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

DRIVE SAMPLE DRIVE


DAI_P20–1
(SCLK)

tHFSE/I
tSFSE/I

DAI_P20–1
(FS)

tDDTE/I
tDDTENFS
tHDTE/I
DAI_P20–1
(DATA CHANNEL 1ST BIT 2ND BIT
A/B)

tDDTLFSE

LATE EXTERNAL TRANSMIT FS

DRIVE SAMPLE DRIVE


DAI_P20–1
(SCLK)

tHFSE/I
tSFSE/I

DAI_P20–1
(FS)

tDDTE/I
tDDTENFS
tHDTE/I
DAI_P20–1
(DATA CHANNEL 1ST BIT 2ND BIT
A/B)

t
Figure 21. External Late Frame Sync1
1
This figure reflects changes made to support left-justified mode.

Rev. I | Page 39 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Table 37. Serial Ports—Enable and Three-State

Parameter Min Max Unit


Switching Characteristics
tDDTEN1 Data Enable from External Transmit SCLK 2 ns
tDDTTE1 Data Disable from External Transmit SCLK 11.5 ns
tDDTIN1 Data Enable from Internal Transmit SCLK –1.5 ns
1
Referenced to drive edge.

DRIVE EDGE DRIVE EDGE

DAI_P20–1
(SCLK, EXT)

tDDTEN tDDTTE
DAI_P20–1
(DATA
CHANNEL A/B)

DRIVE EDGE

DAI_P20–1
(SCLK, INT)
tDDTIN

DAI_P20–1
(DATA
CHANNEL A/B)

Figure 22. Serial Ports—Enable and Three-State

Rev. I | Page 40 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
The SPORTx_TDV_O output signal (routing unit) becomes active in SPORT multichannel mode. During transmit slots (enabled with
active channel selection registers) the SPORTx_TDV_O is asserted for communication with external devices.

Table 38. Serial Ports—TDV (Transmit Data Valid)

Parameter Min Max Unit


Switching Characteristics1
tDRDVEN TDV Assertion Delay from Drive Edge of External Clock 3 ns
tDFDVEN TDV Deassertion Delay from Drive Edge of External Clock 8 ns
tDRDVIN TDV Assertion Delay from Drive Edge of Internal Clock –1 ns
tDFDVIN TDV Deassertion Delay from Drive Edge of Internal Clock 2 ns
1
Referenced to drive edge.

DRIVE EDGE DRIVE EDGE

DAI_P20–1
(SCLK, EXT)

TDVx
DAI_P20-1 tDFDVEN

tDRDVEN

DRIVE EDGE DRIVE EDGE

DAI_P20–1
(SCLK, INT)

TDVx
DAI_P20-1
tDFDVIN

tDRDVIN

Figure 23. Serial Ports—TDM Internal and External Clock

Rev. I | Page 41 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Input Data Port (IDP)
The timing requirements for the IDP are given in Table 39. IDP signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided below are valid at the DAI_P20–1 pins.

Table 39. Input Data Port (IDP)

Parameter Min Max Unit


Timing Requirements
tSISFS1 Frame Sync Setup Before Serial Clock Rising Edge 3.8 ns
tSIHFS1 Frame Sync Hold After Serial Clock Rising Edge 2.5 ns
1
tSISD Data Setup Before Serial Clock Rising Edge 2.5 ns
tSIHD1 Data Hold After Serial Clock Rising Edge 2.5 ns
tIDPCLKW Clock Width (tPCLK × 4) ÷ 2 – 1 ns
tIDPCLK Clock Period tPCLK × 4 ns
1
The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG's input can
be either CLKIN or any of the DAI pins.

SAMPLE EDGE tIDPCLK

tIDPCLKW
DAI_P20–1
(SCLK)

tSISFS tSIHFS

DAI_P20–1
(FS)

tSISD
tSIHD

DAI_P20–1
(SDATA)

Figure 24. IDP Master Timing

Rev. I | Page 42 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in Table 40. PDAP is the parallel mode operation of Channel 0 of the IDP. For details
on the operation of the PDAP, see the “PDAP” chapter of the ADSP-214xx SHARC Processor Hardware Reference. Note that the 20 bits
of external PDAP data can be provided through the ADDR23–4 pins or over the DAI pins.

Table 40. Parallel Data Acquisition Port (PDAP)

Parameter Min Max Unit


Timing Requirements
tSPHOLD1 PDAP_HOLD Setup Before PDAP_CLK Sample Edge 2.5 ns
tHPHOLD1 PDAP_HOLD Hold After PDAP_CLK Sample Edge 2.5 ns
tPDSD1 PDAP_DAT Setup Before PDAP_CLK Sample Edge 3.85 ns
1
tPDHD PDAP_DAT Hold After PDAP_CLK Sample Edge 2.5 ns
tPDCLKW Clock Width (tPCLK × 4) ÷ 2 – 3 ns
tPDCLK Clock Period tPCLK × 4 ns
Switching Characteristics
tPDHLDD Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word 2 × tPCLK + 3 ns
tPDSTRB PDAP Strobe Pulse Width 2 × tPCLK – 1.5 ns
1
Source pins of PDAP_DATA are ADDR23–4 or DAI pins. Source pins for PDAP_CLK and PDAP_HOLD are 1) DAI pins; 2) CLKIN through PCG; 3) DAI pins through
PCG; or 4) ADDR3–2 pins.

SAMPLE EDGE
tPDCLK
tPDCLKW

DAI_P20–1
(PDAP_CLK)

tSPHOLD tHPHOLD

DAI_P20–1
(PDAP_HOLD)

tPDSD tPDHD

DAI_P20–1/
ADDR23–4
(PDAP_DATA)

tPDHLDD tPDSTRB
DAI_P20–1
(PDAP_STROBE)

Figure 25. PDAP Timing

Rev. I | Page 43 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Sample Rate Converter—Serial Input Port
The ASRC input signals are routed from the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided in Table 41 are
valid at the DAI_P20–1 pins.

Table 41. ASRC, Serial Input Port

Parameter Min Max Unit


Timing Requirements
tSRCSFS1 Frame Sync Setup Before Serial Clock Rising Edge 4 ns
tSRCHFS1 Frame Sync Hold After Serial Clock Rising Edge 5.5 ns
1
tSRCSD Data Setup Before Serial Clock Rising Edge 4 ns
tSRCHD1 Data Hold After Serial Clock Rising Edge 5.5 ns
tSRCCLKW Clock Width (tPCLK × 4) ÷ 2 – 1 ns
tSRCCLK Clock Period tPCLK × 4 ns
1
The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input
can be either CLKIN or any of the DAI pins.

SAMPLE EDGE
tSRCCLK

DAI_P20–1 tSRCCLKW
(SCLK)

tSRCSFS tSRCHFS

DAI_P20–1
(FS)

tSRCSD tSRCHD

DAI_P20–1
(SDATA)

Figure 26. ASRC Serial Input Port Timing

Rev. I | Page 44 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Sample Rate Converter—Serial Output Port
For the serial output port, the frame sync is an input, and it should meet setup and hold times with regard to SCLK on the output port. The
serial data output has a hold time and delay specification with regard to serial clock. Note that serial clock rising edge is the sampling edge,
and the falling edge is the
drive edge.

Table 42. ASRC, Serial Output Port

Parameter Min Max Unit


Timing Requirements
tSRCSFS1 Frame Sync Setup Before Serial Clock Rising Edge 4 ns
1
tSRCHFS Frame Sync Hold After Serial Clock Rising Edge 5.5 ns
tSRCCLKW Clock Width (tPCLK × 4) ÷ 2 – 1 ns
tSRCCLK Clock Period tPCLK × 4 ns
Switching Characteristics
tSRCTDD1 Transmit Data Delay After Serial Clock Falling Edge 9.9 ns
tSRCTDH1 Transmit Data Hold After Serial Clock Falling Edge 1 ns
1
The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input
can be either CLKIN or any of the DAI pins.

SAMPLE EDGE
tSRCCLK

DAI_P20–1 tSRCCLKW
(SCLK)

tSRCSFS tSRCHFS

DAI_P20–1
(FS)

tSRCTDD
tSRCTDH
DAI_P20–1
(SDATA)

Figure 27. ASRC Serial Output Port Timing

Rev. I | Page 45 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Pulse-Width Modulation Generators (PWM)
The following timing specifications apply when the ADDR23–8/DPI_14–1 pins are configured as PWM.

Table 43. Pulse-Width Modulation (PWM) Timing

Parameter Min Max Unit


Switching Characteristics
tPWMW PWM Output Pulse Width tPCLK – 2 (216 – 2) × tPCLK ns
tPWMP PWM Output Period 2 × tPCLK – 1.5 (216 – 1) × tPCLK ns

tPWMW

PWM
OUTPUTS

tPWMP

Figure 28. PWM Timing

S/PDIF Transmitter
Serial data input to the S/PDIF transmitter can be formatted as left-justified, I2S, or right-justified with word widths of 16, 18, 20, or 24
bits. The following sections provide timing for the transmitter.
S/PDIF Transmitter-Serial Input Waveforms
Figure 29 shows the right-justified mode. Frame sync is high for the left channel and low for the right channel. Data is valid on the rising
edge of serial clock. The MSB is delayed the minimum in 24-bit output mode or the maximum in 16-bit output mode from a frame sync
transition, so that when there are 64 serial clock periods per frame sync period, the LSB of the data is right-justified to the next frame sync
transition.

Table 44. S/PDIF Transmitter Right-Justified Mode

Parameter Nominal Unit


Timing Requirement
tRJD Frame Sync to MSB Delay in Right-Justified Mode
16-Bit Word Mode 16 SCLK
18-Bit Word Mode 14 SCLK
20-Bit Word Mode 12 SCLK
24-Bit Word Mode 8 SCLK

DAI_P20–1 LEFT/RIGHT CHANNEL


FS

DAI_P20–1
SCLK
tRJD

DAI_P20–1 LSB MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB


SDATA

Figure 29. Right-Justified Mode

Rev. I | Page 46 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Figure 30 shows the default I2S-justified mode. The frame sync is low for the left channel and HI for the right channel. Data is valid on the
rising edge of serial clock. The MSB is left-justified to the frame sync transition but with a delay.

Table 45. S/PDIF Transmitter I2S Mode

Parameter Nominal Unit


Timing Requirement
tI2SD Frame Sync to MSB Delay in I2S Mode 1 SCLK

DAI_P20–1 LEFT/RIGHT CHANNEL


FS

DAI_P20–1
SCLK
tI2SD

DAI_P20–1
MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB
SDATA

Figure 30. I2S-Justified Mode

Figure 31 shows the left-justified mode. The frame sync is high for the left channel and low for the right channel. Data is valid on the rising
edge of serial clock. The MSB is left-justified to the frame sync transition with no delay.

Table 46. S/PDIF Transmitter Left-Justified Mode

Parameter Nominal Unit


Timing Requirement
tLJD Frame Sync to MSB Delay in Left-Justified Mode 0 SCLK

DAI_P20–1 LEFT/RIGHT CHANNEL


FS

DAI_P20–1
SCLK
tLJD

DAI_P20–1
SDATA MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB

Figure 31. Left-Justified Mode

Rev. I | Page 47 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
S/PDIF Transmitter Input Data Timing
The timing requirements for the S/PDIF transmitter are given in Table 47. Input signals are routed to the DAI_P20–1 pins using the SRU.
Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins.

Table 47. S/PDIF Transmitter Input Data Timing

Parameter Min Max Unit


Timing Requirements
tSISFS1 Frame Sync Setup Before Serial Clock Rising Edge 3 ns
tSIHFS1 Frame Sync Hold After Serial Clock Rising Edge 3 ns
tSISD1 Data Setup Before Serial Clock Rising Edge 3 ns
1
tSIHD Data Hold After Serial Clock Rising Edge 3 ns
tSITXCLKW Transmit Clock Width 9 ns
tSITXCLK Transmit Clock Period 20 ns
tSISCLKW Clock Width 36 ns
tSISCLK Clock Period 80 ns
1
The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can
be either CLKIN or any of the DAI pins.

SAMPLE EDGE
tSITXCLKW tSITXCLK

DAI_P20–1
(TxCLK)

tSISCLK
tSISCLKW
DAI_P20–1
(SCLK)

tSISFS tSIHFS

DAI_P20–1
(FS)

tSISD tSIHD

DAI_P20–1
(SDATA)

Figure 32. S/PDIF Transmitter Input Timing

Oversampling Clock (TxCLK) Switching Characteristics


The S/PDIF transmitter requires an oversampling clock input. This high frequency clock (TxCLK) input is divided down to generate the
internal biphase clock.

Table 48. Oversampling Clock (TxCLK) Switching Characteristics

Parameter Max Unit


Frequency for TxCLK = 384 × Frame Sync Oversampling Ratio × Frame Sync ≤ 1/tSITXCLK MHz
Frequency for TxCLK = 256 × Frame Sync 49.2 MHz
Frame Rate (FS) 192.0 kHz

Rev. I | Page 48 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
S/PDIF Receiver
The following section describes timing as it relates to the S/PDIF receiver.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × FS clock.

Table 49. S/PDIF Receiver Internal Digital PLL Mode Timing

Parameter Min Max Unit


Switching Characteristics
tDFSI Frame Sync Delay After Serial Clock 5 ns
tHOFSI Frame Sync Hold After Serial Clock –2 ns
tDDTI Transmit Data Delay After Serial Clock 5 ns
tHDTI Transmit Data Hold After Serial Clock –2 ns
tSCLKIW1 Transmit Serial Clock Width 8 × tPCLK – 2 ns
1
SCLK frequency is 64 × FS where FS = the frequency of frame sync.

DRIVE EDGE SAMPLE EDGE


tSCLKIW

DAI_P20–1
(SCLK)

tDFSI
tHOFSI
DAI_P20–1
(FS)

tDDTI
tHDTI
DAI_P20–1
(DATA CHANNEL
A/B)

Figure 33. S/PDIF Receiver Internal Digital PLL Mode Timing

Rev. I | Page 49 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
SPI Interface—Master
The ADSP-2148x contains two SPI ports. Both primary and secondary are available through DPI only. The timing provided in Table 50
and Table 51 applies to both.

Table 50. SPI Interface Protocol—Master Switching and Timing Specifications

Parameter Min Max Unit


Timing Requirements
tSSPIDM Data Input Valid to SPICLK Edge (Data Input Setup Time) 8.2 ns
tHSPIDM SPICLK Last Sampling Edge to Data Input Not Valid 2 ns
Switching Characteristics
tSPICLKM Serial Clock Cycle 8 × tPCLK – 2 ns
tSPICHM Serial Clock High Period 4 × tPCLK – 2 ns
tSPICLM Serial Clock Low Period 4 × tPCLK – 2 ns
tDDSPIDM SPICLK Edge to Data Out Valid (Data Out Delay Time) 2.5 ns
tHDSPIDM SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 4 × tPCLK – 2 ns
tSDSCIM DPI Pin (SPI Device Select) Low to First SPICLK Edge 4 × tPCLK – 2 ns
tHDSM Last SPICLK Edge to DPI Pin (SPI Device Select) High 4 × tPCLK – 2 ns
tSPITDM Sequential Transfer Delay 4 × tPCLK – 1.2 ns

DPI
(OUTPUT)

tSDSCIM tSPICHM tSPICLM


tSPICLKM tHDSM tSPITDM
SPICLK
(CP = 0,
CP = 1)
(OUTPUT)
tHDSPIDM
tDDSPIDM

MOSI
(OUTPUT)

tSSPIDM tSSPIDM
CPHASE = 1
tHSPIDM tHSPIDM

MISO
(INPUT)

tDDSPIDM tHDSPIDM

MOSI
(OUTPUT)

tSSPIDM tHSPIDM
CPHASE = 0

MISO
(INPUT)

Figure 34. SPI Master Timing

Rev. I | Page 50 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
SPI Interface—Slave

Table 51. SPI Interface Protocol—Slave Switching and Timing Specifications

Parameter Min Max Unit


Timing Requirements
tSPICLKS Serial Clock Cycle 4 × tPCLK – 2 ns
tSPICHS Serial Clock High Period 2 × tPCLK – 2 ns
tSPICLS Serial Clock Low Period 2 × tPCLK – 2 ns
tSDSCO SPIDS Assertion to First SPICLK Edge 2 × tPCLK ns
CPHASE = 0
CPHASE = 1
tHDS Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 2 × tPCLK ns
tSSPIDS Data Input Valid to SPICLK edge (Data Input Set-up Time) 2 ns
tHSPIDS SPICLK Last Sampling Edge to Data Input Not Valid 2 ns
tSDPPW SPIDS Deassertion Pulse Width (CPHASE=0) 2 × tPCLK ns
Switching Characteristics
tDSOE SPIDS Assertion to Data Out Active 0 7.5 ns
tDSOE1 SPIDS Assertion to Data Out Active (SPI2) 0 7.5 ns
tDSDHI SPIDS Deassertion to Data High Impedance 0 10.5 ns
1
tDSDHI SPIDS Deassertion to Data High Impedance (SPI2) 0 10.5 ns
tDDSPIDS SPICLK Edge to Data Out Valid (Data Out Delay Time) 9.5 ns
tHDSPIDS SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 × tPCLK ns
tDSOV SPIDS Assertion to Data Out Valid (CPHASE = 0) 5 × tPCLK ns
1
The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the “Serial Peripheral Interface Port” chapter of
the ADSP-214xx SHARC Processor Hardware Reference.

SPIDS
(INPUT)

tSPICHS tSPICLS tSPICLKS tHDS tSDPPW


SPICLK
(CP = 0,
CP = 1)
(INPUT)
tSDSCO
tDDSPIDS tDSDHI
tDSOE
tDDSPIDS tHDSPIDS

MISO
(OUTPUT)

CPHASE = 1 tSSPIDS tHSPIDS

MOSI
(INPUT)

tHDSPIDS
tDSDHI

MISO
(OUTPUT)
tDSOV
tHSPIDS
CPHASE = 0
tSSPIDS

MOSI
(INPUT)

Figure 35. SPI Slave Timing

Rev. I | Page 51 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Media Local Bus
All the numbers given are applicable for all speed modes (1024 FS, 512 FS and 256 FS for 3-pin; 512 FS and 256 FS for 5-pin), unless
otherwise specified. Refer to the MediaLB specification document revision 3.0 for more details.

Table 52. MLB Interface, 3-Pin Specifications

Parameter Min Typ Max Unit


3-Pin Characteristics
tMLBCLK MLB Clock Period
1024 FS 20.3 ns
512 FS 40 ns
256 FS 81 ns
tMCKL MLBCLK Low Time
1024 FS 6.1 ns
512 FS 14 ns
256 FS 30 ns
tMCKH MLBCLK High Time
1024 FS 9.3 ns
512 FS 14 ns
256 FS 30 ns
tMCKR MLBCLK Rise Time (VIL to VIH)
1024 FS 1 ns
512 FS/256 FS 3 ns
tMCKF MLBCLK Fall Time (VIH to VIL)
1024 FS 1 ns
512 FS/256 FS 3 ns
tMPWV1 MLBCLK Pulse Width Variation
1024 FS 0.7 nspp
512 FS/256 2.0 nspp
tDSMCF DAT/SIG Input Setup Time 1 ns
tDHMCF DAT/SIG Input Hold Time 2 ns
tMCFDZ DAT/SIG Output Time to Three-state 0 15 ns
tMCDRV DAT/SIG Output Data Delay From MLBCLK Rising Edge 8 ns
2
tMDZH Bus Hold Time
1024 FS 2 ns
512 FS/256 4 ns
CMLB DAT/SIG Pin Load
1024 FS 40 pf
512 FS/256 60 pf
1
Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (pp).
2
The board must be designed to ensure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be
minimized while meeting the maximum capacitive load listed.

Rev. I | Page 52 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
MLBSIG/
MLBDAT VALID
(Rx, Input)

tDHMCF
tDSMCF

tMCKH tMCKL

MLBCLK tMCKR
tMCKF

tMLBCLK

tMCFDZ
tMCDRV

tMDZH

MLBSIG/
MLBDAT VALID
(Tx, Output)

Figure 36. MLB Timing (3-Pin Interface)

Table 53. MLB Interface, 5-Pin Specifications

Parameter Min Typ Max Unit


5-Pin Characteristics
tMLBCLK MLB Clock Period
512 FS 40 ns
256 FS 81 ns
tMCKL MLBCLK Low Time
512 FS 15 ns
256 FS 30 ns
tMCKH MLBCLK High Time
512 FS 15 ns
256 FS 30 ns
tMCKR MLBCLK Rise Time (VIL to VIH) 6 ns
tMCKF MLBCLK Fall Time (VIH to VIL) 6 ns
1
tMPWV MLBCLK Pulse Width Variation 2 nspp
tDSMCF2 DAT/SIG Input Setup Time 3 ns
tDHMCF DAT/SIG Input Hold Time 5 ns
tMCDRV DS/DO Output Data Delay From MLBCLK Rising Edge 8 ns
tMCRDL3 DO/SO Low From MLBCLK High
512 FS 10 ns
256 FS 20 ns
CMLB DS/DO Pin Load 40 pf
1
Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (pp).
2
Gate Delays due to OR'ing logic on the pins must be accounted for.
3
When a node is not driving valid data onto the bus, the MLBSO and MLBDO output lines shall remain low. If the output lines can float at anytime, including while in reset,
external pull-down resistors are required to keep the outputs from corrupting the MediaLB signal lines when not being driven.

Rev. I | Page 53 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
MLBSIG/
MLBDAT VALID
(Rx, Input)

tDHMCF
tDSMCF

tMCKH tMCKL

MLBCLK tMCKR
tMCKF

tMLBCLK
tMCRDL

tMCDRV

MLBSO/ VALID
MLBDO
(Tx, Output)

Figure 37. MLB Timing (5-Pin Interface)

MLBCLK

tMPWV tMPWV

Figure 38. MLB 3-Pin and 5-Pin MLBCLK Pulse Width Variation Timing

Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing


For information on the UART port receive and transmit operations, see the ADSP-214xx SHARC Processor Hardware Reference.
2-Wire Interface (TWI)—Receive and Transmit Timing
For information on the TWI receive and transmit operations, see the ADSP-214xx SHARC Processor Hardware Reference.

Rev. I | Page 54 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
JTAG Test Access Port and Emulation

Table 54. JTAG Test Access Port and Emulation

Parameter Min Max Unit


Timing Requirements
tTCK TCK Period 20 ns
tSTAP TDI, TMS Setup Before TCK High 5 ns
tHTAP TDI, TMS Hold After TCK High 6 ns
tSSYS1 System Inputs Setup Before TCK High 7 ns
1
tHSYS System Inputs Hold After TCK High 18 ns
tTRSTW TRST Pulse Width 4tCK ns
Switching Characteristics
tDTDO TDO Delay from TCK Low 10 ns
2
tDSYS System Outputs Delay After TCK Low tTCK ÷ 2 + 7 ns
1
System Inputs = DATA15–0, CLK_CFG1–0, RESET, BOOT_CFG2–0, DAI_Px, DPI_Px, and FLAG3–0.
2
System Outputs = DAI_Px, DPI_Px ADDR23–0, AMI_RD, AMI_WR, FLAG3–0, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, SDCLK and EMU.

tTCK

TCK

tSTAP tHTAP

TMS
TDI

tDTDO

TDO

tSSYS tHSYS

SYSTEM
INPUTS

tDSYS

SYSTEM
OUTPUTS

Figure 39. IEEE 1149.1 JTAG Test Access Port

Rev. I | Page 55 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
OUTPUT DRIVE CURRENTS
TESTER PIN ELECTRONICS
Figure 40 shows typical I-V characteristics for the output driv- 50:
ers of the ADSP-2148x, and Table 55 shows the pins associated VLOAD
T1
DUT
with each driver. The curves represent the current drive capabil- OUTPUT
45:
ity of the output drivers as a function of output voltage. 70:

ZO = 50:(impedance)
50:
Table 55. Driver Types 0.5pF
TD = 4.04 r 1.18 ns
4pF 2pF
Driver Type Associated Pins
400:
A FLAG[0–3], AMI_ADDR[0–23], DATA[0–15],
AMI_RD, AMI_WR, AMI_ACK, MS[1-0], SDRAS,
SDCAS, SDWE, SDDQM, SDCKE, SDA10, EMU, TDO, NOTES:
RESETOUT, DPI[1–14], DAI[1–20], WDTRSTO, THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE
MLBDAT, MLBSIG, MLBSO, MLBDO, MLBCLK EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
B SDCLK
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

200
Figure 41. Equivalent Device Loading for AC Measurements
150 (Includes All Fixtures)
SOURCE/SINK (VDDEXT) CURRENT (mA)

TYPE B VOH 3.13 V, 125 °C

100
TYPE A
CAPACITIVE LOADING
50
Output delays and holds are based on standard capacitive loads:
0
30 pF on all pins (see Figure 41). Figure 45 and Figure 46 show
TYPE A
graphically how output delays and holds vary with load capaci-
-50 tance. The graphs of Figure 43 through Figure 46 may not be
linear outside the ranges shown for Typical Output Delay vs.
-100 TYPE B Load Capacitance and Typical Output Rise Time (20% to 80%,
-150
V = Min) vs. Load Capacitance.
VOL 3.13 V, 125 °C
-200
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 7
SWEEP (VDDEXT) VOLTAGE (V)

6
TYPE A DRIVE FALL
Figure 40. Typical Drive at Junction Temperature
y = 0.0414x + 0.2661

5 TYPE A DRIVE RISE


TEST CONDITIONS
RISE AND FALL TIMES (ns)

y = 0.0341x + 0.3093

The ac signal specifications (timing parameters) appear in 4


Table 21 through Table 54. These include output disable time, TYPE B DRIVE RISE
y = 0.0153x + 0.2131
output enable time, and capacitive loading. The timing specifi- 3
cations for the SHARC apply for the voltage reference levels in
Figure 41. 2

Timing is measured on signals when they cross the 1.5 V level as TYPE B DRIVE FALL
1 y = 0.0152x + 0.1882
described in Figure 42. All delays (in nanoseconds) are mea-
sured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V. 0
0 25 50 75 100 125 150 175 200
LOAD CAPACITANCE (pF)

Figure 43. Typical Output Rise/Fall Time (20% to 80%, VDD_EXT = Max)

INPUT
OR 1.5V 1.5V
OUTPUT

Figure 42. Voltage Reference Levels for AC Measurements

Rev. I | Page 56 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
THERMAL CHARACTERISTICS
14
The ADSP-2148x processor is rated for performance over the
12 TYPE A DRIVE FALL
temperature range specified in Operating Conditions.
y = 0.0747x + 0.5154
The JESD51 package thermal characteristics in this section are
10
provided for package comparison and estimation purposes only.
RISE AND FALL TIMES (ns)

TYPE A DRIVE RISE


y = 0.0571x + 0.5558
They are not intended for accurate system temperature calcula-
8
tion. System thermal simulation is required for accurate
6
TYPE B DRIVE FALL
y = 0.0278x + 0.3138
temperature analysis that accounts for all specific 3D system
design features, including, but not limited to other heat sources,
4 use of heat-sinks, and the system enclosure. Contact Analog
TYPE B DRIVE RISE
Devices for package thermal models that are intended for use
2 y = 0.0258x + 0.3684 with thermal simulation tools.
In Table 56, Table 57, and Table 58, airflow measurements com-
0
0 25 50 75 100 125 150 175 200 ply with JEDEC standards JESD51-2 and JESD51-6, and the
LOAD CAPACITANCE (pF)
junction-to-board measurement complies with JESD51-8. Test
board design complies with JEDEC standards JESD51-7 (LQF-
Figure 44. Typical Output Rise/Fall Time (20% to 80%, VDD_EXT = Min) P_EP). The junction-to-case measurement complies with MIL-
STD-883. All measurements use a 2S2P JEDEC test board.

4.5
To estimate the junction temperature of a single device while on
TYPE A DRIVE FALL
a JEDEC 2S2P PCB, use:
y = 0.0196x + 1.2945 TYPE A DRIVE RISE
4
y = 0.0152x + 1.7607
T J = T CASE +   JT  P D 
RISE AND FALL DELAY (ns)

3.5
TYPE B DRIVE RISE
3
y = 0.0068x + 1.7614 where:

2.5
TJ = junction temperature °C
TYPE B DRIVE FALL TCASE = case temperature (°C) measured at the top center of the
2 y = 0.0074x + 1.421
package
1.5
JT = junction-to-top (of package) characterization parameter
1 is the typical value from Table 56, Table 57, and Table 58.

0.5
PD = power dissipation
Values of JA are provided for package comparison and PCB
design considerations. JA can be used for a first-order approxi-
0
0 25 50 75 100 125 150 175 200
LOAD CAPACITANCE (pF) mation of TJ by the equation:

Figure 45. Typical Output Rise/Fall Delay (VDD_EXT = Max) T J = T A +   JA  P D 

where:
9
TA = ambient temperature °C
8
TYPE A DRIVE RISE
TYPE A DRIVE FALL
y = 0.0256x + 3.5859
y = 0.0359x + 2.924
RISE AND FALL TIMES DELAY (ns)

7
TYPE B DRIVE RISE
6 y = 0.0116x + 3.5697

3 TYPE B DRIVE FALL


y = 0.0136x + 3.1135

0
0 25 50 75 100 125 150 175 200
LOAD CAPACITANCE (pF)

Figure 46. Typical Output Rise/Fall Delay (VDD_EXT = Min)

Rev. I | Page 57 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Note that the thermal characteristics values provided in Thermal Diode
Table 56, Table 57, and Table 58 are modeled values.
The ADSP-2148x processors incorporate thermal diode/s to
monitor the die temperature. The thermal diode of is a
Table 56. Thermal Characteristics for 88-Lead LFCSP_VQ
grounded collector, PNP Bipolar Junction Transistor (BJT). The
Parameter Condition Typical Unit THD_P pin is connected to the emitter and the THD_M pin is
connected to the base of the transistor. These pins can be used
JA Airflow = 0 m/s 22.6 °C/W
by an external temperature sensor (such as ADM 1021A or
JMA Airflow = 1 m/s 18.2 °C/W LM86 or others) to read the die temperature of the chip.
JMA Airflow = 2 m/s 17.3 °C/W
The technique used by the external temperature sensor is to
JC 7.9 °C/W measure the change in VBE when the thermal diode is operated
JT Airflow = 0 m/s 0.22 °C/W at two different currents. This is shown in the following
JMT Airflow = 1 m/s 0.36 °C/W equation:
JMT Airflow = 2 m/s 0.44 °C/W
kT
Table 57. Thermal Characteristics for 100-Lead LQFP_EP V BE = n  ------  In(N)
q
Parameter Condition Typical Unit where:
JA Airflow = 0 m/s 17.8 °C/W n = multiplication factor close to 1, depending on process
JMA Airflow = 1 m/s 15.4 °C/W variations
JMA Airflow = 2 m/s 14.6 °C/W k = Boltzmann’s constant
JC 2.4 °C/W
T = temperature (°C)
JT Airflow = 0 m/s 0.24 °C/W
q = charge of the electron
JMT Airflow = 1 m/s 0.37 °C/W
N = ratio of the two currents
JMT Airflow = 2 m/s 0.51 °C/W
The two currents are usually in the range of 10 micro Amperes
Table 58. Thermal Characteristics for 176-Lead LQFP_EP to 300 micro Amperes for the common temperature sensor
chips available.
Parameter Condition Typical Unit
Table 59 contains the thermal diode specifications using the
JA Airflow = 0 m/s 16.9 °C/W transistor model.
JMA Airflow = 1 m/s 14.6 °C/W
JMA Airflow = 2 m/s 13.8 °C/W
JC 2.3 °C/W
JT Airflow = 0 m/s 0.21 °C/W
JMT Airflow = 1 m/s 0.32 °C/W
JMT Airflow = 2 m/s 0.41 °C/W

Table 59. Thermal Diode Parameters – Transistor Model1

Symbol Parameter Min Typ Max Unit


IFW2 Forward Bias Current 10 300 μA
IE Emitter Current 10 300 μA
nQ3, 4 Transistor Ideality 1.012 1.015 1.017
RT3, 5 Series Resistance 0.12 0.2 0.28 Ω
1
See Engineer-to-Engineer Note Using the On-Chip Thermal Diode on Analog Devices Processors (EE-346).
2
Analog Devices does not recommend operation of the thermal diode under reverse bias.
3
Specified by design characterization.
4
The ideality factor, nQ, represents the deviation from ideal diode behavior as exemplified by the diode equation: IC = IS × (e qVBE/nqkT –1) where IS = saturation current,
q = electronic charge, VBE = voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin).
5
The series resistance (RT) can be used for more accurate readings as needed.

Rev. I | Page 58 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
88-LEAD LFCSP_VQ LEAD ASSIGNMENT
Table 60 lists the 88-Lead LFCSP_VQ package lead names.

Table 60. 88-Lead LFCSP_VQ Lead Assignments (Numerical by Lead Number)

Lead Name Lead No. Lead Name Lead No. Lead Name Lead No. Lead Name Lead No.
CLK_CFG1 1 VDD_EXT 23 DAI_P10 45 VDD_INT 67
BOOT_CFG0 2 DPI_P08 24 VDD_INT 46 FLAG0 68
VDD_EXT 3 DPI_P07 25 VDD_EXT 47 VDD_INT 69
VDD_INT 4 DPI_P09 26 DAI_P20 48 FLAG1 70
BOOT_CFG1 5 DPI_P10 27 VDD_INT 49 FLAG2 71
GND 6 DPI_P11 28 DAI_P08 50 FLAG3 72
CLK_CFG0 7 DPI_P12 29 DAI_P04 51 GND 73
VDD_INT 8 DPI_P13 30 DAI_P14 52 GND 74
CLKIN 9 DAI_P03 31 DAI_P18 53 VDD_EXT 75
XTAL 10 DPI_P14 32 DAI_P17 54 GND 76
VDD_EXT 11 VDD_INT 33 DAI_P16 55 VDD_INT 77
VDD_INT 12 DAI_P13 34 DAI_P15 56 TRST 78
VDD_INT 13 DAI_P07 35 DAI_P12 57 EMU 79
RESETOUT/RUNRSTIN 14 DAI_P19 36 DAI_P11 58 TDO 80
VDD_INT 15 DAI_P01 37 VDD_INT 59 VDD_EXT 81
DPI_P01 16 DAI_P02 38 GND 60 VDD_INT 82
DPI_P02 17 VDD_INT 39 THD_M 61 TDI 83
DPI_P03 18 VDD_EXT 40 THD_P 62 TCK 84
VDD_INT 19 VDD_INT 41 VDD_THD 63 VDD_INT 85
DPI_P05 20 DAI_P06 42 VDD_INT 64 RESET 86
DPI_P04 21 DAI_P05 43 VDD_INT 65 TMS 87
DPI_P06 22 DAI_P09 44 VDD_INT 66 VDD_INT 88
GND 89*
* Lead no. 89 is the GND supply (see Figure 47 and Figure 48) for the processor; this pad must be robustly connected to GND for the processor
to function.

Rev. I | Page 59 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Figure 47 shows the top view of the 88-lead LFCSP_VQ pin configuration. Figure 48 shows the bottom view.

LEAD 88 LEAD 67

LEAD 1 LEAD 66

LEAD 1 INDICATOR
ADSP-2148x
88-LEAD LFCSP_VQ
TOP VIEW

LEAD 22 LEAD 45
LEAD 23 LEAD 44

Figure 47. 88-Lead LFCSP_VQ Lead Configuration (Top View)

LEAD 67 LEAD 88

LEAD 66 LEAD 1

ADSP-2148x
88-LEAD LFCSP_VQ GND PAD
LEAD 1 INDICATOR
BOTTOM VIEW (LEAD 89)

LEAD 45 LEAD 22
LEAD 44 LEAD 23

Figure 48. 88-Lead LFCSP_VQ Lead Configuration (Bottom View)

Rev. I | Page 60 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
100-LEAD LQFP_EP LEAD ASSIGNMENT
Table 61. 100-Lead LQFP_EP Lead Assignments (Numerical by Lead Number)

Lead Name Lead No. Lead Name Lead No. Lead Name Lead No. Lead Name Lead No.
VDD_INT 1 VDD_EXT 26 DAI_P10 51 VDD_INT 76
CLK_CFG1 2 DPI_P08 27 VDD_INT 52 FLAG0 77
BOOT_CFG0 3 DPI_P07 28 VDD_EXT 53 VDD_INT 78
VDD_EXT 4 VDD_INT 29 DAI_P20 54 VDD_INT 79
VDD_INT 5 DPI_P09 30 VDD_INT 55 FLAG1 80
BOOT_CFG1 6 DPI_P10 31 DAI_P08 56 FLAG2 81
GND 7 DPI_P11 32 DAI_P04 57 FLAG3 82
DNC 8* DPI_P12 33 DAI_P14 58 MLBCLK 83
DNC 9* DPI_P13 34 DAI_P18 59 MLBDAT 84
CLK_CFG0 10 DAI_P03 35 DAI_P17 60 MLBDO 85
VDD_INT 11 DPI_P14 36 DAI_P16 61 VDD_EXT 86
CLKIN 12 VDD_INT 37 DAI_P15 62 MLBSIG 87
XTAL 13 VDD_INT 38 DAI_P12 63 VDD_INT 88
VDD_EXT 14 VDD_INT 39 VDD_INT 64 MLBSO 89
VDD_INT 15 DAI_P13 40 DAI_P11 65 TRST 90
VDD_INT 16 DAI_P07 41 VDD_INT 66 EMU 91
RESETOUT/RUNRSTIN 17 DAI_P19 42 VDD_INT 67 TDO 92
VDD_INT 18 DAI_P01 43 GND 68 VDD_EXT 93
DPI_P01 19 DAI_P02 44 THD_M 69 VDD_INT 94
DPI_P02 20 VDD_INT 45 THD_P 70 TDI 95
DPI_P03 21 VDD_EXT 46 VDD_THD 71 TCK 96
VDD_INT 22 VDD_INT 47 VDD_INT 72 VDD_INT 97
DPI_P05 23 DAI_P06 48 VDD_INT 73 RESET 98
DPI_P04 24 DAI_P05 49 VDD_INT 74 TMS 99
DPI_P06 25 DAI_P09 50 VDD_INT 75 VDD_INT 100
GND 101**
MLB pins (pins 83, 84, 85, 87, and 89) are available for automotive models only. For non-automotive models, these pins should be connected
to ground (GND).
* Do not make any electrical connection to this pin.
** Pin no. 101 (exposed pad) is the GND supply (see Figure 49 and Figure 50) for the processor; this pad must be robustly connected to GND.

Rev. I | Page 61 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Figure 49 shows the top view of the 100-lead LQFP_EP lead configuration. Figure 50 shows the bottom view of the 100-lead LQFP_EP
lead configuration.

LEAD 100 LEAD 76

LEAD 1 LEAD 75

LEAD 1 INDICATOR
ADSP-2148x
100-LEAD LQFP_EP
TOP VIEW

LEAD 25 LEAD 51
LEAD 26 LEAD 50

Figure 49. 100-Lead LQFP_EP Lead Configuration (Top View)

LEAD 76 LEAD 100

LEAD 75 LEAD 1

ADSP-2148x
100-LEAD LQFP_EP GND PAD
LEAD 1 INDICATOR
BOTTOM VIEW (LEAD 101)

LEAD 51 LEAD 25
LEAD 50 LEAD 26

Figure 50. 100-Lead LQFP_EP Lead Configuration (Bottom View)

Rev. I | Page 62 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
176-LEAD LQFP_EP LEAD ASSIGNMENT
Table 62. ADSP-21486 176-Lead LQFP_EP Lead Assignment (Numerical by Lead Number)
Lead Name Lead No. Lead Name Lead No. Lead Name Lead No. Lead Name Lead No.
DNC 1* VDD_EXT 45 DAI_P10 89 VDD_INT 133
MS0 2 DPI_P08 46 VDD_INT 90 FLAG0 134
DNC 3* DPI_P07 47 VDD_EXT 91 FLAG1 135
VDD_INT 4 VDD_INT 48 DAI_P20 92 FLAG2 136
CLK_CFG1 5 DPI_P09 49 VDD_INT 93 GND 137
ADDR0 6 DPI_P10 50 DAI_P08 94 FLAG3 138
BOOT_CFG0 7 DPI_P11 51 DAI_P14 95 GND 139
VDD_EXT 8 DPI_P12 52 DAI_P04 96 GND 140
ADDR1 9 DPI_P13 53 DAI_P18 97 VDD_EXT 141
ADDR2 10 DPI_P14 54 DAI_P17 98 GND 142
ADDR3 11 DAI_P03 55 DAI_P16 99 VDD_INT 143
ADDR4 12 DNC 56* DAI_P12 100 TRST 144
ADDR5 13 VDD_EXT 57 DAI_P15 101 GND 145
BOOT_CFG1 14 DNC 58* VDD_INT 102 EMU 146
GND 15 DNC 59* DAI_P11 103 DATA0 147
ADDR6 16 DNC 60* VDD_EXT 104 DATA1 148
ADDR7 17 DNC 61* VDD_INT 105 DATA2 149
DNC 18* VDD_INT 62 BOOT_CFG2 106 DATA3 150
DNC 19* DNC 63* VDD_INT 107 TDO 151
ADDR8 20 DNC 64* AMI_ACK 108 DATA4 152
ADDR9 21 VDD_INT 65 GND 109 VDD_EXT 153
CLK_CFG0 22 DNC 66* THD_M 110 DATA5 154
VDD_INT 23 DNC 67* THD_P 111 DATA6 155
CLKIN 24 VDD_INT 68 VDD_THD 112 VDD_INT 156
XTAL 25 DNC 69* VDD_INT 113 DATA7 157
ADDR10 26 WDTRSTO 70 VDD_INT 114 TDI 158
DNC 27* DNC 71* MS1 115 DNC 159*
VDD_EXT 28 VDD_EXT 72 VDD_INT 116 VDD_EXT 160
VDD_INT 29 DAI_P07 73 WDT_CLKO 117 DATA8 161
ADDR11 30 DAI_P13 74 WDT_CLKIN 118 DATA9 162
ADDR12 31 DAI_P19 75 VDD_EXT 119 DATA10 163
ADDR17 32 DAI_P01 76 ADDR23 120 TCK 164
ADDR13 33 DAI_P02 77 ADDR22 121 DATA11 165
VDD_INT 34 VDD_INT 78 ADDR21 122 DATA12 166
ADDR18 35 DNC 79* VDD_INT 123 DATA14 167
RESETOUT/RUNRSTIN 36 DNC 80* ADDR20 124 DATA13 168
VDD_INT 37 DNC 81* ADDR19 125 VDD_INT 169
DPI_P01 38 DNC 82* VDD_EXT 126 DATA15 170
DPI_P02 39 DNC 83* ADDR16 127 DNC 171*
DPI_P03 40 VDD_EXT 84 ADDR15 128 DNC 172*
VDD_INT 41 VDD_INT 85 VDD_INT 129 RESET 173
DPI_P05 42 DAI_P06 86 ADDR14 130 TMS 174
DPI_P04 43 DAI_P05 87 AMI_WR 131 DNC 175*
DPI_P06 44 DAI_P09 88 AMI_RD 132 VDD_INT 176
GND 177**
* Do not make any electrical connection to this pin.
** Lead no. 177 (exposed pad) is the GND supply (see Figure 51 and Figure 52) for the processor; this pad must be robustly connected to GND.

Rev. I | Page 63 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Table 63. ADSP-21483, ADSP-21487, ADSP-21488, and ADSP-21489 176-Lead LQFP_EP Lead Assignment
(Numerical by Lead Number)
Lead Name Lead No. Lead Name Lead No. Lead Name Lead No. Lead Name Lead No.
SDDQM 1 VDD_EXT 45 DAI_P10 89 VDD_INT 133
MS0 2 DPI_P08 46 VDD_INT 90 FLAG0 134
SDCKE 3 DPI_P07 47 VDD_EXT 91 FLAG1 135
VDD_INT 4 VDD_INT 48 DAI_P20 92 FLAG2 136
CLK_CFG1 5 DPI_P09 49 VDD_INT 93 GND 137
ADDR0 6 DPI_P10 50 DAI_P08 94 FLAG3 138
BOOT_CFG0 7 DPI_P11 51 DAI_P14 95 GND 139
VDD_EXT 8 DPI_P12 52 DAI_P04 96 GND 140
ADDR1 9 DPI_P13 53 DAI_P18 97 VDD_EXT 141
ADDR2 10 DPI_P14 54 DAI_P17 98 GND 142
ADDR3 11 DAI_P03 55 DAI_P16 99 VDD_INT 143
ADDR4 12 DNC 56* DAI_P12 100 TRST 144
ADDR5 13 VDD_EXT 57 DAI_P15 101 GND 145
BOOT_CFG1 14 DNC 58* VDD_INT 102 EMU 146
GND 15 DNC 59* DAI_P11 103 DATA0 147
ADDR6 16 DNC 60* VDD_EXT 104 DATA1 148
ADDR7 17 DNC 61* VDD_INT 105 DATA2 149
DNC 18* VDD_INT 62 BOOT_CFG2 106 DATA3 150
DNC 19* DNC 63* VDD_INT 107 TDO 151
ADDR8 20 DNC 64* AMI_ACK 108 DATA4 152
ADDR9 21 VDD_INT 65 GND 109 VDD_EXT 153
CLK_CFG0 22 DNC 66* THD_M 110 DATA5 154
VDD_INT 23 DNC 67* THD_P 111 DATA6 155
CLKIN 24 VDD_INT 68 VDD_THD 112 VDD_INT 156
XTAL 25 DNC 69* VDD_INT 113 DATA7 157
ADDR10 26 WDTRSTO 70 VDD_INT 114 TDI 158
SDA10 27 DNC 71* MS1 115 SDCLK 159
VDD_EXT 28 VDD_EXT 72 VDD_INT 116 VDD_EXT 160
VDD_INT 29 DAI_P07 73 WDT_CLKO 117 DATA8 161
ADDR11 30 DAI_P13 74 WDT_CLKIN 118 DATA9 162
ADDR12 31 DAI_P19 75 VDD_EXT 119 DATA10 163
ADDR17 32 DAI_P01 76 ADDR23 120 TCK 164
ADDR13 33 DAI_P02 77 ADDR22 121 DATA11 165
VDD_INT 34 VDD_INT 78 ADDR21 122 DATA12 166
ADDR18 35 DNC 79* VDD_INT 123 DATA14 167
RESETOUT/RUNRSTIN 36 DNC 80* ADDR20 124 DATA13 168
VDD_INT 37 DNC 81* ADDR19 125 VDD_INT 169
DPI_P01 38 DNC 82* VDD_EXT 126 DATA15 170
DPI_P02 39 DNC 83* ADDR16 127 SDWE 171
DPI_P03 40 VDD_EXT 84 ADDR15 128 SDRAS 172
VDD_INT 41 VDD_INT 85 VDD_INT 129 RESET 173
DPI_P05 42 DAI_P06 86 ADDR14 130 TMS 174
DPI_P04 43 DAI_P05 87 AMI_WR 131 SDCAS 175
DPI_P06 44 DAI_P09 88 AMI_RD 132 VDD_INT 176
GND 177**
* Do not make any electrical connection to this pin.
** Lead no. 177 (exposed pad) is the GND supply (see Figure 51 and Figure 52) for the processor; this pad must be robustly connected to GND.

Rev. I | Page 64 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Table 64. Automotive Models ADSP-21488, and ADSP-21489 176-Lead LQFP_EP Lead Assignment (Numerical by Lead Number)
Lead Name Lead No. Lead Name Lead No. Lead Name Lead No. Lead Name Lead No.
SDDQM 1 VDD_EXT 45 DAI_P10 89 VDD_INT 133
MS0 2 DPI_P08 46 VDD_INT 90 FLAG0 134
SDCKE 3 DPI_P07 47 VDD_EXT 91 FLAG1 135
VDD_INT 4 VDD_INT 48 DAI_P20 92 FLAG2 136
CLK_CFG1 5 DPI_P09 49 VDD_INT 93 MLBCLK 137
ADDR0 6 DPI_P10 50 DAI_P08 94 FLAG3 138
BOOT_CFG0 7 DPI_P11 51 DAI_P14 95 MLBDAT 139
VDD_EXT 8 DPI_P12 52 DAI_P04 96 MLBDO 140
ADDR1 9 DPI_P13 53 DAI_P18 97 VDD_EXT 141
ADDR2 10 DPI_P14 54 DAI_P17 98 MLBSIG 142
ADDR3 11 DAI_P03 55 DAI_P16 99 VDD_INT 143
ADDR4 12 DNC 56* DAI_P12 100 TRST 144
ADDR5 13 VDD_EXT 57 DAI_P15 101 MLBSO 145
BOOT_CFG1 14 DNC 58* VDD_INT 102 EMU 146
GND 15 DNC 59* DAI_P11 103 DATA0 147
ADDR6 16 DNC 60* VDD_EXT 104 DATA1 148
ADDR7 17 DNC 61* VDD_INT 105 DATA2 149
DNC 18* VDD_INT 62 BOOT_CFG2 106 DATA3 150
DNC 19* DNC 63* VDD_INT 107 TDO 151
ADDR8 20 DNC 64* AMI_ACK 108 DATA4 152
ADDR9 21 VDD_INT 65 GND 109 VDD_EXT 153
CLK_CFG0 22 DNC 66* THD_M 110 DATA5 154
VDD_INT 23 DNC 67* THD_P 111 DATA6 155
CLKIN 24 VDD_INT 68 VDD_THD 112 VDD_INT 156
XTAL 25 DNC 69* VDD_INT 113 DATA7 157
ADDR10 26 WDTRSTO 70 VDD_INT 114 TDI 158
SDA10 27 DNC 71* MS1 115 SDCLK 159
VDD_EXT 28 VDD_EXT 72 VDD_INT 116 VDD_EXT 160
VDD_INT 29 DAI_P07 73 WDT_CLKO 117 DATA8 161
ADDR11 30 DAI_P13 74 WDT_CLKIN 118 DATA9 162
ADDR12 31 DAI_P19 75 VDD_EXT 119 DATA10 163
ADDR17 32 DAI_P01 76 ADDR23 120 TCK 164
ADDR13 33 DAI_P02 77 ADDR22 121 DATA11 165
VDD_INT 34 VDD_INT 78 ADDR21 122 DATA12 166
ADDR18 35 DNC 79* VDD_INT 123 DATA14 167
RESETOUT/RUNRSTIN 36 DNC 80* ADDR20 124 DATA13 168
VDD_INT 37 DNC 81* ADDR19 125 VDD_INT 169
DPI_P01 38 DNC 82* VDD_EXT 126 DATA15 170
DPI_P02 39 DNC 83* ADDR16 127 SDWE 171
DPI_P03 40 VDD_EXT 84 ADDR15 128 SDRAS 172
VDD_INT 41 VDD_INT 85 VDD_INT 129 RESET 173
DPI_P05 42 DAI_P06 86 ADDR14 130 TMS 174
DPI_P04 43 DAI_P05 87 AMI_WR 131 SDCAS 175
DPI_P06 44 DAI_P09 88 AMI_RD 132 VDD_INT 176
GND 177**
* Do not make any electrical connection to this pin.
** Lead no. 177 (exposed pad) is the GND supply (see Figure 51 and Figure 52) for the processor; this pad must be robustly connected to GND.

Rev. I | Page 65 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Figure 51 shows the top view of the 176-lead LQFP_EP lead configuration. Figure 52 shows the bottom view of the 176-lead LQFP_EP
lead configuration.

LEAD 176 LEAD 133

LEAD 1 LEAD 132

LEAD 1 INDICATOR
ADSP-2148x
176-LEAD LQFP_EP
TOP VIEW

LEAD 44 LEAD 89
LEAD 45 LEAD 88

Figure 51. 176-Lead LQFP_EP Lead Configuration (Top View)

LEAD 133 LEAD 176

LEAD 132 LEAD 1

ADSP-2148x
176-LEAD LQFP_EP GND PAD
LEAD 1 INDICATOR
BOTTOM VIEW (LEAD 177)

LEAD 89 LEAD 44
LEAD 88 LEAD 45

Figure 52. 176-Lead LQFP_EP Lead Configuration (Bottom View)

Rev. I | Page 66 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
OUTLINE DIMENSIONS
The ADSP-2148x processors are available in 88-lead LFCSP_VQ, 100-lead LQFP_EP, and 176-lead LQFP_EP RoHS compliant packages.

12.10 0.30
12.00 SQ 0.60 MAX 0.23
11.90 0.60 0.18
MAX
PIN 1
67 88 INDICATOR
66 1
PIN 1
INDICATOR

11.85 0.50
11.75 SQ BSC 6.80
EXPOSED
11.65 PAD 6.70 SQ
6.60

0.50
0.40 45 22
44 23
0.30
TOP VIEW BOTTOM VIEW

0.70 10.50
0.65 REF
*0.90 12° MAX
0.60 0.045 FOR PROPER CONNECTION OF
0.85 THE EXPOSED PAD, REFER TO
0.75 0.025 THE PIN CONFIGURATION AND
0.005 FUNCTION DESCRIPTIONS
SEATING COPLANARITY SECTION OF THIS DATA SHEET.
PLANE 0.08
0.138~0.194 REF

*COMPLIANT TO JEDEC STANDARDS MO-220-VRRD


EXCEPT FOR MINIMUM THICKNESS AND LEAD COUNT.

Figure 53. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ1]


(CP-88-5)
Dimensions shown in millimeters
1
For information relating to the exposed pad on the CP-88-5 package, see the table endnote on Page 59.

16.20
16.00 SQ
1.60 15.80 14.20
MAX
0.75 14.00 SQ
12.00 REF
0.60 13.80
0.45 100 76 76 100
1 75 75 1
1.00 REF
PIN 1
SEATING
PLANE
EXPOSED
PAD 6.00 BSC
SQ

TOP VIEW BOTTOM VIEW


1.45 (PINS DOWN) (PINS UP)
25 51 51 25
1.40 0.20 26 50 26
50
1.35 0.09
0.27
VIEW A
0.22 FOR PROPER CONNECTION OF
0.15 7° 0.50 THE EXPOSED PAD, REFER TO
BSC 0.17
0.05 0.08 0° “SURFACE-MOUNT DESIGN” IN
LEAD PITCH THIS DATA SHEET.
COPLANARITY

VIEW A
ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BED-HD

Figure 54. 100-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP]1
(SW-100-2)
Dimensions shown in millimeters
1
For information relating to the exposed pad on the SW-100-2 package, see the table endnote on Page 61.

Rev. I | Page 67 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
26.20
26.00 SQ
25.80 24.10
1.60 MAX
0.75 24.00 SQ
21.50 REF
0.60 23.90
0.45 176 133 133 176
1 132 132 1
1.00 REF

SEATING PIN 1
PLANE

EXPOSED 6.00 BSC


PAD SQ

1.45 0.20
1.40 0.15
1.35 0.09
0.15 7° TOP VIEW BOTTOM VIEW
0.10 3.5° (PINS DOWN) (PINS UP)
0.05 44 89 89 44
0.08 0°
COPLANARITY 45 88 88 45

0.27
VIEW A 0.50
VIEW A 0.22
ROTATED 90° CCW BSC 0.17
LEAD PITCH
FOR PROPER CONNECTION
OF THE EXPOSED PAD, REFER
TO “SURFACE-MOUNT DESIGN”
COMPLIANT TO JEDEC STANDARDS MS-026-BGA-HD IN THIS DATA SHEET.

Figure 55. 176-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP]1
(SW-176-2)
Dimensions shown in millimeters
1
For information relating to the exposed pad on the SW-176-2 package, see the table endnote on Page 63.

SURFACE-MOUNT DESIGN
The exposed pad is required to be electrically and thermally
connected to GND. Implement this by soldering the exposed
pad to a GND PCB land that is the same size as the exposed pad.
The GND PCB land should be robustly connected to the GND
plane in the PCB for best electrical and thermal performance.
No separate GND pins are provided in the package.

Rev. I | Page 68 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
AUTOMOTIVE PRODUCTS
The following models are available with controlled manufactur- this data sheet carefully. Only the automotive grade products
ing to support the quality and reliability requirements of shown in Table 65 are available for use in automotive applica-
automotive applications. Note that these automotive models tions. Contact your local Analog Devices account representative
may have specifications that differ from the commercial models; for specific product ordering information and to obtain the spe-
therefore designers should review the Specifications section of cific Automotive Reliability reports for these models.

Table 65. Automotive Products

Processor
Instruction
Model1, 2, 3, 4 Notes Temperature Range5 RAM Rate (Max) Package Description Package Option
6
AD21486WBSWZ4Axx –40°C to +125°C 5 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2
AD21488WBCPZ2202 –40°C to +125°C 2 Mbit 300 MHz 88-Lead LFCSP_VQ CP-88-5
AD21488WBCPZ4202 –40°C to +125°C 2 Mbit 400 MHz 88-Lead LFCSP_VQ CP-88-5
AD21488WBCPZ202 –40°C to +125°C 3 Mbit 300 MHz 88-Lead LFCSP_VQ CP-88-5
AD21488WBCPZ302 –40°C to +125°C 3 Mbit 350 MHz 88-Lead LFCSP_VQ CP-88-5
AD21488WBCPZ402 –40°C to +125°C 3 Mbit 400 MHz 88-Lead LFCSP_VQ CP-88-5
AD21488WBSWZ1Axx –40°C to +125°C 3 Mbit 266 MHz 100-Lead LQFP_EP SW-100-2
AD21488WBSWZ2Axx –40°C to +125°C 3 Mbit 300 MHz 100-Lead LQFP_EP SW-100-2
AD21488WBSWZ1Bxx –40°C to +125°C 2 Mbit 266 MHz 176-Lead LQFP_EP SW-176-2
AD21488WBSWZ2Bxx –40°C to +125°C 3 Mbit 266 MHz 176-Lead LQFP_EP SW-176-2
AD21488WBSWZ4Bxx –40°C to +125°C 3 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2
AD21489WBCPZ202 –40°C to +125°C 5 Mbit 300 MHz 88-Lead LFCSP_VQ CP-88-5
AD21489WBCPZ302 –40°C to +125°C 5 Mbit 350 MHz 88-Lead LFCSP_VQ CP-88-5
AD21489WBCPZ402 –40°C to +125°C 5 Mbit 400 MHz 88-Lead LFCSP_VQ CP-88-5
AD21489WBSWZ4xx –40°C to +125°C 5 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2
AD21489WBSWZ4xxRL –40°C to +125°C 5 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2
AD21489WBSWZ4Bxx –40°C to +125°C 5 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2
1
Z =RoHS Compliant Part.
2
W = automotive applications.
3
xx denotes the current die revision.
4
RL = Tape and Reel.
5
Referenced temperature is junction temperature. See Operating Conditions for junction temperature (TJ) specification.
6
This product contains IP from Dolby, DTS and DTLA. Proper software licenses required. Contact Analog Devices, Inc. for information.

Rev. I | Page 69 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
ORDERING GUIDE

Processor
Instruction
Model1, 2 Notes Temperature Range3 RAM Rate (Max) Package Description Package Option
4
ADSP-21483KSWZ-2B 0°C to +110°C 3 Mbit 300 MHz 176-Lead LQFP_EP SW-176-2
4
ADSP-21483KSWZ-3B 0°C to +110°C 3 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2
4
ADSP-21483KSWZ-3AB 0°C to +110°C 3 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2
4
ADSP-21483KSWZ-4B 0°C to +110°C 3 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2
4
ADSP-21483KSWZ-4AB 0°C to +110°C 3 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2
4
ADSP-21486KSWZ-2A 0°C to +110°C 5 Mbit 300 MHz 100-Lead LQFP_EP SW-100-2
4
ADSP-21486KSWZ-2B 0°C to +110°C 5 Mbit 300 MHz 176-Lead LQFP_EP SW-176-2
4
ADSP-21486KSWZ-2AB 0°C to +110°C 5 Mbit 300 MHz 100-Lead LQFP_EP SW-100-2
4
ADSP-21486KSWZ-2BB 0°C to +110°C 5 Mbit 300 MHz 176-Lead LQFP_EP SW-176-2
4
ADSP-21486KSWZ-3A 0°C to +110°C 5 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2
4
ADSP-21486KSWZ-3B 0°C to +110°C 5 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2
4
ADSP-21486KSWZ-3AB 0°C to +110°C 5 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2
4
ADSP21486KSWZ3ABRL 0°C to +110°C 5 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2
4
ADSP-21486KSWZ-3BB 0°C to +110°C 5 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2
4
ADSP-21486KSWZ-4A 0°C to +110°C 5 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2
4
ADSP-21486KSWZ-4AB 0°C to +110°C 5 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2
4
ADSP-21487KCPZ-4 0°C to +115°C 5 Mbit 400 MHz 88-Lead LFCSP_VQ CP-88-5
4
ADSP-21487KSWZ-2B 0°C to +110°C 5 Mbit 300 MHz 176-Lead LQFP_EP SW-176-2
4
ADSP-21487KSWZ-2BB 0°C to +110°C 5 Mbit 300 MHz 176-Lead LQFP_EP SW-176-2
4
ADSP-21487KSWZ-3B 0°C to +110°C 5 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2
4
ADSP-21487KSWZ-3BB 0°C to +110°C 5 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2
4
ADSP-21487KSWZ-4B 0°C to +110°C 5 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2
4
ADSP-21487KSWZ-4BB 0°C to +110°C 5 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2
4, 5
ADSP-21487KSWZ-5B 0°C to +115°C 5 Mbit 450 MHz 176-Lead LQFP_EP SW-176-2
4, 5
ADSP-21487KSWZ-5BB 0°C to +115°C 5 Mbit 450 MHz 176-Lead LQFP_EP SW-176-2
4, 5
ADSP21487KSWZ5BBRL 0°C to +115C 5 Mbit 450 MHz 176-Lead LQFP_EP SW-176-2
ADSP-21488BSWZ-3A –40°C to +125°C 3 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2
ADSP-21488KSWZ-3A 0°C to +110°C 3 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2
6
ADSP-21488KSWZ-3A1 0°C to +110°C 3 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2
ADSP-21488KSWZ-3B 0°C to +110C 3 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2
ADSP-21488BSWZ-3B –40°C to +125°C 3 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2
ADSP-21488KSWZ-4A 0°C to +110°C 3 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2
ADSP-21488BSWZ-4A –40°C to +125°C 3 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2
ADSP-21488KSWZ-4B 0°C to +110°C 3 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2
ADSP-21488BSWZ-4B –40°C to +125°C 3 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2
6
ADSP-21488KSWZ-4B1 0°C to +110°C 3 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2

Rev. I | Page 70 of 71 | February 2024


ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Processor
Instruction
Model1, 2 Notes Temperature Range3 RAM Rate (Max) Package Description Package Option
ADSP-21489KCPZ-4 0°C to +115°C 5 Mbit 400 MHz 88-Lead LFCSP_VQ CP-88-5
ADSP-21489KSWZ-3A 0°C to +110°C 5 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2
ADSP-21489BSWZ-3A –40°C to +125°C 5 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2
ADSP-21489KSWZ-3B 0°C to +110°C 5 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2
ADSP-21489BSWZ-3B –40°C to +125°C 5 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2
ADSP-21489KSWZ-4A 0°C to +110°C 5 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2
ADSP-21489BSWZ-4A –40°C to +125°C 5 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2
ADSP-21489KSWZ-4B 0°C to +110°C 5 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2
ADSP-21489BSWZ-4B –40°C to +125°C 5 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2
5
ADSP-21489KSWZ-5B 0°C to +115°C 5 Mbit 450 MHz 176-Lead LQFP_EP SW-176-2
1
Z = RoHS compliant part.
2
RL = Tape and Reel.
3
Referenced temperature is junction temperature. See Operating Conditions for junction temperature (TJ) specification.
4
The ADSP-21483, ADSP-21486, and ADSP-21487 models are available with factory programmed ROM including the latest multichannel audio decoding and post-processing
algorithms from Dolby Labs and DTS. ROM contents may vary depending on chip version and silicon revision. Visit www.analog.com for complete information.
5
See Engineer-to-Engineer Note Static Voltage Scaling for ADSP-2148x SHARC Processors (EE-357) for operating ADSP-2148x processors at 450 MHz.
6
This product contains a –140 dB sample rate converter.

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

©2024 Analog Devices, Inc. All rights reserved. Trademarks and


registered trademarks are the property of their respective owners.
D09018-2/24(I)

Rev. I | Page 71 of 71 | February 2024

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