Adsp-21483 21486 21487 21488 21489
Adsp-21483 21486 21487 21488 21489
Adsp-21483 21486 21487 21488 21489
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
FEATURES
High performance 32-bit/40-bit floating-point processor The ADSP-2148x processors are available with unique audio-
optimized for high performance audio processing centric peripherals, such as the digital applications
Single-instruction, multiple-data (SIMD) computational interface, serial ports, precision clock generators, S/PDIF
architecture transceiver, asynchronous sample rate converters, input
On-chip memory—5 Mbits on-chip RAM, 4 Mbits on-chip data port, and more
ROM For complete ordering information, see Ordering Guide
Up to 450 MHz operating frequency AEC-Q100 qualified for automotive applications
Code compatible with all other members of the SHARC family
Internal Memory
External
DPI Peripherals DAI Peripherals Peripherals Port
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. I Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication One Analog Way, Wilmington, MA 01887 U.S.A.
or otherwise under any patent or patent rights of Analog Devices. Trademarks and ©2024 Analog Devices, Inc. All rights reserved.
registered trademarks are the property of their respective companies. Technical Support www.analog.com
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
TABLE OF CONTENTS
Features ................................................................. 1 ESD Sensitivity ................................................... 22
Table of Contents ..................................................... 2 Maximum Power Dissipation ................................. 22
Revision History ...................................................... 2 Timing Specifications ........................................... 23
General Description ................................................. 3 Output Drive Currents ......................................... 56
Family Core Architecture ........................................ 4 Test Conditions .................................................. 56
Family Peripheral Architecture ................................ 8 Capacitive Loading .............................................. 56
I/O Processor Features ......................................... 11 Thermal Characteristics ........................................ 57
System Design .................................................... 12 88-Lead LFCSP_VQ Lead Assignment ......................... 59
Development Tools ............................................. 13 100-Lead LQFP_EP Lead Assignment ......................... 61
Additional Information ........................................ 14 176-Lead LQFP_EP Lead Assignment ......................... 63
Related Signal Chains .......................................... 14 Outline Dimensions ................................................ 67
Pin Function Descriptions ....................................... 15 Surface-Mount Design .......................................... 68
Specifications ........................................................ 19 Automotive Products .............................................. 69
Operating Conditions .......................................... 19 Ordering Guide ..................................................... 70
Electrical Characteristics ....................................... 20
Absolute Maximum Ratings .................................. 22
REVISION HISTORY
2/2024—Rev. H to Rev. I
Added Table 3, Internal Memory Space (2 MBits—ADSP-21488
Automotive Products Only) ........................................6
Removed obsolete models AD21487WBSWZ4Axx and
AD21487WBSWZ4Bxx in Automotive Products ............ 69
PM ADDRESS 24
DMD/PMD 64 5 STAGE
PROGRAM SEQUENCER
PM DATA 48
DAG1 DAG2
16x32 16x32
PM ADDRESS 32
SYSTEM
I/F
DM ADDRESS 32
USTAT
PM DATA 64 4x32-BIT
PX
DM DATA 64
64-BIT
RF DATA RF
ALU Rx/Fx SWAP Sx/SFx
MULTIPLIER SHIFTER ALU SHIFTER MULTIPLIER
PEx PEy
16x40-BIT 16x40-BIT
STYKx STYKy
Universal Registers fetches conflict with PM bus data accesses are cached. This
cache allows full speed execution of core, looped operations
These registers can be used for general-purpose tasks. The
such as digital filter multiply-accumulates, and FFT butterfly
USTAT (4) registers allow easy bit manipulations (Set, Clear,
processing.
Toggle, Test, XOR) for all peripheral registers (control/status).
The data bus exchange register (PX) permits data to be passed Data Address Generators With Zero-Overhead Hardware
between the 64-bit PM data bus and the 64-bit DM data bus, or Circular Buffer Support
between the 40-bit register file and the PM/DM data bus. These The two data address generators (DAGs) are used for indirect
registers contain hardware to handle the data width difference. addressing and implementing circular data buffers in hardware.
Single-Cycle Fetch of Instruction and Four Operands Circular buffers allow efficient programming of delay lines and
other data structures required in digital signal processing, and
The ADSP-2148x features an enhanced Harvard architecture in are commonly used in digital filters and Fourier transforms.
which the data memory (DM) bus transfers data and the pro- The two DAGs contain sufficient registers to allow the creation
gram memory (PM) bus transfers both instructions and data. of up to 32 circular buffers (16 primary register sets, 16 second-
With the its separate program and data memory buses and on- ary). The DAGs automatically handle address pointer
chip instruction cache, the processor can simultaneously fetch wraparound, reduce overhead, increase performance, and sim-
four operands (two over each data bus) and one instruction plify implementation. Circular buffers can start and end at any
(from the cache), all in a single cycle. memory location.
Instruction Cache Flexible Instruction Set
The processor includes an on-chip instruction cache that The 48-bit instruction word accommodates a variety of parallel
enables three-bus operation for fetching an instruction and four operations, for concise programming. For example, the
data values. The cache is selective—only the instructions whose processor can conditionally execute a multiply, an add, and a
FAMILY PERIPHERAL ARCHITECTURE • Arbitration logic to coordinate core and DMA transfers
between internal and external memory over the external
The ADSP-2148x family contains a rich set of peripherals that
port.
support a wide variety of applications including high quality
audio, medical imaging, communications, military, test equip- Non-SDRAM external memory address space is shown in
ment, 3D graphics, speech recognition, motor control, imaging, Table 6.
and other applications.
Table 6. External Memory for Non-SDRAM Addresses
External Memory
Size in
The external port interface supports access to the external mem-
Bank Words Address Range
ory through core and DMA accesses. The external memory
address space is divided into four banks. Any bank can be pro- Bank 0 6M 0x0020 0000–0x007F FFFF
grammed as either asynchronous or synchronous memory. The Bank 1 8M 0x0400 0000–0x047F FFFF
external ports are comprised of the following modules. Bank 2 8M 0x0800 0000–0x087F FFFF
• An Asynchronous Memory Interface which communicates Bank 3 8M 0x0C00 0000–0x0C7F FFFF
with SRAM, FLASH, and other devices that meet the stan-
dard asynchronous SRAM access protocol. The AMI External Port
supports 6M words of external memory in bank 0 and 8M The external port provides a high performance, glueless inter-
words of external memory in bank 1, bank 2, and bank 3. face to a wide variety of industry-standard memory devices. The
• A SDRAM controller that supports a glueless interface with external port, available on the 176-lead LQFP, may be used to
any of the standard SDRAMs. The SDC supports 62M interface to synchronous and/or asynchronous memory devices
words of external memory in bank 0, and 64M words of through the use of its separate internal memory controllers. The
external memory in bank 1, bank 2, and bank 3. NOTE: first is an SDRAM controller for connection of industry-stan-
This feature is not available on the ADSP-21486 product. dard synchronous DRAM devices while the second is an
• DMA (direct memory access)—The DMA controller trans- Table 9. DMA Channels
fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer Peripheral DMA Channels
data to and from memory. The UART has two dedicated SPORTs 16
DMA channels, one for transmit and one for receive. These IDP/PDAP 8
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates. SPI 2
UART 2
Timers External Port 2
The ADSP-2148x has a total of three timers: a core timer that Accelerators 2
can generate periodic software interrupts and two general- Memory-to-Memory 2
purpose timers that can generate periodic interrupts and be
independently set to operate in one of three modes: MLB1 31
1
Automotive models only.
• Pulse waveform generation mode
• Pulse width count/capture mode Delay Line DMA
• External event watchdog mode The processor provides delay line DMA functionality. This
The core timer can be configured to use FLAG3 as a timer allows processor reads and writes to external delay line buffers
expired signal, and the general-purpose timers have one bidirec- (and hence to external memory) with limited core interaction.
tional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register, Scatter/Gather DMA
a 32-bit period register, and a 32-bit pulse width register. A sin- The processor provides scatter/gather DMA functionality. This
gle control and status register enables or disables the general- allows processor DMA reads/writes to/from non contiguous
purpose timer. memory blocks.
2-Wire Interface Port (TWI) FFT Accelerator
The TWI is a bidirectional 2-wire, serial bus used to move 8-bit The FFT accelerator implements a radix-2 complex/real input,
data while maintaining compliance with the I2C bus protocol. complex output FFT with no core intervention. The FFT accel-
The TWI module incorporates the following features: erator runs at the peripheral clock frequency.
• 7-bit addressing FIR Accelerator
• Simultaneous controller and target operation on multiple
The FIR (finite impulse response) accelerator consists of a 1024
device systems with support for multimedia data
word coefficient memory, a 1024 word deep delay line for the
arbitration
data, and four MAC units. A controller manages the accelerator.
• Digital filtering and timed event processing The FIR accelerator runs at the peripheral clock frequency.
• 100 kbps and 400 kbps data rates
• Low interrupt rate
ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSP-2148x
architecture and functionality. For detailed information on the
ADSP-2148x family core architecture and instruction set, refer
to the SHARC Processor Programming Reference.
State
During/
Name Type After Reset Description
ADDR23–0 I/O/T (ipu) High-Z/ External Address. The processor outputs addresses for external memory and periph-
driven low erals on these pins. The ADDR pins can be multiplexed to support the external memory
(boot) interface address, and FLAGS15–8 (I/O) and PWM (O). After reset, all ADDR pins are in
external memory interface mode and FLAG(0–3) pins are in FLAGS mode (default).
When configured in the IDP_PDAP_CTL register, IDP channel 0 scans the ADDR23–4 pins
for parallel input data.
DATA15–0 I/O/T (ipu) High-Z External Data. The data pins can be multiplexed to support the external memory
interface data (I/O), and FLAGS7–0 (I/O).
AMI_ACK I (ipu) Memory Acknowledge. External devices can deassert AMI_ACK (low) to add wait
states to an external memory access. AMI_ACK is used by I/O devices, memory
controllers, or other peripherals to hold off completion of an external memory access.
MS0–1 O/T (ipu) High-Z Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corre-
sponding banks of external memory. The MS1-0 lines are decoded memory address lines
that change at the same time as the other address lines. When no external memory
access is occurring the MS1-0 lines are inactive; they are active however when a condi-
tional memory access instruction is executed, when the condition evaluates as true.
The MS1 pin can be used in EPORT/FLASH boot mode. For more information, see the
ADSP-214xx SHARC Processor Hardware Reference.
AMI_RD O/T (ipu) High-Z AMI Port Read Enable. AMI_RD is asserted whenever the processor reads a word from
external memory.
AMI_WR O/T (ipu) High-Z AMI Port Write Enable. AMI_WR is asserted when the processor writes a word to
external memory.
FLAG0/IRQ0 I/O (ipu) FLAG[0] FLAG0/Interrupt Request0.
INPUT
FLAG1/IRQ1 I/O (ipu) FLAG[1] FLAG1/Interrupt Request1.
INPUT
FLAG2/IRQ2/MS2 I/O (ipu) FLAG[2] FLAG2/Interrupt Request2/Memory Select2.
INPUT
FLAG3/TMREXP/MS3 I/O (ipu) FLAG[3] FLAG3/Timer Expired/Memory Select3.
INPUT
The following symbols appear in the Type column of this table: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,
O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic
levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot
be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The
range of an ipd resistor can be between 31 kΩ–85 kΩ. The three-state voltage of ipu pads will not reach to the full VDD_EXT level; at typical
conditions the voltage is in the range of 2.3 V to 2.7 V.
In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.
State
During/
Name Type After Reset Description
SDRAS O/T (ipu) High-Z/ SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other
driven high SDRAM command pins, defines the operation for the SDRAM to perform.
SDCAS O/T (ipu) High-Z/ SDRAM Column Address Select. Connect to SDRAM’s CAS pin. In conjunction with
driven high other SDRAM command pins, defines the operation for the SDRAM to perform.
SDWE O/T (ipu) High-Z/ SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin. In conjunction with
driven high other SDRAM command pins, defines the operation for the SDRAM to perform.
SDCKE O/T (ipu) High-Z/ SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK
driven high signal. For details, see the data sheet supplied with the SDRAM device.
SDA10 O/T (ipu) High-Z/ SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with non-SDRAM
driven high accesses. This pin replaces the DSP’s ADDR10 pin only during SDRAM accesses.
SDDQM O/T (ipu) High-Z/ DQM Data Mask. SDRAM Input mask signal for write accesses and output mask signal
driven high for read accesses. Input data is masked when DQM is sampled high during a write cycle.
The SDRAM output buffers are placed in a High-Z state when DQM is sampled high
during a read cycle. SDDQM is driven high from reset de-assertion until SDRAM initial-
ization completes. Afterwards it is driven low irrespective of whether any SDRAM
accesses occur or not.
SDCLK O/T (ipd) High-Z/ SDRAM Clock Output. Clock driver for this pin differs from all other clock drivers. See
driving Figure 40. For models in the 100-lead package, the SDRAM interface should be disabled
to avoid unnecessary power switching by setting the DSDCTL bit in SDCTL register. For
more information, see the ADSP-214xx SHARC Processor Hardware Reference.
DAI _P20–1 I/O/T (ipu) High-Z Digital Applications Interface. These pins provide the physical interface to the DAI
SRU. The DAI SRU configuration registers define the combination of on-chip audio-
centric peripheral inputs or outputs connected to the pin and to the pin’s output enable.
The configuration registers of these peripherals then determines the exact behavior of
the pin. Any input or output signal present in the DAI SRU may be routed to any of these
pins.
DPI _P14–1 I/O/T (ipu) High-Z Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU.
The DPI SRU configuration registers define the combination of on-chip peripheral
inputs or outputs connected to the pin and to the pin’s output enable. The configu-
ration registers of these peripherals then determines the exact behavior of the pin. Any
input or output signal present in the DPI SRU may be routed to any of these pins.
WDT_CLKIN I Watchdog Timer Clock Input. This pin should be pulled low when not used.
WDT_CLKO O Watchdog Resonator Pad Output.
WDTRSTO O (ipu) Watchdog Timer Reset Out.
THD_P I Thermal Diode Anode. When not used, this pin can be left floating.
THD_M O Thermal Diode Cathode. When not used, this pin can be left floating.
The following symbols appear in the Type column of this table: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,
O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic
levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot
be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The
range of an ipd resistor can be between 31 kΩ–85 kΩ. The three-state voltage of ipu pads will not reach to the full VDD_EXT level; at typical
conditions the voltage is in the range of 2.3 V to 2.7 V.
In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.
State
During/
Name Type After Reset Description
MLBCLK1 I Media Local Bus Clock. This clock is generated by the MLB controller that is synchro-
nized to the MOST network and provides the timing for the entire MLB interface at
49.152 MHz at FS=48 kHz. When the MLB controller is not used, this pin should be
grounded.
1
MLBDAT I/O/T in 3 High-Z Media Local Bus Data. The MLBDAT line is driven by the transmitting MLB device and
pin mode. I is received by all other MLB devices including the MLB controller. The MLBDAT line
in 5 pin carries the actual data. In 5-pin MLB mode, this pin is an input only. When the MLB
mode. controller is not used, this pin should be grounded.
MLBSIG1 I/O/T in 3 High-Z Media Local Bus Signal. This is a multiplexed signal which carries the Channel/Address
pin mode. I generated by the MLB Controller, as well as the Command and RxStatus bytes from
in 5 pin MLB devices. In 5-pin mode, this pin is input only. When the MLB controller is not used,
mode this pin should be grounded.
1
MLBDO O/T High-Z Media Local Bus Data Output (in 5 pin mode). This pin is used only in 5-pin MLB mode.
This serves as the output data pin in 5-pin mode. When the MLB controller is not used,
this pin should be connected to ground.
1
MLBSO O/T High-Z Media Local Bus Signal Output (in 5 pin mode). This pin is used only in 5-pin MLB
mode. This serves as the output signal pin in 5-pin mode. When the MLB controller is
not used, this pin should be connected to ground.
TDI I (ipu) Test Data Input (JTAG). Provides serial data for the boundary scan logic.
TDO O/T High-Z Test Data Output (JTAG). Serial scan output of the boundary scan path.
TMS I (ipu) Test Mode Select (JTAG). Used to control the test state machine.
TCK I Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the device.
TRST I (ipu) Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the processor.
EMU O (O/D, ipu) High-Z Emulation Status. Must be connected to the ADSP-2148x Analog Devices DSP Tools
product line of JTAG emulators target board connector only.
The following symbols appear in the Type column of this table: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,
O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic
levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot
be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The
range of an ipd resistor can be between 31 kΩ–85 kΩ. The three-state voltage of ipu pads will not reach to the full VDD_EXT level; at typical
conditions the voltage is in the range of 2.3 V to 2.7 V.
In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.
State
During/
Name Type After Reset Description
CLK_CFG1–0 I Core to CLKIN Ratio Control. These pins set the start up clock frequency.
Note that the operating frequency can be changed by programming the PLL multiplier
and divider in the PMCTL register at any time after the core comes out of reset. The
allowed values are:
00 = 8:1
01 = 32:1
10 = 16:1
11 = reserved
CLKIN I Local Clock In. Used in conjunction with XTAL. CLKIN is the clock input. It configures
the processors to use either its internal clock generator or an external clock source.
Connecting the necessary components to CLKIN and XTAL enables the internal clock
generator. Connecting the external clock to CLKIN while leaving XTAL unconnected
configures the processors to use the external clock source such as an external clock
oscillator. CLKIN may not be halted, changed, or operated below the specified
frequency.
XTAL O Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external
crystal.
RESET I Processor Reset. Resets the processor to a known state. Upon deassertion, there is a
4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program
execution from the hardware reset vector address. The RESET input must be asserted
(low) at power-up.
RESETOUT/ I/O (ipu) Reset Out/Running Reset In. The default setting on this pin is reset out. This pin also
RUNRSTIN has a second function as RUNRSTIN which is enabled by setting bit 0 of the RUNRSTCTL
register. For more information, see the ADSP-214xx SHARC Processor Hardware
Reference.
BOOT_CFG2–0 I Boot Configuration Select. These pins select the boot mode for the processor (see
Table 10). The BOOT_CFG pins must be valid before RESET (hardware and software) is
asserted.
The following symbols appear in the Type column of this table: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,
O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic
levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot
be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The
range of an ipd resistor can be between 31 kΩ–85 kΩ. The three-state voltage of ipu pads will not reach to the full VDD_EXT level; at typical
conditions the voltage is in the range of 2.3 V to 2.7 V.
In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.
1
The MLB pins are only available on the automotive models.
266 MHz / 300 MHz / 350 MHz / 400 MHz 450 MHz
266 MHz / 300 MHz / 350 MHz / 400 MHz / 450 MHz
VDD_INT (V)
TJ (°C) 0.975 V 1.0 V 1.025 V 1.05 V 1.075 V 1.10 V 1.125 V 1.15 V 1.175 V
–45 68 77 86 96 107 118 131 144 159
–35 74 83 92 103 114 126 140 154 170
–25 82 92 101 113 125 138 153 168 185
–15 94 104 115 127 140 155 171 187 205
–5 109 121 133 147 161 177 194 212 233
+5 129 142 156 171 188 206 225 245 268
+15 152 168 183 201 219 240 261 285 309
+25 182 199 216 237 257 280 305 331 360
+35 217 237 256 279 303 329 358 388 420
+45 259 282 305 331 359 389 421 455 492
+55 309 334 361 391 423 458 495 533 576
+65 369 398 429 464 500 539 582 626 675
+75 437 471 506 547 588 633 682 731 789
+85 519 559 599 645 693 746 802 860 926
+95 615 662 707 761 816 877 942 1007 1083
+105 727 779 833 897 958 1026 1103 1179 1266
+115 853 914 975 1047 1119 1198 1285 1372 1473
+125 997 1067 1138 1219 1305 1397 1498 1601 1716
1
Valid temperature and voltage ranges are model-specific. See Operating Conditions.
PMCTL
(SDCKR)
PMCTL
PLL (PLLBP)
BYPASS
fINPUT fVCO CCLK SDRAM
MUX
CLKIN CLKIN LOOP PLL
DIVIDER VCO DIVIDER DIVIDER
FILTER
BYPASS
fCCLK
MUX
XTAL SDCLK
BUF
CLK_CFGx/ PMCTL
PMCTL PMCTL (2 × PLLM) (PLLD) DIVIDE PCLK
PMCTL
(INDIV) BY 2
(PLLBP)
fVCO ÷ (2 × PLLM)
PCLK
CCLK
CORESRST
*CLKOUT (TEST ONLY) FREQUENCY IS THE SAME AS fINPUT.
THIS SIGNAL IS NOT SPECIFIED OR SUPPORTED FOR ANY DESIGN.
VDDINT
tIVDDEVDD
VDDEXT
tCLKVDD
CLKIN
tCLKRST
CLK_CFG1–0
tPLLRST tCORERST
RESETOUT
Clock Input
266 MHz 300 MHz 350 MHz 400 MHz 450 MHz
Parameter Min Max Min Max Min Max Min Max Min Max Unit
Timing Requirements
tCK CLKIN Period 301 1002 26.661 1002 22.81 1002 201 1002 17.751 1002 ns
tCKL CLKIN Width Low 15 45 13 45 11 45 10 45 8.875 45 ns
tCKH CLKIN Width High 15 45 13 45 11 45 10 45 8.875 45 ns
tCKRF3 CLKIN Rise/Fall (0.4 V to 2.0 V) 3 3 3 3 3 ns
tCCLK4 CCLK Period 3.75 10 3.33 10 2.85 10 2.5 10 2.22 10 ns
fVCO5 VCO Frequency 200 800 200 800 200 800 200 800 200 900 MHz
tCKJ6, 7 CLKIN Jitter Tolerance –250 +250 –250 +250 –250 +250 –250 +250 –250 +250 ps
1
Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL.
2
Applies only for CLK_CFG1–0 = 01 and default values for PLL control bits in PMCTL.
3
Guaranteed by simulation but not tested on silicon.
4
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK.
5
See Figure 3 for VCO diagram.
6
Actual input jitter should be combined with ac specifications for accurate timing analysis.
7
Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
tCK tCKJ
CLKIN
tCKH tCKL
ADSP-2148x
CLKIN R1 XTAL
0ȍ
R2
47ȍ CHOOSE C1 AND C2 BASED ON THE CRYSTAL Y1.
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL DRIVE
C1 C2 POWER. REFER TO CRYSTAL MANUFACTURER’S
22pF Y1 22pF SPECIFICATIONS.
25 MHz
TYPICAL VALUES
CLKIN
tWRST tSRST
RESET
Figure 7. Reset
Running Reset
The following timing specification applies to RESETOUT/RUNRSTIN pin when it is configured as RUNRSTIN.
CLKIN
tWRUNRST tSRUNRST
RUNRSTIN
INTERRUPT
INPUTS
tIPW
Figure 9. Interrupts
Core Timer
The following timing specification applies to FLAG3 when it is configured as the core timer (TMREXP).
tWCTIM
FLAG3
(TMREXP)
tPWMO
PWM
OUTPUTS
tPWI
TIMER
CAPTURE
INPUTS
tWDTCLKPER
WDT_CLKIN
tRST
tRSTPW
WDTRSTO
DAI_Pn
DPI_Pn
tDPIO
DAI_Pm
DPI_Pm
tSTRIG tHTRIG
DAI_Pn
DPI_Pn
PCG_TRIGx_I
DAI_Pm
DPI_Pm
PCG_EXTx_I
(CLKIN)
tDPCGIO tPCGIP
DAI_Py
DPI_Py
PCG_CLKx_O
DAI_Pz
DPI_Pz
PCG_FSx_O
tDTRIGFS
FLAG
INPUTS
tFIPW
FLAG
OUTPUTS
tFOPW
tSDCLK tSDCLKH
SDCLK
DATA (IN)
tDCAD
tDSDAT
tENSDAT
tHCAD
DATA (OUT)
tDCAD tHCAD
COMMAND/ADDR
(OUT)
AMI_RD
tDRLD tSDS
tDAD tHDRH
AMI_DATA
tDSAK tRWR
tDAAK
AMI_ACK
AMI_WR
AMI_ADDR
AMI_MSx
tDAWH tDWHA
tDAWL tWW
AMI_WR
tWWR
tWDE
tDATRWH
tDDWH tDDWR
AMI_DATA
tDSAK tDWHD
tDAAK
AMI_ACK
AMI_RD
DAI_P20–1 DAI_P20–1
(SCLK) (SCLK)
tDFSI tDFSE
tHOFSI tSFSI tHFSI tHOFSE tSFSE tHFSE
DAI_P20–1 DAI_P20–1
(FS) (FS)
DAI_P20–1 DAI_P20–1
(SCLK) (SCLK)
tDFSI tDFSE
tHOFSI tSFSI tHFSI tHOFSE tSFSE tHFSE
DAI_P20–1 DAI_P20–1
(FS) (FS)
tDDTI tDDTE
tHDTI tHDTE
DAI_P20–1 DAI_P20–1
(DATA (DATA
CHANNEL A/B) CHANNEL A/B)
tHFSE/I
tSFSE/I
DAI_P20–1
(FS)
tDDTE/I
tDDTENFS
tHDTE/I
DAI_P20–1
(DATA CHANNEL 1ST BIT 2ND BIT
A/B)
tDDTLFSE
tHFSE/I
tSFSE/I
DAI_P20–1
(FS)
tDDTE/I
tDDTENFS
tHDTE/I
DAI_P20–1
(DATA CHANNEL 1ST BIT 2ND BIT
A/B)
t
Figure 21. External Late Frame Sync1
1
This figure reflects changes made to support left-justified mode.
DAI_P20–1
(SCLK, EXT)
tDDTEN tDDTTE
DAI_P20–1
(DATA
CHANNEL A/B)
DRIVE EDGE
DAI_P20–1
(SCLK, INT)
tDDTIN
DAI_P20–1
(DATA
CHANNEL A/B)
DAI_P20–1
(SCLK, EXT)
TDVx
DAI_P20-1 tDFDVEN
tDRDVEN
DAI_P20–1
(SCLK, INT)
TDVx
DAI_P20-1
tDFDVIN
tDRDVIN
tIDPCLKW
DAI_P20–1
(SCLK)
tSISFS tSIHFS
DAI_P20–1
(FS)
tSISD
tSIHD
DAI_P20–1
(SDATA)
SAMPLE EDGE
tPDCLK
tPDCLKW
DAI_P20–1
(PDAP_CLK)
tSPHOLD tHPHOLD
DAI_P20–1
(PDAP_HOLD)
tPDSD tPDHD
DAI_P20–1/
ADDR23–4
(PDAP_DATA)
tPDHLDD tPDSTRB
DAI_P20–1
(PDAP_STROBE)
SAMPLE EDGE
tSRCCLK
DAI_P20–1 tSRCCLKW
(SCLK)
tSRCSFS tSRCHFS
DAI_P20–1
(FS)
tSRCSD tSRCHD
DAI_P20–1
(SDATA)
SAMPLE EDGE
tSRCCLK
DAI_P20–1 tSRCCLKW
(SCLK)
tSRCSFS tSRCHFS
DAI_P20–1
(FS)
tSRCTDD
tSRCTDH
DAI_P20–1
(SDATA)
tPWMW
PWM
OUTPUTS
tPWMP
S/PDIF Transmitter
Serial data input to the S/PDIF transmitter can be formatted as left-justified, I2S, or right-justified with word widths of 16, 18, 20, or 24
bits. The following sections provide timing for the transmitter.
S/PDIF Transmitter-Serial Input Waveforms
Figure 29 shows the right-justified mode. Frame sync is high for the left channel and low for the right channel. Data is valid on the rising
edge of serial clock. The MSB is delayed the minimum in 24-bit output mode or the maximum in 16-bit output mode from a frame sync
transition, so that when there are 64 serial clock periods per frame sync period, the LSB of the data is right-justified to the next frame sync
transition.
DAI_P20–1
SCLK
tRJD
DAI_P20–1
SCLK
tI2SD
DAI_P20–1
MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB
SDATA
Figure 31 shows the left-justified mode. The frame sync is high for the left channel and low for the right channel. Data is valid on the rising
edge of serial clock. The MSB is left-justified to the frame sync transition with no delay.
DAI_P20–1
SCLK
tLJD
DAI_P20–1
SDATA MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB
SAMPLE EDGE
tSITXCLKW tSITXCLK
DAI_P20–1
(TxCLK)
tSISCLK
tSISCLKW
DAI_P20–1
(SCLK)
tSISFS tSIHFS
DAI_P20–1
(FS)
tSISD tSIHD
DAI_P20–1
(SDATA)
DAI_P20–1
(SCLK)
tDFSI
tHOFSI
DAI_P20–1
(FS)
tDDTI
tHDTI
DAI_P20–1
(DATA CHANNEL
A/B)
DPI
(OUTPUT)
MOSI
(OUTPUT)
tSSPIDM tSSPIDM
CPHASE = 1
tHSPIDM tHSPIDM
MISO
(INPUT)
tDDSPIDM tHDSPIDM
MOSI
(OUTPUT)
tSSPIDM tHSPIDM
CPHASE = 0
MISO
(INPUT)
SPIDS
(INPUT)
MISO
(OUTPUT)
MOSI
(INPUT)
tHDSPIDS
tDSDHI
MISO
(OUTPUT)
tDSOV
tHSPIDS
CPHASE = 0
tSSPIDS
MOSI
(INPUT)
tDHMCF
tDSMCF
tMCKH tMCKL
MLBCLK tMCKR
tMCKF
tMLBCLK
tMCFDZ
tMCDRV
tMDZH
MLBSIG/
MLBDAT VALID
(Tx, Output)
tDHMCF
tDSMCF
tMCKH tMCKL
MLBCLK tMCKR
tMCKF
tMLBCLK
tMCRDL
tMCDRV
MLBSO/ VALID
MLBDO
(Tx, Output)
MLBCLK
tMPWV tMPWV
Figure 38. MLB 3-Pin and 5-Pin MLBCLK Pulse Width Variation Timing
tTCK
TCK
tSTAP tHTAP
TMS
TDI
tDTDO
TDO
tSSYS tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
ZO = 50:(impedance)
50:
Table 55. Driver Types 0.5pF
TD = 4.04 r 1.18 ns
4pF 2pF
Driver Type Associated Pins
400:
A FLAG[0–3], AMI_ADDR[0–23], DATA[0–15],
AMI_RD, AMI_WR, AMI_ACK, MS[1-0], SDRAS,
SDCAS, SDWE, SDDQM, SDCKE, SDA10, EMU, TDO, NOTES:
RESETOUT, DPI[1–14], DAI[1–20], WDTRSTO, THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE
MLBDAT, MLBSIG, MLBSO, MLBDO, MLBCLK EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
B SDCLK
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
200
Figure 41. Equivalent Device Loading for AC Measurements
150 (Includes All Fixtures)
SOURCE/SINK (VDDEXT) CURRENT (mA)
100
TYPE A
CAPACITIVE LOADING
50
Output delays and holds are based on standard capacitive loads:
0
30 pF on all pins (see Figure 41). Figure 45 and Figure 46 show
TYPE A
graphically how output delays and holds vary with load capaci-
-50 tance. The graphs of Figure 43 through Figure 46 may not be
linear outside the ranges shown for Typical Output Delay vs.
-100 TYPE B Load Capacitance and Typical Output Rise Time (20% to 80%,
-150
V = Min) vs. Load Capacitance.
VOL 3.13 V, 125 °C
-200
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 7
SWEEP (VDDEXT) VOLTAGE (V)
6
TYPE A DRIVE FALL
Figure 40. Typical Drive at Junction Temperature
y = 0.0414x + 0.2661
y = 0.0341x + 0.3093
Timing is measured on signals when they cross the 1.5 V level as TYPE B DRIVE FALL
1 y = 0.0152x + 0.1882
described in Figure 42. All delays (in nanoseconds) are mea-
sured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V. 0
0 25 50 75 100 125 150 175 200
LOAD CAPACITANCE (pF)
Figure 43. Typical Output Rise/Fall Time (20% to 80%, VDD_EXT = Max)
INPUT
OR 1.5V 1.5V
OUTPUT
4.5
To estimate the junction temperature of a single device while on
TYPE A DRIVE FALL
a JEDEC 2S2P PCB, use:
y = 0.0196x + 1.2945 TYPE A DRIVE RISE
4
y = 0.0152x + 1.7607
T J = T CASE + JT P D
RISE AND FALL DELAY (ns)
3.5
TYPE B DRIVE RISE
3
y = 0.0068x + 1.7614 where:
2.5
TJ = junction temperature °C
TYPE B DRIVE FALL TCASE = case temperature (°C) measured at the top center of the
2 y = 0.0074x + 1.421
package
1.5
JT = junction-to-top (of package) characterization parameter
1 is the typical value from Table 56, Table 57, and Table 58.
0.5
PD = power dissipation
Values of JA are provided for package comparison and PCB
design considerations. JA can be used for a first-order approxi-
0
0 25 50 75 100 125 150 175 200
LOAD CAPACITANCE (pF) mation of TJ by the equation:
where:
9
TA = ambient temperature °C
8
TYPE A DRIVE RISE
TYPE A DRIVE FALL
y = 0.0256x + 3.5859
y = 0.0359x + 2.924
RISE AND FALL TIMES DELAY (ns)
7
TYPE B DRIVE RISE
6 y = 0.0116x + 3.5697
0
0 25 50 75 100 125 150 175 200
LOAD CAPACITANCE (pF)
Lead Name Lead No. Lead Name Lead No. Lead Name Lead No. Lead Name Lead No.
CLK_CFG1 1 VDD_EXT 23 DAI_P10 45 VDD_INT 67
BOOT_CFG0 2 DPI_P08 24 VDD_INT 46 FLAG0 68
VDD_EXT 3 DPI_P07 25 VDD_EXT 47 VDD_INT 69
VDD_INT 4 DPI_P09 26 DAI_P20 48 FLAG1 70
BOOT_CFG1 5 DPI_P10 27 VDD_INT 49 FLAG2 71
GND 6 DPI_P11 28 DAI_P08 50 FLAG3 72
CLK_CFG0 7 DPI_P12 29 DAI_P04 51 GND 73
VDD_INT 8 DPI_P13 30 DAI_P14 52 GND 74
CLKIN 9 DAI_P03 31 DAI_P18 53 VDD_EXT 75
XTAL 10 DPI_P14 32 DAI_P17 54 GND 76
VDD_EXT 11 VDD_INT 33 DAI_P16 55 VDD_INT 77
VDD_INT 12 DAI_P13 34 DAI_P15 56 TRST 78
VDD_INT 13 DAI_P07 35 DAI_P12 57 EMU 79
RESETOUT/RUNRSTIN 14 DAI_P19 36 DAI_P11 58 TDO 80
VDD_INT 15 DAI_P01 37 VDD_INT 59 VDD_EXT 81
DPI_P01 16 DAI_P02 38 GND 60 VDD_INT 82
DPI_P02 17 VDD_INT 39 THD_M 61 TDI 83
DPI_P03 18 VDD_EXT 40 THD_P 62 TCK 84
VDD_INT 19 VDD_INT 41 VDD_THD 63 VDD_INT 85
DPI_P05 20 DAI_P06 42 VDD_INT 64 RESET 86
DPI_P04 21 DAI_P05 43 VDD_INT 65 TMS 87
DPI_P06 22 DAI_P09 44 VDD_INT 66 VDD_INT 88
GND 89*
* Lead no. 89 is the GND supply (see Figure 47 and Figure 48) for the processor; this pad must be robustly connected to GND for the processor
to function.
LEAD 88 LEAD 67
LEAD 1 LEAD 66
LEAD 1 INDICATOR
ADSP-2148x
88-LEAD LFCSP_VQ
TOP VIEW
LEAD 22 LEAD 45
LEAD 23 LEAD 44
LEAD 67 LEAD 88
LEAD 66 LEAD 1
ADSP-2148x
88-LEAD LFCSP_VQ GND PAD
LEAD 1 INDICATOR
BOTTOM VIEW (LEAD 89)
LEAD 45 LEAD 22
LEAD 44 LEAD 23
Lead Name Lead No. Lead Name Lead No. Lead Name Lead No. Lead Name Lead No.
VDD_INT 1 VDD_EXT 26 DAI_P10 51 VDD_INT 76
CLK_CFG1 2 DPI_P08 27 VDD_INT 52 FLAG0 77
BOOT_CFG0 3 DPI_P07 28 VDD_EXT 53 VDD_INT 78
VDD_EXT 4 VDD_INT 29 DAI_P20 54 VDD_INT 79
VDD_INT 5 DPI_P09 30 VDD_INT 55 FLAG1 80
BOOT_CFG1 6 DPI_P10 31 DAI_P08 56 FLAG2 81
GND 7 DPI_P11 32 DAI_P04 57 FLAG3 82
DNC 8* DPI_P12 33 DAI_P14 58 MLBCLK 83
DNC 9* DPI_P13 34 DAI_P18 59 MLBDAT 84
CLK_CFG0 10 DAI_P03 35 DAI_P17 60 MLBDO 85
VDD_INT 11 DPI_P14 36 DAI_P16 61 VDD_EXT 86
CLKIN 12 VDD_INT 37 DAI_P15 62 MLBSIG 87
XTAL 13 VDD_INT 38 DAI_P12 63 VDD_INT 88
VDD_EXT 14 VDD_INT 39 VDD_INT 64 MLBSO 89
VDD_INT 15 DAI_P13 40 DAI_P11 65 TRST 90
VDD_INT 16 DAI_P07 41 VDD_INT 66 EMU 91
RESETOUT/RUNRSTIN 17 DAI_P19 42 VDD_INT 67 TDO 92
VDD_INT 18 DAI_P01 43 GND 68 VDD_EXT 93
DPI_P01 19 DAI_P02 44 THD_M 69 VDD_INT 94
DPI_P02 20 VDD_INT 45 THD_P 70 TDI 95
DPI_P03 21 VDD_EXT 46 VDD_THD 71 TCK 96
VDD_INT 22 VDD_INT 47 VDD_INT 72 VDD_INT 97
DPI_P05 23 DAI_P06 48 VDD_INT 73 RESET 98
DPI_P04 24 DAI_P05 49 VDD_INT 74 TMS 99
DPI_P06 25 DAI_P09 50 VDD_INT 75 VDD_INT 100
GND 101**
MLB pins (pins 83, 84, 85, 87, and 89) are available for automotive models only. For non-automotive models, these pins should be connected
to ground (GND).
* Do not make any electrical connection to this pin.
** Pin no. 101 (exposed pad) is the GND supply (see Figure 49 and Figure 50) for the processor; this pad must be robustly connected to GND.
LEAD 1 LEAD 75
LEAD 1 INDICATOR
ADSP-2148x
100-LEAD LQFP_EP
TOP VIEW
LEAD 25 LEAD 51
LEAD 26 LEAD 50
LEAD 75 LEAD 1
ADSP-2148x
100-LEAD LQFP_EP GND PAD
LEAD 1 INDICATOR
BOTTOM VIEW (LEAD 101)
LEAD 51 LEAD 25
LEAD 50 LEAD 26
LEAD 1 INDICATOR
ADSP-2148x
176-LEAD LQFP_EP
TOP VIEW
LEAD 44 LEAD 89
LEAD 45 LEAD 88
ADSP-2148x
176-LEAD LQFP_EP GND PAD
LEAD 1 INDICATOR
BOTTOM VIEW (LEAD 177)
LEAD 89 LEAD 44
LEAD 88 LEAD 45
12.10 0.30
12.00 SQ 0.60 MAX 0.23
11.90 0.60 0.18
MAX
PIN 1
67 88 INDICATOR
66 1
PIN 1
INDICATOR
11.85 0.50
11.75 SQ BSC 6.80
EXPOSED
11.65 PAD 6.70 SQ
6.60
0.50
0.40 45 22
44 23
0.30
TOP VIEW BOTTOM VIEW
0.70 10.50
0.65 REF
*0.90 12° MAX
0.60 0.045 FOR PROPER CONNECTION OF
0.85 THE EXPOSED PAD, REFER TO
0.75 0.025 THE PIN CONFIGURATION AND
0.005 FUNCTION DESCRIPTIONS
SEATING COPLANARITY SECTION OF THIS DATA SHEET.
PLANE 0.08
0.138~0.194 REF
16.20
16.00 SQ
1.60 15.80 14.20
MAX
0.75 14.00 SQ
12.00 REF
0.60 13.80
0.45 100 76 76 100
1 75 75 1
1.00 REF
PIN 1
SEATING
PLANE
EXPOSED
PAD 6.00 BSC
SQ
VIEW A
ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BED-HD
Figure 54. 100-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP]1
(SW-100-2)
Dimensions shown in millimeters
1
For information relating to the exposed pad on the SW-100-2 package, see the table endnote on Page 61.
SEATING PIN 1
PLANE
1.45 0.20
1.40 0.15
1.35 0.09
0.15 7° TOP VIEW BOTTOM VIEW
0.10 3.5° (PINS DOWN) (PINS UP)
0.05 44 89 89 44
0.08 0°
COPLANARITY 45 88 88 45
0.27
VIEW A 0.50
VIEW A 0.22
ROTATED 90° CCW BSC 0.17
LEAD PITCH
FOR PROPER CONNECTION
OF THE EXPOSED PAD, REFER
TO “SURFACE-MOUNT DESIGN”
COMPLIANT TO JEDEC STANDARDS MS-026-BGA-HD IN THIS DATA SHEET.
Figure 55. 176-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP]1
(SW-176-2)
Dimensions shown in millimeters
1
For information relating to the exposed pad on the SW-176-2 package, see the table endnote on Page 63.
SURFACE-MOUNT DESIGN
The exposed pad is required to be electrically and thermally
connected to GND. Implement this by soldering the exposed
pad to a GND PCB land that is the same size as the exposed pad.
The GND PCB land should be robustly connected to the GND
plane in the PCB for best electrical and thermal performance.
No separate GND pins are provided in the package.
Processor
Instruction
Model1, 2, 3, 4 Notes Temperature Range5 RAM Rate (Max) Package Description Package Option
6
AD21486WBSWZ4Axx –40°C to +125°C 5 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2
AD21488WBCPZ2202 –40°C to +125°C 2 Mbit 300 MHz 88-Lead LFCSP_VQ CP-88-5
AD21488WBCPZ4202 –40°C to +125°C 2 Mbit 400 MHz 88-Lead LFCSP_VQ CP-88-5
AD21488WBCPZ202 –40°C to +125°C 3 Mbit 300 MHz 88-Lead LFCSP_VQ CP-88-5
AD21488WBCPZ302 –40°C to +125°C 3 Mbit 350 MHz 88-Lead LFCSP_VQ CP-88-5
AD21488WBCPZ402 –40°C to +125°C 3 Mbit 400 MHz 88-Lead LFCSP_VQ CP-88-5
AD21488WBSWZ1Axx –40°C to +125°C 3 Mbit 266 MHz 100-Lead LQFP_EP SW-100-2
AD21488WBSWZ2Axx –40°C to +125°C 3 Mbit 300 MHz 100-Lead LQFP_EP SW-100-2
AD21488WBSWZ1Bxx –40°C to +125°C 2 Mbit 266 MHz 176-Lead LQFP_EP SW-176-2
AD21488WBSWZ2Bxx –40°C to +125°C 3 Mbit 266 MHz 176-Lead LQFP_EP SW-176-2
AD21488WBSWZ4Bxx –40°C to +125°C 3 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2
AD21489WBCPZ202 –40°C to +125°C 5 Mbit 300 MHz 88-Lead LFCSP_VQ CP-88-5
AD21489WBCPZ302 –40°C to +125°C 5 Mbit 350 MHz 88-Lead LFCSP_VQ CP-88-5
AD21489WBCPZ402 –40°C to +125°C 5 Mbit 400 MHz 88-Lead LFCSP_VQ CP-88-5
AD21489WBSWZ4xx –40°C to +125°C 5 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2
AD21489WBSWZ4xxRL –40°C to +125°C 5 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2
AD21489WBSWZ4Bxx –40°C to +125°C 5 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2
1
Z =RoHS Compliant Part.
2
W = automotive applications.
3
xx denotes the current die revision.
4
RL = Tape and Reel.
5
Referenced temperature is junction temperature. See Operating Conditions for junction temperature (TJ) specification.
6
This product contains IP from Dolby, DTS and DTLA. Proper software licenses required. Contact Analog Devices, Inc. for information.
Processor
Instruction
Model1, 2 Notes Temperature Range3 RAM Rate (Max) Package Description Package Option
4
ADSP-21483KSWZ-2B 0°C to +110°C 3 Mbit 300 MHz 176-Lead LQFP_EP SW-176-2
4
ADSP-21483KSWZ-3B 0°C to +110°C 3 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2
4
ADSP-21483KSWZ-3AB 0°C to +110°C 3 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2
4
ADSP-21483KSWZ-4B 0°C to +110°C 3 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2
4
ADSP-21483KSWZ-4AB 0°C to +110°C 3 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2
4
ADSP-21486KSWZ-2A 0°C to +110°C 5 Mbit 300 MHz 100-Lead LQFP_EP SW-100-2
4
ADSP-21486KSWZ-2B 0°C to +110°C 5 Mbit 300 MHz 176-Lead LQFP_EP SW-176-2
4
ADSP-21486KSWZ-2AB 0°C to +110°C 5 Mbit 300 MHz 100-Lead LQFP_EP SW-100-2
4
ADSP-21486KSWZ-2BB 0°C to +110°C 5 Mbit 300 MHz 176-Lead LQFP_EP SW-176-2
4
ADSP-21486KSWZ-3A 0°C to +110°C 5 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2
4
ADSP-21486KSWZ-3B 0°C to +110°C 5 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2
4
ADSP-21486KSWZ-3AB 0°C to +110°C 5 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2
4
ADSP21486KSWZ3ABRL 0°C to +110°C 5 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2
4
ADSP-21486KSWZ-3BB 0°C to +110°C 5 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2
4
ADSP-21486KSWZ-4A 0°C to +110°C 5 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2
4
ADSP-21486KSWZ-4AB 0°C to +110°C 5 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2
4
ADSP-21487KCPZ-4 0°C to +115°C 5 Mbit 400 MHz 88-Lead LFCSP_VQ CP-88-5
4
ADSP-21487KSWZ-2B 0°C to +110°C 5 Mbit 300 MHz 176-Lead LQFP_EP SW-176-2
4
ADSP-21487KSWZ-2BB 0°C to +110°C 5 Mbit 300 MHz 176-Lead LQFP_EP SW-176-2
4
ADSP-21487KSWZ-3B 0°C to +110°C 5 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2
4
ADSP-21487KSWZ-3BB 0°C to +110°C 5 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2
4
ADSP-21487KSWZ-4B 0°C to +110°C 5 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2
4
ADSP-21487KSWZ-4BB 0°C to +110°C 5 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2
4, 5
ADSP-21487KSWZ-5B 0°C to +115°C 5 Mbit 450 MHz 176-Lead LQFP_EP SW-176-2
4, 5
ADSP-21487KSWZ-5BB 0°C to +115°C 5 Mbit 450 MHz 176-Lead LQFP_EP SW-176-2
4, 5
ADSP21487KSWZ5BBRL 0°C to +115C 5 Mbit 450 MHz 176-Lead LQFP_EP SW-176-2
ADSP-21488BSWZ-3A –40°C to +125°C 3 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2
ADSP-21488KSWZ-3A 0°C to +110°C 3 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2
6
ADSP-21488KSWZ-3A1 0°C to +110°C 3 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2
ADSP-21488KSWZ-3B 0°C to +110C 3 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2
ADSP-21488BSWZ-3B –40°C to +125°C 3 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2
ADSP-21488KSWZ-4A 0°C to +110°C 3 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2
ADSP-21488BSWZ-4A –40°C to +125°C 3 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2
ADSP-21488KSWZ-4B 0°C to +110°C 3 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2
ADSP-21488BSWZ-4B –40°C to +125°C 3 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2
6
ADSP-21488KSWZ-4B1 0°C to +110°C 3 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).