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    Processor Core Options

    Uploaded by

    Devesh Bhaskaran

    Copyright:

    © All Rights Reserved
    Download as XLSX, PDF, TXT or read online from Scribd

    Processor Core Options

    Uploaded by

    Devesh Bhaskaran
    7 views4 pages

    Original Title

    Processor_Core_options

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    © © All Rights Reserved

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    Copyright:

    © All Rights Reserved
    Download as XLSX, PDF, TXT or read online from Scribd
    Download as xlsx, pdf, or txt
    7 views4 pages

    Processor Core Options

    Uploaded by

    Devesh Bhaskaran

    Copyright:

    © All Rights Reserved
    Download as XLSX, PDF, TXT or read online from Scribd
    Download as xlsx, pdf, or txt
    of 4

    Core Comparison

    Feature M33 M55


    License availability ADI Perpetual Not used by ADI yet, Cost $$$
    FuSA ASIL D Certified Expected in 2022
    Dual Core Lock-step Yes Yes (in Sep 2021 release)
    ECC on memories No Yes
    ECC on Cache No Cache Yes
    Sa
    Fu
    Memory protection unit
    (MPU) Optional Optional
    TrustZone Optional Optional
    DMIPS/MHz 1.5 1.6
    CoreMark/MHz 3.86 4.4
    Max frequency (To be
    ce

    validated) 235 MHz (40LP SVT) 215 MHz (40LP SVT/LVT 1.1V)
    an
    rm

    MAC (Execution cycles) 2 ( Throughput =1) 2 ( Throughput =1)


    rfo
    Pe

    MUL 32b (Execution cycles) 2 2


    FPU SP (Execution cycles) 3 5
    FPU DP (Execution cycles) No 35
    Pipeline stages 3 4
    Tightly Coupled Mem No Yes, up to 16MB
    Address bits 32bit 32bit
    Internal power modes - finer
    Power modes Internal power modes control
    2x16b SIMD or 4x8b
    SIMD, only on integer 2x16b SIMD or 4x8b SIMD, only
    DSP functions data - optional on integer data
    e
    ur
    ct

    Optional - Single
    ite
    ch

    FPU precision Optional - double precision


    Ar

    2x32b or 4x16b or 8x8b SIMD,


    can be floating point with
    Vector Processing No Helium extn
    Bus interface AHB5 AXI
    Peripheral Bus NA AHBP
    upto 480 external
    Interrupt interrupts upto 480 external interrupts
    optional - 4/8
    Breakpoint Unit breakpoints optional - 4/8 breakpoints
    g

    Debug CoreSight CoreSight


    bu
    De

    Trace Optional Optional


    Selftest No No
    S
    W
    SW support CMSIS, STL CMSIS, STL
    Process corner 40 ULP, 9T uLVT 40LP, 9T
    0.191 typical
    Area (sq. mm) - Single core 0.093 typical 0.3 (with helium, FPU)
    er
    ow
    ,P
    ea
    Ar
    15.75 - 21.40 (Typical)
    Power (uW/MHz) - Single 45 (with helium, FPU)
    core 12.6 - 17.1 Leakage : 70mW

    Performance issues :
    No Cache.
    No TCM.
    Require external
    SRAM controlelr and
    Cache controller Risk for the Enforcer+ program
    ECC controllers since no gurantee on ASIL-D
    Summary
    Core IP Cost Only Royalty NRE (1M USD) + Royalty
    Additional IPs, design effort High Low
    Safety SW re-work Low Low
    Trustzone Yes Yes
    FPU SIMD No float32 SIMD
    ASIL-D Collaterals Yes In Progress - 2022* expected
    Compute Requirement HW Accelerator HW Accelerator
    R5
    Enforcer
    ASIL D Certified
    Supported
    Optional - ECC logic on TCMs
    Optional - ECC scheme is fixed

    Optional
    No
    1.66
    3.47

    200MHz (40ULP SVT)


    2
    2
    1
    13
    8
    Optional - 8MB
    32bit

    No

    2x16b SIMD or 4x8b SIMD, only on


    integer data

    Optional - double precision

    No
    AXI
    AHBP

    External interrupt controller

    optional - 4/8 breakpoints


    CoreSight
    Optional
    No

    STL - SW team feedback


    40 ULP, 1.1V

    0.2
    50-70

    NRE (700K USD) + Royalty


    Low
    High
    No
    No
    Yes
    HW Accelerator

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