Data Sheet

a SHARC® Processor
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SUMMARY
High performance, 32-bit/40-bit, floating-point processor The ADSP-2136x processors are available with a 333 MHz
optimized for high performance processing core instruction rate and unique peripherals such as the digi-
Single-instruction, multiple-data (SIMD) computational tal audio interface, S/PDIF transceiver, DTCP (digital
architecture transmission content protection protocol), serial ports,
On-chip memory—3M bit of on-chip SRAM 8-channel asynchronous sample rate converter, precision
Code compatible with all other members of the SHARC family clock generators, and more. For complete ordering informa-
tion, see Ordering Guide on Page 52.
4 BLOCKS OF ON-CHIP MEMORY

CORE PROCESSOR
BLOCK 0 BLOCK 1 BLOCK 2 BLOCK 3
INSTRUCTION
SRAM SRAM
TIMER CACHE SRAM SRAM
1M BIT ROM 1M BIT ROM
32-BIT ⴛ 48-BIT 0.5M BIT 0.5M BIT
2M BIT 2M BIT
DAG1 DAG2 ADDR DATA ADDR DATA ADDR DATA ADDR DATA
PROGRAM
8ⴛ4ⴛ32 8ⴛ4ⴛ32
SEQUENCER
PM ADDRESS BUS 32
DM ADDRESS BUS 32
PM DATA BUS 64
DM DATA BUS 64
IOA IOD IOA IOD IOA IOD IOA IOD
PX REGISTER SPI
PROCESSING PROCESSING SPORTS
ELEMENT ELEMENT IDP
(PEX) (PEY) IOP REGISTERS PCG SIGNAL
(MEMORY MAPPED) TIMERS ROUTING
SRC UNIT
SPDIF
DTCP
6
JTAG TEST AND EMULATION
I/O PROCESSOR
AND PERIPHERALS
S
Figure 1. Functional Block Diagram—Processor Core
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
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registered trademarks are the property of their respective owners. Fax: 781.461.3113 © 2006 Analog Devices, Inc. All rights reserved.
KEY FEATURES—PROCESSOR CORE Up to 12 TDM stream support, each with 128 channels per
frame
At 333 MHz (3.0 ns) core instruction rate, the ADSP-2136x
Companding selection on a per channel basis in TDM mode
performs 2 GFLOPS/666 MMACs
Input data port provides an additional input path to the pro-
3M bit on-chip SRAM (1M bit in blocks 0 and 1, and 0.50M bit
cessor core, configurable as eight channels of serial data or
in blocks 2 and 3) for simultaneous access by the core pro-
seven channels of serial data, and up to a 20-bit wide paral-
cessor and DMA
lel data channel
4M bit on-chip ROM (2M bit in block 0 and 2M bit in block 1)
Signal routing unit provides configurable and flexible con-
Dual data address generators (DAGs) with modulo and bit-
nections between all DAI components–six serial ports, one
reverse addressing
SPI port, eight channels of asynchronous sample rate con-
Zero-overhead looping with single-cycle loop setup, provid- verters, an S/PDIF receiver/transmitter, three timers, an SPI
ing efficient program sequencing port,10 interrupts, six flag inputs, six flag outputs, and
Single-instruction multiple-data (SIMD) architecture 20 SRU I/O pins (DAI_Px)
provides: Two serial peripheral interfaces (SPI): primary on dedicated
Two computational processing elements pins, secondary on DAI pins provide:
Concurrent execution Master or slave serial boot through primary SPI
Code compatibility with other SHARC family members at Full-duplex operation
the assembly level Master slave mode multimaster support
Parallelism in buses and computational units allows single Open drain outputs
cycle execution (with or without SIMD) of a multiply
Programmable baud rates, clock polarities, and phases
operation, an ALU operation, a dual memory read or
3 muxed flag/IRQ lines
write, and an instruction fetch
1 muxed flag/timer expired line
Transfers between memory and core at a sustained
5.4G bytes/s bandwidth at 333 MHz core instruction rate DEDICATED AUDIO COMPONENTS
INPUT/OUTPUT FEATURES S/PDIF-compatible digital audio receiver/transmitter
supports:
DMA controller supports:
EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards
25 DMA channels for transfers between ADSP-2136x internal
memory and a variety of peripherals Left-justified, I2S, or right-justified serial data input with
16-, 18-, 20- or 24-bit word widths (transmitter)
32-bit DMA transfers at peripheral clock speed, in parallel
with full-speed processor execution Two channel mode and single channel double frequency
(SCDF) mode
Asynchronous parallel port provides access to asynchronous
external memory Sample rate converter (SRC) contains a serial input port,
de-emphasis filter, sample rate converter (SRC) and serial
16 multiplexed address/data lines support 24-bit address
output port providing up to –140 dB SNR performance (see
external address range with 8-bit data or 16-bit address
Table 2 on Page 4)
external address range with 16-bit data
Supports left-justified, I2S, TDM, and right-justified
55M byte per sec transfer rate
24-, 20-, 18-, and 16-bit serial formats (input)
External memory access in a dedicated DMA channel
Pulse-width modulation provides:
8-bit to 32-bit and 16-bit to 32-bit packing options
16 PWM outputs configured as four groups of four outputs
Programmable data cycle duration: 2 CCLK to 31 CCLK
Supports center-aligned or edge-aligned PWM waveforms
Digital audio interface (DAI) includes six serial ports, two pre-
Can generate complementary signals on two outputs in
cision clock generators, an input data port, three timers, an
paired mode or independent signals in nonpaired mode
S/PDIF transceiver, a DTCP cipher, an 8-channel asynchro-
ROM-based security features include:
nous sample rate converter, an SPI port, and a signal
routing unit JTAG access to memory permitted with a 64-bit key
Six dual data line serial ports that operate at up to 41.67M Protected memory regions that can be assigned to limit
bits/s on each data line—each has a clock, frame sync, and access under program control to sensitive code
two data lines that can be configured as either a receiver or PLL has a wide variety of software and hardware multi-
transmitter pair plier/divider ratios
Left-justified sample pair and I2S support, programmable Dual voltage: 3.3 V I/O, 1.2 V core
direction for up to 24 simultaneous receive or transmit Available in 136-ball BGA package (see Ordering Guide on
channels using two I2S-compatible stereo devices per Page 52)
serial port
TDM support for telecommunications interfaces including
128 TDM channel support for newer telephony interfaces
such as H.100/H.110
Rev. A | Page 2 of 52 | December 2006

TABLE OF CONTENTS
Summary ................................................................1 REVISION HISTORY
Key Features—Processor Core ..................................2 12/06—Rev 0 to Rev A
Input/Output Features ............................................2 This version of the data sheet combines the ADSP-21362,
Dedicated Audio Components ..................................2 ADSP-21363, ADSP-21364, ADSP-21365, and ADSP-21366
data sheets. Throughout this document, these products are
General Description ..................................................4
referred to as “ADSP-2136x” except where features or specifica-
SHARC Family Core Architecture .............................5 tions apply to a specific processor. For a comparison of each
Memory and I/O Interface Features ............................6 processor, see Table 2 on Page 4.
Development Tools .............................................. 10 Added Package Information ......................................17
Additional Information ......................................... 11 Fixed Figure 6, Core Clock and System Clock Relationship to
CLKIN .................................................................18
Pin Function Descriptions ........................................ 12
Fixed Figure 24, IDP Master Timing ............................34
Address Data Pins as FLAGs .................................. 15
This version of the data sheet is for BGA parts only. An alternate
Address/Data Modes ............................................ 15 LQFP package (exposed pad) will be available in the future.
Boot Modes ........................................................ 15 Information on that option is available on the ADSP-21365
Core Instruction Rate to CLKIN Ratio Modes ............. 15 product page. See Ordering Guide ...............................52
ADSP-2136x Specifications ....................................... 16

Operating Conditions ........................................... 16
Electrical Characteristics ........................................ 16
Package Information ............................................ 17
Maximum Power Dissipation ................................. 17
Absolute Maximum Ratings ................................... 17
ESD Sensitivity .................................................... 17
Timing Specifications ........................................... 18
Output Drive Currents .......................................... 46
Test Conditions ................................................... 46
Capacitive Loading ............................................... 46
Thermal Characteristics ........................................ 47
136-Ball BGA Pin Configurations ............................... 48
Outline Dimensions ................................................ 51
Surface Mount Design .......................................... 51
Ordering Guide ...................................................... 52

GENERAL DESCRIPTION
The ADSP-2136x SHARC processor is a member of the SIMD • On-chip ROM (4M bit)
SHARC family of DSPs that feature Analog Devices’ Super Har- • 8-bit or 16-bit parallel port that supports interfaces to off-
vard Architecture. The processor is source code-compatible chip memory peripherals
with the ADSP-2126x and ADSP-2116x DSPs, as well as with
first generation ADSP-2106x SHARC processors in SISD (sin- • JTAG test access port
gle-instruction, single-data) mode. The ADSP-2136x is a
32-bit/40-bit floating-point processor optimized for high Table 2. ADSP-2136x SHARC Processor Family Features
performance automotive audio applications with a large on-
chip SRAM and ROM, multiple internal buses to eliminate I/O
ADSP-21362
ADSP-21363
ADSP-21364
ADSP-21365
ADSP-21366
bottlenecks, and an innovative digital audio interface (DAI).
As shown in the functional block diagram on Page 1, the
ADSP-2136x uses two computational units to deliver a signifi-
Feature
cant performance increase over the previous SHARC processors
on a range of signal processing algorithms. Fabricated in a state- RAM 3M bit 3M bit 3M bit 3M bit 3M bit
of-the-art, high speed, CMOS process, the ADSP-2136x proces- ROM 4M bit 4M bit 4M bit 4M bit 4M bit
sor achieves an instruction cycle time of 3.0 ns at 333 MHz.
With its SIMD computational hardware, the ADSP-2136x can Audio No No No Yes Yes
perform two GFLOPS running at 333 MHz. Decoders in
ROM1
Table 2 shows the features of the individual product offerings
and Table 1 shows performance benchmarks for the processors Pulse Width Yes Yes Yes Yes Yes
running at 333 MHz. Modulation
S/PDIF Yes No Yes Yes Yes
Table 1. Benchmarks (at 333 MHz)
DTCP2 Yes No No Yes No
Speed
Benchmark Algorithm (at 333 MHz) SRC 128 dB No SRC 140 dB 128 dB 128 dB
Performance
1024 Point Complex FFT (Radix 4, with reversal) 27.9 μs
1
Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Prologic IIx,
FIR Filter (per tap)1 1.5 ns
DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like Bass
IIR Filter (per biquad)1 6.0 ns management, delay, speaker equalization, graphic equalization, and more.
Decoder/post-processor algorithm combination support varies depending upon
Matrix Multiply (pipelined) the chip version and the system configurations. Please visit www.analog.com for
[3×3] × [3×1] 13.5 ns complete information.
2
[4×4] × [4×1] 23.9 ns The ADSP-21362 and ADSP-21365 processors provide the Digital Transmission
Content Protection protocol, a proprietary security protocol. Contact your
Divide (y/x) 10.5 ns Analog Devices sales office for more information.
Inverse Square Root 16.3 ns
1
Assumes two files in multichannel SIMD mode The block diagram on Page 7 illustrates the following architec-
tural features:
The ADSP-2136x continues SHARC’s industry-leading stan-
• DMA controller
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features. • Six full duplex serial ports
The block diagram on Page 1, illustrates the following architec- • Two SPI-compatible interface ports—primary on dedi-
tural features: cated pins, secondary on DAI pins
• Two processing elements, each of which comprises an • Digital audio interface that includes two precision clock
ALU, multiplier, shifter, and data register file generators (PCG), an input data port (IDP), an S/PDIF
receiver/transmitter, eight channels asynchronous sample
• Data address generators (DAG1, DAG2)
rate converter, DTCP cipher, six serial ports, eight serial
• Program sequencer with instruction cache interfaces, a 20-bit parallel input port, 10 interrupts, six flag
• PM and DM buses capable of supporting four 32-bit data outputs, six flag inputs, three timers, and a flexible signal
transfers between memory and the core at every core pro- routing unit (SRU)
cessor cycle Figure 2 shows a sample SPORT configuration using the preci-
• Three programmable interval timers with PWM genera- sion clock generators to interface with an I2S ADC and an I2S
tion, PWM capture/pulse width measurement, and DAC with a much lower jitter clock than the serial port would
external event counter capabilities generate itself. Many other SRU configurations are possible.
• On-chip SRAM (3M bit)

ADSP-2136x
CLK OU T
C LOC K C LK IN
X TA L A LE
2 C LK _C FG1-0 AD 1 5-0 LA TCH A DD R
PA R A LLEL
2 B OOTC FG1 -0 D ATA POR T
3 RD RAM
FLA G3-1 OE I /O D EVI CE
WR WE
FLA G0 CS
A DC
(OPTI ONA L)
CONTROL
DATA
ADDRESS
C LK D A I_P1
FS DA I_ P2
S D AT DA I_ P3
S C LK 0
S FS0
SR U S D 0A
D AC
(OPTI ONA L) S D 0B
C LK D A I_P 18
SP OR T0-5
FS D AI _P 19 TIME R S
S D AT DA I_ P2 0 SPD IF
SR C
ID P
S PI
C LK
FS
PC GA
DAI P CG B
R ES ET JTA G
Figure 2. ADSP-2136x System Sample Configuration
SHARC FAMILY CORE ARCHITECTURE bandwidth between memory and the processing elements.
When using the DAGs to transfer data in SIMD mode, two data
The ADSP-2136x is code-compatible at the assembly level with
values are transferred with each access of memory or the regis-
the ADSP-2126x, ADSP-21160, and ADSP-21161, and with the
ter file.
first generation ADSP-2106x SHARC processors. The
ADSP-2136x shares architectural features with the ADSP-2126x Independent, Parallel Computation Units
and ADSP-2116x SIMD SHARC processors, as detailed in the
Within each processing element is a set of computational units.
following sections.
The computational units consist of an arithmetic/logic unit
SIMD Computational Engine (ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
The ADSP-2136x contains two computational processing ele-
element are arranged in parallel, maximizing computational
ments that operate as a single-instruction multiple-data (SIMD)
throughput. Single multifunction instructions execute parallel
engine. The processing elements are referred to as PEX and PEY
ALU and multiplier operations. In SIMD mode, the parallel
and each contains an ALU, multiplier, shifter, and register file.
ALU and multiplier operations occur in both processing
PEX is always active, and PEY may be enabled by setting the
elements. These computation units support IEEE 32-bit
PEYEN mode bit in the MODE1 register. When this mode is
single-precision floating-point, 40-bit extended-precision
enabled, the same instruction is executed in both processing ele-
floating-point, and 32-bit fixed-point data formats.
ments, but each processing element operates on different data.
This architecture is efficient at executing math intensive signal Data Register File
processing algorithms.
A general-purpose data register file is contained in each pro-
Entering SIMD mode also has an effect on the way data is trans- cessing element. The register files transfer data between the
ferred between memory and the processing elements. When in computation units and the data buses, and store intermediate
SIMD mode, twice the data bandwidth is required to sustain results. These 10-port, 32-register (16 primary, 16 secondary)
computational operation in the processing elements. Because of register files, combined with the ADSP-2136x enhanced
this requirement, entering SIMD mode also doubles the

Harvard architecture, allow unconstrained data flow between signal processing, and are commonly used in digital filters and
computation units and internal memory. The registers in PEX Fourier transforms. The two DAGs contain sufficient registers
are referred to as R0–R15 and in PEY as S0–S15. to allow the creation of up to 32 circular buffers (16 primary
register sets, 16 secondary). The DAGs automatically handle
Single-Cycle Fetch of Instruction and Four Operands address pointer wraparound, reduce overhead, increase perfor-
The ADSP-2136x features an enhanced Harvard architecture in mance, and simplify implementation. Circular buffers can start
which the data memory (DM) bus transfers data and the pro- and end at any memory location.
gram memory (PM) bus transfers both instructions and data
(see Figure 1 on Page 1). With the processor’s separate program Flexible Instruction Set
and data memory buses and on-chip instruction cache, the pro- The 48-bit instruction word accommodates a variety of parallel
cessor can simultaneously fetch four operands (two over each operations, for concise programming. For example, the
data bus) and one instruction (from the cache), all in a ADSP-2136x can conditionally execute a multiply, an add, and a
single cycle. subtract in both processing elements while branching and fetch-
ing up to four 32-bit values from memory—all in a single
Instruction Cache instruction.
The ADSP-2136x includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four MEMORY AND I/O INTERFACE FEATURES
data values. The cache is selective—only the instructions whose The ADSP-2136x adds the following architectural features to
fetches conflict with PM bus data accesses are cached. This the SIMD SHARC family core.
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly On-Chip Memory
processing. The ADSP-2136x contains three megabits of internal SRAM
and four megabits of internal ROM. Each block can be config-
Data Address Generators with Zero-Overhead Hardware
ured for different combinations of code and data storage (see
Circular Buffer Support Table 3). Each memory block supports single-cycle, indepen-
The ADSP-2136x’s two data address generators (DAGs) are dent accesses by the core processor and I/O processor. The
used for indirect addressing and implementing circular data processor’s memory architecture, in combination with its sepa-
buffers in hardware. Circular buffers allow efficient program- rate on-chip buses, allows two data transfers from the core and
ming of delay lines and other data structures required in digital one from the I/O processor, in a single cycle.
Table 3. ADSP-2136x Internal Memory Space
IOP Registers 0x0000 0000–0003 FFFF

Extended Precision Normal or
Long Word (64 Bits) Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)
BLOCK 0 ROM BLOCK 0 ROM BLOCK 0 ROM BLOCK 0 ROM
0x0004 0000–0x0004 7FFF 0x0008 0000–0x0008 AAA9 0x0008 0000–0x0008 FFFF 0x0010 0000–0x0011 FFFF
Reserved Reserved Reserved
0x0004 8000–0x0004 BFFF 0x0009 0000–0x0009 7FFF 0x0012 0000–0x0012 FFFF
BLOCK 0 SRAM BLOCK 0 SRAM BLOCK 0 SRAM BLOCK 0 SRAM
0x0004 C000–0x0004 FFFF 0x0009 0000–0x0009 5554 0x0009 8000–0x0009 FFFF 0x0013 0000–0x0013 FFFF
BLOCK 1 ROM BLOCK 1 ROM BLOCK 1 ROM BLOCK 1 ROM
0x0005 0000–0x0005 7FFF 0x000A 0000–0x000A AAA9 0x000A 0000–0x000A FFFF 0x0014 0000–0x0015 FFFF
0x0005 8000–0x0005 BFFF 0x000B 0000–0x000B 7FFF 0x0016 0000–0x0016 FFFF
0x0005 C000–0x0005 FFFF 0x000B 0000–0x000B 5554 0x000B 8000–0x000B FFFF 0x0017 0000–0x0017 FFFF
0x0006 0000–0x0006 1FFF 0x000C 0000–0x000C 2AA9 0x000C 0000–0x000C 3FFF 0x0018 0000–0x0018 7FFF
0x0006 2000–0x0006 FFFF 0x000C 4000–0x000D FFFF 0x0018 8000–0x001B FFFF
0x0007 0000–0x0007 1FFF 0x000E 0000–0x000E 2AA9 0x000E 0000–0x000E 3FFF 0x001C 0000–0x001C 7FFF

Table 3. ADSP-2136x Internal Memory Space (Continued)
IOP Registers 0x0000 0000–0003 FFFF

Extended Precision Normal or
Long Word (64 Bits) Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)
0x0007 2000–0x0007 FFFF 0x000E 4000–0x000F FFFF 0x001C 8000–0x001F FFFF
Reserved
0x0020 0000–0xFFFF FFFF
The SRAM can be configured as a maximum of 96K words of DAI- associated peripherals for a much wider variety of applica-
32-bit data, 192K words of 16-bit data, 64K words of 48-bit tions by using a larger set of algorithms than is possible with
instructions (or 40-bit data), or combinations of different word nonconfigurable signal paths.
sizes up to three megabits. All of the memory can be accessed as
16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point
storage format is supported that effectively doubles the amount TO PROCESSOR BUSES AND
SYSTEM MEMORY
of data that may be stored on-chip. Conversion between the 32-
bit floating-point and 16-bit floating-point formats is per- IO DATA IO ADDRESS
formed in a single instruction. While each memory block can BUS (32) BUS (18)
store combinations of code and data, accesses are most efficient

GPIO FLAGS/IRQ/TIMEXP
when one block stores data using the DM bus for transfers, and 4
the other block stores instructions and data using the PM bus DMA CONTROLLER
25 CHANNELS
for transfers. 3
CONTROL/GPIO
Using the DM bus and PM buses, with one bus dedicated to 16
ADDRESS/DATA BUS/ GPIO
each memory block, assures single-cycle execution with two
PARALLEL PORT
data transfers. In this case, the instruction must be available in
the cache. PWM (16)
4
DMA Controller
SPI PORT (1)
The ADSP-2136x’s on-chip DMA controllers allow data trans- 4
CONTROL, STATUS, AND DATA BUFFERS
fers without processor intervention. The DMA controller SPI PORT (1)
operates independently and invisibly to the processor core,
allowing DMA operations to occur while the core is simulta- SERIAL PORTS (6)
(MEMORY MAPPED)
neously executing its program instructions. DMA transfers can

IOP REGISTERS
SIGNAL ROUTING UNIT

occur between the processor’s internal memory and its serial INPUT
DATA PORTS (8)
ports, the SPI-compatible (serial peripheral interface) ports, the 20
IDP (input data port), the parallel data acquisition port (PDAP), DTCP CIPHER
or the parallel port. Twenty-five channels of DMA are available
on the processors—two for the SPI interface, 12 via the serial SPDIF (Rx/Tx)
ports, eight via the input data port, two for DTCP (or memory-
to-memory data transfer when DTCP is not used), and one via SRC (8 CHANNELS)
the processor’s parallel port. Programs can be downloaded to
the processors using DMA transfers. Other DMA features PRECISION CLOCK
include interrupt generation upon completion of DMA trans- GENERATORS (2)
fers, and DMA chaining for automatic linked DMA transfers. 3

TIMERS (3)
Digital Audio Interface (DAI) DIGITAL AUDIO INTERFACE

The digital audio interface (DAI) provides the ability to connect
I/O PROCESSOR
various peripherals to any of the DSP’s DAI pins (DAI_P20–1).
Programs make these connections using the signal routing unit
Figure 3. ADSP-2136x I/O Processor and
(SRU, shown in Figure 3).
Peripherals Block Diagram
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon- The DAI also includes six serial ports, an S/PDIF receiver/trans-
nected under software control. This allows easy use of the mitter, a DTCP cipher, a precision clock generator (PCG), eight
channels of asynchronous sample rate converters, an input data
port (IDP), an SPI port, six flag outputs and six flag inputs, and

three timers. The IDP provides an additional input path to the Parallel Port
ADSP-2136x core, configurable as either eight channels of I2S
The parallel port provides interfaces to SRAM and peripheral
serial data or as seven channels plus a single 20-bit wide syn-
devices. The multiplexed address and data pins (AD15–0) can
chronous parallel data acquisition port. Each data channel has
access 8-bit devices with up to 24 bits of address, or 16-bit
its own DMA channel that is independent from the processor’s
devices with up to 16 bits of address. In either mode, 8-bit or
serial ports.
16-bit, the maximum data transfer rate is 55M bytes/sec.
For complete information on using the DAI, see the
DMA transfers are used to move data to and from internal
ADSP-2136x SHARC Processor Hardware Reference.
memory. Access to the core is also facilitated through the paral-
Serial Ports lel port register read/write functions. The RD, WR, and ALE
(address latch enable) pins are the control pins for the
The ADSP-2136x features six synchronous serial ports that pro- parallel port.
vide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog Devices’ Serial Peripheral (Compatible) Interface
AD183x family of audio codecs, ADCs, and DACs. The serial
The processors contain two serial peripheral interface ports
ports are made up of two data lines, a clock, and a frame sync.
(SPIs). The SPI is an industry-standard synchronous serial link,
The data lines can be programmed to either transmit or receive
enabling the ADSP-2136x SPI-compatible port to communicate
and each data line has a dedicated DMA channel.
with other SPI-compatible devices. The SPI consists of two data
Serial ports are enabled via 12 programmable and simultaneous pins, one device select pin, and one clock pin. It is a full-duplex
receive or transmit pins that support up to 24 transmit or 24 synchronous serial interface, supporting both master and slave
receive channels of audio data when all six SPORTS are enabled, modes. The SPI port can operate in a multimaster environment
or six full duplex TDM streams of 128 channels per frame. by interfacing with up to four other SPI-compatible devices,
The serial ports operate at a maximum data rate of 41.67 M either acting as a master or slave device. The ADSP-2136x SPI-
bits/s. Serial port data can be automatically transferred to and compatible peripheral implementation also features program-
from on-chip memory via dedicated DMA channels. Each of the mable baud rate, clock phase, and polarities. The SPI-
serial ports can work in conjunction with another serial port to compatible port uses open drain drivers to support a multimas-
provide TDM support. One SPORT provides two transmit sig- ter configuration and to avoid data contention.
nals while the other SPORT provides the two receive signals. S/PDIF-Compatible Digital Audio Receiver/Transmitter
The frame sync and clock are shared.
and Synchronous/Asynchronous Sample Rate Converter
Serial ports operate in four modes:
The S/PDIF transmitter has no separate DMA channels. It
• Standard DSP serial mode receives audio data in serial format and converts it into a
• Multichannel (TDM) mode biphase encoded signal. The serial data input to the transmitter
can be formatted as left-justified, I2S, or right-justified with
• I2S mode
word widths of 16, 18, 20, or 24 bits.
• Left-justified sample pair mode
The serial data, clock, and frame sync inputs to the S/PDIF
Left-justified sample pair mode is a mode where in each frame transmitter are routed through the signal routing unit (SRU).
sync cycle two samples of data are transmitted/received—one They can come from a variety of sources such as the SPORTs,
sample on the high segment of the frame sync, the other on the external pins, the precision clock generators (PCGs), or the
low segment of the frame sync. Programs have control over var- sample rate converters (SRC) and are controlled by the SRU
ious attributes of this mode. control registers.
Each of the serial ports supports the left-justified sample pair The sample rate converter (SRC) contains four SRC blocks and
and I2S protocols (I2S is an industry-standard interface com- is the same core as that used in the AD1896 192 kHz stereo
monly used by audio codecs, ADCs, and DACs, such as the asynchronous sample rate converter and provides up to 140 dB
Analog Devices AD183x family), with two data pins, allowing SNR (see Table 2 on Page 4 for details). The SRC block is used
four left-justified sample pair or I2S channels (using two stereo to perform synchronous or asynchronous sample rate conver-
devices) per serial port, with a maximum of up to 24 I2S chan- sion across independent stereo channels, without using internal
nels. The serial ports permit little-endian or big-endian processor resources. The four SRC blocks can also be config-
transmission formats and word lengths selectable from 3 bits to ured to operate together to convert multichannel audio data
32 bits. For the left-justified sample pair and I2S modes, data- without phase mismatches. Finally, the SRC is used to clean up
word lengths are selectable between 8 bits and 32 bits. Serial audio data from jittery clock sources such as the S/PDIF
ports offer selectable synchronization and transmit modes as receiver. The S/PDIF and SRC are not available on the
well as optional μ-law or A-law companding selection on a per ADSP-21363 models.
channel basis. Serial port clocks and frame syncs can be inter-
nally or externally generated. Digital Transmission Content Protection
The DTCP specification defines a cryptographic protocol for
protecting audio entertainment content from illegal copying,
intercepting, and tampering as it traverses high performance

digital buses, such as the IEEE 1394 standard. Only legitimate Additionally, the processor is not freely accessible via the JTAG
entertainment content delivered to a source device via another port. Instead, a unique 64-bit key, which must be scanned in
approved copy protection system (such as the DVD content through the JTAG or test access port will be assigned to each
scrambling system) will be protected by this copy protection customer. The device will ignore a wrong key. Emulation fea-
system. This feature is available on the ADSP-21362 and tures and external boot modes are only available after the
ADSP-21365 processors only. Licensing through DTLA is correct key is scanned.
required for these products. Visit www.dtcp.com for more
information. Program Booting
The internal memory of the ADSP-2136x boots at system
Pulse-Width Modulation power-up from an 8-bit EPROM via the parallel port, an SPI
The PWM module is a flexible, programmable, PWM waveform master, an SPI slave, or an internal boot. Booting is determined
generator that can be programmed to generate the required by the boot configuration (BOOTCFG1–0) pins (see Table 7 on
switching patterns for various applications related to motor and Page 15). Selection of the boot source is controlled via the SPI as
engine control or audio power control. The PWM generator can either a master or slave device, or it can immediately begin exe-
generate either center-aligned or edge-aligned PWM wave- cuting from ROM.
forms. In addition, it can generate complementary signals on
two outputs in paired mode or independent signals in non- Phase-Locked Loop
paired mode (applicable to a single group of four PWM The processors use an on-chip phase-locked loop (PLL) to gen-
waveforms). erate the internal clock for the core. On power up, the
The entire PWM module has four groups of four PWM outputs CLKCFG1–0 pins are used to select ratios of 32:1, 16:1, and 6:1
each. Therefore, this module generates 16 PWM outputs in (see Table 8 on Page 15). After booting, numerous other ratios
total. Each PWM group produces two pairs of PWM signals on can be selected via software control.
the four PWM outputs. The ratios are made up of software configurable numerator val-
The PWM generator is capable of operating in two distinct ues from 1 to 64 and software configurable divisor values of 1, 2,
modes while generating center-aligned PWM waveforms: single 4, and 8.
update mode or double update mode. In single update mode the Power Supplies
duty cycle values are programmable only once per PWM period.
This results in PWM patterns that are symmetrical about the The ADSP-2136x has a separate power supply connection for
midpoint of the PWM period. In double update mode, a second the internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS)
updating of the PWM registers is implemented at the midpoint power supplies. The internal and analog supplies must meet the
of the PWM period. In this mode, it is possible to produce 1.2 V requirement for K, B, and Y grade models, and the 1.0 V
asymmetrical PWM patterns that produce lower harmonic dis- requirement for Y and W Grade models. (For information on
tortion in three-phase PWM inverters. the temperature ranges offered for this product, see Operating
Conditions on Page 16, Package Information on Page 17, and
Timers Ordering Guide on Page 52. The external supply must meet the
The ADSP-2136x has a total of four timers: a core timer that can 3.3 V requirement. All external supply pins must be connected
generate periodic software interrupts and three general-purpose to the same power supply.
timers that can generate periodic interrupts and be indepen- Note that the analog supply pin (AVDD) powers the processor’s
dently set to operate in one of three modes: internal clock generator PLL. To produce a stable clock, it is rec-
• Pulse waveform generation mode ommended that PCB designs use an external filter circuit for the
AVDD pin. Place the filter components as close as possible to the
• Pulse width count/capture mode AVDD/AVSS pins. For an example circuit, see Figure 4. (A recom-
• External event watchdog mode mended ferrite chip is the muRata BLM18AG102SN1D). To
The core timer can be configured to use FLAG3 as a timer reduce noise coupling, the PCB should use a parallel pair of
expired signal, and each general-purpose timer has one bidirec- power and ground planes for VDDINT and GND. Use wide traces
tional pin and four registers that implement its mode of to connect the bypass capacitors to the analog power (AVDD) and
operation: a 6-bit configuration register, a 32-bit count register, ground (AVSS) pins. Note that the AVDD and AVSS pins specified in
a 32-bit period register, and a 32-bit pulse width register. A sin- Figure 4 are inputs to the processor and not the analog ground
gle control and status register enables or disables all three plane on the board—the AVSS pin should connect directly to dig-
general-purpose timers independently. ital ground (GND) at the chip.
ROM-Based Security Target Board JTAG Emulator Connector

The ADSP-2136x has a ROM security feature that provides Analog Devices DSP Tools product line of JTAG emulators uses
hardware support for securing user software code by preventing the IEEE 1149.1 JTAG test access port of the processor to moni-
unauthorized reading from the internal code when enabled. tor and control the target board processor during emulation.
When using this feature, the processor does not boot-load any Analog Devices’ DSP Tools product line of JTAG emulators
external code, executing exclusively from internal SRAM/ROM. provides emulation at full processor speed, allowing inspection

Debugging both C/C++ and assembly programs with the
100nF 10nF 1nF
ADSP-213xx VisualDSP++ debugger, programmers can:
VDDINT AVDD • View mixed C/C++ and assembly code (interleaved source
and object information)
HI Z FERRITE
BEAD CHIP
• Insert breakpoints
AVSS
• Set conditional breakpoints on registers, memory,
and stacks
LOCATE ALL COMPONENTS
CLOSE TO AVDD AND AVSS PINS • Trace instruction execution
Figure 4. Analog Power (AVDD) Filter Circuit • Perform linear or statistical profiling of program execution
• Fill, dump, and graphically plot the contents of memory
and modification of memory, registers, and processor stacks.
• Perform source level debugging
The processor’s JTAG interface ensures that the emulator will
not affect target system loading or timing. • Create custom debugger windows
For complete information on Analog Devices’ SHARC DSP The VisualDSP++ IDDE lets programmers define and manage
Tools product line of JTAG emulator operation, see the appro- DSP software development. Its dialog boxes and property pages
priate “Emulator Hardware User’s Guide.” let programmers configure and manage all of the SHARC devel-
opment tools, including the color syntax highlighting in the
DEVELOPMENT TOOLS VisualDSP++ editor. This capability permits programmers to:
The ADSP-2136x is supported with a complete set of • Control how the development tools process inputs and
CROSSCORE®† software and hardware development tools, generate outputs
including Analog Devices emulators and VisualDSP++®‡ devel-
• Maintain a one-to-one correspondence with the tool’s
opment environment. The same emulator hardware that
command line switches
supports other SHARC processors also fully emulates the
ADSP-2136x. The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
The VisualDSP++ project management environment lets pro-
ory and timing constraints of DSP programming. These
grammers develop and debug an application. This environment
capabilities enable engineers to develop code more effectively,
includes an easy to use assembler (which is based on an alge-
eliminating the need to start from the very beginning, when
braic syntax), an archiver (librarian/library builder), a linker, a
developing new application code. The VDK features include
loader, a cycle-accurate instruction-level simulator, a C/C++
threads, critical and unscheduled regions, semaphores, events,
compiler, and a C/C++ runtime library that includes DSP and
and device flags. The VDK also supports priority-based, pre-
mathematical functions. A key point for these tools is C/C++
emptive, cooperative, and time-sliced scheduling approaches. In
code efficiency. The compiler has been developed for efficient
addition, the VDK was designed to be scalable. If the application
translation of C/C++ code to DSP assembly. The SHARC has
does not use a specific feature, the support code for that feature
architectural features that improve the efficiency of compiled
is excluded from the target system.
C/C++ code.
Because the VDK is a library, a developer can decide whether to
The VisualDSP++ debugger has a number of important fea-
use it or not. The VDK is integrated into the VisualDSP++
tures. Data visualization is enhanced by a plotting package that
development environment, but can also be used via standard
offers a significant level of flexibility. This graphical representa-
command line tools. When the VDK is used, the development
tion of user data enables the programmer to quickly determine
environment assists the developer with many error-prone tasks
the performance of an algorithm. As algorithms grow in com-
and assists in managing system resources, automating the gen-
plexity, this capability can have increasing significance on the
eration of various VDK-based objects, and visualizing the
designer’s development schedule, increasing productivity. Sta-
system state, when debugging an application that uses the VDK.
tistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique VisualDSP++ component software engineering (VCSE) is Ana-
to VisualDSP++, enables the software developer to passively log Devices’ technology for creating, using, and reusing software
gather important code execution metrics without interrupting components (independent modules of substantial functionality)
the real-time characteristics of the program. Essentially, the to quickly and reliably assemble software applications. It allows
developer can identify bottlenecks in software quickly and downloading components from the Web, dropping them into
efficiently. By using the profiler, the programmer can focus on the application, and publishing component archives from
those areas in the program that impact performance and take within VisualDSP++. VCSE supports component implementa-
corrective action. tion in C/C++ or assembly language.
Use the expert linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza-
†
tion in a color-coded graphical form, easily move code and data
CROSSCORE is a registered trademark of Analog Devices, Inc.
‡ to different areas of the processor or external memory with a
VisualDSP++ is a registered trademark of Analog Devices, Inc.

drag of the mouse and examine runtime stack and heap usage. With a full version of VisualDSP++ installed (sold separately),
The expert linker is fully compatible with the existing linker def- engineers can develop software for the EZ-KIT Lite or any cus-
inition file (LDF), allowing the developer to move between the tom defined system. Connecting one of Analog Devices’ JTAG
graphical and textual environments. emulators to the EZ-KIT Lite board enables high speed, non-
In addition to the software and hardware development tools intrusive emulation.
available from Analog Devices, third parties provide a wide ADDITIONAL INFORMATION
range of tools supporting the SHARC processor family. Hard-
ware tools include SHARC processor PC plug-in cards. Third This data sheet provides a general overview of the
party software tools include DSP libraries, real-time operating ADSP-2136x architecture and functionality. For detailed infor-
systems, and block diagram design tools. mation on the ADSP-2136x family core architecture and
instruction set, refer to the ADSP-2136x SHARC Processor
Designing an Emulator-Compatible DSP Board (Target) Hardware Reference and the ADSP-2136x SHARC Processor
The Analog Devices family of emulators are tools that every Programming Reference.
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG test
access port (TAP) on each JTAG processor. Nonintrusive in-
circuit emulation is assured by the use of the processor’s JTAG
interface—the emulator does not affect target system loading or
timing. The emulator uses the TAP to access the internal fea-
tures of the processor, allowing the developer to load code, set
breakpoints, observe variables, observe memory, and examine
registers. The processor must be halted to send data and com-
mands, but once an operation has been completed by the
emulator, the DSP system is set running at full speed with no
impact on system timing.
To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website (www.analog.com)—
use site search on “EE-68.” This document is updated regularly
to keep pace with improvements to emulator support.
Evaluation Kit
Analog Devices offers a range of EZ-KIT Lite®† evaluation plat-
forms to use as a cost-effective method to learn more about
developing or prototyping applications with Analog Devices
processors, platforms, and software tools. Each EZ-KIT Lite
platform includes an evaluation board along with an evaluation
suite of the VisualDSP++ development and debugging environ-
ment with the C/C++ compiler, assembler, and linker. Also
included are sample application programs, power supply, and a
USB cable. All evaluation versions of the software tools are lim-
ited for use only with the EZ-KIT Lite product.
The USB controller on the EZ-KIT Lite board connects the
board to the USB port of the user’s PC, enabling the
VisualDSP++ evaluation suite to emulate the on-board proces-
sor in-circuit. This permits the customer to download, execute,
and debug programs for the EZ-KIT Lite system. It also allows
in-circuit programming of the on-board flash device to store
user-specific boot code, enabling the board to run as a stand-
alone unit without being connected to the PC.
†
EZ-KIT Lite is a registered trademark of Analog Devices, Inc.

PIN FUNCTION DESCRIPTIONS
The ADSP-2136x pin definitions are listed below. Inputs identi- • DAI_Px, SPICLK, MISO, MOSI, EMU, TMS, TRST, TDI,
fied as synchronous (S) must meet timing requirements with and AD15–0 (NOTE: These pins have pull-up resistors.)
respect to CLKIN (or with respect to TCK for TMS and TDI). The following symbols appear in the Type column of Table 4:
Inputs identified as asynchronous (A) can be asserted asynchro- A = asynchronous, G = ground, I = input, O = output,
nously to CLKIN (or to TCK for TRST). Tie or pull unused P = power supply, S = synchronous, (A/D) = active drive,
inputs to VDDEXT or GND, except for the following: (O/D) = open drain, and T = three-state, (pd) = pull-down resis-
tor, (pu) = pull-up resistor.
Table 4. Pin Descriptions
State During and

Pin Type After Reset Description
AD15–0 I/O/T Three-state with Parallel Port Address/Data. The ADSP-2136x parallel port and its corresponding
(pu) pull-up enabled DMA unit output addresses and data for peripherals on these multiplexed pins. The
multiplex state is determined by the ALE pin. The parallel port can operate in either
8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ internal pull-up resistor. See
Address/Data Modes on Page 15 for details of the AD pin operation.
For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper
16 external address bits, A23–8; ALE is used in conjunction with an external latch to
retain the values of the A23–8.
For detailed information on I/O operations and pin multiplexing, see the ADSP-2136x
SHARC Processor Hardware Reference.
RD O Three-state, driven Parallel Port Read Enable. RD is asserted low whenever the processor reads 8-bit or
(pu) high1 16-bit data from an external memory device. When AD15–0 are flags, this pin remains
deasserted. RD has a 22.5 kΩ internal pull-up resistor.
WR O Three-state, driven Parallel Port Write Enable. WR is asserted low whenever the processor writes 8-bit or
(pu) high1 16-bit data to an external memory device. When AD15–0 are flags, this pin remains
deasserted. WR has a 22.5 kΩ internal pull-up resistor.
ALE O Three-state, driven Parallel Port Address Latch Enable. ALE is asserted whenever the processor drives
(pd) low1 a new address on the parallel port address pins. On reset, ALE is active high. However,
it can be reconfigured using software to be active low. When AD15–0 are flags, this
pin remains deasserted. ALE has a 20 kΩ internal pull-down resistor.
FLAG3–0 I/O/A Three-state Flag Pins. Each flag pin is configured via control bits as either an input or output. As
an input, it can be tested as a condition. As an output, it can be used to signal external
peripherals. These pins can be used as an SPI interface slave select output during SPI
mastering. These pins are also multiplexed with the IRQx and the TIMEXP signals. For
detailed information on I/O operations and pin multiplexing, see the ADSP-2136x
SHARC Processor Hardware Reference.
DAI_P20–1 I/O/T Three-state with Digital Audio Interface Pins. These pins provide the physical interface to the SRU.
(pu) programmable The SRU configuration registers define the combination of on-chip peripheral inputs
pull-up or outputs connected to the pin and to the pin’s output enable. The configuration
registers of these peripherals then determines the exact behavior of the pin. Any input
or output signal present in the SRU may be routed to any of these pins. The SRU
provides the connection from the serial ports, input data port, precision clock gener-
ators and timers, sample rate converters and SPI to the DAI_P20–1 pins. These pins
have internal 22.5 kΩ pull-up resistors which are enabled on reset. These pull-ups can
be disabled in the DAI_PIN_PULLUP register.

Table 4. Pin Descriptions (Continued)
State During and

SPICLK I/O Three-state with Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls
(pu) pull-up enabled the rate at which data is transferred. The master may transmit data at a variety of baud
rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active
during data transfers, only for the length of the transferred word. Slave devices ignore
the serial clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift
out and shift in the data driven on the MISO and MOSI lines. The data is always shifted
out on one clock edge and sampled on the opposite edge of the clock. Clock polarity
and clock phase relative to data are programmable into the SPICTL control register
and define the transfer format. SPICLK has a 22.5 kΩ internal pull-up resistor.
SPIDS I Input only Serial Peripheral Interface Slave Device Select. An active low signal used to select
the processor as an SPI slave device. This input signal behaves like a chip select, and
is provided by the master device for the slave devices. In multimaster mode the
processor’s SPIDS signal can be driven by a slave device to signal to the processor (as
SPI master) that an error has occurred, as some other device is also trying to be the
master device. If asserted low when the device is in master mode, it is considered a
multimaster error. For a single-master, multiple-slave configuration where flag pins
are used, this pin must be tied or pulled high to VDDEXT on the master device. For
processor to processor SPI interaction, any of the master processor’s flag pins can be
used to drive the SPIDS signal on the SPI slave device.
MOSI I/O (O/D) Three-state with SPI Master Out Slave In. If the ADSP-2136x is configured as a master, the MOSI pin
(pu) pull-up enabled becomes a data transmit (output) pin, transmitting output data. If the processor is
configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input
data. In a SPI interconnection, the data is shifted out from the MOSI output pin of the
master and shifted into the MOSI input(s) of the slave(s). MOSI has a 22.5 kΩ internal
pull-up resistor.
MISO I/O (O/D) Three-state with SPI Master In Slave Out. If the ADSP-2136x is configured as a master, the MISO pin
(pu) pull-up enabled becomes a data receive (input) pin, receiving input data. If the processor is configured
as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output
data. In an SPI interconnection, the data is shifted out from the MISO output pin of the
slave and shifted into the MISO input pin of the master. MISO has a 22.5 kΩ internal
pull-up resistor. MISO can be configured as O/D by setting the OPD bit in the SPICTL
register.
Note: Only one slave is allowed to transmit data at any given time. To enable broadcast
transmission to multiple SPI-slaves, the processor’s MISO pin may be disabled by
setting (=1) Bit 5 (DMISO) of the SPICTL register.
BOOTCFG1–0 I Input only Boot Configuration Select. This pin is used to select the boot mode for the processor.
The BOOTCFG pins must be valid before reset is asserted. See Table 7 for a description
of the boot modes.
CLKIN I Input only Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-2136x clock input.
It configures the ADSP-2136x to use either its internal clock generator or an external
clock source. Connecting the necessary components to CLKIN and XTAL enables the
internal clock generator. Connecting the external clock to CLKIN while leaving XTAL
unconnected configures the processors to use the external clock source such as an
external clock oscillator. The core is clocked either by the PLL output or this clock input
depending on the CLKCFG1–0 pin settings. CLKIN may not be halted, changed, or
operated below the specified frequency.
XTAL O Output only2 Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external
crystal.
CLKCFG1–0 I Input only Core/CLKIN Ratio Control. These pins set the start up clock frequency. See Table 8
for a description of the clock configuration modes. Note that the operating frequency
can be changed by programming the PLL multiplier and divider in the PMCTL register
at any time after the core comes out of reset.

Table 4. Pin Descriptions (Continued)
State During and

RSTOUT/CLKOUT O Output only Local Clock Out/Reset Out. Drives out the core reset signal to an external device.
CLKOUT can also be configured as a reset out pin. The functionality can be switched
between the PLL output clock and reset out by setting Bit 12 of the PMCTREG register.
The default is reset out.
RESET I/A Input only Processor Reset. Resets the ADSP-2136x to a known state. Upon deassertion, there is
a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program
execution from the hardware reset vector address. The RESET input must be asserted
(low) at power-up.
TCK I Input only3 Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the processors.
TMS I/S Three-state with Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 kΩ
(pu) pull-up enabled internal pull-up resistor.
TDI I/S Three-state with Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
(pu) pull-up enabled 22.5 kΩ internal pull-up resistor.
TDO O Three-state4 Test Data Output (JTAG). Serial scan output of the boundary scan path.
TRST I/A Three-state with Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
(pu) pull-up enabled after power-up or held low for proper operation of the ADSP-2136x. TRST has a
22.5 kΩ internal pull-up resistor.
EMU O (O/D) Three-state with Emulation Status. Must be connected to the processor’s JTAG emulators target board
(pu) pull-up enabled connector only. EMU has a 22.5 kΩ internal pull-up resistor.
VDDINT P Core Power Supply. Nominally +1.2 V dc for the K, B grade models, and
1.0 V dc for the Y and W grade models, and supplies the processor’s core (13 pins).
VDDEXT P I/O Power Supply. Nominally +3.3 V dc (6 pins).
AVDD P Analog Power Supply. Nominally +1.2 V dc for the K, B grade models, and
1.0 V dc for the Y and W Grade models, and supplies the processor’s internal PLL (clock
generator). This pin has the same specifications as VDDINT, except that added filtering
circuitry is required. For more information, see Power Supplies on Page 9.
AVSS G Analog Power Supply Return.
GND G Power Supply Return. (54 pins)
1
RD, WR, and ALE are three-stated (and not driven) only when RESET is active.
2
Output only is a three-state driver with its output path always enabled.
3
Input only is a three-state driver with both output path and pull-up disabled.
4
Three-state is a three-state driver with pull-up disabled.

ADDRESS DATA PINS AS FLAGS BOOT MODES
To use these pins as flags (FLAGS15–0) set (=1) Bit 20 of the
Table 7. Boot Mode Selection
SYSCTL register to disable the parallel port. Then set (=1)
Bits 22 to 25 in the SYSCTL register accordingly. BOOTCFG1–0 Booting Mode
00 SPI Slave Boot
Table 5. AD15–0 to Flag Pin Mapping
01 SPI Master Boot
AD Pin Flag Pin AD Pin Flag Pin 10 Parallel Port Boot via EPROM
AD0 FLAG8 AD8 FLAG0
AD1 FLAG9 AD9 FLAG1 CORE INSTRUCTION RATE TO CLKIN RATIO MODES
AD2 FLAG10 AD10 FLAG2 For details on processor timing, see Timing Specifications and
AD3 FLAG11 AD11 FLAG3 Figure 6 on Page 18.
AD4 FLAG12 AD12 FLAG4
AD5 FLAG13 AD13 FLAG5 Table 8. Core Instruction Rate/CLKIN Ratio Selection
AD6 FLAG14 AD14 FLAG6 CLKCFG1–0 Core to CLKIN Ratio
AD7 FLAG15 AD15 FLAG7 00 6:1
01 32:1
ADDRESS/DATA MODES 10 16:1
The following table shows the functionality of the AD pins for
8-bit and 16-bit transfers to the parallel port. For 8-bit data
transfers, ALE latches Address Bits A23–A8 when asserted, fol-
lowed by Address Bits A7–A0 and Data Bits D7–D0 when
deasserted. For 16-bit data transfers, ALE latches Address Bits
A15–A0 when asserted, followed by Data Bits D15–D0 when
deasserted.
Table 6. Address/Data Mode Selection
PP Data AD7–AD0 AD15–AD8

Mode ALE Function Function
8-bit Asserted A15–A8 A23–A16
8-bit Deasserted D7–D0 A7–A0
16-bit Asserted A7–A0 A15–A8
16-bit Deasserted D7–D0 D15–D8

ADSP-2136x SPECIFICATIONS
OPERATING CONDITIONS
K Grade B Grade
Parameter1 Description Min Max Min Max Unit
VDDINT Internal (Core) Supply Voltage 1.14 1.26 1.14 1.26 V

AVDD Analog (PLL) Supply Voltage 1.14 1.26 1.14 1.26 V
VDDEXT External (I/O) Supply Voltage 3.13 3.47 3.13 3.47 V
2
VIH High Level Input Voltage @ VDDEXT = max 2.0 VDDEXT + 0.5 2.0 VDDEXT + 0.5 V
VIL2 Low Level Input Voltage @ VDDEXT = min –0.5 +0.8 –0.5 +0.8 V
VIH_CLKIN3 High Level Input Voltage @ VDDEXT = max 1.74 VDDEXT + 0.5 1.74 VDDEXT + 0.5 V
VIL_CLKIN Low Level Input Voltage @ VDDEXT = min –0.5 +1.19 –0.5 +1.19 V
TAMB 4, 5
Ambient Operating Temperature 0 +70 –40 +85 °C
1
Specifications subject to change without notice.
2
Applies to input and bidirectional pins: AD15–0, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKCFGx, RESET, TCK, TMS, TDI, TRST.
3
Applies to input pin CLKIN.
4
See Thermal Characteristics on Page 47 for information on thermal specifications.
5
See Engineer-to-Engineer Note (No. EE-277) for further information.
ELECTRICAL CHARACTERISTICS
Parameter1 Description Test Conditions Min Max Unit
VOH2 High Level Output Voltage @ VDDEXT = min, IOH = –1.0 mA3 2.4 V
2 3
VOL Low Level Output Voltage @ VDDEXT = min, IOL = 1.0 mA 0.4 V
4, 5
IIH High Level Input Current @ VDDEXT = max, VIN = VDDEXT max 10 μA
IIL4 Low Level Input Current @ VDDEXT = max, VIN = 0 V 10 μA
5
IILPU Low Level Input Current Pull-Up @ VDDEXT = max, VIN = 0 V 200 μA
6, 7
IOZH Three-State Leakage Current @ VDDEXT= max, VIN = VDDEXT max 10 μA
6
IOZL Three-State Leakage Current @ VDDEXT = max, VIN = 0 V 10 μA
IOZLPU7 Three-State Leakage Current Pull-Up @ VDDEXT = max, VIN = 0 V 200 μA
8, 9
IDD-INTYP Supply Current (Internal) tCCLK = min, VDDINT = nom 800 mA
10
AIDD Supply Current (Analog) AVDD = max 10 mA
11, 12
CIN Input Capacitance fIN = 1 MHz, TCASE = 25°C, VIN = 1.2 V 4.7 pF
1
Specifications subject to change without notice.
2
Applies to output and bidirectional pins: AD15–0, RD, WR, ALE, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL.
3
See Output Drive Currents on Page 46 for typical drive current capabilities.
4
Applies to input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN.
5
Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI.
6
Applies to three-stateable pins: FLAG3–0.
7
Applies to three-stateable pins with 22.5 kΩ pull-ups: AD15–0, DAI_Px, SPICLK, EMU, MISO, MOSI.
8
Typical internal current data reflects nominal operating conditions.
9
See Engineer-to-Engineer Note (No. EE-277) for further information.
10
Characterized, but not tested.
11
Applies to all signal pins.
12
Guaranteed, but not tested.

PACKAGE INFORMATION MAXIMUM POWER DISSIPATION
The information presented in Figure 5 provides details about See Engineer-to-Engineer Note (EE-277) for detailed thermal
the package branding for the ADSP-2136x processor. For a and power information regarding maximum power dissipation.
complete listing of product availability, see Ordering Guide on For information on package thermal specifications, see Thermal
Page 52. Characteristics on Page 47.
ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed below may cause permanent
a damage to the device. These are stress ratings only; functional
ADSP-2136x operation of the device at these or any other conditions greater
tppZ-cc than those indicated in the operational sections of this specifica-
vvvvvv.x n.n
tion is not implied. Exposure to absolute maximum rating
yyww country_of_origin
conditions for extended periods may affect device reliability.
S
Parameter Rating
Internal (Core) Supply Voltage (VDDINT) –0.3 V to +1.5 V
Figure 5. Typical Package Brand Analog (PLL) Supply Voltage (AVDD) –0.3 V to +1.5 V
Table 9. Package Brand Information External (I/O) Supply Voltage (VDDEXT) –0.3 V to +4.6 V
Input Voltage –0.5 V to +3.8 V
Brand Key Field Description Output Voltage Swing –0.5 V to VDDEXT + 0.5 V
t Temperature Range Load Capacitance 200 pF
pp Package Type Storage Temperature Range –65°C to +150°C
Z Lead Free Option Junction Temperature Under Bias 125°C
cc See Ordering Guide
vvvvvv.x Assembly Lot Code
n.n Silicon Revision
yyww Date Code
ESD SENSITIVITY
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-2136x features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

TIMING SPECIFICATIONS
The ADSP-2136x’s internal clock (a multiple of CLKIN) pro- Table 11. Clock Periods
vides the clock signal for timing internal memory, processor
core, serial ports, and parallel port (as required for read/write Timing
strobes in asynchronous access mode). During reset, program Requirements Description1
the ratio between the processor’s internal clock frequency and tCK CLKIN Clock Period
external (CLKIN) clock frequency with the CLKCFG1–0 pins tCCLK (Processor) Core Clock Period
(see Table 8 on Page 15). To determine switching frequencies tPCLK (Peripheral) Clock Period = 2 × tCCLK
for the serial ports, divide down the internal clock, using the
tSCLK Serial Port Clock Period = (tPCLK) × SR
programmable divider control of each port (DIVx for the
serial ports). tSPICLK SPI Clock Period = (tPCLK) × SPIR
1
The ADSP-2136x’s internal clock switches at higher frequencies where:
SR = serial port-to-peripheral clock ratio (wide range, determined by SPORT
than the system input clock (CLKIN). To generate the internal CLKDIV)
clock, the processor uses an internal phase-locked loop (PLL). SPIR = SPI-to-peripheral clock ratio (wide range, determined by SPIBAUD
This PLL-based clocking minimizes the skew between the sys- register)
DAI_Px = serial port clock
tem clock (CLKIN) signal and the processor’s internal clock (the SPICLK = SPI clock
clock source for the parallel port logic and I/O pads).
Note the definitions of various clock periods that are a function Figure 6 shows core to CLKIN ratios of 6:1, 16:1, and 32:1 with
of CLKIN and the appropriate ratio control shown in Table 10 external oscillator or crystal. Note that more ratios are possible
and Table 11. and can be set through software using the power management
control register (PMCTL). For more information, see the
Table 10. ADSP-2136x Clock Generation Operation ADSP-2136x SHARC Processor Programming Reference.
Timing Use the exact timing information given. Do not attempt to
Requirements Description Calculation derive parameters from the addition or subtraction of others.
CLKIN Input Clock 1/tCK While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
CCLK Core Clock 1/tCCLK
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 39 on Page 46 under Test Conditions for voltage
reference levels.
CCLK
(CORE CLOCK)
CLKIN
XTAL INDIV DIVEN
PLLM
XTAL OSC ÷1, 2 ÷2, 4, 8, 16
PLLICLK
PCLK
÷2
(PERIPHERAL CLOCK)
CLK_CFG [1:0]
(6:1, 16:1, 32:1)
CLKOUT
OR
RESET RESETOUT
DELAY
Figure 6. Core Clock and System Clock Relationship to CLKIN
Timing Requirements apply to signals that are controlled by cir- circumstance. Use switching characteristics to ensure that any
cuitry external to the processor, such as the data input for a read timing requirement of a device connected to the processor (such
operation. Timing requirements guarantee that the processor as memory) is satisfied.
operates correctly with other devices.
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given

Power-Up Sequencing
The timing requirements for processor startup are given in
Table 12.
Table 12. Power-Up Sequencing Timing Requirements (Processor Startup)
Parameter Min Max Unit

Timing Requirements
tRSTVDD RESET Low Before VDDINT/VDDEXT On 0 ns
tIVDDEVDD VDDINT On Before VDDEXT –50 +200 ms
tCLKVDD1 CLKIN Valid After VDDINT/VDDEXT Valid 0 +200 ms
tCLKRST CLKIN Valid Before RESET Deasserted 102 μs
tPLLRST PLL Control Setup Before RESET Deasserted 20 μs
Switching Characteristic
tCORERST Core Reset Deasserted After RESET Deasserted 4096tCK + 2 tCCLK 3, 4
1
Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.2 volt rails and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of
milliseconds depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time.
Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3
Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
4
The 4096 cycle count depends on tSRST specification in Table 14. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097
cycles maximum.
RESET
tRSTVDD
VDDINT
tIVDDEVDD
VDDEXT tCLKVDD
CLKIN
tCLKRST
CLK_CFG1-0
tCORERST
tPLLRST
RSTOUT
Figure 7. Power-Up Sequencing

Clock Input
Table 13. Clock Input
333 MHz
Timing Requirements
tCK CLKIN Period 181 100 ns
tCKL CLKIN Width Low 7.51 ns
tCKH CLKIN Width High 7.51 ns
tCKRF CLKIN Rise/Fall (0.4 V to 2.0 V) 3 ns
tCCLK2 CCLK Period 3.01 10 ns
tCKJ3,4 CLKIN Jitter Tolerance –250 +250 ps
1
Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.
2
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK.
3
Actual input jitter should be combined with ac specifications for accurate timing analysis.
4
Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
tC K J
tC K
C LK IN
tC K H tC K L
Figure 8. Clock Input
Clock Signals
The ADSP-2136x can use an external clock or a crystal. See the
CLKIN pin description in Table 4 on Page 12. The user applica- ADSP-2136X
tion program can configure theADSP-2136x to use its internal

clock generator by connecting the necessary components to the CLKIN R1
1M⍀*
XTAL
CLKIN and XTAL pins. Figure 9 shows the component connec-

R2
tions used for a fundamental frequency crystal operating in 47⍀*
parallel mode. C1 C2
22pF Y1 22pF
Note that the clock rate is achieved using a 16.67 MHz crystal
and a PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock 24.576MHz
speed of 266.72 MHz). To achieve the full core clock rate, pro-
grams need to configure the multiplier bits in the
PMCTL register. R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’S SPECIFICATIONS
*TYPICAL VALUES
Figure 9. 333 MHz Operation (Fundamental Mode Crystal)

Reset
Table 14. Reset

Timing Requirements
tWRST1 RESET Pulse Width Low 4tCK ns
tSRST RESET Setup Before CLKIN Low 8 ns
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable
VDD and CLKIN (not including start-up time of external clock oscillator).
CLKIN
tWRST tSRST
RESET
Figure 10. Reset
Interrupts
The following timing specification applies to the FLAG0,
FLAG1, and FLAG2 pins when they are configured as IRQ0,
IRQ1, and IRQ2 interrupts.
Table 15. Interrupts

Timing Requirement
tIPW IRQx Pulse Width 2 × tPCLK +2 ns
DAI20-1
FLAG2-0
(IRQ2-0)
tIPW
Figure 11. Interrupts

Core Timer
The following timing specification applies to FLAG3 when it is
configured as the core timer (CTIMER).
Table 16. Core Timer

tWCTIM CTIMER Pulse Width 2 × tPCLK – 1 ns
FLAG3 tWCTIM
(CTIMER)
Figure 12. Core Timer
Timer PWM_OUT Cycle Timing

The following timing specification applies to Timer0, Timer1,
and Timer2 in PWM_OUT (pulse-width modulation) mode.
Timer signals are routed to the DAI_P20–1 pins through the
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20–1 pins.
Table 17. Timer PWM_OUT Timing

tPWMO Timer Pulse Width Output 2 tPCLK – 1 2(231 – 1) tPCLK ns
tPWM O
DAI_P20 -1
(TIMER2-0)
Figure 13. Timer PWM_OUT Timing

Timer WDTH_CAP Timing
The following timing specification applies to Timer0, Timer1,
and Timer2 in WDTH_CAP (pulse width count and capture)
mode. Timer signals are routed to the DAI_P20–1 pins through
the SRU. Therefore, the timing specification provided below are
valid at the DAI_P20–1 pins.
Table 18. Timer Width Capture Timing

Timing Requirement
tPWI Timer Pulse Width 2 tPCLK 2(231– 1) tPCLK ns
tPWI
DAI_P20-1
(TIMER2-0)
Figure 14. Timer Width Capture Timing
DAI Pin to Pin Direct Routing

For direct pin connections only (for example, DAI_PB01_I to
DAI_PB02_O).
Table 19. DAI Pin to Pin Routing

Timing Requirement
tDPIO Delay DAI Pin Input Valid to DAI Output Valid 1.5 10 ns
DAI_Pn
DAI_Pm
tDPIO
Figure 15. DAI Pin to Pin Direct Routing

Precision Clock Generator (Direct Pin Routing) inputs and outputs are not directly routed to/from DAI pins (via
pin buffers) there is no timing data available. All timing param-
This timing is only valid when the SRU is configured such that
eters and switching characteristics apply to external DAI pins
the precision clock generator (PCG) takes its inputs directly
(DAI_P01 – DAI_P20).
from the DAI pins (via pin buffers) and sends its outputs
directly to the DAI pins. For the other cases, where the PCG’s
Table 20. Precision Clock Generator (Direct Pin Routing)

Timing Requirements
tPCGIP Input Clock Period 20 ns
tSTRIG PCG Trigger Setup Before Falling 4.5 ns
Edge of PCG Input Clock
tHTRIG PCG Trigger Hold After Falling 3 ns
Edge of PCG Input Clock
Switching Characteristics
tDPCGIO PCG Output Clock and Frame Sync Active Edge
Delay After PCG Input Clock 2.5 10 ns
tDTRIGCLK PCG Output Clock Delay After PCG Trigger 2.5 + ((2.5 + D) × tPCGIP) 10 + ((2.5 + D) × tPCGIP) ns
tDTRIGFS PCG Frame Sync Delay After PCG Trigger 2.5 + ((2.5 + D – PH) × tPCGIP) 10 + ((2.5 + D – PH) × tPCGIP) ns
tPCGOP Output Clock Period 2 × tPCGIP1 ns
D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-2136x SHARC Processor Hardware Reference, “Precision Clock Generators”
chapter.
1
In normal mode, tPCGOP (min) = 2 × tPCGIP.
tSTRIG tHTRIG
DAI_Pn
PCG_TRIGx_I
tPCGIP
DAI_Pm
PCG_EXTx_I
(CLKIN)
tDPCGIO
DAI_Py
PCG_CLKx_O tDTRIGCLK tDPCGIO tPCGOP
DAI_Pz
PCG_FSx_O
tDTRIGFS
Figure 16. Precision Clock Generator (Direct Pin Routing)

Flags
The timing specifications provided below apply to the FLAG3–0
and DAI_P20–1 pins, the parallel port, and the serial peripheral
interface (SPI). See Table 4, “Pin Descriptions,” on Page 12 for
more information on flag use.
Table 21. Flags

Timing Requirement
tFIPW FLAG3–0 IN Pulse Width 2 × tPCLK + 3 ns
tFOPW FLAG3–0 OUT Pulse Width 2 × tPCLK – 1 ns
DAI_P20-1
(FLAG3-0IN)
(DATA31-0)
tFIPW
DAI_P20-1
(FLAG3-0OUT)
(DATA31-0)
tFOPW
Figure 17. Flags

Memory Read—Parallel Port
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) when the ADSP-2136x
is accessing external memory space.
Table 22. 8-Bit Memory Read Cycle

Timing Requirements
tDRS1 AD7–0 Data Setup Before RD High 3.3 ns
tDRH AD7–0 Data Hold After RD High 0 ns
tDAD1 AD15–8 Address to AD7–0 Data Valid D + tPCLK – 5.0 ns
tALEW ALE Pulse Width 2 × tPCLK – 2.0 ns
tADAS2 AD15–0 Address Setup Before ALE Deasserted tPCLK – 2.5 ns
tRRH Delay Between RD Rising Edge to Next H + tPCLK – 1.4 ns
Falling Edge
tALERW ALE Deasserted to Read Asserted 2 × tPCLK – 3.8 ns
tRWALE Read Deasserted to ALE Asserted F + H + 0.5 ns
tADAH2 AD15–0 Address Hold After ALE Deasserted tPCLK – 2.3 ns
tALEHZ2 ALE Deasserted to AD7–0 Address in High Z tPCLK tPCLK + 3.0 ns
tRW RD Pulse Width D – 2.0 ns
tRDDRV AD7–0 ALE Address Drive After Read High F + H + tPCLK – 2.3 ns
tADRH AD15–8 Address Hold After RD High H ns
tDAWH AD15–8 Address to RD High D + tPCLK – 4.0 ns
D = (data cycle duration = the value set by the PPDUR Bits (5–1) in the PPCTL register) × tPCLK
H = tPCLK (if a hold cycle is specified, else H = 0)
F = 7 × tPCLK (if FLASH_MODE is set, else F = 0)
tPCLK = (peripheral) clock period = 2 × tCCLK
1
The timing specified here is sufficient to satisfy either tDAD or tDRS as they are independent.
2
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

tRWALE
tALERW
ALE tALEW
tRRH
RD
tRW
tRDDRV
WR
tDAWH
tADRH
tADAS tADAH
AD15-8 VALID
VALID ADDRESS VALID ADDRESS VALID ADDRESS
ADDRESS
tDAD tDRS tDRH
VALID VALID VALID

AD7-0 VALID ADDRESS DATA ADDRESS
DATA
tALEHZ
NOTE: MEMORY READS ALWAYS OCCUR IN GROUPS OF FOUR

BETWEEN ALE CYCLES. THIS FIGURE ONLY SHOWS TWO MEMORY
READS IN ORDER TO PROVIDE THE NECESSARY TIMING INFORMATION.
Figure 18. Read Cycle for 8-Bit Memory Timing

Table 23. 16-Bit Memory Read Cycle

Timing Requirements
tDRS AD15–0 Data Setup Before RD High 3.3 ns
tDRH AD15–0 Data Hold After RD High 0 ns
tALERW ALE Deasserted to Read Asserted 2 × tPCLK – 3.8 ns
tRRH2 Delay Between RD Rising Edge to Next Falling Edge H + tPCLK – 1.4 ns
tRWALE Read Deasserted to ALE Asserted F + H + 0.5 ns
tRDDRV ALE Address Drive After Read High F + H + tPCLK – 2.3 ns
tALEHZ1 ALE Deasserted to Address/Data15–0 in High Z tPCLK tPCLK + 3.0 ns
tRW RD Pulse Width D – 2.0 ns
D = (data cycle duration = the value set by the PPDUR Bits (5–1) in the PPCTL register) × tPCLK
F = 7 × tPCLK (if FLASH_MODE is set, else F = 0)
1
2
This parameter is only available when in EMPP = 0 mode.
tRWALE
tALERW
ALE tALEW
tRRH
RD
tRW
WR tRDDRV
tALEHZ
tDRS tDRH
tADAS tADAH
VALID
AD15-0 VALID ADDRESS VALID DATA VALID DATA
ADDRESS
NOTE: FOR 16-BIT MEMORY READS, WHEN EMPP ⫽ 0, ONLY ONE RD PULSE OCCURS BETWEEN ALE CYCLES.
WHEN EMPP = 0, MULTIPLE RD PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION,
SEE THE ADSP-2136X SHARC PROCESSOR HARDWARE REFERENCE.
Figure 19. Read Cycle for 16-Bit Memory Timing

Memory Write—Parallel Port
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) when the
ADSP-2136x is accessing external memory space.
Table 24. 8-Bit Memory Write Cycle

tALERW ALE Deasserted to Write Asserted 2 × tPCLK – 3.8 ns
tRWALE Write Deasserted to ALE Asserted H + 0.5 ns
tWRH Delay Between WR Rising Edge to Next WR Falling Edge F + H + tPCLK – 2.3 ns
tWW WR Pulse Width D – F – 2.0 ns
tADWL AD15–8 Address to WR Low tPCLK – 2.8 ns
tADWH AD15–8 Address Hold After WR High H ns
tDWS AD7–0 Data Setup Before WR High D – F + tPCLK – 4.0 ns
tDWH AD7–0 Data Hold After WR High H ns
tDAWH AD15–8 Address to WR High D – F + tPCLK – 4.0 ns
D = (data cycle duration = the value set by the PPDUR Bits (5–1) in the PPCTL register) × tPCLK.
F = 7 × tPCLK (if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be ≥ 9 × tPCLK.
1
tALERW
tALEW
ALE
tRWALE
tWW
WR
tADWL tWRH
tDAWH
RD
tADAS tADAH
tADWH
AD15-8 VALID
ADDRESS VALID ADDRESS VALID ADDRESS
tDWH
tDWS
VALID
VALID DATA VALID DATA
AD7-0 ADDRESS
NOTE: MEMORY WRITES ALWAYS OCCUR IN GROUPS OF FOUR

BETWEEN ALE CYCLES. THIS FIGURE ONLY SHOWS TWO MEMORY
WRITES IN ORDER TO PROVIDE THE NECESSARY TIMING INFORMATION.
Figure 20. Write Cycle for 8-Bit Memory Timing

Table 25. 16-Bit Memory Write Cycle

tALERW ALE Deasserted to Write Asserted 2 × tPCLK – 3.8 ns
tRWALE Write Deasserted to ALE Asserted H + 0.5 ns
tWRH2 Delay Between WR Rising Edge to Next WR Falling Edge F + H + tPCLK – 2.3 ns
tWW WR Pulse Width D – F – 2.0 ns
tDWS AD15–0 Data Setup Before WR High D – F + tPCLK – 4.0 ns
tDWH AD15–0 Data Hold After WR High H ns
D = (data cycle duration = the value set by the PPDUR Bits (5–1) in the PPCTL register) × tPCLK.
F = 7 × tPCLK (if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be ≥ 9 × tPCLK.
1
2
This parameter is only available when in EMPP = 0 mode.
tALEW tALERW
ALE
tRWALE
tWW
WR
tWRH
RD
tADAS tADAH tDWH
AD15-0 VALID VALID

ADDRESS VALID DATA VALID DATA ADDRESS
tDWS
NOTE: FOR 16-BIT MEMORY WRITES, WHEN EMPP ⫽ 0, ONLY ONE WR PULSE OCCURS BETWEEN ALE CYCLES.
WHEN EMPP = 0, MULTIPLE WR PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION,
SEE THE ADSP-2136X SHARC PROCESSOR HARDWARE REFERENCE.
Figure 21. Write Cycle for 16-Bit Memory Timing

Serial Ports
To determine whether communication is possible between two Serial port signals (SCLK, FS, data channel A, data channel B)
devices at clock speed n, the following specifications must be are routed to the DAI_P20–1 pins using the SRU. Therefore, the
confirmed: 1) frame sync delay and frame sync setup and hold, timing specifications provided below are valid at the
2) data delay and data setup and hold, and 3) SCLK width. DAI_P20–1 pins.
Table 26. Serial Ports—External Clock

Timing Requirements
tSFSE1 FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode) 2.5 ns
tHFSE1 FS Hold After SCLK
1
tSDRE Receive Data Setup Before Receive SCLK 2.5 ns
tHDRE1 Receive Data Hold After SCLK 2.5 ns
tSCLKW SCLK Width 12 ns
tSCLK SCLK Period 24 ns
tDFSE2 FS Delay After SCLK
(Internally Generated FS in Either Transmit or Receive Mode) 9.5 ns
tHOFSE2 FS Hold After SCLK
(Internally Generated FS in Either Transmit or Receive Mode) 2 ns
tDDTE2 Transmit Data Delay After Transmit SCLK 9.5 ns
tHDTE2 Transmit Data Hold After Transmit SCLK 2 ns
1
Referenced to sample edge.
2
Referenced to drive edge.
Table 27. Serial Ports—Internal Clock

Timing Requirements
tSFSI1 FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode) 7 ns
tHFSI1 FS Hold After SCLK
1
tSDRI Receive Data Setup Before SCLK 7 ns
tHDRI1 Receive Data Hold After SCLK 2.5 ns
tDFSI2 FS Delay After SCLK (Internally Generated FS in Transmit Mode) 3 ns
tHOFSI2 FS Hold After SCLK (Internally Generated FS in Transmit Mode) –1.0 ns
2
tDFSIR FS Delay After SCLK (Internally Generated FS in Receive Mode) 8 ns
tHOFSIR2 FS Hold After SCLK (Internally Generated FS in Receive Mode) –1.0 ns
tDDTI2 Transmit Data Delay After SCLK 3 ns
2
tHDTI Transmit Data Hold After SCLK –1.0 ns
tSCLKIW Transmit or Receive SCLK Width 0.5tSCLK – 2 0.5tSCLK + 2 ns
1
Referenced to the sample edge.
2

Table 28. Serial Ports—Enable and Three-State

tDDTEN1 Data Enable from External Transmit SCLK 2 ns
tDDTTE1 Data Disable from External Transmit SCLK 7 ns
tDDTIN1 Data Enable from Internal Transmit SCLK –1 ns
1
Table 29. Serial Ports—External Late Frame Sync

tDDTLFSE1 Data Delay from Late External Transmit FS or External Receive
FS with MCE = 1, MFD = 0 9 ns
tDDTENFS1 Data Enable for MCE = 1, MFD = 0 0.5 ns
1
The tDDTLFSE and tDDTENFS parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
DAI_P20-1 DRIVE SAMPLE DRIVE

(SCLK)
tSFSE/I tHFSE/I
DAI_P20-1
(FS)
tDDTENFS tDDTE/I
DAI_P20-1
tHDTE/I
(DATA CHANNEL A/B)
1ST BIT 2ND BIT
tDDTLFSE
LATE EXTERNAL TRANSMIT FS
DRIVE SAMPLE DRIVE

DAI_P20-1
(SCLK)
tSFSE/I tHFSE/I
DAI_P20-1
(FS)
tDDTE/I
tDDTENFS
tHDTE/I
DAI_P20-1
(DATA CHANNEL A/B)
1ST BIT 2ND BIT
tDDTLFSE
NOTE: SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20-1 PINS
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20-1 PINS.
Figure 22. External Late Frame Sync1

1
This figure reflects changes made to support left-justified sample pair mode.

DATA RECEIVE—INTERNAL CLOCK DATA RECEIVE—EXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE

tSCLKIW tSCLKW
DAI_P20-1 DAI_P20-1
(SCLK) (SCLK)
tDFSIR tDFSE
tSFSI tHFSI tHFSE
tHOFSR tHOFSE tSFSE
DAI_P20-1 DAI_P20-1
(FS) (FS)
tSDRI tHDRI tSDRE tHDRE

DAI_P20-1 DAI_P20-1
(DATA CHANNEL A/B) (DATA CHANNEL A/B)
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT—INTERNAL CLOCK DATA TRANSMIT—EXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE
tSCLKIW tSCLKW
DAI_P20-1 DAI_P20-1
(SCLK) (SCLK)
tDFSI tDFSE
tHOFSI tSFSI tHFSI tHOFSE tSFSE tHFSE
DAI_P20-1 DAI_P20-1
(FS) (FS)
tDDTI tDDTE
tHDTI tHDTE
DAI_P20-1 DAI_P20-1
(DATA CHANNEL A/B) (DATA CHANNEL A/B)
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE EDGE DRIVE EDGE
DAI_P20-1 SCLK
SCLK (EXT)
tDDTEN tDDTTE
DAI_P20-1
(DATA CHANNEL A/B)
DRIVE EDGE
DAI_P20-1
SCLK (INT)
tDDTIN
DAI_P20-1
(DATA CHANNEL A/B)
Figure 23. Serial Ports

Input Data Port (IDP)
The timing requirements for the IDP are given in Table 30. IDP
signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided
below are valid at the DAI_P20–1 pins.
Table 30. IDP

Timing Requirements
tSISFS1 FS Setup Before SCLK Rising Edge 3 ns
1
tSIHFS FS Hold After SCLK Rising Edge 3 ns
tSISD1 SDATA Setup Before SCLK Rising Edge 3 ns
tSIHD1 SDATA Hold After SCLK Rising Edge 3 ns
tIDPCLKW Clock Width 9 ns
tIDPCLK Clock Period 24 ns
1
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
SAMPLE EDGE
tIDPCLK
DAI_P20-1 tIDPCLKW
(SCLK)
tSISFS tSIHFS
DAI_P20-1
(FS)
tSISD tSIHD
DAI_P20-1
(SDATA)
Figure 24. IDP Master Timing

Parallel Data Acquisition Port (PDAP) Hardware Reference. Note that the most significant 16 bits of
external PDAP data can be provided through either the parallel
The timing requirements for the PDAP are provided in
port AD15–0 or the DAI_P20–5 pins. The remaining 4 bits can
Table 31. PDAP is the parallel mode operation of Channel 0 of
only be sourced through DAI_P4–1. The timing below is valid
the IDP. For details on the operation of the IDP, see the IDP
at the DAI_P20–1 pins or at the AD15–0 pins.
chapter of the ADSP-2136x SHARC Processor
Table 31. Parallel Data Acquisition Port (PDAP)

Timing Requirements
tSPCLKEN1 PDAP_CLKEN Setup Before PDAP_CLK Sample Edge 2.5 ns
1
tHPCLKEN PDAP_CLKEN Hold After PDAP_CLK Sample Edge 2.5 ns
tPDSD1 PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge 3.0 ns
tPDHD1 PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge 2.5 ns
tPDCLKW Clock Width 7.0 ns
tPDCLK Clock Period 24 ns
tPDHLDD Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word 2 × tPCLK – 1 ns
tPDSTRB PDAP Strobe Pulse Width 2 × tPCLK – 1.5 ns
1
Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.
SAMPLE EDGE
t PDCLK
t PDCLKW
DAI_P20 -1
(PDAP_CLK)
t SPCLKEN
t HPCLKEN
DAI_P20 -1
(PDAP_CLKEN)
t PDSD t PDHD
DATA
DAI_P20-1
(PDAP_STROBE) tPDSTRB
t PDHLDD
Figure 25. PDAP Timing

Pulse-Width Modulation Generators
Table 32. PWM Timing

tPWMW PWM Output Pulse Width tPCLK – 2 (216 – 2) × tPCLK – 2 ns
tPWMP PWM Output Period 2 × tPCLK – 1.5 (216 – 1) × tPCLK ns
tPWMW
PWM
OUTPUTS
tPWMP
Figure 26. PWM Timing
Sample Rate Converter—Serial Input Port

The SRC input signals (SCLK, FS, and SDATA) are routed from
the DAI_P20–1 pins using the SRU. Therefore, the timing spec-
ifications provided in Table 33 are valid at the DAI_P20–1 pins.
This feature is not available on the ADSP-21363 models.
Table 33. SRC, Serial Input Port

Timing Requirements
tSRCSFS1 FS Setup Before SCLK Rising Edge 3 ns
tSRCHFS1 FS Hold After SCLK Rising Edge 3 ns
1
tSRCSD SDATA Setup Before SCLK Rising Edge 3 ns
tSRCHD1 SDATA Hold After SCLK Rising Edge 3 ns
tSRCCLKW Clock Width 36 ns
tSRCCLK Clock Period 80 ns
1
SAMPLE EDGE
tSRCCLK
DAI_P20-1 tSRCCLKW
(SCLK)
tSRCSFS tSRCHFS
DAI_P20-1
(FS)
tSRCSD tSRCHD
DAI_P20-1
(SDATA)
Figure 27. SRC Serial Input Port Timing

Sample Rate Converter—Serial Output Port
For the serial output port, the frame-sync is an input and should
meet setup and hold times with regard to SCLK on the output
port. The serial data output, SDATA, has a hold time and delay
specification with regard to SCLK. Note that SCLK rising edge is
the sampling edge and the falling edge is the drive edge.
Table 34. SRC, Serial Output Port

Timing Requirements
tSRCSFS1 FS Setup Before SCLK Rising Edge 3 ns
tSRCHFS1 FS Hold After SCLK Rising Edge 3 ns
tSRCTDD1 Transmit Data Delay After SCLK Falling Edge 10.5 ns
tSRCTDH1 Transmit Data Hold After SCLK Falling Edge 2 ns
1
SAMPLE EDGE
tSRCCLK
DAI_P20-1 tSRCCLKW
(SCLK)
tSRCSFS tSRCHFS
DAI_P20-1
(FS)
tSRCTDD
DAI_P20-1
(SDATA)
tSRCTDH
Figure 28. SRC Serial Output Port Timing

SPDIF Transmitter SPDIF Transmitter—Serial Input Waveforms
Serial data input to the SPDIF transmitter can be formatted as Figure 29 shows the right-justified mode. LRCLK is HI for the
left-justified, I2S, or right-justified with word widths of 16, 18, left channel and LO for the right channel. Data is valid on the
20, or 24 bits. The following sections provide timing for the rising edge of SCLK. The MSB is delayed 12-bit clock periods
transmitter. This feature is not available on the (in 20-bit output mode) or 16-bit clock periods (in 16-bit output
ADSP-21363 models. mode) from an LRCLK transition, so that when there are
64 SCLK periods per LRCLK period, the LSB of the data will be
right-justified to the next LRCLK transition.
LRCLK LEFT CHANNEL RIGHT CHANNEL
SCLK
SDATA LSB MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB
Figure 29. Right -Justified Mode
Figure 30 shows the default I2S-justified mode. LRCLK is LO for

the left channel and HI for the right channel. Data is valid on the
rising edge of SCLK. The MSB is left-justified to an LRCLK
transition but with a single SCLK period delay.
RIGHT CHANNEL
LRCLK LEFT CHANNEL
SCLK
SDATA MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB
Figure 30. I2S-Justified Mode
Figure 31 shows the left-justified mode. LRCLK is HI for the left

channel and LO for the right channel. Data is valid on the rising
edge of SCLK. The MSB is left-justified to an LRCLK transition
with no MSB delay.
LRCLK LEFT CHANNEL RIGHT CHANNEL
SCLK
SDATA MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB+1
Figure 31. Left-Justified Mode

SPDIF Transmitter Input Data Timing
The timing requirements for the input port are given in
Table 35. Input signals (SCLK, FS, and SDATA) are routed to
the DAI_P20–1 pins using the SRU. Therefore, the timing spec-
ifications provided below are valid at the DAI_P20–1 pins.
Table 35. SPDIF Transmitter Input Data Timing

Timing Requirements
tSISFS1 FS Setup Before SCLK Rising Edge 3 ns
tSIHFS1 FS Hold After SCLK Rising Edge 3 ns
tSISD1 SDATA Setup Before SCLK Rising Edge 3 ns
tSIHD1 SDATA Hold After SCLK Rising Edge 3 ns
tSISCLKW Clock Width 36 ns
tSISCLK Clock Period 80 ns
tSITXCLKW Transmit Clock Width 9 ns
tSITXCLK Transmit Clock Period 20 ns
1
tSITXCLKW
SAMPLE EDGE tSITXCLK
DAI_P20-1
(TXCLK)
tSISCLKW
DAI_P20-1
(SCLK)
tSISFS tSIHFS
DAI_P20-1
(FS)
tSISD tSIHD
DAI_P20-1
(SDATA)
Figure 32. SPDIF Transmitter Input Timing
Oversampling Clock (TXCLK) Switching Characteristics

SPDIF Transmitter has an over sampling clock. This TXCLK
input is divided down to generate the biphase clock.
Table 36. Oversampling Clock (TXCLK) Switching Characteristics

TXCLK Frequency for TXCLK = 768 × FS 147.5 MHz
Frame Rate 192.0 kHz

SPDIF Receiver
The following section describes timing as it relates to the SPDIF
receiver. This feature is not available on the
ADSP-21363 models.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the 512 × FS clock.
Table 37. SPDIF Receiver Output Timing (Internal Digital PLL Mode)

tDFSI LRCLK Delay After SCLK 5 ns
tHOFSI LRCLK Hold After SCLK –2 ns
tDDTI Transmit Data Delay After SCLK 5 ns
tHDTI Transmit Data Hold After SCLK –2 ns
tSCLKIW1 Transmit SCLK Width 38 ns
tCCLK Core Clock Period 5 ns
1
SCLK frequency is 64 × FS where FS = the frequency of LRCLK.
DRIVE EDGE SAMPLE EDGE

tSCLKIW
DAI_P20-1
(SCLK)
tDFSI
tHOFSI
DAI_P20-1
(FS)
tDDTI
tHDTI
DAI_P20-1
(DATA CHANNEL A/B)
Figure 33. SPDIF Receiver Internal Digital PLL Mode Timing

SPI Interface—Master
The ADSP-2136x contains two SPI ports. The primary has dedi-
cated pins and the secondary is available through the DAI. The
timing provided in Table 38 and Table 39 applies to both.
Table 38. SPI Interface Protocol—Master Switching and Timing Specifications

Timing Requirements
tSSPIDM Data Input Valid to SPICLK Edge (Data Input Setup Time) 5.2 ns
tSSPIDM Data Input Valid to SPICLK Edge (Data Input Setup Time) 8.2 ns
(SPI2)
tHSPIDM SPICLK Last Sampling Edge to Data 2 ns
Input Not Valid
tSPICLKM Serial Clock Cycle 8 × tPCLK – 2 ns
tSPICHM Serial Clock High Period 4 × tPCLK – 2 ns
tSPICLM Serial Clock Low Period 4 × tPCLK – 2 ns
tDDSPIDM SPICLK Edge to Data Out Valid 3.0 ns
(Data Out Delay Time)
tDDSPIDM SPICLK Edge to Data Out Valid 8.0 ns
(Data Out Delay Time) (SPI2)
tHDSPIDM SPICLK Edge to Data Out Not Valid 2 ns
(Data Out Hold Time)
tSDSCIM FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge 4 × tPCLK – 2.5 ns
tSDSCIM FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge (SPI2) 4 × tPCLK – 2.5 ns
tHDSM Last SPICLK Edge to FLAG3–0IN High 4 × tPCLK – 2 ns
tSPITDM Sequential Transfer Delay 4 × tPCLK – 1 ns

FLAG3-0
(OUTPUT)
tSDSCIM tSPICHM tSPICLM tSPICLKM tHDSM tSPIT DM
SPICLK
(CP = 0)
(OUTPUT)
tSPICLM tSPICHM
SPICLK
(CP = 1)
(OUTPUT)
tD D S P I D M t HDSPIDM
MOSI
MSB LSB
(OUTPUT)
tS S P I D M
tSSPIDM
CPHASE = 1
tHSPIDM tH S P I D M
MISO MSB LSB
(INPUT) VALID VALID
tDDSPIDM tHDSPIDM
MOSI
MSB LSB
(OUTPUT)
tSSPIDM tHSPIDM
CPHASE = 0
MISO MSB LSB

(INPUT) VALID VALID
Figure 34. SPI Master Timing

SPI Interface—Slave
Table 39. SPI Interface Protocol—Slave Switching and Timing Specifications

Timing Requirements
tSPICLKS Serial Clock Cycle 4 × tPCLK – 2 ns
tSPICHS Serial Clock High Period 2 × tPCLK – 2 ns
tSPICLS Serial Clock Low Period 2 × tPCLK – 2 ns
tSDSCO SPIDS Assertion to First SPICLK Edge
CPHASE = 0 2 × tPCLK ns
CPHASE = 1 2 × tPCLK ns
tHDS Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 2 × tPCLK ns
tSSPIDS Data Input Valid to SPICLK Edge (Data Input Setup Time) 2 ns
tHSPIDS SPICLK Last Sampling Edge to Data Input Not Valid 2 ns
tSDPPW SPIDS Deassertion Pulse Width (CPHASE = 0) 2 × tPCLK ns
tDSOE SPIDS Assertion to Data Out Active 0 5 ns
1
tDSOE SPIDS Assertion to Data Out Active (SPI2) 0 8 ns
tDSDHI SPIDS Deassertion to Data High Impedance 0 5 ns
tDSDHI1 SPIDS Deassertion to Data High Impedance (SPI2) 0 8.6 ns
tDDSPIDS SPICLK Edge to Data Out Valid (Data Out Delay Time) 9.5 ns
tHDSPIDS SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 × tPCLK ns
tDSOV SPIDS Assertion to Data Out Valid (CPHASE = 0) 5 × tPCLK ns
1
The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the ADSP-2136x SHARC Processor Hardware
Reference, “Serial Peripheral Interface Port” chapter.

SPIDS
(INPUT)
t S P IC H S tSPICLS tSPICL KS
SPICLK tHDS tSDPPW
(CP = 0)
(INPUT)
tSPICLS
tSDSCO tSPICHS
SPICLK
(CP = 1)
(INPUT) tDSDHI
tDDSPIDS
tDSOE tDDSPIDS
tHDSPIDS
MISO MSB LSB

(OUTPUT)
tHSPIDS
CPHASE = 1 tSSPIDS tSSPIDS
MOSI MSB VALID LSB VALID

(INPUT)
tDSOV
tDDSPIDS tHDSPIDS
tDSDHI
tD S O E
MISO MSB LSB

(OUTPUT)
CPHASE = 0 tHSPIDS
tSSPIDS
MOSI MSB VALID LSB VALID

(INPUT)
Figure 35. SPI Slave Timing

JTAG Test Access Port and Emulation
Table 40. JTAG Test Access Port and Emulation

Timing Requirements
tTCK TCK Period tCK ns
tSTAP TDI, TMS Setup Before TCK High 5 ns
tHTAP TDI, TMS Hold After TCK High 6 ns
tSSYS1 System Inputs Setup Before TCK High 7 ns
1
tHSYS System Inputs Hold After TCK High 18 ns
tTRSTW TRST Pulse Width 4tCK ns
tDTDO TDO Delay from TCK Low 7 ns
2
tDSYS System Outputs Delay After TCK Low tCK ÷ 2 + 7 ns
1
System Inputs = AD15–0, SPIDS, CLKCFG1–0, RESET, BOOTCFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.
2
System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU, ALE.
tTCK
TCK
tSTAP tHTAP
TMS
TDI
tDTDO
TDO
tSSYS tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 36. IEEE 1149.1 JTAG Test Access Port

OUTPUT DRIVE CURRENTS CAPACITIVE LOADING
Figure 37 shows typical I-V characteristics for the output driv- Output delays and holds are based on standard capacitive loads:
ers of the ADSP-2136x. The curves represent the current drive 30 pF on all pins (see Figure 38). Figure 42 shows graphically
capability of the output drivers as a function of output voltage. how output delays and holds vary with load capacitance. The
graphs of Figure 40, Figure 41, and Figure 42 may not be linear
outside the ranges shown for Typical Output Delay vs. Load
40 Capacitance and Typical Output Rise Time (20% to 80%,
VOH
V = Min) vs. Load Capacitance.
30 3.3V, +25°C
SOURCE (VDDEXT) CURRENT (mA)
20 3.47V, -45°C
12
10
3.11V, +125°C
10
0
RISE
y = 0.0467x + 1.6323
RISE AND FALL TIMES (ns)

-10 FALL
8
3.11V, +125°C
-20
3.3V, +25°C 6
-30 VOL
-40 3.47V, -45°C 4

y = 0.045x + 1.524
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
SWEEP (VDDEXT) VOLTAGE (V)
2
Figure 37. ADSP-2136x Typical Drive

0
0 50 100 150 200 250
TEST CONDITIONS LOAD CAPACITANCE (pF)
The ac signal specifications (timing parameters) appear in

Table 14 on Page 21 through Table 40 on Page 45. These include Figure 40. Typical Output Rise/Fall Time
output disable time, output enable time, and capacitive loading. (20% to 80%, VDDEXT = Max)
The timing specifications for the SHARC apply for the voltage
reference levels in Figure 38.
Timing is measured on signals when they cross the 1.5 V level as 12
described in Figure 39. All delays (in nanoseconds) are mea-
sured between the point that the first signal reaches 1.5 V and RISE
10
the point that the second signal reaches 1.5 V.
RISE AND FALL TIMES (ns)
y = 0.049x + 1.5105 FALL

8
50⍀
TO
6
OUTPUT 1.5V
PIN y = 0.0482x + 1.4604
4
30pF
2
Figure 38. Equivalent Device Loading for AC Measurements 0

0 50 100 150 200 250
(Includes All Fixtures)
LOAD CAPACITANCE (pF)
Figure 41. Typical Output Rise/Fall Time

INPUT
OR 1.5V 1.5V (20% to 80%, VDDEXT = Min)
OUTPUT
Figure 39. Voltage Reference Levels for AC Measurements

Table 41. Thermal Characteristics for BGA (No thermal vias
10 in PCB)
8 Parameter Condition Typical Unit

θJA
OUTPUT DELAY OR HOLD (ns)
Airflow = 0 m/s 25.40 °C/W

6 Y = 0.0488x - 1.5923
θJMA Airflow = 1 m/s 21.90 °C/W
4 θJMA Airflow = 2 m/s 20.90 °C/W
θJC 5.07 °C/W
2
ΨJT Airflow = 0 m/s 0.140 °C/W
0 ΨJMT Airflow = 1 m/s 0.330 °C/W
ΨJMT Airflow = 2 m/s 0.410 °C/W
-2
Table 42. Thermal Characteristics for BGA (Thermal vias in

-4
0 50 100 150 200 PCB)
LOAD CAPACITANCE (pF) Parameter Condition Typical Unit
θJA Airflow = 0 m/s 23.40 °C/W
Figure 42. Typical Output Delay or Hold vs. Load Capacitance
(at Ambient Temperature)
THERMAL CHARACTERISTICS θJC 5.00 °C/W
ΨJT Airflow = 0 m/s 0.130 °C/W
The ADSP-2136x processor is rated for performance over the
temperature range specified in Operating Conditions ΨJMT Airflow = 1 m/s 0.300 °C/W
on Page 16. ΨJMT Airflow = 2 m/s 0.360 °C/W
Table 41 and Table 42 airflow measurements comply with
JEDEC standards JESD51-2 and JESD51-6 and the junction-to-
board measurement complies with JESD51-8. Test board and
thermal via design comply with JEDEC standards JESD51-9
(BGA). The junction-to-case measurement complies with MIL-
STD-883. All measurements use a 2S2P JEDEC test board.
Industrial applications using the BGA package require thermal
vias, to an embedded ground plane, in the PCB. Refer to JEDEC
standard JESD51-9 for printed circuit board thermal ball land
and thermal via design information.
To determine the junction temperature of the device while on
the application PCB, use:
T J = T T + ( Ψ JT × P D )
where:
TJ = junction temperature (°C)
TT = case temperature (°C) measured at the top center of the
package
ΨJT = junction-to-top (of package) characterization parameter
is the typical value from Table 41.
PD = power dissipation (see EE Note No. EE-277 for more
information).
Values of θJA are provided for package comparison and PCB
design considerations.
Values of θJC are provided for package comparison and PCB
design considerations when an external heat sink is required.
Note that the thermal characteristics values provided in
Table 41 and Table 42 are modeled values.

136-BALL BGA PIN CONFIGURATIONS
The following table shows the ADSP-2136x’s pin names and
their default function after reset (in parentheses).
Table 43. BGA Pin Assignments
Ball Name Ball No. Ball Name Ball No. Ball Name Ball No. Ball Name Ball No.
CLKCFG0 A01 CLKCFG1 B01 BOOTCFG1 C01 VDDINT D01
XTAL A02 GND B02 BOOTCFG0 C02 GND D02
TMS A03 VDDEXT B03 GND C03 GND D04
TCK A04 CLKIN B04 GND C12 GND D05
TDI A05 TRST B05 GND C13 GND D06
CLKOUT A06 AVSS B06 VDDINT C14 GND D09
TDO A07 AVDD B07 GND D10
EMU A08 VDDEXT B08 GND D11
MOSI A09 SPICLK B09 GND D13
MISO A10 RESET B10 VDDINT D14
SPIDS A11 VDDINT B11
VDDINT A12 GND B12
GND A13 GND B13
GND A14 GND B14
VDDINT E01 FLAG1 F01 AD7 G01 AD6 H01
GND E02 FLAG0 F02 VDDINT G02 VDDEXT H02
GND E04 GND F04 VDDEXT G13 DAI_P18 (SD5B) H13
GND E05 GND F05 DAI_P19 (SCLK45) G14 DAI_P17 (SD5A) H14
GND E06 GND F06
GND E09 GND F09
GND E10 GND F10
GND E11 GND F11
GND E13 FLAG2 F13
FLAG3 E14 DAI_P20 (SFS45) F14

Table 43. BGA Pin Assignments (Continued)
Ball Name Ball No. Ball Name Ball No. Ball Name Ball No. Ball Name Ball No.
AD5 J01 AD3 K01 AD2 L01 AD0 M01
AD4 J02 VDDINT K02 AD1 L02 WR M02
GND J04 GND K04 GND L04 GND M03
GND J05 GND K05 GND L05 GND M12
GND J06 GND K06 GND L06 DAI_P12 (SD3B) M13
GND J09 GND K09 GND L09 DAI_P13 (SCLK23) M14
GND J10 GND K10 GND L10
GND J11 GND K11 GND L11
VDDINT J13 GND K13 GND L13
DAI_P16 (SD4B) J14 DAI_P15 (SD4A) K14 DAI_P14 (SFS23) L14
AD15 N01 AD14 P01
ALE N02 AD13 P02
RD N03 AD12 P03
VDDINT N04 AD11 P04
VDDEXT N05 AD10 P05
AD8 N06 AD9 P06
VDDINT N07 DAI_P1 (SD0A) P07
DAI_P2 (SD0B) N08 DAI_P3 (SCLK0) P08
VDDEXT N09 DAI_P5 (SD1A) P09
DAI_P4 (SFS0) N10 DAI_P6 (SD1B) P10
VDDINT N11 DAI_P7 (SCLK1) P11
VDDINT N12 DAI_P8 (SFS1) P12
GND N13 DAI_P9 (SD2A) P13
DAI_P10 (SD2B) N14 DAI_P11 (SD3A) P14

14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
KEY
VDDINT AVDD
GND*
VDDEXT AVSS I/O SIGNALS
*USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE

THERMAL PATHWAYS TO YOUR PRINTED
CIRCUIT BOARD’S GROUND PLANE.
Figure 43. BGA Pin Assignments (Bottom View, Summary)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
KEY
VDDINT GND* AVDD
VDDEXT AVSS I/O SIGNALS
*USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE

THERMAL PATHWAYS TO YOUR PRINTED
CIRCUIT BOARD’S GROUND PLANE.
Figure 44. BGA Pin Assignments (Top View, Summary)

OUTLINE DIMENSIONS
The ADSP-2136x is available in a 136-ball BGA package.
10.40 BSC SQ
12.00 BSC SQ 0.80
BSC
TYP
A
PIN A1 INDICATOR B
C
D
E
F
G
H
J
K 0.80
L BSC
M
N
TYP
P
14 13 12 11 10 9 8 7 6 5 4 3 2 1
TOP VIEW BOTTOM VIEW
1.70
DETAIL A
MAX
0.25 0.50 SEATING

1. DIMENSIONS ARE IN MILIMETERS (MM). MIN PLANE
2. THE ACTUAL POSITION OF THE BALL GRID IS 0.45
WITHIN 0.15 MM OF ITS IDEAL POSITION RELATIVE 0.40 0.12 MAX (BALL
TO THE PACKAGE EDGES. (BALL COPLANARITY)
3. COMPLIANT TO JEDEC STANDARD MO-205-AE, EXCEPT FOR DIAMETER)
THE BALL DIAMETER.
4. CENTER DIMENSIONS ARE NOMINAL.
DETAIL A
Figure 45. 136-Ball Chip Scale Package Ball Grid Array [CSP_BGA](BC-136-2)
SURFACE MOUNT DESIGN

Table 44 is provided as an aide to PCB design. For industry-
standard design recommendations, refer to IPC-7351, Generic
Requirements for Surface Mount Design and Land Pattern
Standard.
Table 44. BGA Data for Use with Surface Mount Design
Package Ball Attach Type Solder Mask Opening Ball Pad Size
136-Ball Grid Array (BC-136-2) Solder Mask Defined 0.40 mm diameter 0.53 mm diameter

ORDERING GUIDE
Operating
Temperature Instruction On-Chip Voltage Package
Model Range 1 Rate SRAM ROM Internal/External Package Description Option
ADSP-21362KBC-1AA 0°C to +70°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136-2
ADSP-21362KBCZ-1AA2 0°C to +70°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136-2
ADSP-21362BBC-1AA –40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136-2
ADSP-21362BBCZ-1AA2 –40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136-2
ADSP-21362WBBCZ-1A2 –40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136-2
ASDP-21365KBC-1AA3 0°C to +70°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136-2
ASDP-21365KBCZ-1AA2, 3 0°C to +70°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136-2
ASDP-21365BBC-1AA3 –40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136-2
ASDP-21365BBCZ-1AA2, 3 –40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136-2
ASDP-21365WBBCZ-1A2, 3 –40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136-2
ADSP-21366KBC-1AA3 0°C to +70°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136-2
ADSP-21366KBCZ-1AA2, 3 0°C to +70°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136-2
ADSP-21366BBC-1AA3 –40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136-2
ADSP-21366BBCZ-1AA2, 3 –40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136-2
ADSP-21366WBBCZ-1A2, 3 –40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136-2
1
Referenced temperature is ambient temperature.
2
Z = Pb-free part.
3
Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at
www.analog.com/SHARC.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D06359-0-12/06(A)

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a SHARC® Processor

4 BLOCKS OF ON-CHIP MEMORY

IOA IOD IOA IOD IOA IOD IOA IOD

Rev. A | Page 2 of 52 | December 2006

ADSP-2136x Specifications ....................................... 16

Rev. A | Page 3 of 52 | December 2006

Rev. A | Page 4 of 52 | December 2006

Figure 2. ADSP-2136x System Sample Configuration

Rev. A | Page 5 of 52 | December 2006

Table 3. ADSP-2136x Internal Memory Space

IOP Registers 0x0000 0000–0003 FFFF

Rev. A | Page 6 of 52 | December 2006

IOP Registers 0x0000 0000–0003 FFFF

store combinations of code and data, accesses are most efficient

neously executing its program instructions. DMA transfers can

SIGNAL ROUTING UNIT

fers, and DMA chaining for automatic linked DMA transfers. 3

Digital Audio Interface (DAI) DIGITAL AUDIO INTERFACE

Rev. A | Page 7 of 52 | December 2006

Rev. A | Page 8 of 52 | December 2006

ROM-Based Security Target Board JTAG Emulator Connector

Rev. A | Page 9 of 52 | December 2006

Rev. A | Page 10 of 52 | December 2006

Rev. A | Page 11 of 52 | December 2006

Table 4. Pin Descriptions

State During and

Rev. A | Page 12 of 52 | December 2006

State During and

Rev. A | Page 13 of 52 | December 2006

State During and

Rev. A | Page 14 of 52 | December 2006

Table 6. Address/Data Mode Selection

PP Data AD7–AD0 AD15–AD8

Rev. A | Page 15 of 52 | December 2006

Parameter1 Description Min Max Min Max Unit

VDDINT Internal (Core) Supply Voltage 1.14 1.26 1.14 1.26 V

Parameter1 Description Test Conditions Min Max Unit

Rev. A | Page 16 of 52 | December 2006

ABSOLUTE MAXIMUM RATINGS

Rev. A | Page 17 of 52 | December 2006

Figure 6. Core Clock and System Clock Relationship to CLKIN

Rev. A | Page 18 of 52 | December 2006

Table 12. Power-Up Sequencing Timing Requirements (Processor Startup)

Parameter Min Max Unit

Figure 7. Power-Up Sequencing

Rev. A | Page 19 of 52 | December 2006

Table 13. Clock Input

Figure 8. Clock Input

tion program can configure theADSP-2136x to use its internal

CLKIN and XTAL pins. Figure 9 shows the component connec-

Figure 9. 333 MHz Operation (Fundamental Mode Crystal)

Rev. A | Page 20 of 52 | December 2006

Table 14. Reset

Parameter Min Max Unit

Figure 10. Reset

Table 15. Interrupts

Parameter Min Max Unit

Figure 11. Interrupts

Rev. A | Page 21 of 52 | December 2006

Table 16. Core Timer