ADSP-BF561 Data Sheet

Blackfin Embedded
Symmetric Multiprocessor
ADSP-BF561
FEATURES 2 internal memory-to-memory DMAs and 1 internal memory
DMA controller
Dual symmetric 600 MHz high performance Blackfin cores
12 general-purpose 32-bit timers/counters with PWM
328K bytes of on-chip memory
capability
(see Memory Architecture on Page 4)
SPI-compatible port
Each Blackfin core includes
UART with support for IrDA
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter Dual watchdog timers
RISC-like register and instruction model for ease of pro Dual 32-bit core timers
gramming and compiler-friendly support 48 programmable flags (GPIO)
Advanced debug, trace, and performance monitoring On-chip phase-locked loop capable of 0.5× to 64× frequency
Wide range of operating voltages, (see Operating Conditions multiplication
on Page 20) 2 parallel input/output peripheral interface units supporting
256-ball CSP_BGA (2 sizes) and 297-ball PBGA ITU-R 656 video and glueless interface to analog front end
package options ADCs
2 dual channel, full duplex synchronous serial ports support
PERIPHERALS ing eight stereo I2S channels
Dual 12-channel DMA controllers
(supporting 24 peripheral DMAs)
2 memory-to-memory DMAs
IRQ CONTROL/ JTAG TEST IRQ CONTROL/

VOLTAGE
WATCHDOG EMULATION WATCHDOG
REGULATOR
TIMER TIMER
B B UART
IrDA
L1 L1 L1 L1 SPI
INSTRUCTION DATA INSTRUCTION DATA L2 SRAM
MEMORY MEMORY MEMORY MEMORY 128K BYTES
SPORT0
IMDMA SPORT1
CORE SYSTEM/BUS INTERFACE
CONTROLLER
GPIO
EAB
DMA
CONTROLLER1
32 TIMERS
DMA
DEB CONTROLLER2
DAB 16
BOOT ROM
32 PAB 16
DAB
EXTERNAL PORT
PPI0 PPI1
FLASH/SDRAM CONTROL
Figure 1. Functional Block Diagram

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Rev. E
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ADSP-BF561
TABLE OF CONTENTS
Features ................................................................. 1 Designing an Emulator-Compatible Processor Board ... 16
Peripherals ............................................................. 1 Related Documents .............................................. 16
Table of Contents ..................................................... 2 Pin Descriptions .................................................... 17
Revision History ...................................................... 2 Specifications ........................................................ 20
General Description ................................................. 3 Operating Conditions ........................................... 20
Portable Low Power Architecture ............................. 3 Electrical Characteristics ....................................... 21
Blackfin Processor Core .......................................... 3 Absolute Maximum Ratings ................................... 22
Memory Architecture ............................................ 4 Package Information ............................................ 22
DMA Controllers .................................................. 8 ESD Sensitivity ................................................... 22
Watchdog Timer .................................................. 8 Timing Specifications ........................................... 23
Timers ............................................................... 9 Output Drive Currents ......................................... 41
Serial Ports (SPORTs) ............................................ 9 Power Dissipation ............................................... 42
Serial Peripheral Interface (SPI) Port ......................... 9 Test Conditions .................................................. 42
UART Port .......................................................... 9 Environmental Conditions .................................... 44
Programmable Flags (PFx) .................................... 10 256-Ball CSP_BGA (17 mm) Ball Assignment ............... 46
Parallel Peripheral Interface ................................... 10 256-Ball CSP_BGA (12 mm) Ball Assignment ............... 51
Dynamic Power Management ................................ 11 297-Ball PBGA Ball Assignment ................................. 56
Voltage Regulation .............................................. 12 Outline Dimensions ................................................ 61
Clock Signals ..................................................... 13 Surface-Mount Design .......................................... 63
Booting Modes ................................................... 14 Automotive Products .............................................. 63
Instruction Set Description ................................... 14 Ordering Guide ..................................................... 63
Development Tools ............................................. 15
REVISION HISTORY
9/09—Rev. D to Rev. E
Correct all outstanding document errata.
Revised Figure 5 ..................................................................... 13
Added 533 MHz operation Table 10 .................................. 20
Removed reference to 1.8 V operation Table 12 ............... 21
Added Table 17 and Figure 9 Power-Up Reset Timing .... 23
Removed references to TJ from tSCLK parameter
Table 20 ................................................................................... 26
Added new SPORT timing parameters and diagram
Table 23 ................................................................................... 32
Figure 21 ................................................................................. 33
Rev. E | Page 2 of 64 | September 2009

ADSP-BF561
GENERAL DESCRIPTION
The ADSP-BF561 processor is a high performance member of The powerful 40-bit shifter has extensive capabilities for per
the Blackfin® family of products targeting a variety of multime forming shifting, rotating, normalization, extraction, and
dia, industrial, and telecommunications applications. At the depositing of data. The data for the computational units is
heart of this device are two independent Analog Devices found in a multiported register file of sixteen 16-bit entries or
Blackfin processors. These Blackfin processors combine a dual- eight 32-bit entries.
MAC state-of-the-art signal processing engine, the advantage of A powerful program sequencer controls the flow of instruction
a clean, orthogonal RISC-like microprocessor instruction set, execution, including instruction alignment and decoding. The
and single instruction, multiple data (SIMD) multimedia capa sequencer supports conditional jumps and subroutine calls, as
bilities in a single instruction set architecture. well as zero overhead looping. A loop buffer stores instructions
The ADSP-BF561 processor has 328K bytes of on-chip memory. locally, eliminating instruction memory accesses for tight
Each Blackfin core includes: looped code.
• 16K bytes of instruction SRAM/cache Two data address generators (DAGs) provide addresses for
• 16K bytes of instruction SRAM simultaneous dual operand fetches from memory. The DAGs
share a register file containing four sets of 32-bit Index, Modify,
• 32K bytes of data SRAM/cache Length, and Base registers. Eight additional 32-bit registers
• 32K bytes of data SRAM provide pointers for general indexing of variables and stack
locations.
• 4K bytes of scratchpad SRAM
Blackfin processors support a modified Harvard architecture in
Additional on-chip memory peripherals include:
combination with a hierarchical memory structure. Level 1 (L1)
• 128K bytes of low latency on-chip L2 SRAM memories are those that typically operate at the full processor
• Four-channel internal memory DMA controller speed with little or no latency. Level 2 (L2) memories are other
memories, on-chip or off-chip, that may take multiple processor
• External memory controller with glueless support for
cycles to access. At the L1 level, the instruction memory holds
SDRAM, mobile SDRAM, SRAM, and flash.
instructions only. The two data memories hold data, and a dedi
PORTABLE LOW POWER ARCHITECTURE cated scratchpad data memory stores stack and local variable
information. At the L2 level, there is a single unified memory
Blackfin processors provide world-class power management space, holding both instructions and data.
and performance. Blackfin processors are designed in a low
power and low voltage design methodology and feature In addition, half of L1 instruction memory and half of L1 data
dynamic power management, the ability to vary both the voltage memory may be configured as either Static RAMs (SRAMs) or
and frequency of operation to significantly lower overall power caches. The Memory Management Unit (MMU) provides mem
consumption. Varying the voltage and frequency can result in a ory protection for individual tasks that may be operating on the
substantial reduction in power consumption, compared with core and may protect system registers from unintended access.
just varying the frequency of operation. This translates into The architecture provides three modes of operation: user mode,
longer battery life for portable appliances. supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
BLACKFIN PROCESSOR CORE protected software environment, while supervisor mode has
As shown in Figure 2, each Blackfin core contains two multi unrestricted access to the system and core resources.
plier/accumulators (MACs), two 40-bit ALUs, four video ALUs, The Blackfin instruction set has been optimized so that 16-bit
and a single shifter. The computational units process 8-bit, op-codes represent the most frequently used instructions,
16-bit, or 32-bit data from the register file. resulting in excellent compiled code density. Complex DSP
Each MAC performs a 16-bit by 16-bit multiply in every cycle, instructions are encoded into 32-bit op-codes, representing fully
with accumulation to a 40-bit result, providing eight bits of featured multifunction instructions. Blackfin processors sup
extended precision. The ALUs perform a standard set of arith port a limited multi-issue capability, where a 32-bit instruction
metic and logical operations. With two ALUs capable of can be issued in parallel with two 16-bit instructions, allowing
operating on 16-bit or 32-bit data, the flexibility of the computa the programmer to use many of the core resources in a single
tion units covers the signal processing requirements of a varied instruction cycle.
set of application needs. The Blackfin assembly language uses an algebraic syntax for
Each of the two 32-bit input registers can be regarded as two ease of coding and readability. The architecture has been opti
16-bit halves, so each ALU can accomplish very flexible single mized for use in conjunction with the VisualDSP C/C++
16-bit arithmetic operations. By viewing the registers as pairs of compiler, resulting in fast and efficient software
16-bit operands, dual 16-bit or single 32-bit operations can be implementations.
accomplished in a single cycle. By further taking advantage of
the second ALU, quad 16-bit operations can be accomplished
simply, accelerating the per cycle throughput.

ADSP-BF561
ADDRESS ARITHMETIC UNIT
SP
I3 L3 B3 M3 FP
I2 L2 B2 M2 P5
I1 L1 B1 M1 DAG1 P4
I0 L0 B0 M0 P3
DAG0
P2
DA1 32
P1
DA0 32
P0
TO MEMORY
32 32
RAB PREG
SD 32
LD1 32 32 ASTAT
LD0 32
32
SEQUENCER
R7.H R7.L
R6.H R6.L
R5.H R5.L ALIGN
R4.H R4.L 16 16
8 8 8 8
R3.H R3.L
R2.H R2.L DECODE
R1.H R1.L BARREL
R0.H R0.L SHIFTER 40 40 LOOP BUFFER
40 40
A0 A1 CONTROL
UNIT
32
32
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
MEMORY ARCHITECTURE Internal (On-Chip) Memory

The ADSP-BF561 views memory as a single unified 4G byte The ADSP-BF561 has four blocks of on-chip memory providing
address space, using 32-bit addresses. All resources including high bandwidth access to the core.
internal memory, external memory, and I/O control registers The first is the L1 instruction memory of each Blackfin core
occupy separate sections of this common address space. The consisting of 16K bytes of four-way set-associative cache mem
memory portions of this address space are arranged in a hierar ory and 16K bytes of SRAM. The cache memory may also be
chical structure to provide a good cost/performance balance of configured as an SRAM. This memory is accessed at full proces
some very fast, low latency memory as cache or SRAM very sor speed. When configured as SRAM, each of the two 16K
close to the processor, and larger, lower cost and performance banks of memory is broken into 4K sub-banks which can be
memory systems farther away from the processor. The independently accessed by the processor and DMA.
ADSP-BF561 memory map is shown in Figure 3.
The second on-chip memory block is the L1 data memory of
The L1 memory system in each core is the highest performance each Blackfin core which consists of four banks of 16K bytes
memory available to each Blackfin core. The L2 memory pro each. Two of the L1 data memory banks can be configured as
vides additional capacity with lower performance. Lastly, the one way of a two-way set-associative cache or as an SRAM. The
off-chip memory system, accessed through the External Bus other two banks are configured as SRAM. All banks are accessed
Interface Unit (EBIU), provides expansion with SDRAM, flash at full processor speed. When configured as SRAM, each of the
memory, and SRAM, optionally accessing more than four 16K banks of memory is broken into 4K sub-banks which
768M bytes of physical memory. The memory DMA controllers can be independently accessed by the processor and DMA.
provide high bandwidth data movement capability. They can
perform block transfers of code or data between the internal The third memory block associated with each core is a 4K byte
L1/L2 memories and the external memory spaces. scratchpad SRAM which runs at the same speed as the L1 mem
ories, but is only accessible as data SRAM (it cannot be
configured as cache memory and is not accessible via DMA).

ADSP-BF561
CORE A MEMORY MAP CORE B MEMORY MAP

0xFFFF FFFF
CORE MMR REGISTERS CORE MMR REGISTERS
0xFFE0 0000
0xFFC0 0000 SYSTEM MMR REGISTERS
RESERVED
0xFFB0 1000
L1 SCRATCHPAD SRAM (4K)
0xFFB0 0000
RESERVED
0xFFA1 4000
L1 INSTRUCTION SRAM/CACHE (16K)
0xFFA1 0000
RESERVED
0xFFA0 4000
L1 INSTRUCTION SRAM (16K)
0xFFA0 0000 RESERVED
RESERVED
0xFF90 8000
L1 DATA BANK B SRAM/CACHE (16K)
0xFF90 4000
L1 DATA BANK B SRAM (16K)
0xFF90 0000
RESERVED
0xFF80 8000
L1 DATA BANK A SRAM/CACHE (16K)
0xFF80 4000
L1 DATA BANK A SRAM (16K)
0xFF80 0000 0xFF80 0000
RESERVED
0xFF70 1000
INTERNAL MEMORY
L1 SCRATCHPAD SRAM (4K)
0xFF70 0000
RESERVED
0xFF61 4000
L1 INSTRUCTION SRAM/CACHE (16K)
0xFF61 0000
RESERVED
0xFF60 4000
L1 INSTRUCTION SRAM (16K)
RESERVED 0xFF60 0000
RESERVED
0xFF50 8000
L1 DATA BANK B SRAM/CACHE (16K)
0xFF50 4000
L1 DATA BANK B SRAM (16K)
0xFF50 0000
RESERVED
0xFF40 8000
L1 DATA BANK A SRAM/CACHE (16K)
0xFF40 4000
L1 DATA BANK A SRAM (16K)
0xFF40 0000
RESERVED
0xFEB2 0000
L2 SRAM (128K)
0xFEB0 0000
RESERVED
0xEF00 4000
BOOT ROM
0xEF00 0000
RESERVED
0x3000 0000
ASYNC MEMORY BANK 3
0x2C00 0000
ASYNC MEMORY BANK 2
0x2800 0000
ASYNC MEMORY BANK 1
0x2400 0000
ASYNC MEMORY BANK 0
0x2000 0000
RESERVED EXTERNAL MEMORY
Top of last SDRAM page
SDRAM BANK 3
SDRAM BANK 2
SDRAM BANK 1
SDRAM BANK 0
0x0000 0000
Figure 3. Memory Map
The fourth on-chip memory system is the L2 SRAM memory External (Off-Chip) Memory
array which provides 128K bytes of high speed SRAM operating
The ADSP-BF561 external memory is accessed via the External
at one half the frequency of the core, and slightly longer latency
Bus Interface Unit (EBIU). This interface provides a glueless
than the L1 memory banks. The L2 memory is a unified instruc
connection to up to four banks of synchronous DRAM
tion and data memory and can hold any mixture of code and
(SDRAM) as well as up to four banks of asynchronous memory
data required by the system design. The Blackfin cores share a
devices, including flash, EPROM, ROM, SRAM, and memory
dedicated low latency 64-bit wide data path port into the L2
mapped I/O devices.
SRAM memory.
The PC133-compliant SDRAM controller can be programmed
Each Blackfin core processor has its own set of core Memory
to interface to up to four banks of SDRAM, with each bank con
Mapped Registers (MMRs) but share the same system MMR
taining between 16M bytes and 128M bytes providing access to
registers and 128K bytes L2 SRAM memory.
up to 512M bytes of SDRAM. Each bank is independently pro
grammable and is contiguous with adjacent banks regardless of
the sizes of the different banks or their placement. This allows

ADSP-BF561
flexible configuration and upgradability of system memory • Interrupts – Events that occur asynchronously to program
while allowing the core to view all SDRAM as a single, contigu flow. They are caused by timers, peripherals, input pins,
ous, physical address space. and an explicit software instruction.
The asynchronous memory controller can also be programmed Each event has an associated register to hold the return address
to control up to four banks of devices with very flexible timing and an associated “return from event” instruction. When an
parameters for a wide variety of devices. Each bank occupies a event is triggered, the state of the processor is saved on the
64M byte segment regardless of the size of the devices used so supervisor stack.
that these banks will only be contiguous if fully populated with The ADSP-BF561 event controller consists of two stages: the
64M bytes of memory. Core Event Controller (CEC) and the System Interrupt Control
I/O Memory Space ler (SIC). The Core Event Controller works with the System
Interrupt Controller to prioritize and control all system events.
Blackfin processors do not define a separate I/O space. All Conceptually, interrupts from the peripherals enter into the
resources are mapped through the flat 32-bit address space. On- SIC, and are then routed directly into the general-purpose
chip I/O devices have their control registers mapped into mem interrupts of the CEC.
ory mapped registers (MMRs) at addresses near the top of the
4G byte address space. These are separated into two smaller Core Event Controller (CEC)
blocks, one which contains the control MMRs for all core func The CEC supports nine general-purpose interrupts (IVG15–7),
tions, and the other which contains the registers needed for in addition to the dedicated interrupt and exception events. Of
setup and control of the on-chip peripherals outside of the core. these general-purpose interrupts, the two lowest priority inter
The core MMRs are accessible only by the core and only in rupts (IVG15–14) are recommended to be reserved for software
supervisor mode and appear as reserved space by on-chip interrupt handlers, leaving seven prioritized interrupt inputs to
peripherals. The system MMRs are accessible by the core in support the peripherals of the ADSP-BF561. Table 1 describes
supervisor mode and can be mapped as either visible or reserved the inputs to the CEC, identifies their names in the Event Vector
to other devices, depending on the system protection Table (EVT), and lists their priorities.
model desired.
Booting Table 1. Core Event Controller (CEC)
The ADSP-BF561 contains a small boot kernel, which config Priority

ures the appropriate peripheral for booting. If the ADSP-BF561 (0 is Highest) Event Class EVT Entry
is configured to boot from boot ROM memory space, the pro 0 Emulation/Test Control EMU
cessor starts executing from the on-chip boot ROM. 1 Reset RST
Event Handling 2 Nonmaskable Interrupt NMI
3 Exceptions EVX
The event controller on the ADSP-BF561 handles all asynchro
nous and synchronous events to the processor. The 4 Global Enable
ADSP-BF561 provides event handling that supports both nest 5 Hardware Error IVHW
ing and prioritization. Nesting allows multiple event service 6 Core Timer IVTMR
routines to be active simultaneously. Prioritization ensures that 7 General Interrupt 7 IVG7
servicing of a higher priority event takes precedence over servic
8 General Interrupt 8 IVG8
ing of a lower priority event. The controller provides support for
five different types of events: 9 General Interrupt 9 IVG9
• Emulation – An emulation event causes the processor to 10 General Interrupt 10 IVG10
enter emulation mode, allowing command and control of 11 General Interrupt 11 IVG11
the processor via the JTAG interface. 12 General Interrupt 12 IVG12
• Reset – This event resets the processor. 13 General Interrupt 13 IVG13
• Nonmaskable Interrupt (NMI) – The NMI event can be 14 General Interrupt 14 IVG14
generated by the software watchdog timer or by the NMI 15 General Interrupt 15 IVG15
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut System Interrupt Controller (SIC)
down of the system.
The System Interrupt Controller provides the mapping and
• Exceptions – Events that occur synchronously to program routing of events from the many peripheral interrupt sources to
flow, i.e., the exception will be taken before the instruction the prioritized general-purpose interrupt inputs of the CEC.
is allowed to complete. Conditions such as data alignment Although the ADSP-BF561 provides a default mapping, the user
violations or undefined instructions cause exceptions. can alter the mappings and priorities of interrupt events by

ADSP-BF561
writing the appropriate values into the Interrupt Assignment Table 2. System Interrupt Controller (SIC) (Continued)
Registers (SIC_IAR7–0). Table 2 describes the inputs into the
Default
SIC and the default mappings into the CEC.
Peripheral Interrupt Event Mapping
Table 2. System Interrupt Controller (SIC) Timer7 Interrupt IVG10
Timer8 Interrupt IVG10
Default
Peripheral Interrupt Event Mapping Timer9 Interrupt IVG10
PLL Wakeup IVG7 Timer10 Interrupt IVG10
DMA1 Error (Generic) IVG7 Timer11 Interrupt IVG10
DMA2 Error (Generic) IVG7 Programmable Flags 15–0 Interrupt A IVG11
IMDMA Error IVG7 Programmable Flags 15–0 Interrupt B IVG11
PPI0 Error IVG7 Programmable Flags 31–16 Interrupt A IVG11
PPI1 Error IVG7 Programmable Flags 31–16 Interrupt B IVG11
SPORT0 Error IVG7 Programmable Flags 47–32 Interrupt A IVG11
SPORT1 Error IVG7 Programmable Flags 47–32 Interrupt B IVG11
SPI Error IVG7 DMA1 Channel 12/13 Interrupt IVG8
(Memory DMA/Stream 0)
UART Error IVG7
DMA1 Channel 14/15 Interrupt IVG8
Reserved IVG7
(Memory DMA/Stream 1)
DMA1 Channel 0 Interrupt (PPI0) IVG8
DMA2 Channel 12/13 Interrupt IVG9
DMA1 Channel 1 Interrupt (PPI1) IVG8 (Memory DMA/Stream 0)
DMA1 Channel 2 Interrupt IVG8 DMA2 Channel 14/15 Interrupt IVG9
DMA1 Channel 3 Interrupt IVG8 (Memory DMA/Stream 1)
DMA1 Channel 4 Interrupt IVG8 IMDMA Stream 0 Interrupt IVG12
DMA1 Channel 5 Interrupt IVG8 IMDMA Stream 1 Interrupt IVG12
DMA1 Channel 6 Interrupt IVG8 Watchdog Timer Interrupt IVG13
DMA1 Channel 7 Interrupt IVG8 Reserved IVG7
DMA1 Channel 8 Interrupt IVG8 Reserved IVG7
DMA1 Channel 9 Interrupt IVG8 Supplemental Interrupt 0 IVG7
DMA1 Channel 10 Interrupt IVG8 Supplemental Interrupt 1 IVG7
DMA1 Channel 11 Interrupt IVG8
DMA2 Channel 0 Interrupt (SPORT0 Rx) IVG9 Event Control
DMA2 Channel 1 Interrupt (SPORT0 Tx) IVG9 The ADSP-BF561 provides the user with a very flexible mecha
DMA2 Channel 2 Interrupt (SPORT1 Rx) IVG9 nism to control the processing of events. In the CEC, three
DMA2 Channel 3 Interrupt (SPORT1 Tx) IVG9 registers are used to coordinate and control events. Each of the
registers is 16 bits wide, while each bit represents a particular
DMA2 Channel 4 Interrupt (SPI) IVG9
event class.
DMA2 Channel 5 Interrupt (UART Rx) IVG9
• CEC Interrupt Latch Register (ILAT) – The ILAT register
DMA2 Channel 6 Interrupt (UART Tx) IVG9
indicates when events have been latched. The appropriate
DMA2 Channel 7 Interrupt IVG9 bit is set when the processor has latched the event and
DMA2 Channel 8 Interrupt IVG9 cleared when the event has been accepted into the system.
DMA2 Channel 9 Interrupt IVG9 This register is updated automatically by the controller, but
DMA2 Channel 10 Interrupt IVG9 may also be written to clear (cancel) latched events. This
register may be read while in supervisor mode and may
DMA2 Channel 11 Interrupt IVG9 only be written while in supervisor mode when the corre
Timer0 Interrupt IVG10 sponding IMASK bit is cleared.
Timer1 Interrupt IVG10 • CEC Interrupt Mask Register (IMASK) – The IMASK reg
Timer2 Interrupt IVG10 ister controls the masking and unmasking of individual
Timer3 Interrupt IVG10 events. When a bit is set in the IMASK register, that event is
Timer4 Interrupt IVG10 unmasked and will be processed by the CEC when asserted.
A cleared bit in the IMASK register masks the event,
thereby preventing the processor from servicing the event

ADSP-BF561
even though the event may be latched in the ILAT register. peripherals. Additionally, DMA transfers can be accomplished
This register may be read from or written to while in between any of the DMA-capable peripherals and external
supervisor mode. devices connected to the external memory interfaces, including
Note that general-purpose interrupts can be globally the SDRAM controller and the asynchronous memory
enabled and disabled with the STI and CLI instructions, controller. DMA-capable peripherals include the SPORTs, SPI
respectively. port, UART, and PPIs. Each individual DMA-capable periph
eral has at least one dedicated DMA channel.
• CEC Interrupt Pending Register (IPEND) – The IPEND
register keeps track of all nested events. A set bit in the The ADSP-BF561 DMA controllers support both 1-dimen
IPEND register indicates the event is currently active or sional (1-D) and 2-dimensional (2-D) DMA transfers. DMA
nested at some level. This register is updated automatically transfer initialization can be implemented from registers or
by the controller but may be read while in supervisor mode. from sets of parameters called descriptor blocks.
The SIC allows further control of event processing by providing The 2-D DMA capability supports arbitrary row and column
six 32-bit interrupt control and status registers. Each register sizes up to 64K elements by 64K elements, and arbitrary row
contains a bit corresponding to each of the peripheral interrupt and column step sizes up to ± 32K elements. Furthermore, the
events shown in Table 2. column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
• SIC Interrupt Mask Registers (SIC_IMASKx) – These reg especially useful in video applications where data can be de-
isters control the masking and unmasking of each interleaved on the fly.
peripheral interrupt event. When a bit is set in these regis
ters, that peripheral event is unmasked and will be Examples of DMA types supported by the ADSP-BF561 DMA
processed by the system when asserted. A cleared bit in controllers include:
these registers masks the peripheral event, thereby prevent • A single linear buffer that stops upon completion.
ing the processor from servicing the event. • A circular autorefreshing buffer that interrupts on each full
• SIC Interrupt Status Registers (SIC_ISRx) – As multiple or fractionally full buffer.
peripherals can be mapped to a single event, these registers • 1-D or 2-D DMA using a linked list of descriptors.
allow the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the • 2-D DMA using an array of descriptors, specifying only the
peripheral is asserting the interrupt; a cleared bit indicates base DMA address within a common page.
the peripheral is not asserting the event. In addition to the dedicated peripheral DMA channels, each
• SIC Interrupt Wakeup Enable Registers (SIC_IWRx) – By DMA Controller has four memory DMA channels provided for
enabling the corresponding bit in these registers, each transfers between the various memories of the ADSP-BF561
peripheral can be configured to wake up the processor, system. These enable transfers of blocks of data between any of
should the processor be in a powered-down mode when the memories—including external SDRAM, ROM, SRAM, and
the event is generated. flash memory—with minimal processor intervention. Memory
DMA transfers can be controlled by a very flexible descriptor-
Because multiple interrupt sources can map to a single general- based methodology or by a standard register-based autobuffer
purpose interrupt, multiple pulse assertions can occur simulta mechanism.
neously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND reg Further, the ADSP-BF561 has a four channel Internal Memory
ister contents are monitored by the SIC as the interrupt DMA (IMDMA) Controller. The IMDMA Controller allows
acknowledgement. data transfers between any of the internal L1 and L2 memories.
The appropriate ILAT register bit is set when an interrupt rising WATCHDOG TIMER
edge is detected (detection requires two core clock cycles). The
Each ADSP-BF561 core includes a 32-bit timer, which can be
bit is cleared when the respective IPEND register bit is set. The
used to implement a software watchdog function. A software
IPEND bit indicates that the event has entered into the proces
watchdog can improve system availability by forcing the proces
sor pipeline. At this point the CEC will recognize and queue the
sor to a known state, via generation of a hardware reset,
next rising edge event on the corresponding event input. The
nonmaskable interrupt (NMI), or general-purpose interrupt, if
minimum latency from the rising edge transition of the general-
the timer expires before being reset by software. The program
purpose interrupt to the IPEND output asserted is three core
mer initializes the count value of the timer, enables the
clock cycles; however, the latency can be much higher, depend
appropriate interrupt, then enables the timer. Thereafter, the
ing on the activity within and the mode of the processor.
software must reload the counter before it counts to zero from
DMA CONTROLLERS the programmed value. This protects the system from remain
ing in an unknown state where software, which would normally
The ADSP-BF561 has two independent DMA controllers that reset the timer, has stopped running due to an external noise
support automated data transfers with minimal overhead for condition or software error.
the DSP cores. DMA transfers can occur between the
ADSP-BF561 internal memories and any of its DMA-capable

ADSP-BF561
After a reset, software can determine if the watchdog was the • DMA operations with single-cycle overhead – Each SPORT
source of the hardware reset by interrogating a status bit in the can automatically receive and transmit multiple buffers of
timer control register, which is set only upon a watchdog gener memory data. The DSP can link or chain sequences of
ated reset. DMA transfers between a SPORT and memory.
The timer is clocked by the system clock (SCLK) at a maximum • Interrupts – Each transmit and receive port generates an
frequency of fSCLK. interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
TIMERS DMA.
There are 14 programmable timer units in the ADSP-BF561. • Multichannel capability – Each SPORT supports 128 chan
Each of the 12 general-purpose timer units can be indepen nels out of a 1,024-channel window and is compatible with
dently programmed as a Pulse Width Modulator (PWM), the H.100, H.110, MVIP-90, and HMVIP standards.
internally or externally clocked timer, or pulse width counter. An additional 250 mV of SPORT input hysteresis can be
The general-purpose timer units can be used in conjunction enabled by setting Bit 15 of the PLL_CTL register. When this bit
with the UART to measure the width of the pulses in the data is set, all SPORT input pins have the increased hysteresis.
stream to provide an autobaud detect function for a serial chan
nel. The general-purpose timers can generate interrupts to the SERIAL PERIPHERAL INTERFACE (SPI) PORT
processor core providing periodic events for synchronization, The ADSP-BF561 processor has an SPI-compatible port that
either to the processor clock or to a count of external signals. enables the processor to communicate with multiple SPI-com
In addition to the 12 general-purpose programmable timers, patible devices.
another timer is also provided for each core. These extra timers The SPI interface uses three pins for transferring data: two data
are clocked by the internal processor clock (CCLK) and are typ pins (master output-slave input, MOSI, and master input-slave
ically used as a system tick clock for generation of operating output, MISO) and a clock pin (serial clock, SCK). An SPI chip
system periodic interrupts. select input pin (SPISS) lets other SPI devices select the proces
SERIAL PORTS (SPORTs) sor, and seven SPI chip select output pins (SPISEL7–1) let the
processor select other SPI devices. The SPI select pins are recon
The ADSP-BF561 incorporates two dual-channel synchronous figured programmable flag pins. Using these pins, the SPI port
serial ports (SPORT0 and SPORT1) for serial and multiproces provides a full-duplex, synchronous serial interface which sup
sor communications. The SPORTs support the following ports both master/slave modes and multimaster environments.
features:
The baud rate and clock phase/polarities for the SPI port are
• I2S capable operation. programmable, and it has an integrated DMA controller, con
• Bidirectional operation – Each SPORT has two sets of inde figurable to support transmit or receive data streams. The SPI
pendent transmit and receive pins, enabling eight channels DMA controller can only service unidirectional accesses at any
of I2S stereo audio. given time.
• Buffered (8-deep) transmit and receive ports – Each port The SPI port clock rate is calculated as:
has a data register for transferring data words to and from
f SCLK
other DSP components and shift registers for shifting data SPI Clock Rate = -----------------------------------
-
in and out of the data registers. 2 × SPI_BAUD
Where the 16-bit SPI_BAUD register contains a value of 2 to
• Clocking – Each transmit and receive port can either use an 65,535.
external serial clock or generate its own, in frequencies
During transfers, the SPI port simultaneously transmits and
ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz.
receives by serially shifting data in and out on its two serial data
• Word length – Each SPORT supports serial data words lines. The serial clock line synchronizes the shifting and sam
from 3 bits to 32 bits in length, transferred most significant pling of data on the two serial data lines.
bit first or least significant bit first.
• Framing – Each transmit and receive port can run with or
UART PORT
without frame sync signals for each data word. Frame sync The ADSP-BF561 processor provides a full-duplex universal
signals can be generated internally or externally, active high asynchronous receiver/transmitter (UART) port, which is fully
or low, and with either of two pulse widths and early or late compatible with PC-standard UARTs. The UART port provides
frame sync. a simplified UART interface to other peripherals or hosts, sup
• Companding in hardware – Each SPORT can perform porting full-duplex, DMA-supported, asynchronous transfers of
A-law or μ-law companding according to ITU recommen serial data. The UART port includes support for 5 data bits to
dation G.711. Companding can be selected on the transmit 8 data bits, 1 stop bit or 2 stop bits, and none, even, or odd par
and/or receive channel of the SPORT without additional ity. The UART port supports two modes of operation:
latencies.

ADSP-BF561
• PIO (programmed I/O) – The processor sends or receives • Flag interrupt mask registers – These registers allow each
data by writing or reading I/O-mapped UART registers. individual PFx pin to function as an interrupt to the pro
The data is double-buffered on both transmit and receive. cessor. Similar to the flag control registers that are used to
• DMA (direct memory access) – The DMA controller trans set and clear individual flag values, one flag interrupt mask
fers both transmit and receive data. This reduces the register sets bits to enable an interrupt function, and the
number and frequency of interrupts required to transfer other flag interrupt mask register clears bits to disable an
data to and from memory. The UART has two dedicated interrupt function. PFx pins defined as inputs can be con
DMA channels, one for transmit and one for receive. These figured to generate hardware interrupts, while output PFx
DMA channels have lower default priority than most DMA pins can be configured to generate software interrupts.
channels because of their relatively low service rates. • Flag interrupt sensitivity registers – These registers specify
The baud rate, serial data format, error code generation and whether individual PFx pins are level- or edge-sensitive
status, and interrupts for the UART port are programmable. and specify, if edge-sensitive, whether just the rising edge
or both the rising and falling edges of the signal are signifi
The UART programmable features include: cant. One register selects the type of sensitivity, and one
• Supporting bit rates ranging from (fSCLK/1,048,576) bits per register selects which edges are significant for edge
second to (fSCLK/16) bits per second. sensitivity.
• Supporting data formats from seven bits to 12 bits per PARALLEL PERIPHERAL INTERFACE
frame.
The ADSP-BF561 processor provides two parallel peripheral
• Both transmit and receive operations can be configured to interfaces (PPI0, PPI1) that can connect directly to parallel A/D
generate maskable interrupts to the processor. and D/A converters, video encoders and decoders, and other
The UART port’s clock rate is calculated as: general-purpose peripherals. The PPI consists of a dedicated
f SCLK input clock pin, up to 3 frame synchronization pins, and up to
-
UART Clock Rate = ---------------------------------------------- 16 data pins. The input clock supports parallel data rates at up to
16 × UART_Divisor
fSCLK/2 MHz, and the synchronization signals can be configured
Where the 16-bit UART_Divisor comes from the UART_DLH as either inputs or outputs.
register (most significant 8 bits) and UART_DLL register (least
significant 8 bits). The PPI supports a variety of general-purpose and ITU-R 656
modes of operation. In general-purpose mode, the PPI provides
In conjunction with the general-purpose timer functions, half-duplex, bi-directional data transfer with up to 16 bits of
autobaud detection is supported. data. Up to 3 frame synchronization signals are also provided.
The capabilities of the UART are further extended with support In ITU-R 656 mode, the PPI provides half-duplex, bi-direc
for the Infrared Data Association (IrDA®) serial infrared physi tional transfer of 8- or 10-bit video data. Additionally, on-chip
cal layer link specification (SIR) protocol. decode of embedded start-of-line (SOL) and start-of-field (SOF)
preamble packets is supported.
PROGRAMMABLE FLAGS (PFx)
General-Purpose Mode Descriptions
The ADSP-BF561 has 48 bidirectional, general-purpose I/O,
programmable flag (PF47–0) pins. Some programmable flag The general-purpose modes of the PPI are intended to suit a
pins are used by peripherals (see Pin Descriptions on Page 17). wide variety of data capture and transmission applications.
When not used as a peripheral pin, each programmable flag can Three distinct submodes are supported:
be individually controlled by manipulation of the flag control, • Input mode – frame syncs and data are inputs into the PPI.
status, and interrupt registers as follows:
• Frame capture mode – frame syncs are outputs from the
• Flag direction control register – Specifies the direction of PPI, but data are inputs.
each individual PFx pin as input or output.
• Output mode – frame syncs and data are outputs from the
• Flag control and status registers – Rather than forcing the PPI.
software to use a read-modify-write process to control the
setting of individual flags, the ADSP-BF561 employs a Input Mode
“write one to set” and “write one to clear” mechanism that Input mode is intended for ADC applications, as well as video
allows any combination of individual flags to be set or communication with hardware signaling. In its simplest form,
cleared in a single instruction, without affecting the level of PPI_FS1 is an external frame sync input that controls when to
any other flags. Two control registers are provided, one read data. The PPI_DELAY MMR allows for a delay (in
register is written-to in order to set flag values, while PPI_CLK cycles) between reception of this frame sync and the
another register is written-to in order to clear flag values. initiation of data reads. The number of input data samples is
Reading the flag status register allows software to interro user programmable and defined by the contents of the
gate the sense of the flags. PPI_COUNT register. The PPI supports 8-bit, and 10-bit
through 16-bit data, and are programmable in the
PPI_CONTROL register.

ADSP-BF561
Frame Capture Mode Table 3. Power Settings
Frame capture mode allows the video source(s) to act as a slave Core System
(e.g., for frame capture). The ADSP-BF561 processors control PLL Clock Clock Core
when to read from the video source(s). PPI_FS1 is an HSYNC Mode/State PLL Bypassed (CCLK) (SCLK) Power
output and PPI_FS2 is a VSYNC output. Full-On Enabled No Enabled Enabled On
Output Mode Active Enabled/ Yes Enabled Enabled On
Disabled
Output mode is used for transmitting video or other data with
up to three output frame syncs. Typically, a single frame sync is Sleep Enabled – Disabled Enabled On
appropriate for data converter applications, whereas two or Deep Sleep Disabled – Disabled Disabled On
three frame syncs could be used for sending video with hard Hibernate Disabled – Disabled Disabled Off
ware signaling.
ITU-R 656 Mode Descriptions Full-On Operating Mode—Maximum Performance
The ITU-R 656 modes of the PPI are intended to suit a wide In the full-on mode, the PLL is enabled and is not bypassed,
variety of video capture, processing, and transmission applica providing capability for maximum operational frequency. This
tions. Three distinct submodes are supported: is the default execution state in which maximum performance
can be achieved. The processor cores and all enabled peripherals
• Active video only mode run at full speed.
• Vertical blanking only mode
Active Operating Mode—Moderate Power Savings
• Entire field mode
In the active mode, the PLL is enabled but bypassed. Because the
Active Video Only Mode PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. In this
Active video only mode is used when only the active video por
mode, the CLKIN to CCLK multiplier ratio can be changed,
tion of a field is of interest and not any of the blanking intervals.
although the changes are not realized until the full-on mode is
The PPI does not read in any data between the end of active
entered. DMA access is available to appropriately configured L1
video (EAV) and start of active video (SAV) preamble symbols,
and L2 memories.
or any data present during the vertical blanking intervals. In this
mode, the control byte sequences are not stored to memory; In the active mode, it is possible to disable the PLL through the
they are filtered by the PPI. After synchronizing to the start of PLL control register (PLL_CTL). If disabled, the PLL must be
Field 1, the PPI ignores incoming samples until it sees an SAV re-enabled before transitioning to the full-on or sleep modes.
code. The user specifies the number of active video lines per
frame (in the PPI_COUNT register). Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces power dissipation by disabling the
Vertical Blanking Interval Mode clock to the processor core (CCLK). The PLL and system clock
In this mode, the PPI only transfers vertical blanking interval (SCLK), however, continue to operate in this mode. Typically an
(VBI) data. external event will wake up the processor. When in the sleep
mode, assertion of wakeup will cause the processor to sense the
Entire Field Mode value of the BYPASS bit in the PLL control register (PLL_CTL).
In this mode, the entire incoming bit stream is read in through When in the sleep mode, system DMA access is only available to
the PPI. This includes active video, control preamble sequences, external memory, not to L1 or on-chip L2 memory.
and ancillary data that may be embedded in horizontal and ver
tical blanking intervals. Data transfer starts immediately after Deep Sleep Operating Mode—Maximum Dynamic Power
synchronization to Field 1. Savings
DYNAMIC POWER MANAGEMENT The deep sleep mode maximizes power savings by disabling the
clocks to the processor cores (CCLK) and to all synchronous
The ADSP-BF561 provides four power management modes and peripherals (SCLK). Asynchronous peripherals will not be able
one power management state, each with a different perfor to access internal resources or external memory. This powered-
mance/power profile. In addition, dynamic power management down mode can only be exited by assertion of the reset pin
provides the control functions to dynamically alter the proces (RESET). If BYPASS is disabled, the processor will transition to
sor core supply voltage, further reducing power dissipation. the full-on mode. If BYPASS is enabled, the processor will tran
Control of clocking to each of the ADSP-BF561 peripherals also sition to the active mode.
reduces power consumption. See Table 3 for a summary of the
power settings for each mode. Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all
the synchronous peripherals (SCLK). The internal voltage

ADSP-BF561
regulator for the processor can be shut off by writing b#00 to the tNOM is the duration running at fCCLKNOM
FREQ bits of the VR_CTL register. This disables both CCLK tRED is the duration running at fCCLKRED
and SCLK. Furthermore, it sets the internal power supply volt
age (VDDINT) to 0 V to provide the lowest static power dissipation. The percent power savings is calculated as:
Any critical information stored internally (memory contents, % power savings = (1 – power savings factor) × 100%
register contents, etc.) must be written to a nonvolatile storage
device prior to removing power if the processor state is to be VOLTAGE REGULATION
preserved. Since VDDEXT is still supplied in this mode, all of the The ADSP-BF561 processor provides an on-chip voltage regula
external pins three-state, unless otherwise specified. This allows tor that can generate appropriate VDDINT voltage levels from the
other devices that may be connected to the processor to have VDDEXT supply. See Operating Conditions on Page 20 for regula
power still applied without drawing unwanted current. The tor tolerances and acceptable VDDEXT ranges for specific models.
internal supply regulator can be woken up by asserting the
RESET pin. Figure 4 shows the typical external components required to
complete the power management system. The regulator con
Power Savings trols the internal logic voltage levels and is programmable with
the voltage regulator control register (VR_CTL) in increments
As shown in Table 4, the ADSP-BF561 supports two different
of 50 mV. To reduce standby power consumption, the internal
power domains. The use of multiple power domains maximizes
voltage regulator can be programmed to remove power to the
flexibility, while maintaining compliance with industry stan
processor core while keeping I/O power (VDDEXT) supplied. While
dards and conventions. By isolating the internal logic of the
in the hibernate state, VDDEXT can still be applied, thus eliminating
ADSP-BF561 into its own power domain, separate from the I/O,
the need for external buffers. The voltage regulator can be acti
the processor can take advantage of Dynamic Power Manage
vated from this power-down state by asserting RESET, which
ment, without affecting the I/O devices. There are no
will then initiate a boot sequence. The regulator can also be dis
sequencing requirements for the various power domains.
abled and bypassed at the user’s discretion.
Table 4. ADSP-BF561 Power Domains The internal voltage regulation feature is not available on any of
the 600 MHz speed grade models or automotive grade models.
Power Domain VDD Range External voltage regulation is required to ensure correct opera
All internal logic VDDINT tion of these parts at 600 MHz.
I/O VDDEXT
VDDEXT
The power dissipated by a processor is largely a function of the (LOW-INDUCTANCE)
SET OF DECOUPLING
CAPACITORS
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25% VDDEXT
+
results in a 25% reduction in dynamic power dissipation, while
100μF
reducing the voltage by 25% reduces dynamic power dissipation
by more than 40%. Further, these power savings are additive, in 100nF 10μH
that if the clock frequency and supply voltage are both reduced, VDDINT
+ +
the power savings can be dramatic. 100μF
FDS9431A
The dynamic power management feature of the ADSP-BF561 100μF
10μF
allows both the processor’s input voltage (VDDINT) and clock fre- LOW ESR ZHCS1000
quency (fCCLK) to be dynamically controlled. VROUT
The savings in power dissipation can be modeled using the

SHORT AND LOW- VROUT
power savings factor and % power savings calculations. INDUCTANCE WIRE
The power savings factor is calculated as: NOTE: DESIGNER SHOULD MINIMIZE
TRACE LENGTH TO FDS9431A. GND
power savings factor
f CCLKRED  V DDINTRED  2  t RED 
- × -------------------------- × -----------
= --------------------
f CCLKNOM  V DDINTNOM  t NOM  Figure 4. Voltage Regulator Circuit
where the variables in the equations are:
Voltage Regulator Layout Guidelines
fCCLKNOM is the nominal core clock frequency
fCCLKRED is the reduced core clock frequency Regulator external component placement, board routing, and
bypass capacitors all have a significant effect on noise injected
VDDINTNOM is the nominal internal supply voltage into the other analog circuits on-chip. The VROUT1–0 traces
VDDINTRED is the reduced internal supply voltage and voltage regulator external components should be consid
ered as noise sources when doing board layout and should not
be routed or placed near sensitive circuits or components on the

ADSP-BF561
board. All internal and I/O power supplies should be well
Blackfin
bypassed with bypass capacitors placed as close to the
CLKOUT
ADSP-BF561 processors as possible. TO PLL CIRCUITRY
For further details on the on-chip voltage regulator and related EN
board design guidelines, see the Switching Regulator Design
Considerations for ADSP-BF533 Blackfin Processors (EE-228)
applications note on the Analog Devices web site (www.ana 700O
log.com)—use site search on “EE-228”.
VDDEXT
CLOCK SIGNALS CLKIN XTAL
The ADSP-BF561 processor can be clocked by an external crys 0O* 1MO

tal, a sine wave input, or a buffered, shaped clock derived from
an external clock oscillator.
18pF* 18pF* FOR OVERTONE
If an external clock is used, it should be a TTL compatible signal OPERATION ONLY
and must not be halted, changed, or operated below the speci
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED
DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE
clock is used, the XTAL pin must be left unconnected. ANALYZE CAREFULLY.
Alternatively, because the ADSP-BF561 processor includes an Figure 5. External Crystal Connections
on-chip oscillator circuit, an external crystal may be used. For
fundamental frequency operation, use the circuit shown in
Figure 5. A parallel-resonant, fundamental frequency, micro
processor-grade crystal is connected across the CLKIN and “FINE” ADJUSTMENT “COARSE” ADJUSTMENT
REQUIRES PLL SEQUENCING ON-THE-FLY
XTAL pins. The on-chip resistance between CLKIN and the
XTAL pin is in the 500 kΩ range. Further parallel resistors are
typically not recommended. The two capacitors and the series
resistor shown in Figure 5 fine tune the phase and amplitude of ÷ 1, 2, 4, 8 CCLK
the sine frequency. The capacitor and resistor values shown in CLKIN
PLL
0.5u to 64u
Figure 5 are typical values only. The capacitor values are depen VCO
dent upon the crystal manufacturer’s load capacitance ÷ 1 to 15 SCLK
recommendations and the physical PCB layout. The resistor

value depends on the drive level specified by the crystal manu
facturer. System designs should verify the customized values SCLK d CCLK
based on careful investigation on multiple devices over the SCLK d 133 MHz
allowed temperature range.
A third-overtone crystal can be used at frequencies above Figure 6. Frequency Modification Methods
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as into the SSEL fields define a divide ratio between the PLL output
shown in Figure 5. (VCO) and the system clock. SCLK divider values are 1 through
15. Table 5 illustrates typical system clock ratios.
As shown in Figure 6, the core clock (CCLK) and system
peripheral clock (SCLK) are derived from the input clock Table 5. Example System Clock Ratios
(CLKIN) signal. An on-chip PLL is capable of multiplying the
CLKIN signal by a user-programmable 0.5× to 64× multiplica Example Frequency
tion factor. The default multiplier is 10×, but it can be modified Signal Name Divider Ratio Ratios (MHz)
by a software instruction sequence. On the fly frequency SSEL3–0 VCO/SCLK VCO SCLK
changes can be effected by simply writing to the PLL_DIV 0001 1:1 100 100
register. 0110 6:1 300 50
All on-chip peripherals are clocked by the system clock (SCLK). 1010 10:1 500 50
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
The maximum frequency of the system clock is fSCLK. Note that
the divisor ratio must be chosen to limit the system clock fre
quency to its maximum of fSCLK. The SSEL value can be changed
dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).

ADSP-BF561
The core clock (CCLK) frequency can also be dynamically All configuration settings are set for the slowest device pos
changed by means of the CSEL1–0 bits of the PLL_DIV register. sible (3-cycle hold time; 15-cycle R/W access times; 4-cycle
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in setup).
Table 6. This programmable core clock capability is useful for • Boot from SPI host device – The Blackfin processor oper
fast core frequency modifications. ates in SPI slave mode and is configured to receive the bytes
of the .LDR file from an SPI host (master) agent. To hold
Table 6. Core Clock Ratios off the host device from transmitting while the boot ROM
Example Frequency is busy, the Blackfin processor asserts a GPIO pin, called
Signal Name Divider Ratio Ratios (MHz) host wait (HWAIT), to signal the host device not to send
CSEL1–0 VCO/CCLK VCO CCLK any more bytes until the flag is deasserted. The flag is cho
sen by the user and this information is transferred to the
00 1:1 500 500
Blackfin processor via bits 10:5 of the FLAG header.
01 2:1 500 250
• Boot from SPI serial EEPROM (16-, 24-bit addressable) –
10 4:1 200 50 The SPI uses the PF2 output pin to select a single SPI
11 8:1 200 25 EPROM device, submits a read command at address
0x0000, and begins clocking data into the beginning of L1
The maximum PLL clock time when a change is programmed instruction memory. A 16-, 24-bit addressable SPI-compat
via the PLL_CTL register is 40 μs. The maximum time to change ible EPROM must be used.
the internal voltage via the internal voltage regulator is also For each of the boot modes, a boot loading protocol is used to
40 μs. The reset value for the PLL_LOCKCNT register is 0x200. transfer program and data blocks from an external memory
This value should be programmed to ensure a 40 μs wakeup device to their specified memory locations. Multiple memory
time when either the voltage is changed or a new MSEL value is blocks may be loaded by any boot sequence. Once all blocks are
programmed. The value should be programmed to ensure an loaded, Core A program execution commences from the start of
80 μs wakeup time when both voltage and the MSEL value are L1 instruction SRAM (0xFFA0 0000). Core B remains in a held-
changed. The time base for the PLL_LOCKCNT register is the off state until Bit 5 of SICA_SYSCR is cleared by Core A. After
period of CLKIN. that, Core B will start execution at address 0xFF60 0000.
BOOTING MODES In addition, Bit 4 of the reset configuration register can be set by
application code to bypass the normal boot sequence during a
The ADSP-BF561 has three mechanisms (listed in Table 7) for
software reset. For this case, the processor jumps directly to the
automatically loading internal L1 instruction memory, L2, or
beginning of L1 instruction memory.
external memory after a reset. A fourth mode is provided to exe
cute from external memory, bypassing the boot sequence. INSTRUCTION SET DESCRIPTION
Table 7. Booting Modes The Blackfin processor family assembly language instruction set
employs an algebraic syntax that was designed for ease of coding
BMODE1 –0 Description and readability. The instructions have been specifically tuned to
00 Execute from 16-bit external memory provide a flexible, densely encoded instruction set that compiles
(Bypass Boot ROM) to a very small final memory size. The instruction set also pro
01 Boot from 8-bit/16-bit flash vides fully featured multifunction instructions that allow the
programmer to use many of the processor core resources in a
10 Boot from SPI host slave mode
single instruction. Coupled with many features more often seen
11 Boot from SPI serial EEPROM on microcontrollers, this instruction set is very efficient when
(16-, 24-bit address range) compiling C and C++ source code. In addition, the architecture
supports both a user (algorithm/application code) and a super
The BMODE pins of the reset configuration register, sampled visor (O/S kernel, device drivers, debuggers, ISRs) mode of
during power-on resets and software initiated resets, implement operation—allowing multiple levels of access to core processor
the following modes: resources.
• Execute from 16-bit external memory – Execution starts The assembly language, which takes advantage of the proces
from address 0x2000 0000 with 16-bit packing. The boot sor’s unique architecture, offers the following advantages:
ROM is bypassed in this mode. All configuration settings • Seamlessly integrated DSP/CPU features are optimized for
are set for the slowest device possible (3-cycle hold time, both 8-bit and 16-bit operations.
15-cycle R/W access times, 4-cycle setup). Note that, in
bypass mode, only Core A can execute instructions from • A multi-issue load/store modified Harvard architecture,
external memory. which supports two 16-bit MAC or four 8-bit ALU plus
two load/store plus two pointer updates per cycle.
• Boot from 8-bit/16-bit external flash memory – The
8-bit/16-bit flash boot routine located in boot ROM mem
ory space is set up using Asynchronous Memory Bank 0.

ADSP-BF561
• All registers, I/O, and memory are mapped into a unified • Set conditional breakpoints on registers, memory, and
4G byte memory space providing a simplified program stacks.
ming model. • Trace instruction execution.
• Microcontroller features, such as arbitrary bit and bit-field • Perform linear or statistical profiling of program execution.
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data types; and separate user and ker • Fill, dump, and graphically plot the contents of memory.
nel stack pointers. • Perform source level debugging.
• Code density enhancements, which include intermixing of • Create custom debugger windows.
16-bit and 32-bit instructions (no mode switching, no code
The VisualDSP++ IDE lets programmers define and manage
segregation). Frequently used instructions are encoded as
software development. Its dialog boxes and property pages let
16-bits.
programmers configure and manage all development tools,
DEVELOPMENT TOOLS including color syntax highlighting in the VisualDSP++ editor.
These capabilities permit programmers to:
The ADSP-BF561 is supported with a complete set of
CROSSCORE®† software and hardware development tools, • Control how the development tools process inputs and
including Analog Devices emulators and the VisualDSP++®‡ generate outputs.
development environment. The same emulator hardware that • Maintain a one-to-one correspondence with the tool’s
supports other Analog Devices processors also fully emulates command line switches.
the ADSP-BF561. The VisualDSP++ Kernel (VDK) incorporates scheduling and
The VisualDSP++ project management environment lets pro resource management tailored specifically to address the mem
grammers develop and debug an application. This environment ory and timing constraints of embedded, real-time
includes an easy to use assembler that is based on an algebraic programming. These capabilities enable engineers to develop
syntax, an archiver (librarian/library builder), a linker, a loader, code more effectively, eliminating the need to start from the
a cycle-accurate instruction-level simulator, a C/C++ compiler, very beginning when developing new application code. The
and a C/C++ runtime library that includes DSP and mathemati VDK features include threads, critical and unscheduled regions,
cal functions. A key point for these tools is C/C++ code semaphores, events, and device flags. The VDK also supports
efficiency. The compiler has been developed for efficient trans priority-based, pre-emptive, cooperative, and time-sliced
lation of C/C++ code to Blackfin assembly. The Blackfin scheduling approaches. In addition, the VDK was designed to
processor has architectural features that improve the efficiency be scalable. If the application does not use a specific feature, the
of compiled C/C++ code. support code for that feature is excluded from the target system.
The VisualDSP++ debugger has a number of important fea Because the VDK is a library, a developer can decide whether to
tures. Data visualization is enhanced by a plotting package that use it or not. The VDK is integrated into the VisualDSP++
offers a significant level of flexibility. This graphical representa development environment, but can also be used with standard
tion of user data enables the programmer to quickly determine command line tools. When the VDK is used, the development
the performance of an algorithm. As algorithms grow in com environment assists the developer with many error prone tasks
plexity, this capability can have increasing significance on the and assists in managing system resources, automating the
designer’s development schedule, increasing productivity. Sta generation of various VDK-based objects, and visualizing the
tistical profiling enables the programmer to nonintrusively poll system state when debugging an application that uses the VDK.
the processor as it is running the program. This feature, unique The Expert Linker can be used to visually manipulate the place
to VisualDSP++, enables the software developer to passively ment of code and data in the embedded system. Memory
gather important code execution metrics without interrupting utilization can be viewed in a color-coded graphical form. Code
the real-time characteristics of the program. Essentially, the and data can be easily moved to different areas of the processor
developer can identify bottlenecks in software quickly and effi or external memory with the drag of the mouse. Runtime stack
ciently. By using the profiler, the programmer can focus on and heap usage can be examined. The Expert Linker is fully
those areas in the program that impact performance and take compatible with existing Linker Definition File (LDF), allowing
corrective action. the developer to move between the graphical and textual
Debugging both C/C++ and assembly programs with the environments.
VisualDSP++ debugger, programmers can: Analog Devices emulators use the IEEE 1149.1 JTAG test access
• View mixed C/C++ and assembly code (interleaved source port of the ADSP-BF561 to monitor and control the target
and object information). board processor during emulation. The emulator provides full-
• Insert breakpoints. speed emulation, allowing inspection and modification of mem
ory, registers, and processor stacks. Nonintrusive in-circuit
emulation is assured by the use of the processor’s JTAG inter-
face—the emulator does not affect the loading or timing of the
target system.
†
CROSSCORE is a registered trademark of Analog Devices, Inc.
‡
VisualDSP++ is a registered trademark of Analog Devices, Inc.

ADSP-BF561
In addition to the software and hardware development tools RELATED DOCUMENTS
available from Analog Devices, third parties provide a wide
The following publications that describe the ADSP-BF561 pro
range of tools supporting the Blackfin processor family. Third
cessors (and related processors) can be ordered from any
party software tools include DSP libraries, real-time operating
Analog Devices sales office or accessed electronically on our
systems, and block diagram design tools.
website:
EZ-KIT Lite Evaluation Board • Getting Started With Blackfin Processors
For evaluation of ADSP-BF561 processors, use the • ADSP-BF561 Blackfin Processor Hardware Reference
ADSP-BF561 EZ-KIT Lite® board available from Analog
• ADSP-BF53x/BF56x Blackfin Processor Programming
Devices. Order part number ADDS-BF561-EZLITE. The board
Reference
comes with on-chip emulation capabilities and is equipped to
enable software development. Multiple daughter cards are • ADSP-BF561 Blackfin Processor Anomaly List
available.
DESIGNING AN EMULATOR-COMPATIBLE
PROCESSOR BOARD
The Analog Devices family of emulators are tools that every sys
tem developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on the ADSP-BF561. The emulator uses
the TAP to access the internal features of the processor, allow
ing the developer to load code, set breakpoints, observe
variables, observe memory, and examine registers. The proces
sor must be halted to send data and commands, but once an
operation has been completed by the emulator, the processor is
set running at full speed with no impact on system timing.
To use these emulators, the target board must include a header
that connects the processor’s JTAG port to the emulator.
For details on target board design issues, including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see Analog Devices JTAG Emulation Technical Reference
(EE-68) on the Analog Devices website (www.analog.com)—use
site search on “EE-68.” This document is updated regularly to
keep pace with improvements to emulator support.

ADSP-BF561
PIN DESCRIPTIONS
ADSP-BF561 pin definitions are listed in Table 8. In order to all driven high, with the exception of CLKOUT, which toggles at
maintain maximum function and reduce package size and pin the system clock rate. However if BR is active, the memory pins
count, some pins have multiple functions. In cases where pin are also three-stated.
function is reconfigurable, the default state is shown in plain All I/O pins have their input buffers disabled, with the exception
text, while alternate functionality is shown in italics. of the pins that need pull-ups or pull-downs if unused, as noted
All pins are three-stated during and immediately after reset, in Table 8.
except the external memory interface, asynchronous memory
control, and synchronous memory control pins. These pins are
Table 8. Pin Descriptions

Driver
Pin Name Type Function Type1
EBIU
ADDR25–2 O Address Bus for Async/Sync Access A
DATA31–0 I/O Data Bus for Async/Sync Access A
ABE3–0/SDQM3–0 O Byte Enables/Data Masks for Async/Sync Access A
BR I Bus Request (This pin should be pulled HIGH if not used.)
BG O Bus Grant A
BGH O Bus Grant Hang A
EBIU (ASYNC)
AMS3–0 O Bank Select A
ARDY I Hardware Ready Control (This pin should be pulled HIGH if not used.)
AOE O Output Enable A
AWE O Write Enable A
ARE O Read Enable A
EBIU (SDRAM)
SRAS O Row Address Strobe A
SCAS O Column Address Strobe A
SWE O Write Enable A
SCKE O Clock Enable A
SCLK0/CLKOUT O Clock Output Pin 0 B
SCLK1 O Clock Output Pin 1 B
SA10 O SDRAM A10 Pin A
SMS3–0 O Bank Select A

ADSP-BF561
Table 8. Pin Descriptions (Continued)
Driver
PF/SPI/TIMER
PF0/SPISS/TMR0 I/O Programmable Flag/Slave SPI Select/Timer C
PF1/SPISEL1/TMR1 I/O Programmable Flag/SPI Select/Timer C
PF8 I/O Programmable Flag C
PF15/EXT CLK I/O Programmable Flag/External Timer Clock Input C
PPI0
PPI0D15–8/PF47–40 I/O PPI Data/Programmable Flag Pins C
PPI0D7–0 I/O PPI Data Pins C
PPI0CLK I PPI Clock
PPI0SYNC1/TMR8 I/O PPI Sync/Timer C
PPI0SYNC3 I/O PPI Sync C
PPI1
PPI1D15–8/PF39–32 I/O PPI Data/Programmable Flag Pins C
PPI1D7–0 I/O PPI Data Pins C
PPI1CLK I PPI Clock
PPI1SYNC3 I/O PPI Sync C
SPORT0
RSCLK0/PF28 I/O Sport0 Receive Serial Clock/Programmable Flag D
RFS0/PF19 I/O Sport0 Receive Frame Sync/Programmable Flag C
DR0PRI I Sport0 Receive Data Primary
DR0SEC/PF20 I/O Sport0 Receive Data Secondary/Programmable Flag C
TSCLK0/PF29 I/O Sport0 Transmit Serial Clock/Programmable Flag D
TFS0/PF16 I/O Sport0 Transmit Frame Sync/Programmable Flag C
DT0PRI/PF18 I/O Sport0 Transmit Data Primary/Programmable Flag C
DT0SEC/PF17 I/O Sport0 Transmit Data Secondary/Programmable Flag C

ADSP-BF561
Table 8. Pin Descriptions (Continued)
Driver
SPORT1
RSCLK1/PF30 I/O Sport1 Receive Serial Clock/Programmable Flag D
RFS1/PF24 I/O Sport1 Receive Frame Sync/Programmable Flag C
DR1PRI I Sport1 Receive Data Primary
DR1SEC/PF25 I/O Sport1 Receive Data Secondary/Programmable Flag C
TSCLK1/PF31 I/O Sport1 Transmit Serial Clock/Programmable Flag D
TFS1/PF21 I/O Sport1 Transmit Frame Sync/Programmable Flag C
DT1PRI/PF23 I/O Sport1 Transmit Data Primary/Programmable Flag C
DT1SEC/PF22 I/O Sport1 Transmit Data Secondary/Programmable Flag C
SPI
MOSI I/O Master Out Slave In C
MISO I/O Master In Slave Out (This pin should be pulled HIGH through a 4.7 kΩ resistor if booting via the SPI C
port.)
SCK I/O SPI Clock D
UART
RX/PF27 I/O UART Receive/Programmable Flag C
TX/PF26 I/O UART Transmit/Programmable Flag C
JTAG
EMU O Emulation Output C
TCK I JTAG Clock
TDO O JTAG Serial Data Out C
TDI I JTAG Serial Data In
TMS I JTAG Mode Select
TRST I JTAG Reset (This pin should be pulled LOW if JTAG is not used.)
Clock
CLKIN I Clock/Crystal Input (This pin needs to be at a level or clocking.)
XTAL O Crystal Connection
Mode Controls
RESET I Reset (This pin is always active during core power-on.)
NMI0 I Nonmaskable Interrupt Core A (This pin should be pulled LOW when not used.)
NMI1 I Nonmaskable Interrupt Core B (This pin should be pulled LOW when not used.)
BMODE1–0 I Boot Mode Strap (These pins must be pulled to the state required for the desired boot mode.)
SLEEP O Sleep C
BYPASS I PLL BYPASS Control (Pull-up or pull-down Required.)
Voltage Regulator
VROUT1–0 O External FET Drive
Supplies
VDDEXT P Power Supply
VDDINT P Power Supply
GND G Power Supply Return
No Connection NC NC
1
Refer to Figure 30 on Page 41 to Figure 34 on Page 42.

ADSP-BF561
SPECIFICATIONS
Component specifications are subject to change without notice.
OPERATING CONDITIONS
Parameter Conditions Min Nominal Max Unit

VDDINT Internal Supply Voltage1 Non automotive 500 MHz and 533 MHz speed grade models2 0.8 1.25 1.375 V
VDDINT Internal Supply Voltage3 600 MHz speed grade models2 0.8 1.35 1.4185 V
VDDINT Internal Supply Voltage3 Automotive grade models2 0.95 1.25 1.375 V
VDDEXT External Supply Voltage Non automotive grade models2 2.25 2.5, or 3.3 3.6 V
VDDEXT External Supply Voltage Automotive grade models2 2.7 3.3 3.6 V
VIH High Level Input Voltage4, 5 2.0 3.6 V
VIL Low Level Input Voltage5 –0.3 +0.6 V
TJ Junction Temperature 256-Ball CSP_BGA (12 mm × 12 mm) @ TAMBIENT = 0°C to +70°C 0 +105 °C
TJ Junction Temperature 256-Ball CSP_BGA (17 mm × 17 mm) @ TAMBIENT = 0°C to +70°C 0 +95 °C
TJ Junction Temperature 256-Ball CSP_BGA (17 mm × 17 mm) @ TAMBIENT =–40°C to +85°C –40 +115 °C
TJ Junction Temperature 297-Ball PBGA @ TAMBIENT = 0°C to +70°C 0 +95 °C
TJ Junction Temperature 297-Ball PBGA @ TAMBIENT = –40°C to +85°C –40 +115 °C
1
Internal voltage (VDDINT) regulator tolerance is –5% to +10% for all models.
2
See Ordering Guide on Page 63.
3
The internal voltage regulation feature is not available. External voltage regulation is required to ensure correct operation.
4
The ADSP-BF561 is 3.3 V tolerant (always accepts up to 3.6 V maximum VIH), but voltage compliance (on outputs, VOH) depends on the input VDDEXT, because VOH (maximum)
approximately equals VDDEXT (maximum). This 3.3 V tolerance applies to bidirectional and input only pins.
5
Applies to all signal pins.
Table 9 and Table 10 describe the timing requirements for the (VCO) operating frequencies, as described in Absolute Maxi
ADSP-BF561 clocks (tCCLK = 1/fCCLK). Take care in selecting mum Ratings on Page 22. Table 11 describes phase-locked loop
MSEL, SSEL, and CSEL ratios so as not to exceed the maximum operating conditions.
core clock, system clock, and Voltage Controlled Oscillator
Table 9. Core Clock (CCLK) Requirements—500 MHz and 533 MHz Speed Grade Models1
Parameter Max Unit
fCCLK CCLK Frequency (VDDINT = 1.235 Vminimum)2 533 MHz
fCCLK CCLK Frequency (VDDINT = 1.1875 Vminimum) 500 MHz
fCCLK CCLK Frequency (VDDINT = 0.855 Vminimum)3 300 MHz
fCCLK CCLK Frequency (VDDINT = 0.8 V minimum)3 250 MHz
1
2
External Voltage regulation is required on automotive grade models (see Ordering Guide on Page 63) to ensure correct operation.
3
Not applicable to automotive grade models. See Ordering Guide on Page 63.
Table 10. Core Clock (CCLK) Requirements—600 MHz Speed Grade Models1
Parameter Max Unit
fCCLK CCLK Frequency (VDDINT = 1.2825 V minimum)2 600 MHz
fCCLK CCLK Frequency (VDDINT = 1.235 V minimum) 533 MHz
1
2
External voltage regulator required to ensure proper operation at 600 MHz.

ADSP-BF561
Table 11. Phase-Locked Loop Operating Conditions
Parameter Min Max Unit
Voltage Controlled Oscillator (VCO) Frequency 50 Maximum fCCLK MHz
Table 12. System Clock (SCLK) Requirements

Parameter1 Max VDDEXT = 2.5V/3.3V Unit
fSCLK CLKOUT/SCLK Frequency (VDDINT ≥ 1.14 V) 1332 MHz
fSCLK CLKOUT/SCLK Frequency (VDDINT < 1.14 V) 100 MHz
1
tSCLK (= 1/fSCLK) must be greater than or equal to tCCLK.
2
Rounded number. Guaranteed to tSCLK = 7.5 ns. See Table 20 on Page 26.
ELECTRICAL CHARACTERISTICS
Parameter Test Conditions Min Typical Max Unit

VOH High Level Output Voltage1 VDDEXT = 3.0 V, IOH = –0.5 mA 2.4 V
VOL Low Level Output Voltage1 VDDEXT = 3.0 V, IOL = 2.0 mA 0.4 V
IIH High Level Input Current2 VDDEXT = Maximum, VIN = VDD Maximum 10.0 μA
IIHP High Level Input Current JTAG3 VDDEXT = Maximum, VIN = VDD Maximum 50.0 μA
IIL4 Low Level Input Current2 VDDEXT = Maximum, VIN = 0 V 10.0 μA
IOZH Three-State Leakage Current5 VDDEXT = Maximum, VIN = VDD Maximum 10.0 μA
IOZL4 Three-State Leakage Current5 VDDEXT = Maximum, VIN = 0 V 10.0 μA
CIN Input Capacitance6 fIN = 1 MHz, TAMBIENT = 25°C, VIN = 2.5 V 4 87 pF
IDDHIBERNATE8 VDDEXT Current in Hibernate Mode CLKIN=0 MHz, VDDEXT = 3.65 V with Voltage Regulator Off 50 μA
(VDDINT = 0 V)
IDDDEEPSLEEP9 VDDINT Current in Deep Sleep Mode VDDINT = 0.8 V, TJUNCTION = 25°C 70 mA
IDD_TYP9, 10 VDDINT Current VDDINT = 0.8 V, fCCLK = 50 MHz, TJUNCTION = 25°C 127 mA
1
Applies to output and bidirectional pins.
2
Applies to input pins except JTAG inputs.
3
Applies to JTAG input pins (TCK, TDI, TMS, TRST).
4
Absolute value.
5
Applies to three-statable pins.
6
Applies to all signal pins.
7
Guaranteed, but not tested.
8
CLKIN must be tied to VDDEXT or GND during hibernate.
9
Maximum current drawn. See Estimating Power for ADSP-BF561 Blackfin Processors (EE-293) on the Analog Devices website (www.analog.com)—use site search on “EE-293”.
10
Both cores executing 75% dual MAC, 25% ADD instructions with moderate data bus activity.
System designers should refer to Estimating Power for the

ADSP-BF561 (EE-293), which provides detailed information for
optimizing designs for lowest power. All topics discussed in this
section are described in detail in EE-293. Total power dissipa
tion has two components:
1. Static, including leakage current
2. Dynamic, due to transistor switching characteristics
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and pro
cessor activity. Electrical Characteristics on Page 21 shows the
current dissipation for internal circuitry (VDDINT).

ADSP-BF561
ABSOLUTE MAXIMUM RATINGS PACKAGE INFORMATION
Stresses greater than those listed in Table 13 may cause perma The information presented in Figure 7 and Table 15 provides
nent damage to the device. These are stress ratings only. details about the package branding for the Blackfin processors.
Functional operation of the device at these or any other condi For a complete listing of product availability, see the Ordering
tions greater than those indicated in the operational sections of Guide on Page 63.
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Table 13. Absolute Maximum Ratings a

ADSP-BF561
Parameter Value
tppZccc
Internal (Core) Supply Voltage (VDDINT) –0.3 V to +1.42 V
vvvvvv.x n.n
External (I/O) Supply Voltage (VDDEXT) –0.5 V to +3.8 V
yyww country_of_origin
Input Voltage1 –0.5 V to +3.8 V
Output Voltage Swing –0.5 V to VDDEXT + 0.5 V B
Load Capacitance2 200 pF
Storage Temperature Range –65°C to +150°C Figure 7. Product Information on Package
Junction Temperature Under Bias 125°C
Table 15. Package Brand Information
1
Applies to 100% transient duty cycle. For other duty cycles see Table 14.
2
For proper SDRAM controller operation, the maximum load capacitance is 50 pF Brand Key Field Description
(at 3.3 V) or 30 pF (at 2.5 V) for ADDR19–1, DATA15–0, ABE1–0/SDQM1–0, t Temperature Range
CLKOUT, SCKE, SA10, SRAS, SCAS, SWE, and SMS.
pp Package Type
Table 14. Maximum Duty Cycle for Input Transient Voltage1 Z RoHS Compliant Part
ccc See Ordering Guide
VIN Min (V) VIN Max (V)2 Maximum Duty Cycle
–0.50 3.80 100% vvvvvv.x Assembly Lot Code
–0.70 4.00 40% n.n Silicon Revision
–0.80 4.10 25% yyww Date Code
–0.90 4.20 15%
–1.00 4.30 10%
ESD SENSITIVITY
1
Applies to all signal pins with the exception of CLKIN, XTAL, VROUT1–0.
2
Only one of the listed options can apply to a particular design.
ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.

ADSP-BF561
TIMING SPECIFICATIONS
Clock and Reset Timing
Table 16 and Figure 8 describe clock and reset operations. Per
Absolute Maximum Ratings on Page 22, combinations of
CLKIN and clock multipliers must not result in core/system
clocks exceeding the maximum limits allowed for the processor,
including system clock restrictions related to supply voltage.
Table 16. Clock and Normal Reset Timing

Timing Requirements
tCKIN CLKIN (to PLL) Period1, 2, 3 25.0 100.0 ns
tCKINL CLKIN Low Pulse 10.0 ns
tCKINH CLKIN High Pulse 10.0 ns
tWRST RESET Asserted Pulse Width Low4 11 × tCKIN ns
1
If DF bit in PLL_CTL register is set tCLKIN is divided by two before going to PLL, then the tCLKIN maximum period is 50 ns and the tCLKIN minimum period is 12.5 ns.
2
Applies to PLL bypass mode and PLL nonbypass mode.
3
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 9 on Page 20 through Table 12
on Page 21.
4
Applies after power-up sequence is complete. See Table 17 and Figure 9 for power-up reset timing.
tCKIN
CLKIN
tCKINL tCKINH
tWRST
RESET
Figure 8. Clock and Normal Reset Timing
Table 17. Power-Up Reset Timing

Timing Requirements
tRST_IN_PWR RESET Deasserted after the VDDINT, VDDEXT, and CLKIN Pins are Stable and Within 3500 × tCKIN μs
Specification
tRST_IN_PWR
RESET
CLKIN,
VDDINT, VDDEXT
Figure 9. Power-Up Reset Timing

ADSP-BF561
Asynchronous Memory Read Cycle Timing
Table 18. Asynchronous Memory Read Cycle Timing

Timing Requirements
tSDAT DATA31 –0 Setup Before CLKOUT 2.1 ns
tHDAT DATA31–0 Hold After CLKOUT 0.8 ns
tSARDY ARDY Setup Before CLKOUT 4.0 ns
tHARDY ARDY Hold After CLKOUT 0.0 ns
Switching Characteristics
tDO Output Delay After CLKOUT1 6.0 ns
tHO Output Hold After CLKOUT 1 0.8 ns
1
Output pins include AMS3–0, ABE3–0, ADDR25–2, AOE, ARE.
1 CYCLE
SETUP PROGRAMMED READ ACCESS ACCESS EXTENDED
2 CYCLES 4 CYCLES 3 CYCLES
CLKOUT
tDO tHO
AMSx
ABE1–0
ABE, ADDRESS
ADDR19–1
AOE
tDO
tHO
ARE
tHARDY
tSARDY tHARDY
ARDY
tSARDY tSDAT
tHDAT
DATA15–0 READ
Figure 10. Asynchronous Memory Read Cycle Timing

ADSP-BF561
Asynchronous Memory Write Cycle Timing
Table 19. Asynchronous Memory Write Cycle Timing

Timing Requirements
tSARDY ARDY Setup Before CLKOUT 4.0 ns
tHARDY ARDY Hold After CLKOUT 0.0 ns
tDDAT DATA31–0 Disable After CLKOUT 6.0 ns
tENDAT DATA31–0 Enable After CLKOUT 1.0 ns
tDO Output Delay After CLKOUT1 6.0 ns
tHO Output Hold After CLKOUT 1 0.8 ns
1
Output pins include AMS3–0, ABE3–0, ADDR25–2, DATA31–0, AOE, AWE.
ACCESS
SETUP PROGRAMMED WRITE EXTENDED HOLD
2 CYCLES ACCESS 2 CYCLES 1 CYCLE 1 CYCLE
CLKOUT
t DO t HO
AMSx
ABE1–0
ABE, ADDRESS
ADDR19–1
tDO
tHO
AWE
t SARDY t HARDY
ARDY
tSARDY
t ENDAT t DDAT
DATA15–0 WRITE DATA
Figure 11. Asynchronous Memory Write Cycle Timing

ADSP-BF561
SDRAM Interface Timing
Table 20. SDRAM Interface Timing

Timing Requirements
tSSDAT DATA Setup Before CLKOUT 1.5 ns
tHSDAT DATA Hold After CLKOUT 0.8 ns
tDCAD Command, ADDR, Data Delay After CLKOUT1 4.0 ns
tHCAD Command, ADDR, Data Hold After CLKOUT1 0.8 ns
tDSDAT Data Disable After CLKOUT 4.0 ns
tENSDAT Data Enable After CLKOUT 1.0 ns
tSCLK CLKOUT Period 7.5 ns
tSCLKH CLKOUT Width High 2.5 ns
tSCLKL CLKOUT Width Low 2.5 ns
1
Command pins include: SRAS, SCAS, SWE, SDQM, SMS3–0, SA10, SCKE.
tSDCLKH
tSDCLK
SDCLK
tSSDAT
tHSDAT tSDCLKL
DATA (IN)
tDCAD tDSDAT
tENSDAT tHCAD
DATA (OUT)
tDCAD
CMND ADDR
(OUT)
tHCAD
Figure 12. SDRAM Interface Timing

ADSP-BF561
External Port Bus Request and Grant Cycle Timing
Table 21 and Figure 13 describe external port bus request and
bus grant operations.
Table 21. External Port Bus Request and Grant Cycle Timing
Parameter1, 2 Min Max Unit
Timing Requirements
tBS BR Asserted to CLKOUT High Setup 4.6 ns
tBH CLKOUT High to BR Deasserted Hold Time 0.0 ns
tSD CLKOUT Low to AMSx, Address and ARE/AWE Disable 4.5 ns
tSE CLKOUT Low to AMSx, Address and ARE/AWE Enable 4.5 ns
tDBG CLKOUT High to BG Asserted Setup 3.6 ns
tEBG CLKOUT High to BG Deasserted Hold Time 3.6 ns
tDBH CLKOUT High to BGH Asserted Setup 3.6 ns
tEBH CLKOUT High to BGH Deasserted Hold Time 3.6 ns
1
These are preliminary timing parameters that are based on worst-case operating conditions.
2
The pad loads for these timing parameters are 20 pF.
CLKOUT
tBS tBH
BR
tSD
tSE
AMSx
tSD
tSE
ADDR19-1
ABE1-0
tSD
tSE
AWE
ARE
tDBG
tEBG
BG
tDBH
tEBH
BGH
Figure 13. External Port Bus Request and Grant Cycle Timing

ADSP-BF561
Parallel Peripheral Interface Timing
Table 22, and Figure 14 through Figure 17 on Page 30, describe If bit 4 of the PLL_CTL register is set, then Figure 18 on Page 30
default Parallel Peripheral Interface operations. and Figure 19 on Page 31 apply.
Table 22. Parallel Peripheral Interface Timing

Timing Requirements
tPCLKW PPIxCLK Width1 5.0 ns
tPCLK PPIxCLK Period1 13.3 ns
tSFSPE External Frame Sync Setup Before PPIxCLK 4.0 ns
tHFSPE External Frame Sync Hold After PPIxCLK 1.0 ns
tSDRPE Receive Data Setup Before PPIxCLK 3.5 ns
tHDRPE Receive Data Hold After PPIxCLK 2.0 ns
tDFSPE Internal Frame Sync Delay After PPIxCLK 8.0 ns
tHOFSPE Internal Frame Sync Hold After PPIxCLK 1.7 ns
tDDTPE Transmit Data Delay After PPIxCLK 8.0 ns
tHDTPE Transmit Data Hold After PPIxCLK 2.0 ns
1
For PPI modes that use an internally generated frame sync, the PPIxCLK frequency cannot exceed fSCLK/2. For modes with no frame syncs or external frame syncs, PPIxCLK
cannot exceed 75 MHz and fSCLK should be equal to or greater than PPIxCLK.
FRAME
SYNC IS DATA0
DRIVEN IS
OUT SAMPLED
POLC = 0
PPIxCLK
PPIxCLK
POLC = 1
tDFSPE
tHOFSPE
POLS = 1
PPIxSYNC1
POLS = 0
POLS = 1
PPIxSYNC2
POLS = 0
tSDRPE tHDRPE
PPIx_DATA
Figure 14. PPI GP Rx Mode with Internal Frame Sync Timing (Default)

ADSP-BF561
FRAME
SYNC IS
SAMPLED
DATA0 IS FOR DATA1 IS
SAMPLED DATA0 SAMPLED
PPIxCLK
POLC = 0
PPIxCLK
POLC = 1
t
HFSPE
tSFSPE
POLS = 1
PPIxSYNC1
POLS = 0
POLS = 1
PPIxSYNC2
POLS = 0
t t
SDRPE HDRPE
PPIx_DATA
Figure 15. PPI GP Rx Mode with External Frame Sync Timing (Default)
FRAME
SYNC IS
DRIVEN DATA0 IS
OUT DRIVEN
OUT
PPIxCLK
POLC = 0
PPIxCLK
POLC = 1
t
DFSPE
tHOFSPE
POLS = 1
PPIxSYNC1
POLS = 0
POLS = 1
PPIxSYNC2
POLS = 0
tDDTPE
tHDTPE
PPIx_DATA DATA0
Figure 16. PPI GP Tx Mode with Internal Frame Sync Timing (Default)

ADSP-BF561
FRAME DATA0 IS
SYNC IS DRIVEN
SAMPLED OUT
PPIxCLK
POLC = 0
PPIxCLK
POLC = 1
tHFSPE
t
SFSPE
POLS = 1
PPxSYNC1
POLS = 0
POLS = 1
PPIxSYNC2
POLS = 0
t
HDTPE
PPIx_DATA DATA0
tDDTPE
Figure 17. PPI GP Tx Mode with External Frame Sync Timing (Default)
DATA DATA
SAMPLING/ SAMPLING/
FRAME FRAME
SYNC SYNC
SAMPLING SAMPLING
EDGE EDGE
PPIxCLK
POLC = 0
PPIxCLK
POLC = 1
tSFSPE t
HFSPE
POLS = 1
PPIxSYNC1
POLS = 0
POLS = 1
PPIxSYNC2
POLS = 0
tSDRPE tHDRPE
PPIx_DATA
Figure 18. PPI GP Rx Mode with External Frame Sync Timing (Bit 4 of PLL_CTL Set)

ADSP-BF561
DATA DATA
DRIVING/ DRIVING/
FRAME FRAME
SYNC SYNC
SAMPLING SAMPLING
EDGE EDGE
PPIxCLK
POLC = 0
PPIxCLK
POLC = 1
t
HFSPE
t
SFSPE
POLS = 1
PPIxSYNC1
POLS = 0
POLS = 1
PPIxSYNC2
POLS = 0
tDDTPE
t
HDTPE
PPIx_DATA
Figure 19. PPI GP Tx Mode with External Frame Sync Timing (Bit 4 of PLL_CTL Set)

ADSP-BF561
Serial Ports
Table 23 through Table 26 on Page 34 and Figure 20 on Page 33
through Figure 22 on Page 34 describe Serial Port operations.
Table 23. Serial Ports—External Clock

Timing Requirements
tSFSE TFSx/RFSx Setup Before TSCLKx/RSCLKx1 3.0 ns
tHFSE TFSx/RFSx Hold After TSCLKx/RSCLKx1 3.0 ns
tSDRE Receive Data Setup Before RSCLKx1 3.0 ns
tHDRE Receive Data Hold After RSCLKx1 3.0 ns
tSCLKW TSCLKx/RSCLKx Width 4.5 ns
tSCLK TSCLKx/RSCLKx Period 15.0 ns
tSUDTE Start-Up Delay From SPORT Enable To First External TFSx 4.0 TSCLKx
tSUDRE Start-Up Delay From SPORT Enable To First External RFSx 4.0 RSCLKx
tDFSE TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 10.0 ns
tHOFSE TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 0.0 ns
tDDTE Transmit Data Delay After TSCLKx2 10.0 ns
tHDTE Transmit Data Hold After TSCLKx2 0.0 ns
1
Referenced to sample edge.
2
Referenced to drive edge.
Table 24. Serial Ports—Internal Clock

Timing Requirements
tSFSI TFSx/RFSx Setup Before TSCLKx/RSCLKx1 8.0 ns
tHFSI TFSx/RFSx Hold After TSCLKx/RSCLKx1 –2.0 ns
tSDRI Receive Data Setup Before RSCLKx1 6.0 ns
tHDRI Receive Data Hold After RSCLKx1 0.0 ns
tSCLKW TSCLKx/RSCLKx Width 4.5 ns
tSCLK TSCLKx/RSCLKx Period 15.0 ns
tDFSI TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 3.0 ns
tHOFSI TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 –1.0 ns
tDDTI Transmit Data Delay After TSCLKx2 3.0 ns
tHDTI Transmit Data Hold After TSCLKx2 –2.0 ns
tSCLKIW TSCLKx/RSCLKx Width 4.5 ns
1
Referenced to sample edge.
2

ADSP-BF561
DATA RECEIVE—INTERNAL CLOCK DATA RECEIVE—EXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE

tSCLKIW tSCLKW
RSCLKx RSCLKx
tDFSIR tDFSE
tHOFSIR tSFSI tHFSI tHOFSE tSFSE tHFSE
RFSx RFSx
tSDRI tHDRI tSDRE tHDRE
DRx DRx
NOTES
1. EITHER THE RISING EDGE OR THE FALLING EDGE OF SCLK (EXTERNAL OR INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT—INTERNAL CLOCK DATA TRANSMIT—EXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE

tSCLKIW tSCLKW
TSCLKx TSCLKx
tDFSI tDFSE
tHOFSI tSFSI tHFSI tHOFSE tSFSE tHFSE
TFSx TFSx
tDDTI tDDTE
tHDTI tHDTE
DTx DTx
Figure 20. Serial Ports
TSCLKx
(INPUT)
tSUDTE
TFSx
(INPUT)
RSCLKx
(INPUT)
tSUDRE
RFSx
(INPUT)
SPORT
ENABLED
Figure 21. Serial Port Start Up with External Clock and Frame Sync

ADSP-BF561
Table 25. Serial Ports—Enable and Three-State
tDTENE Data Enable Delay from External TSCLKx1 0 ns
tDDTTE Data Disable Delay from External TSCLKx1 10.0 ns
tDTENI Data Enable Delay from Internal TSCLKx1 –2.0 ns
tDDTTI Data Disable Delay from Internal TSCLKx1 3.0 ns
1
Table 26. External Late Frame Sync

tDDTLFSE Data Delay from Late External TFSx or External RFSx with MCMEN = 1, MFD = 01, 2 10.0 ns
tDTENLFS Data Enable from Late FS or MCMEN = 1, MFD = 01, 2 0 ns
1
MCMEN = 1, TFSx enable and TFSx valid follow tDTENLFS and tDDTLFSE.
2
If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2, then tDDTTE/I and tDTENE/I apply; otherwise tDDTLFSE and tDTENLFS apply.
EXTERNAL RECEIVE FS WITH MCMEN = 1, MFD = 0
DRIVE SAMPLE DRIVE
RSCLKx
tHFSE/I
tSFSE/I
RFSx
tDDTE/I
tDDTENFS
tHDTE/I
DTx 1ST BIT 2ND BIT
tDDTLFSE
LATE EXTERNAL TRANSMIT FS
DRIVE SAMPLE DRIVE
TSCLKx
tHFSE/I
tSFSE/I
TFSx
tDDTE/I
tDDTENFS
tHDTE/I
DTx 1ST BIT 2ND BIT
tDDTLFSE
Figure 22. External Late Frame Sync

ADSP-BF561
Serial Peripheral Interface (SPI) Port—
Master Timing
Table 27 and Figure 23 describe SPI port master operations.
Table 27. Serial Peripheral Interface (SPI) Port—Master Timing

Timing Requirements
tSSPIDM Data Input Valid to SCK Edge (Data Input Setup) 7.5 ns
tHSPIDM SCK Sampling Edge to Data Input Invalid –1.5 ns
tSDSCIM SPISELx Low to First SCK Edge 2 × tSCLK – 1.5 ns
tSPICHM Serial Clock High Period 2 × tSCLK – 1.5 ns
tSPICLM Serial Clock Low Period 2 × tSCLK – 1.5 ns
tSPICLK Serial Clock Period 4 × tSCLK – 1.5 ns
tHDSM Last SCK Edge to SPISELx High 2 × tSCLK – 1.5 ns
tSPITDM Sequential Transfer Delay 2 × tSCLK – 1.5 ns
tDDSPIDM SCK Edge to Data Out Valid (Data Out Delay) 0 6 ns
tHDSPIDM SCK Edge to Data Out Invalid (Data Out Hold) –1.0 +4.0 ns
FLAG3–0
(OUTPUT)
tSDSCIM tSPICHM tSPICLM

tSPICLKM tHDSM tSPITDM
SPICLK
(CP = 0)
(OUTPUT)
tSPICLM tSPICHM
SPICLK
(CP = 1)
(OUTPUT)
tHDSPIDM
tDDSPIDM
MOSI
(OUTPUT) MSB LSB
tSSPIDM tSSPIDM
CPHASE = 1
tHSPIDM tHSPIDM
MISO MSB
(INPUT) VALID LSB VALID
tDDSPIDM tHDSPIDM
MOSI
(OUTPUT) MSB LSB
tSSPIDM tHSPIDM
CPHASE = 0
MISO
(INPUT) MSB VALID LSB VALID
Figure 23. Serial Peripheral Interface (SPI) Port—Master Timing

ADSP-BF561
Serial Peripheral Interface (SPI) Port—
Slave Timing
Table 28 and Figure 24 describe SPI port slave operations.
Table 28. Serial Peripheral Interface (SPI) Port—Slave Timing

Timing Requirements
tSPICHS Serial Clock High Period 2× tSCLK – 1.5 ns
tSPICLS Serial Clock Low Period 2× tSCLK – 1.5 ns
tSPICLK Serial Clock Period 4× tSCLK ns
tHDS Last SCK Edge to SPISS Not Asserted 2× tSCLK – 1.5 ns
tSPITDS Sequential Transfer Delay 2× tSCLK – 1.5 ns
tSDSCI SPISS Assertion to First SCK Edge 2× tSCLK – 1.5 ns
tSSPID Data Input Valid to SCK Edge (Data Input Setup) 1.6 ns
tHSPID SCK Sampling Edge to Data Input Invalid 1.6 ns
tDSOE SPISS Assertion to Data Out Active 0 8 ns
tDSDHI SPISS Deassertion to Data High Impedance 0 8 ns
tDDSPID SCK Edge to Data Out Valid (Data Out Delay) 0 10 ns
tHDSPID SCK Edge to Data Out Invalid (Data Out Hold) 0 10 ns
SPIDS
(INPUT)
tSPICHS tSPICLS tSPICLKS tHDS tSDPPW

SPICLK
(CP = 0)
(INPUT)
tSPICLS
tSDSCO tSPICHS
SPICLK
(CP = 1)
(INPUT)
tDDSPIDS tDSDHI
tDSOE
tDDSPIDS tHDSPIDS
MISO
(OUTPUT) MSB LSB
CPHASE = 1 tSSPIDS tSSPIDS tHSPIDS
MOSI
tHDSPIDS
tDDSPIDS tDSDHI
MISO
(OUTPUT) MSB LSB
tDSOV
tHSPIDS
CPHASE = 0
tSSPIDS
MOSI
Figure 24. Serial Peripheral Interface (SPI) Port—Slave Timing

ADSP-BF561
Universal Asynchronous Receiver Transmitter (UART)
Port—Receive and Transmit Timing
Figure 25 describes UART port receive and transmit operations.
The maximum baud rate is SCLK/16. As shown in Figure 25,
there is some latency between the generation internal UART
interrupts and the external data operations. These latencies are
negligible at the data transmission rates for the UART.
DPI_P14–1 DATA (5–8)

[RxD] STOP
RECEIVE tRXD
INTERNAL
UART RECEIVE UART RECEIVE BIT SET BY DATA STOP;
INTERRUPT CLEARED BY FIFO READ
START
DPI_P14–1
DATA (5–8) STOP (1–2)
[TxD]
TRANSMIT tTXD
INTERNAL
UART TRANSMIT UART TRANSMIT BIT SET BY PROGRAM;
INTERRUPT CLEARED BY WRITE TO TRANSMIT
Figure 25. UART Port—Receive and Transmit Timing

ADSP-BF561
Programmable Flags Cycle Timing
Table 29 and Figure 26 describe programmable flag operations.
Table 29. Programmable Flags Cycle Timing

Timing Requirement
tWFI Flag Input Pulse Width tSCLK + 1 ns
Switching Characteristic
tDFO Flag Output Delay from CLKOUT Low 6 ns
CLKOUT
tDFO
PFx (OUTPUT)
FLAG OUTPUT
tWFI
PFx (INPUT)
FLAG INPUT
Figure 26. Programmable Flags Cycle Timing

ADSP-BF561
Timer Cycle Timing
Table 30 and Figure 27 describe timer expired operations. The
input signal is asynchronous in width capture mode and exter
nal clock mode and has an absolute maximum input frequency
of fSCLK/2 MHz.
Table 30. Timer Cycle Timing

Timing Characteristics
tWL Timer Pulse Width Input Low1 (Measured in SCLK Cycles) 1 SCLK
tWH Timer Pulse Width Input High1 (Measured in SCLK Cycles) 1 SCLK
Switching Characteristic
tHTO Timer Pulse Width Output2 (Measured in SCLK Cycles) 1 (232–1) SCLK
1
The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPIxCLK input pins in PWM output mode.
2
The minimum time for tHTO is one cycle, and the maximum time for tHTO equals (232–1) cycles.
CLKOUT
tHTO
TMRx
(PWM OUTPUT MODE)
TMRx tWL tWH

(WIDTH CAPTURE AND
EXTERNAL CLOCK MODES)
Figure 27. Timer PWM_OUT Cycle Timing

ADSP-BF561
JTAG Test and Emulation Port Timing
Table 31 and Figure 28 describe JTAG port operations.
Table 31. JTAG Port Timing

Timing Parameters
tTCK TCK Period 20 ns
tSTAP TDI, TMS Setup Before TCK High 4 ns
tHTAP TDI, TMS Hold After TCK High 4 ns
tSSYS System Inputs Setup Before TCK High1 4 ns
tHSYS System Inputs Hold After TCK High1 5 ns
tTRSTW TRST Pulse Width2 (Measured in TCK Cycles) 4 TCK
tDTDO TDO Delay from TCK Low 10 ns
tDSYS System Outputs Delay After TCK Low3 0 12 ns
1
System Inputs= DATA31–0, ARDY, PF47–0, PPI0CLK, PPI1CLK, RSCLK0–1, RFS0–1, DR0PRI, DR0SEC, TSCLK0–1, TFS0–1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RX,
RESET, NMI0, NMI1, BMODE1–0, BR, and PPIxD7–0.
2
50 MHz maximum
3
System Outputs = DATA31–0, ADDR25–2, ABE3–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS3–0, PF47–0, RSCLK0–1, RFS0–1,
TSCLK0–1, TFS0–1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, and PPIxD7–0.
tTCK
TCK
tSTAP tHTAP
TMS
TDI
tDTDO
TDO
tSSYS tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 28. JTAG Port Timing

ADSP-BF561
OUTPUT DRIVE CURRENTS 150
Figure 29 through Figure 36 on Page 42 show typical current VDDEXT = 2.75V
voltage characteristics for the output drivers of the 100 VDDEXT = 2.50V
ADSP-BF561 processor. The curves represent the current drive VDDEXT = 2.25V
SOURCE CURRENT (mA)

capability of the output drivers as a function of output voltage. 50
Refer to Table 8 on Page 17 to identify the driver type for a pin.
0 VOH
150
VDDEXT = 2.75V
–50
VDDEXT = 2.50V
100
VDDEXT = 2.25V
–100
SOURCE CURRENT (mA)
VOL
50
–150
0 0 0.5 1.0 1.5 2.0 2.5 3.0
VOH
SOURCE VOLTAGE (V)
–50
Figure 31. Drive Current B (Low VDDEXT)
VOL
–100
150
VDDEXT = 3.65V
–150
0 0.5 1.0 1.5 2.0 2.5 3.0 VDDEXT = 2.95V
100
VDDEXT = 3.30V
SOURCE VOLTAGE (V)
SOURCE CURRENT (mA)
50
Figure 29. Drive Current A (Low VDDEXT)
0
150 VOH
VDDEXT = 3.65V
VDDEXT = 3.30V –50
100 VDDEXT = 2.95V
–100
SOURCE CURRENT (mA)
50 VOL
–150
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VOH SOURCE VOLTAGE (V)
–50
Figure 32. Drive Current B (High VDDEXT)
–100
VOL
60
–150 VDDEXT = 2.75V
VDDEXT = 2.50V
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 40 VDDEXT = 2.25V
SOURCE VOLTAGE (V)
20
Figure 30. Drive Current A (High VDDEXT)
SOURCE CURRENT (mA)
0
VOH
–20
–40
VOL
–60
0 0.5 1.0 1.5 2.0 2.5 3.0
SOURCE VOLTAGE (V)
Figure 33. Drive Current C (Low VDDEXT)

ADSP-BF561
100 POWER DISSIPATION
80 VDDEXT = 3.65V Many operating conditions can affect power dissipation. System
VDDEXT = 3.30V designers should refer to Estimating Power for ADSP-BF561
60 VDDEXT = 2.95V
Blackfin Processors (EE-293) on the Analog Devices website
40 (www.analog.com)—use site search on “EE-293.” This docu
SOURCE CURRENT (mA)
20
ment provides detailed information for optimizing your design
for lowest power.
0
VOH See the ADSP-BF561 Blackfin Processor Hardware Reference
–20 Manual for definitions of the various operating modes and for
–40 instructions on how to minimize system power.
VOL
–60 TEST CONDITIONS
–80 All timing parameters appearing in this data sheet were mea
–100 sured under the conditions described in this section. Figure 37
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 shows the measurement point for ac measurements (except out-
SOURCE VOLTAGE (V)
put enable/disable). The measurement point VMEAS is 1.5 V for
Figure 34. Drive Current C (High VDDEXT) VDDEXT (nominal) = 2.5 V/3.3 V.
100
VDDEXT = 2.75V
80
VDDEXT = 2.50V INPUT
60 VDDEXT = 2.25V OR VMEAS VMEAS
OUTPUT
SOURCE CURRENT (mA)
40
20
0
VOH
Figure 37. Voltage Reference Levels for AC
–20
Measurements (Except Output Enable/Disable)
–40
Output Enable Time Measurement
–60 VOL
Output pins are considered to be enabled when they have made
–80 a transition from a high impedance state to the point when they
–100 start driving.
0 0.5 1.0 1.5 2.0 2.5 3.0
SOURCE VOLTAGE (V) The output enable time tENA is the interval from the point when a
reference signal reaches a high or low voltage level to the point
Figure 35. Drive Current D (Low VDDEXT)
when the output starts driving as shown on the right side of
Figure 38 on Page 43.
150
The time tENA_MEASURED is the interval, from when the reference sig
VDDEXT = 3.65V
nal switches, to when the output voltage reaches VTRIP(high) or
VDDEXT = 3.30V VTRIP(low). VTRIP(high) is 2.0 V and VTRIP(low) is 1.0 V for VDDEXT
100
VDDEXT = 2.95V (nominal) = 2.5 V/3.3 V. Time tTRIP is the interval from when the
output starts driving to when the output reaches the VTRIP(high)
SOURCE CURRENT (mA)
50
or VTRIP(low) trip voltage.
0
Time tENA is calculated as shown in the equation:
VOH
t ENA = t ENA_MEASURED – t TRIP
–50 If multiple pins (such as the data bus) are enabled, the measure
VOL ment value is that of the first pin to start driving.
–100
Output Disable Time Measurement
–150 Output pins are considered to be disabled when they stop driv
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
ing, go into a high impedance state, and start to decay from their
SOURCE VOLTAGE (V) output high or low voltage. The output disable time tDIS is the
difference between tDIS_MEASURED and tDECAY as shown on the left side
Figure 36. Drive Current D (High VDDEXT) of Figure 38 on Page 43.
t DIS = t DIS_MEASURED – t DECAY

ADSP-BF561
The time for the voltage on the bus to decay by ΔV is dependent 14
on the capacitive load CL and the load current IL. This decay time
RISE AND FALL TIME ns (10% to 90%)

can be approximated by the equation: 12
RISE TIME
t DECAY = (C L ΔV) ⁄ I L 10
FALL TIME
The time tDECAY is calculated with test loads CL and IL, and with 8
ΔV equal to 0.5 V for VDDEXT (nominal) = 2.5 V/3.3 V.

6
The time tDIS_MEASURED is the interval from when the reference sig
nal switches, to when the output voltage decays ΔV from the 4
measured output high or output low voltage.
2
Example System Hold Time Calculation
To determine the data output hold time in a particular system, 0
0 50 100 150 200 250
first calculate tDECAY using the equation given above. Choose ΔV LOAD CAPACITANCE (pF)
to be the difference between the ADSP-BF561 processor’s out
Figure 40. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
put voltage and the input threshold for the device requiring the
for Driver A at VDDEXT (min)
hold time. CL is the total bus capacitance (per data line), and IL is
the total leakage or three-state current (per data line). The hold
12
time will be tDECAY plus the various output disable times as speci

fied in the Timing Specifications on Page 23 (for example tDSDAT
10
for an SDRAM write cycle as shown in SDRAM Interface Tim
RISE TIME
ing on Page 26).
8
FALL TIME
6
REFERENCE
SIGNAL
4
tDIS_MEASURED tENA_MEASURED
tDIS tENA
2
VOH VOH(MEASURED)
(MEASURED) VOH (MEASURED) V VTRIP(HIGH)
0
VOL (MEASURED) + V VTRIP(LOW) 0 50 100 150 200 250
VOL VOL (MEASURED) LOAD CAPACITANCE (pF)
(MEASURED)
tDECAY tTRIP Figure 41. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver A at VDDEXT (max)
OUTPUT STOPS DRIVING OUTPUT STARTS DRIVING

12
HIGH IMPEDANCE STATE
10
Figure 38. Output Enable/Disable
RISE TIME
Capacitive Loading 8
Output delays and holds are based on standard capacitive loads: FALL TIME
6
30 pF on all pins (see Figure 39). VLOAD is 1.5 V for VDDEXT (nomi
nal) = 2.5 V/3.3 V. Figure 40 through Figure 47 on Page 44 show
4
how output rise time varies with capacitance. The delay and
hold specifications given should be derated by a factor derived
from these figures. The graphs in these figures may not be linear 2
outside the ranges shown.
0
0 50 100 150 200 250
TO 50 O
LOAD CAPACITANCE (pF)
OUTPUT VLOAD
PIN Figure 42. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
30pF for Driver B at VDDEXT (min)
Figure 39. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

ADSP-BF561
DDEXT
10 18

9 16
8
14
RISE TIME
RISE TIME
7
12
6
FALL TIME 10
5 FALL TIME
8
4
6
3
4
2
1 2
0 0
0 50 100 150 200 250 0 50 100 150 200 250
LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF)
Figure 43. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance Figure 46. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver B at VDDEXT (max) for Driver D at VDDEXT (min)
30 14

25 12
RISE TIME RISE TIME

10
20
8
15 FALL TIME
FALL TIME
6
10
4
5
2
0 0
0 50 100 150 200 250 0 50 100 150 200 250
LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF)
Figure 44. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance Figure 47. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver C at VDDEXT (min) for Driver D at VDDEXT (max)
20 ENVIRONMENTAL CONDITIONS
18
To determine the junction temperature on the application
16 printed circuit board use:
RISE TIME
14 T J = T CASE + (Ψ JT × P D )
12 where:
FALL TIME
10 TJ = junction temperature (°C).
8 TCASE = case temperature (°C) measured by customer at top
center of package.
6
4
ΨJT = from Table 32 on Page 45 through Table 34 on Page 45.
2
PD = power dissipation (see Power Dissipation on Page 42 for
the method to calculate PD).
0
0 50 100 150 200 250
Values of θJA are provided for package comparison and printed
LOAD CAPACITANCE (pF)
circuit board design considerations. θJA can be used for a first
Figure 45. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance order approximation of TJ by the equation:
for Driver C at VDDEXT (max)
T J = T A + (θ JA × P D )
where:
TA = ambient temperature (°C).

ADSP-BF561
In Table 32 through Table 34, airflow measurements comply
with JEDEC standards JESD51–2 and JESD51–6, and the junc
tion-to-board measurement complies with JESD51–8. The
junction-to-case measurement complies with MIL-STD-883
(Method 1012.1). All measurements use a 2S2P JEDEC test
board.
Thermal resistance θJA in Table 32 through Table 34 is the figure
of merit relating to performance of the package and board in a
convective environment. θJMA represents the thermal resistance
under two conditions of airflow. θJB represents the heat
extracted from the periphery of the board. ΨJT represents the
correlation between TJ and TCASE. Values of θJB are provided for
package comparison and printed circuit board design
considerations.
Table 32. Thermal Characteristics for BC-256-4

(17 mm × 17 mm) Package
Parameter Condition Typical Unit
θJA 0 Linear m/s Airflow 18.1 °C/W
θJMA 1 Linear m/s Airflow 15.9 °C/W
θJC Not Applicable 3.72 °C/W
ΨJT 0 Linear m/s Airflow 0.11 °C/W
Table 33. Thermal Characteristics for BC-256-1

(12 mm × 12 mm) Package
θJB Not Applicable 18.9 °C/W
ΨJT 1 Linear m/s Airflow n/a °C/W
Table 34. Thermal Characteristics for B-297 Package

θJB Not Applicable 16.3 °C/W

ADSP-BF561
256-BALL CSP_BGA (17 mm) BALL ASSIGNMENT
Table 35 lists the 256-Ball CSP_BGA (17 mm × 17 mm) ball
assignment by ball number. Table 36 on Page 48 lists the ball
assignment alphabetically by signal.
Table 35. 256-Ball CSP_BGA (17 mm × 17 mm) Ball Assignment (Numerically by Ball Number)
Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal
A1 VDDEXT C9 SMS3 F1 CLKIN H9 GND L1 PPI0D3
A2 ADDR22 C10 SWE F2 PPI0D10 H10 GND L2 PPI0D2
A3 ADDR18 C11 SA10 F3 RESET H11 GND L3 PPI0D1
A4 ADDR14 C12 ABE0 F4 BYPASS H12 GND L4 PPI0D0
A5 ADDR11 C13 ADDR07 F5 VDDEXT H13 GND L5 VDDEXT
A6 AMS3 C14 ADDR04 F6 VDDEXT H14 DATA21 L6 VDDEXT
A7 AMS0 C15 DATA0 F7 VDDEXT H15 DATA19 L7 VDDEXT
A8 ARDY C16 DATA05 F8 GND H16 DATA23 L8 VDDEXT
A9 SMS2 D1 PPI0D15 F9 GND J1 VROUT1 L9 GND
A10 SCLK0 D2 PPI0SYNC3 F10 VDDEXT J2 PPI0D8 L10 VDDEXT
A11 SCLK1 D3 PPI0SYNC2 F11 VDDEXT J3 PPI0D7 L11 VDDEXT
A12 ABE2 D4 ADDR21 F12 VDDEXT J4 PPI0D9 L12 VDDEXT
A13 ABE3 D5 ADDR15 F13 DATA11 J5 GND L13 NC
A14 ADDR06 D6 ADDR09 F14 DATA08 J6 GND L14 DT0PRI
A15 ADDR03 D7 AWE F15 DATA10 J7 GND L15 DATA31
A16 VDDEXT D8 SMS0 F16 DATA16 J8 GND L16 DATA28
B1 ADDR24 D9 SRAS G1 XTAL J9 GND M1 PPI1SYNC2
B2 ADDR23 D10 SCAS G2 VDDEXT J10 GND M2 PPI1D15
B3 ADDR19 D11 BGH G3 VDDEXT J11 GND M3 PPI1D14
B4 ADDR17 D12 ABE1 G4 GND J12 VDDINT M4 PPI1D9
B5 ADDR12 D13 DATA02 G5 GND J13 VDDINT M5 VDDINT
B6 ADDR10 D14 DATA01 G6 VDDEXT J14 DATA20 M6 VDDINT
B7 AMS1 D15 DATA03 G7 GND J15 DATA22 M7 GND
B8 AOE D16 DATA07 G8 GND J16 DATA24 M8 VDDINT
B9 SMS1 E1 PPI0D11 G9 GND K1 PPI0D6 M9 GND
B10 SCKE E2 PPI0D13 G10 GND K2 PPI0D5 M10 VDDINT
B11 BR E3 PPI0D12 G11 VDDEXT K3 PPI0D4 M11 GND
B12 BG E4 PPI0D14 G12 VDDEXT K4 PPI1SYNC3 M12 VDDINT
B13 ADDR08 E5 PPI1CLK G13 DATA17 K5 VDDEXT M13 RSCLK0
B14 ADDR05 E6 VDDINT G14 DATA14 K6 VDDEXT M14 DR0PRI
B15 ADDR02 E7 GND G15 DATA15 K7 GND M15 TSCLK0
B16 DATA04 E8 VDDINT G16 DATA18 K8 GND M16 DATA29
C1 PPI0SYNC1 E9 GND H1 VROUT0 K9 GND N1 PPI1SYNC1
C2 ADDR25 E10 VDDINT H2 GND K10 GND N2 PPI1D10
C3 PPI0CLK E11 GND H3 GND K11 VDDEXT N3 PPI1D7
C4 ADDR20 E12 VDDINT H4 VDDINT K12 GND N4 PPI1D5
C5 ADDR16 E13 DATA06 H5 VDDINT K13 GND N5 PF0
C6 ADDR13 E14 DATA13 H6 GND K14 DATA26 N6 PF04
C7 AMS2 E15 DATA09 H7 GND K15 DATA25 N7 PF09
C8 ARE E16 DATA12 H8 GND K16 DATA27 N8 PF12

ADSP-BF561
Table 35. 256-Ball CSP_BGA (17 mm × 17 mm) Ball Assignment (Numerically by Ball Number) (Continued)
N9 GND P5 PF01 R1 PPI1D12 R13 RSCLK1 T9 TDO
N10 BMODE1 P6 PF06 R2 PPI1D11 R14 TSCLK1 T10 TDI
N11 BMODE0 P7 PF08 R3 PPI1D4 R15 NC T11 EMU
N12 RX P8 PF15 R4 PPI1D1 R16 TFS0 T12 MISO
N13 DR1SEC P9 NMI1 R5 PF02 T1 VDDEXT T13 TX
N14 DT1SEC P10 TMS R6 PF07 T2 NC T14 DR1PRI
N15 RFS0 P11 NMI0 R7 PF11 T3 PPI1D3 T15 DT1PRI
N16 DATA30 P12 SCK R8 PF14 T4 PPI1D2 T16 VDDEXT
P1 PPI1D13 P13 RFS1 R9 TCK T5 PF03
P2 PPI1D8 P14 TFS1 R10 TRST T6 PF05
P3 PPI1D6 P15 DR0SEC R11 SLEEP T7 PF10
P4 PPI1D0 P16 DT0SEC R12 MOSI T8 PF13

ADSP-BF561
Table 36. 256-Ball CSP_BGA (17 mm × 17 mm) Ball Assignment (Alphabetically by Signal)
Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No.
ABE0 C12 BR B11 DT0SEC P16 GND M9 PPI0D13 E2
ABE1 D12 BYPASS F4 DT1PRI T15 GND M11 PPI0D14 E4
ABE2 A12 CLKIN F1 DT1SEC N14 GND N9 PPI0D15 D1
ABE3 A13 DATA0 C15 EMU T11 MISO T12 PPI0SYNC1 C1
ADDR02 B15 DATA01 D14 GND E7 MOSI R12 PPI0SYNC2 D3
ADDR03 A15 DATA02 D13 GND E9 NC L13 PPI0SYNC3 D2
ADDR04 C14 DATA03 D15 GND E11 NC R15 PPI1CLK E5
ADDR05 B14 DATA04 B16 GND F8 NC T2 PPI1D0 P4
ADDR06 A14 DATA05 C16 GND F9 NMI0 P11 PPI1D1 R4
ADDR07 C13 DATA06 E13 GND G4 NMI1 P9 PPI1D2 T4
ADDR08 B13 DATA07 D16 GND G5 PF0 N5 PPI1D3 T3
ADDR09 D6 DATA08 F14 GND G7 PF01 P5 PPI1D4 R3
ADDR10 B6 DATA09 E15 GND G8 PF02 R5 PPI1D5 N4
ADDR11 A5 DATA10 F15 GND G9 PF03 T5 PPI1D6 P3
ADDR12 B5 DATA11 F13 GND G10 PF04 N6 PPI1D7 N3
ADDR13 C6 DATA12 E16 GND H2 PF05 T6 PPI1D8 P2
ADDR14 A4 DATA13 E14 GND H3 PF06 P6 PPI1D9 M4
ADDR15 D5 DATA14 G14 GND H6 PF07 R6 PPI1D10 N2
ADDR16 C5 DATA15 G15 GND H7 PF08 P7 PPI1D11 R2
ADDR17 B4 DATA16 F16 GND H8 PF09 N7 PPI1D12 R1
ADDR18 A3 DATA17 G13 GND H9 PF10 T7 PPI1D13 P1
ADDR19 B3 DATA18 G16 GND H10 PF11 R7 PPI1D14 M3
ADDR20 C4 DATA19 H15 GND H11 PF12 N8 PPI1D15 M2
ADDR21 D4 DATA20 J14 GND H12 PF13 T8 PPI1SYNC1 N1
ADDR22 A2 DATA21 H14 GND H13 PF14 R8 PPI1SYNC2 M1
ADDR23 B2 DATA22 J15 GND J5 PF15 P8 PPI1SYNC3 K4
ADDR24 B1 DATA23 H16 GND J6 PPI0CLK C3 RESET F3
ADDR25 C2 DATA24 J16 GND J7 PPI0D0 L4 RFS0 N15
AMS0 A7 DATA25 K15 GND J8 PPI0D1 L3 RFS1 P13
AMS1 B7 DATA26 K14 GND J9 PPI0D2 L2 RSCLK0 M13
AMS2 C7 DATA27 K16 GND J10 PPI0D3 L1 RSCLK1 R13
AMS3 A6 DATA28 L16 GND J11 PPI0D4 K3 RX N12
AOE B8 DATA29 M16 GND K7 PPI0D5 K2 SA10 C11
ARDY A8 DATA30 N16 GND K8 PPI0D6 K1 SCAS D10
ARE C8 DATA31 L15 GND K9 PPI0D7 J3 SCK P12
AWE D7 DR0PRI M14 GND K10 PPI0D8 J2 SCKE B10
BG B12 DR0SEC P15 GND K12 PPI0D9 J4 SCLK0 A10
BGH D11 DR1PRI T14 GND K13 PPI0D10 F2 SCLK1 A11
BMODE0 N11 DR1SEC N13 GND L9 PPI0D11 E1 SLEEP R11
BMODE1 N10 DT0PRI L14 GND M7 PPI0D12 E3 SMS0 D8

ADSP-BF561
Table 36. 256-Ball CSP_BGA (17 mm × 17 mm) Ball Assignment (Alphabetically by Signal) (Continued)
Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No.
SMS1 B9 TSCLK0 M15 VDDEXT G3 VDDEXT L11 VDDINT M5
SMS2 A9 TSCLK1 R14 VDDEXT G6 VDDEXT L12 VDDINT M6
SMS3 C9 TX T13 VDDEXT G11 VDDEXT T1 VDDINT M8
SRAS D9 VDDEXT A1 VDDEXT G12 VDDEXT T16 VDDINT M10
SWE C10 VDDEXT A16 VDDEXT K5 VDDINT E6 VDDINT M12
TCK R9 VDDEXT F5 VDDEXT K6 VDDINT E8 VROUT0 H1
TDI T10 VDDEXT F6 VDDEXT K11 VDDINT E10 VROUT1 J1
TDO T9 VDDEXT F7 VDDEXT L5 VDDINT E12 XTAL G1
TFS0 R16 VDDEXT F10 VDDEXT L6 VDDINT H4
TFS1 P14 VDDEXT F11 VDDEXT L7 VDDINT H5
TMS P10 VDDEXT F12 VDDEXT L8 VDDINT J12
TRST R10 VDDEXT G2 VDDEXT L10 VDDINT J13

ADSP-BF561
Figure 48 lists the top view of the 256-Ball CSP_BGA
(17 mm × 17 mm) ball configuration. Figure 49 lists the bottom
view.
A1 BALL
PAD CORNER
A
KEY:
B
VDDINT GND NC
C
VDDEXT I/O VROUT
D
R
T
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TOP VIEW
Figure 48. 256-Ball CSP_BGA Ball Configuration (Top View)
A1 BALL
PAD CORNER
B KEY:
VDDINT GND NC
C
VDDEXT I/O VROUT
D
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
BOTTOM VIEW
Figure 49. 256-Ball CSP_BGA Ball Configuration (Bottom View)

ADSP-BF561
256-BALL CSP_BGA (12 mm) BALL ASSIGNMENT
Table 37 lists the 256-Ball CSP_BGA (12 mm × 12 mm) ball
assignment by ball number. Table 38 on Page 53 lists the ball
assignment alphabetically by signal.
Table 37. 256-Ball CSP_BGA (12 mm × 12 mm) Ball Assignment (Numerically by Ball Number)
A01 VDDEXT C09 SMS2 F01 CLKIN H09 GND L01 PPI0D0
A02 ADDR24 C10 SRAS F02 VDDEXT H10 GND L02 PPI1SYNC2
A03 ADDR20 C11 GND F03 RESET H11 VDDINT L03 GND
A04 VDDEXT C12 BGH F04 PPI0D10 H12 DATA16 L04 PPI1SYNC3
A05 ADDR14 C13 GND F05 ADDR21 H13 DATA18 L05 VDDEXT
A06 ADDR10 C14 ADDR07 F06 ADDR17 H14 DATA20 L06 PPI1D11
A07 AMS3 C15 DATA1 F07 VDDINT H15 DATA17 L07 GND
A08 AWE C16 DATA3 F08 GND H16 DATA19 L08 VDDINT
A09 VDDEXT D01 PPI0D13 F09 VDDINT J01 VROUT0 L09 GND
A10 SMS3 D02 PPI0D15 F10 GND J02 VROUT1 L10 VDDEXT
A11 SCLK0 D03 PPI0SYNC3 F11 ADDR08 J03 PPI0D2 L11 GND
A12 SCLK1 D04 ADDR23 F12 DATA10 J04 PPI0D3 L12 DR0PRI
A13 BG D05 GND F13 DATA8 J05 PPI0D1 L13 TFS0
A14 ABE2 D06 GND F14 DATA12 J06 VDDEXT L14 GND
A15 ABE3 D07 ADDR09 F15 DATA9 J07 GND L15 DATA27
A16 VDDEXT D08 GND F16 DATA11 J08 VDDINT L16 DATA29
B01 PPI1CLK D09 ARDY G01 XTAL J09 VDDINT M01 PPI1D15
B02 ADDR22 D10 SCAS G02 GND J10 VDDINT M02 PPI1D13
B03 ADDR18 D11 SA10 G03 VDDEXT J11 GND M03 PPI1D9
B04 ADDR16 D12 VDDEXT G04 BYPASS J12 DATA30 M04 GND
B05 ADDR12 D13 ADDR02 G05 PPI0D14 J13 DATA22 M05 NC
B06 VDDEXT D14 GND G06 GND J14 GND M06 PF3
B07 AMS1 D15 DATA5 G07 GND J15 DATA21 M07 PF7
B08 ARE D16 DATA6 G08 GND J16 DATA23 M08 VDDINT
B09 SMS1 E01 GND G09 VDDINT K01 PPI0D6 M09 GND
B10 SCKE E02 PPI0D11 G10 ADDR05 K02 PPI0D4 M10 BMODE0
B11 VDDEXT E03 PPI0D12 G11 ADDR03 K03 PPI0D8 M11 SCK
B12 BR E04 PPI0SYNC1 G12 DATA15 K04 PPI1SYNC1 M12 DR1PRI
B13 ABE1 E05 ADDR15 G13 DATA14 K05 PPI1D14 M13 NC
B14 ADDR06 E06 ADDR13 G14 GND K06 VDDEXT M14 VDDEXT
B15 ADDR04 E07 AMS2 G15 DATA13 K07 GND M15 DATA31
B16 DATA0 E08 VDDINT G16 VDDEXT K08 VDDINT M16 DT0PRI
C01 PPI0SYNC2 E09 SMS0 H01 GND K09 GND N01 PPI1D12
C02 PPI0CLK E10 SWE H02 GND K10 GND N02 PPI1D10
C03 ADDR25 E11 ABE0 H03 PPI0D9 K11 VDDINT N03 PPI1D3
C04 ADDR19 E12 DATA2 H04 PPI0D7 K12 DATA28 N04 PPI1D1
C05 GND E13 GND H05 PPI0D5 K13 DATA26 N05 PF1
C06 ADDR11 E14 DATA4 H06 VDDINT K14 DATA24 N06 PF9
C07 AOE E15 DATA7 H07 VDDINT K15 DATA25 N07 GND
C08 AMS0 E16 VDDEXT H08 GND K16 VDDEXT N08 PF13

ADSP-BF561
Table 37. 256-Ball CSP_BGA (12 mm × 12 mm) Ball Assignment (Numerically by Ball Number) (Continued)
N09 TDO P05 GND R01 PPI1D7 R13 TX/PF26 T09 TCK
N10 BMODE1 P06 PF5 R02 PPI1D6 R14 TSCLK1 T10 TMS
N11 MOSI P07 PF11 R03 PPI1D2 R15 DT1PRI T11 SLEEP
N12 GND P08 PF15 R04 PPI1D0 R16 RFS0 T12 VDDEXT
N13 RFS1 P09 GND R05 PF4 T01 VDDEXT T13 RX/PF27
N14 GND P10 TRST R06 PF8 T02 PPI1D4 T14 DR1SEC
N15 DT0SEC P11 NMI0 R07 PF10 T03 VDDEXT T15 DT1SEC
N16 TSCLK0 P12 GND R08 PF14 T04 PF2 T16 VDDEXT
P01 PPI1D8 P13 RSCLK1 R09 NMI1 T05 PF6
P02 GND P14 TFS1 R10 TDI T06 VDDEXT
P03 PPI1D5 P15 RSCLK0 R11 EMU T07 PF12
P04 PF0 P16 DR0SEC R12 MISO T08 VDDEXT

ADSP-BF561
Table 38. 256-Ball CSP_BGA (12 mm × 12 mm) Ball Assignment (Alphabetically by Signal)
Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No.
ABE0 E11 BR B12 DT0SEC N15 GND N14
ABE1 B13 BYPASS G04 DT1PRI R15 GND P02
ABE2 A14 CLKIN F01 DT1SEC T15 GND P05
ABE3 A15 DATA0 B16 EMU R11 GND P09
ADDR02 D13 DATA1 C15 GND C05 GND P12
ADDR03 G11 DATA2 E12 GND C11 MISO R12
ADDR04 B15 DATA3 C16 GND C13 MOSI N11
ADDR05 G10 DATA4 E14 GND D05 NC M05
ADDR06 B14 DATA5 D15 GND D06 NC M13
ADDR07 C14 DATA6 D16 GND D08 NMI0 P11
ADDR08 F11 DATA7 E15 GND D14 NMI1 R09
ADDR09 D07 DATA8 F13 GND E01 PF0 P04
ADDR10 A06 DATA9 F15 GND E13 PF1 N05
ADDR11 C06 DATA10 F12 GND F08 PF2 T04
ADDR12 B05 DATA11 F16 GND F10 PF3 M06
ADDR13 E06 DATA12 F14 GND G02 PF4 R05
ADDR14 A05 DATA13 G15 GND G06 PF5 P06
ADDR15 E05 DATA14 G13 GND G07 PF6 T05
ADDR16 B04 DATA15 G12 GND G08 PF7 M07
ADDR17 F06 DATA16 H12 GND G14 PF8 R06
ADDR18 B03 DATA17 H15 GND H01 PF9 N06
ADDR19 C04 DATA18 H13 GND H02 PF10 R07
ADDR20 A03 DATA19 H16 GND H08 PF11 P07
ADDR21 F05 DATA20 H14 GND H09 PF12 T07
ADDR22 B02 DATA21 J15 GND H10 PF13 N08
ADDR23 D04 DATA22 J13 GND J07 PF14 R08
ADDR24 A02 DATA23 J16 GND J11 PF15 P08
ADDR25 C03 DATA24 K14 GND J14 PPI0CLK C02
AMS0 C08 DATA25 K15 GND K07 PPI0D0 L01
AMS1 B07 DATA26 K13 GND K09 PPI0D1 J05
AMS2 E07 DATA27 L15 GND K10 PPI0D2 J03
AMS3 A07 DATA28 K12 GND L03 PPI0D3 J04
AOE C07 DATA29 L16 GND L07 PPI0D4 K02
ARDY D09 DATA30 J12 GND L09 PPI0D5 H05
ARE B08 DATA31 M15 GND L11 PPI0D6 K01
AWE A08 DR0PRI L12 GND L14 PPI0D7 H04
BG A13 DR0SEC P16 GND M04 PPI0D8 K03
BGH C12 DR1PRI M12 GND M09 PPI0D9 H03
BMODE0 M10 DR1SEC T14 GND N07 PPI0D10 F04
BMODE1 N10 DT0PRI M16 GND N12 PPI0D11 E02

ADSP-BF561
Table 38. 256-Ball CSP_BGA (12 mm × 12 mm) Ball Assignment (Alphabetically by Signal) (Continued)
PPI0D12 E03 PPI1SYNC1 K04 TDO N09 VDDEXT M14
PPI0D13 D01 PPI1SYNC2 L02 TFS0 L13 VDDEXT T01
PPI0D14 G05 PPI1SYNC3 L04 TFS1 P14 VDDEXT T03
PPI0D15 D02 RESET F03 TMS T10 VDDEXT T06
PPI0SYNC1 E04 RFS0 R16 TRST P10 VDDEXT T08
PPI0SYNC2 C01 RFS1 N13 TSCLK0 N16 VDDEXT T12
PPI0SYNC3 D03 RSCLK0 P15 TSCLK1 R14 VDDEXT T16
PPI1CLK B01 RSCLK1 P13 TX/PF26 R13 VDDINT E08
PPI1D0 R04 RX T13 VDDEXT A01 VDDINT F07
PPI1D1 N04 SA10 D11 VDDEXT A04 VDDINT F09
PPI1D2 R03 SCAS D10 VDDEXT A09 VDDINT G09
PPI1D3 N03 SCK M11 VDDEXT A16 VDDINT H06
PPI1D4 T02 SCKE B10 VDDEXT B06 VDDINT H07
PPI1D5 P03 SCLK0 A11 VDDEXT B11 VDDINT H11
PPI1D6 R02 SCLK1 A12 VDDEXT D12 VDDINT J08
PPI1D7 R01 SLEEP T11 VDDEXT E16 VDDINT J09
PPI1D8 P01 SMS0 E09 VDDEXT F02 VDDINT J10
PPI1D9 M03 SMS1 B09 VDDEXT G03 VDDINT K08
PPI1D10 N02 SMS2 C09 VDDEXT G16 VDDINT K11
PPI1D11 L06 SMS3 A10 VDDEXT J06 VDDINT L08
PPI1D12 N01 SRAS C10 VDDEXT K06 VDDINT M08
PPI1D13 M02 SWE E10 VDDEXT K16 VROUT0 J01
PPI1D14 K05 TCK T09 VDDEXT L05 VROUT1 J02
PPI1D15 M01 TDI R10 VDDEXT L10 XTAL G01

ADSP-BF561
Figure 50 lists the top view of the 256-Ball CSP_BGA (12 mm ×
12 mm) ball configuration. Figure 51 lists the bottom view.
A1 BALL
PAD CORNER
A
KEY:
B
VDDINT GND NC
C
VDDEXT I/O VROUT
D
R
T
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TOP VIEW
Figure 50. 256-Ball CSP_BGA Ball Configuration (Top View)
A1 BALL
PAD CORNER
B KEY:
VDDINT GND NC
C
VDDEXT I/O VROUT
D
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
BOTTOM VIEW
Figure 51. 256-Ball CSP_BGA Ball Configuration (Bottom View)

ADSP-BF561
297-BALL PBGA BALL ASSIGNMENT
Table 39 lists the 297-Ball PBGA ball assignment numerically by
ball number. Table 40 on Page 58 lists the ball assignment
alphabetically by signal.
Table 39. 297-Ball PBGA Ball Assignment (Numerically by Ball Number)
Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal
A01 GND B15 SMS1 G01 PPI0D11 L14 GND
A02 ADDR25 B16 SMS3 G02 PPI0D10 L15 GND
A03 ADDR23 B17 SCKE G25 DATA4 L16 GND
A04 ADDR21 B18 SWE G26 DATA7 L17 GND
A05 ADDR19 B19 SA10 H01 BYPASS L18 VDDINT
A06 ADDR17 B20 BR H02 RESET L25 DATA12
A07 ADDR15 B21 BG H25 DATA6 L26 DATA15
A08 ADDR13 B22 ABE1 H26 DATA9 M01 VROUT0
A09 ADDR11 B23 ABE3 J01 CLKIN M02 GND
A10 ADDR09 B24 ADDR07 J02 GND M10 VDDEXT
A11 AMS3 B25 GND J10 VDDEXT M11 GND
A12 AMS1 B26 ADDR05 J11 VDDEXT M12 GND
A13 AWE C01 PPI0SYNC3 J12 VDDEXT M13 GND
A14 ARE C02 PPI0CLK J13 VDDEXT M14 GND
A15 SMS0 C03 GND J14 VDDEXT M15 GND
A16 SMS2 C04 GND J15 VDDEXT M16 GND
A17 SRAS C05 GND J16 VDDINT M17 GND
A18 SCAS C22 GND J17 VDDINT M18 VDDINT
A19 SCLK0 C23 GND J18 VDDINT M25 DATA14
A20 SCLK1 C24 GND J25 DATA8 M26 DATA17
A21 BGH C25 ADDR04 J26 DATA11 N01 VROUT1
A22 ABE0 C26 ADDR03 K01 XTAL N02 PPI0D9
A23 ABE2 D01 PPI0SYNC1 K02 NC N10 VDDEXT
A24 ADDR08 D02 PPI0SYNC2 K10 VDDEXT N11 GND
A25 ADDR06 D03 GND K11 VDDEXT N12 GND
A26 GND D04 GND K12 VDDEXT N13 GND
B01 PPI1CLK D23 GND K13 VDDEXT N14 GND
B02 GND D24 GND K14 VDDEXT N15 GND
B03 ADDR24 D25 ADDR02 K15 VDDEXT N16 GND
B04 ADDR22 D26 DATA1 K16 VDDINT N17 GND
B05 ADDR20 E01 PPI0D15 K17 VDDINT N18 VDDINT
B06 ADDR18 E02 PPI0D14 K18 VDDINT N25 DATA16
B07 ADDR16 E03 GND K25 DATA10 N26 DATA19
B08 ADDR14 E24 GND K26 DATA13 P01 PPI0D7
B09 ADDR12 E25 DATA0 L01 NC P02 PPI0D8
B10 ADDR10 E26 DATA3 L02 NC P10 VDDEXT
B11 AMS2 F01 PPI0D13 L10 VDDEXT P11 GND
B12 AMS0 F02 PPI0D12 L11 GND P12 GND
B13 AOE F25 DATA2 L12 GND P13 GND
B14 ARDY F26 DATA5 L13 GND P14 GND

ADSP-BF561
Table 39. 297-Ball PBGA Ball Assignment (Numerically by Ball Number) (Continued)
Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal
P15 GND U11 VDDEXT AC04 GND AE21 RX
P16 GND U12 VDDEXT AC23 GND AE22 RFS1
P17 GND U13 VDDEXT AC24 GND AE23 DR1SEC
P18 VDDINT U14 GND AC25 DR0SEC AE24 TFS1
P25 DATA18 U15 VDDINT AC26 RFS0 AE25 GND
P26 DATA21 U16 VDDINT AD01 PPI1D7 AE26 NC
R01 PPI0D5 U17 VDDINT AD02 PPI1D6 AF01 GND
R02 PPI0D6 U18 VDDINT AD03 GND AF02 PPI1D4
R10 VDDEXT U25 DATA24 AD04 GND AF03 PPI1D2
R11 GND U26 DATA27 AD05 GND AF04 PPI1D0
R12 GND V01 PPI1SYNC3 AD22 GND AF05 PF1
R13 GND V02 PPI0D0 AD23 GND AF06 PF3
R14 GND V25 DATA26 AD24 GND AF07 PF5
R15 GND V26 DATA29 AD25 NC AF08 PF7
R16 GND W01 PPI1SYNC1 AD26 RSCLK0 AF09 PF9
R17 GND W02 PPI1SYNC2 AE01 PPI1D5 AF10 PF11
R18 VDDINT W25 DATA28 AE02 GND AF11 PF13
R25 DATA20 W26 DATA31 AE03 PPI1D3 AF12 PF15
R26 DATA23 Y01 PPI1D15 AE04 PPI1D1 AF13 NMI1
T01 PPI0D3 Y02 PPI1D14 AE05 PF0 AF14 TCK
T02 PPI0D4 Y25 DATA30 AE06 PF2 AF15 TDI
T10 VDDEXT Y26 DT0PRI AE07 PF4 AF16 TMS
T11 GND AA01 PPI1D13 AE08 PF6 AF17 SLEEP
T12 GND AA02 PPI1D12 AE09 PF8 AF18 NMI0
T13 GND AA25 DT0SEC AE10 PF10 AF19 SCK
T14 GND AA26 TSCLK0 AE11 PF12 AF20 TX
T15 GND AB01 PPI1D11 AE12 PF14 AF21 RSCLK1
T16 GND AB02 PPI1D10 AE13 NC AF22 DR1PRI
T17 GND AB03 GND AE14 TDO AF23 TSCLK1
T18 VDDINT AB24 GND AE15 TRST AF24 DT1SEC
T25 DATA22 AB25 TFS0 AE16 EMU AF25 DT1PRI
T26 DATA25 AB26 DR0PRI AE17 BMODE1 AF26 GND
U01 PPI0D1 AC01 PPI1D9 AE18 BMODE0
U02 PPI0D2 AC02 PPI1D8 AE19 MISO
U10 VDDEXT AC03 GND AE20 MOSI

ADSP-BF561
Table 40. 297-Ball PBGA Ball Assignment (Alphabetically by Signal)
ABE0 A22 BR B20 DT0SEC AA25 GND N15
ABE1 B22 BYPASS H01 DT1PRI AF25 GND N16
ABE2 A23 CLKIN J01 DT1SEC AF24 GND N17
ABE3 B23 DATA0 E25 EMU AE16 GND P11
ADDR02 D25 DATA1 D26 GND A01 GND P12
ADDR03 C26 DATA2 F25 GND A26 GND P13
ADDR04 C25 DATA3 E26 GND B02 GND P14
ADDR05 B26 DATA4 G25 GND B25 GND P15
ADDR06 A25 DATA5 F26 GND C03 GND P16
ADDR07 B24 DATA6 H25 GND C04 GND P17
ADDR08 A24 DATA7 G26 GND C05 GND R11
ADDR09 A10 DATA8 J25 GND C22 GND R12
ADDR10 B10 DATA9 H26 GND C23 GND R13
ADDR11 A09 DATA10 K25 GND C24 GND R14
ADDR12 B09 DATA11 J26 GND D03 GND R15
ADDR13 A08 DATA12 L25 GND D04 GND R16
ADDR14 B08 DATA13 K26 GND D23 GND R17
ADDR15 A07 DATA14 M25 GND D24 GND T11
ADDR16 B07 DATA15 L26 GND E03 GND T12
ADDR17 A06 DATA16 N25 GND E24 GND T13
ADDR18 B06 DATA17 M26 GND J02 GND T14
ADDR19 A05 DATA18 P25 GND L11 GND T15
ADDR20 B05 DATA19 N26 GND L12 GND T16
ADDR21 A04 DATA20 R25 GND L13 GND T17
ADDR22 B04 DATA21 P26 GND L14 GND U14
ADDR23 A03 DATA22 T25 GND L15 GND AB03
ADDR24 B03 DATA23 R26 GND L16 GND AB24
ADDR25 A02 DATA24 U25 GND L17 GND AC03
AMS0 B12 DATA25 T26 GND M02 GND AC04
AMS1 A12 DATA26 V25 GND M11 GND AC23
AMS2 B11 DATA27 U26 GND M12 GND AC24
AMS3 A11 DATA28 W25 GND M13 GND AD03
AOE B13 DATA29 V26 GND M14 GND AD04
ARDY B14 DATA30 Y25 GND M15 GND AD05
ARE A14 DATA31 W26 GND M16 GND AD22
AWE A13 DR0PRI AB26 GND M17 GND AD23
BG B21 DR0SEC AC25 GND N11 GND AD24
BGH A21 DR1PRI AF22 GND N12 GND AE02
BMODE0 AE18 DR1SEC AE23 GND N13 GND AE25
BMODE1 AE17 DT0PRI Y26 GND N14 GND AF01

ADSP-BF561
Table 40. 297-Ball PBGA Ball Assignment (Alphabetically by Signal) (Continued)
GND AF26 PPI0D7 P01 RSCLK0 AD26 VDDEXT K13
MISO AE19 PPI0D8 P02 RSCLK1 AF21 VDDEXT K14
MOSI AE20 PPI0D9 N02 RX AE21 VDDEXT K15
NC K02 PPI0D10 G02 SA10 B19 VDDEXT L10
NC L01 PPI0D11 G01 SCAS A18 VDDEXT M10
NC L02 PPI0D12 F02 SCK AF19 VDDEXT N10
NC AD25 PPI0D13 F01 SCKE B17 VDDEXT P10
NC AE13 PPI0D14 E02 SCLK0 A19 VDDEXT R10
NC AE26 PPI0D15 E01 SCLK1 A20 VDDEXT T10
NMI0 AF18 PPI0SYNC1 D01 SLEEP AF17 VDDEXT U10
NMI1 AF13 PPI0SYNC2 D02 SMS0 A15 VDDEXT U11
PF0 AE05 PPI0SYNC3 C01 SMS1 B15 VDDEXT U12
PF1 AF05 PPI1CLK B01 SMS2 A16 VDDEXT U13
PF2 AE06 PPI1D0 AF04 SMS3 B16 VDDINT J16
PF3 AF06 PPI1D1 AE04 SRAS A17 VDDINT J17
PF4 AE07 PPI1D2 AF03 SWE B18 VDDINT J18
PF5 AF07 PPI1D3 AE03 TCK AF14 VDDINT K16
PF6 AE08 PPI1D4 AF02 TDI AF15 VDDINT K17
PF7 AF08 PPI1D5 AE01 TDO AE14 VDDINT K18
PF8 AE09 PPI1D6 AD02 TFS0 AB25 VDDINT L18
PF9 AF09 PPI1D7 AD01 TFS1 AE24 VDDINT M18
PF10 AE10 PPI1D8 AC02 TMS AF16 VDDINT N18
PF11 AF10 PPI1D9 AC01 TRST AE15 VDDINT P18
PF12 AE11 PPI1D10 AB02 TSCLK0 AA26 VDDINT R18
PF13 AF11 PPI1D11 AB01 TSCLK1 AF23 VDDINT T18
PF14 AE12 PPI1D12 AA02 TX/PF26 AF20 VDDINT U15
PF15 AF12 PPI1D13 AA01 VDDEXT J10 VDDINT U16
PPI0CLK C02 PPI1D14 Y02 VDDEXT J11 VDDINT U17
PPI0D0 V02 PPI1D15 Y01 VDDEXT J12 VDDINT U18
PPI0D1 U01 PPI1SYNC1 W01 VDDEXT J13 VROUT0 M01
PPI0D2 U02 PPI1SYNC2 W02 VDDEXT J14 VROUT1 N01
PPI0D3 T01 PPI1SYNC3 V01 VDDEXT J15 XTAL K01
PPI0D4 T02 RESET H02 VDDEXT K10
PPI0D5 R01 RFS0 AC26 VDDEXT K11
PPI0D6 R02 RFS1 AE22 VDDEXT K12

ADSP-BF561
Figure 52 lists the top view of the 297-Ball PBGA ball configura
tion. Figure 53 lists the bottom view.
A
B
C
D
E
F
G
KEY:
H
J VDDINT GND NC
K
VDDEXT I/O VROUT
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
TOP VIEW
Figure 52. 297-Ball PBGA Ball Configuration (Top View)
A
B
C
D
E
F
G KEY:
H V GND NC
DDINT
J
VDDEXT I/O VROUT
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
BOTTOM VIEW
Figure 53. 297-Ball PBGA Ball Configuration (Bottom View)

ADSP-BF561
OUTLINE DIMENSIONS
Dimensions in the outline dimension figures are shown in
millimeters.
17.00 BSC SQ 15.00 BSC SQ

A1 BALL
1.00 BSC PAD CORNER
BALL PITCH
A1 BALL
PAD CORNER
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
TOP VIEW 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
BOTTOM VIEW
1.90*
1.76 SIDE VIEW
1.61 DETAIL A
0.45 MIN
0.20 MAX
*NOTES COPLANARITY
1. COMPLIES WITH JEDEC REGISTERED OUTLINE SEATING PLANE
MO-192-AAF-1, WITH EXCEPTION TO PACKAGE HEIGHT. DETAIL A
2. MINIMUM BALL HEIGHT 0.45 0.70
0.60
0.50
BALL
DIAMETER
Figure 54. 256-Ball Chip Scale Package Ball Grid Array (CSP_BGA) (BC-256-4)

ADSP-BF561
12.10 A1 CORNER
12.00 SQ INDEX AREA
16 14 12 10 8 6 4 2
11.90 15 13 11 9 7 5 3 1
A
BALL A1 B
C
INDICATOR D
E
9.75 F
BSC SQ G
TOP VIEW H
J
0.65
K
BSC L
M
N
P
R
T
BOTTOM VIEW
DETAIL A
*1.70
1.51 *1.31
1.36 DETAIL A 1.21
1.10
*0.30 NOM
0.25 MIN
0.45
COPLANARITY
0.40 0.10 MAX
SEATING 0.35
PLANE BALL DIAMETER
*COMPLIANT TO JEDEC STANDARDS MO-225 WITH EXCEPTION

TO DIMENSIONS INDICATED BY AN ASTERISK.
Figure 55. 256-Ball Chip Scale Package Ball Grid Array (CSP_BGA) (BC-256-1)
27.20 A1 CORNER
27.00 SQ INDEX AREA
26.80 26 24 22 20 18 16 14 12 10 8 6 4 2
25 23 21 19 17 15 13 11 9 7 5 3 1
A
B
C
D
A1 BALL E
PAD CORNER F
G
24.20 BOTTOM VIEW H
24.00 SQ J
K
23.80 L
M
TOP VIEW 25.00 N
BSC SQ P
R
T
U
V
W
Y
1.00 AA
BSC AB
AC
AD
AE
AF
8.00
BSC SQ
2.43
DETAIL A
2.23
1.22
2.03 DETAIL A
1.17
0.61 1.12
0.56
0.51
0.50 NOM COPLANARITY

0.70 0.20 MAX
0.40 MIN
0.60 SEATING
0.50 PLANE
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MS-034-AAL-1
Figure 56. 297-Ball Plastic Ball Grid Array (PBGA) (B-297)

ADSP-BF561
SURFACE-MOUNT DESIGN
Table 41 is provided as an aid to PCB design. For industry-
standard design recommendations, refer to IPC-7351, Generic
Requirements for Surface Mount Design and Land Pattern
Standard.
Table 41. BGA Data for Use with Surface-Mount Design

Package Ball Attach Type Solder Mask Opening Ball Pad Size
256-Ball CSP_BGA (BC-256-1) Solder Mask Defined 0.30 mm diameter 0.43 mm diameter
256-Ball CSP_BGA (BC-256-4) Solder Mask Defined 0.43 mm diameter 0.55 mm diameter
297-Ball PBGA (B-297) Solder Mask Defined 0.43 mm diameter 0.58 mm diameter
AUTOMOTIVE PRODUCTS
Some ADSP-BF561 models are available for automotive appli The automotive grade products shown in Table 42 are available
cations with controlled manufacturing. Note that these special for use in automotive applications. Contact your local ADI
models may have specifications that differ from the general account representative or authorized ADI product distributor
release models. for specific product ordering information. Note that all automo
tive products are RoHS compliant.
Table 42. Automotive Products
Temperature Speed Grade Package

Product Family1 Range2 (Max)3 Package Description Option
ADBF561WBBZ5xx –40°C to +85°C 533 MHz 297-Ball PBGA B-297
ADBF561WBBCZ5xx –40°C to +85°C 533 MHz 256-Ball CSP_BGA BC-256-4
1
xx denotes silicon revision.
2
Referenced temperature is ambient temperature.
3
The internal voltage regulation feature is not available. External voltage regulation is required to ensure correct operation.
ORDERING GUIDE
Temperature Package
Model Range1 Speed Grade (Max) Package Description Option
ADSP-BF561SKBCZ-6V2 0°C to +70°C 600 MHz 256-Ball CSP_BGA BC-256-1
ADSP-BF561SKBCZ-5V2 0°C to +70°C 533 MHz 256-Ball CSP_BGA BC-256-1
ADSP-BF561SKBCZ5002 0°C to +70°C 500 MHz 256-Ball CSP_BGA BC-256-1
ADSP-BF561SKB500 0°C to +70°C 500 MHz 297-Ball PBGA B-297
ADSP-BF561SKB600 0°C to +70°C 600 MHz 297-Ball PBGA B-297
ADSP-BF561SKBZ5002 0°C to +70°C 500 MHz 297-Ball PBGA B-297
ADSP-BF561SKBZ6002 0°C to +70°C 600 MHz 297-Ball PBGA B-297
ADSP-BF561SBB600 –40°C to +85°C 600 MHz 297-Ball PBGA B-297
ADSP-BF561SBB500 –40°C to +85°C 500 MHz 297-Ball PBGA B-297
ADSP-BF561SBBZ6002 –40°C to +85°C 600 MHz 297-Ball PBGA B-297
ADSP-BF561SBBZ5002 –40°C to +85°C 500 MHz 297-Ball PBGA B-297
ADSP-BF561SKBCZ-6A2 0°C to +70°C 600 MHz 256-Ball CSP_BGA BC-256-4
ADSP-BF561SKBCZ-5A2 0°C to +70°C 500 MHz 256-Ball CSP_BGA BC-256-4
ADSP-BF561SBBCZ-5A2 –40°C to +85°C 500 MHz 256-Ball CSP_BGA BC-256-4
1
Referenced temperature is ambient temperature.
2
Z = RoHS compliant part.

ADSP-BF561
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Blackfin Embedded

IRQ CONTROL/ JTAG TEST IRQ CONTROL/

Figure 1. Functional Block Diagram

Rev. E | Page 2 of 64 | September 2009

Rev. E | Page 3 of 64 | September 2009

ADDRESS ARITHMETIC UNIT

DATA ARITHMETIC UNIT

Figure 2. Blackfin Processor Core

MEMORY ARCHITECTURE Internal (On-Chip) Memory

Rev. E | Page 4 of 64 | September 2009

CORE A MEMORY MAP CORE B MEMORY MAP

Figure 3. Memory Map

Rev. E | Page 5 of 64 | September 2009

The ADSP-BF561 contains a small boot kernel, which config­ Priority

Rev. E | Page 6 of 64 | September 2009

Rev. E | Page 7 of 64 | September 2009

Rev. E | Page 8 of 64 | September 2009

Rev. E | Page 9 of 64 | September 2009

Rev. E | Page 10 of 64 | September 2009

Rev. E | Page 11 of 64 | September 2009

The savings in power dissipation can be modeled using the

Rev. E | Page 12 of 64 | September 2009

The ADSP-BF561 processor can be clocked by an external crys­ 0O* 1MO

recommendations and the physical PCB layout. The resistor

Rev. E | Page 13 of 64 | September 2009

Rev. E | Page 14 of 64 | September 2009

Rev. E | Page 15 of 64 | September 2009

Rev. E | Page 16 of 64 | September 2009

Table 8. Pin Descriptions

Rev. E | Page 17 of 64 | September 2009

Rev. E | Page 18 of 64 | September 2009

Rev. E | Page 19 of 64 | September 2009

Parameter Conditions Min Nominal Max Unit

Rev. E | Page 20 of 64 | September 2009

Table 12. System Clock (SCLK) Requirements

Parameter Test Conditions Min Typical Max Unit

System designers should refer to Estimating Power for the

Rev. E | Page 21 of 64 | September 2009

Table 13. Absolute Maximum Ratings a

ESD (electrostatic discharge) sensitive device.

Rev. E | Page 22 of 64 | September 2009

Table 16. Clock and Normal Reset Timing

Figure 8. Clock and Normal Reset Timing

Table 17. Power-Up Reset Timing

Figure 9. Power-Up Reset Timing

Rev. E | Page 23 of 64 | September 2009

Table 18. Asynchronous Memory Read Cycle Timing

Figure 10. Asynchronous Memory Read Cycle Timing

Rev. E | Page 24 of 64 | September 2009

Table 19. Asynchronous Memory Write Cycle Timing

DATA15–0 WRITE DATA

Figure 11. Asynchronous Memory Write Cycle Timing

Rev. E | Page 25 of 64 | September 2009

Table 20. SDRAM Interface Timing

Figure 12. SDRAM Interface Timing

Rev. E | Page 26 of 64 | September 2009

Rev. E | Page 27 of 64 | September 2009

Table 22. Parallel Peripheral Interface Timing

Rev. E | Page 28 of 64 | September 2009

The ADSP-BF561 contains a small boot kernel, which config Priority

The ADSP-BF561 processor can be clocked by an external crys 0O* 1MO