MB 3 2 PDF

MB L3 Training
Materials
ASUS Confidential
Overview
Chapter 1. Repair Rule……..................……………...P5~P6
Chapter 2.
2 MB Frame Structure……….………….....P7~P18
Structure P7~P18
Chapter 3. Voltage..................................................P19~P83
Chapter
p 4. Clock.………………………..………..… P84~P95
Chapter 5. Power On Sequence ….……………...P96~P106
Chapter 6. PS/2…………………………………...P107~P113
Chapter 7. USB……………………………………P114~P123
Chapter 8. Com Port…………………….…….….P124~P129
Chapter 9.
9 Print Port
Port…………………………...…P130~P134 P130~P134
Chapter 10. FDD….………………………………P135~P139
Chapter
p 11. IDE……………….…………….…….P140~P147
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ASUS Confidential
Overview
Chapter 12. SATA………………………………...P148~P156
Chapter 13.
13 RAID……………………………...….P157~P167
RAID P157~P167
Chapter 14. AGP ………..………………………..P168~P179
Chapter
p 15. Onboard VGA………………..……..P180~P188
Chapter 16. Audio…………………………………P189~P202
Chapter 17. PCI ……………………………….….P203~P226
Chapter 18. PCI-E …………………………….….P227~P238
Chapter 19. LAN…………………………………..P239~P260
Chapter 20.
20 1394 …………………………………P261~P277
P261~P277
Chapter 21. Memory ……………….………….....P278~P301
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ASUS Confidential
Overview
Chapter 22. Hardware Monitor ……………….…P302~P319
Chapter 23.
23 BIOS………………………...……….P320~P331
BIOS P320~P331
Chapter 24. SMBUS……………………………...P332~P338
Chapter
p 25. POST Code…………………………P339~P378
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ASUS Confidential
Repair Rule
ASUS Confidential
Repair Sequence
1. Voltage
g – DDR,, AGP(PCI-E),
( ), CPU,, BIOS...,,
2. Clock – CPU, DDR, AGP(PCI-E), BIOS…,
3. Reset – CPU, DDR, AGP(PCI-E), BIOS…,
Repair Key:
You must know those 3 points before you repair
motherboard and use those rules step by step.
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ASUS Confidential
MB Frame Structure
ASUS Confidential
Intel P5 Frame Structure ((915 +ICH6))
Intel Pentium 4
Socket 775
Prescott/Tejas
j
CPU
533/800 MB/s FSB

2 channel
Intel DDR SDRAM
PCI-E X16 Slot 8 GB/s Grantsdale-P 333/400 MHz 4 x DIMMs
(North Bridge) 128 bit
PCI-E X16
Marvell
88E8052(Gbit)
DMI Bus
B
2GB/s
3 x PCI-E X1 Slots 500MB/s
PCI-E X1 1 IDE Ports
3 x PCI Slots (Ultra ATA 66/100)
Intel ICH6R
PCI BUS 33MHz (South Bridge)
4 Serial ATA Ports
ITE 8212
Audio Codec USB USB USB USB
Realtek ALC861 azalia
USB USB USB USB
LPC BUS
Winbond
Wi b d USB1.1/2.0 Port x8
83627EHF
4M Supper I/O
BIOS
FWH
1xParallel, Floppy
2 S i l
2xSerial,
KB,MS,Game Port,
HW monitor
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ASUS Confidential
INTEL P5 Frame Structure (955 + ICH7)
Intel LGA775
Pentium 4
Prescott / Cedar Mill / Smithfield DDR2 x 2
3.8GHz+ CPU
FSB 533/800/1066 MHz DDR2 533/667
Intel 82955X ECC
Per dir MCH
PCI-EX x16 Slot 4Gbytes/s Glenwood
8 ch
h ALC882 (
(North Bridge)
g )
Audio DDR2 x 2
DMI bus Per-dir
PCI-EX x16 Azalia 10Gb/s
slot 1x ATA100 port
PCI-EX x1 PCI-EX x4 ATA100
slot PCI-EX x1
Intel 82801G SATA II 4x SATA300 ports
ICH7R
(South Bridge) 8x USB2.0 ports
GBE
PCI Bus Marvell USB
33MHz 88E8001
3x PCI slot
LPC Bus
BIOS 1x Parallel
Flash LPC I/O 1x Floppy
ATA133 ROM Winbond 1x Serial
IDE (FWH) W83627EHG
ITE8211 ATA133 KB & MS
1x Game Ports
2x ATA133
port
ASUS Confidential 9
INTEL P5 Frame Structure (P35 + ICH9R)
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ASUS Confidential
P5Q Deluxe Frame Structure
Intel LGA775
Pentium 4 (90/65/45nm)
3 8GHz+ CPU
3.8GHz+
DDR2 x 2 DDR2 x 2
FSB 800/1066/1333/1600 MHz

PCIe Gen2
PCI-EX x16 Slot
Intel
Eagle Lake P45
DDR2 667/800/1066/1200
PCI-EX x16 Slot (North Bridge)
DMI bus Per-dir

Per dir
1Gbytes/s
PCIe Gen1 6x SATA150/300
PCI-EX x16 Slot
SATA
PCIEx2
8 ch Audio Azalia
ADI2000B Intel ICH10R
88E8001GbE (South Bridge)
PCI Bus 10x USB2.0 ports
33MHz
2x PCI slot WIFI module
PCIex1 88E8056
6
LSI-FW3227 RAID BIOS GbE
MARVELL Flash
88SE6121 ROM
2 x 1394 ports (SPI)
PCI ex x1
PCI-ex
ATA133 LPC I/O 1x Floppy
SiI5723 Winbond 1x Serial
SATA150/300 W83667DHG KB
ASUS Confidential
INTEL P6 Frame Structure
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ASUS Confidential
VIA K8 Frame Structure (K8T400+8237)
AMD
K8 - CrawHammer DDR SDRAM
266/333 Mb/s 3 x DIMMs
CPU
64 bit
800 Mb/s HyperTransport
AGP 8x VIA
533 Mb/s
slot K8T400M
(North Bridge)
533 Mb/s Via Link

5 x PCI Slots 2 SATA P
Ports
t
RAID (RAID)
VIA
VT6410
VT 8237 USB USB USB USB
PCI BUS IEEE1394
(South Bridge)
33MHz VIA VT6307 USB USB USB USB
Wireless
Gbit LAN AC97
Module Codec
3COM/Marvell
3C940-MV00
3C940 MV00 ADI
LPC BUS AD1980
Super I/O BIOS
ITE Flash 6ch Audio
10/100M PHY IT8705F ISA Bus ROM
VIA 1xParallel,
VT6103 2xSerial KB
2xSerial, KB,MS,
MS
Game Port,Floppy
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ASUS Confidential
NVIDIA K8 Frame Structure
AMD 939 DDR ECC
Athlon 64FX/64
CPU 333/400 MHz
Hyper-Transport 800/1000 MHz
2 x PCI-E*1 Slots 2 IDE Ports
(Ultra ATA 66/100/133)
PCI-E*1 Slots
SATA
2 x PCI-E*16 Slots
nVIDIA 4x Serial ATA Ports
RAID
3 x PCI Slots
PCI BUS PCI BUS Sil 3114
TI 1394a 33 MHz CK804 33 MHz 4x Serial ATA 150 Ports
TS43AB22A
10x USB1.1 / USB 2.0 Ports
M
Marvell
ll PCI
Gbit LAN
88E8001
Gb MII
AC97
Marvell
M ll PHY Audio
A di CCodec
d
Gbit LAN Realtek LPC BUS BIOS
Flash
Fl h ROM
88E1111 ALC 850
ITE KB MS
FLOPPY
IT8712F-A IX
3 * FAN (Speed Sense) Supper I/O
(Chassis/CPU/SPS)
Serial port
3 * TEMPERATURE Parallel port
(CPU/MB/SPS)
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ASUS Confidential
VIA AM2 Frame Structure
DDR2
AMD
AMD AM2
AM2
533/667/800 MHz
K8M890
PCIE X16 Slots VGA
NF570 SLI
JMB363
RTL8100C SATA
LAN
(Ultra ATA 33/66/100)
ALC883 Azalia VT8237A
Audio Codec SATA
PCI Bus 2x Serial ATA Ports
2 x PCI Slots USB USB USB USB

USB USB USB USB
USB1.1/ 2.0 Port x10
LPC Bus
BIOS 1xParallel, Floppy

Super I/O 2xSerial,
LPC ITE 8716 KB MS HW monitor
KB,MS,HW
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ASUS Confidential
NVIDIA AM2 Frame Structure (NF570-
(NF570-SLI)
DDR2 ECC
AMD
AMDAM2
AM2
533/667/800 MHz
CHA1 CHB1
CHA2 CHB2
1 x PCI-E X16 Slots
PCI E X16
PCI-E
Audio Codec
nVIDIA
nVIDIA 1xESATA
AD1988B Azalia RAID
1 x PCI-E X16 Slots RAID
Sil3132
Sil3132
NF570-SLI
NF570-SLI PCI-E
PCI-E X16
1 IDE Ports
(Ultra ATA 33/66/100)
2 x PCI
PCI-E
E X1 Slots
SATA
PCI-E X1
6x Serial ATA Ports
RAID 0/1/0+1/5/ JBOD
Marvell
88E1116 Gbit LAN USB USB USB USB
Phy USB USB USB USB
Marvell LPC Bus
88E1116 Gbit LAN USB1.1/2.0 Port x10
3 x PCI Slots PCI Bus 33MHz 1xParallel, Floppyy

Super I/O
S 2xSerial,
BIOS ITE 8716
TITITSB43AB22A LPC KB,MS,HW monitor
TSB43AB22A
1394a
1394a 16
ASUS Confidential
M4A79 Deluxe Frame Structure
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ASUS Confidential
Q & A (Repair Experience)
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ASUS Confidential
Voltage
ASUS Confidential
Outline
Advanced Configuration and Power Interface

Before Power On Voltage and Signal
 Power Supply and Stand By Voltage
 Power button#, RSTCON#, RSMRST#
 Battery Voltage
After Power On Voltage
 Linear & Switch Regulator introduction
Voltage
V lt Solution
S l ti - Linear
Li &S
&Switch
it h R
Regulator
l t
Typical Linear Regulator
Typical Switch Regulator
 Voltage Distribution
P5ND2-SLI
Intel P4 (Old models)
Detail Sample-P4S800D
 VCORE
Multi-Phase Architecture
Multi-Phase Controller Sample ADP3180
Problem Debug Procedure
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ASUS Confidential
Advanced Configuration and Power Interface
S1: All Power
S3: Standby and Dual
S5: Only Standby
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ASUS Confidential
Before Power On
ASUS Confidential
Power Supply and
Stand By Voltage
ASUS Confidential
Power Supply-
Supply-Overview
3.3V * 11 1 3.3V *
-12V 12 2 3.3V *
GND
COM 13 3 GND
COM
PS-ON# 14 4 5V
GND
COM 15 5 GND
COM
GND
COM 16 6 5V
GND
COM 17 7 GND
COM
-5V 18 8 PW-OK
5V 19 9 5VSB
5V 20 10 12V
* optional
ti l
ASUS Confidential
Power Supply-
Supply-PS_ON#, 5VSB
3.3V * 11 1 3.3V *
PS-ON# is an active low signal that
-12V 12 2 3.3V * turns on all of the main power rails
GND including 3
3.3V,
3V 5V
5V, -5V,
5V 12V
12V, and -12V
12V
GND
COM 13 3 COM power rails.
PS-ON # 14 4 5V
GND
COM 15 5 GND
COM
COM
GND 16 6 5V
GND
COM 17 7 GND
COM
-5V 18 8 PW-OK
5VSB is a standby voltage that may
be used to power circuits that require
5V 19 9 5VSB power input during the powered down
state of the power rails.
5V 20 10 12V
* optional
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ASUS Confidential
Power Supply Sequence
+5VSB
PS_ON#
+12V,5V,3V
1. Before you turn on power 5VSB is always high! while you plug in
the power supply which offers the standby voltage to some
chipsets that can boot MB up!
2. PS_ON#
PS ON# must be touched off low to turn MB on !
3. If PS_ON# were low, every voltages from power supply will
operate!
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ASUS Confidential
Power Supply-
Supply-Standby Voltage
Unplug ATX Power Supply Plug-in ATX Power Supply
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ASUS Confidential
Power Supply-
Supply-5VSB Circuit
For LAN Voltage

+1.5VSB
3.3V * 11 1 3.3V *
Linear
12V
-12V 12 2 3 3V *
3.3V
Regulator
COM 13 3 COM
PS-ON 14 4 5V
+2 5VSB
+2.5VSB
COM 15 5 COM
COM 16 6 5V Linear
COM 17 7 COM R
Regulator
l t South
-5V 18 8 PW-OK Bride
Linear
5V 19 9 5VSB +3VSB
Reg lator
Regulator
5V 20 10 12V Super I/O
* optional
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ASUS Confidential
PWRBTN#
Before you boot up the board, it’s 1. +5VSB

b t way to
best t measure the
th Power
P
Button#.
#, you must know this signal is
#
acted by low, initially it is high. 2.
+3VSB
South
Bridge
3.
Power Button#
Super I/O
+3VSB GND
ASIC 3.
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ASUS Confidential
RSTCON#
RSTCON# is high
g Initially.
y 1. +5VSB
While you touch it off, it will

reset all of the chipset.
2.
+3VSB
South
Bridge
3.
RSTCON#
Super I/O
+3VSB GND
ASIC 3.
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ASUS Confidential
RSMRST#
When 5VSB and 3VSB send to SIO and SB

SIO will send this signal ‘’RSMRST# ’’ to SB’s boot up circuit to
notice the MB is ready to boot up! If this signal is Lo, you can’t
boot up
p MB.
Do you know when RSMRST# is Lo?

The answer is unplug the ATX connector!
+5VSB
South
B id
Bridge +5VSB
RSMSRT# = Hi
+3VSB
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ASUS Confidential
PS ON#
PS_ON#
ASUS Confidential
Power Supply-
Supply-PS_ON Circuit
5V
0V 3.3V * 11 1 3.3V *
Super IO, ASIC, IT8282
4. -12V 12 2 3.3V *
PS_ON# COM 13 3 COM
Power Button# PS_ON PS-ON# 14 4 5V
1. Circuit
COM 15 5 COM
2. 3. COM 16 6 5V
IO_PWRBTN#
SLP_S4#
COM 17 7 COM
SLP_S3#
-5V 18 8 PW-OK
5V 19 9 5VSB
South
Bride 5V 20 10 12V
* optional
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ASUS Confidential
Battery Circuit
ASUS Confidential
Outline
1.Diagram
g
2.Signal Description
3.Repair Flow Chart
4.Repair Technique
5.Q & A (Repair Experience)
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ASUS Confidential
Function of Battery
ACPI S5 State
• ATX unpluged
l d
• Battery power only
• All power is shut off except for RTC
• No wake events are possible
Function of Battery Power are:

• CMOS SRAM
• Real Time Clock
• AC Power Loss Restart
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ASUS Confidential
CLRTC setting
First Pin
Before boot up the board, please check the jumper in normal status.
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ASUS Confidential
Real Time Clock circuit
Battery
32.7 KHz
ASUS Super
p
ASIC I/O South Bridge
3VSB
RTCRST#
B A
RTCRST#
C CLR *Current Leakage g measure:
1kohm CMOS
Use multi-meter to measure the 1kohm,
the voltage value between 1mV~15mV is
When you plug in power supply, A=C ok, out of this range is NG.
According to Ohm theory: I=V/R,
I=V/R the
When you unplug power supply, A=B Current leakage should be 1uA~10uA.
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ASUS Confidential
Repair Flow Chart
START
Use Multi-meter to measure

Current Leakage value
NG ok Change Battery,
Ch B tt ok
The value is out Check Battery
Measure the C.L.
of range Power is 3V
value is OK.
ok NG
ok Change diode, ok
Check Diode Measure the C.L.
RB715 is OK value is OK
NG
ok
Change I/O, ASIC,
Check Vbatt related ok
Measure the C.L.
CL
Components I/O,ASIC
value is OK
NG
Change SB
ok
Finished
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ASUS Confidential
Repair Technique
Technique-- Measure Current Leakage
1. Use multi-meter to measure 1k

ohm near the battery circuit, the
value between 1mV~10mV is ok,
out Of this range is NG.
(According to Ohm theory: I=V/R,

the Current leakage should be
1uA~10uA.))
1
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ASUS Confidential
Repair Technique
Technique--Check Battery, Diode..
2. If the value is NG,

2 NG check the
battery voltage is 3V. If not,
change battery and measure the
leakage current again
again.
3. If the value is still NG, check

the diode (RB715F) near battery is
ok. If NG,, please
p try
y to change
g it
and measure again.
3
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ASUS Confidential
Repair Technique
Technique--Check Vbatt connection
4. If the value is still NG,

4 NG check
which component use Vbatt. Most
MB Vbatt connect to SB, I/O and
ASUS ASIC
ASIC. We can strip up the
Vbatt pin of I/O and ASIC to
confirm which component is NG.
5. If it’s not I/O or ASIC problem

finally please try to change SB.
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ASUS Confidential
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After Power On
ASUS Confidential
Voltage Solution
Linear & Switch Regulator
ASUS Confidential
Linear &Switch Regulator
1. Linear Regulator – Lower Cost and Higher heat.
For DDR voltage, AGP voltage, LAN voltage, FAN.
2. Switch Regulator – Higher Cost and Lower heat.
For VCORE, DDR voltage, AGP voltage.
Switch Regulator Linear Regulator
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Linear Regulator
S G
D
S
D
G
Linear Regulator
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ASUS Confidential
MOSFET
MOSFET
 N channel, Current high
 If G is hi, the voltage in D should transfer to S.
A B
Hi
 P channel, Current low.

 If G is lo, the voltage in S should transfer to D.
B A
Lo
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ASUS Confidential
IN+ = IN-, +1.5VSB REF (12th pin)= +1.5VSB FB (13th pin)
If 13th p
pin ((Feedback)) were lower than 12th p
pin ((Reference),
) the 14th
pin will make VG hi, meanwhile MOSFET is working till IN 4 - = IN4 +.
1.
Input
Output
Hi 2. 3
3.
5. 4
4.
6.
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ASUS Confidential
2. 1.
Input
p
Hi
4
4.
3.
6.
Output 5.
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ASUS Confidential
A.C.P.I.
– S0--Working
S0 Working Status
– S1--POS(Power on Suspend)
– S3--STR(Suspend
S3 STR(Suspend to RAM), Memory Working
– S4--STD(Suspend to Disk), H.D.D. Working
– S5--Soft Off
SLP_S3# = Hi S0
_
SLP_S4# = Hi S1 S0 S1 S3 S4 S5
SLP_S3# = Lo S3# 1 1 0 0 0
S3
SLP S4# = Hi
SLP_S4#
S4# 1 1 1 0 0
SLP_S3# = Lo S4
S5# 1 1 1 1 0
SLP_S4# = Lo S5
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ASUS Confidential
S0: All Power

S3 St
S3: Standby
db and
d Dual
D l
S5: Only Standby
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ASUS Confidential
‘’Dual’’ Switch Solution
5.ACPI
 N channel for S0, Current high
 If G is hi, the voltage in D should transfer to S.
A B
Hi
 P channel for S3 and S5, Current low.

 If G is lo, the voltage in S should transfer to D.
B A
Lo
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ASUS Confidential
‘’Dual’’ Switch Circuit
S0 N-Ch.
S3 P-Ch.
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S0 – Dual Switch Circuit
7.
S0 N-Ch. +5V
6
6. Output
4. Hi 5.
3.
2. Low
Hi
1.
P-Ch.
Hi
Input
From 3VSB to GND
ASUS Confidential 55
N-Ch.
5. Lo
Output
6.
2
2. Hi
Lo
1.
Lo 4. P-Ch.
3.
Input
S3
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ASUS Confidential
66.
N-Ch. +0V
p
Output
55.
4. Lo
Lo
3
3.
5.
2. Low
1. Hi
Hi P-Ch.
4.
3.
Input
From 3VSB to GND
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ASUS Confidential
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Switch Regulator
Switch Regulator
Switch Regulator
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ASUS Confidential
Typical Switch Regulator
1. Input
4.
High side ON
Low side OFF
2. High Gate 6.
O t t
Output
Low Gate
5. High side OFF
Low side ON
Controller
3.
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ASUS Confidential
Voltage Distribution
ASUS Confidential
P5Q Deluxe Voltage Distribution
Vcore Batt
1.8V
VTTCPU 3VSB W83667DHG
CPU VTTDDR DDR II 3 3V
3.3V
CPU_PLL
12V
5VDUAL
3VSB USB
3V Clock PCIEX16
Gen 3V
3.3V
SPI
5V
3VSB 12V
1.1V_NB PCI SLOT FAN
+/-12V
1.8VDUAL Eaglelake
1.5V 5VDUAL
3V KB/MS
1.2V
3.3V
88SE6111 1.8VSB
1.1VSB
1.2VSB Marvell
1.5V 3.3VA 8056
VTT_CPU AD2000B 3VSB
3.3V
3V ICH10 12V
3VSB 3.3V 3.3VSB
Batt 1.8V
Q Switch
Q-Switch PCIEx1
3.3V
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ASUS Confidential
Voltage Distribution – P5ND2
P5ND2--SLI
5VDual 1.8V VTT_DDR
1.4V
3VSBSW#
1.4VSB
2.5VSB
1.0VSB
2.5VSB
VTT_CPU
1.5VSB
Red is for stand by voltage

Blue is for memory
Green is for VCORE voltage
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Voltage Distribution Sample [Intel 915 (925)]
+12V
+12V_4P VCORE
+12V_4P
Switch CPU +5V HDD/ODD
+12V VTT_CPU
+12V
Power +5V +1. 5V
+5V SATA
GMCH
Supply +3V Switch +3V-DUAL VTT_CPU
+12V
+2. 5V(1.8V)-DU
+5VSB +5V FLOPPY
Lin. R. +3VSB Switch
+1. 5V
-12V +3V
VTT_CPU
+3V-DUAL +2.5VDUAL +3VSB
Lin. R. (+2.5V) SUPER IO
+3V V-BAT
ICH
+3V Lin R.
Lin. R VTT_DDR
VTT DDR
+5V
+5V-DUAL
+3VSB PS2 KB/MS
+3V Lin. R. +2. 5V
V-BAT
+12V
+5V(3V) Switch +1. 5V Lin. R. VTT_CPU
+2. 5V(1.8V)-DU
( )
+5V
DDR SERIAL
VTT_DDR
+5V Switch (1.8VDU) Lin. R. (VTT_DDR)
-12V
+3V CLOCK
+3VSB +2.5VSB +3VSB
Lin. R. +5V
PARALLEL
((+2.5VSB)) LAN +12V
(+1.2VSB) +3V
+1.2VSB PCI-E +5V-DUAL
Lin. R. USB PORT
+3VSB
+5VA
+3V
AUDIO +12V BIOS
+3V
+3V
+12V Lin. R. +5VA +12V
+5V PCI FAN
+3V
1394
64 +3VSB
ASUS Confidential -12V
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ASUS Confidential
VCORE
ASUS Confidential
VCORE
Driver
Driver
Power Controller
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VCORE Control IC—
IC—ADP3180
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VCORE Architecture
+5V
0 ((Low Level)) ：0V
1 (High Level) ：5V 1K
10K
VID4
VID3
Vcore
Switching
S it hi
CPU VID2
Regulator
VID1
VID0
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ADP3180 Output Voltage V.S. VID code
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VCORE_EN Sequence for P5 Module
1.
1.2V Inside short circuit
We should measure
the Controller EN
pin 1.2V in 11th at
2
2.
fi t time,
first ti if VCORE
no work!
12V
3.
1.2V
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1.
1.2V Inside short circuit
We should measure
the Controller EN
pin 1.2V in 11th at
2
2.
fi t time,
first ti if VCORE
no work!
12V
1 2V
1.2V
3.
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2.
We should measure
the Controller EN pinp
1.1V at first time, if
VCORE no work!
1.
3.
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Phase Option
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Controller Operation
+12V
Output filter and

load
BOOT
VCC
UGATE
Drive PHASE
PWM
HIP6601
Compensation LGATE
components
+12V
+5V
+Vcore
BOOT
VFB VCC COMP VCC
UGATE
VSEN PWM1
VCORE_EN Drive PHASE
PWM
PWM2 HIP6601
PGOOD
LGATE
MainPWM3
Control
HIP6301
VID ISEN1
ISEN2
+12V
ISEN3
FS
GND BOOT
VCC
UGATE
VCC Drive PHASE

PWM
HIP6601
PWM (Pulse-width LGATE
modulating)
switching and
control
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Driver Operation
I1
Iout 12 VIN
VCC
t
High side ON
I2 Low side OFF
12Vin
t UGATE
Iout
I2 Driver
PHASE
LGATE
t PGND
I3 FB
High side OFF
GND I3 Low side ON
t
SYNCHRONOUS BUCK
CONVERTER
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Between Driver and MOSFET Operation
P.S. High side VGS and Low side VGS

both value are 8.2KΩ!
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Flow Chart 1. – Measure 12V’s Impedance and VCORE’s
START 1.Impedance in 12V is <100
2.Impedance in VCORE is <50
3.Impedance from 12V to VCORE is <100

‧12V Impedance NO
‧Vcore Impedance
‧12V to Vcore Impedance
No short?
Yes
Boot up
Check Other Circuit fail:

Check Vcore OK? NO whether Yes Example: PWM IC fail,
All wave OK? boot after RC small component or
repairing? soldering fail.
Yes
NO
END
Check
Power
Supply
workk OK?
Yes
NO
Check PWM Other Circuit fail:
IC EN PIN Example:
p Socket fail
1.25V OK? NO 1.25VTT_CPU fail
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Flow Chart 2. – Measure Driver’s Impedance and MOSFET’s
Turn off Power Supply

Remove Power Supply cable
Check
MOS NO Remove all abnormal
RGS is MOS which RGS is
OK? NG.
Yes
Check
Driver NO
Impedance Remove Driver
is OK?
Yes
+ Point: Red Line PIN1(BST) PIN8(DRVH) PIN4(VCC) PIN5(DRVL) PIN2(DRVL) PIN3(DRVL)
- Point: Black Line ( )

PIN8(DRVH) PIN7(SW)
( ) PIN5(DRVL)
( ) PIN6(PGND)
( ) PIN6(PGND)
( ) PIN6(PGND)
( )
Impedance >1M 8.2K(10%) > 300K 8.2K(10%) > 100K > 50K
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Flow Chart 3. – Replace and Boot up
Other Circuit fail:

Measure the Pad NO Example: PWM IC fail,
which MOS &
Driver just been RC small component or
removed is OK? soldering fail.
Yes
Measure MOS component
which was just removed.
Then record the defect
MOS & Driver.
Mount good MOS and

Driver
Measure MOS & NO

Driver Impedance
Other root cause like
are OK. soldering short.
Y
Yes
‧12V Impedance
‧Vcore Impedance NO Other rootcause like
Socket short or Soldering
‧12V
12V tto V
Vcore iimpedance
d
are all OK. short.
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Vcore Problem Debug Procedure (1)
If no Output
p
 Check if both 5V and 12V are OK
 Check POWER MOSFET (both UGATE/ LGATE) are not
short
h t
 Check all VIDs of Power Regulator are not high
 Check EN/FS of Power Regulator is not zero Volt
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Vcore Problem Debug Procedure (2)
If the output
p voltage
g wrong
g
 Check if VIDs of Power Regulator are wrong setting
 Check if the feedback resistor divider is wrong
 Check if UGATE and LGATE of Power Regulator with
wrong voltage level
 Check if POWER MOSFET failure
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Clock
ASUS Confidential
Outline
1.Diagram
g
3.Repair Flow Chart
4.Repair Technique
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Clock Chip Diagram
1.Sometimes the Clock chip connect one Diode or BJT
component either
either.
2.It depends on designer.
3V 3V
3V 3V
Inductor Inductor
Clock Clock
Generator Generator
14.318 MHZ 14.318 MHZ
PG PG
Figure A. BJT Diode
SLP_S3# SLP_S3# Figure B.
South
ASIC Bridge
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PWRGD
PWR GD for Clock Generator
Sometimes we can find BAT54AW near ICS.

VRMPWRGD and SLP_S3# must be 3V
Finally, CLKVCC offer 3V PWRGD to Clock Generator .
If Clock Generator doesn’t work,, you
y must measure this PWRGD
signal first.
CLKVCC3
8
CRN1D
8.2KOHM
7
3V CD2 3V
1
(25) R_ICH_VRMPWRGD C_PG
3
2
(25,34) SLP_S3#
3V BAT54AW
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CLOCK Generator Distribution Diagram
CPUHCLK
CPUHCLK# CPU
66M_MCH
MCHHCLK
MCHHCLK# MCH
100M_CK_HL_NB
66MHZ
AGP
33MHZ
48MHZ S I/O
33MHZ
PCI
33MHZ
CLK 14M_ICH
FWH
Generator 48M_ICH
66M_ICH
66M ICH ICH5
100M_CK_HL_SB
33MHZ TSB43AB22 24.576Mhz
(1394) Crystal
33MHZ
BCM5702 25Mhz
(LAN)
Crystal
24.576Mhz Realtek
33MHZ
Crystal ALC650
PDC 20378 20Mhz
(RAID) Crystal (Audio)
14.318MHZ
AD1888
(Audio)
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P5Q Deluxe Clock Distribution
MCHHCLK/# 200/266MHZ
Intel
CK_100M_MCH/# 100MHZ
BearLake DDR2 1,2,3,4
CPUHCLK CK 96M DREF/# 96MHZ
CK_96M_DREF/#
GMCH
200/266/333MHZ M_CHB_CLK/#
CK_100M_ICH/# 100MHZ
Intel
LGA775 CK_100M_SATA/# 100MHZ
CK_33M_ICH/# 33MHZ BITCLK 24MHZ

Intel
CK 48M USB/# 48MHZ
CK_48M_USB/#
ICH9 AUDIO Code
Clock
Chip CK_14M_ICH/# 14.318MHZ
CK_33M33HZ
PCI Slot CK_100M_PE16/# 100MHZ

PCIEx16 Slot
VIA6308 CK 100M PE1/# 100MHZ
CK_100M_PE1/#
PCIEx1 Slot
TPM CK_100M_PE1/# 100MHZ
Attansic L1
CK 48M SIO 48MHZ
CK_48M_SIO
CK_33M_SIO 33MHZ W83667EHF

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Repair Flow Chart
START
Visual Inspection NG Change damaged CLK OK

check CLK Gen. and related small
Gen.& NG components
components are ok
OK NG
Check CLK Vcc 3V & Fix any trace open and OK

NG
Measure CLK Gen. Voltage Input related trace change any NG RLC
component component
OK NG
NG OK
Measure X’TAL 14.318Mhz is ok
Check X’TAL & related Change NG X’TAL or
two Capacitors
p are ok Capacitor
p
NG
OK
Trace the circuit, check Fix any trace open and OK

NG
Check which CLK signal is wrong related trace & resistor
resistor, change any NG RLC
capacitor component
OK NG
Change CLK Generator Finished

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Repair Technique-
Technique-Visual Inspection
Visual Inspection to check

Clock Generator and related
small components are not
damaged.
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Repair Technique-
Technique-Measure Vcc_CLK
Use Multi-Meter or
Oscilloscope to measure
Clock voltage 3
3.3V
3V is ok.
ok
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Repair Technique
Technique--Measure CLK X’TAL
Use Oscilloscope to measure

Clock X’TAL 14.318Mhz is ok.
3-1
3-2
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Repair Technique
Technique--Check Individual NG signal
Use O
U Oscilloscope
ill to
t measure
every individual CLK signal.
If find error please trace the
circuit to find it
it’ss connection
connection.
If related RLC components

4 are ok but CLK still is NG
please try to change CLK
generator at last.
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95
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Power On Sequence
ASUS Confidential
Outline
1.General Power On Sequence

2.Power On Sequence with Reset (General)
3.Power On Sequence with Reset (W/ASUS ASIC)
4 Power On Sequence with Reset (P5GD1 Sample)
4.Power
5.Advanced Configuration and Power Interface
6.Power On Sequence with Reset (P4P800 Sample)
7.No Power Problem Debug Point
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PSON# Hi
ATX
TOP VIEW
+5 + 12 PWRBTN PANNEL
5VSB to 3VSB Cap./ 3VSB
+5 5VSB
Linear Reg. Res.
-5
1/0
PWOK 5VSB 1
GND GND 1
GND + 5
GND GND
0
PSON + 5
GND GND
ASIC
IT8282
- 12V + 3V
+ 3V + 3V
PSON
PSON Pull low circuit
PWRBTN
Super I/O
0 0
South
Bridge
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PSON# Low
+5 + 12
+5 5VSB CPU SOCKET
-5 PWOK
(2)
CPURST (5)
GND GND
PG1
GND + 5
IDERST
GND GND
Circuit IDE SLOT
PSON + 5 PWROK (4)
(3) PCIRST
GND GND
PCI SLOT
- 12V + 3V North Bridge
+ 3V + 3V
Circuit
PSON
South Bridge
(1)
PANNEL
PWRBTN
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Power On Sequence with Reset (P5GD1 Sample)
CPURST# PLTRST#
(10)
GMCH (8)
User press
Ctrl+Alt+Del PWROK Power
(7)
PSON
User press (6)
Power button PWRBTN#
Super IO IDE
PLTRST#
(3)
(9)
PWRBTN#_SB
RSMRST# IO_PWRBTN#
SLP_S3# SLP_S4# PWROK
(2) (4)
(5) (5) (7)
PCIRST#
(8)
ICH6 PCI
User Clear
CMOS RTCRST#
(1)
CPUPWRG
PLTRST#
CPU D
((8))
GB L
Lan PCI-EX16
1. When +5VSB is good, SIO send out RSMRST#. FWH PLTRST#
(9)
2. When RSTCON#_SIO is sent,, SIO send
PWRGD/PWROK to notice SB.
1394 PCI-EX1
3. When SLP_S3# is sent by SB, SIO will drive PSON#
High, then Power Supply will cut off main power. 100
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Power On Sequence (P5Q3 Sample)
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Power On Sequence (P6T Sample)
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M3N78--VM Power On Sequence
M3N78
14. CPU_RST#
13. PCI_RST#
CPU PCI SLOT 1,2
12. CPU_PWROK# 13. PCIE_RST#
10. 1.2VHT_EN
MCP78 PCIE X1
9. VCORE_PG
8. VCORE_EN
7 11 3
.PW 4 4 1
.SIO
.SIO
.SU
.SU
.RS
WROK_SB
O_RST#
O_PWRBTN
USB#
USC#
SMRST#
VRM
6. 12V
N#
6. 3V 6. 5V
ATX PCIE X16

SIO 13.PCIERST#
Power ITE8712F
5. PSON# IDE Port
11. IDE_RST#
103 2. PWR_BTN#
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M4A79 Deluxe Power On Sequence
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No Power Problem Debug Point
POWER UP PROBLEM
1. Check if any burned components or traces
2. Check no voltages
g short with GND such as +5,, +12 , +5VSB,,
+3, -12, +3VSB, VCORE 1.5V, 2.5V
3. Check Battery voltage
4. Check X’tal 32.768 KHz
5. Check 5VSB ,3VSB, PWRBTN#
6. Check PSON signal & related circuit
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PS/2
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Outline
1.Diagram
g
3.Repair Flow Chart
4.Repair Technique
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PS/2 Diagram
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Signal Description (PS/2 Mouse)
Pin Define Signal Description

1 Data Data signal
2 N/C Not connection
3 GND Ground signal
g
4 VCC Power signal (+5VDC)
5 CLK Clock signal
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Signal Description (PS/2 KB)

1 Data Data signal
3 GND Ground signal
4 VCC Power signal (+5VDC)
5 CLK Clock signal
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Repair Flow Chart
START
Visual Inspection NG Change NG PS2 Connector, OK

Check Connector. RLC components RLC components,
& PS2 Jumper and Mount PS2 Jumper
NG
OK
Measure PS2 NG Check PS2 Jumper is ok, Change NG PS2 Jumper,

5V_Dual
V D l is
i correct 5V Dual trace is not open
5V_Dual open, fix the open trace or
inductor is ok. change NG inductor
OK
OK NG
Measure the bias value of Change NG RLC

Measure PS2 CLK
CLK & DATA signals, trace NG components or fix any
& Data signal is OK OK
signal’s connection. pcb open
NG
Change Super I/O or SB
Finished
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113
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USB
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Outline
1.Diagram
g
3.Repair Flow Chart
4.Repair Technique
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USB Diagram
South
S th
Bridge
EX : R = 0 OHM
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Signal Description

1 VBUS Power signal
2 D- Data signal
3 D+ Data signal
4 GND G
Ground
d signal
i l
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Repair Flow Chart
START
Visual Inspection Check OK

Change Defect
Connector & Pins No
Connector
Damaged.
NG
OK
Check USB 5V Jumper,
Check USB 5V (SB) Change Defect
Related Trace
Trace, Fuse
Fuse,
--VBUS(USB Vcc) Component
Inductor.
NG
Check 48 Mhz OK
Check USB 48Mhz at Change Defect
Related CLK Gen,
Clock Generator Component
Resistor, Trace
NG
Check USB-,USB+ OK
Change Defect
Check USB-, USB+ Signals Related SB, Resistor,
Component
Capacitor, Trace
Finished 118
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Repair Technique-
Visual inspection check

USB connector
appearance and inside
pins no damaged, USB
5V(SB) jumper is
mounted.
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Repair Technique-
Technique-Check USB 5V_Dual
Use Multi-meter to check USB 5V

Vcc ((5V_Dual)
_ ) is correct.
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Repair Technique-
Technique-Check CLK_USB
Check USB CLK 48Mhz from

CLK Generator.
3-1
3-2
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Repair Technique-
Technique-Measure USB
USB--,USB+
Use Multi-meter to measure USB-,,

USB+ bias voltage value. The
value should be the same. If you
find the value is high,
g , please
p
check related resistor or inductor
is ok & trace is not open. If the
4-1 value is low please check there’s
no component short or SB short.
If the problem is still existing

after you check above, please try
to change South Bridge.
Bridge
4-2
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Most of USB problems caused by USB 5V Vbus (Vcc) is not

correct. Sometimes we can find inductor bad, trace burned or
forgot to mount USB jumper.
If You’ve checked USB 5V,, 48Mhz,, USB- & USB+ signals
g but
can’t find unusual root cause, please try to change South Bridge.
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COM Port
ASUS Confidential
Outline
1.Diagram
g
3.Repair Flow Chart
4.Repair Technique
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COM Diagram
EX : Visual Inspection first
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Signal Description
9 Pins
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Repair Flow Chart
START
Visual Inspection
Change NG connector
Check Connector & NG Ok
& damaged RLC
RLC components
components
Ok
Enable Com port

Check Bios setting , NG Ok
setting in the Bios,
COM Port is enable make sure there is no
conflict.
Ok
Measure COM controller Check +5V, +12V,-12V NG Change NG R.L.C.

NG trace is not open, Ok
Power included+5V, +12V, components. Fix any pcb
-12V is correct inductor is OK trace open
Ok Ok
Ok
Use meter to measure Check NG signal Change NG NG Change

Signal’s bias voltage value NG connect to which array array COM
is ok capacitor capacitor controller
Ok
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129
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Print Port
ASUS Confidential
Outline
1.Diagram
g
3.Repair Flow Chart
4.Repair Technique
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Print Diagram
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Repair Flow Chart
START
Visual Inspection Change NG connector

Ch t OK
Check Connector & NG
& damaged RLC
RLC components components
OK NG
Check Bios setting , NG Enable LPT port & OK

LPT Port is enable change to “EPP”mode
t EPP mode
to d in the Bios.
Bios
OK NG
NG Change NG inductor & OK

Measure LPT Check inductor & fuse
power 5V is correct is ok, trace is not open. fuse. Fix any open trace.
OK NG
Use meter to measure NG Check NG signal Change NG array NG OK

Change
Signal’s bias voltage value connect to which array capacitor & Super I/O
is ok capacitor & resistor resistor
OK
133
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FDD
ASUS Confidential
Outline
1.Diagram
g
3.Repair Flow Chart
4.Repair Technique
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Diagram
1 3 5……………………… 33 GND
2 4 .……………………… 34 Pi 8 26 28 30 34
Pin8,26,28,30,34
…
+5V
S
Super I/O
Clock RN
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Repair Flow Chart
START
Visual Inspection to check NG Change NG connector, re-

OK
Connector is no damaged, solder NG soldering point,
Soldering is ok. test again
OK
Load set up default/ Load bios default OK

NG
check
h k FDD item
it is
i enable
bl /Enable FDD setting in
in the bios the bios, test again
OK NG
Use meter to measure NG If find improper signal, Try to find out if there is
OK
signals bias voltage value trace the circuit any trace open or short,
Compare with good MB connection to I/O. if not, change I/O
OK
Change Super I/O,

SC
138
Finished
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139
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IDE
ASUS Confidential
Outline
1.Diagram
g
3.Repair Flow Chart
4.Repair Technique
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Diagram
South Register
Bridge
g Network Super
p I/O
IDE Reset Circuit
Pin1 : Reset Signal

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Repair Flow Chart
START
Visual Inspection to check NG Change NG connector, re- OK

Connector is no damaged, solder NG soldering point,
Soldering is ok. test again
OK NG
Load set up default NG Load setup default and

OK
in the bios/ update bios update to latest bios if
to latest version can’t detect new HDD.
NG
OK
Use meter to measure NG Trace NG signals, check Change NG resistor,

OK
signal’s bias voltage value, compare the trace & related fix any trace open
with good MB. resistors are ok or short.
NG NG
Ch
Change SB
143
Repair Technique-

IDE connector is no
damaged, soldering points
are ok.
1-1
1-2
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Repair Technique-
Technique-Check Bios
Load
L d Bios
Bi setupt
default, update to the
latest Bios version
before testing
testing.
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Repair Technique-
Technique-Measure IDE signals
Use multi-meter to measure

signal’s bias voltage value.
Compare with good MB.
If the value is high please
check
h k related
l t d trace
t is
i nott
open, related resistor is ok &
SB is not poor soldering.
If the value is low check the
3 trace is not short, the resistor
is ok & SB is not short.
If above way is not the real

root cause please try to
change SB.
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147
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SATA
ASUS Confidential
Outline
1.Diagram
g
3.Repair Flow Chart
4.Repair Technique
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Diagram
South
Bridge
C C C C
Pin3 Pin5
Pin2 Pin6
Pin1
Pin4 Pin7
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Signal Description
Pin1……………Pin4……………….Pin7
S1 Gnd
Sig
S2
gnal Se
A+ Si
Signal
l liline(pair
( i A)
S3 A- Signal line(pair A)
S4 Gnd
egmen
S5 B+ Signal line(pair B)
S6 B- Signal line(pair B)
nt
S7 Gnd
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Repair Flow Chart
START
Visual Inspection to NG OK
Change NG connector,
check SATA connector is
no damaged Test again
NG
OK
Check CLK CK_SATA_SB,

_ _ , NG If no CLK check CLK OK
CK_SATA_SB# from G
Generator & related
l d
Clock generator trace. resistors.
NG
OK
Use meter to measure Trace to check related OK

NG
signal’s bias voltage value, compare R.L.C. components
with good MB. and circuit trace.
NG
OK
Change SB
152
Repair Technique-

SATA connector is not
damaged.
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ASUS Confidential
Repair Technique-
Technique-Measure SATA CLK
Measure SATA CLK from

CLK Generator.
2-1
2-2
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Repair Technique
Technique--Measure SATA signals

SATA signals (A+ & A- , B+ & B-)
Trace the circuit to SB if any
signal is error. If there is no
trace short or open
p please
p try
y
to change SB.
3
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Q & A ( Repair Experience)
156
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RAID
ASUS Confidential
Outline
1.Diagram
g
3.Repair Flow Chart
4.Repair Technique
158
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Raid Diagram
3V
South
Bridge IT7212F
PCI Bus
33.3Mhz
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ITE 8212F Diagram
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Repair Flow Chart
START
Visual Inspection NG Change any damaged OK

check Raid connector & controller are
connector or controller
Not damaged.
OK NG
NG Enable Raid setting in OK

Check Bios setting the Bios
OK NG
NG Check Raid 3V is ok if Fix any trace open or OK
Measure Raid Voltage NG trace the circuit. RLC damaged
OK NG
NG Check Raid CLK Fix any trace or RLC

Measure Raid Clock 33.3Mhz if NG trace the damaged/ Change NG OK
circuit. CLK Generator
OK
NG
NG Measure AD signals Fix any trace/ remove OK
Measure PCI AD signals compare with good MB any NG PCI device
OK NG
G
OK
Change Raid Chip
NG
161
Change SB
Repair Technique-

Raid connector, chipp and
related trace, component is
not damaged.
1
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Repair Technique-
Technique-Check Bios setting
Check Raid setting is enable

in the Bios.
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Repair Technique
Technique--Measure Raid Voltage
Use Multi-Meter to measure

Raid voltage.
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Repair Technique-
Technique-Measure Raid Clock
Use Oscilloscope to
measure Raid clock
(33.3Mhz).
4-1
44-22
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Repair Technique
Technique--Measure other signals

Raid AD signals bias voltage
value.
Due
ue to Raid
a d AD signals
sg asa are
e
connect to “PCI” AD signals,
we can also use PCI signal
measure card to measure AD
51
5-1
signals will be easier (Fig. 3-2).
If still
till cannott fi
find
d any
abnormal please try to
change Raid controller and
check other device under
PCI bus.
52
5-2 after change Raid controller
please change SB at last.
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AGP
ASUS Confidential
Outline
1.Diagram
g
3.Repair Flow Chart
4.Repair Technique
169
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AGP Diagram
Voltage
Clock
RAG R AG
P66M PC B7
LK
Clock
66M
Gen. Hz
C C
AGP
Slot
Add and Data
AGP 8X MCH
AGP BUS
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Voltage
g and Clock
1.Check Voltage： 2.Check Clock：
Pi #
Pin# V lt
Voltage Pi #
Pin# V lt
Voltage Pi #
Pin# F
Frequency
A1 +12V B24 3Vaux B7 66MHz
A9 VCC3.3V B25 VCC3.3V
A16 VCC3.3V B28 VCC3.3V
A25 VCC3.3V B34 Vddq1.5V
A28 VCC3.3V B40 q
Vddq1.5V
A34 Vddq1.5V B47 Vddq1.5V
A52 Vddq1 5V
Vddq1.5V B58 Vddq1 5V
Vddq1.5V
A64 Vddq1.5V
B2 +5V
B3 +5V
B9 VCC3.3V A mean “Left”,
Left , B mean “Right”
Right
B16 VCC3.3V
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Resistor of AD Signal
g
Pin Name Pin# Pin Name Pin#
AD[00] A65 AD[16] A39
AD[01] B65 AD[17] B38
AD[02] A63 AD[18] A38
AD[03]
[ ] B63 AD[19]
[ ] B36
AD[04] A62 AD[20] A36
AD[05] B62 AD[21] B35
AD[06] A60 AD[22] A35
AD[07] B60 AD[23] B33
AD[08] B57 AD[24] A30
AD[09] A56 AD[25] B30 A mean “L

“Left”,
ft”
B mean “Right”
AD[10] B56 AD[26] A29
AD[11]
[ ] A54 AD[27]
[ ] B29
AD[12] B54 AD[28] A27
AD[13] A53 AD[29] B27
AD[14] B53 AD[30] A26
AD[15] A51 AD[31] B26

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Control Signal
g
1.Check Control Signal：
Pi Name
Pin N Pi #
Pin#
FRAME# A41
IRDY# B41
TRDY# A46
STOP# A47
DEVSEL# B46 A mean “Left”, B mean “Right”
RST# A7
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Repair Flow Chart
START
NG Check AGP slot no pin Change NG AGP slot, fix

Vi
Visual
l Inspection
I ti bent, pcb trace no burn any trace if burn out
OK NG OK
NG
Check 1.5 V, 3.3V ,5 Trace error voltage to
Measure Voltage V ,12 V is correct change any NG regulator.
OK NG OK
NG If no AGP CLK or error, Trace error CLK to

Measure AGP CLK- trace the connection to change NG CLK Gen. or
66Mhz CLK gen. resistor near the CLK.
OK NG OK
NG
Check AD bias voltage
Measure Address/Data Trace error signal to find
value & control signals
Control signals out any trace open, fix it
are ok
OK
OK NG
Change NB Finished
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Repair Technique-

there is no bent pin inside
AGP slot. Check the trace is
not open near AGP slot and
back side.
1
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Repair Technique-
Technique-Measure Voltage
Check AGP voltage is ok

included in 1.5V, 3.3V, 5V, 12V.
Pin# Voltage
A1 +12V
B2 +5V
A9 VCC3.3V
A34 Vddq1.5V
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Repair Technique-
Technique-Measure CLK
Use oscilloscope to check

AGP CLK 66Mhz is correct,
if NG trace the circuit to
CLK Generator.
3-1
Pin# Frequency
B7 66MHz
3-2
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Repair Technique
Technique--Measure AGP signals
Use Multi
Multi-meter
meter to check
address / data line (AD) &
control signals (refer to
P13 14) , if find error please
P13,14)
trace the circuit to North
Bridge.
4 If the trace is no open or

short, try to change North
Bridge.
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1. Some models 1.5Vddq error cause AGP no display (like

P4P800 series).
2. Sometimes if no 12V on AGP slot we’ll find AGP fan is not
rotating.
g
3. Some AGP no display problem caused by NB poor soldering,
we can try to press NB and confirm again.
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On Board VGA
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Outline
1.Diagram
g
3.Repair Flow Chart
4.Repair Technique
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On Board Diagram - 1
8 pins from North Bridge.
R G,
R, G B,
B
+5V,
HSYNC VSYNC,
HSYNC, VSYNC
SDATA, SCLK
North
Bridge
g
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On Board Diagram - 2
R G
R, G, B
+3V
HSYNC,
VSYNC
North +5V
Bridge +5V
+3V
SDATA,
183
SCLK
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Repair Flow Chart
Visual Inspection NG OK
START check VGA connector Change NG component
no damaged
OK
Clear CMOS, NG Clear CMOS or change OK

Load Default/ Bios change bios to test again
OK
NG
Confirm the problem
RGB color error problem Is color error or No display /other problem
No display
Use multi-meter to measure Use multi-meter to measure

which color signal is error. onboard VGA CLK/DATA,
Trace the connection. HSYNC/ VSYNC signals.
Confirm the problem is Confirm the problem is

caused by RLC components Change NB caused by RLC components
Or NB Or NB
Change NG RLC Change NG RLC or

components. Finished related 74XX logic IC
184
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Repair Technique-

VGA connector is no pin
bent, the connector is no
damaged.
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Repair Technique
Technique--Load Default / Check Bios
If onboard VGA is no display,

please clear CMOS, load Bios
default at first. If no use, please
try to change Bios.
2
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Repair Technique
Technique--Measure VGA signals
Check the problem belongs to (i) RGB
color error problem (ii) No display
or display error problem.
(i) RGB color error problem please

use multi-meter to measure which
color (R.G.B.) signal is error.
Trace the connection to confirm
related inductor or capacitor
p is ok.
3-1 If it’s not caused by R.L.C.Q. small
components please change NB.
(ii) No display or display error (not

included color error). Use the
meter to measure bias voltage
value on VGA CLK & DATA ,
VSYNC & HSYNC. Trace the
connection to confirm related
R C L Q and
R.C.L.Q. d 74
74xx llogic
i IC is
i ok.
k If
3-2 all check items are no problem
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187 please change NB.
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Audio
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Outline
1.Diagram
g
3.Repair Flow Chart
4.Repair Technique
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Diagram
South
Bridge AC97 codec
5-pin serial data transaction :

BIT_CLK, SYNC, RESET,
SDATA_IN, SDATA_OUT
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H/W Architecture (1)
AC Li k bus
AC-Link b isi the
th pathway
th that
th t codec
d communicate
i t with
ith controller.
t ll
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AC--Link Bus
AC
AC-link bus is a 5-wire digital serial interface.
The codec derives its clock internally from an externally attached
24.576MHz crystal.
The codec drives the BIT_CLK with 12.288MHz (half of
24.576MHz). )
The clock of SYNC signal, driven by the controller, is 48kHz
(BIT_CLK/256).
SDATA IN and SDATA_OUT
SDATA_IN SDATA OUT are used to transfer digital audio
data between controller and codec.
RESET# is an asynchronous master reset signal for codec driven
by controller (# means active if driving low)
low).
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Package and Pinout
The standard industry package for AC’97 is 7mm x 7mm 48-pin
LQFP.
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The Difference between AC97 & HD AUDIO
195
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Repair Flow Chart
START
OK
Visual Inspection fix any trace or
fi
check no phys. damaged damaged component
OK NG
Enable
E bl Audio
A di setting
tti iin Bios/
Bi / OK
Check Audio setting in the
Bios /check jumper Confirm jumper setting
OK NG
Check +5VA & +3V are Fix or change any R.C. OK

Check Audio Voltage
ok L.Q. related to Voltage
OK NG
Check Audio CLK Change any component OK

Check Audio Clock
24.576Mhz or 14.3M related to CLK
OK NG
OK
Use meter to compare Change any component
Measure other Audio signals
other Audio signals related to NG signal
OK NG
OK
Change Audio chip
NG
196
Change SB
Repair Technique-
Visual Inspection to check Audio

connector, Audio chipp & nearby
y
related components are not
damaged.
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Repair Technique-
Technique-Check Bios & Jumper setting
Check Audio setting is

enable in the Bios.
2-1
Make sure Audio

Jumper is mounted
properly.
2-2
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Repair Technique
Technique--Measure Audio Voltage
Use Multi-Meter to measure AUD

+5V & 3.3V.
P.S. Audio +5V is transferred by

g
small regulator like 78L05 (+12V
(
3-1 to AUD+5V)
33-22
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Repair Technique
Technique--Measure Audio Clock

Audio CLK 24.576Mhz (from
X’TAL) or 14.318Mhz (from
CLK Generator)
4-1
4-2
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Repair Technique
Technique--Measure Audio signals

other Audio signals’
signals bias
voltage value.
(This method should be
comparedd with
ith good
d MB)
If the symptom is still existing
please try
p y to change
g Audio
5 chip.
After change Audio chip the
problem is still constant
please try to change SB at last.
P.S.
AC97 Audio chip through
AC97 link connect to SB.
HA AAudio
di chip
hi through
th h Azalia
A li
link connect to SB.
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202
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PCI
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Outline
1.Diagram
g
3.Repair Flow Chart
4.Repair Technique
204
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PCI
205
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PCI System
y Block Diagram
g
RAID TV
1394
Card
PCI Local Bus #0
LAN SCSI PCI tto PCI

Bridge
PCI Local Bus #1
206
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PCI Diagram
PCI BUS
South
S th
Bridge
Clock Signal
Clock
Gen.
PCI SLOT
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PCI Diagram
RN
PCLK1 B76
PCLK2 B76
PCLK3 B76
Clock
Gen.
C C C
Clock Circuit PCI 1 PCI 2 PCI 3
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Signal Description
AD[63:32]
[ ]
AD[31:0]
AD[31 0]
C/BE[7:4]#
Address & Data C/BE[3:0]
PAR64
PAR
REQ63#
FRAME#
ACK64#
IRDY#
Interface LOCK#
TRDY#
INTA#
Control STOP# PCI INTB#
DEVSEL#
IDSEL
Compliant INTC#
Device INTD#
PERR#
Error Reporting SBO#
SERR#
SDONE
REQ#
Arbitration TDI
GNT#
TDO
CLK#
System
y TCK
RST#
TMS
209 TRST#
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(1)System Pins
CLK
All other PCI signals, except RST#, INTA#, INTB#, INTC#, and
INTD#, are sampled on the rising edge of CLK and all other
timing parameters are defined with respect to this edge
edge.
RST#
Anytime RST# is asserted, all PCI output signals must be driven
t their
to th i benign t t RST# may be
b i state. b asynchronous
h tto CLK when
h
asserted or deasserted.
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(2) Address and Data Pins
AD[31::00]
[ ]
A bus transaction consists of an address phase followed by one
or more data phases. PCI supports both read and write bursts.
C/BE[3::0]#
During the address phase of a transaction, C/BE[3::0]# define
the bus command. During the data phase, C/BE[3::0]# are used
as Byte
B t Enables.
E bl
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(3)Interface Control Pins
FRAME# (Cycle Frame)
Driven by
y the current master to indicate the beginning
g g and duration of an
access.
IRDY# (Initiator Ready)
Indicates the initiating agent’s (bus master’s) ability to complete the current
d t phase
data h off the
th transaction.
t ti
TRDY# (Target Ready)
Indicates the target agent’s (selected device’s) ability to complete the current
data phase of the transaction.
transaction
DEVSEL# (Device Select)
Indicates the driving device has decoded its address as the target of the
current
cu e t access
access.
STOP#
Indicates the current target is requesting the master to stop the current
transaction.
IDSEL (Initialization
(I iti li ti D Device
i S Select)
l t)
Chip select during configuration read and write transactions.
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(4)Arbitration Pins
REQ#
Q
Indicates to the arbiter that this agent desires use of the bus.
This is a point-to-point signal. Every master has its own REQ#.
GNT#
Indicates to the agent that access to the bus has been granted.
This is a point-to-point signal. Every master has its own GNT#.
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(5)Interrupt Pins
Interrupts on PCI are optional and defined as

“l
“levell sensitive”,
iti ” ““active
ti llow”,” using
i open d drain
i
output drivers.
INTA# : Interrupt A is used to request an interrupt
interrupt.
INTB~D# : Interrupt B~D are used to request an interrupt and only has
mean on a multi-function device.
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Basic Arbitration
CLK
C
1 2 3 4 5 6 7 8 9
FRAME#
REQ#a
REQ#b
GNT#a
GNT#b
Address Data Address Data
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Basic Read
CLK
1 2 3 4 5 6 7 8 9
FRAME#
AD Address Data-1 Data-2 Data -3
C/BE# Bus CMD
IRDY#
TRDY#
DEVSEL#
Address Data Data Data

phase phase phase phase
Bus Transaction
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Basic Write
CLK
1 2 3 4 5 6 7 8 9
FRAME#
AD Address Data-1 Data-2 Data -3
C/BE# Bus CMD BE#-1 BE#-2 BE#-3
IRDY#
TRDY#
DEVSEL#
Address Data Data Data

phase phase phase phase
Bus Transaction
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Voltage
g and Clock
1.Check Voltage： 2.Check Clock：
Pi #
Pin# V lt
Voltage Pi #
Pin# V lt
Voltage Pi #
Pin# F
Frequency
A2 +12V B1 -12V B16 33MHz
A5 +5V B5 +5V
A8 +5V B6 +5V
A10 +5V(I/O) B19 +5V(I/O)
A16 +5V(I/O)
( ) B25 +3.3V
A21 +3.3V B31 +3.3V
A27 +3.3V B36 +3.3V
A33 +3 3V
+3.3V B41 +3 3V
+3.3V
A39 +3.3V B43 +3.3V
A45 +3.3V B54 +3.3V
A53 +3.3V B59 +5V(I/O)
A59 +5V(I/O) B61 +5V A mean “Left”, B mean “Right”
A61 +5V B62 +5V
A62 +5V
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AD Signal
Pin Name Pin# Diode Mode Pin Name Pin# Diode Mode
Sample Sample
AD[00] A58 .317 AD[16] A32 .317
AD[01] B58 .319 AD[17] B32 .319
AD[02] A57 .321 AD[18] A31 .321
AD[03] B56 .318 AD[19] B30 .318
AD[04] A55 .319 AD[20] A29 .319
AD[05] B55 .321 AD[21] B29 .322
AD[06] A54 .319 AD[22] A28 .319
AD[07] B53 .317 AD[23] B27 .318
AD[08] B52 .319 AD[24] A25 .317
AD[09] A49 .321 AD[25] B24 .319
AD[10] B48 .317 AD[26] A23 .321
AD[11] A47 .319 AD[27] B23 .323
AD[12] B47 .321 AD[28] A22 .319
AD[13] A46 .323 AD[29] B21 .321
AD[14] B45 .318 AD[30] A20 .319
AD[15] A44 .317 AD[31] B20 .318

ASUS Confidential
Control Signal
1.Check Control Signal：
Pin Name Pin#

FRAME# A34
IRDY# B35
TRDY# A36
STOP# A38
DEVSEL# B37
IDSEL A26
A mean “Left”, B mean “Right”
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Repair Flow Chart
START
Visual Inspection NG OK
Change any damaged
check PCI pin is not bent or
PCI connector
damaged.
OK
NG Check PCI Voltage 12V.- Fix any trace open or OK

Measure PCI Voltage 12V.5V.3V.3VSB RLC damaged
OK NG
NG
Fix any trace or RLC
Check PCI CLK OK
Measure PCI Clock damaged, change NG
33Mhz
CLK Generator
OK NG
NG Check AD0~31, Fix any trace open or OK
Measure PCI AD signals compare with good MB RLC damaged
OK NG
NG Check RST#,FRAME#, Fix any trace open or OK
Measure PCI control signals DEVSEL#,IRDY#..... RLC damaged
OK NG
Remove NG Device under
PCI /Change SB 221Finished
ASUS Confidential
Repair Technique-
Visual Inspection to check the

PCI connector is no pin bent
or broken.
broken
222
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Repair Technique
Technique--Measure PCI Voltage

PCI related voltages
g (+12V,
(
-12V,5V,3.3V)
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Repair Technique-
Technique-Measure PCI Clock
Use Oscilloscope to
measure PCI Clock =33Mhz
3-1
3-2
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Repair Technique
Technique-- Measure PCI other signals
Use Multi
Multi-Meter
Meter to measure
other PCI signals:
AD0~AD31(refer to P16)&
control signals ( FRAME#,
IRDY#, TRDY#.......(refer to P17)
4
Compare with good MB. If find
error trace the connection to
fi d any ttrace open or short.
find h t If
cannot find the root cause
please try to remove other
component under PCI bus and
change PCI controller-SB.
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226
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PCI E
PCI-E
ASUS Confidential
Outline
1.Diagram
g
3.Repair Flow Chart
4.Repair Technique
228
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PCI--E
PCI
229
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PCI--E X16 Diagram
PCI Diagram--1
B8,A9,A10 +3V
North
N th B10 +3VSB
Bridge
B1,B2,B3,A2,A3 +12V
PCI E *16 SLOT

PCI-E
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PCI--E X16 Diagram
PCI Diagram--2
R
Clock+ A13
Clock- A14
Clock
Gen.
Clock Circuit PCI-E *16
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PCI--E X1 Diagram
PCI
+12V (B1,B2,B3) +12V (A2,A3)
+3VSB (B10) +3V (A9,A10)
+3V (B8)
Clock (A13,A14)
South
Bridge
PCIE*1
PCIE 1
232
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Repair Flow Chart
START
Visual Inspection NG Change any damaged in

OK
check PCI-E pin is not bent or PCI-E connector
damaged.
OK
NG Check PCI Voltage Fix any trace open or OK

Measure PCI-E Voltage 12V.3V.3VSB RLC damaged
OK NG
NG Fix any trace or RLC OK

Check PCI-E CLK
Measure PCI-E Clock damaged, change NG
100Mhz
CLK Generator
OK NG
NG OK
Check TX /RX signals, Fix any trace open or
Measure PCI-E TX /RX signals compare with good MB RLC damaged
NG
OK
OK
Change NB(PCI-EX16) or
SB(PCI-EX1)
Finished 233
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Repair Technique-

PCI-E connector is not
damaged or bent pin inside.
1-1
1-2
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Repair Technique
Technique--Measure PCI
PCI--E Voltage

PCI-E working Voltages—12V,
3V, 3VSB.
2-1
P.S. We can use PCI-E X16

Signals Pin Out card to
measure.
P/N: 08
08-900036900
900036900
Name: ENG_PCI-E PIN
NAME R1.00
2-2
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Repair Technique
Technique-- Measure PCI
PCI--E Clock
Use Oscilloscope to
measure PCI-E CLK
=100Mhz
31
3-1
32
3-2
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Repair Technique-
Technique-Measure PCI-
PCI-E TX/RX signals
Use Multi
Multi-Meter
Meter to measure
PCI-E TX/RX signals,
compare with good MB.
If find error please trace the
circuit to check related
trace & RLC components.
4-1
If still can’t find any
abnormal
b l please
l try
t tot
change NB (PCI-E X16
controller) or SB (PCI-E X1
controller).
controller)
4-2
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238
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LAN
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Outline
1.Diagram
g
3.Repair Flow Chart
4.Repair Technique
240
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Diagram
(2.5VSB/
(2 5VSB/
1.2VSB)
3VSB
Reset
South Controller
Bridge IC
SMBus
SMB
3VSB
EEPROM
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Lan Head Signal Description
242
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Lan Chip Structure Diagram
243
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Sample--Realtek 8100C Pin Assignment Diagram
Sample
244
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Pin Description
Description--1
245
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Pin Description
Description--2
246
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Pin Description
Description--3
247
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Pin Description
Description--4
248
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Pin Description
Description--5
249
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EEPROM Pinout
AT24C08N
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What is MAC Address?
Each device connected to a standard LAN needs a Data Link Layer

address
dd ((or called
ll d h
hardware
d address),
dd ) providing
idi a means off unique
i
identification.
Each NIC has its unique, hard-coded MAC (Media Access Control)
address. It is a 48 bits (6 bytes) address written in a hexadecimal format.
The first 3 bytes represents for vendor ID and the remaining 3 bytes are
serial number.
MAC: 000C6E 7D3D0F

Vender ID Serial Number
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What is IP Address?
 Internet Protocol Address
 IP address = Network and Host ID Number
– An IP address is a unique software, logical address
assigned to each machine on an IP network.
– It was designed to allow a host on one network to
communicate with a host on a different network,
regardless of the type of LANs the hosts are
participating
p p g in.
 Two major categories of IP address type : 192.168.0. 3

– Static (Fixed) IP and Dynamic IP
Network Host
– Real IP and Private IP
Address Address
192.168.0. 2
Network
N k Host
H
Address Address
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Repair Flow Chart
START
Visual Inspection NG Change

g damaged
g OK
check Lan connector & related components
connector / component
are not damaged.
OK
NG OK
Check Lan Voltage Change NG transistor (Q)
Measure Lan Voltage 3VSB, 2.5VSB, 1.2SB.... or fix any trace open
OK NG
OK
NG Check Lan 25Mhz Change NG X’TAL /CLK
Measure Lan Clock & PCI CLK 33Mhz Gen. Fix any trace open
OK NG
NG
Check AD0~31, Fix any trace / remove any OK
Measure Lan AD signals compare with good MB NG PCI device
OK NG
NG
Change NG OK
Measure Lan Transformer Transformer
OK NG
OK
Change Lan Chip
NG
253
Change SB
Repair Flow Chart (Lan Mac ID error)
START
N
No Y
Yes
Mac ID error
Mac can be Check ?
NG OK
Re-write Mac ID
Check Lan EEPROM 3VSB
Re-check Mac ID again
Check & fix any
3VSB trace open NG
OK
OK
NG OK
Change EEPROM /
Change EEPROM / Re-Write Mac again
Re-Write Mac again
NG
NG
Go to check Lan
OK
(refer to previous Go to check Lan
page) (refer to previous page)
254 Finished
ASUS Confidential
Repair Technique-
Visual Inspection to check Lan

connector & related
components are not damaged
or burned.
b d
1-1
1-2
255
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Repair Technique-
Technique-Measure Lan Voltage
Measure Lan working voltage

3VSB, 2.5VSB,1.2VSB…
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Repair Technique-
Technique-Measure Lan Clock
Use Oscilloscope to check

Lan X’TAL 25Mhz & 33.3Mhz
(synchronization with PCI)
are ok.
k
3-1
3-2
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Repair Technique-
Technique-Measure AD signals

Lan AD signals bias voltage
value.
Due
ue to Lan
a AD s signals
g asa aree
4 measure card to measure AD
signals will be easier (Fig. 4).
If still cannot find any

y
abnormal please try to
check other device under
PCI bus.
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Repair Technique-
Technique-Measure Transformer Signals

Transformer signals. Some
signals should be connected
together (Show as Fig.5-2, the
signals
i l marked
k d orange color)
l )
If Transformer NG, please
55-11 changeg it .
If the
th problem
bl iis still
till existing
i ti
please change Lan controller
first.
If change Lan controller is NG
5-2
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260
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IEEE 1394
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Outline
1.Diagram
g
3.Repair Flow Chart
4.Repair Technique
262
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IEEE 1394 Diagram
X’TAL24.576Mhz
3V
South Controller
Bridge 1394
IC Connector
33.3Mhz
SMB
SMBus
3V
EEPROM
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IEEE1394 Introduction
A very fast external bus standard that supports data transfer rates
of up to 400Mbps (in 1394a) and 800Mbps (in 1394b)
1394b).
also called FireWire (Apple), iLink (Sony)
A single 1394 port can be used to connect up 63 external devices.
supports
t isochronous
i h d
data
t -- delivering
d li i d data
t att a
guaranteed rate. This makes it ideal for devices that
need to transfer high levels of data in real-time
real time, such
as video devices.
What devices are using 1394 interface?
 digital cameras, camcorders, printers, TVs, network cards
and mass storage devices.
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Comparison Table
Meaning Transfer rate Interface

IEEE1394 Apple: FireWire 100Mbps /
Sony: iLink 200Mbps /
400Mbps
USB Universal Low Speed Mode:

Serial 1.5Mbps
Bus Full Speed Mode:
12Mbps
High Speed Mode:
480Mbps
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1394a
It’s called FireWire in 1986 ((byy Apple

pp computer)
p )
It’s called I.Link in 1995 (by Sony)
Features: (IEEE 1394a)
 Scalable Performance (S100,S200,S400,etc.)
– S100=100Mbps; S200=200Mbps; S400=400Mbps
 Hot Plug
 Plug & Play
 Support for 63 Devices
 Peer-to-Peer Transfer
 Maximum Cable Length: 4.5m
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1394a Connector
6 Pi
Pin
4 Pin
267
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1394b
Features: (IEEE 1394b)

 Compatible
C tibl with
ith IEEE 1394
1394a
 Scalable Performance
– 800Mbps
– 1.6Gbps
 Add a plug for 9 pin
 Cables Defined
– 9 pin to 9 pin
– 9 pin to 6 pin
– 9 pin to 4 pin
 Cable material
– POF (Plastic Optic Fiber)
– GOF (Glass Optical Fiber)
 Scalable Cable Length
– 4.5m
– 50m
– 100m 268
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1394b Connector
9 Pin
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1394 chip –TSB43AB22A Diagram
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Repair Flow Chart
START

check 1394 connector & controller are
connector or controller
not damaged.
OK NG
NG Enable 1394 setting in OK

Check Bios setting the Bios
OK NG
NG Check 1394 3V(5V) if Fix any trace open or OK
Measure 1394 Voltage NG trace the circuit. RLC damaged
OK NG
NG Fix any trace or RLC OK

Check 1394 CLK damaged/ Change NG
Measure 1394 Clock 24.576&33.3Mhz X’TAL/CLK Gen.
OK
NG
NG Fix any trace/ remove OK
Measure AD signals
Measure PCI AD signals any NG PCI device
compare with good MB
OK NG
G
OK
Change 1394 Chip
NG 271
Change SB
Repair Technique-

1394 connector, controller &
related small component is not
damaged.
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Repair Technique-
Technique-Check Bios setting
Check 1394 setting is

enable in the Bios.
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Repair Technique
Technique--Measure 1394 Voltage

1394 working voltage 3V,5V
(depends on different chip)
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Repair Technique-
Technique-Measure 1394 Clock
Use Oscilloscope to check

1394 X’TAL 24.576Mhz &
33.3Mhz (synchronization
with
ith PCI) are ok.
k
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Repair Technique-
Technique-Measure AD signals

1394 AD signals bias voltage
value.
Due
ue to 1394
39 AD s signals
g asa aree
measure card to measure AD
5 signals will be easier (Fig. 5).
If still
till cannott fi
find
d any
abnormal please try to change
1394 controller and check
other device under PCI busbus.
after change 1394 controller,
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Memory
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Outline
Introduction
1.SDRAM
2.DDR
3 DDR II
3.DDR
4.DDR III
5.Repair Flow Chart
6.Repair Technique
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Introduction
What is memory anyway?

All computer
t functions
f ti have
h common features
f t
 Data processing (CPU, GPU….)
 Data storage (CDR, HDD, Memory…)
 Data movement (FSB, PCI-E, USB….)
 Control (North Bridge, South Bridge…)
Why memory improve performance?
 CPU runs much more faster than HDD.
If all data & application were stored in HDD.
C
CPU will always wait ffor HDD to pass data.
 Bottle neck in HDD, CPU idle most of the time
 Memory y enhance the usage g of CPU.
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Introduction
Static RAM (SRAM)

 Faster, more expensive
 Need not to be recharged regularly like DRAM
 Cache
Dynamic RAM (DRAM)
 Less expensive, need to be refreshed
 DRAM subtypes to be introduced
– Synchronous DRAM (SDRAM)
– Double Data Rate Synchronous DRAM (DDR)
– Double Data Rate 2 Synchronous DRAM (DDR2)
– Rambus DRAM(RDRAM)
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Introduction
Memory Module (SDR)
North
B id
Bridge
Type 1
Main Clock Gen
Gen.
Memory Module (DDR)
North
Bridge
M i Cl
Main Clock
kGGen. Type 2
DDR Clock Gen.
Memory Module (DDR, DDR2)

North
Bridge
Type 3
Main Clock Gen.
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Introduction
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Other important terms
 Error Correction Code (ECC)

data integrity checking method used primarily in high-end PCs and
file servers.
 Serial Presence Detect (SPD)
store information about the memory module.
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DDR
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DDR Basic
Short for Double Data Rate-Synchronous DRAM, a type of SDRAM

that supports data transfers on both edges of each clock cycle (the
rising and falling edges), effectively doubling the memory chip's
d t throughput.
data th h t
DDR-SDRAM also consumes less power, which makes it well-
suited to notebook computers. DDR-SDRAM is also called SDRAM
II and DDRAM.
DDRAM
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Throughput
PC1600 (DDR200)
-100(MHz)×2×8(Byte)
100(MHz)×2×8(Byte) = 1
1.6GB/S
6GB/S
PC2100 (DDR266)
-133(MHz)×2×8(Byte) = 2.1GB/S
PC 2700 (DDR333)
-166(MHz)x2x8(Byte) = 2.7GB/S
PC 3200 (DDR400)
-200(MHz)x2x8(Byte)
200(MHz)x2x8(Byte) = 3
3.2GB/S
2GB/S
D t strobe
Data t b signal
i l
(Double Data Rate) 200 / 266 / 333 / 400 MHz
100 / 133 / 166 / 200MHz
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DDR
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DDR II
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DDR2 Basic
DDR2 SDRAM (Double Data Rate Two Synchronous Dynamic
Random Access Memory)
The advantage of DDR2 over DDR SDRAM is its ability to run at
much higher clock speeds due to an improved electrical interface.
Like DDR,, DDR2 will transfer data on every
y rising
g and falling
g edge
g
of the clock (double pumped), achieving an effective rate of 200
MHz with the same clock frequency
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DDR2 Basic count.
DDR2 DIMM memory modules are not backward-compatible with

DDR DIMM , due
d to t incompatible
i tibl pin
i configurations,
fi ti core voltage,
lt
and memory chip technology.
DDR2 modules
d l are designed
d i d with
ith a different
diff t "key"
"k " in
i the
th edge
d
connector to prevent insertion into incompatible memory sockets
such as DDR motherboard. A DDR2 SDRAM DIMM will not fit into
a standard SDRAM DIMM socket or a DDR DIMM socket socket.
DDR2 modules use a 1.8V power supply, providing a big power

saving over the 2
2.5V
5V DDR modules
modules.
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DDR2
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DDR3
DDR3 SDRAM(Double
( Data Rate Three
Synchronous Dynamic Random Access Memory)
DDR3 SDRAM improves on DDR2 SDRAM in
several significant ways:
 Higher bandwidth due to increased clock rate
 Reduced power consumption due to 90nm fabrication
technology
 Pre-fetch buffer is doubled to 8 bits to further increase
performance
 The voltage of DDR3 SDRAM DIMM's was lowered from
1 8V to 1.5V.
1.8V 1 5V This reduces power consumption and heat
generation, as well as enabling more dense memory
configurations for higher capacities.
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DDR3
DDR3 SDRAM is normallyy p

packaged
g in DIMM modules.
DIMM Module Chip Type Clock Speed Data Rate
Transfer Rate
DIMM Transfer
Chip Type Clock Speed Data Rate
Module Rate
PC3-6400 DDR3-800 400 800 6,400
PC3-8500 DDR3-1066 533 1066 8,530
PC3-10667 DDR3-1333 667 1333 10,660
PC3-12800 DDR3-1600 800 1600 12,800
PC3-14900 DDR3-1866
DDR3 1866 933 1866 14 930
14,930
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Repair Flow Chart
START

check memory slot is no bent pin memory slot
or damaged.
NG
OK
Check memory Voltage Fix any voltage

NG OK
Measure memory Voltage 2.5V (1.8 or 3V) dual & regulator or small
Vtt inductor../trace open
OK NG
Fix any trace or RLC

Measure memory Clock NG Check memory CLK OK
damaged, change NG
100/133/166 Mhz
100/133/166..Mhz
CLK Generator
OK NG
Measure memory DQ / NG Compare with good MB, Fix any trace open or OK
Address,RAS#,CAS#,WE# trace NG signal resistor damaged
OK NG
Change NB
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Repair Technique-

memory slot is not damaged or
b
bent pin
i inside.
i id
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Repair Technique
Technique--Measure Memory Voltage
Use Multi-Meter or
Oscilloscope to measure
Memory Voltage.
2-1
Memory Voltage:
SDRAM: 3V Dual
DDR :2.5V Dual, 1.2Vtt_DDR
DDR2: 1.8 Dual, 0.8Vtt_DDR
2-2
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Repair Technique
Technique--Measure Memory Clock

Memory Clock (100Mhz or
133Mh 166Mh
133Mhz, 166Mhz…depends
d d
on different chipset &
memory)
31
3-1
3-2
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Repair Technique
Technique--Measure Memory Signals
Plug Memory measure card into

slot. Use Multi-Meter to measure
memory signals’ bias voltage
value. Compare with good MB if
you find any unusual.
4-1
1 ENG
1. ENG_RIMM
RIMM R1
R1.00
00 (SDRAM)
P/N: 08-900019700
2. ENG-DDR-DIMM184 TEST (DDR)
( )
P/N: 08-900019900
3. ENG_DDR2 PIN NAME 1.01(DDR2)
P/N: 08-900037800
4-2
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Repair Technique-
Technique-DDR measure
*Special Hint when we measure DDR signals*
When we use DDR measure tool to

measure DDR signals, need to add
an extra voltage
voltage. We can use one
9V battery across each probe (Red
connect +, Black connect--). The
reason is there are pull high array
resistors between North Bridge &
DDR slot. If without extra voltage
is not able to measure the signals
from slot to NB.
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Hardware Monitor
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Outline
1.Diagram
g
3.Repair Flow Chart
4.Repair Technique
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Diagram
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Clock Diagram (for super I/O)
Clock Signal R Clock Signal
??MHz C R
Clock Super I/O

Gen
Gen.
Clock Signal2 R
Clock Signa2l
??MHz C
Depends on difference chip

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Signal Description
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Theorem (Temp. Sense)
CPU Temperature
Super IO BIOS Menu
Super I/O
Motherboard Temperature
ASUS PC Probe
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Diagram Sample ( Temp. Sense)
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Repair Flow Chart (Temp. Sense)
START
NG Confirm CPU fan Change NG CPU fan or

OK
Check real CPU/ MB temp. is ok attached on the CPU is any NG R.C.L.Q. for fan
good, rotation is ok. power circuit
OK NG
Check Bios is ok
NG Change Bios if Bios is OK
NG
OK
Check VREF related Change any NG R.C.

NG OK
Check VREF is ok circuit, R.C. components
components are good
OK NG
NG Check Temp.
Temp sense
Check Temp. sense related Change any NG R.C. OK
related circuit, R.C.
circuit is ok components
components are good
OK
O NG
Change I/O (H.M.

controller) Finished
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Repair Technique (Temp. Sense)
1. Check real CPU or MB temperature is ok or not, if ok

change bios first; if NG check CPU fan rotation and
contact is good.
2 Check VREF (Reference Voltage)
2. Voltage). If NG check VREF
related resistor & capacitor(104P).
3. Check Temp. Sense signal (TR CPU or TR MB).
If NG check related resistor & capacitor.
4. If check above signals there’s nothing abnormal,
please try to change super I/O (Hardware Monitor
controller).
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Theorem (Fan Sense)
Chassis FAN
Super IO BIOS Menu
Power FAN
Super I/O
CPU FAN
ASUS PC Probe
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Diagram Sample (Fan Sense)
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Repair Flow Chart (Fan Sense)
START
NG Check fan power 12V Change NG transistor OK

Check real fan rotation is ok is ok for 12 V fan power
NG
OK
NG Change Bios if Bios OK

Check Bios is OK
cause Fan RPM error
NG
OK
NG Check Fan sense OK

Check Fan sense related Change any NG R.C.
related circuit, R.C.
circuit is ok components
t
components are good
NG
OK NG
Change I/O (H.M.

controller)
Finished
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Repair Technique (Fan Sense)
1. Check real fan rotation is ok or not, if NG check fan

12V related circuit. Especially check fan transistor
which provides fan 12V.
2 Check Bios is ok or not
2. not.
3. Check Fan Sense signal (CPU Fan, Chassis Fan,
Power Fan). If NG check related resistor & capacitor.
controller).
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Theorem (Voltage Sense)
BIOS Menu
Super IO
Super I/O
Power Supply
5V 12V 3 3V
5V、12V、3.3V ASUS PC P
Probe
b
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Diagram Sample (Voltage Sense)
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Repair Flow Chart (Voltage Sense)
START
Check Vcore circuit,

circuit Change NG power OK
Check real voltage is ok NG
power supply and supply. Cable or Vcore
(Vcore,3, 5, 12 V)
power cable is ok. related NG component
OK NG
Change Bios if Bios
NG OK
Check Bios is OK cause voltage detect
error
OK
NG Check VREF related Change any NG R.C.

OK
Check VREF is OK circuit, R.C. components
components are good
OK NG
NG Check Voltage sense Change any NG R.C.

Ch k Voltage
Check V lt sense related
l t d OK
related circuit, R.C. components cause
circuit is ok
components are good voltage detect error
OK
NG
Change I/O (H.M.
controller) Finished
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Repair Technique (Voltage Sense)
1. Check real voltage (Vcore, 3.3V, 5V ,12V )is ok or not,

if ok change bios first; if NG check Vcore related
circuit or check power supply (power supply cable
also included) is good
good.
2. Check VREF (Reference Voltage). If NG check VREF
related resistor & capacitor(104P).
3. Check Voltage Sense signal (12Vin, 5Vin, 3Vin..).
If NG check related resistor & capacitor.
controller).
controller)
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BIOS
ASUS Confidential
Outline
1.Diagram
g
3.Repair Flow Chart
4.Repair Technique
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Bios Pin Definition (Intel Sample)
LPC Bus
BIOS SIO
Voltage: +3V or +5v
SB
C
Clock: 33
33MHz
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Signal Description
Description--1
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Signal Description
Description--2
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Signal Description
Description--3
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Repair Flow Chart
START
Visual Inspection Check

Ch k Bi
Bios no pin
i is
i Change NG Bios
Ch Bi or NG
NG
check bios pin no damaged, damaged. Check the socket. Make sure the OK
socket is ok sock connection is ok. connection is ok
OK NG
NG
Check Bios Voltage Check Bios voltage Trace 3.3V voltage, fix OK
is ok 3.3V related circuit. any trace open.
OK NG
NG Check Bios PCLK Changeg NG CLK Gen,, OK

Check Bios CLK
33Mhz and related fix any trace open or
is ok
circuit. component damaged.
OK NG
Measure other control NG

Trace NG signal’s Fix any trace open or OK
Signals & LPC AD signals
are ok connection component damaged.
NG
G
OK
Change I/O,ASIC (bios 326
controller) or SB. Finished
ASUS Confidential
Repair Technique-

Bios & the socket is not
d
damaged.d
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Repair Technique-
Technique-Measure Voltage

Bios (PLCC) Voltage 3.3V
3 3V .
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Repair Technique-
Technique-Measure Bios PCLK
Use Oscilloscope to
measure Bios PCLK
(33Mhz)
3-1
P.S. Not every model pin31
connect to PCLK, other
models use for FWE#.
3-2
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Repair Technique-
Technique-Measure other Bios signals

other Bios signals( DQ.A…)
compare with good MB.
MB
If find error trace the

4 connection to I/O (Bios
Controller), ASUS ASIC or SB.
Try to change NG component.
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SMBUS
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Outline
1.Diagram
g
3.Repair Flow Chart
4.Repair Technique
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Clock Diagram
Clock
Speech
p ASIC Generator
Memory PCI-E
South
Bridge
SMBus
SMCK = 3.3V
3 3V
SMDA = 3.3V
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Repair Flow Chart
START
NG Check SMBUS jumper setting

Visual Inspection OK
check SMBUS jumper i good.
is d
mount is ok Change jumper if it’s oxidized
NG
OK
NG
Check NG signal’s connection,
Use meter to measure use elimination way
y to find out
th voltage
the lt off SMBUS CLK /Data,
/D t OK
Compare with good MB. which related component is
N.G. and change it.
OK
Finished
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Repair Technique-
Visual Inspection to
check SMBUS jjumperp
setting is ok.
1-1
1-2
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Repair Technique
Technique--Measure SMBUS signals

SMBUS CLK & SMBUS DATA,
the voltage should be 3.3V.
If the value is error, try to trace

the connection and check one
by one.
2
Most MB SMBUS signals
connect to CLK generator,
Memory & South Bridge.
If you have checked CLK

generator and other related
componentt but
b t still
till NG.
NG Please
Pl
try to change SB at last.
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POST Code
ASUS Confidential
Overview
What is POST Code
Using POST Code to Debug
Appendix:
(1) Award Bios Code Definition
(2) AMI Bios Code Definition
(3) Phoenix Bios Code Definition
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What is POST Code
POST : Power On Self Test

 The tag thrown out by BIOS
– Usually, BIOS would output some number through 80ports.
Using I/O access card (debug card)
card), user could read those
number.
– The POST codes used by Award, Phoenix, and AMI are
diff
different.
t
– These numbers mean something was executing in the
system.
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What is POST Code
POST Code as BIOS executing

g process
p
 Standard POST Code
– These numbers were used as standard process.
 BIOS Debug Code
– These numbers depend on various project.
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POST “00”, “FF”
POST Code “00”,”FF” or Debug card shows all dots(……) / all 00
(1)Check Voltage:
a)V_core, if no V_core check from power block circuit diagram
b)1.5v,if no 1.5v check from power block circuit diagram
c)2 5v if no 2
c)2.5v,if 2.5v
5v check from power block circuit diagram
d)3.3v,if no 3.3v check from power block circuit diagram
e)check for N/B,S/B voltage is ok or not
(2)Check CLK:
a)CPU CLK, if no CPU CLK check from CLK gen. circuit diagram
b)N/B CLK
CLK, if no N/B CLK check
h k ffrom CLK gen. circuit
i i di diagram
c)S/B CLK, if no S/B CLK check from CLK gen. circuit diagram
d)14.318MHz,if no 14.318MHz check from CLK gen. circuit diagram
e)CLK generator. if all no CLK, change 14.318MHz,and then change
CLK gen. Before must check any open or short
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(3)Check Power ok & Reset
a)H/W reset
reset, if low voltage check circuit diagram
diagram, normal is capacitor bad
b)power supply power ok, if low voltage, normal is capacitor bad
c)CPU power ok, if low voltage check circuit diagram, and above signal
d)PCI reset,
reset if low voltage check above signal and for S/B CLKCLK, voltage
e)CPU reset, if low voltage check above signal and for N/B CLK, voltage
f)Check boot up sequence.
(4)Check control signal:

a)Check CPU control signal(ADS#,BRDY#…) is ok or not
b)Check PCI control signal(FRAME#,IRDY#,TRDY#…) is ok or not
c)Check others control signal is ok or not
(5)Check Jumper setting:

a)Check USB jumper setting is ok or not
b)Check JEN jumper setting is ok or not
C)Check all jumper setting is ok or not
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00(no data)
(1)Change BIOS
(2)Check bios voltage
(3)Check BIOS CLK
(4)Check LAD0~3
(5)Check BIOS control signal
(6)Check CPU control signal
00(Have address & data)

((1)CPU
) N/B:HD0~63,HA3~HA31,control
, , signal
g open
p or short
(2)N/BS/B:PCI BUS(AD0~AD31,CBE0~CBE3) or HUB
Link(HL0~HL10) or V_link or LDT BUS open or short
(3)S/BBIOS:ISA BIOS(SA0~SA19
BIOS(SA0 SA19,SD0 SD0~SD7)
SD7) or LPC BUS
(LAD0~LAD3) open or short
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POST “C0”, “D0”
C0 (Award)
( )
D0 (AMI)
(1)Change BIOS
(2)Check HD0~63 signal open or short
(3)Check HA3~31 signal open or short
(4)Check AD0~31 signal open or short
(5)Check SM BUS is ok or not
(6)Ch k allll V
(6)Check Voltage
lt iis ok
k or nott ,especially
i ll 22.5V,3V
5V 3V dual
d l
(7)Check all CLK is ok or not
(8)Check jumper setting is ok or not
(9)Check SB
SB, especiall
especially for Intel ICH4
ICH4, 5
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POST “C1”, “9F”, “D3”, “EF”….
C1, E1, 9F, 99, Ad (Award)

D3 D4,
D3, D4 E0,
E0 E5,
E5 A4 (AMI)
EF, EE, 28 (Phoenix)
(1)Change BIOS
(2)Ch k M
(2)Check Memory CLK is
i okk or nott
(3)Check Memory voltage is ok or not, especially 2.5V, 3Vdual,
1.25Vtt
(4)Check SM BUS is ok or not
(5)Check MA,MD,CAS,RAS,CKE… signal is Open or Short
(6)DIMM socket not clean or bad
(7)Check HA,AD,CPU
HA AD CPU control signal is open or Short
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POST “C3”, “C5”, “C7”, “05”
C3 (Award)
(1)Change BIOS
(2)Check memory problem
(3)Check frequency problem
C5 (Award)
(1)Change BIOS
(2)Check memory problem
(3)Check HA3~31 is open or short
(4)Change super I/O
C7 (AMI)
((1)) Check K/B +5Vdual
05 (Award)
(1)Check super I/O CLK is ok or not
(2)Check super I/O voltage is ok or not
(3)Check super I/O address, data, control signal is open or short
(4)Change super I/O
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POST “0B”, “13”, “20”
0B (Award)
(1)Change BIOS
(2)Check battery is ok or not
(3)Check all CLK signal(14.318MHz,25MHz,40MHz….)
(4)Check all voltage is ok or not
(5)Ch k INIT,TRDY#,RADY
(5)Check INIT TRDY# RADY signal…i l iis open or short
h t
(6) Check C/BE0~3 is short or not
(7)Check all control signal(CPU,PCI,AGP) is open or short
13 (AMI)
(1) Check 1.5Vcc to NB ,especially Intel 865,875 series.
20 (AMI)
(1) Check 2.5V dual, 1.25Vtt
(2) Check Memory problems
(3) Check AGP signals
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POST ”18”, “31”,”3D”,”41”
18 (Award)
(1)Check D/C# is Open or Short
(2)Check HITM# is Open or Short
(3)Check NMI# is Open or Short
(4)Check INTR
INTR,LOCK
LOCK is open or short
(5)Check LINT0,1 is open or short
31,3D (Award)
(1)Check super I/O CLK is ok or not
(2)Check K/B problem
(3)Check CPU control signal(HITM#,ITIN,ITNK#…)is open or short
( )C
(4)Check N/B
/ control signal… is open or short
41 (Award)
(1)Change BIOS
(2)Check SA0~SA16 is Open or short
(3)Check MEMR#,MEMW# is open or short
((4)Check
) HA3~31 is open
p or short
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POST “4E”, “61”, “85”
4E (Award)
(1)Check TRDY#,DEVSEL# is open or short
(2)Check K/B problem
61 (Award)
(1)Check Cache problem
(2)Check CPU control signal is ok or not
(3)Check N/B control signal is ok or not
85 (AMI)
(1) Check Bios
( ) Check
(2) C NB ((No display problem))
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AWARD Bios Code Definition
Definition--1
Post (HEX) Descriptions
1.Turn
1 Turn off OEM specific cache
cache, shadow
shadow.....
2.Initialize all the standard devices with default values
Standard devices includes:
C0  DMA controller (8237)
 Programmable Interrupt Controller (8259)
 P
Programmable bl IInterval
t l Timer
Ti (8254)
 RTC chip
C1 Auto detection of onboard DRAM & Cache
1.Test the first 256K DRAM
C3 2.Expand the compressed codes into temporary DRAM area including the compressed system
BIOS & Option ROMs
C5 Copy the BIOS from ROM into E000-FFFF shadow RAM so that POST will go faster
01-02
01 02 Reserved
03 Initialize EISA registers (EISA BIOS only)
04 Reserved
1.Keyboard
y Controller Self-Test
05
2.Enable Keyboard Interface
06 Reserved
07 Verifies CMOS's basic R/W functionality
BE Program defaults values into chipset according to the MODBINable Chipset Default Table
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Definition--2
1.Program the configuration register of Cyrix CPU according to the MODBINable Cyrix
09 Register
g Table
2.OEM specific cache initialization
1.Initialize the first 32 interrupt vectors with corresponding interrupt handlers

Initialize INT No. from 33-120 with Dummy(Spurious) interrupt handler
0A
2.Issue CPUID instruction to identify CPU type
3.Early Power Management initialization (OEM specific)
1.Verify
1 Verify the RTC time is valid or not
2.Detect bad battery
3.Read CMOS data into BIOS stack area
0B 4.PnP initializations including (PnP BIOS only)
 Assign CSN to PnP ISA card
 C t resource map from
Create f ESCD
5.Assign IO & Memory for PCI devices (PCI BIOS only)
0C Initialization of the BIOS data area (40:0-40:FF)
1.Program some of the chipset's value according to setup.(Early setup value program)
2.Measure CPU speed for display & decide the system clock speed.
0D
3.Video initialization including Monochrome, CGA, EGA/VGA.
If no display device found
found, the speaker will beep
beep.
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Definition--3
1.Initialize the APIC (Multi-Processor BIOS only)
2.Test video RAM (If Monochrome display device found)
3.Show message including:
0E  Award logo, Copyright string, BIOS date code & Part No.
 OEM specific sign on messages
 Energy Star logo (Green BIOS only)
 CPU brand,, type
yp & speed
p
0F DMA channel 0 test
10 DMA channel 1 test
11 DMA page registers test
12-13 Reserved
14 Test 8254 timer 0 counter 2
15 Test 8259 interrupt mask bits for channel 1
16 Test 8259 interrupt mask bits for channel 2
17 Reserved
19 Test 8259 functionality
1A-1D Reserved
1E If EISA NVM checksum is good, execute EISA initialization(EISA BIOS only)
1F-29 Reserved
30 Get base memory & extended memory size
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Definition--4
1.Test base memory from 256K to 640K
31
2.Test extended memory from 1M to the top of memory
1.Display the Award Plug & Play BIOS extension message(PnP BIOS only)
32 2.Program all onboard super I/O chips(if any) including COM ports, LPT ports, FDD port...
according to setup value
33-3B Reserved
3C Set flag to allow users to enter CMOS setup utility
1.Initialise keyboard
3D
2.Install PS2 mouse
Try to turn on level 2 cache
3E Note: Some chipset may need to turn on the L2 cache in this stage. But usually, the cache is turn
on later in Post 61h
3F-40 Reserved
1.Program the rest of the chipset's value according to setup(Later setup value program)
BF 2.If auto configuration is enabled, programmed the chipset with pre-defined values in the
MODBINable Auto-Table
41 Initialize floppy
ppy disk drive controller
42 Initialize hard drive controller
43 If it is a PnP BIOS, initialize serial & parrallel ports
44 Reserved
45 Initialize math coprocessor
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Definition--5
46-4D Reserved
If there is any error detected(such as video,KB....), show all the error messages on the
4E
screen & wait for user to press <F1> key
1.If password is needed, ask for password
4F
2.Clear the Energy Star logo (Green BIOS only)
50 Write all the CMOS values currently in the BIOS stack ares back into the CMOS
51 Reserved
1.Initialize all ISA ROMs

2.Later PCI initializations(PCI BIOS only)
 assign IRQ to PCI devices
 initialize all PCI ROMs
3.PnP initializations (PnP BIOS only)
 assign IO, Memory, IRQ & DMA to PnP ISA devices
52
 initialize all PnP ISA ROMs
4.Program shadow RAM according to setup settings
5.Program parity according to setup setting
6.Power Management initialization
Enable/Disable global PM .
APM interface initializtion
1.If it is not a PnP BIOS, initialize serial & parallel ports

53 2.Initialize time value in BIOS data area by translate the RTC time value into a timer tick
value
54-5F Reserved
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Definition--6
Setup virus protection (Boot sector protection) functionality
60
according to setup setting
1.Try to turn on level 2 cache
Note: If L2 cache is already turned on in post 3D, this part will be
skipped
2.Set the boot up speed according to setup setting
61
3.Last chance for chipset initialization
4.Last chance for Power Management initialization (Green BIOS
only)
l )
5.Show the system configuration table
1.Setup daylight saving according to setup values
62 2 Program the NUM lock
2.Program lock, typmatic rate & typmatic speed according
to setup setting
1.If there is any changes in the hardware configuration, update the
ESCD information (PnP BIOS only)
63
2.Clear memory that have been used
3.Boot system via INT 19h
System booting
booting. This means that the BIOS already pass the control
FF
right to the operating system
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AMI Bios Definition-
Definition-1
01 Processor register test about to start,
and NMI to be disabled.
02 NMI is Disabled.
P
Power on d delay
l starting.
t ti
03 Power on delay complete.
Any initialization before keyboard BAT is in progress.
04 Any initialization before keyboard BAT is complete.
Reading keyboard SYS bit bit, to check soft reset/ power-on
power-on.
05 Soft reset/ power-on determined.
Going to enable ROM. i.e. disable shadow RAM/Cache if any.
06 ROM is enabled. Calculating ROM BIOS checksum, and
waiting
g
for KB controller input buffer to be free.
07 ROM BIOS checksum passed, KB controller I/B free.
Going to issue the BAT command to keyboard controller.
08 BAT command to keyboard controller is issued.
Going to verify the BAT command
command.
09 Keyboard controller BAT result verified.
Keyboard command byte to be written next.
0A Keyboard command byte code is issued.
Going to write command byte data data.
0B Keyboard controller command byte is written.
Going to issue Pin-23,24 blocking/unblocking command.
0C Pin-23,24 of keyboard controller is blocked/ unblocked.
NOP command of keyboard controller to be issued next.
0D NOP command d processing
i iis ddone.
CMOS shutdown register test to be done next.
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Definition-2
0E CMOS shutdown register R/W test passed.
Going to calculate CMOS checksum, and update DIAG byte.
0F CMOS checksum
h k calculation
l l ti iis d done, DIAG b byte
t written.
itt
CMOS init. to begin (If "INIT CMOS IN EVERY BOOT IS SET").
10 CMOS initialization done (if any).
CMOS status register about to init for Date and Time.
11 CMOS Status register initialized
initialized.
Going to disable DMA and Interrupt controllers.
12 DMA controller #1,#2, interrupt controller #1,#2
disabled.
About to disable Video displayp y and init p
port-B.
13 Video display is disabled and port-B is initialized.
Chipset init/ auto memory detection about to begin.
14 Chipset initialization/ auto memory detection over.
8254 timer test about to start.
15 CH 2 timer test halfway
CH-2 halfway.
8254 CH-2 timer test to be complete.
16 Ch-2 timer test over.
17 CH-1
CH 1 timer test over.
over
18 CH-0 timer test over.
About to start memory refresh.
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Definition-3
19 Memory Refresh started.
Memory Refresh test to be done next.
1A Memoryy Refresh line is toggling. gg g
Going to check 15 micro second ON/OFF time.
1B Memory Refresh period 30 micro second test complete.
Base 64K memory test about to start.
20 Base 64k memory test started.
Add
Address liline ttestt tto b
be d
done next.
t
21 Address line test passed.
Going to do toggle parity.
22 Toggle parity over.
Going for sequential data R/W test. test
23 Base 64k sequential data R/W test passed.
Any setup before Interrupt vector init about to start.
24 Setup required before vector initialization complete.
Interruptp vector initialization about to begin.
g
25 Interrupt vector initialization done.
Going to read I/O port of 8042 for turbo switch (if any).
26 I/O port of 8042 is read.
Going to initialize global data for turbo switch.
27 Global data initialization is over over.
Any initialization after interrupt vector to be done next.
28 Initialization after interrupt vector is complete.
Going for monochrome mode setting.
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Definition-4
29 Monochrome mode setting is done.
Going for Color mode setting.
2A Color mode setting is done.
About to go for toggle parity before optional rom test.
2B Toggle parity over. About to give control for any
setup required before optional video ROM check.
2C Processing before video ROM control is done.
Ab t to
About t look
l k for
f optional
ti l video
id ROM and d give
i control.
t l
2D Optional video ROM control is done. About to give control
to do any processing after video ROM returns control.
2E Return from processing after the video ROM control.
If EGA/VGA not found then do display memory R/W test. test
2F EGA/VGA not found.
Display memory R/W test about to begin.
30 Display memory R/W test passed.
About to look for the retrace checking.g
31 Display memory R/W test or retrace checking failed.
About to do alternate Display memory R/W test.
32 Alternate Display memory R/W test passed.
About to look for the alternate display retrace checking.
33 Video display checking over
over. Verification of display
type with switch setting and actual card to begin.
34 Verification of display adapter done.
Display mode to be set next.
35 Display mode set complete.
BIOS ROM data area about to be checked.
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Definition-5
36 BIOS ROM data area check over.
Going to set cursor for power on message.
37 Cursor setting for power on message id complete
complete.
Going to display the power on message.
38 Power on message display complete.
Going to read new cursor position.
39 New cursor p position read and saved.
Going to display the reference string.
3A Reference string display is over.
Going to display the Hit <ESC> message.
3B Hit <ESC> message displayed.
Vi t l mode
Virtual d memory ttestt about
b t to
t start.
t t
40 Preparation for virtual mode test started.
Going to verify from video memory.
41 Returned after verifying from display memory.
Going to prepare the descriptor tables
tables.
42 Descriptor tables prepared.
Going to enter in virtual mode for memory test.
43 Entered in the virtual mode.
Going to enable interrupts for diagnostics mode.
44 Interrupts enabled (if diagnostics switch is on). Going
to initialize data to check memory wrap around at 0:0.
45 Data initialized. Going to check for memory wrap around
at 0:0 and finding the total system memory size.
46 Memory wrap around test done. done Memory size calculation
over. About to go for writing patterns to test memory.
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Definition-6
47 Pattern to be tested written in extended memory.
Going to write patterns in base 640k memory.
48 Patterns written in base memory.
Going to find out amount of memory below 1M memory.
49 Amount of memory below 1M found and verified.
Going to find out amount of memory above 1M memory.
4A Amount of memory above 1M found and verified.
G i ffor BIOS ROM d
Going data
t area check.
h k
4B BIOS ROM data area check over. Going to check <ESC>
and to clear memory below 1M for soft reset.
4C Memory below 1M cleared. (SOFT RESET)
Going to clear memory above 1M 1M.
4D Memory above 1M cleared. (SOFT RESET)
Going to save the memory size.
4E Memory test started. (NO SOFT RESET)
About to display
p y the first 64k memory y test.
4F Memory size display started. This will be updated during
memory test. Going for sequential and random memory test.
50 Memory test below 1M complete.
Going to adjust memory size for relocation/ shadow.
51 Memory size adjusted due to relocation/ shadow
shadow.
Memory test above 1M to follow.
52 Memory test above 1M complete.
Going to prepare to go back to real mode.
53 CPU registers are saved including memory size.
Going to enter in real mode.
54 Shutdown successful, CPU in real mode. Going to restore
registers saved during preparation for shutdown.
ASUS Confidential 363
Definition-7
55 Registers restored.
Going to disable gate A20 address line.
56 A20 address
dd liline di
disable
bl successful.
f l
BIOS ROM data area about to be checked.
57 BIOS ROM data area check halfway.
BIOS ROM data area check to be complete.
58 BIOS ROM data area check over. over
Going to clear Hit <ESC> message.
59 Hit <ESC> message cleared. <WAIT...> message displayed.
About to start DMA and interrupt controller test.
60 DMA p page
g register
g test p
passed.
About to verify from display memory.
61 Display memory verification over.
About to go for DMA #1 base register test.
62 DMA #1 base register test passed.
About to go for DMA #2 base register test. test
63 DMA #2 base register test passed.
About to go for BIOS ROM data area check.
BIOS ROM data area check to be complete complete.
About to program DMA unit 1 and 2.
66 DMA unit 1 and 2 programming over.
About to initialize 8259 interrupt controller.
67 8259 iinitialization
i i li i over.
About to start keyboard test.
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Definition-8
80 Keyboard test started. clearing output buffer, checking
for stuck key, About to issue keyboard reset command.
81 Keyboard reset error/stuck key found
found. About to
issue keyboard controller interface test command.
82 Keyboard controller interface test over.
About to write command byte and init circular buffer.
83 Command byte y written,, Global data init done.
About to check for lock-key.
84 Lock-key checking over.
About to check for memory size mismatch with CMOS.
85 Memory size check done. About to display soft error
andd check
h k ffor passwordd or b
bypass setup.
t
86 Password checked.
About to do programming before setup.
87 Programming before setup complete.
Going to CMOS setup program
program.
88 Returned from CMOS setup program and screen is cleared.
About to do programming after setup.
89 Programming after setup complete.
Going to display power on screen message.
8A First screen message displayed. About to display
<WAIT...>message
8B <WAIT...> message displayed.
About to do Main and Video BIOS shadow.
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Definition-9
8C Main and Video BIOS shadow successful.
Setup options programming after CMOS setup about to start.
8D Setup options are programmed
programmed, mouse check and init
to be done next.
8E Mouse check and initialization complete.
Going for hard disk, floppy reset.
8F Floppy check returns that floppy is to be initialized.
Floppy setup to follow.
90 Floppy setup is over.
Test for hard disk presence to be done.
91 Hard disk presence test over.
H d di
Hard disk
k setup
t tto ffollow.
ll
92 Hard disk setup complete.
About to go for BIOS ROM data area check.
BIOS ROM data area check to be complete
complete.
Going to set base and extended memory size.
95 Memory size adjusted due to mouse support, hdisk type-47.
Goingg to verify
y from display
p y memory.y
96 Returned after verifying from display memory.
Going to do any init before C800 optional ROM control
97 Any init before C800 optional ROM control is over.
Optional ROM check and control will be done next.
98 Optional ROM control is done
done. About to give control to do
any required processing after optional ROM returns control.
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Definition-9
99 Any initialization required after optional ROM test over.

Going to setup timer data area and printer base address.
9A Return after setting timer and printer base address.
Going to set the RS-232 base address.
9B Returned after RS-232 base address.
Going to do any initialization before Co-processor test
9C R
Required
i d iinitialization
iti li ti b before
f co-processor is
i over.
Going to initialize the coprocessor next.
9D Coprocessor initialized.
Going to do any initialization after Co-processor test.
9E Initialization after co-processor test is complete
complete.
Going to check external keyboard, keyboard ID and num-lock.
9F External keyboard check is done, ID flag set. num-lock
on/off. Keyboard ID command to be issued.
A0 Keyboard
y ID command issued.
Keyboard ID flag to be reset.
A1 Keyboard ID flag reset.
Cache memory test to follow.
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Definition-10
A2 Cache memory test over.

Going to display any soft errors.
A3 Soft error display complete.
Going to set the keyboard typematic rate.
A4 Keyboard typematic rate set.
Going to program memory wait states.
A5 M
Memory waitit states
t t programming i over.
Screen to be cleared next.
A6 Screen cleared.
Going to enable parity and NMI.
A7 NMI and parity enabled
enabled. Going to do any
initialization required before giving control
to optional ROM at E000.
A8 Initialization before E000 ROM control over.
E000 ROM to g get control next.
A9 Returned from E000 ROM control. Going to do any
initialization required after E000 optional ROM
control.
AA Initialization after E000 optional ROM control is over.
Going to display the system configuration
configuration.
00 System configuration is displayed.
Going to give control to INT 19h boot loader.
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Phoenix Bios Code Definition
Definition--1
02h confirms the true way
03h removes MNI to establish
04h obtains
bt i CPU ttype
06h initializes the hardware in the system
08h initializes chipset with POST initial value Flag
09h establishes POST course is marked
0Ah initializes the register within CPU
0Bh can cause the register within CPU
0Ch initializes Cache with POST initial value
0Eh initializes the part related to I/O
0Fh initializes IDE equipment
q p
10h initializes the power and manages worker's function
11h load a register POST initial value to make
12h is warm while starting the machine, resume control word yard of CPU
13h initializes the top management device on PCI bus
14h initializes the keyboard controller
16h checks checksum value within BIOS
17h is established mainly before the capacity of the storing device automatically,
initializes cache first
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Definition--2
18h initializes 8254 time-recorders
1Ah initializes 8237DMA controller
1Ch can resett the
th procedure
d cuts
t off
ff the
th controller
t ll (PIC)
20h tests refresh function of DRAM
22h tests 8742 keyboard controllers
24h establishes the temporary device of ES sector to 4GB
26h can cause A20 control the line
28h mainly establishes the capacity of the storing device automatically (auto size)
29h initial POST course storing device managing device
2Ah removes 512K content value of the storing device basically
2Ch as detect and examine 512K RAM mistake,, then Hao shows
corresponding address line xxxx
2Eh Hao shows wrong low-order district (low bytes of storing device Materials line
xxxx
2Fh duplicates BIOS to shadow RAM, initializes cache first
30h shows the wrong low high high-order
order district (high
(high-bytes
bytes ) of storing device Materials
line xxxx
32h tests the pulse frequency when CPU bus
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Definition--3
33h initializes Phoenix materials and assigns administrators
36h starts the machine and is over warmlyy
38h duplicates BIOS to shadow RAM
3Ah establishes cache capacity automatically (auto size) The register enters the
configuration of the steps to establish inside chip group 3Ch
3D h value in CMOS is loaded another register
42h initializes
initiali es and ccuts
ts off the vectorial
ectorial form
45h initializes POST component
46h checks the copyright statement within ROM
48h checks the configuration value of video-information
49h initializes PCI bus and device
4Ah initializes all video-information adapters in the system
4Bh get up sound the attitudes start the machine (/optional)
4Ch duplicates video BIOS to shadow
4Eh shows the copyright statement of BIOS
50h shows CPU type and speed
51h initializes EISA Board
52h tests the keyboard
54h establishing
58h tests the sudden signal of cutting off
59h initializes POST video-information service function
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Definition--4
5Ah shows information Press F2 to enter SETUP Cache in
5Bh Disable CPU
5Ch tests 512KB 5Ch 640KB storing device
60h tests and extends the storing device (extended memory )
62h tests and extends the storing device address line
64h jumps to user patch 1
66h is established into the steps cache register
67h initializes APIC of many processors
68h can cause CPU / cache outside
69h establishes the systematic management style area (SMM )
6Ah shows outside L2 Cache Size of CPU
6Bh is loaded BIOS value that the user establishes
6Ch Hao shows the information of shadow sector
6Eh Hao shows the high address which resumes UMB
70h shows wrong information
72h checks the configuration mistake
76h checks the mistake of the keyboard
7Ch establishes the vector quantity in the hardware
7Eh is initialized in coordination with the processor (if the words existing)
Super IO and IRQ 80h Disable onboard One section of POST components
Super-IO
initializes
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Definition--5
81h It is examined and installed that 82h is detected to the outside RS232 port
82h is detected to the outside RS232 port
83h organizes non-MCD IDE controller, it is examined and installed that
84h is detected to the parallel port of outside
85h initializes ISA device of PnP
86h initializes on-board IO port again
87h can organizei on the
th host
h t computert board
b d the th organization
i ti componentt
88h initializes BIOS materials area
89h Enable Non-maskable interrupts(NMI)
The rose can be unable to interdict to cut off the vector quantity
8Ah initializes the BIOS materials area of extension
8Bh tests and initializes PS2 Genius mouse
8Ch initializes FDC
8Fh confirms ATA equipment's figure
90h initializes the hard disk controller
91h initializes the regional hard disk controller
92h jumps to userpatch2
93h sets up Mptable (there are many processor host computer boards)
Installation CD-ROM
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Definition--6
95h enables starting the machine

96h removes ES sector register content
97h select / arrange for Mptable (whether large processors choose form)
98h searches having and ROM, there is and checksum mistake, a two long short humming
99h checks whether there is SMART device
9Ah and ROM duplicate to shadow RAM
9Ch establishes
t bli h th the ffunctions
ti off managementt off power
9Dh initializes the safe functions of management
9Eh starts the hardware and cuts off the function
9Fh determines ATA and SCSI device figure
A0h sets for date
A2h checks key-lock function
A4h initializes the keyboard and reflects the speed
A8h dispels F2 and points out number
AAh scans F2 keyy and is struck down
ACh prohibits entering SETUP
AEh removes and starts the machine the flag is marked
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Definition--7
B0H checks whether there is any mistake
B2h POST finished planning to start the machine with the operating system procedure
Th b
The buzzer iis lloud
dbbefore
f
B4h operating system starts the machine A short
B5h discontinues the static behavior and starts the machine (option )
B6h checks the password to establish (option )
B9h plans to start the machine
BAh initializes DMI parameter
BBh initialize and type PnP ROM
BCh is removed with the location location detector
BDh shows that start the machine and choose the form again
g more
Beh removes the screen (optional)
BFh checks the virus
C0h tries to start the machine with INT19
C1h initializes the wrong administrator of POST (PEM)
C2h initializes the wrong log
log-in
in function
C3h initializes wrong Hao and shows the function
C4h initializes the wrong processor
C5h PnP CMOS
C6h initializes the note type computer dock function
C7h initializes the note type working speed of computer dock
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Definition--8
C8h Force checking Extending type checksum inspection of C9h
D2h checking and cutting off unidentifiedly
E0h iinitializes
iti li th
the chip
hi group
E1h initializes the north and south bridge
E2h initializes CPU
E3h initializes the systematic time-recorder
E4h initializes systematic IO
Function that E5h checks and resumes starting the machine by force
E6h calculates checksum of BIOS ROM
E7h is moved to BIOS
E8h establishes the large g sector
E9h initializes many processors
EAh initializes OEM special yard
EBh initializes PIC and DMA
ECh initializes the modeling of the storing device to establish
EEh initializes the size of the storing device to establish
EDh starts the machine in the area to duplicate to Shadow RAM
EFh system storing device tests
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Definition--9
F0h initializes and cuts off the vectorial form
F1h initializes RTC ((Run Time Clock))
F2h initializes the video-information function
F3h initializes the systematic management style
A loud a short before F4h starts the machine
F5h starts the machine to small-scale DOS system
F6h removes th the llarge sector
t content
t t
F7h starts the machine to DOS
If BIOS is it examine get mistake yards of 2C to detect, 2E or 30 (mainly 512K
mistake of storing etc. basically ), it will show 4 is it show which one address line lose
efficiency to come at the same time
time, for example " 2C 0002 " expresses the address
bit1 mistake, 2E, 1020 " express materials location bit5, 12 wrong BIOSs will send off
corresponding wrong location line to PORT80 LED card and show that it will show first
then 2C shows 00 high bytes, low byte is 02, regard the covering as equally important
and show finally.
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MB L3 Training

533/800 MB/s FSB

FSB 800/1066/1333/1600 MHz

DMI bus Per-dir

533 Mb/s Via Link

PCI Bus 2x Serial ATA Ports

2 x PCI Slots USB USB USB USB

BIOS 1xParallel, Floppy

3 x PCI Slots PCI Bus 33MHz 1xParallel, Floppyy

Advanced Configuration and Power Interface

Unplug ATX Power Supply Plug-in ATX Power Supply

For LAN Voltage

Before you boot up the board, it’s 1. +5VSB

While you touch it off, it will

When 5VSB and 3VSB send to SIO and SB

Do you know when RSMRST# is Lo?

Function of Battery Power are:

Use Multi-meter to measure

1. Use multi-meter to measure 1k

(According to Ohm theory: I=V/R,

2. If the value is NG,

3. If the value is still NG, check

4. If the value is still NG,

5. If it’s not I/O or ASIC problem

Switch Regulator Linear Regulator

 P channel, Current low.

S0: All Power

 P channel for S3 and S5, Current low.

Red is for stand by voltage

Green is for VCORE voltage

Output filter and

VCC Drive PHASE

P.S. High side VGS and Low side VGS

2.Impedance in VCORE is <50

3.Impedance from 12V to VCORE is <100

Check Other Circuit fail:

Turn off Power Supply

+ Point: Red Line PIN1(BST) PIN8(DRVH) PIN4(VCC) PIN5(DRVL) PIN2(DRVL) PIN3(DRVL)

- Point: Black Line ( )

Other Circuit fail:

Mount good MOS and

Measure MOS & NO

Sometimes we can find BAT54AW near ICS.

CK_33M_ICH/# 33MHZ BITCLK 24MHZ

PCI Slot CK_100M_PE16/# 100MHZ

CK_33M_SIO 33MHZ W83667EHF

Visual Inspection NG Change damaged CLK OK

Check CLK Vcc 3V & Fix any trace open and OK

Trace the circuit, check Fix any trace open and OK

Change CLK Generator Finished

Visual Inspection to check

Use Oscilloscope to measure

If related RLC components

1.General Power On Sequence

+5 5VSB CPU SOCKET

ATX PCIE X16

Pin Define Signal Description

Pin Define Signal Description

Visual Inspection NG Change NG PS2 Connector, OK