DST Tmpm370fydfg-Tde en 21751

32-bit RISC Microcontroller
TX03 Series
TMPM370FYDFG/FYFG
Semiconductor Company
Revision History
Date Revision
2010/10/18 Rev 1 First Release
2011/3/7 Rev 2 Contents Revised
TMPM370
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ARM, ARM Powered, AMBA, ADK, ARM9TDMI, TDMI, PrimeCell, RealView, Thumb, Cortex,
Coresight, ARM9, ARM926EJ-S, Embedded Trace Macrocell, ETM, AHB, APB, and KEIL are
registered trademarks or trademarks of ARM Limited in the EU and other countries.
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TMPM370 1-1
TMPM370
32-bit RISC microcontroller TX03 series

TMPM370FYDFG
TMPM370FYFG
TX03 series is a 32-bit RISC microcontroller with an ARM® Cortex™-M3 microcontroller core.
Product No. On chip Flash ROM On chip RAM Package

TMPM370FYDFG 256 Kbyte 10 Kbyte QFP100-P-1420-0.65Q
TMPM370FYFG 256 Kbyte 10 Kbyte LQFP100-P-1414-0.50H
1.1 Features
( 1 ) ARM Cortex-M3 microcontroller core
1) Improved code efficiency has been realized through the use of Thumb®-2 instruction
- New 16-bit Thumb® instructions for improved program flow
- New 32-bit Thumb instructions for improved performance and code size.
- Auto-switching between 32-bit instruction and 16-bit instruction is executed by compiler.
2) Both high performance and low power consumption have been achieved
High performance
- A 32-bit multiplication (32×32=32 bit) can be executed with one clock
- Division takes between 2 and 12 cycles depending on dividend and devisor
Low power consumption

- Optimized design using a low power consumption library
- Standby function that stops the operation of the microcontroller core
3) High-speed interrupt response suitable for real-time control

- An interruptible long instruction
- Stack push automatically handled by hardware
( 2 ) Interrupt source
- Internal: 62 factors…The order of precedence can be set over 7 levels (except the watchdog
timer interrupt).
- External: 16 factors…The order of precedence can be set over 7 levels
( 3 ) Input/ output ports

- Input/Output: 74 pins Input: 2pins
( 4 ) Watchdog timer (WDT): 1 channel

- 26 cycles of binary counter
( 5 ) Power_On reset function(POR)
( 6 ) Voltage detect function(VLTD)
( 7 ) Oscillation frequency detect function(OFD)
TMPM370 1-2 Overview and Features

TMPM370
( 8 ) Vector engine(VE): 1 unit

- Calculationg circuit for motor control
- corresponding to 2 motors
( 9 ) Programmable motor driver(PMD): 2channel

- 3phase complementary PWM generator
- Synchronous A/D convert start trigger generator
- Emergency protective function(EMG pin/comparator output)
( 10 ) Encoder input circuit(ENC): 2 channel

- Correspond to increamental encoder(AB/ABZ)
- Rotation direction detecttion
- Counter for absolute position detection
- Comparator for position detection
- Noise filter
- 3 phase sensor input
( 11 ) 16-bit timer(TMRB): 8 channel

- 16-bit interval timer mode
- 16-bit event counter mode
- 16-bit PPG output
- External trigger PPG output
- Input capture function
( 12 ) General-purpose serial interface(SIO): 4 channel

- Either UART mode or synchronous mode can be selected (4byte FIFO equipped)
( 13 ) 12-bit A/D converter (ADC): 2unit( 22 channel for analog input)

- Start by the internal trigger: TMRB interrupt / PMD trigger
- Constant conversion mode
- AD conversion monitoring function(2ch)
- Conversion speed 2usec (@ ADC conversion clock = 40MHz)
( 14 ) OP-Amp(AMP): 4 channel
- 8 gain can be selected
( 15 ) comparator(CMP): 3+1 channel

- Protection for motor emergence stop
- 2 input type(OP-Amp output/analog input)
( 16 ) Standby mode
- Standby mode: IDLE, STOP
( 17 ) Clock generator(CG)
- On-chip PLL (8 times)
- Clock gear function: The high-speed clock can be divided into 1/1, 1/2, 1/4, 1/8 or 1/16
( 18 ) Endian
- Little endian
( 19 ) Maximum operating frequency

- 80MHz
( 20 ) Operating voltage range

- 4.5V~5.5V (with on-chip regulator)
( 21 ) Temperature range
- -40°C~85°C (except during Flash writing/ erasing and debugging)
- 0°C~70°C (during Flash writing/ erasing and degugging)

TMPM370
1.2 Block Diagram
3.3V
I/F NANO
REGULATOR 5V
Cortex-M3 I-Code FLASH
AHB-Bus-Matrix (80MHz)
CPU
1.5V
D-Code
I/F RAM
Debug System
NVIC
I/F BOOT
ROM
Bus Bridge
Oscillator
ROM for VE
CG PLL
VE WDT
PMD OFD On_chip oscillator

IO-Bus
PMD POR/VLTD
ADC SIO (4ch)
ADC TMRB (8ch)
AMP/CMP (4ch) PORT A - L
ENC (2ch)
Fig1.1 TMPM370FYDFG/ FYFG block diagram

TMPM370
2. Pin Layout and Pin Functions

This chapter describes the pin layout, pin names and pin functions of TMPM370FYFG/TMPM370FYDFG.
2.1 Pin Layout (Top view)
PI2/AINA10/AINB1
PI3/AINA11/AINB2
AVDD5A/VREFHA
AVDD5B/VREFHB
PI1/AINA9/AINB0
PH0/AINA0/INT0
PH1/AINA1/INT1
PH2/AINA2/INT2
AVSSA/VREFLA
AVSSB/VREFLB
CVREFABC
PH3/AINA3
PH4/AINA4
PH5/AINA5
PH6/AINA6
PH7/AINA7
PJ0/AINB3
PJ1/AINB4
PJ2/AINB5
PJ3/AINB6
PJ4/AINB7
AMPVDD5
PI0/AINA8
AMPVSS
CVREFD
100
95
90
85
80
76
DVSS 1 75 PJ5/AINB8
INT3/TB0IN/PA0 PJ6/AINB9/INTC
TB0OUT/PA1 PJ7/AINB10/INTD
INT4/TB1IN/PA2 PK0/AINB11/INTE
TB1OUT/PA3 5 PK1/AINB12/INTF
CTS1/SCLK1/PA4 70 PB7/TRST
TB6OUT/TXD1/PA5 PB6/TDI
TB6IN/RXD1/PA6 PB5/TDO/SWV
INT8/TB4IN/PA7 PB4/TCK/SWCLK
TXD0/PE0
RXD0/PE1
10 TMPM370FYFG 65
PB3/TMS/SWDIO
PB2/TRACEDATA 1
CTS0/SCLK0/PE2 PB1/TRACEDATA 0
TB4OUT/PE3
DVDD5
100 pin(14x14) PB0/TRACECLK
DVSS
INT5/TB2IN/PE4 15 DVDD5E
TB2OUT/PE5
INT6/TB3IN/PE6
(Top View) 60 VOUT3
RESET
INT7/TB3OUT/PE7 RVDD5
DVSS MODE
INTB/PL0 20 DVSS
INTA/PL1 55 VOUT15
UO0/PC0 PF4/ENCZ1/RXD3
XO0/PC1 PF3/ENCB1/TXD3
VO0/PC2 PF2/ENCA1/SCLK3/CTS3
YO0/PC3 25 51 PF1/TB7OUT
26
30
35
40
45
50
DVDD5
WO0/PC4
ZO0/PC5
DVSS
X1
DVSS
X2
EMG0/PC6
OVV0/PC7
INT9/PD3
CTS2/SCLK2/PD4
TXD2/PD5
RXD2/PD6
BOOT/TB7IN/PF0
UO1/PG0
TB5IN/ENCA0/PD0
TB5OUT/ENCB0/PD1
ENCZ0/PD2
XO1/PG1
VO1/PG2
YO1/PG3
WO1/PG4
ZO1/PG5
EMG1/PG6
OVV1/PG7
Fig 2-1 Pin layout (TMPM370FYFG)
TMPM370 2-1 Pin layout and pin function

TMPM370
PI2/AINA10/AINB1
PI3/AINA11/AINB2
AVDD5A/VREFHA
AVDD5B/VREFHB
PI1/AINA9/AINB0
PH0/AINA0/INT0
PH1/AINA1/INT1
PH2/AINA2/INT2
AVSSA/VREFLA
AVSSB/VREFLB
PH3/AINA3
PH4/AINA4
PH5/AINA5
PH6/AINA6
PH7/AINA7
PJ0/AINB3
PJ1/AINB4
AMPVDD5
PI0/AINA8
AMPVSS
100
95
90
85
81
CVREFD 1 80 PJ2/AINB5
CVREFABC PJ3/AINB6
DVSS PJ4/AINB7
INT3/TB0IN/PA0 PJ5/AINB8
TB0OUT/PA1 5 PJ6/AINB9/INTC
INT4/TB1IN/PA2 75 PJ7/AINB10/INTD
TB1OUT/PA3 PK0/AINB11/INTE
CTS1/SCLK1/PA4 PK1/AINB12/INTF
TB6OUT/TXD1/PA5 PB7/TRST
TB6IN/RXD1/PA6 10 PB6/TDI
INT8/TB4IN/PA7 70 PB5/TDO/SWV
TXD0/PE0 PB4/TCK/SWCLK
RXD0/PE1 TMPM370FYDFG PB3/TMS/SWDIO
CTS0/SCLK0/PE2 PB2/TRACEDATA 1
TB4OUT/PE3 15 PB1/TRACEDATA 0
DVDD5 100 pin(14x20) 65 PB0/TRACECLK
INT5/TB2IN/PE4 DVSS
TB2OUT/PE5 DVDD5E
INT6/TB3IN/PE6 (Top View) VOUT3
INT7/TB3OUT/PE7 20 RESET
DVSS 60 RVDD5
INTB/PL0 MODE
INTA/PL1 DVSS
UO0/PC0 VOUT15
XO0/PC1 25 PF4/ENCZ1/RXD3
VO0/PC2 55 PF3/ENCB1/TXD3
YO0/PC3 PF2/ENCA1/SCLK3/CTS3
WO0/PC4 PF1/TB7OUT
ZO0/PC5 PF0/TB7IN/BOOT
EMG0/PC6 30 51 X2
31
35
40
45
50
OVV0/PC7
DVDD5
INT9/PD3
CTS2/SCLK2/PD4
TXD2/PD5
RXD2/PD6
DVSS
X1
UO1/PG0
OVV1/PG7
DVSS
TB5IN/ENCA0/PD0
TB5OUT/ENCB0/PD1
ENCZ0/PD2
XO1/PG1
VO1/PG2
YO1/PG3
WO1/PG4
ZO1/PG5
EMG1/PG6
Fig 2-2 Pin layout (TMPM370FYDFG)

TMPM370
2.2 Pin function
Table2.1 shows the pin functions of TMPM370FYFG/FYDFG. Table 2.2 shows the operating voltage of
each pin, and table 2.3 shows the voltage range of every pin.
Table 2.1 Pin functions (1/5)
SCHIMITT Open Drain High
Pin name Output during Reset
(O:Yes) mode Speed
CVREFD Hi-Z
CVREFABC Hi-Z
DVSS
PA0
Hi-Z O O
TB0IN/INT3
PA1
Hi-Z O O
TB0OUT
PA2
TB1IN Hi-Z O O
INT4
PA3
Hi-Z O O
TB1OUT
PA4
SCLK1 Hi-Z O O
CTS1
PA5
TXD1 Hi-Z O O
TB6OUT
PA6
RXD1 Hi-Z O O
TB6IN
PA7
TB4IN Hi-Z O O
INT8
PE0
Hi-Z O O
TXD0
PE1
Hi-Z O O
RXD0
PE2
SCLK0 Hi-Z O O
CTS0
PE3
Hi-Z O O
TB4OUT
DVDD5
PE4
TB2IN Hi-Z O O
INT5
PE5
Hi-Z O O
TB2OUT
PE6
TB3IN Hi-Z O O
INT6
PE7
TB3OUT Hi-Z O O
INT7
DVSS

TMPM370

(O:Yes) mode Speed
PL0
Hi-Z O
INTB
PL1
Hi-Z O
INTA
PC0
Hi-Z O O
UO0
PC1
Hi-Z O O
XO0
PC2
Hi-Z O O
VO0
PC3
Hi-Z O O
YO0
PC4
Hi-Z O O
WO0
PC5
Hi-Z O O
ZO0
PC6
Hi-Z O O
EMG0
PC7
Hi-Z O O
OVV0
PD0
ENCA0 Hi-Z O O
TB5IN
PD1
ENCB0 Hi-Z O O
TB5OUT
PD2
Hi-Z O O
ENCZ0
PD3
Hi-Z O O
INT9
PD4
SCLK2 Hi-Z O O
CTS2
PD5
Hi-Z O O
TXD2
PD6
Hi-Z O O
RXD2
PG0
Hi-Z O O
UO1
PG1
Hi-Z O O
XO1
PG2
Hi-Z O O
VO1
DVDD5
DVSS

TMPM370

(O:Yes) mode Speed
PG3
Hi-Z O O
YO1
PG4
Hi-Z O O
WO1
PG5
Hi-Z O O
ZO1
PG6
Hi-Z O O
EMG1
PG7
Hi-Z O O
OVV1
X1
DVSS Hi-Z O
X2
PF0
TB7IN Pull UP O O
BOOT
PF1
Hi-Z O O
TB7OUT
PF2
ENCA1
Hi-Z O O
SCLK3
CTS3
PF3
ENCB1 Hi-Z O O
TXD3
PF4
ENCZ1 Hi-Z O O
RXD3
VOUT15
DVSS
MODE Hi-Z O
RVDD5
RESET Pull UP O
VOUT3
DVDD5E
DVSS
PB0
Hi-Z O O O
TRACECLK
PB1
Hi-Z O O O
TRACEDATA 0
PB2
Hi-Z O O O
TRACEDATA 1
PB3
TMS Pull UP O O
SWDIO
PB4
TCK Pull DOWN O O
SWCLK
PB5
TDO Hi-Z O O
SWV
PB6
Pull UP O O
TDI

TMPM370

(O:Yes) mode Speed
PB7
Pull UP O O
TRST
PK1
AINB12 Hi-Z O O
INTF
PK0
AINB11 Hi-Z O O
INTE
PJ7
AINB10 Hi-Z O O
INTD
PJ6
AINB9 Hi-Z O O
INTC
PJ5
Hi-Z O O
AINB8
PJ4
Hi-Z O O
AINB7
PJ3
Hi-Z O O
AINB6
PJ2
Hi-Z O O
AINB5
PJ1
Hi-Z O O
AINB4
PJ0
Hi-Z O O
AINB3
AVSSB
VREFLB
AVDD5B
VREFHB
PI3
AINA11 Hi-Z O O
AINB2
PI2
AINA10 Hi-Z O O
AINB1
PI1
AINA9 Hi-Z O O
AINB0
AVSSA
VREFLA
AVDD5A
VREFHA
PI0
Hi-Z O O
AINA8
PH7
Hi-Z O O
AINA7
PH6
Hi-Z O O
AINA6
PH5
Hi-Z O O
AINA5
PH4
Hi-Z O O
AINA4

TMPM370
Table 2.1 Pin function (5/5)

(O:Yes) mode Speed
PH3
Hi-Z O O
AINA3
PH2
AINA2 Hi-Z O O
INT2
PH1
AINA1 Hi-Z O O
INT1
PH0
AINA0 Hi-Z O O
INT0
AMPVSS
AMPVDD5
Table 2.2 Operating voltage of each Pin

Pin name Operating voltage
X1,X2 Internal 1.5V/CVSS Do not be driven by external circuit.

RESET DVDD5/DVSS
MODE DVDD5/DVSS must be connect with GND
Compare(reference) voltage input for

CVREFABC, CVREFD AMPVDD5/AMPVSS
comparator ABC and comparator D
I/O
DVDD5/DVSS
(PAx,PCx-PGx,PLx)
I/O(PBx) DVDD5E/DVSS
AVDD5A/AVSSB
AIN(PHx-PKx)
AVDD5B/AVSSB
Table 2.3 voltage range of each pin

Pin name Voltage range
DVDD5 For I/O ports
RVDD5 For internal circuit
AVDD5A,AVDD5B 4.5 to 5.5V For ADCs
AMPVDD5 For operational amp and comparator
DVDD5E DVDD5E must be connect with DVDD5

VOUT15 must be connected with DVSS
through 3.3 to 4.7uF capacitor for supply
VOUT15 (Note) 1.35 to 1.65V power to internal circuit.The capacitor
should be placed close to the MCU.
Do not supply power to external circuits.
VOUT3 must be connected with DVSS
through 3.3 to 4.7uF capacitor for supply
VOUT3 (Note) 2.7 to 3.6V power to internal circuit. The capacitor
should be placed close to the MCU.
Do not supply power to external circuits.
DVSS
AVSSA,AVSSB GND
AMPVSS
Note: VOUT15 and VOUT3 must be connected with the same value of capacitors.

TMPM370
3 Processor Core
3.1 Processor Core

The TX03 series has a high-performance 32-bit processor core (the ARM Cortex-M3 processor
core). For information on the operations of this processor core, please refer to the “Cortex-M3
Technical Reference Manual” issued by ARM Limited. This chapter describes the functions unique to
the TX03 series that are not explained in that document.
The following table shows the revision of the processor core in the TMPM370FY. For further
information on each revision, see the documents issued by ARM Limited.
Product Name Core Revision

TMPM370FY r2p0
3.2 Optional block
The Cortex-M3 core has the optional blocks. The optional blocks of the revision r2p0 are below;
Optional block Implementation

FPB O
DWT O
ITM O
MPU X
TM
ETM O
AHB-AP O
AHB trace macro-cell interface O
TPIU O
WIC X
O: Implement
X: Not implement
3.3 Event
TMPM370FY is not support event input/output. Do not use SEV instruction and WFE instruction.
3.4 SLEEPDEEP
TMPM370FY is not support SLEEPDEEP. Do not set SLEEPDEEP bit.

Event signal is not supported also. Do not use WFE instruction.
TMPM370 3-1 Processor Core

TMPM370
3.5 Exclusive access
The DCode bus and the system bus of TMPM370FY are not support EXCLUSIVE ACCESS.
3.6 Reset operation
3.6.1 Initial state

The internal circuits, register settings and pin status are undefined right after the power-on. The
state continues until the RESET pin receives “Low” level signal after all the power supply voltage is
applied.
3.6.2 Reset operation

TMPM370 has Power-on reset circuit, power-on reset signal is generated when power supply is
turned on. More information is described in Chapter “Power-on Reset Circuit (POR)” and “Note the
power on” in the chapter ”Electrical Characteristics”.
When reset from external RESET pin, as the precondition, ensure that a high-speed osciilator
provides stable oscillation while power supply voltage is in the operating range.
To reset the TMPM370, input reset signal to RESET pin at “Low” level for minimum duration of 12
system clocks.
3.6.3 After Reset

When the reset is released, the system control register and the internal I/O register of the
Cortex-M3 processor core are initialized. High-speed oscillator is started oscillation. Note that the PLL
multiplication circuit stops after releasing the reset. Therefore, set CGOSCCR register and
CGPLLSEL register to use PLL multiplication circuit. Regarding detail information, see to “Clock/Mode
control”.
After the reset exception handling is executed, the program branches off to the interrupt service
routine. The address with which the interrupt service routine starts is stored in 0x0000_0004.
(Note 1) It is possible to turn power on after RESET pin is set to "Low". Detail information is
describedi in “Note the power on” in the chapter “Electrical Characteristics”.
(Note 2) The reset operation may alter the internal RAM state.
TMPM370 3-2 Processor Core

TMPM370
4 Dubug Interface
4.1 Specification Overview

The TMPM370 contains the Serial Wire JTAG Debug Port (SWJ-DP) unit for interfacing with the
Debug Interface and the Embedded Trace MacrocellTM (ETM) unit for trace output. Trace data is
output to the dedicated pins (TRACEDATA[0]-[1], SWV) via the on-chip Trace Port Interface Unit
(TPIU).
For details about SWJ-DP, ETM and TPIU, refer to “Cortex-M3 Technical Reference Manual”.
4.2 Features of SWJ-DP

SWJ-DP supports the two-pin Serial Wire Debug Port (SWDCK, SWDIO) and the JTAG Debug
------------------
Port (TDI, TDO, TMS, TCK, TRST ).
4.3 Features of ETM

ETM supports two data signal pins (TRACEDATA[0]-[1]), one clock signal pin (TRACECLK) and
trace output from SWV.
4.4 Pin Functions

The debug interface pins can also be used as general-purpose ports. The PB3 and PB4 are shared
between the JTAG debug port function and the serial wire debug port function. The PB5 is shared
between the JTAG debug port function and the SWV trace output function.
Table 4-1 SWJ-DP、ETM function

SWJ-DP Name of JTAG debug function SW debug
Pin name port I/O Discription I/O Discription
JTAG Test Mode Serial Wire Data
TMS/SWDIO PB3 Input I/O
Selection Input/Output
TCK/SWCLK PB4 Input JTAG Test Check Input Serial Wire Clock
－
( Ser ia l W ire
TDO/SWV PB5 Output JTAG Test Data Output (Output)
Viewer Output)
(Note)
TDI PB6 Input JTAG Test Data Input －－
------------------
TRST PB7 Input JTAG Test RESET －－
TRACECLK PB0 Output TRACE Clock Output
TRACEDATA0 PB1 Output TRACE DATA Output0
TRACEDATA1 PB2 Output TRACE DATA Output1
(Note)In case of enabling SWV function.
After reset, the PB3, PB4, PB5, PB6 and PB7 are configured as debug port function pins. The
functions of other debug interface pins need to be programmed as required. Debug interface pins
TMPM370 4-1 Dubug Interface

TMPM370
can use general purpose port that is not use debug interface.
The table 4-2 below summarizes the debug interface pin functions and related port settings after reset.
Table 4-2 Debug interface pins and port setting after reset
Port Setting After Reset
Initial PORT
Debug Function
Setting (Bit name) Function Input Output Open drain Pull-up Pull-down
(PBFR1) (PBIE) (PBCR) (PBOD) (PBPUP) (PBPDN)
PORT PB0 TRACECLK 0 0 0 0 0 0
PORT PB1 TARCEDATA0 0 0 0 0 0 0
PORT PB2 TRACEDATA1 0 0 0 0 0 0
DEBUG PB3 TMS/SWDIO 1 1 1 0 1 0
DEBUG PB4 TCK/SWCLK 1 1 0 0 0 1
DEBUG PB5 TDO/SWV 1 0 1 0 0 0
DEBUG PB6 TDI 1 1 0 0 1 0
---------------
DEBUG PB7 TRST 1 1 0 0 1 0
When using a low power consumption mode, take note of the following points.
(Note 1) If PB3 and PB5 are configured as debug function pins, output continues to be enabled
even in STOP mode regardless of the setting of the CGSTBYCR<DRVE> .
(Note 2) If PB4 is configured as a debug function pin, it prevents a low power consumption mode
from being fully effective. Configure PB4 to function as a general-purpose port if the
debug function is not used.
4.5 Connection with a Debug Tool
4.6 How to connect
For how to connect a debug tool, refer to the method recommended by each manufacturer.
Debug interface pins have pull-up or pull-down register. When connect with pull-up or pull-down
registers ,be sure their settings.
4.7 When use general purpose port

When debugging, do not change setting debug interface to general purpose port by program. Then,
MCU will be unable to control signals received from the debugging tools and can not continue
debugging. According to the usage of the debug interface pins, be sure their settings.

TMPM370
Table 4-3 Debug Interface

Using Debug Interface pins
Usag ------------------ TDO/ TCK/ TMS/ TRACE TARCE TRACE
TRST TDI
SWV SWCLK SWDIO DATA1 DATA0 CLK
JTAG+SW (After RESET) ○ ○ ○ ○ ○ × × ×
------------------
JTAG+SW (No TRST ) × ○ ○ ○ ○ × × ×
JTAG+TRACE ○ ○ ○ ○ ○ ○ ○ ○
SW × × × ○ ○ × × ×
SW+SWV × × ○ ○ ○ × × ×
Disable Debug function × × × × × × × ×
○：Enable、×：Disable (Can use general purpose port)
4.8 Peripherals operation during HALT mode (one time stop of running program)
When Break during debugging, Cortex-M3 CPU core going into HALT mode. Watch dog timer (WDT)
is stopped counting automatically. Other peripherals are continue operating.

TMPM370
5 Memory Map
The memory maps for the TMPM370FY are based on the ARM Cortex-M3 processor core memory map.
The internal ROM, internal RAM and internal I/O regions of the TMPM370FY are mapped to the code,
SRAM and peripheral regions of the Cortex-M3 respectively. The SRAM and internal I/O regions are all
included in the bit-band region.
The CPU register region is the processor core’s internal register region.
For more information on each region, see the “Cortex-M3 Technical Reference Manual”.
Note that regions indicated as “Fault” is accessed, memory fault is generated if memory fault is enable, or
hard fault is generated if memory fault is disable. Do not access the vendor-specific regions.
See “Special Function Registers” for details on the internal I/O region.
TMPM370 5-1 Memory map

TMPM370
5.1 Memory Map
Fig 5-1 shows the memory map of the TMPM370FY.
Single chip mode Single boot mode
0xFFFF FFFF 0xFFFF FFFF

Vendor Specific Vendor Specific
0xE010 0000 0xE010 0000
0xE00F FFFF 0xE00F FFFF
CPU Register Region CPU Register Region
0xE000 0000 0xE000 0000
Fault Fault
0x41FF FFFF Internal IO 0x41FF FFFF Internal IO

0x4000 0000 0x4000 0000
Fault
0x3F83 FFFF
Fault Internal ROM (256K)
0x3F80 0000
0x3F7F FFFF Reserved
0x3F7F F000
Fault
0x2000 27FF Internal RAM (10K) 0x2000 27FF Internal RAM (10K)
0x2000 0000 0x2000 0000
Fault
Fault
0x0003 FFFF
Internal ROM (256K) 0x0000 0FFF BOOTROM (4K)
0x0000 0000 0x0000 0000
Fig 5-1 Memory Map
TMPM370 5-2 Memory map

TMPM370
6 Clock/Mode Control
6.1 Features
The clock/mode control block enables to select clock gear, prescaler clock and warm-up of the PLL
(including clock multiplication circuit) and oscillator.
The low power consumption mode can reduce power consumption.
This chapter describes how to control clocks, clock operating modes and mode transitions.
The clock/mode control block has the following functions:

y Controls the oscillator.
y Controls the system clock.
y Controls the prescaler clock.
y Controls the PLL multiplication circuit.
y Controls the warm-up timer.
In addition to NORMAL mode, the TMPM370FY can operate in two types of low power mode to reduce
power consumption according to its usage conditions.
TMPM370 6-1 Clock/Mode control

TMPM370
6.2 Registers
6.2.1 Register List

Table 6-1 shows registers and addresses of the clock generator.
Table 6-1 Registers of Clock Generator

Register name Address
System control register CGSYSCR 0x4004_0200
Oscillation control register CGOSCCR 0x4004_0204
Standby control register CGSTBYCR 0x4004_0208
PLL selection register CGPLLSEL 0x4004_020C
System clock selection register CGCKSEL 0x4004_0210

TMPM370
6.2.2 Detailed Description of Registers
6.2.2.1 System Control Register (CGSYSCR)

7 6 5 4 3 2 1 0
Bit symbol - - - - - GEAR2 GEAR1 GEAR0
Read/Write R R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
Function “0” is read. High-speed clock (fc) gear
000: fc 100: fc/2
001: reserved 101: fc/4
15 14 13 12 11 10 9 8
Bit symbol - - - FPSEL - PRCK2 PRCK1 PRCK0
Read/Write R R/W R R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
Function “0” is read. Fperiph “0” is read. Prescaler clock
clock 000: fperiph 100: fperiph/16
001: fperiph/2 101: fperiph/32
0:fgear 010: fperiph/4 110: Reserved
1:fc 011: fperiph/8 111: Reserved
23 22 21 20 19 18 17 16
Bit symbol - - - - - - - -
Read/Write R R/W R/W
After reset 0 0 0 0 0 0 0 1
Function “0” is read. Write “01”
31 30 29 28 27 26 25 24
Bit symbol - - - - - - - -
Read/Write R
After reset 0 0 0 0 0 0 0 0
Function “0” is read.
<Bit 2:0><GEAR 2:0> : Specifies the high-speed clock (fc) gear.
<Bit 10:8><PRCK 2:0> : Specifies the prescaler clock to peripheral I/O.
<Bit 12><FPSEL> : Specifies the source clock to fperiph.

TMPM370
6.2.2.2 Oscillation Control Register (CGOSCCR)
7 6 5 4 3 2 1 0
Bit symbol - - - - WUPSEL1 PLLON WUEF WUEON
Read/Write R R R R R/W R/W R W
After reset 0 0 0 0 0 0 0 0
Function “0” is read. Clock PLL Status of Operation of
source for operation Warm-up warm-up
Warm-up timer (WUP) timer (WUP)
timer 0: Stop
1: Oscillation 0: warm-up 0: don’t care
Write “0”. completed 1: starting
1: Warm-up in warm-up
operation
15 14 13 12 11 10 9 8
Bit symbol WUODR1 WUODR0 - - - - - XEN1
Read/Write R/W R/W R/W R R/W R/W
After reset 0 0 0 0 0 0 0 1
Function Write “00”. Write “0”. Write “0” “0” is read. Write “0”. High-speed
oscillator
0: Stop
1: Oscillation
23 22 21 20 19 18 17 16
Bit symbol WUODR5 WUODR4 WUODR3 WUODR2 - - - -
Read/Write R/W R/W R/W R/W R/W
After reset 0 0 0 0 1 1 1 0
Function Bit5:2 for warm-up counter value. Write “1110”
31 30 29 28 27 26 25 24
Bit symbol WUODR13 WUODR12 WUODR11 WUODR10 WUODR9 WUODR8 WUODR7 WUODR6
Read/Write R/W
After reset 1 0 0 0 0 0 0 0
Function Bit13:6 for warm-up counter value.
<Bit 0><WUEON> : Enables to start the warm-up timer.

<Bit 1><WUEF> : Enables to monitor the status of the warm-up timer.
<Bit 2><PLLON> : Specifies operation of the PLL.
It stops after reset. Setting the bit is required.
<Bit 3><WUPSEL1> : Write “0” to WUPSEL1.
<Bit 8><XEN1> : Specifies operation of the high-speed oscillator.
<Bit 31:24, 23:20><WUODR 13:2> : Warm-up cunter value.
The warm-up counter consists of 16-bit counter. The warm-up period lasts until the
upper 12-bit of the counter value corresponds to the values specified in <WUODR
13:2>.

TMPM370
6.2.2.3 Standby Control Register (CGSTBYCR)
7 6 5 4 3 2 1 0
Bit symbol - - - - - STBY2 STBY1 STBY0
After reset 0 0 0 0 0 0 1 1
Function “0” is read. Low power consumption mode
000: Reserved
001: STOP
010: Reserved
011: IDLE
100: Reserved
101: Reserved
110: Reserved
111: Reserved
15 14 13 12 11 10 9 8
Bit symbol - - - - - - - RXEN
After reset 0 0 0 0 0 0 0 1
Function “0” is read. Write “0”. High-speed
oscillator after
releasing
STOP mode
Write “1”.
23 22 21 20 19 18 17 16
Bit symbol - - - - - - - DRVE
After reset 0 0 0 0 0 0 0 0
Function “0” is read. Write “0”. Pin status in
STOP mode
0: Active
1: Inactive
31 30 29 28 27 26 25 24
Bit symbol - - - - - - - -
Read/Write R
After reset 0 0 0 0 0 0 0 0
<Bit 2:0><STBY2:0> : Specifies the low power consumption mode.
<Bit 8><RXEN> : Write “1”.
<Bit 16><DRVE> : Specifies the pin status in the STOP mode.

TMPM370
6.2.2.4 PLL Selection Register (CGPLLSEL)
7 6 5 4 3 2 1 0
Bit symbol - - - - - - - PLLSEL
Read/Write R/W R/W
After reset 0 0 1 1 1 1 1 0
Function Write “0011111” Select PLL
output
0: fosc
1: fpll
15 14 13 12 11 10 9 8
Bit symbol - - - - - - - -
Read/Write R/W R R/W R/W R/W
After reset 1 0 1 0 0 0 0 1
Function Write “1010” “0” is read. Write “001”
23 22 21 20 19 18 17 16
Bit symbol - - - - - - - -
Read/Write R
After reset 0 0 0 0 0 0 0 0
Function “0” is read
31 30 29 27 26 25 24 23
Bit symbol - - - - - - - -
Read/Write R
After reset 0 0 0 0 0 0 0 0
Function “0” is read
<Bit 0><PLLSEL> : Specifies use or disuse of the clock multiplied by the PLL.
“fosc” is automatically set after reset. Resetting is required when using the PLL.
Note: When the PLLSEL is controlled, the oscillation frequency detector (OFD) must
be disablded beforehand even though the PLLSEL is controlled in an initial
routine. Note that the OFD reset doesn’t initialize OFD setting.
Example of PLL setting

OFDCR1<OFDWEN7:0>=”0xF9” :Write enable code for OFD registers
OFDCR2<OFDEN7:0>=”0x00” :OFD disable
CGPLLSEL<PLLSEL>=”1” :Enabling of PLL
OFDMNPLLON=”xxxx” :Lower detection frequency setting
OFDMXPLLON=”yyyy” :Higher detection frequency setting
OFDCR2<OFDEN7:0>=”0xE4” :OFD enable
OFDCR1<OFDWEN7:0>=”0x06” :Write disable code for OFD registes

TMPM370
6.2.2.5 System Clock Selection Register (CGCKSEL)
7 6 5 4 3 2 1 0
Bit symbol - - - - - - SYSCK SYSCK
FLG
Read/Write R R/W R
After reset 0 0 0 0 0 0 0 0
Function “0” is read. System clock System clock
status
0:High-speed
(fc) 0:High-speed
1: Reserved (fc)
1: -
15 14 13 12 11 10 9 8
Bit symbol - - - - - - - -
Read/Write R
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit symbol - - - - - - - -
Read/Write R
After reset 0 0 0 0 0 0 0 0
31 30 29 28 27 26 25 24
Bit symbol - - - - - - - -
Read/Write R
After reset 0 0 0 0 0 0 0 0
<Bit 0><SYSCKFLG> : Shows the status of the system clock.
<Bit 1><SYSCK> : Write “0” to SYSCK.

TMPM370
6.3 Clock Control
6.3.1 Clock System Block Diagram
Fig.6-1 shows the clock system diagram. Each clock is defined as follows.
fosc : Clock input from high-speed oscillator (X1 and X2)
fpll : Clock octupled by PLL
fc : Clock specified by CGPLLSEL<PLLSEL> (high-speed clock)
fgear : Clock specified by CGSYSCR<GEAR2:0>
fsys : The same clock as fgear (system clock)
fperiph : Clock specified by CGSYSCR<FPSEL>
ΦT0 : Clock specified by CGSYSCR<PRCK2:0> (prescaler clock)
The high-speed clock gear (fgear) and the prescaler clock ΦT0 are dividable.
• High-speed clock gear : fc, fc/2, fc/4, fc/8, fc/16

• Prescaler clock : fperiph, fperiph/2, fperiph/4, fperiph/8, fperiph/16,fperiph/32
6.3.2 Initial Values after Reset

Reset initializes the clock configuration as follows.
High-speed oscillator : ON (oscillating)
PLL (phase locked loop circuit) : OFF (stop)
High-speed clock gear : fc (no frequency dividing)
Reset causes all the clock configurations to be the same as fosc.

fc = fosc
fsys = fc (=fosc)
fperiph = fc (=fosc)
ΦT0 = fperiph (=fosc)

TMPM370
CGOSCCR<WUEON>
CGOSCCR<WUODR>
Warm-up timer
CGSYSCR<FPSEL>
CGSYSCR<PRCK2:0>
fperiph
1/2 1/4 1/8 1/16 1/32
CGOSCCR<PLLON>
fgear
fpll ΦT0
PLL
External fosc fosc 1/2 1/4 1/8 1/16

fc fsys
oscillator
CGSYSCR<GEAR2:0>
CGPLLSEL<PLLSEL>
CGOSCCR<XEN1>
[AHB-Bus I/O]
CPU, ROM, RAM,
BOOT ROM
A/D conversion clock [IO-Bus I/O] [Peripheral I/O, prescaler input]
OFD monitoring clock TMRB, WDT,VE,PMD TMRB,SIO
SIO,ADC,PORT,OFD
ENC,VLTD,CMP,AMP
Fig.6-1 Clock Block Diagram
(Note) The input clocks to selector shown with an arrow are set as default after reset.
6.3.3 Clock Multiplication Circuit (PLL)
This circuit outputs the fpll clock that is octuple of the high-speed oscillator output clock, fosc. This
lowers the oscillator input frequency while increasing the internal clock speed.
The PLL is disabled after reset is released. To enable the PLL, set "1" to the CGOSCCR<PLLON> bit.
The PLL requires a certain amount of time to be stabilized, which should be secured using the warm-up
function.
(Note) It takes approx. 200μs for the PLL to be stabilized.
6.3.4 Warm-up Function

The warm-up function secures the stability time for the oscillator and the PLL with the warm-up timer.
The warm-up function is used when returning from STOP mode. In this case, an interrupt for returning
from the low power consumption mode triggers the automatic timer count. After the specified time is
reached, the system clock is output and the CPU starts operation.
In STOP modes, the PLL is disabled. When returning from these modes, configure the warm-up time in
consideration of the stability time of the PLL.

TMPM370
How to configure the warm-up function

Specify the count up clock for the warm-up counter in the CGOSCCR<WUPSEL1> bit. Write “0” to
<WUPSEL1>.
The warm-up time can be specified by setting the CGOSCCR<WUODR13:2>. The
CGOSCCR<WUEON><WUEF> is used to confirm the start and completion of warm-up through software
(instruction).
(Note) The warm-up timer operates according to the oscillation clock, and it may contain errors
if there is any fluctuation in the oscillation frequency. Therefore, the warm-up time should
be taken as approximate time.
The following are the examples of the warm-up function configuration.
<Example Securing the stability time fro the PLL> (fc = fosc)
CGOSCCR<WUPSEL1>=”0” : Write “0” to CGOSCCR<WUPSEL1>
CGOSCCR<WUPODR13:2>= “Warm-up time” / (1/fosc) / 16
: Specify the warm-up time
CGOSCCR<WUEON>=”1” : Start the warm-up timer (WUP)
CGOSCCR<WUEF> Read : Wait until the state becomes "0" (warm-up is finished)
(Note) The warm-up counter consists of 16-bit counter. The warm-up period lasts until the upper
12-bit of the counter value corresponds to the values specified in <WUODR 13:2>.

TMPM370
6.3.5 System Clock

The TMPM370 offers high-speed clock as system clock. The high-speed clock is dividable.
• Input frequency from X1 and X2: 8MHz to 10MHz
• Clock gear:1/1, 1/2, 1/4, 1/8, 1/16 (after reset: 1/1)
Table 6-2 Range of High-frequency (Unit:MHz)

Min. Max. After reset Clock gear (CG) : PLL=ON Clock gear (CG) : PLL=OFF
Input frequency operating operating (PLL=OFF,
1/1 1/2 1/4 1/8 1/16 1/1 1/2 1/4 1/8 1/16
freq. freq. CG=1/1)
8MHz 8MHz 64 32 16 8 4 8 4 2 1 **
OSC 1MHz 80MHz
10MHz 10MHz 80 40 20 10 5 10 5 2.5 1.25 **
Note 1 : PLL=ON/OFF setting: available in CGOSCCR<PLLON>
Note 2 : Clock gear setting: available in CGSYSCR<GEAR2:0>
Note 3 : **: Reserved
(Note ) Switching of clock gear is executed when a value is written to the CGSYSCR<GEAR2:0>
register. The actual switching takes place after a slight delay.
6.3.6 Prescaler Clock Control

Each peripheral function (TMRB0-7 and SIO0-3) has a prescaler for dividing a clock. As the clock φT0
to be input to each prescaler, the "fperiph" clock specified in the CGSYSCR<FPSEL> can be divided
according to the setting in the CGSYSCR<PRCK2:0>. After the controller is reset, fperiph is selected as
φT0.
(Note) To use the clock gear, ensure that you make the time setting such that prescaler output
φTn from each peripheral function is slower than fsys (φTn < fsys). Do not switch the
clock gear while the timer counter or other peripheral function is operating.

TMPM370
6.4 Modes and Mode Transitions
6.4.1 Mode Transitions
The NORMAL mode uses the high-speed clock for system clock.
The IDLE and STOP modes can be used as the low power consumption mode that enables to reduce
power consumption by halting processor core operation.
Fig.6-2 shows a mode transition diagram

For a description of sleep-on-exit, refer to “Cortex-M3 Technical Reference Manual”.
Reset
Reset has been performed.
Interrupt Interrupt
IDLE mode NORMAL mode STOP mode
Instruction / Instruction /
sleep on exit sleep on exit
Fig.6-2 Mode Transition Diagram

TMPM370
6.5 Operation Modes

As an operation mode, NORMAL is available. The features of NORMAL mode are described below.
6.5.1 NORMAL Mode

This mode is to operate the CPU core and the peripheral hardware by using the high-speed clock.
It is shifted to the NORMAL mode after reset.
6.6 Low Power Consumption Modes

The TMPM370 has two low power consumption modes: IDLE and STOP. To shift to the low power
consumption mode, specify the mode in the system control register CGSTBYCR<STBY2:0> and
execute the WFI (Wait For Interrupt) instruction. In this case, execute reset or generate the interrupt to
release the mode. Releasing by the interrupt requires settings in advance. See chapter 6 for details.
(Note 1) Transition to the low power consumption mode by executing the WFE (Wait For
Event) instruction is prohibited as the TMPM370 does not offer any event for
releasing the low power consumption mode.
(Note 2) The TMPM370 does not support the low power consumption mode configured with
the SLEEPDEEP bit in the Cortex-M3 core. Setting the SLEEPDEEP bit of the system
control register is prohibited.
The features of each mode are described as follows.

TMPM370
6.6.1 IDLE Mode

Only the CPU is stopped in this mode.
Each peripheral function has one bit in its control register for enabling or disabling operation in the
IDLE mode. When the IDLE mode is entered, peripheral functions for which operation in the IDLE
mode is disabled stop operation and hold the state at that time.
The following peripheral functions can be enabled or disabled in the IDLE mode. For setting details,
see the chapter on each peripheral function.
y 16-bit timer/event counter (TMRB)

y Serial channel (SIO)
y Watchdog timer (WDT)
y Vector Engine (VE)
6.6.2 STOP Mode

All the internal circuits including the internal oscillator are brought to a stop.
By releasing the STOP mode, the device returns to the preceding mode of the STOP mode and
starts operation.
The STOP mode enables to select the pin status by setting the CGSTBYCR<DRVE>.Table 6-3
shows the pin status in the STOP mode.
(Note1) In STOP modes, the PLL is disabled. When returning from these modes, configure the
warm-up time in consideration of the stability time of the PLL. It takes approx. 200μs
for the PLL to be stabilized. When the PLL is not used, 60μs or more is needed for
warm-up to stabilize the internal circuit.
(Note2) When PB4 is configured as a debug function pin, it prevents the low power
consumption mode from being fully effective. Configure PB4 to function as a
general-purpose port when the debug function is not used.
Table 6-3 Pin States in STOP Mode

Pin Name I/O <DRVE>=0 <DRVE>=1
X1 Input only × ×
Not
X2 Output only “H” level output “H” level output
Ports
RESET, MODE Input only ○ ○
PB3, PB5 Input × Depends on PxIE<n>.
[When used as a debug pin
(PBFR<n>=1) and output is enabled Enabled when data is valid. Enabled when data is valid.
Output
(PBCR<n>=1)] Disabled when data is invalid. Disabled when data is invalid.
PH0-2, PA0, PA2, PE4, PE6-7, PA7, PD3, Input ○ ○
Ports PL0-1, PJ6-7, PK0-1
[When used as an interrupt pin
(PxFR<n>=1) and input is enabled Output × Depends on PxCR<n>.
(PxIE<n>=1)
Input × Depends on PxIE<n>.
Other port pins
Output × Depends on PxCR<n>.
○： Input or output enabled
×： Input or output disabled.

TMPM370
6.6.3 Low power Consumption Mode Setting

The low power consumption mode is specified by the setting of the standby control register
CGSTBYCR<STBY2:0>.
Table 6-4 shows the mode setting in the <STBY2:0>.
Table 6-4 Low power consumption mode setting

CGSTBYCR
Mode <STBY2:0>
STOP 001
IDLE 011
(Note) Do not set any value other than those shown above in <STBY2:0>.
6.6.4 Operational State in Each Mode
Table 6-5 show the operational state in each mode.

For I/O port, “○” and “×” indicate that input/output is enabled and disabled respectively. For other
functions, “○” and “×” indicate that clock is supplied and is not supplied respectively.
Table 6-5 Operational State in Each Mode

Block NORMAL IDLE STOP
Processor core ○ × ×
I/O port ○ ○ * (Note 1)
PMD ○ ○ ×
ENC ○ ○ ×
ADC
○ ○ ×
VE ○ ×
ON/OFF
SIO ○ ×
selectable for
TMRB ○ each module
×
WDT ○ ×
AMP/CMP ○ ○ ○ (Note 2)
VLTD ○ ○ ○ (Note 2)
POR ○ ○ ○ (Note 2)
CG ○ ○ ×
PLL ○ ○ ×
High-speed oscillator (fc) ○ ○ ×
○: Operating, ×: Stopped
(Note 1) The state depends on the CGSYSCR<DRVE> bit.
(Note 2) The blocks are not stopped even though the clock is halted.

TMPM370
6.6.5 Releasing the Low Power Consumption Mode
The low power consumption mode can be released by an interrupt request or reset. The release
source that can be used is determined by the low power consumption mode selected. Details are
shown in Table 6-6.
Table 6-6 Release Source in Each Mode

Low power consumption mode IDLE STOP
INT0 to INTF (Note 1) ○ ○
INTRX0 to 3, INTTX0 to 3 ○ ×
INTVCNA, INTVCNB ○ ×
INTEMG0 to 1 ○ ×
INTOVV0 to 1 ○ ×
INTTB0 to 7 ○ ×
Interrupt INTPMD0 to 1 ○ ×
Release
INTENC0 to 1 ○ ×
source
INTCAP00, 01, 10, 11, 20, 21, 30, 31, 40, 41, 50, 51, 60, 61, 70, 71 ○ ×
INTAD0PDA, INTAD1PDA, INTAD0PDB, INTAD1PDB ○ ×
INTAD0CPA, INTAD1CPA, INTAD0CPB, INTAD1CPB ○ ×
INTAD0SFT, INTAD1SFT ○ ×
INTAD0TMR, INTAD1TMR ○ ×
NMI (INTWDT) ○ ×
RESET (RESET pin) ○ ○
○: Starts the interrupt handling after the mode is released. (The reset
initializes the LSI).
×: Unavailable
(Note 1) To release the low power consumption mode by using the level mode interrupt,
keep the level until the interrupt handling is started. Changing the level before
then will prevent the interrupt handling from starting properly.
(Note 2) For shifting to the low power consumption mode, set the CPU to prohibit all the
interrupts other than the release source. If not, releasing may be executed by an
unspecified interrupt.
● Release by interrupt request

To release the low power consumption mode by an interrupt, the CPU must be set in advance to
detect the interrupt. In addition to the setting in the CPU, the clock generator must be set to detect
the interrupt to be used to release the STOP modes.
● Release by Non-Maskable Ininterrupt (NMI)

There is a watchdog timer interrupt (INTWDT) as a non-maskable interrupt source. INTWDT can
only be used in the IDLE mode.
● Release by reset
------------------------------
Any low power consumption modes can be released by reset from the R E S E T pin. After that, the
mode switches to NORMAL and all the registers are initialized as is the case with normal reset.
Note that returning to NORMAL mode by reset does not induce the automatic warm-up. Keep the
reset signal valid until the oscillator operation becomes stable.
Refer to “Interrupts" for details.

TMPM370
6.6.6 Warm-up
Mode transition requires the warm-up for stabilization of the internal circuit.
In the mode transition from STOP to NORMAL, the warm-up counter is activated automatically.
And then the system clock output is started after the elapse of configured warm-up time. It is
necessary to set the oscillator to be used for warm-up in the CGOCCR<WUPSEL> and to set the
warm-up time in the CGOSCCR<WUODR13:0> before executing the instruction to enter the STOP
mode.
(Note) In STOP mode, the PLL is disabled. When returning from these modes, configure
the warm-up time in consideration of the stability time of the PLL and the internal
oscillator. It takes approx. 200μs for the PLL to be stabilized.
Table 6-7 shows whether the warm-up setting of each mode transition is required or not.
Table 6-7 Warm-up setting in mode transition

Mode transition Warm-up setting
NORMAL→IDLE Not required
NORMAL→STOP Not required
IDLE→NORMAL Not required
STOP→NORMAL Auto-warm-up (Note 1)
(Note 1) Returning to NORMAL mode by reset does not induce the automatic warm-up.
Keep the reset signal valid until the oscillator operation becomes stable.

TMPM370
6.6.7 Clock Operations in Mode Transition
The clock operations in mode transition are described in the following section.
6.6.7.1 Transition of operation modes: NORMAL→STOP→NORMAL
When returning to NORMAL mode from STOP mode, the warm-up is activated automatically. It is
necessary to set the warm-up time before entering the STOP mode.
Returning to NORMAL mode by reset does not induce the automatic warm-up. Keep the reset signal
asserted until the oscillator operation becomes stable.
WFI instruction / Release event

sleep-on-exit occurs.
Mode NORMAL STOP NORMAL
fosc
Warm-up
fsys
(System clock)
System clock High-speed clock starts oscillating. Warm-up completes.

stops. Warm-up starts. System clock starts.

TMPM370
7. Exceptions
This chapter describes features, types and handling of exceptions.
Exceptions have close relation to the CPU core. Refer to “Cortex-M3 Technical Reference Manual” if
needed.
7.1 Overview
An exception causes the CPU to stop the currently executing process and handle another process.
There are two types of exceptions: those that are generated when some error condition occurs or when
an instruction to generate an exception is executed; and those that are generated by hardware, such as an
interrupt request signal from an external pin or peripheral function.
All exceptions are handled by the Nested Vectored Interrupt Controller (NVIC) in the CPU according to
the respective priority levels. When an exception occurs, the CPU stores the current state to the stack
and branches to the corresponding interrupt service routine (ISR). Upon completion of the ISR, the
information stored to the stack is automatically restored.
7.1.1 Exception Types

The following types of exceptions exist in the Cortex-M3.
For detailed descriptions on each exception, refer to “Cortex-M3 Technical Reference Manual”.
z Reset
z Non-Maskable Interrupt (NMI)
z Hard Fault
z Memory Management
z Bus Fault
z Usage Fault
z SVCall (Supervisor Call)
z Debug Monitor
z PendSV
z SysTick
z External Interrupt
TMPM370 7-1 Interrupt

TMPM370
7.1.2 Handling Flowchart
The following shows how an exception/interrupt is handled. In the following descriptions,

indicates hardware handling. Indicates software handling.
Each step is described later in this chapter.
Processing Description See
Detection by CG/CPU The CG/CPU detects the exception request. Section 7.1.2.1
Handling by CPU The CPU handles the exception request.

Section 7.1.2.2
The CPU branches to the corresponding

Branch to ISR
interrupt service routine (ISR).
Execution of ISR Necessary processing is executed。 Section 7.1.2.3
The CPU branches to another ISR or returns

Return from exception Section 7.1.2.4
to the previous program.

TMPM370
7.1.2.1 Exception Request and Detection
(1) Exception occurrence

Exception sources include instruction execution by the CPU, memory accesses, and interrupt requests
from external interrupt pins or peripheral functions.
An exception occurs when the CPU executes an instruction that causes an exception or when an error
condition occurs during instruction execution.
An exception also occurs by an instruction fetch from the Execute Never (XN) region or an access
violation to the Fault region.
An interrupt request is generated from an external interrupt pin or peripheral function. For interrupts that
are used for releasing a standby mode, relevant settings must be made in the clock generator. For
details,refer to “7.5 Interrupts”.
(2) Exception detection
If multiple exceptions occur simultaneously, the CPU takes the exception with the highest priority.
Table 7-1 shows the priority of exceptions. “Configurable” means that you can assign a priority level to that
exception. Memory Management, Bus Fault and Usage Fault exceptions can be enabled or disabled. If a
disabled exception occurs, it is handled as Hard Fault.

TMPM370
Table 7-1 Exception Types and Priority

No Exception type Priority Description
１ Reset -3 (highest) Reset pin, WDT ,POR, VLTD, OFD or SYSRESETREQ
Non-Maskable
2 -2 WDT
Interrupt
Fault that cannot activate because a higher-priority
3 Hard Fault -1
fault is being handled or it is disabled
Exception from the Memory Protection Unit (MPU)
Memory
4 Configurable (Note 1)
Management
Instruction fetch from the Execute Never (XN) region
Access violation to the Hard Fault region of the
5 Bus Fault Configurable
memory map
Undefined instruction execution or other faults related
6 Usage Fault Configurable
to instruction execution
7-10 Reserved
11 SVCall Configurable System service call with SVC instruction
12 Debug Monitor Configurable Debug monitor when the core is not halting
13 Reserved
14 PendSV Configurable Pendable system service request
15 SysTick Configurable Notification from system timer
Configurable External interrupt pin or peripheral
16- External Interrupt Configurable
function (Note 2)
(Note 1) This product does not contain the MPU

(Note 2) External interrupts have different sources and numbers in each product. For details,
see “7.5.1.5 List of Interrupt Factors”.
(3) Priority setting
z Priority levels
The external interrupt priority is set to the interrupt priority register and other exceptions are set to
<PRI_n> bit in the system handler priority register.
The configuration <PRI_n> can be changed, and the number of bits required for setting the priority
varies from 3 bits to 8 bits depending on products. Thus, the range of priority values you can specify is
different depending on products.
In case of 8-bit configuration, the priority can be configured in the range from 0 to 255. The highest
priority is “0”. If multiple elements with the same priority exist, the smaller the number, the higher the
priority becomes.
(Note) <PRI_n> bit is dfined as a 3-bit configuration with this product.

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z Priority groping
The priority group can be split into groups. By setting the <PRIGROUP> of the application interrupt
and reset control register, <PRI_n> can be divided into the pre-emption priority and the sub priority.
A priority is compared with the pre-emption priority. If the priority is the same as the preemption
priority, then it is compared with the sub priority. If the sub priority is the same as the priority, the smaller
the exception number, the higher the priority.
The Table 7-2 Priority grouping setting shows the priority group setting. The pre-emption priority and
the sub priority in the table are the number in the case that <PRI_n> is defined as an 8-bit configuration.
Table 7-2 Priority grouping setting

<PRI_n[7:0]> Number of
<PRIGROUP[2:0]> Number of
Pre-emption Subpriority pre-emption
setting subpriorities
field field priorities
000 [7:1] [0] 128 2
001 [7:2] [1:0] 64 4
010 [7:3] [2:0] 32 8
011 [7:4] [3:0] 16 16
100 [7:5] [4:0] 8 32
101 [7:6] [5:0] 4 64
110 [7] [6:0] 2 128
110 None [7:0] 1 256
(Note) If the configuration of <PRI_n> is less than 8 bits, the lower bit is "0".
For the example, in the case of 3-bit configuration, the priority is set as <PRI_n[7:5]>
and <PRI_n[4:0]> is "00000".

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7.1.2.2 Exception Handling and Branch to the Interrupt Service Routine

(Pre-emption)
When an exception occurs, the CPU suspends the currently executing process and branches to the
interrupt service routine. This is called “pre-emption”.
(1) Stacking
When the CPU detects an exception, it pushes the contents of the following eight registers to the stack
in the following order:
・Program Counter (PC)

・ Program Status Register (xPSR)
・ r0 - r3
・ r12
・ Link Register (LR)
The SP is decremented by eight words by the completion of the stack push. The following shows the
state of the stack after the register contents have been pushed.
Old SP
<previous>
xPSR
PC
LR
r12
r3
r2
r1
SP r0
(2) Fetching an ISR
The CPU enables instruction to fetch the interrupt processing with data store to the register.
Prepare a vector table containing the top addresses of ISRs for each exception. After reset, the vector
table is located at address 0x0000_0000 in the code space. By setting the Vector Table Offset Register,
you can place the vector table at any address in the code or SRAM space.
The vector table should also contain the initial value of the main stack.

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(3) Late-arriving
If the CPU detects a higher priority exception before executing the ISR for a previous exception, the
CPU handles the higher priority exception first. This is called “late-arriving”.
A late-arriving exception causes the CPU to fetch a new vector address for branching to the
corresponding ISR, but the CPU does not newly push the register contents to the stack.
(4) Vector table
The vector table is configured as shown below.

You must always set the first four words (stack top address, reset ISR address, NMI ISR address, and
Hard Fault ISR address). Set ISR addresses for other exceptions are prepared in case if necessary.
Offset Exception Contents Setting
0x00 Reset Initial value of the main stack Required
0x04 Reset ISR address Required
0x08 Non-Maskable ISR address Required

Interrupt
0x0C Hard Fault ISR address Required
0x10 Memory Management ISR address Optional
0x14 Bus Fault ISR address Optional
0x18 Usage Fault ISR address Optional
0x1C to 0x28 Reserved
0x2C SVCall ISR address Optional
0x30 Debug Monitor ISR address Optional
0x34 Reserved
0x38 PendSV ISR address Optional
0x3C SysTick ISR address Optional
0x40 External Interrupt ISR address Optional

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7.1.2.3 Executing an ISR
An ISR performs necessary processing for the corresponding exception. ISRs must be prepared by
the user.
An ISR may need to include code for clearing the interrupt request so that the same interrupt will not
occur again upon return to normal program execution.
For details about interrupt handling, see “7.5 Interrupts”.
If a higher priority exception occurs during ISR execution for the current exception, the CPU abandons
the currently executing ISR and services the newly detected exception.
7.1.2.4 Exception exit
(1) Execution after returning from an ISR
When returning from an ISR, the CPU takes one of the following actions:
z Tail-chaining
If a pending exception exists and there are no stacked exceptions or the pending exception has higher
priority than all stacked exceptions, the CPU returns to the ISR of the pending exception.
In this case, the CPU skips the pop of eight registers and push of eight registers when exiting one ISR
and entering another. This is called “tail-chaining”.
z Returning to the last stacked ISR

If there are no pending exceptions or if the highest priority stacked exception is higher priority than
the highest priority pending exception, the CPU returns to the last stacked ISR.
z Returning to the previous program

If there are no pending or stacked exceptions, the CPU returns to the previous program.
(2) Exception exit sequence
When returning from an ISR, the CPU performs the following operations:
z Pop eight registers

Pops the eight registers (PC, xPSR, r0 to r3, r12 and LR) from the stack and adjust the SP.

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z Load current active interrupt number

Loads the current active interrupt number from the stacked xPSR. The CPU uses this to track which
interrupt to return to.
z Select SP
If returning to an exception (Handler Mode), SP is SP_main. If returning to Thread Mode, SP can be
SP_main or SP_process.

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7.2 Reset Exceptions
Reset exceptions are generated from the following six sources.

Use the Reset Flag (RSTFLG) Register of the Clock Generator to identify the source of a reset.
・External reset pin

A reset exception occurs when an external reset pin changes from “Low” to “High”.
At least 12 Low level system clock is necessary for reset the device, with the condition that the power
supply is within the operation voltage and high frequency oscilation is stable.
Please refer the “Electrical characteristics” for detail about power supply sequence.
・Reset exception by POR

Please refer the chapter “POR Power on Reset circuit” for detail.
・Reset exception by VLTD

Please refer the chapter “VLTD Voltage Detection Circuit” for detail.
・Reset exception by OFD

Please refer the chapter “OFD Oscillation Frequency Detector” for detail.
・Reset exception by WDT

The watchdog timer (WDT) has a reset generating feature. For details, see the chapter on the WDT.
・Reset exception by SYSRESETREQ

A reset can be generated by setting the SYSRESETREQ bit in the NVIC’s Application Interrupt and
Reset Control Register.
7.3 Non-Maskable Interrupts (NMIs)
The watchdog timer (WDT) has a non-maskable interrupt generating feature. For details, see
the chapter on the WDT.

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7.4 SysTick
SysTick provides interrupt features using the CPU’s system timer.
When you set a value in the SysTick Reload Value Register and enable the SysTick features in the
SysTick Control and Status Register, the counter loads with the value set in the Reload Value Register
and begins counting down. When the counter reaches “0”, a SysTick exception occurs. You may be
pending exceptions and use a flag to know when the timer reaches “0”.
The SysTick Calibration Value Register holds a reload value for counting 10 ms with the system timer.
The count clock frequency varies with each product, and so the value set in the SysTick Calibration Value
Register also varies with each product.
(Note) In this product, the system timer counts based on a clock obtained by dividing the
clock input from the X1 pin by 32.
The SysTick Calibration Value Register is set to 0x9C4, which provides 10 ms timing
when the clock input from X1 is 8 MHz. In case of 10MHz clock input, 10 ms timing is
made by setting 0xC35 to SysTick Reload Register.

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7.5 Interrupts
This chapter describes routes, factors and required settings of interrupts.

The CPU is notified of interrupts by the interrupt signal from each interrupt source.
It sets priority on the interrupts and handles an interrupt request with the highest priority.
Interrupt requests for clearing a standby mode are notified to the CPU via the clock generator.
Therefore, appropriate settings must be made in the clock generator.
7.5.1 Interrupt factors
7.5.1.1 Interrupt route
Fig7.1 shows an interrupt request route.
The interrupts issued by the peripheral function that is not used to release standby are directly input to
the CPU (route1).
The peripheral function interrupts used to release standby (route 2) and interrupts from the external
interrupt pin (route 3) are input to the clock generator and are input to the CPU through the logic for
releasing standby (route 4 and 5).
If interrupts from the external interrupt pins are not used to release standby, they are directly input to
the CPU, not through the logic for standby release (route 6).
Peripheral
function
Interrupt request Rout 1
Rout 5 CPU
Rout 6
<INTxEN>
External Rout 3
Port Exiting
interrupt standby
pin mode
Rout 2
Clock generator
Peripheral
function
Fig 7.1 Interrupt Route

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7.5.1.2 Generation
An interrupt request is generated from an external pin or peripheral function assigned as an interrupt
source or by setting the NVIC’s Interrupt Set-Pending Register.
・From external pin

Set the port control register so that the external pin can perform as an interrupt function pin.
・From peripheral function

Set the peripheral function to make it possible to output interrupt requests.
See chapters of each peripheral function for details.
・By setting Interrupt Set-Pending Register (forced pending)

An interrupt request can be generated by setting the relevant bit of the Interrupt Set-Pending Register.
7.5.1.3 Transmission
An interrupt signal from an external pin or a peripheral function is directly sent to the CPU unless it is
used to exit the standby mode.
Interrupt requests from interrupt sources that can be used for clearing a standby mode is transmitted to
the CPU via the clock generator. For these interrupt sources, appropriate settings must be made in the
clock generator in advance. External interrupt sources not used for exiting a standby mode can be used
without setting the clock generator.
7.5.1.4 Precautions when using external interrupt pins

If you use external interrupts, be aware the followings not to generate unexpected interrupts.
If input disabled (PxIE<PnmIE>="0"), inputs from external interrupt pins are "H". Also, if external
interrupts are not used as a trigger to release standby (route 6 of "Figure 1-1 Interrupt Route"), input
signals from the external interrupt pins are directly sent to the CPU. Since the CPU recognizes "H" input
as an interrupt, interrupts occur if corresponding interrupts are enabled by the CPU as inputs are being
disabled.
To use the external interrupt without setting it as a standby trigger, set the interrupt pin input as "L" and
enable it. Then, enable interrupts on the CPU.

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7.5.1.5 List of Interrupt Sources

Table 7-3 shows the list of interrupt sources.
Table 7-3 List of Hardware Interrupt Sources (1/2)

Active level CG interrupt
INT
Interrupt factors (Clearing mode control
No
standby) register
0 INT0 Interrupt Pin (PH0/AINA0/96pin or 98pin)
High/Low CGIMCGA
Edge/Level
3 INT3 Interrupt Pin (PA0/TB0IN/2pin or 4pin)
Selectable
4 INT4 Interrupt Pin (PA2/TB1IN/4pin or 6pin)
CGIMCGB
5 INT5 Interrupt Pin (PE4/TB2IN//15pin or 17pin)
6 INTRX0 Serial reception (channel.0)
7 INTTX0 Serial transmit (channel.0)
10 INTVCNA Vector Engine interrupt A
11 INTVCNB Vector Engine interrupt B
12 INTEMG0 PMD0 EMG interrupt
13 INTEMG1 PMD1 EMG interrupt
14 INTOVV0 PMD0 OVV interrupt
15 INTOVV1 PMD1 OVV interrupt
16 INTADAPDA ADCA conversion triggered by PMD0 is finished
17 INTADBPDA ADCB conversion triggered by PMD0 is finished
18 INTADAPDB ADCA conversion triggered by PMD1 is finished
19 INTADBPDB ADCB conversion triggered by PMD1 is finished
20 INTTB00 16bit TMRB0 compare match detection 0/ Over flow
21 INTTB01 16bit TMRB0 compare match detection 1
28 INTPMD0 PMD0 PWM interrupt
29 INTPMD1 PMD1 PWM interrupt
30 INTCAP00 16bit TMRB0 input capture 0
38 INT6 Interrupt Pin (PE6/TB3IN//17pin or 19pin) High/Low
39 Edge/Level CGIMCGB
INT7 Interrupt Pin (PE7/TB3OUT/18pin or 20pin)
Selectable
42 INTADACPA ADCA conversion monitoring function interrupt A
43 INTADBCPA ADCB conversion monitoring function interrupt A
44 INTADACPB ADCA conversion monitoring function interrupt B
45 INTADACPB ADCB conversion monitoring function interrupt B

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Table 7-3 List of Hardware Interrupt Sources (2/2)

CG interrupt
Active trigger
No. Interrupt factors mode control
(Clearing standby)
register
54 INTADASFT ADC unit A conversion started by software is finished
55 INTADBSFT ADC unit B conversion started by software is finished
56 INTADATMR ADC unit A conversion triggered by timer is finished
57 INTADBTMR ADC unit B conversion triggered by timer is finished
58 INT8 Interrupt Pin (PA7/TB4IN/9pin or 11pin) High/Low
59 INT9 Interrupt Pin (PD3/33pin or 35pin) Edge/Level CGIMCGC
60 INTA Interrupt Pin (PL1/21pin or 23pin) Selectable
61 INTB Interrupt Pin (PL0/20pin or 22pin)
62 INTENC0 Ender input0 interrupt
63 INTENC1 Ender input1 interrupt
66 INTTB60 16bit TMRB6 compare match detection 0 / Over flow
68 INTTB70 16bit TMRB7 compare match detection 0 / Over flow
74 INTC Interrupt Pin (PJ6/AINB9/74pin or 76 pin)
High/Low
75 INTD Interrupt Pin (PJ7/AINB10/73pin or 75pin)
Edge/Level CGIMCGD
76 INTE Interrupt Pin (PK0/AINB11/72pin or 74pin)
Selectable
77 INTF Interrupt Pin (PK1/AINB12/71pin or 73pin)
7.5.1.6 Active Level

The active level indicates which change in signal of an interrupt source triggers an interrupt. The CPU
recognize interrupt signal in “H” level as interrupt..Interrupt signals directly sent from the peripheral
functions to the CPU are configured to output “H” to indicate an interrupt request.
Active level is set to the clock generator for interrupts which can be a trigger to release standby.
Interrupt requests from peripheral functions are set as rising-edge or falling-edge triggered. Interrupt
requests from interrupt pins can be set as level-sensitive ("High" or "Low") or edge-triggered (rising or
falling).
If an interrupt source is used for clearing a standby mode, setting the relevant clock generator register
is also required. Enable the CGIMCGx<INTxEN> bit and specify the active level in the
CGIMCGx<EMCGx> bits. You must set the active level for interrupt requests from each peripheral
function as shown in Table 7-3.
An interrupt request detected by the clock generator is notified to the CPU with a signal in “H” level .

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7.5.2 Interrupt handling
7.5.2.1 Flowchart
The following shows how an interrupt is handled.

In the following descriptions, indicates hardware handling. indicates software handling.
Processing Details See
7.5.2.2
Set the NVIC registers for detecting interrupts.
Preparation
Set the clock generator as well if the interrupt source is used
to clear a standby mode.
○ Common setting
Settings for detection
NVIC registers
○ Setting to clear standby mode
Clock generator
Execute an appropriate setting to send the interrupt signal

depending on the interrupt type.
○Setting for interrupt from the external pin
Settings for generating Port
interrupt request signal
○Setting for interrupt from peripheral function
Peripheral function (See the chapter of each peripheral
function for details.)
Interrupt generation An interrupt request is generated.
Not clearing
standby mode Clearing standby
mode
Interrupt lines used for clearing a standby mode are 7.5.2.3

CG detects interrupt connected to the CPU via the clock generator. Detection
(clearing standby mode) by Clock
Generator

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Processing Details See
The CPU detects the interrupt. 7.5.2.4

Detection
CPU detects interrupt If multiple interrupt requests occur simultaneously,, the by CPU
interrupt request with the highest priority is selected
according to the priority order.
The CPU handles the interrupt. 7.5.2.5

CPU handles interrupt CPU
The CPU pushes resister contents to the stack before
entering the ISR. processing
Program for the ISR. 7.5.2.6

ISR Execution
Clear the interrupt factor if needed. Interrupt
service
routine
Returning to preceding
Configure to return to the preceding program of the ISR.
program

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7.5.2.2 Preparation
When preparing for an interrupt, it is needed to pay attention to the order of configuration to avoid
any unexpected interrupt on the way.
Initiating an interrupt or changing its configuration must be implemented in the following order
basically. Disable the interrupt by the CPU. Configure from the farthest route from the CPU. Then
enable the interrupt by the CPU.
To configure the clock generator, you must follow the order indicated here not to cause any
unexpected interrupt. First, configure the precondition. Secondly, clear the data related to the interrupt
in the clock generator and then enable the interrupt.
The following sections are listed in the order of interrupt handling and describe how to configure
them.
(1) Disabling interrupt by CPU

(2) CPU registers setting
(3) Preconfiguration 1 (Interrupt from external pin）
(4) Preconfiguration 2 (interrupt from peripheral function）
(5) Preconfiguration 3 (interrupt Set-Pending Register）
(6) Configuring the clock generator
(7) Enabling interrupt by CPU
（１）Disabling interrupt by CPU

To make the CPU for not accepting any interrupt, write “1” to the corresponding bit of the
PRIMASK Register. All interrupts and exceptions other than non-maskable interrupts and hard
faults can be masked.
Use "MSR" instruction to set this register.
●Interrupt mask register

PRIMASK ← “1”(interrupt disabled)
(Note1) PRIMASK register cannot be modified by the user access level.

(Note2) If a fault causes when “1” is set to the PRIMASK register, it is
treated as a hard fault.
（２）CPU interrupt registers setting

You can assign a priority level by writing to <PRI_n> field in an Interrupt Priority Register of the
NVIC registers.
Each interrupt source is provided with eight bits for assigning a priority level from 0 to 255, but
the number of bits actually used varies with each product.Priority level 0 is the highest priority
level.If multiple sources have the same priority, the smallest-numbered interrupt source has the
highest priority.

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You can assign grouping priority by using the PRIGROUP field in the Application Interrupt and
Reset Control Register.
●NVIC register
<PRI_n> ← “Priority”
<PRIGROUP> ← “group priority” (This is configurable if required)
(Note) "n" indicates the corresponding exceptions/interrupts.

This product uses three bits for assigning a priority level.
（３）Preconfiguration 1 (Interrupt from external pin)

Set “1” to the port function register of the corresponding pin. Setting PnFRx[m] allows the pin to
be used as the function pin. Setting PnIE[m] allows the pin to be used as the input port.
● Port register
PnFRx<PnmFRx> ← “1”
PnIE<PnmIE> ← “1”
(Note) n: port number / m: corresponding bit / x: function register number

In modes other than STOP mode, setting PxIE to enable input
enables the corresponding interrupt input regardless of the PnFR
setting. Be careful not to enable interrupts that are not used. Also,
be aware of the description of “Precautions when using external
interrpt pins”
（４）Preconfiguration 2 (interrupt from peripheral function)

The setting varies depending on the peripheral function to be used. See chapters of each
peripheral function for details.
（５）Preconfiguration 3 (interrupt Set-Pending Register)

To generate an interrupt by using the Interrupt Set-Pending Register, set "1" to the
corresponding bit of this register.
● NVIC register
Interrupt Set-Pending[m] ← “1”
(Note) m: corresponding bit
（６）Configuring the clock generator
For an interrupt source to be used for exiting a standby mode, you need to set the active level
and enable interrupts in the CGIMCG register of the clock generator. The CGIMCG register is
capable of configuring each source.
Before enabling an interrupt, clear the corresponding interrupt request already held. This can
avoid unexpected interrupt. To clear corresponding interrupt request, write a value corresponding

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to the interrupt to be used to the CGICRCG register. See “7.6.3.5 CGICRCG (CG Interrupt Clear
Register)” for each value.
Interrupt requests from external pins can be used without setting the clock generator if they are
not used for exiting a standby mode. However, an “H” pulse or “H”–level signal must be input so
that the CPU can detect it as an interrupt request. Also, be aware of the description of “7.5.1.4
Precautions when using external interrupt pins”.
●Clock generator register

CGIMCGn<EMCGm> ← Active level
CGICRCG<ICRCG4-0> ← Value corresponding to the interrupt to be used
CGIMCGn<INTmEN> ← “1” (interrupt enabled)
(Note) n: register number

m: number assigned to each interrupt factor
（７）Enabling interrupt by CPU

Enable the interrupt by the CPU as shown below.
Clear the suspended interrupt in the Interrupt Clear-Pending register. Enable the intended
interrupt with the Interrupt Set-Enable Register. Each bit of the register is assigned to a single
interrupt source.
Writing “1” to the corresponding bit of the Interrupt Clear-Pending Register clears the suspended
interrupt. Writing “1” to the corresponding bit of the Interrupt Set-Enable Register enables the
intended interrupt.
To generate interrupts in the Interrupt Set-Pending Register setting, factors to trigger interrupts
are lost if pending interrupts are cleared. Thus, this operation is not necessary.
At the end, PRIMASK register is zero cleared.
●NVIC register
Interrupt Clear-Pending<m> ← “1”
Interrupt Set-Enable<m> ← “1”
●Interrupt mask register
PRIMASK ← “0”
(Note1) m: corresponding bit

(Note2) PRIMASK register cannot be modified by the user access level.

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7.5.2.3 Detection by Clock Generator
If an interrupt source is used for exiting a standby mode, an interrupt request is detected
according to the active level specified in the clock generator, and is notified to the CPU.
An edge-triggered interrupt request, once detected, is held in the clock generator. A

level-sensitive interrupt request must be held at the active level until it is detected, otherwise the
interrupt request will cease to exist when the signal level changes from active to inactive.
When the clock generator detects an interrupt request, it keeps sending the interrupt signal in
"High" level to the CPU until the interrupt request is cleared in the CG Interrupt Request Clear
(CGICRCG) Register. If a standby mode is exited without clearing the interrupt request, the same
interrupt will be detected again when normal operation is resumed. Be sure to clear each interrupt
request in the ISR.
7.5.2.4 Detection by CPU
The CPU detects an interrupt with the highest priority.
7.5.2.5 CPU processing
On detecting an interrupt, the CPU pushes the contents of PC, PSR, r0-r3, r12 and LR to the
stack then enter the ISR.
7.5.2.6 Interrupt Service Routine (ISR)
An ISR requires specific programming according to the application to be used. This section
describes what is recommended at the service routine programming and how the factor is cleared.
（１）Pushing during ISR

An ISR normally pushes register contents to the stack and handles an interrupt as required. The
Cortex-M3 core automatically pushes the contents of PC, PSR, r0-r3, r12 and LR to the stack. No
extra programming is required for them.
Push the contents of other registers if needed.
Interrupt with the higher priority and exceptions such as NMI are accepted even when an ISR is
being executed. We recommend you to push the contents of general-purpose registers that might
be rewritten.
（２）Clearing interrupt factor

If an interrupt source is used for clearing a standby mode, each interrupt request must be
cleared with the CG Interrupt Request Clear (CGICRCG) register.

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If an interrupt source is set as level-sensitive, an interrupt request continues to exist until it is

cleared at its source. Therefore, the interrupt source must be cleared. Clearing the interrupt source
automatically clears the interrupt request signal from the clock generator.
If an interrupt is set as edge-sensitive, clear an interrupt request by setting the corresponding
value in the CGICRCG register. When an active edge occurs again, a new interrupt request will
be detected.

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7.6 Exception/Interrupt-related registers

The CPU's NVIC registers and clock generator registers described in this chapter are shown below
with their respective addresses.
7.6.1 Register List

●NVIC Resisters
SysTick Control and Status Resister 0xE000_E010
SysTick Reload Value Resister 0xE000_E014
SysTick Current Value Resister 0xE000_E018
SysTick Calibration Value Register 0xE000_E01C
Interrupt Set-Enable Register 1 0xE000_E100
Interrupt Clear-Enable Register 1 0xE000_E180
Interrupt Set-Pending Register 1 0xE000_E200
Interrupt Clear-Pending Register 1 0xE000_E280
Interrupt Priority Register 0xE000_E400-0xE000_E450
Vector Table Offset Register 0xE000_ED08
Application Interrupt and Reset Control Register 0xE000_ED0C
System Handler Priority Register 0xE000_ED18,0xE000_ED1C,0xE000_ED20
System Handler Control and State Register 0xE000_ED24
●Clock generator registers

CGICRCG CG Interrupt Request Clear Register 0x4004_0214
CGNMIFLG NMI Flag Register 0x4004_0218
CGRSTFLG Reset Flag Register 0x4004_021C
CGIMCGA CG Interrupt Mode Control Register A 0x4004_0220
CGIMCGB CG Interrupt Mode Control Register B 0x4004_0224
CGIMCGC CG Interrupt Mode Control Register C 0x4004_0228
CGIMCGD CG Interrupt Mode Control Register D 0x4004_022C
Reserved - 0x4004_0230
Reserved - 0x4004_023C
(Note) Access to the “Reserved” areas is prohibited.

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7.6.2 NVIC Registers
7.6.2.1 SysTick Control and Status Register
7 6 5 4 3 2 1 0
bit Symbol CLK TICKINT ENABLE
SOURCE
After reset 0 0 0 0
Function “0” is read. 0: External 0: Do not 0: Disable
reference pend 1: Enable
clock SysTick
1: Core 1: Pend
clock SysTick
15 14 13 12 11 10 9 8
bit Symbol
Read/Write R
After reset 0
23 22 21 20 19 18 17 16
bit Symbol COUNT
FLAG
Read/Write R R/W
After reset 0 0
Function “0” is read. 0: Timer not
counted to 0
1: Timer
counted to 0
31 30 29 28 27 26 25 24
bit Symbol
Read/Write R
After reset 0
<bit0> <ENABLE> 1 = The counter loads with the Reload value and then begins counting down.
0 = The timer is disabled.
<bit1> <TICKINT> 1 = SysTick exceptions are pended.
0 = SysTick exceptions are not pended.
<bit2> <CLKSOURCE> 0 = External reference clock
1 = Core clock
<bit16> <COUNTFLAG> 1 =Indicates that the timer counted to 0 since last time this was read.
Clears on read of any part of the SysTick Control and Status Register.

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7.6.2.2 SysTick Reload Value Register
7 6 5 4 3 2 1 0
bit Symbol RELOAD
Read/Write R/W
After reset Undefined
Function Reload value
15 14 13 12 11 10 9 8
bit Symbol RELOAD
Read/Write R/W
23 22 21 20 19 18 17 16
bit Symbol RELOAD
Read/Write R/W
31 30 29 28 27 26 25 24
bit Symbol
Read/Write R
After reset 0
<bit23:0> <RELOAD> Set the value to load into the SysTick Current Value Register when the timer reaches
“0”.

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7.6.2.3 SysTick Current Value Register
7 6 5 4 3 2 1 0
bit Symbol CURRENT
Read/Write R/W
Function [Read] Current SysTick timer value
[Write] Clear
15 14 13 12 11 10 9 8
bit Symbol CURRENT
Read/Write R/W
[Write] Clear
23 22 21 20 19 18 17 16
bit Symbol CURRENT
Read/Write R/W
[Write] Clear
31 30 29 28 27 26 25 24
bit Symbol
Read/Write R
After reset 0
<bit23:0> <CURRENT> [Read] Current SysTick timer value.

[Write] Writing to this register with any value clears it to 0. Clearing this register
also clears the COUNTFLAG bit of the SysTick Control and Status
Register.

TMPM370
7.6.2.4 SysTick Calibration Value Register
7 6 5 4 3 2 1 0
bit Symbol TENMS
Read/Write R
After reset 1 1 0 0 0 1 0 0
Function Calibration value (Note)
15 14 13 12 11 10 9 8
bit Symbol TENMS
Read/Write R
After reset 0 0 0 0 1 0 0 1
23 22 21 20 19 18 17 16
bit Symbol TENMS
Read/Write R
After reset 0 0 0 0 0 0 0 0
31 30 29 28 27 26 25 24
bit Symbol NOREF SKEW
Read/Write R R R
After reset 0 0 0
Function 0: 0: “0” is read.
Reference Calibration
clock value is 10
provided ms.
1: No 1:
reference Calibration
clock value is not
10 ms.
<bit23:0> <TENMS> Reload value to use for 10 ms timing (0x9C4). (Note)

<bit30> <SKEW> 1 = The calibration value is not exactly 10 ms.
<bit31> <NOREF> 1 = The reference clock is not provided.
The SysTick Calibration Value Register is set to a value that provides 10 ms timing
when the cock input from X1 is 8 MHz. In case of 10MHz clock input, 10 ms timing is
made by setting 0xC35 to SysTick Reload Register.

TMPM370
7.6.2.5 Interrupt Set-Enable Register 1

7 6 5 4 3 2 1 0
bit Symbol SETENA
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt
number 7 number 6 number 5 number 4 number 3 number 2 number 1 number 0
[Write] [Write] [Write] [Write] [Write] [Write] [Write] [Write]
1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable
[Read] [Read] [Read] [Read] [Read] [Read] [Read] [Read]
0: Disabled 0: Disabled 0: Disabled 0: Disabled 0: Disabled 0: Disabled 0: Disabled 0: Disabled
1: Enabled 1: Enabled 1: Enabled 1: Enabled 1: Enabled 1: Enabled 1: Enabled 1: Enabled
15 14 13 12 11 10 9 8
bit Symbol SETENA
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
0: Disabled 0: Disabled 0 Disabled 0: Disabled 0: Disabled 0: Disabled 0: Disabled 0: Disabled
23 22 21 20 19 18 17 16
bit Symbol SETENA
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
number 23 number 22 number 21 number 20 number 19 number 18 number 17 number16
31 30 29 28 27 26 25 24
bit Symbol SETENA
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
<bit31:0> <SETENA> Use these bits to enable interrupts or determine which interrupts are currently
enabled.
Writing “1” to a bit in this register enables the corresponding interrupt. Writing “0” has
no effect.
Reading a bit in this register returns the current state of the corresponding interrupt
as shown below.
0 = Disabled
1 = Enabled
(Note) For descriptions of interrupts and interrupt numbers, see Section 7.5.1.5 List of
Interrupt Sources.

TMPM370
7 6 5 4 3 2 1 0
bit Symbol SETENA
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
bit Symbol SETENA
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
bit Symbol SETENA
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
31 30 29 28 27 26 25 24
bit Symbol SETENA
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
enabled.
no effect.
as shown below.
0 = Disabled
1 = Enabled
Interrupt Sources.

TMPM370
7 6 5 4 3 2 1 0
bit Symbol SETENA
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
bit Symbol SETENA
Read/Write R R/W
After reset 0 0 0 0 0 0 0 0
Function “0” is read. Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt
number 77 number 76 number 75 number 74 number 73 number 72
[Write] [Write] [Write] [Write] [Write] [Write]
1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable
[Read] [Read] [Read] [Read] [Read] [Read]
0: Disabled 0: Disabled 0: Disabled 0: Disabled 0: Disabled 0: Disabled
1: Enabled 1: Enabled 1: Enabled 1: Enabled 1: Enabled 1:
Enabled
23 22 21 20 19 18 17 16
bit Symbol
Read/Write R
After reset 0 0 0 0 0 0 0 0
31 30 29 28 27 26 25 24
bit Symbol
Read/Write R
After reset 0 0 0 0 0 0 0 0
enabled.
no effect.
as shown below.
0 = Disabled
1 = Enabled
Interrupt Sources.

TMPM370
7.6.2.8 Interrupt Clear-Enable Register 1
7 6 5 4 3 2 1 0
bit Symbol CLRENA
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
1: Disable 1: Disable 1: Disable 1: Disable 1: Disable 1: Disable 1: Disable 1: Disable
[Read] [Read] [Read] [read] [Read] [Read] [Read] [Read]
0: Disabled 0: Disabled 0: Disabled 0: Disabled 0: Disabled 0: Disabled 0: Disabled 0: Disable
1: Enabled 1: Enabled 1: Enabled 1: Enabled 1: Enabled 1: Enabled 1: Enabled 1: Enable
15 14 13 12 11 10 9 8
bit Symbol CLRENA
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
1: Enabled 1: Enabled 1 Enabled 1: Enabled 1: Enabled 1: Enabled 1: Enabled 1: Enabled
23 22 21 20 19 18 17 16
bit Symbol CLRENA
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
31 30 29 28 27 26 25 24
bit Symbol CLRENA
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
<bit31:0> <CLRENA> Use these bits to disable or determine which interrupts are currently disabled.
Writing “1” to a bit in this register disables the corresponding interrupt. Writing “0”
has no effect.
as shown below.
0 = Disabled
1 = Enabled
Interrupt Sources.

TMPM370
7 6 5 4 3 2 1 0
bit Symbol CLRENA
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
[Read] [Read] [Read] [read] [Read] [Read] [Read] [Read]
0: Disabled 0: Disabled 0: Disabled 0: Disabled 0: Disabled 0: Disabled 0: Disabled 0: Disable
1: Enabled 1: Enabled 1: Enabled 1: Enabled 1: Enabled 1: Enabled 1: Enabled 1: Enable
15 14 13 12 11 10 9 8
bit Symbol CLRENA
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
1: Enabled 1: Enabled 1 Enabled 1: Enabled 1: Enabled 1: Enabled 1: Enabled 1: Enabled
23 22 21 20 19 18 17 16
bit Symbol CLRENA
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
31 30 29 28 27 26 25 24
bit Symbol CLRENA
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
has no effect.
as shown below.
0 = Disabled
1 = Enabled
Interrupt Sources.

TMPM370
7 6 5 4 3 2 1 0
bit Symbol CLRENA
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
bit Symbol CLRENA
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
number 77 number76 number 75 number 74 number 73 number 72
1: Disable 1: Disable 1: Disable 1: Disable 1: Disable 1: Disable
0: Disabled 0: Disabled 0: Disabled 0: Disabled 0: Disabled 0: Disabled
1: Enabled 1: Enabled 1: Enabled 1: Enabled 1: Enabled 1: Enabled
23 22 21 20 19 18 17 16
bit Symbol
Read/Write R
After reset 0
31 30 29 28 27 26 25 24
bit Symbol
Read/Write R
After reset 0
has no effect.
as shown below.
0 = Disabled
1 = Enabled
Interrupt Sources.

TMPM370
7.6.2.11 Interrupt Set-Pending Register 1
7 6 5 4 3 2 1 0
bit Symbol SETPEND
Read/Write R/W
1: Pend 1: Pend 1: Pend 1: Pend 1: Pend 1: Pend 1: Pend 1: Pend
0: Not 0: Not 0: Not 0: Not 0: Not 0: Not 0: Not 0: Not
pending pending pending pending pending pending pending pending
1: Pending 1: Pending 1: Pending 1: Pending 1: Pending 1: Pending 1: Pending 1: Pending
15 14 13 12 11 10 9 8
bit Symbol SETPEND
Read/Write R/W
number 15 number 14 number 13 number 12 number 11 number10 number 9 number 8
23 22 21 20 19 18 17 16
bit Symbol SETPEND
Read/Write R/W
31 30 29 28 27 26 25 24
bit Symbol SETPEND
Read/Write R/W

TMPM370
<bit31:0> <SETPEND> Use these bits to force interrupts into the pending state or determine which
interrupts are currently pending.
Writing “1” to a bit in this register pends the corresponding interrupt. However,
writing “1” has no effect on an interrupt that is already pending or is disabled.
Writing “0” has no effect.
as shown below.
0 = Not pending
1 = Pending
Each bit in this register can be cleared by writing “1” to the corresponding bit in the
Interrupt Clear-Pending Register.
Interrupt Sources.

TMPM370
7 6 5 4 3 2 1 0
bit Symbol SETPEND
Read/Write R/W
15 14 13 12 11 10 9 8
bit Symbol SETPEND
Read/Write R/W
number 47 number 46 number 45 number 44 number 43 number42 number 41 number40
23 22 21 20 19 18 17 16
bit Symbol SETPEND
Read/Write R/W
31 30 29 28 27 26 25 24
bit Symbol SETPEND
Read/Write R/W

TMPM370
as shown below.
0 = Not pending
1 = Pending
Interrupt Sources.

TMPM370
7 6 5 4 3 2 1 0
bit Symbol SETPEND
Read/Write R/W
15 14 13 12 11 10 9 8
bit Symbol SETPEND
Read/Write R R/W
After reset 0 Undefined
1: Pend 1: Pend 1: Pend 1: Pend 1: Pend 1: Pend
0: Not 0: Not 0: Not 0: Not 0: Not 0: Not
pending pending pending pending pending pending
1: Pending 1: Pending 1: Pending 1: Pending 1: Pending 1: Pending
23 22 21 20 19 18 17 16
bit Symbol
Read/Write R
After reset 0
31 30 29 28 27 26 25 24
bit Symbol
Read/Write R
After reset 0
Reading a bit in this register returns the current state of the corresponding
interrupt as shown below.
0 = Not pending
1 = Pending
Interrupt Sources.

TMPM370
7.6.2.14 Interrupt Clear-Pending Register 1
7 6 5 4 3 2 1 0
bit Symbol CLRPEND
Read/Write R/W
1: Clear 1: Clear 1: Clear 1: Clear 1: Clear 1: Clear 1: Clear 1: Clear
interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt
15 14 13 12 11 10 9 8
bit Symbol CLRPEND
Read/Write R/W
23 22 21 20 19 18 17 16
bit Symbol CLRPEND
Read/Write R/W
31 30 29 28 27 26 25 24
bit Symbol CLRPEND
Read/Write R/W

TMPM370
<bit31:0> <CLRPEND> Use these bits to clear pending interrupts or determine which interrupts are
currently pending.
Writing “1” to a bit in this register clears the corresponding pending interrupt.
However, writing “1” has no effect on an interrupt that is already being serviced.
as shown below.
0 = Not pending
1 = Pending
Interrupt Sources.

TMPM370
7 6 5 4 3 2 1 0
bit Symbol CLRPEND
Read/Write R/W
number39 number 38 number 37 number 36 number 35 number 34 number 33 number 32
15 14 13 12 11 10 9 8
bit Symbol CLRPEND
Read/Write R/W
23 22 21 20 19 18 17 16
bit Symbol CLRPEND
Read/Write R/W
31 30 29 28 27 26 25 24
bit Symbol CLRPEND
Read/Write R/W
number 63 number 62 number 61 number 60 number 59 number58 number 57 number 56

TMPM370
currently pending.
as shown below.
0 = Not pending
1 = Pending
Interrupt Sources.

TMPM370
7 6 5 4 3 2 1 0
bit Symbol CLRPEND
Read/Write R/W
15 14 13 12 11 10 9 8
bit Symbol CLRPEND
Read/Write R R/W
After reset 0 Undefined
1: Clear 1: Clear 1: Clear 1: Clear 1: Clear 1: Clear
interrupt interrupt interrupt interrupt interrupt interrupt
0: Not 0: Not 0: Not 0: Not 0: Not 0: Not
1: Pending 1: Pending 1: Pending 1: Pending 1: Pending 1: Pending
23 22 21 20 19 18 17 16
bit Symbol
Read/Write R
After reset 0
31 30 29 28 27 26 25 24
bit Symbol
Read/Write R
After reset 0
currently pending.
Reading a bit in this register returns the current state of the corresponding
interrupt as shown below.
0 = Not pending
1 = Pending
Interrupt Sources.

TMPM370
7.6.2.17 Interrupt Priority Registers
Each interrupt is provided with eight bits of an Interrupt Priority Register.

The following shows the addresses of the Interrupt Priority Registers corresponding to interrupt
numbers.
31 24 23 16 15 8 7 0
0xE000_E400 PRI_3 PRI_2 PRI_1 PRI_0
0xE000_E40C PRI_15 PRI_14 PRI_13 PRI_12
0xE000_E44C - - PRI_77 PRI_76
The number of bits to be used for assigning a priority varies with each product. This product uses three
bits for assigning a priority.
The following shows the fields of the Interrupt Priority Registers for interrupt numbers 0 to 3. The
Interrupt Priority Registers for all other interrupt numbers have the identical fields. Unused bits return “0”
when read, and writing to unused bits has no effect.

TMPM370
7 6 5 4 3 2 1 0
bit Symbol PRI_0
Read/Write R/W R
After reset 0 0
Function Priority of interrupt number 0 “0” is read.
15 14 13 12 11 10 9 8
bit Symbol PRI_1
Read/Write R/W R
After reset 0 0
23 22 21 20 19 18 17 16
bit Symbol PRI_2
Read/Write R/W R
After reset 0 0
31 30 29 28 27 26 25 24
bit Symbol PRI_3
Read/Write R/W R
After reset 0 0
<bit7:5> <PRI_0> Priority of interrupt number 0


TMPM370
7.6.2.18 Vector Table Offset Register
7 6 5 4 3 2 1 0
bit Symbol TBLOFF
Read/Write R/W R
After reset 0 0
Function Offset value “0” is read.
15 14 13 12 11 10 9 8
bit Symbol TBLOFF
Read/Write R/W
After reset 0
Function Offset value
23 22 21 20 19 18 17 16
bit Symbol TBLOFF
Read/Write R/W
After reset 0
Function Offset value
31 30 29 28 27 26 25 24
bit Symbol TBLBA TBLOFF
SE
After reset 0 0 0
Function “0” is read. Table base Offset value
<bit28:7> <TBLOFF> Set the offset value from the top of the space specified in TBLBASE.
The offset must be aligned based on the number of exceptions in the table. This
means that the minimum alignment is 32 words that you can use for up to 16
interrupts. For more interrupts, it is necessary to adjust the alignment by rounding
up to the next power of two.
<bit29> <TBLBASE> The vector table is in:
0 = Code space
1 = SRAM space

TMPM370
7.6.2.19 Application Interrupt and Reset Control Register
7 6 5 4 3 2 1 0
bit Symbol SYS VECT VECT
RESET CLR RESET
REQ ACTIVE
After reset 0 0 0 0 0 0 0 0
Function “0” is read. System Clear active System
Reset vector bit Reset bit
Request.
15 14 13 12 11 10 9 8
bit Symbol ENDIAN PRIGROUP
ESS
Read/Write R/W R R R R R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
Function Endiannes “0” is read. Interrupt priority grouping
s bit
23 22 21 20 19 18 17 16
bit Symbol VECTKEY/VECTKEYSTAT
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function Register key
[Write] Writing to this register requires 0x5FA in the <VECTKEY> field.
[Read] Read as 0xFA05
31 30 29 28 27 26 25 24
bit Symbol VECTKEY/VECTKEYSTAT
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function Register key
[Write] Writing to this register requires 0x5FA in the <VECTKEY> field.
[Read] Read as 0xFA05
<bit0> <VECTRESET> System Reset bit

1: reset system
0: do not reset system
Resets the system, with the exception of debug components (FPB, DWT
and ITM) by setting "1" and this bit is also zero cleared.
<bit1> <VECTCLRACTIVE> Clear active vector bit
1: clear all state information for active NMI, fault, and interrupts
0: do not clear.
This bit self-clears.
It is the responsibility of the application to reinitialize the stack.
<bit2> <SYSRESETREQ> System Reset Request.
1=CPU outputs a SYSRESETREQ signal. (note2)
<bit10:8> <PRIGROUP> Interrupt priority grouping
000: seven bits of pre-emption priority, one bit of subpriority
001: six bits of pre-emption priority, two bits of subpriority
010: five bits of pre-emption priority, three bits of subpriority
011: four bits of pre-emption priority, four bits of subpriority
100: three bits of pre-emption priority, five bits of subpriority
101: two bits of pre-emption priority, six bits of subpriority
110: one bit of pre-emption priority, seven bits of subpriority
111: no pre-emption priority, eight bits of subpriority
The bit configuration to split the interrupt priority register <PRI_n> into
pre-emption priority and sub priority.
<bit15> <ENDIANESS> Endianness bit:(Note1)

TMPM370
1: big endian
0: little endian
<bit31:16> VECTKEY/ Register key
VECTSTAT [Write] Writing to this register requires 0x5FA in the <VECTKEY> field.
[Read] Read as 0xFA05.
(Note1) Little-endian is the default memory format for this product.

(Note2) When SYSRESETREQ is output, warm reset is performed on this product.
<SYSRESETREQ> is cleared by warm reset.

TMPM370
7.6.2.20 System Handler Priority Registers
System Handler Priority Registers have eight bits per each exception.
The following shows the addresses of the System Handler Priority Registers corresponding to each
exception.
31 24 23 16 15 8 7 0
0xE000_ED18 PRI_7 PRI_6 PRI_5 PRI_4
(Usage Fault) (Bus Fault) (Memory
Management)
0xE000_ED1C PRI_11 PRI_10 PRI_9 PRI_8
(SVCall)
0xE000_ED20 PRI_15 PRI_14 PRI_13 PRI_12
(SysTick) (PendSV) (Debug Monitor)
The number of bits to be used for assigning a priority varies with each product. This product uses three
bits for assigning a priority.
The following shows the fields of the System Handler Priority Registers for Memory Management, Bus
Fault and Usage Fault. The System Handler Priority Registers for all other exceptions have the identical
fields. Unused bits return “0” when read, and writing to unused bits has no effect.
7 6 5 4 3 2 1 0
bit Symbol PRI_4
Read/Write R/W R
After reset 0 0
Function Priority of Memory Management “0” is read.
15 14 13 12 11 10 9 8
bit Symbol PRI_5
Read/Write R/W R
After reset 0 0
Function Priority of Bus Fault “0” is read.
23 22 21 20 19 18 17 16
bit Symbol PRI_6
Read/Write R/W R
After reset 0 0
Function Priority of Usage Fault “0” is read.
31 30 29 28 27 26 25 24
bit Symbol PRI_7
Read/Write R/W R
After reset 0 0
Function Reserved “0” is read.

TMPM370
7.6.2.21 System Handler Control and State Register
7 6 5 4 3 2 1 0
bit Symbol SVCALL USG BUS MEM
ACT FAULT FAULT FAULT
ACT ACT ACT
Read/Write R/W R R/W R R/W R/W
After reset 0 0 0 0 0 0
Function SVCall “0” is read. Usage fault “0” is read. Bus fault Memory
Management
0: Inactive 0: Inactive 0: Inactive 0: Inactive
1: Active 1: Active 1: Active 1: Active
15 14 13 12 11 10 9 8
bit Symbol SVCALL BUS MEM USG SYSTICK PENDSV MONI
PENDED FAULT FAULT FAULT ACT ACT TOR
PENDED PENDED PENDED ACT
Read/Write R/W R/W R/W R/W R/W R/W R R/W
After reset 0 0 0 0 0 0 0 0
Function SVCall Bus Fault Memory Usage SysTick PendSV “0” is read. Debug
Management Fault Monitor
0: Not 0: Not 0: Not 0: Not 0: Inactive 0: Inactive 0: Inactive
pended pended pended pended 1: Active 1: Active 1: Active
1: Pended 1: Pended 1: Pended 1: Pended
23 22 21 20 19 18 17 16
bit Symbol USG BUS MEM
FAULT FAULT FAULT
ENA ENA ENA
After reset 0 0 0 0
Function “0” is read. Usage Bus Fault Memory
Fault Management
0: Disable 0: Disable 0: Disable
1: Enable 1: Enable 1: Enable
31 30 29 28 27 26 25 24
bit Symbol
Read/Write R
After reset 0
<bit0> <MEMFAULTACT> Reads as “1” if Memory Management is active.

<bit1> <BUSFAULTACT> Reads as “1” if Bus Fault is active.
<bit3> <USGFALTACT> Reads as “1” if Usage Fault is active.
<bit7> <SVCALLACT> Reads as “1” if SVCall is active.
<bit8> <MONITORACT> Reads as “1” if Debug Monitor is active.
<bit10> <PENDSVACT> Reads as “1” if PendSV is active.
<bit11> <SYSTICKACT> Reads as “1” if SysTick is active.
<bit12> <USGFAULTPENDED> Reads as “1” if Usage Fault is pended.
<bit13> <MEMFAULTPENDED> Reads as “1” if Memory Management is pended.
<bit14> <BUSFAULTPENDED> Reads as “1” if Bus Fault is pended.
<bit15> <SVCALLPENDED> Reads as “1” if SVCall is pended.

TMPM370
<bit16> <MEMFAULTENA> Set to “0” to disable or “1” to enable Memory Management.

<bit17> <BUSFAULTENA> Set to “0” to disable or “1” to enable Bus Fault.
<bit18> <USGFAULTENA> Set to “0” to disable or “1” to enable Usage Fault.
(Note) Extreme caution is needed to clear or set the active bits, because clearing and setting
these bits does not repair stack contents.

TMPM370
7.6.3 Clock Generator Registers

7.6.3.1 CG Interrupt Mode Control Register A
This resister set the clearing standby request active level of external interrupt INT0 to INT3.
7 6 5 4 3 2 1 0
CGIMCGA bit Symbol EMCG02 EMCG01 EMCG00 EMST01 EMST00 INT0EN
Read/Write R R/W R R R/W
After reset 0 0 1 0 0 0 Undefined 0
Function “0” is read Active state setting of INT0 standby Active state of INT0 Reads as INT0 clear
clear request. (101~111: setting standby clear request undefined. input
prohibited)
000: “L” level 00: － 0: Disable
001: “H” level 01: Rising edge 1: Enable
010: Falling edge 10: Falling edge
011: Rising edge 11: Both edges
100: Both edges
15 14 13 12 11 10 9 8
bit Symbol EMCG12 EMCG11 EMCG10 EMST11 EMST10 INT1EN
clear request. (101 to 111: setting standby clear request undefined. input
prohibited)
100: Both edges
23 22 21 20 19 18 17 16
prohibited)
100: Both edges
31 30 29 28 27 26 25 24
prohibited)
100: Both edges
(Note1) EMSTxx is effective only when EMCGxx is set to "100" for both rising and falling
edge. The active level used for the reset of standby can be checked by referring
EMSTxx. If interrupts are cleared with the CGICRCG register, EMSTxx is also
cleared.
(Note2) Please specify the bit for the edge first and then specify the bit for the <INTxEN>.
Setting them simultaneously is prohibited.

TMPM370
7.6.3.2 CG Interrupt Mode Control Register B
This resister set the clearing standby request active level of external interrupt INT4 to INT7.
7 6 5 4 3 2 1 0
CGIMCGB bit Symbol EMCG42 EMCG41 EMCG40 EMST41 EMST40 INT4EN
prohibited)
100: Both edges
15 14 13 12 11 10 9 8
prohibited)
100: Both edges
23 22 21 20 19 18 17 16
prohibited)
100: Both edges
31 30 29 28 27 26 25 24
prohibited)
100: Both edges
cleared.

TMPM370
7.6.3.3 CG Interrupt Mode Control Register C
This resister set the clearing standby request active level of external interrupt INT8 to INTB.
7 6 5 4 3 2 1 0
CGIMCGC bit Symbol EMCG82 EMCG81 EMCG80 EMST81 EMST80 INT8EN
prohibited)
100: Both edges
15 14 13 12 11 10 9 8
prohibited)
100: Both edges
23 22 21 20 19 18 17 16
bit Symbol EMCGA2 EMCGA1 EMCGA0 EMSTA1 EMSTA0 INTAEN
Function “0” is read Active state setting of INTA standby Active state of INTA Reads as INTA clear
prohibited)
100: Both edges
31 30 29 28 27 26 25 24
bit Symbol EMCGB2 EMCGB1 EMCGB0 EMSTB1 EMSTB0 INTBEN
Function “0” is read Active state setting of INTB standby Active state of INTB Reads as INTB clear
prohibited)
100: Both edges
cleared.

TMPM370
7.6.3.4 CG Interrupt Mode Control Register D
This resister set the clearing standby request active level of external interrupt INTC to INTF.
7 6 5 4 3 2 1 0
CGIMCGD bit Symbol EMCGC2 EMCGC1 EMCGC0 EMSTC1 EMSTC0 INTCEN
Read/Write R R/W R R/W
Function “0” is read Active state setting of INTC standby Active state of INTC Reads as INTC clear
prohibited)
100: Both edges
15 14 13 12 11 10 9 8
bit Symbol EMCGD2 EMCGD1 EMCGD0 EMSTD1 EMSTD0 INTDEN
Function “0” is read Active state setting of INTD standby Active state of INTD Reads as INTD clear
prohibited)
100: Both edges
23 22 21 20 19 18 17 16
bit Symbol EMCGE2 EMCGE1 EMCGE0 EMSTE1 EMSTE0 INTEEN
Function “0” is read Active state setting of INTE standby Active state of INTE Reads as INTE clear
prohibited)
100: Both edges
31 30 29 28 27 26 25 24
bit Symbol EMCGF2 EMCGF1 EMCGF0 EMSTF1 EMSTF0 INTFEN
Function “0” is read Active state setting of INTF standby Active state of INTF Reads as INTF clear
prohibited)
100: Both edges
cleared.

TMPM370
Be sure to set active state of the Standby clear request, in case the interrupt is enabled for clearing the
Standby modes.
(Note 1) When using interrupts, be sure to follow the sequence of actions shown below:
1) If the external intrrupt request pin shared with other general ports, enable the port to receive the
interrupt.
2) Set conditions such as active state upon initialization.
3) Clear interrupt requests.
4) Enable interrupts.
(Note 2) Each settings must be performed while interrupts are disabled.
(Note 3) For clearing the Standby modes , 16 interrupt factors (INT0 to INTF) are available. CGIMCGA to
CGIMCGD Resisters in CG are used for selecting edge/level of active state and which
aforementioned factors are used for clearing the standby modes.
(Note 4) In case the standby mode clear is not required, INT0 to INTF can be used as a normal interrupt
without setting CGIMCGA to CGIMCGD Resisters in CG.

TMPM370
7.6.3.5 CG Interrupt Clear Request Register
This resister clear the Interrupt request from INT0 to INTF.
7 6 5 4 3 2 1 0
CGICRCG bit Symbol ICRCG4 ICRCG3 ICRCG2 ICRCG1 ICRCG0
Read/Write R W
Function “0” is read. Clear interrupt requests
0_0000:INT0 0_1000:INT8
0_0001:INT1 0_1001:INT9
0_0010:INT2 0_1010:INTA
0_0011:INT3 0_1011:INTB
0_0100:INT4 0_1100:INTC
0_0101:INT5 0_1101:INTD
0_0110:INT6 0_1110:INTE
0_0111:INT7 0_1111:INTF
1_0000 to 1_1111: setting prohibited
* ”0” is read.
15 14 13 12 11 10 9 8
bit Symbol
Read/Write R
After reset 0
Function “0” is read.。
23 22 21 20 19 18 17 16
bit Symbol
Read/Write
After reset
Function “0” is read.。
31 30 29 28 27 26 25 24
bit Symbol
Read/Write R
After reset 0

TMPM370
7.6.3.6 NMI Flag Register
NMI Flag resister is a resister for reading NMI generation status.
CGNMIFLG 7 6 5 4 3 2 1 0
bit Symbol NMIFLG0
Read/Write R
After reset 0 0 0 0 0 0 0 0
Function “0” is read. NMI factor

generation
flag
0:not
applicable
1:
generated
from WDT
15 14 13 12 11 10 9 8
bit Symbol
Read/Write R
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
bit Symbol
Read/Write R
After reset 0 0 0 0 0 0 0 0
31 30 29 28 27 26 25 24
bit Symbol
Read/Write R
After reset 0 0 0 0 0 0 0 0
(Note) <NMIFLG0> is cleared to “0” when it is read.

TMPM370
7.6.3.7 Reset Flag Register
Reset Flag Resister is a resister for reading internal Reset generation status per generation factors.
Since this register is not cleared automatically, it is necceary to write “0” to clear the register.
CGRSTFLG 7 6 5 4 3 2 1 0
bit Symbol OFDRSTF SYSRSTF VLTDRSTF WDTRSTF PINRSTF PONRSTF
Read/Write R R/W R/W R/W R/W R/W R/W
After pin reset 0 0 0 0 0 0 0 1/0
Function “0” is read. OFD reset Debug reset VLTD reset WDT reset RESETpin Power On
flag flag (Note 1) flag. flag flag Reset
flag
0：“0” is 0： “0” is 0： “0” is 0：“0” is 0： “0” is 0： “0” is

written written written written written written
1：Reset 1：Reset 1：Reset 1：Reset 1：Reset 1：Reset
from OFD from from from WDT from from
debugger VLTD RESET Power On
pin Reset
15 14 13 12 11 10 9 8
bit Symbol
Read/Write R
After pin reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
bit Symbol
Read/Write R
31 30 29 28 27 26 25 24
bit Symbol
Read/Write R
(Note 1) This flag indicates a reset generated by the SYSRESETREQ bit of the Application
Interrupt and Reset Control Register of the CPU's NVIC.
(Note 2) This register is not cleared automatically. Write "0" to clear the register.

TMPM370
8 Input/Output Ports
8.1 Port registers
PxDATA : Port data register

To read/write port data.
PxCR : Output control Register

To control enable/disable output.
* To enable/disable input, controled by PxIE register.
PxFRn : Function control Register

To set functions. An assigned function can be activated by setting “1”.
PxOD : Open Drain control register

To switch CMOS output or open drain output.
PxPUP : Port Pull-Up control register

To enable/disable pull-up resister.
PxPDN : Port Pull-Down control register

To enable/disable pull-down resister.
PxIE : Input Enable control register

To enable/disable input. Default setting is disabled for avoiding through current.
TMPM370 8-1 Input/Output Ports

TMPM370
8.2 Port Functions
8.2.1 Port States in Stop Mode

Input and output in Stop mode are enabled/disabled by the CGSTBYCR<DRVE> bit in the Standby
Control Register
If PxIE or PxCR is enabled with <DRVE>=1, input or output is enabled respectively in STOP mode.
If <DRVE>=0, both input and output are disabled in STOP mode except for some ports even if PxIE
and PxCR are enabled.
The differences are summarized in the table shown below.
Table 8.1 Differences of <DRVE> setting
Port I/O <DRVE>=0 <DRVE>=1

Depends on
PB3,PB5 Input ×
PxIE<n>
[When used for debug(PxFR<n>=1) and output is
Enable when data is valid.
enabled(PxCR<n>=1)] Output
Disable when data is invalid.
PH0-2,PA0,PA2,PE4,PE6-7,PA7,PD3,PL0-1,PJ6-7,PK0-1 Input O O
[When used for interrupt(PxFR<n>=1) and input is
Depends on
enabled(PxIE<n>=1)] Output ×
PxCR<n>
Depends on
Input ×
PxIE<n>
Other ports
Depends on
Output ×
PxCR<n>
O：Input or Output enabled
×：Input or Output disabled

TMPM370
8.2.2 Port A (PA0 to PA7)
The port A is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be
specified in units of bits. Besides the general-purpose input/output function, the port A performs the
serial interface function and the external interrupt input and 16-bit timer input and 16-bit timer output.
Reset initializes all bits of the port A as general-purpose ports with input, output, pull-up and pull-down
disabled.
To use the external interrupt input for releasing STOP mode, select this function in the PAFR2 register
and enable input in the PAIE register. These settings enable the interrupt input even if the
CGSTBYCR<DRVE> bit in the clock/mode control block is set to stop driving of pins during STOP
mode.
(Note) In modes other than STOP mode, interrupt input is enabled regardless of the PxFR
register setting as long as input is enabled in PxIE. Make sure to disable unused
interrupts when programming the device.
Port A circiut types

7 6 5 4 3 2 1 0
Type T12 T11 T13 T9 T2 T12 T2 T12
Port A register
7 6 5 4 3 2 1 0
PADATA Bit Symbol PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
(0x4000_0000) Read/Write R/W
After reset “0”
Port A control register

7 6 5 4 3 2 1 0
PACR Bit Symbol PA7C PA6C PA5C PA4C PA3C PA2C PA1C PA0C
After reset 0 0 0 0 0 0 0 0
Function Output
0: disabled
1: enabled
Port A function register 1

7 6 5 4 3 2 1 0
PAFR1 Bit Symbol PA7F1 PA6F1 PA5F1 PA4F1 PA3F1 PA2F1 PA1F1 PA0F1
After reset 0 0 0 0 0 0 0 0
Function 0:PORT 0:PORT 0:PORT 0:PORT 0:PORT 0:PORT 0:PORT 0:PORT
1:TB4IN 1:RXD1 1:TXD1 1:SCLK1 1:TB1OUT 1:TB1IN 1:TB0OUT 1:TB0IN

TMPM370
Port A function register 2

7 6 5 4 3 2 1 0
PAFR2 Bit Symbol PA7F2 PA6F2 PA5F2 PA4F2 － PA2F2 － PA0F2
(0x4000_000C) Read/Write R/W R R/W R R/W
After reset 0 0 0 0 0 0 0 0
Function 0:PORT 0:PORT 0:PORT 0:PORT “0” is read. 0:PORT “0” is read. 0:PORT
__________
1 INT8 1:TB6IN 1:TB6OUT 1:CTS1 1:INT4 1:INT3
Port A open drain Control register

7 6 5 4 3 2 1 0
PAOD Bit Symbol PA7OD PA6OD PA5OD PA4OD PA3OD PA2OD PA1OD PA0OD
(0x4000_ 0028) Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function 0:CMOS
1: open drain
Port A pull-up control register

7 6 5 4 3 2 1 0
PAPUP Bit Symbol PA7UP PA6UP PA5UP PA4UP PA3UP PA2UP PA1UP PA0UP
(0x4000_002C) Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function Pull-up
0: disabled
1: enabled
Port A pull-down control register

7 6 5 4 3 2 1 0
PAPDN Bit Symbol PA7DN PA6DN PA5DN PA4DN PA3DN PA2DN PA1DN PA0DN
After reset 0 0 0 0 0 0 0 0
Function Pull-down
0: disabled
1: enabled
Port A input enable control register

7 6 5 4 3 2 1 0
PAIE Bit Symbol PA7IE PA6IE PA5IE PA4IE PA3IE PA2IE PA1IE PA0IE
After reset 0 0 0 0 0 0 0 0
Function Input
0: disabled
1: enabled

TMPM370
8.2.3 Port B (PB0 to PB7)
The port B is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be
specified in units of bits. Besides the general-purpose input/output function, the port B performs the
debug communication function and the debug trace output function.
Reset initializes PB3, PB4, PB5, PB6 and PB7 to perform debug communication function.When PB3
functions as the TMS or SWDIO, input, output and pull-up are enabled. When PB4 functions as the TCK
or SWCLK, input, pull-down are enabled. When PB5 functions as the TDO or SWV, output is enabled.
When PB6 functions TDI, input, pull-up are enabled. When PB7 functions as TRST input, pull-up is
enabled. PB0, PB1, PB2 perform as the general-purpose ports with input, output and pull-up disabled.
(Note 1) The default setting for PB3 is function port. Input, output, and pull-up are enabled.
(Note 2) The default setting for PB4 is function port. Input, and pull-down are enabled.
(Note 3) The default setting for PB5 is function port. Output is enabled.
(Note 4) The default setting for PB6 and PB7 are function port. Input and pull-up are enabled.
(Note 5) If PB3 and PB5 are configured to alternated function port for debug function, outputs
are enabled even during Stop mode regardless of the CGSTBYCR<DRVE> bit setting.
Port B circiut types
7 6 5 4 3 2 1 0
Type T7 T7 T19 T8 T6 T18 T18 T18
Port B register
7 6 5 4 3 2 1 0
PBDATA Bit Symbol PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
After reset “0”
Port B control register

7 6 5 4 3 2 1 0
PBCR Bit Symbol PB7C PB6C PB5C PB4C PB3C PB2C PB1C PB0C
After reset 0 0 1 0 1 0 0 0
Function Output
0: disabled
1: enabled

TMPM370
Port B function register 1

7 6 5 4 3 2 1 0
PBFR1 Bit Symbol PB7F1 PB6F1 PB5F1 PB4F1 PB3F1 PB2F1 PB1F1 PB0F1
After reset 1 1 1 1 1 0 0 0
1:TRST 1:TDI 1:TDO/ 1:TCK/ 1:TMS/ 1:TRACE 1:TRACE 1:TRACE
SWV SWCLK SWDIO DATA1 DATA0 CLK
Port B open drain Control register

7 6 5 4 3 2 1 0
PBOD Bit Symbol PB7OD PB6OD PB5OD PB4OD PB3OD PB2OD PB1OD PB0OD
After reset 0 0 0 0 0 0 0 0
Function 0:CMOS
1: open drain
Port B pull-up control register

7 6 5 4 3 2 1 0
PBPUP Bit Symbol PB7UP PB6UP PB5UP PB4UP PB3UP PB2UP PB1UP PB0UP
After reset 1 1 0 0 1 0 0 0
Function Pull-up
0: disabled
1: enabled
Port B pull-down control register

7 6 5 4 3 2 1 0
PBPDN Bit Symbol PB7DN PB6DN PB5DN PB4DN PB3DN PB2DN PB1DN PB0DN
After reset 0 0 0 1 0 0 0 0
Function Pull-down
0: disabled
1: enabled
Port B input enable control register

7 6 5 4 3 2 1 0
PBIE Bit Symbol PB7IE PB6IE PB5IE PB4IE PB3IE PB2IE PB1IE PB0IE
After reset 1 1 0 1 1 0 0 0
Function Input
0: disabled
1: enabled

TMPM370
8.2.4 Port C (PC0 to PC7)
The port C is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be
specified in units of bits. Besides the general-purpose input/output function, the ports C perform the
input/output port for three-phase moter control (PMD).
Reset initializes all bits of the port C as general-purpose ports with input, output, pull-up and
pull-down disabled.
Port C circuit types
7 6 5 4 3 2 1 0
Type T3 T3 T1 T1 T1 T1 T1 T1
Port C register
7 6 5 4 3 2 1 0
PCDATA Bit Symbol PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
After reset “0”
Port C control register

7 6 5 4 3 2 1 0
PCCR Bit Symbol PC7C PC6C PC5C PC4C PC3C PC2C PC1C PC0C
After reset 0 0 0 0 0 0 0 0
Function Output
0: disabled
1: enabled
Port C function register 1

7 6 5 4 3 2 1 0
PCFR1 Bit Symbol PC7F1 PC6F1 PC5F1 PC4F1 PC3F1 PC2F1 PC1F1 PC0F1
After reset 0 0 0 0 0 0 0 0
Function 0:port 0:port 0:port 0:port 0:port 0:port 0:port 0:port
------------------ --------------------
1:OVV0 1:E M G 0 1:Z0 1:W0 1:Y0 1:V0 1:X0 1:U0

TMPM370
Port C open drain Control register

7 6 5 4 3 2 1 0
PCOD Bit Symbol PC7OD PC6OD PC5OD PC4OD PC3OD PC2OD PC1OD PC0OD
(0x4000_ 00A8) Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function 0:CMOS
1:open drain
Port C pull-up control register

7 6 5 4 3 2 1 0
PCPUP Bit Symbol PC7UP PC6UP PC5UP PC4UP PC3UP PC2UP PC1UP PC0UP
(0x4000_00AC) Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function Pull-up
0: disabled
1: enabled
Port C pull-down control register

7 6 5 4 3 2 1 0
PCPDN Bit Symbol PC7DN PC6DN PC5DN PC4DN PC3DN PC2DN PC1DN PC0DN
(0x4000_00B0 Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function Pull-down
0: disabled
1: enabled
Port C input enable control register

7 6 5 4 3 2 1 0
PCIE Bit Symbol PC7IE PC6IE PC5IE PC4IE PC3IE PC2IE PC1IE PC0IE
(0x4000_00B8) Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function Input
0:disabled
1:enabled

TMPM370
8.2.5 Port D (PD0 to PD6)
The port D is a general-purpose, 7-bit input/output port. For this port, inputs and outputs can be
specified in units of bits. Besides the general-purpose input/output function, the port D performs the
serial interface function, 16-bit timer input/output, the external interrupt input and encoder input.
Reset initializes all bits of the port D as general-purpose ports with input, output, pull-up and
pull-down disabled.
To use the external interrupt input for releasing STOP mode, select this function in the PDFR1 register
and enable input in the PDIE register. These settings enable the interrupt input even if the
mode.
Port D circuit types
7 6 5 4 3 2 1 0
Type － T3 T2 T9 T4 T3 T10 T11
Port D register
7 6 5 4 3 2 1 0
PDDATA Bit Symbol - PD6 PD5 PD4 PD3 PD2 PD1 PD0
(0x4000_00C0) Read/Write R R/W
After reset “0” is read. “0”
Port D control register

7 6 5 4 3 2 1 0
PDCR Bit Symbol － PD6C PD5C PD4C PD3C PD2C PD1C PD0C
After reset 0 0 0 0 0 0 0 0
Function “0” is read. Output
0: disabled
1: enabled
Port D function register 1

7 6 5 4 3 2 1 0
PDFR1 Bit Symbol － PD6F1 PD5F1 PD4F1 PD3F1 PD2F1 PD1F1 PD0F1
After reset 0 0 0 0 0 0 0 0
Function “0” is read. 0:PORT 0:PORT 0:PORT 0:PORT 0:PORT 0:PORT 0:PORT
1:RXD2 1:TXD2 1:SCLK2 1:INT9 1:ENCZ0 1:ENCB0 1:ENCA0

TMPM370
Port D function register 2

7 6 5 4 3 2 1 0
PDFR2 Bit Symbol －－－ PD4F2 －－ PD1F2 PD0F2
(0x4000_00CC) Read/Write R R/W R R/W R/W
After reset 0 0 0 0 0
Function “0” is read. 0:PORT “0” is read. 0:PORT 0:PORT
__________
1:CTS2 1:TB5OUT 1: TB5IN
Port D open drain control register

7 6 5 4 3 2 1 0
PDOD Bit Symbol － PD6OD PD5OD PD4OD PD3OD PD2OD PD1OD PD0OD
(0x4000_ 00E8) Read/Write R R/W
After reset 0 0 0 0 0 0 0 0
Function “0” is read. 0:CMOS
1: open drain
Port D pull-up control register

7 6 5 4 3 2 1 0
PDPUP Bit Symbol - PD6UP PD5UP PD4UP PD3UP PD2UP PD1UP PD0UP
(0x4000_00EC) Read/Write R R/W
After reset 0 0 0 0 0 0 0 0
Function “0” is read. Pull-up
0:disabled
1:enabled
Port D pull-down control register

7 6 5 4 3 2 1 0
PDPDN Bit Symbol - PD6DN PD5DN PD4DN PD3DN PD2DN PD1DN PD0DN
(0x4000_00F0) Read/Write R R/W
After reset 0 0 0 0 0 0 0 0
Function “0” is read. Pull-down
0:disabled
1:enabled
Port D input enable control register

7 6 5 4 3 2 1 0
PDIE Bit Symbol - PD6IE PD5IE PD4IE PD3IE PD2IE PD1IE PD0IE
After reset 0 0 0 0 0 0 0 0
Function “0” is read. Input
0:disabled
1:enabled

TMPM370
8.2.6 Port E (PE0 to PE7)
The port E is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be
specified in units of bits. Besides the general-purpose input/output function, the port E performs the
serial interface function, timer input/output and the external interrupt input.
Reset initializes all bits of the port E as general-purpose ports with input, output, pull-up and pull-down
disabled.
To use the external interrupt input for releasing STOP mode, select this function in the PEFR2 register
and enable input in the PEIE register. These settings enable the interrupt input even if the
mode.
Port E circuit type
7 6 5 4 3 2 1 0
Type T14 T12 T2 T12 T2 T9 T3 T2
Port E register
7 6 5 4 3 2 1 0
PEDATA Bit Symbol PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
After reset “0”
Port E control register

7 6 5 4 3 2 1 0
PECR Bit Symbol PE7C PE6C PE5C PE4C PE3C PE2C PE1C PE0C
After reset 0 0 0 0 0 0 0 0
Function Output
0: disabled
1: enabled
Port E functions register 1

7 6 5 4 3 2 1 0
PEFR1 Bit Symbol PE7F1 PE6F1 PE5F1 PE4F1 PE3F1 PE2F1 PE1F1 PE0F1
After reset 0 0 0 0 0 0 0 0
1:TB3OUT. 1:TB3IN 1:TB2OUT 1: TB2IN 1:TB4OUT 1:SCLK0 1:RXD0 1: TXD0

TMPM370
Port E functions register 2

7 6 5 4 3 2 1 0
PEFR2 Bit Symbol PE7F2 PE6F2 － PE4F2 － PE2F2 －－
(0x4000_010C) Read/Write R/W R/W R R/W R R/W R
After reset 0 0 0 0 0 0 0
Function 0:PORT 0:PORT “0” is read. 0:PORT “0” is read. 0:PORT “0” is read.
__________
1:INT7. 1:INT6 1:INT5 1:CTS0
Port E open drain control register

7 6 5 4 3 2 1 0
PEOD Bit Symbol PE7OD PE6OD PE5OD PE4OD PE3OD PE2OD PE1OD PE0OD
After reset 0 0 0 0 0 0 0 0
Function 0:CMOS
1:Open drain
Port E pull-up control register

7 6 5 4 3 2 1 0
PEPUP Bit Symbol PE7UP PE6UP PE5UP PE4UP PE3UP PE2UP PE1UP PE0UP
After reset 0 0 0 0 0 0 0 0
Function Pull-up
0:disabled
1:enabled
Port E pull-down control register

7 6 5 4 3 2 1 0
PEPDN Bit Symbol PE7DN PE6DN PE5DN PE4DN PE3DN PE2DN PE1DN PE0DN
After reset 0 0 0 0 0 0 0 0
Function Pull-down
0:disabled
1:enabled
Port E input enable control register

7 6 5 4 3 2 1 0
PEIE Bit Symbol PE7IE PE6IE PE5IE PE4IE PE3IE PE2IE PE1IE PE0IE
After reset 0 0 0 0 0 0 0 0
Function Input
0:disabled
1:enabled

TMPM370
8.2.7 Port F (PF0 to PF4)

The port F is a general-purpose, 5-bit input/output port. For this port, inputs and outputs can be
specified in units of bits. Besides the general-purpose input/output function, the port F performs the
functions of the serial interface, timer output and the operation mode setting.
While a reset signal is in “0”state, the PF0 input and pull-up are enabled. At the rising edge of the
reset signal, if PF0 is “1”, the device enters single mode and boots from the on-chip flash memory. If PF0
is “0”, the device enters single boot mode and boots from the internal boot program. For details of single
boot mode, refer to Chapter “Flash Memory Operation”.
After reset release, all bits of the port F are configured as general-purpose ports with input, output and
pull-down disabled.
Port F circuit type

7 6 5 4 3 2 1 0
Type －－－ T11 T10 T15 T2 T20
Port F register
7 6 5 4 3 2 1 0
PFDATA Bit Symbol －－－ PF4 PF3 PF2 PF1 PF0
(0x4000_0140) Read/Write R R/W
After reset “0” is read. “0”
Port F control register

7 6 5 4 3 2 1 0
PFCR Bit Symbol －－－ PF4C PF3C PF2C PF1C PF0C
0: disabled
1: enabled
Port F function register 1

7 6 5 4 3 2 1 0
PFFR1 Bit Symbol －－－ PF4F1 PF3F1 PF2F1 PF1F1 PF0F1
Function “0” is read. 0:PORT 0:PORT 0:PORT 0:PORT 0:PORT
1: ENCZ1 1: ENCB1 1: ENCA1 1:TB7OUT 1: TB7IN

7 6 5 4 3 2 1 0
PFFR2 Bit Symbol －－－ PF4F2 PF3F2 PF2F2 －－
(0x4000_014C) Read/Write R R/W R
Function “0” is read. 0:PORT 0:PORT 0:PORT “0” is read.
1:RXD3 1:TXD3 1:SCLK3

TMPM370

7 6 5 4 3 2 1 0
PFFR3 Bit Symbol －－－－－ PF2F3 －－
(0x4000_0150) Read/Write R R/W R
After reset 0 0 0
Function “0” is read. 0:PORT “0” is read.
__________
1:CTS3
Port F open drain control register

7 6 5 4 3 2 1 0
PFOD Bit Symbol －－－ PF4OD PF3OD PF2OD PF1OD PF0OD
Function “0” is read 0:CMOS
1:Open drain
Port F pull-up control register

7 6 5 4 3 2 1 0
PFPUP Bit Symbol －－－ PF4UP PF3UP PF2UP PF1UP PF0UP
(0x4000_016C) Read/Write R R/W
Function “0” is read Pull-up
0:disabled
1:enabled
Port F pull-down control register

7 6 5 4 3 2 1 0
PFPDN Bit Symbol －－－ PF4DN PF3DN PF2DN PF1DN PF0DN
Function “0” is read Pull-down
0:disabled
1:enabled
Port F input enable control register

7 6 5 4 3 2 1 0
PFIE Bit Symbol －－－ PF4IE PF3IE PF2IE PF1IE PF0IE
Function “0” is read Input
0:disabled
1:enabled

TMPM370
8.2.8 Port G (PG0 to PG7)
The port G is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be
specified in units of bits. Besides the general-purpose input/output function, the port G performs the
input/output port for three-phase moter control (PMD).
Reset initializes all bits of the port G as general-purpose ports with input, output, pull-up and
pull-down disabled.
Port G circuit type
7 6 5 4 3 2 1 0
Type T3 T3 T1 T1 T1 T1 T1 T1
Port G register
7 6 5 4 3 2 1 0
PGDATA Bit Symbol PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0
After reset “0”
Port G control register

7 6 5 4 3 2 1 0
PGCR Bit Symbol PG7C PG6C PG5C PG4C PG3C PG2C PG1C PG0C
After reset 0 0 0 0 0 0 0 0
Function Output
0: disabled
1: enabled
Port G function register 1

7 6 5 4 3 2 1 0
PGFR1 Bit Symbol PG7F1 PG6F1 PG5F1 PG4F1 PG3F1 PG2F1 PG1F1 PG0F1
After reset 0 0 0 0 0 0 0 0
------------------ -------------------
1: OVV1 1: EMG1 1: Z1 1: W1 1: Y1 1: V1 1: X1 1: U1

TMPM370
Port G open drain control register

7 6 5 4 3 2 1 0
PGOD Bit Symbol PG7OD PG6OD PG5OD PG4OD PG3OD PG2OD PG1OD PG0OD
(0x4000_01A8) Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function 0:CMOS
1:Open drain
Port G pull-up control register

7 6 5 4 3 2 1 0
PGPUP Bit Symbol PG7UP PG6UP PG5UP PG4UP PG3UP PG2UP PG1UP PG0UP
(0x4000_01AC) Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function Pull-up
0:disabled
1:enabled
Port G pull-down control register

7 6 5 4 3 2 1 0
PGPDN Bit Symbol PG7DN PG6DN PG5DN PG4DN PG3DN PG2DN PG1DN PG0DN
After reset 0 0 0 0 0 0 0 0
Function Pull-down
0:disabled
1:enabled
Port G input enable control register

7 6 5 4 3 2 1 0
PGIE Bit Symbol PG7IE PG6IE PG5IE PG4IE PG3IE PG2IE PG1IE PG0IE
After reset 0 0 0 0 0 0 0 0
Function Input
0:disabled
1:enabled

TMPM370
8.2.9 Port H (PH0 to PH7)
The port H is a general-purpose 8-bit input/output port. For this port, inputs and outputs can be
specified in units of bits. Besides the general-purpose input/output function, the port H performs the
analog input of the A/D converter and the external interrupt input.
Reset initializes all bits of the port H as general-purpose ports with input, output, pull-up and
pull-down disabled.
To use the external interrupt input for releasing STOP mode, select this function in the PHFR1 register
and enable input in the PHIE register. These settings enable the interrupt input even if the
mode.
(Note 1) In modes other than STOP mode, interrupt input is enabled regardless of the PxFR
(Note 2) Unless you use all the bits of port H as analog input pins, conversion accuracy may be
reduced. Be sure to verify that this causes no problem on your system.
Port H circuit type
7 6 5 4 3 2 1 0
Type T16 T16 T16 T16 T16 T17 T17 T17
Port H register
7 6 5 4 3 2 1 0
PHDATA Bit Symbol PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0
(0x4000_01C0) Read/Write R/W
After reset “0”
Port H control register

7 6 5 4 3 2 1 0
PHCR Bit Symbol PH7C PH6C PH5C PH4C PH3C PH2C PH1C PH0C
(0x4000_01C4) Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function Output
0: disabled
1: enabled
Port H function register 1

7 6 5 4 3 2 1 0
PHFR1 Bit Symbol - - - - - PH2F1 PH1F1 PH0F1
After reset 0 0 0 0 0 0 0 0
Function “0” is read 0:PORT 0:PORT 0:PORT
1:INT2 1:INT1 1:INT0

TMPM370
Port H open drain control register

7 6 5 4 3 2 1 0
PHOD Bit Symbol PH7OD PH6OD PH5OD PH4OD PH3OD PH2OD PH1OD PH0OD
(0x4000_ 01E8) Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function 0:CMOS
1:open drain
Port H pull-up control register

7 6 5 4 3 2 1 0
PHPUP Bit Symbol PH7UP PH6UP PH5UP PH4UP PH3UP PH2UP PH1UP PH0UP
(0x4000_01EC) Read/Write R/W
After reset 0 0 0 0 0 0 0 1
Function Pull-up
0:disabled
1:enabled
Port H pull-down control register

7 6 5 4 3 2 1 0
PHPDN Bit Symbol PH7DN PH6DN PH5DN PH4DN PH3DN PH2DN PH1DN PH0DN
(0x4000_01F0) Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function Pull-down
0:disabled
1:enabled
Port H input enable control register

7 6 5 4 3 2 1 0
PHIE Bit Symbol PH7IE PH6IE PH5IE PH4IE PH3IE PH2IE PH1IE PH0IE
(0x4000_01F8) Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function Input
0:disabled
1:enabled

TMPM370
8.2.10 Port I (PI0 to PI3)
The port I is a general-purpose, 4-bit input/output port. For this port, inputs and outputs can be
specified in units of bits. Besides the general-purpose input/output function, the port I performs the
analog input of the A/D converter.
Reset initializes all bits of the port I as general-purpose ports with input, output, pull-up and pull-down
disabled.
(Note) Unless you use all the bits of port I as analog input pins, conversion accuracy may be
Port I circuit type
7 6 5 4 3 2 1 0
Type －－－－ T16 T16 T16 T16
Port I register
7 6 5 4 3 2 1 0
PIDATA Bit Symbol －－－－ PI3 PI2 PI1 PI0
After reset “0” is read “0”
Port I control register

7 6 5 4 3 2 1 0
PICR Bit Symbol －－－－ PI3C PI2C PI1C PI0C
After reset 0 0 0 0 0 0 0 0
Function “0” is read Output
0: disabled
1: enabled
Port I open drain control register

7 6 5 4 3 2 1 0
PIOD Bit Symbol －－－－ PI3OD PI2OD PI1OD PI0OD
(0x4000_ 0228) Read/Write R R/W
After reset 0 0 0 0 0 0 0 0
1:open drain
Port I pull-up control register

7 6 5 4 3 2 1 0
PIPUP Bit Symbol －－－－ PI3UP PI2UP PI1UP PI0UP
After reset 0 0 0 0 0 0 0 0
0: disabled
1: enabled

TMPM370
Port I pull-down control register

7 6 5 4 3 2 1 0
PIPDN Bit Symbol －－－－ PI3DN PI2DN PI1DN PI0DN
After reset 0 0 0 0 0 0 0 0
0:disabled
1:enabled
Port I input enable control register

7 6 5 4 3 2 1 0
PIIE Bit Symbol －－－－ PI3IE PI2IE PI1IE PI0IE
After reset 0 0 0 0 0 0 0 0
0:disabled
1:enabled

TMPM370
8.2.11 Port J (PJ0 to PJ7)
The port J is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be
specified in units of bits. Besides the general-purpose input/output function, the port J performs the
analog input of the A/D converter and external interrupt input.
Reset initializes all bits of the port J as general-purpose ports with input, output, pull-up and pull-down
disabled.
To use the external interrupt input for releasing STOP mode, select this function in the PJFR1 register
and enable input in the PJIE register. These settings enable the interrupt input even if the
mode.
(Note 2) Unless you use all the bits of port J as analog input pins, conversion accuracy may be
Port J circuit type
7 6 5 4 3 2 1 0
Type T17 T17 T16 T16 T16 T16 T16 T16
Port J register
7 6 5 4 3 2 1 0
PJDATA Bit Symbol PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0
After reset “0”
Port J control register

7 6 5 4 3 2 1 0
PJCR Bit Symbol PJ7C PJ6C PJ5C PJ4C PJ3C PJ2C PJ1C PJ0C
After reset 0 0 0 0 0 0 0 0
Function Output
0: disabled
1: enabled
Port J function register 1

7 6 5 4 3 2 1 0
PJFR1 Bit Symbol PJ7F1 PJ6F1 －－－－－－
(0x4000_0248) Read/Write R/W R
After reset 0 0 0 0 0 0 0 0
Function 0:PORT 0:PORT “0” is read
1:INTD 1:INTC

TMPM370
Port J open drain control register

7 6 5 4 3 2 1 0
PJOD Bit Symbol PJ7OD PJ6OD PJ5OD PJ4OD PJ3OD PJ2OD PJ1OD PJ0OD
After reset 0 0 0 0 0 0 0 0
Function 0:CMOS
1:open drain
Port J pull-up control register

7 6 5 4 3 2 1 0
PJPUP Bit Symbol PJ7UP PJ6UP PJ5UP PJ4UP PJ3UP PJ2UP PJ1UP PJ0UP
After reset 0 0 0 0 0 0 0 0
After reset Pull-up
0:disabled
1:enabled
Port J pull-down control register

7 6 5 4 3 2 1 0
PJPDN Bit Symbol PJ7DN PJ6DN PJ5DN PJ4DN PJ3DN PJ2DN PJ1DN PJ0DN
After reset 0 0 0 0 0 0 0 0
After reset Pull-down
0:disabled
1:enabled
Port J input enable control register

7 6 5 4 3 2 1 0
PJIE Bit Symbol PJ7IE PJ6IE PJ5IE PJ4IE PJ3IE PJ2IE PJ1IE PJ0IE
After reset 0 0 0 0 0 0 0 0
Function Input
0:disabled
1:enabled

TMPM370
8.2.12 Port K (PK0 to PK1)
The port K is a general-purpose, 2-bit input/output port. For this port, inputs and outputs can be
specified in units of bits. Besides the general-purpose input/output function, the port K performs the
functions as the analog input of the A/D converter and the external interrupt input.
Reset initializes all bits of the port K as general-purpose ports with input, output, pull-up and pull-down
disabled.
To use the external interrupt input for releasing STOP mode, select this function in the PKFR1 register
and enable input in the PKIE register. These settings enable the interrupt input even if the
mode.
(Note 2) Unless you use all the bits of port K as analog input pins, conversion accuracy may be
Port K circuit type
7 6 5 4 3 2 1 0
Type －－－－－－ T17 T17
Port K register
7 6 5 4 3 2 1 0
PKDATA Bit Symbol －－－－－－ PK1 PK0
Port K control register

7 6 5 4 3 2 1 0
PKCR Bit Symbol －－－－－－ PK1C PK0C
After reset 0 0 0
0: disabled
1: enabled
Port K function register 1

7 6 5 4 3 2 1 0
PKFR1 Bit Symbol －－－－－－ PK1F1 PK0F1
After reset 0 0 0
Function “0” is read 0:PORT 0:PORT
1: INTF 1: INTE

TMPM370
Port K open drain control register

7 6 5 4 3 2 1 0
PKOD Bit Symbol －－－－－－ PK1OD PK0OD
(0x4000_ 02A8) Read/Write R R/W
After reset 0 0 0 0 0 0 0 0
1:open drain
Port K pull-up control register

7 6 5 4 3 2 1 0
PKPUP Bit Symbol －－－－－－ PK1UP PK0UP
(0x4000_02AC) Read/Write R R/W
After reset 0 0 0 0 0 0 0 0
0:disabled
1:enabled
Port K pull-down control register

7 6 5 4 3 2 1 0
PKPDN Bit Symbol －－－－－－ PK1DN PK0DN
(0x4000_02B0) Read/Write R R/W
After reset 0 0 0 0 0 0 0 0
0:disabled
1:enabled
Port K input enable control register

7 6 5 4 3 2 1 0
PKIE Bit Symbol －－－－－－ PK1IE PK0IE
(0x4000_02B8) Read/Write R R/W
After reset 0 0 0
0:disabled
1:enabled

TMPM370
8.2.13 Port L(PL0 to PL1)
The port L is a general-purpose, 2-bit input port. For this port, inputs can be specified in units of bits.
Besides the general-purpose input function, the port L performs the functions as the external interrupt
input.
Reset initializes all bits of the port L as general-purpose input ports with input disabled.
To use the external interrupt input for releasing STOP mode, select this function in the PLFR1 register
and enable input in the PLIE register. These settings enable the interrupt input even if the
mode.
(Note1) In modes other than STOP mode, interrupt input is enabled regardless of the PxFR
(Note2)
When the power supply switch on, please keep ‘L’ level to port_L, constant time.
(include in reset time) The details please watch ‘Notice for the power supply’ of
‘Electrical Characteristics’.
Port L circuit type
7 6 5 4 3 2 1 0
Type －－－－－－ T5 T5
Port L register
7 6 5 4 3 2 1 0
PL Bit Symbol －－－－－－ PL1 PL0
(0x4000_02C0) Read/Write R R
Port L function register 1

7 6 5 4 3 2 1 0
PLFR1 Bit Symbol －－－－－－ PL1F1 PL0F1
After reset 0 0 0
Function “0” is read 0:PORT 0:PORT
1: INTA 1: INTB
Port L input enable control register

7 6 5 4 3 2 1 0
PLIE Bit Symbol －－－－－－ PL1IE PL0IE
After reset 0 0 0
0:disabled
1:enabled

TMPM370
8.3 Block Diagrams of Ports
8.3.1 Port Types
The ports are classified into 21 types shown below. Please refer to the following pages for the block diagrams
of each port type.
Table 8.2 Port type

Type Port Function1 Function2 Function3 Analog Pull-up Pull-down OD Note
Function output triggered
T1 i/o o - - - R R ○
by enable signal
T2 i/o o - - - R R ○
T3 i/o i - - - R R ○
T4 i/o i(int) - - - R R ○
T5 i i(int) - - - - - -

T6 i/o i/o - - - NoR - -
by enable signal
T7 i/o i - - - NoR - -
T8 i/o i - - - - NoR -
T9 i/o i/o i - - R R ○
T10 i/o i o - - R R ○
T11 i/o i i - - R R ○
T12 i/o i i(int) - - R R ○
T13 i/o o o - - R R ○
T14 i/o o i/o - - R R ○
T15 i/o i i/o i - R R ○
T16 i/o - - - ○ R R ○
T17 i/o i(int) - - ○ R R ○
T18 i/o o - - - R - -

T19 i/o o - - - NoR - -
by enable signal
BOOT input enabled
T20 i/o i - - - NoR NoR ○
during reset
R : Forced disable during reset.
NoR : Unaffected by reset.

TMPM370
8.3.2 Type T1
Type T1 is a general-purpose input/output port with pull-up and pull-down. It is used to output function
data as well.
The function output is controlled by an enable signal. If enabled, the function data is output.
Drive時のドライブ禁止
STOP disable in RESET Programmable
プログラマブル
Stop mode pull-up and
プルアップ/
プルダウン
pull-down
PxUP
PxDN
PxCR
0
Internal Data Bus
内部データバス
機能出力許可
Function output control
1
PxFR1
機能出力output1
Function 1 I/O port
1
ポート
PxDATA 入出力
0
PxOD
PxIE
1
ポートリード
Port read
Fig 8.1 Type T1

TMPM370
8.3.3 Type T2
data as well.
Drive
STOP disable in
時のドライブ禁止 RESET Programmable
プルアップ/
pull-down
プルダウン
PxUP
PxDN
PxCR
Internal Data Bus
PxFR1
Function
機能出力 output1
1 I/O port
1
ポート
PxDATA 入出力
0
PxOD
PxIE
1
ポートリード
Port read
Fig 8.2 Type T2

TMPM370
8.3.4 Type T3
Type T3 is a general-purpose input/output port with pull-up and pull-down. It is used to input function
data as well.
Drive
STOP disable in
プルアップ/
pull-down
プルダウン
PxUP
PxDN
PxCR
Internal Data Bus
PxFR1
I/O port
ポート
PxDATA 入出力
PxOD
PxIE
1
Port read
ポートリード
機能入力
Function input11
Fig 8.3 Type T3

TMPM370
8.3.5 Type T4
data and interrupt input as well.
STOP 時のドライブ禁止
Drive disable in RESET Programmable
プルアップ/
プルダウン
pull-down
PxUP
PxDN
PxCR
Internal Data Bus
PxFR1
I/O port
ポート
PxDATA 入出力
PxOD
PxIE
1
ポートリード
Port read
割り込み入力
Interrupt
input
Fig 8.4 Type T4

TMPM370
8.3.6 Type T5
Type T5 is a general-purpose input/output port. It is used to interrupt input as well.
Drive
STOP disable in
時のドライブ禁止
Stop mode
PxFR1
Internal Data Bus
PxIE
0
I/O port
ポート
1 入出力
Port read
ポートリード
Interrupt
割り込み入力
input
Fig 8.5 Type T5

TMPM370
8.3.7 Type T6
Type T6 is a general-purpose port with pull-up. It is used to output function data and input interrupt as
well.
Drive
STOP disable in
Stop mode Programmable
PxUP pull-up
プルアップ
PxCR
0
機能出力許可
1
Internal Data Bus
PxFR1
機能出力
Function 1
output1 I/O port
1
ポート
PxDATA 入出力
0
PxIE
1
Port read
ポートリード
機能入力
Function input11
Fig 8.6 Type T6

TMPM370
8.3.8 Type T7
Type T7 is a general-purpose input/output port with pull-up. It is used to input function data as well.
Drive
STOP disable in
時のドライブ禁止 RESET
Stop mode プログラマブル
Programmable
PxUP プルアップ
pull-up
PxCR
Internal Data Bus
PxFR1
I/O port
ポート
PxDATA 入出力
PxIE
1
Port read
ポートリード
機能入力
Function input11
Fig 8.7 Type T7

TMPM370
8.3.9 Type T8
Type T8 is a general-purpose input/output port with pull-down. It is used to input function data as well.
Drive
STOP disable in
Programmable
PxDN プルダウン
pull-down
PxCR
Internal Data Bus
PxFR1
I/O port
ポート
PxDATA 入出力
PxIE
1
Port read
ポートリード
機能入力
Function input1
1
Fig 8.8 Type T8

TMPM370
8.3.10 Type T9
data and two input function data as well.
Drive
STOP disable in
pull-up and
プルアップ/
pull-down
プルダウン
PxUP
PxDN
PxCR
Internal Data Bus
PxFR1
PxFR2
Function output1 I/O port
機能出力 1 1
ポート
PxDATA 入出力
0
PxOD
PxIE
1
Port read
ポートリード
Function input11
機能入力
機能入力
Function input22
Fig 8.9 Type T9

TMPM370
8.3.11 Type T10

Type T10 is a general-purpose input/output port with pull-up and pull-down. It is used to output
function data and input function data as well.
Drive
STOP disable in
プルアップ/
pull-down
プルダウン
PxUP
PxDN
PxCR
Internal Data Bus
PxFR1
PxFR2
I/O port
機能出力
Function output1
1 1
ポート
PxDATA 入出力
0
PxOD
PxIE
1
Port read
ポートリード
機能入力
Function input11
Fig 8.10 Type T10

TMPM370
8.3.12 Type T11
Type T11 is a general-purpose input/output port with pull-up and pull-down. It is used to two input
function data as well.
Drive
STOP disable in
プルアップ/
プルダウン
pull-down
PxUP
PxDN
PxCR
Internal Data Bus
PxFR1
PxFR2
I/O port
ポート
PxDATA 入出力
PxOD
PxIE
1
Port read
ポートリード
機能入力
Function input11
機能入力
Function 2
input2
Fig 8.11 Type T11

TMPM370
8.3.13 Type T12
data and interrupt input as well.
Drive
STOP disable in
pull-up and
プルアップ/
pull-down
プルダウン
PxUP
PxDN
PxCR
Internal Data Bus
PxFR1
PxFR2
I/O port
ポート
PxDATA 入出力
PxOD
PxIE
1
Port read
ポートリード
Interrupt
割り込み入力
input
Function input1
機能入力 1
Fig 8.12 Type T12

TMPM370
8.3.14 Type T13
Type T13 is a general-purpose input/output port with pull-up and pull-down. It is used to two output
function data as well.
Drive
STOP disable in
プルアップ/
pull-down
プルダウン
PxUP
PxDN
PxCR
Internal Data Bus
PxFR1
PxFR2
機能出力
Function input
22 I/O port
1
機能出力 1 1
Function input 1 ポート
入出力
PxDATA 0
0
PxOD
PxIE
1
Port read
ポートリード
Fig 8.13 Type T13

TMPM370
8.3.15 Type T14
function data and interrupt input as well.
プルアップ/
pull-down
プルダウン
PxUP
PxDN
PxCR
Internal Data Bus
PxFR1
PxFR2
Function
機能出力 output
1 1 I/O port
1
ポート
PxDATA 入出力
0
PxOD
PxIE
1
Port read
ポートリード
Interrupt
割り込み入力 input
Fig 8.14 Type T14

TMPM370
8.3.16 Type T15
function data and three input function data as well.
プルアップ/
pull-down
プルダウン
PxUP
PxDN
PxCR
PxFR1
Internal Data Bus
PxFR2
PxFR3
Function output1 I/O port
機能出力 2 1
ポート
PxDATA 入出力
0
PxOD
PxIE
1
Port read
ポートリード
Function input11
機能入力
機能入力
Function input22
機能入力
Function input33
Fig 8.15 Type T15

TMPM370
8.3.17 Type T16
Type T16 is a general-purpose input/output port with pull-up and pull-down. It is used to input analog
signals for A/D converter as well.
Drive disable in RESET
Programmable
Stop mode プルアップ/
pull-up and
プルダウン
pull-down
PxUP
PxDN
PxCR
Internal Data Bus
I/O port
ポート
PxDATA 入出力
PxOD
PxIE
1
Port read
ポートリード
アナログ入力
Analog input
Fig 8.16 Type T16

TMPM370
8.3.18 Type T17
Type T17 is a general-purpose input/output port with pull-up and pull-down. It is used to input analog
signals for A/D converter and interrupt input as well.
Drive
STOP disable in
プルアップ/
pull-down
プルダウン
PxUP
PxDN
PxCR
Internal Data Bus
PxFR1
I/O port
ポート
PxDATA 入出力
PxOD
PxIE
1
Port read
ポートリード
Interrupt
input
割り込み入力
Analog
アナログ入力
input
Fig 8.17 Type T17

TMPM370
8.3.19 Type T18
Type T18 is a general-purpose input/output port with pull-up. It is used to output function data as well.
Drive
STOP disable in
プルアップ
pull-up
PxUP
PxCR
Internal Data Bus
PxFR1
機能出力
Function 1
output1 I/O port
1
ポート
PxDATA 入出力
0
PxIE
1
Port read
ポートリード
Fig 8.18 Type T18

TMPM370
8.3.20 Type T19
Type T19 is a general-purpose port with pull-up. It is used to output function data as well.
Drive
STOP disable in
PxUP pull-up
プルアップ
PxCR
0
機能出力許可
Internal Data Bus
1
PxFR1
機能出力
Function output1
1 I/O port
1
ポート
PxDATA 入出力
0
PxIE
1
Port read
ポートリード
Fig 8.19 Type T19

TMPM370
8.3.21 Type T20
data as well.
During reset, it functions as an input port for a BOOT signal.
Drive
STOP disable in
pull-up and
プルアップ/
PxUP プルダウン
pull-down
PxDN
PxCR
Internal Data Bus
PxFR1
I/O port
ポート
PxDATA 入出力
PxIE
1
Port read
ポートリード
機能入力
Function input11
BOOT
Fig 8.20 Type T20

TMPM370
9. 16-bit Timer/Event Counters (TMRBs)
9.1 Outline
TMPM370 have the eight channels multi-functional 16-bit timer/event counter. (TMRB0 through
TMRB7) TMRBs operate in the following four operation modes:
• 16-bit interval timer mode

• 16-bit event counter mode
• 16-bit programmable square-wave output mode (PPG)
• External trigger programmable square-wave output mode (PPG)
The use of the capture function allows TMRBs to perform the following two measurements
Pulse width measurement
One-shot pulse generation from an external trigger pulse
TMPM370 9-1 16-bit Timer/Event Counters

TMPM370
9.2 Specification differences among channels
Channels (TMRB0 through TMRB7) operate independently and the functions are same except the
differences as shown in Table 9-1 and Table 9-2. Therefore, the operational descriptions here are
explained only for TMRB0.
Table 9-1 Differences in the Specifications of TMRB Modules (1)
External pins
Specification
External clock/
Channel Timer flip-flop output pin
capture trigger input pin
TMRB0 TB0IN (shared with PA0) TB0OUT (shared with PA1)
TMRB2 TB2IN (shared with PE4) TB2OUT (shared with PE5)
TMRB3 TB3IN (shared with PE6) TB3OUT (shared with PE7)
TMRB4 TB4IN (shared with PA7) TB4OUT (shared with PE3)
TMRB5 TB5IN (shared with PD0) TB5OUT (shared with PD1)
TMRB7 TB7IN (shared with PF0) TB7OUT (shared with PF1)
Table 9-2 Differences in the Specifications of TMRB Modules (2)

Specification Interrupt
Channel Capture interrupt TMRB interrupt
INTCAP00 INTTB00
TMRB0
INTCAP01 INTTB01
INTCAP10 INTTB10
TMRB1
INTCAP11 INTTB11
INTCAP20 INTTB20
TMRB2
INTCAP21 INTTB21
INTCAP30 INTTB30
TMRB3
INTCAP31 INTTB31
INTCAP40 INTTB40
TMRB4
INTCAP41 INTTB41
INTCAP50 INTTB50
TMRB5
INTCAP51 INTTB51
INTCAP60 INTTB60
TMRB6
INTCAP61 INTTB61
INTCAP70 INTTB70
TMRB7
INTCAP71 INTTB71

TMPM370
9.3 Configuration
Each channel consists of a 16-bit up-counter, two 16-bit timer registers (one of which is
double-buffered), two 16-bit capture registers, two comparators, a capture input control, a timer
flip-flop and its associated control circuit.
Timer operation modes and the timer flip-flop are controlled by registers.
Fig. 9-1 TMRB0 Block Diagram (the same applies to channels 1 through7)

TMPM370
9.4 Registers
9.4.1 TMRB registers

Table 9-3 shows the register names and addresses of each channel.
Table 9-3 TMRB registers

Channel
TMRB0 TMRB1 TMRB2 TMRB3
Specification
Timer enable register TB0EN 0x4001_0000 TB1EN 0x4001_0040 TB2EN 0x4001_0080 TB3EN 0x4001_00C0
Timer RUN register TB0RUN 0x4001_0004 TB1RUN 0x4001_0044 TB2RUN 0x4001_0084 TB3RUN 0x4001_00C4
Timer control register TB0CR 0x4001_0008 TB1CR 0x4001_0048 TB2CR 0x4001_0088 TB3CR 0x4001_00C8
Timer mode register TB0MOD 0x4001_000C TB1MOD 0x4001_004C TB2MOD 0x4001_008C TB3MOD 0x4001_00CC
Timer flip-flop control
TB0FFCR 0x4001_0010 TB1FFCR 0x4001_0050 TB2FFCR 0x4001_0090 TB3FFCR 0x4001_00D0
register
Register Timer status register TB0ST 0x4001_0014 TB1ST 0x4001_0054 TB2ST 0x4001_0094 TB3ST 0x4001_00D4
names
(addresses) Interrupt mask register TB0IM 0x4001_0018 TB1IM 0x4001_0058 TB2IM 0x4001_0098 TB3IM 0x4001_00D8
Timer up counter
TB0UC 0x4001_001C TB1UC 0x4001_005C TB2UC 0x4001_009C TB3UC 0x4001_00DC
register
TB0RG0 0x4001_0020 TB1RG0 0x4001_0060 TB2RG0 0x4001_00A0 TB3RG0 0x4001_00E0
Timer register
TB0CP0 0x4001_0028 TB1CP0 0x4001_0068 TB2CP0 0x4001_00A8 TB3CP0 0x4001_00E8
Capture register
TB0CP1 0x4001_002C TB1CP1 0x4001_006C TB2CP1 0x4001_00AC TB3CP1 0x4001_00EC
Channel
TMRB4 TMRB5 TMRB6 TMRB7
Specification
Timer enable register TB4EN 0x4001_0100 TB5EN 0x4001_0140 TB6EN 0x4001_0180 TB7EN 0x4001_01C0
Timer RUN register TB4RUN 0x4001_0104 TB5RUN 0x4001_0144 TB6RUN 0x4001_0184 TB7RUN 0x4001_01C4
Timer control register TB4CR 0x4001_0108 TB5CR 0x4001_0148 TB6CR 0x4001_0188 TB7CR 0x4001_01C8
Timer mode register TB4MOD 0x4001_010C TB5MOD 0x4001_014C TB6MOD 0x4001_018C TB7MOD 0x4001_01CC
Timer flip-flop control
TB4FFCR 0x4001_0110 TB5FFCR 0x4001_0150 TB6FFCR 0x4001_0190 TB7FFCR 0x4001_01D0
register
Register Timer status register TB4ST 0x4001_0114 TB5ST 0x4001_0154 TB6ST 0x4001_0194 TB7ST 0x4001_01D4
names
(addresses) Interrupt mask register TB4IM 0x4001_0118 TB5IM 0x4001_0158 TB6IM 0x4001_0198 TB7IM 0x4001_01D8
Timer up counter
TB4UC 0x4001_011C TB5UC 0x4001_015C TB6UC 0x4001_019C TB7UC 0x4001_01DC
register
Timer register
TB4CP0 0x4001_0128 TB5CP0 0x4001_0168 TB6CP0 0x4001_01A8 TB7CP0 0x4001_01E8
Capture register
TB4CP1 0x4001_012C TB5CP1 0x4001_016C TB6CP1 0x4001_01AC TB7CP1 0x4001_01EC

TMPM370
9.4.1.1 TMRBn enable register (channels 0 through 7)
TMRBn enable register (n=0 to 7)

31 30 29 28 27 26 25 24
TBnEN bit Symbol
(0x4001_0xx0) Read/Write R R R R R R R R
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
bit Symbol
Read/Write R R R R R R R R
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
bit Symbol
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
bit Symbol TBnEN
Read/Write R/W R
After reset 0 0
TMRBn “0” is read.
operation
Function
0: Disabled
1: Enabled
＜TBnEN＞: Specifies the TMRBn operation. When the operation is disabled, no clock is supplied to the
other registers in the TMRBn module. This can reduce power consumption. (This disables
reading from and writing to the other registers.)
To use the TMRBn, enable the TMRBn operation (set to “1”) before programming each register
in the TMRBn module.
After the TMRBn operation is executed and then disabled, the settings will be maintained in
each registers.

TMPM370
9.4.1.2 TMRB RUN register (channels 0 through 7)
TMRBn RUN register (n=0 to 7)

31 30 29 28 27 26 25 24
TBnRUN bit Symbol
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
bit Symbol
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
bit Symbol
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
bit Symbol TBnPRUN TBnRUN
After reset 0 0 0 0
“0” is read. Timer Run/Stop Control
0: Stop & clear
Function
1: Count
* The bit 1 can be read as “0.”
＜TBnRUN＞ :Controls the TMRBn count operation.

0: Stop counting and the counter is cleared to “0”.
1: Start counter
(Note) To start couting by the external trigger, the TBnRUN bit must be set to 1.
＜TBnPRUN＞:Controls the TMRBn prescaler operation.

0: Stop prescaler operation and the prescaler is cleared to “0”.
1: Start prescaler operation.

TMPM370
9.4.1.3 TMRB control register (channels 0 through 7)
TMRBn control register (n=0 to 7)

31 30 29 28 27 26 25 24
TBnCR bit Symbol
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
bit Symbol
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
bit Symbol
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
bit Symbol TBnWBF I2TBn TRGSELn CSSELn
Read/Write R/W R/W R/W R R/W R R/W R/W
After reset 0 0 0 0 0 0 0 0
Double Write “0”. Write “0”. “0” is read. IDLE “0” is read. External Counter
Buffer 0:Stop Trigger Start select
0: Disabled 1:Operation select 0: Software
Function 1: Enabled 0: Rising start
edge 1: External
1: Falling trigger
edge
<CSSELn>: Selects how the timer starts counting.
0: Select software for timer count start.

1: Select external trigger for timer count start.
<TRGSELn>: Selects the active edge of the external trigger signal.
0: Select rising edge of external trigger.

1: Select falling edge of external trigger.
＜I2TBn＞:Controls the clock keep/ stop operation during the IDLE mode.
0: Stop the clock.

1: Keep clock operation during IDLE mode.
＜TBWBF＞:Controls the enabling/disabling of double buffering.
0: Disable Double Buffer.

1: Enable Double Buffer.
(Note1) TBnCR resister must not be changed during Timer operation TBnRUN<TERUN>=1”.
(Note2) When the external trigger start is used (<CSSELn>=”1”), select <CSSELn> and
<TRGSELn> before the setting of <TBnRUN>=<TBnPRUN>=”1”.

TMPM370
9.4.1.4 TMRB mode register (channels 0 thorough 7)
TMRBn mode register(n=0 to 7)

31 30 29 28 27 26 25 24
TBnMOD bit Symbol
(0x4001_0xxC) Read/Write R R R R R R R R
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
bit Symbol
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
bit Symbol
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
bit Symbol TBnRSWR TBnCP0 TBnCPM1 TBnCPM0 TBnCLE TBnCLK1 TBnCLK0
Read/Write R R/W W R/W
After reset 0 0 1 0 0 0 0 0
“0” Writes to Software Capture timing Up-counter Source clock select
timer capture clear control
is read.
registers control 00: Disable 00: TBnIN pin input
0 and 1 01: TBnIN ↑ 0: 01: φT1
(when 10: TBnIN ↑ TBnIN ↓
0: Software Clear/disable 10: φT4
double
capture 11: Disable 1: 11: φT16
buffering is
enabled) clear/enable
1: Don't
Function 0: Can be care
written
separately
1: Must be
written
simultaneo
usly
＜TBnCLK1:0＞:Selects the TMRBn timer count clock.

00: select TBnIN input pin
01: select φT1 (1/2φT0)
＜TBnCLE＞:Clears and controls the TMRBn up-counter.

0: Disables clearing of the up-counter.
1: Clears up-counter if there is a match with timer register 1 (TBnRG1).
＜TBnCPM1:0＞:Specifies TMRBn capture timing.

00: Capture disable
01: Takes count values into capture register 0 (TBnCP0) upon rising of TBnIN pin input.
10: Takes count values into capture register 0 (TBnCP0) upon rising of TBnIN pin input.
Takes count values into capture register 1 (TBnCP1) upon falling of TBnIN pin input.
11: .Capture disable
＜TBnCP0＞:Captures count values by software and takes them into capture register 0 (TBnCP0).
00: software capture
01: Don’t care

TMPM370
<TBnRSWR>: Controls the timing to write to timer registers 0 and 1 when double buffering is enabled.
0: The data transfer to the timer register 0 and 1 is done by corresponding to the up-counter
(UC) regardless of the rewriting of the buffer register 0 and 1.
1: To transfer the buffer registers data to the timer registers, the writing of the timer register 0
and 1 together are needed.
(Note 1) The value read from bit 5 of TBnMOD is “1”.

(Note 2) TBnMOD register must not be changed during Timer operation TBnRUN<TBRUN>=”1”.
(Note 3) When TBnPSWR is set to “1”, do not write data to the buffer registers two or more times
before completion of data transfer to the timer registers.

TMPM370
9.4.1.5 TMRB flip-flop control register (channels 0 through 7)
TMRBn flip-flop control register (n=0 to 7)

31 30 29 28 27 26 25 24
TBnFFCR bit Symbol
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
bit Symbol
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
bit Symbol
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
bit Symbol TBnC1T1 TBnC0T1 TBnE1T1 TBnE0T1 TBnFF0C1 TBnFF0C0
After reset 1 1 0 0 0 0 1 1
“11” is read. TBnFF0 reverse trigger TBnFF0 control
00: Invert
0: Disable trigger
01: Set
1: Enable trigger 10: Clear
Function When the When the When the When the 11: Don't care
up-counter up-counter up-counter up-counter * This is always read
value is value is matches matches as “11.”
taken into taken into TBnRG1 TBnRG0
TBnCP1 TBnCP0
＜TBnFF0C1:0＞:Controls the timer flip-flop.

00 : Reverses the value of TBnFF0
01 : Sets TBnFF0 to “1”.
10 : Clears TBnFF0 to “0”.
11 :Don’t care
＜TBnE0T1＞:Reverses the timer flip-flop when the up-counter matches the timer register 0 (TBnRG0).
0: TBnFF0 not reverse
1: TBnFF0 reverse
＜TBnE1T1＞:Reverses the timer flip-flop when the up-counter matches the timer register 1 (TBnRG1).
1: TBnFF0 reverse
＜TBnC0T1＞:Reverses the timer flip-flop when the up-counter value is taken into the capture register 0
(TBnCP0).
1: TBnFF0 reverse
＜TBnC1T1＞:Reverses the timer flip-flop when the up-counter value is taken into the capture register 1
(TBnCP1).
1: TBnFF0 reverse
(Note) TBnFFCR register must not be changed during Timer operation TBnRUN<TBRUN>=”1”.

TMPM370
9.4.1.6 TMRB status register (channels 0 through 7)
TMRBn status register (n=0 to 7)

31 30 29 28 27 26 25 24
TBnST bit Symbol
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
bit Symbol
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
bit Symbol
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
bit Symbol INTTBOFn INTTBn1 INTTBn0
Read/Write R R
After reset 0 0 0 0
“0” is read. 0: Interrupt 0: Interrupt 0: Interrupt
not not not
Function generated generated generated
1: Interrupt 1: Interrupt 1: Interrupt
generated generated generated
＜INTTBn0＞:Interrupt generated status for a match with timer register 0 (TBnRG0)

0: No interrupt generated
1: Interrupt generated
＜INTTBn1＞:Interrupt generated status for a match with timer register 1 (TBnRG1)
＜INTTBOFn＞:Interrupt generated status for an up-counter overflow occurs
(Note) If any interrupt is generated, the flag that corresponds to the interrupt is set to TBnST and
the generation of interrupt enabled by TBnIM is notified to the CPU.
The flag is cleared by reading the TBnST register.

TMPM370
9.4.1.7 TMRB interrupt mask register (channels 0 through 7)
TMRBn interrupt mask register (n=0 to 7)

31 30 29 28 27 26 25 24
TBnIM bit Symbol
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
bit Symbol
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
bit Symbol
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
bit Symbol TBIMOFn TBIMn1 TBIMn0
Read/Write R R/W
After reset 0 0 0 0
“0” is read 0: No Interrupt 0: No Interrupt 0: No Interrupt
mask mask mask
Function
1: Interrupt 1: Interrupt 1: Interrupt
is masked is masked is masked
＜TBIMn0＞: Interrupt mask for a match with timer register 0 (TBnRG0)

0: No interrupt mask
1: Interrupt is masked
＜TBIMn1＞:Interrupt mask for a match with timer register 1 (TBnRG1).
＜TBIMOFn＞:Interrupt mask for an up counter overflow.
(Note) Even in case TBnIM set interrupt Mask, TBnST status register have an interrupt requested status.

TMPM370
9.4.1.8 TMRB read capture register (channels 0 through 7)
TBnUC0 read capture register (n=0 to 7)

31 30 29 28 27 26 25 24
TBnUC0 bit Symbol
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
bit Symbol
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
bit Symbol UCn15 UCn14 UCn13 UCn12 UCn11 UCn10 UCn9 UCn8
Read/Write R
After reset 0
Function Data obtained by read capture: 15-8 bit data
7 6 5 4 3 2 1 0
bit Symbol UCn7 UCn6 UCn5 UCn4 UCn3 UCn2 UCn1 UCn0
Read/Write R
After reset 0
Function Data obtained by read capture: 7-0 bit
<UCn15-0>：Captured Up-counter value.

TMPM370
9.4.1.9 TMRB timer register (channels 0 through 7)
TBnRG0 timer register (n=0 to 7)

31 30 29 28 27 26 25 24
TBnRG0 bit Symbol
(0x4001_0xx0)
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
bit Symbol
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
bit Symbol TBnRG015 TBnRG014 TBnRG013 TBnRG012 TBnRG011 TBnRG010 TBnRG09 TBnRG08
Read/Write R/W
After reset 0
Function Timer count value: 15-8 bit data
7 6 5 4 3 2 1 0
Read/Write R/W
After reset 0
<TBnRG015-000>：16bit Compare value0 with Up- counter
TBnRG1 timer register (n=0~7)

31 30 29 28 27 26 25 24
TBnRG1
bit Symbol
(0x4001_0xx4)
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
bit Symbol
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Read/Write R/W
After reset 0
7 6 5 4 3 2 1 0
Read/Write R/W
After reset 0
<TBnRG115-100>：16bit Compare value1 with Up- counter

TMPM370
9.4.1.10 TMRB capture register (channels 0 through 7)
TBnCP0capture register (n=0 to 7)

31 30 29 28 27 26 25 24
TBnCP0 bit Symbol
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
bit Symbol
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
bit Symbol TBnCP015 TBnCP014 TBnCP013 TBnCP012 TBnCP011 TBnCP010 TBnCP09 TBnCP08
Read/Write R
After reset 0
Function Timer capture value: 15-8 bit data
7 6 5 4 3 2 1 0
Read/Write R
After reset 0
<TBnCP015-000>: 16bit up-counter capture value0
TBnCP1 capture register (n=0 to 7)

31 30 29 28 27 26 25 24
TBnCP1 bit Symbol
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
bit Symbol
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Read/Write R
After reset 0
7 6 5 4 3 2 1 0
Read/Write R
After reset 0
<TBnCP115-100>: 16bit up-counter capture value1

TMPM370
9.5 Description of Operations for Each Circuit
The channels operate in the same way, except for the differences in their specifications as shown in Table 9-1
and Table 9-2 . Therefore, the operational descriptions here are only for channel 0.
9.5.1 Prescaler
There is a 4-bit prescaler to generate the source clock for up-counter UC. The prescaler input
clock φT0 is fperiph, fperiph/2, fperiph/4, fperiph/8, fperiph/16 or fperiph/32 selected by
SYSCR1<PRCLK2:0> in the CG. The peripheral clock, fperiph, is either fgear, a clock selected by
SYSCR1<FPSEL> in the CG, or fc, which is a clock before it is divided by the clock gear.
The operation or the stop of a prescaler is set with TB0RUN<TB0PRUN> where writing “1” starts
counting and writing “0” clears and stops counting. Table 9-4 show prescaler output clock
resolutions.

TMPM370
Table 9-4 Prescaler Output Clock Resolutions @fc = 80MHz

Clear peripheral Clock gear Prescaler clock Prescaler output clock resolution
clock value selection
<FPSEL> <GEAR2:0> <PRCK2:0> φT1 φT4 φT16
1 3 5
000(fperiph/1) fc/2 (0.025μs) fc/2 (0.1μs) fc/2 (0.4μs)
001(fperiph/2) fc/22(0.05μs) fc/24(0.2μs) fc/26(0.8μs)
000 (fc)
100(fc/2)
0 (fgear)
101(fc/4)
110(fc/8)
000 (fc)
000(fperiph/1) － fc/23(0.1μs) fc/25(0.4μs)
100(fc/2)
1 (fc)
101(fc/4)
000(fperiph/1) －－ fc/25(0.4μs)
5
010(fperiph/4) － fc/2 (0.4μs) fc/27(1.6μs)
110(fc/8)

TMPM370
(Note 1) The prescaler output clock φTn must be selected as φTn<fsys. (φTn is slower than
fsys).
(Note 2) Do not change the clock gear while the timer is operating.
(Note 3) “⎯“ denotes a setting prohibited.

TMPM370
9.5.2 Up-counter (UC)

UC is a 16-bit binary counter.
• Source clock
UC source clock, specified by TB0MOD<TB0CLK1:0>, can be selected from either three
types φT1, φT4 and φT16 of prescaler output clock or the external clock of the TB0IN pin.
• Count start/ stop

Counter operation is specified by TB0RUN<TB0RUN>. UC starts counting if <TB0RUN>
= “1”, and stops counting and clears counter value if <TB0RUN> = “0”.
• Timing to clear UC
1) When a compare match is detected
By setting TB0MOD<TB0CLE> = “1”, UC is cleared in case the comparator detects a
match between counter value and the value set in TB0RG1. UC operates as a
free-running counter if TB0MOD<TB0CLE> = “0”.
2) When UC stops
UC stops counting and clears counter value if TB0RUN <TB0RUN> = “0”.
• UC overflow
If UC overflow occurs, the INTTB00 overflow interrupt is generated.

TMPM370
9.5.3 Timer registers (TB0RG0, TB0RG1)

TB0RG0 and TB0RG1 are registers for setting values to compare with up-counter values and
two registers are built into each channel. If the comparator detects a match between a value set
in this timer register and that in a UC up-counter, it outputs the match detection signal.
TB0RG0 andTB0RG1 consist of the double-buffered configuration which is paired with
register buffers. The double buffering is disabled in the initial state.
Controlling double buffering disable or enable is specified by TB0CR<TBWBF> bit. If the
<TBWBF> is set to “0”, the double buffering becomes disabled. If the <TBWBF> is set to “0”, it
becomes enabled. When the double buffering is enabled, a data transfer from the register buffer
to the timer register (Tb0RG0/1) is done in the case that UC is matched with TB0RG1. When the
counter is stopped even if the double buffering is enabled, the double buffering operates as a
single buffer, and an immediate data can be written to the TB0RG0 and TB0RG1.
TB0RG0/ TB0RG1 and the register buffers are assigned to the same address. If the
<TB0WBF> is set to “0,” the same value is written to TB0RG0, TB0RG1 and each register buffer;
if the <TB0WBF> is set to “1,” the value is only written to each register buffer. Therefore, in order
to write an initial value to the timer register, the register buffers must be set to “disable”. Then set
<TB0WBF> = “1”and write the following data to the register.
• Interrupt
INTTB00 is generated by UC count value matching with TB0RG0 value.
INTTB01 is generated by UC count value matching with TB0RG1 value.
9.5.4 Capture Control

This is a circuit that controls the timing to latch UC up-counter values into the TB0CP0 and
TB0CP1 capture registers. The timing to latch data is specified by TB0MOD <TB0CPM1:0>.
Software can also be used to capture values from the UC up-counter into the capture register;
specifically, UC values are taken into the TB0CP0 capture register each time “0” is written to
TB0MOD<TB0CP0>. To use this capability, the prescaler must be running
(TB0RUN<TB0PRUN> = “1”).

TMPM370
9.5.5 Capture Registers (TB0CP0, TB0CP1)

These are 16-bit registers for latching values from the UC up-counter. To read data from the
capture register, use a 16-bit data transfer instruction or read in the order of low-order bits
followed by high-order bits.
9.5.6 Up-counter capture register (TB0UC)

Other than the capturing functions shown above, the current count value of the UC can be captured by
reading the TB0UC registers.
9.5.7 Comparators (CP0,CP1)

These are 16-bit comparators for detecting a match by comparing set values of the UC
up-counter with set values of the TB0RG0 and TB0RG1 timer registers. If a match is detected,
INTTB00 and INTTB01 are generated.
9.5.8 Timer Flip-flop (TB0FF0)

The timer flip-flop (TB0FF0) is reversed by a match signal from the comparator and a latch
signal to the capture registers. It can be enabled or disabled to reverse by setting the
TB0FFCR<TB0C1T1, TB0C0T1, TB0E1T1, TB0E0T1>.
The value of TB0FF0 becomes undefined after a reset. The flip-flop can be reversed by
writing “00” to TB0FFCR<TB0FF0C1:0>. It can be set to “1” by writing “01,” and can be cleared
to “0” by writing “10.”
The TB0FF0 value can be output to the timer output pin:TB0OUT (shared with PA1). To
enable timer output, the port A related registers PACR and PAFR1 must be programmed
beforehand.
9.5.9 Capture interrupt (INTCAP00, INTCAP01)

Interrupts INTCAP00 and INTCAP01 can be generated at the timing of latching values from
the UC up-counter into the TB0CP0 and TB0CP1 capture registers. The interrupt setting is
specified by the CPU.

TMPM370
9.6 Description of Operations for Each Mode
9.6.1 16-bit Interval Timer Mode

-Generating interrupts at periodic cycles
To generate the INTTB01 interrupt, specify a time interval in the TB0RG1 timer register.
Same as TB0RG0, INTTB01 interrupt is generated by setting different interval time value
to TB0RG1 timer resister,
9.6.2 16-bit Event Counter Mode

It is possible to make it the event counter by using an input clock as an external clock
(TB0IN pin input).
The up-counter counts up on the rising edge of TB0IN pin input. It is possible to read the
count value by capturing value using software and reading the captured value.
To use it as an event counter, put the prescaler in a “RUN” state (TB0RUN<TB0PRUN> =

“1”).

TMPM370
9.6.3 16-bit Programmable Square Wave Output Mode (PPG)

Square waves with any frequency and any duty (programmable square waves) can be
output. The output pulse can be either low-active or high-active.
Programmable square waves can be output from the TB0OUT pin by triggering the timer
flip-flop (TB0FF0) to reverse when the set value of the up-counter (UC) matches the set
values of the timer registers (TB0RG0 and TB0RG1). Note that the set values of TB0RG0
and TB0RG1 must satisfy the following requirement:
(Set value of TB0RG0) < (Set value of TB0RG1)
Match with B0RG0

(INTTB00 interrupt)
Match with B0RG1
(INTTB01 interrupt)
TB0OUT pin
Fig. 9-2 Example of Output of Programmable Square Wave (PPG)
In this mode, by enabling the double buffering of TB0RG0 and TB0RG1, the value of
register buffers are shifted into TB0RG0 and TB0RG1 when the set value of the up-counter
matches the set value of TB0RG1. Since software writing time is secured by double buffer,
this facilitates handling of small duties pulse.
Match with TB0RG0

Up-counter = Q1 Up-counter = Q2
Match with TB0RG1
Trigger to shift to TB0RG1
TB0RG0
Q1 Q2
(compare value)
Register buffer Q2 Q3
Write TB0RG0
Fig. 9-3 Register Buffer Operation

TMPM370
The block diagram of this mode is shown below.
TB0RUN<TB0RUN>
TB0OUT (PPG output)
Selector
TB0IN0
φT1 16-bit up-counter UC0 F/F
φT4 Clear
φT16 (TB0FF0)
Match
16-bit comparator 16-bit comparator
Selector TB0RG0 TB0RG1
TB0RG0-WR
Register buffer 0 Register buffer 1

TB0CR<TB0WBF>
Internal data bus
Fig. 9-4 Block Diagram of 16-bit PPG Mode
Each register in the 16-bit PPG output mode must be programmed as listed below.
7 6 5 4 3 2 1 0
TB0EN ← 1 X X X X X X X Starts the TMRB0 module.
TB0RUN ← X X X X X 0 X 0 Stops the TMRB0
TB0RG0 ← * * * * * * * * Specifies a duty. (16 bits *32-bits register length)

← * * * * * * * *
TB0RG1 ← * * * * * * * * Specifies a cycle. (16 bits *32-bits register length)
← * * * * * * * *
TB0CR ← 1 0 X 0 0 0 0 0 Enables the TB0RG0 double buffering.
(Changes the duty/cycle when the INTTB0 interrupt is
generated)
TB0FFCR ← X X 0 0 1 1 1 0 Specifies to trigger TB0FF0 to reverse
when a match with TB0RG0 or TB0RG1 is detected,
and sets the initial value of TB0FF0 to "0."
TB0MOD ← 0 0 1 0 0 1 * * Designates the prescaler output clock as the input clock,
(** = 01, 10, 11) and disables the capture function.
PACR ← − − − − − − 1 －
Assigns PA1 to output and TB0OUT
PAFR1 ← − － − − − − 1 －
TB0RUN ← * * * * * 1 X 1 Starts TMRB0
X; Don’t care −; no change

TMPM370
9.6.4 External trigger Programmable Square Wave Output Mode (PPG)
Using an external count start trigger enables one-shot pulse generation with a short delay.
(1) The 16-bit up-counter (UC) is programmed to count up on the rising edge of the TB0IN pin
(TB0CR<TRGSEL0,CSSEL0>=”01”). The TB0RG0 is loaded with the pulse delay (d), and the
TB0RG1 is loaded with the sum of the TB0RG0 value (d) and the pulse width (P). The above
settings must be done while the 16-bit up-counter is stopped (TB0RUN<TB0RUN>=0).
(2) To enable the trigger for timer flip-flop, sets TB0FFCR<TB0E1T1, TB0E0T1> to 11. With this
setting, the timer flip-flop reverses when 16-bit up-counter (UC) corresponds to TB0RG0 or
TB0RG1.
(3) Sets TB0RUN<TB0RUN> to 1 to enable the count-up by an external trigger.
(4) After the generation of one-shot pulse by the external trigger, to disable reverse of the timer
flip-flop or to stop 16bit counter by TB0RUN<TB0RUN> setting.
Figure 9-5 shows one-shot pulse generation, with annotations showing (d) and (p).
Counter Clock
(Internal Clock) 0 d+ p
d
TB0IN Input PIn
(External Trigger Pulse) The counter starts at the rising edge of external trigger.
INTTB00 is
generated.
TB0RG0 Match
Toggle is INTTB01
enabled. is generated.
TB0RG1 Match
Toggle is disabled for a Toggle is
capture into CAP1. enabled.
TB0OUT (Timer Output) P in

Delay Pulse
(d) (p)
Fig. 9-5 One-shot pulse generation using an external count start trigger (with a delay)

TMPM370
9.7 Application example using the Capture Function

The capture function can be used to develop many applications, including those described below:
c One-shot pulse output triggered by an external pulse
d Pulse width measurement
c One-shot pulse output triggered by an external pulse

One-shot pulse output triggered by an external pulse is carried out as follows:
The 16-bit up-counter is made to count up by putting it in a free-running state using the prescaler
output clock. An external pulse is input through the TB0IN pin. A trigger is generated at the rising of
the external pulse by using the capture function and the value of the up-counter is taken into the
capture registers (TB0CP0).
The CPU must be programmed so that an interrupt INTCAP00 is generated at the rising of an
external trigger pulse. This interrupt is used to set the timer registers (TB0RG0) to the sum of the
TB0CP0 value (c) and the delay time (d), (c + d), and set the timer registers (TB0RG1) to the sum of
the TB0RG0 values and the pulse width (p) of one-shot pulse, (c + d + p).
TB0RG1 change must be completed before the next match.
In addition, the timer flip-flop control registers (TB0FFCR<TB0E1T1, TB0E0T1>) must be set to “11.”
This enables triggering the timer flip-flop (TB0FF0) to reverse when UC matches TB0RG0 and
TB0RG1. This trigger is disabled by the INTTB01 interrupt after a one-shot pulse is output.
Symbols (c), (d) and (p) used in the text correspond to symbols c, d and p in Fig. 9-6 One-shot Pulse
Output (With Delay).”
Put the counter in a free-running state.
Count clock
(Internal clock) c c+d c+d +p
TB0IN pin input
(External trigger pulse) Taking data into the capture register (TB0CP0)
INTCAP00 generation
INTTB00
Match with TB0RG0
Enable reverse INTTB01 generation
Match with TB0RG1

Enable
Disable reverse when
reverse
data is taken into CAP0
Timer output TB0OUTpin
Delay time Pulse width
(d) (p)
Fig. 9-6 One-shot Pulse Output (With Delay)

TMPM370
If a delay is not required, TB0FF0 is reversed when data is taken into TB0CP0, and
TB0RG1 is set to the sum of the TB0CPO value (c) and the one-shot pulse width (p), (c + p),
by generating the INTTB00 interrupt. TB0RG1 change must be completed before the next
match. TB0FF0 is enabled to reverse when UC matches with TB0RG1, and is disabled by
generating the INTTB01 interrupt.
Count clock
(Prescaler output
clock) c c+p
TB0IN input Taking data into the capture register
(External trigger pulse)
TB0CP0. INTCAP00 generation Taking data into the capture
register TB0CP1
INTTB01 generation
Match with TB0RG1
Enable reverse
Timer output TB0OUT pin
Pulse width
Enable reverse when data is (p) Disable reverse when data is taken into
taken into TB0CP0 TB0CP1
Fig. 9-7 One-shot Pulse Output Triggered by an External Pulse (Without Delay)

TMPM370
d Pulse width measurement

By using the capture function, the “H” level width of an external pulse can be measured.
Specifically, by putting it in a free-running state using the prescaler output clock, an
external pulse is input through the TB0IN pin and the up-counter (UC) is made to count
up. A trigger is generated at each rising and falling edge of the external pulse by using
the capture function and the value of the up-counter is taken into the capture registers
(TB0CP0, TB0CP1). The CPU must be programmed so that INTCAP01 is generated
at the falling edge of an external pulse input through the TB0IN pin.
The “H” level pulse width can be calculated by multiplying the difference between
TB0CP0 and TB0CP1 by the clock cycle of an internal clock.
For example, if the difference between TB0CP0 and TB0CP1 is 100 and the cycle of
the prescaler output clock is 0.5 us, the pulse width is 100 × 0.5 us = 50 us.
Caution must be exercised when measuring pulse widths exceeding the UC maximum
count time which is dependant upon the source clock used. The measurement of such
pulse widths must be made using software.
Prescaler output clock
C1 C2
TB0IN pin input
(external pulse)
Taking data into TB0CP0 C1
Taking data into TB0CP1 C2 C2
INTCAP00
INTCAP01
Fig. 9-8 Pulse Width Measurement
The “L” level width of an external pulse can also be measured. In such cases, the
difference between C2 generated the first time and C1 generated the second time is
initially obtained by performing the second stage of INTCAP00 interrupt processing as
shown in “Fig. 9-8 Pulse Width Measurement” and this difference is multiplied by the
cycle of the prescaler output clock to obtain the “Low” level width.

TMPM370
10 Serial Channel (SIO)

10.1 Features
This device has four serial I/O channels: SIO0 to SIO3. Each channel operates in either the UART
mode (asynchronous communication) or the I/O interface mode (synchronous communication)
which is selected by the user.
I/O interface mode Mode 0: This is the mode to transmit and receive I/O data
and associated synchronization signals (SCLK) to extend I/O.
Mode 1: TX/RX Data Length: 7 bits

Asynchronous (UART) mode: Mode 2: TX/RX Data Length: 8 bits
Mode 3: TX/RX Data Length: 9 bits
In the above modes 1 and 2, parity bits can be added. The mode 3 has a wakeup function in which
the master controller can start up slave controllers via the serial link (multi-controller system). Fig.
10-2 shows the block diagram of SIO0.
Each channel consists of a prescaler, a serial clock generation circuit, a receive buffer, its control
circuit, a transmit buffer and its control circuit. Each channel functions independently.
As the SIOs 0 to 3 operate in the same way, only SIO0 is described here.
TMPM370 10-1 Serial Channel

TMPM370
Table 10-1 Difference in the Specifications of SIO Modules

Channel 0 Channel 1 Channel 2 Channel 3
Pin name TXD0 (PE0) TXD1 (PA5) TXD2 (PD5) TXD3 (PF3)
RXD0 (PE1) RXD1 (PA6) RXD2 (PD6) RXD3 (PF4)
CTS0 /SCLK0 (PE2) CTS1 /SCLK1 (PA4) CTS2 /SCLK2 (PD4) CTS3 /SCLK3 (PF2)
Interrupt INTRX0 INTRX1 INTRX2 INTRX3
INTTX0 INTTX1 INTTX2 INTTX3
In the UART mode, TMRB output to TB4OUT TB4OUT TB7OUT TB7OUT
use for the serial transfer clock
SC0EN SC1EN SC2EN SC3EN
Enable register
0x4002_0080 0x4002_00C0 0x4002_0100 0x4002_0140
Transmit/ receive SC0BUF SC1BUF SC2BUF SC3BUF
buffer register 0x4002_0084 0x4002_00C4 0x4002_0104 0x4002_0144
SC0CR SC1CR SC2CR SC3CR
Control register
0x4002_0088 0x4002_00C8 0x4002_0108 0x4002_0148
Mode control SC0MOD0 SC1MOD0 SC2MOD0 SC3MOD0
register 0 0x4002_008C 0x4002_00CC 0x4002_010C 0x4002_014C
Baud rate generator SC0BRCR SC1BRCR SC2BRCR SC3BRCR
control 0x4002_0090 0x4002_00D0 0x4002_0110 0x4002_0150
Baud rate generator SC0BRADD SC1BRADD SC2BRADD SC3BRADD
control 2 0x4002_0094 0x4002_00D4 0x4002_0114 0x4002_0154
Register name Mode control SC0MOD1 SC1MOD1 SC2MOD1 SC3MOD1
(address) register 1 0x4002_0098 0x4002_00D8 0x4002_0118 0x4002_0158
Mode control SC0MOD2 SC1MOD2 SC2MOD2 SC3MOD2
register 2 0x4002_009C 0x4002_00DC 0x4002_011C 0x4002_015C
Receive FIFO SC0RFC SC1RFC SC2RFC SC3RFC
configuration register 0x4002_00A0 0x4002_00E0 0x4002_0120 0x4002_0160
Transmit FIFO SC0TFC SC1TFC SC2TFC SC3TFC
configuration register 0x4002_00A4 0x4002_00E4 0x4002_0124 0x4002_0164
Receive FIFO SC0RST SC1RST SC2RST SC3RST
status register 0x4002_00A8 0x4002_00E8 0x4002_0128 0x4002_0168
Transmit FIFO SC0TST SC1TST SC2TST SC3TST
status register 0x4002_00AC 0x4002_00EC 0x4002_012C 0x4002_016C
FIFO configuration SC0FCNF SC1FCNF SC2FCNF SC3FCNF
register 0x4002_00B0 0x4002_00F0 0x4002_0130 0x4002_0170

TMPM370
• Mode 0 (I/O Interface mode) /LSB first
bit 0 1 2 3 4 5 6 7
Transmission direction
• Mode 0 (I/O Interface mode) /MSB first
bit 7 6 5 4 3 2 1 0
Transmission direction
• Mode 1 (7 bits UART mode)
Without parity start bit 0 1 2 3 4 5 6 stop
With parity start bit 0 1 2 3 4 5 6 parity stop
• Mode 2 ( 8 bits UART mode)
Without parity start bit 0 1 2 3 4 5 6 7 stop
With parity start bit 0 1 2 3 4 5 6 7 p arity stop
• Mode 3 ( 9 bits UART mode)
start bit 0 1 2 3 4 5 6 7 8 stop
start bit 0 1 2 3 4 5 6 7 bit 8 Stop(Wake-up)
IIf bit 8=1, r epr esents address (select code)

IIf bit 8=0, r epr esents data.
Fig. 10-1 Data Format

TMPM370
10.2 Block Diagram (Channel 0)
Prescaler
φT0 2 4 8 16 32 64 128
φT1 φT4 φT16 φT64

Serial clock generation circuit
SC0BRCR TB4OUT
<BR0CK1, 0> (From TMRB4)
SC0BRCR SC0BRADD
<BR0S3: 0> <BR0K3: 0>
φT1 UART
Selector
Selector
Selector
mode
Divider
φT4 SIOCLK
φT16
φT64
SC0BRCR
<BR0ADDE> SC0MOD0 SC0MOD0
Baud rate generator <SC1, 0> <SM1, 0>
fSYS/2
Selector
÷2
I/O interface mode
SCLK0 input
(shared with
PE2)
SC0CR
I/O interface mode <IOC>
SCLK0 output Interrupt
(shared with request INTRX0
PE2) Interrupt
SC0MOD0 request INTTX0
Receive counter Serial channel Transmit counter
(÷ 16 only with UART) <WU> interrupt control (÷ 16 only with UART)
RXDCLK TXDCLK
SC0MOD0
<RXE> Receive control Transmit control CTS0
(Shared with
SC0CR
<PE> <EVEN> PE2)
SC0MOD0
<CTSE>
Parity control
RXD0 Receive buffer 1(shift register)

Transmit buffer 1 (shift register) TXD0
(shared with (Shared with
PE1) PE0)
RB8 Receive buffer 2(SC0BUF) Error flag TB8 Transmit buffer 2(SC0BUF)
SC0CR FIFO control
FIFO control <OERR><PERR><FERR>
Internal data Internal data Internal data

bus bus bus
Fig. 10-2 SIO0 Block Diagram

TMPM370
10.3 Operation of Each Circuit (Channel 0)
10.3.1 Prescaler
The device includes a 7-bit prescaler to generate necessary clocks to drive SIO0. The input
clock φT0 to the prescaler is selected by SYSCR1 of CG <PRCK2:0> to provide the frequency of
either fperiph/1, fperiph/2, fperiph/4, fperiph/8, fperiph/16 or fperiph/32.
The clock frequency fperiph is either the clock “fgear,” to be selected by SYSCR1<FPSEL> of
CG, or the clock “fc” before it is divided by the clock gear.
The prescaler becomes active only when the baud rate generator is selected for generating the
serial transfer clock. Table 10-2 list the prescaler output clock resolution.

TMPM370
Table 10-2 Clock Resolution to the Baud Rate Generator @ = 80MHz
Clear peripheral Clock gear Prescaler clock Prescaler output clock resolution
clock value selection
<FPSEL> <GEAR2:0> <PRCK2:0>
000(fperiph/1) fc/21(0.025μs) fc/23(0.1μs) fc/25(0.4μs) fc/27(1.6μs)

000 (fc)
100(fc/2)
0 (fgear)
101(fc/4)
110(fc/8)
000 (fc)
000(fperiph/1) － fc/23(0.1μs) fc/25(0.4μs) fc/27(1.6μs)
100(fc/2)
1 (fc)
101(fc/4)
000(fperiph/1) －－ fc/25(0.4μs) fc/27(1.6μs)
5 7
010(fperiph/4) － fc/2 (0.4μs) fc/2 (1.6μs) fc/29(6.4μs)
110(fc/8)

TMPM370
(Note 1) The prescaler output clock φTn must be selected so that the relationship “φTn < fsys”
is satisfied (so that φTn is slower than fsys).
(Note 2) Do not change the clock gear while SIO is operating.
(Note 3) The horizontal lines in the above table indicate that the setting is prohibited.
The serial interface baud rate generator uses four different clocks, i.e., φT1, φT4, φT16 and φT64, supplied from
the prescaler output clock.

TMPM370
10.3.2 Baud Rate Generator

The baud rate generator generates transmit and receive clocks to determine the serial
channel transfer rate.
The baud rate generator uses either the φT1, φT4, φT16 or φT64 clock supplied from the
7-bit prescaler. This input clock selection is made by setting the baud rate generator control
register, SC0BRCR <BR0CK1:0>.
The baud rate generator contains built-in dividers for divide by 1, N + m/16 (N=2~15,
m=1~15), and 16. The division is performed according to the settings of the baud rate
generator control registers SC0BRCR <BR0ADDE> <BR0S3:0> and SC0BRADD
<BR0K3:0> to determine the resulting transfer rate.
The highest baud rate of each mode is limited.
• UART mode
1) If SC0BRCR <BR0ADDE> = 0,
The setting of SC0BRADD <BR0K3:0> is ignored and the counter is divided by N
where N is the value set to SC0BRCR <BR0S3:0>. (N = 1 to 16).
2) If SC0BRCR <BR0ADDE> = 1,
The N + (16 - K)/16 division function is enabled and the division is made by using the
values N (set in SC0BRCR <BR0S3:0>) and K (set in SC0BRADD<BR0K3:0>). (N = 2
to 15, K = 1 to 15)
(Note) For the N values of 1 and 16, the above N+(16-K)/16 division function is
inhibited. So, be sure to set SC0BRCR<BR0ADDE> to “0.”
• I/O interface mode
The N + (16 - K)/16 division function cannot be used in the I/O interface mode. Be sure to
divide by N, by setting SC0BRCR <BR0ADDE> to “0”.
• Baud rate calculation to use the baud rate generator:
1) UART mode
Baud rated generator input clock
Baud rate = /16
Frequency divided by the divide ratio
The highest baud rate out of the baud rate generator is 2.5 Mbps.
The fsys frequency, which is independent of the baud rate generator, can be used as
the serial clock. In this case, the highest baud rate will be 5.0 Mbps.
2) I/O interface mode

Baud rated generator input clock
Baud rate = /2
Frequency divided by the divide ratio
When it uses a double buffer, the highest baud rate generated with the baud rate
generator becomes 20Mbps. (If double buffering is not used, the highest baud rate will
be 10 Mbps).

TMPM370
• Example baud rate setting:
1) Division by an integer (divide by N):

Selecting fc = 78.642 MHz for fperiph, setting φT0 to fperiph/16, using the baud rate
generator input clock φT1, setting the divide ratio N (SC0BRCR<BR0S3:0>) = 4, and
setting SC0BRCR<BR0ADDE> = “0,” the resulting baud rate in the UART mode is
calculated as follows:
* Clocking conditions System clock : High-speed (fc)

High speed clock gear : x 1 (fc)
Prescaler clock : fperiph/16 (fperiph = fsys)
fc/32
Baud rate = /16
4
= 78.642 × 106 ÷ 32 ÷ 4 ÷ 16 ≒ 38400 (bps)
(Note) The divide by (N + (16-K)/16) function is inhibited and thus SC0BRADD

<BR0K3:0> is ignored.
2) For divide by N + (16-K)/16 (only for UART mode):

Selecting fc = 9.6 MHz for fperiph, setting φT0 to fperiph/8, using the baud rate
generator input clock φT1, setting the divide ratio N (SC0BRCR<BR0S3:0>) = 7,
setting K (SC0BRADD<BR0K3:0>) = 3, and selecting SC0BRCR<BR0ADDE> = 1,
the resulting baud rate is calculated as follows:

High-speed clock gear : x 1 (fc)
fc/16
Baud rate = /16
(16 - 3)
7+
16
= 9.6 × 10 ÷ 16 ÷ ( 7 + 13 ) ÷ 16 = 4800 (bps)
6
16
Also, an external clock input may be used as the serial clock. The resulting baud rate
calculation is shown below:

TMPM370
• Baud rate calculation for an external clock input:
1) UART mode
Baud Rate = external clock input / 16
In this, the period of the external clock input must be greater than 2/fsys.
The highest baud rate must be less than 80 ÷ 2 ÷ 16 = 2.5 Mbps.
2) I/O interface mode

Baud Rate = external clock input
When double buffering is used, it is necessary to satisfy the following relationship:
External clock input period > 6/fsys
The highest baud rate must be less than 80 ÷ 6 = 13.3 Mbps.
When double buffering is not used, it is necessary to satisfy the following relationship:
External clock input period > 8/fsys
The highest baud rate must be less than 80 ÷ 8 = 10 Mbps.
The baud rate examples for the UART mode are shown in Table 10-3 and Table 10-4.

TMPM370
Table 10-3 Selection of UART Baud Rate

(Using the baud rate generator with SC0BRCR <BR0ADDE> = 0) Unit: (kbps)
Input clock
fc [MHz] Divide ratio N
(fc/4) (fc/16) (fc/64) (fc/256)
(Set to SC0BRCR <BR0S3 : 0>)
9.830400 2 76.800 19.200 4.800 1.200
↑ 4 38.400 9.600 2.400 0.600
↑ 8 19.200 4.800 1.200 0.300
↑ 16 9.600 2.400 0.600 0.150
(Note) This table shows the case where the system clock is set to fc, the clock gear is set to fc/1,
and the prescaler clock is set to fperiph/2.
Table 10-4 Selection of UART Baud Rate

(The TMRB4 timer output (internal TB4OUT) is used with the timer input clock set to φT1.)
Unit: (Kbbs)
fc 80 9.8304 8
TB4RG MHz MHz MHz
0x0001 625.0 76.8 62.5
0x0002 312.5 38.4 31.25
0x0003 25.6
0x0004 156.25 19.2 15.625
0x0005 125.0 15.36 12.5
0x0006 12.8
0x0008 78.125 9.6
0x000A 62.5 7.68 6.25
0x0010 39.0625 4.8
0x0014 31.25 3.84 3.125
Baud rate calculation to use the TMRB4 timer:
Clock frequency selected by SYSCR0<PRCK2:0>

Transfer rate =
TB4RG×2×2×16
(When input clock to the timer TMRB4 is φT1)
(Note 1) In the I/O interface mode, the TMRB4 timer output signal cannot be used internally
as the transfer clock.
(Note 2) This table shows the case where the system clock is set to fc, the clock gear is set
to fc, and the prescaler clock is set to fperiph/2.

TMPM370
10.3.3 Serial Clock Generation Circuit

This circuit generates basic transmit and receive clocks.

In the SCLK output mode with the SC0CR <IOC> serial control register set to “0,” the
output of the previously mentioned baud rate generator is divided by 2 to generate the
basic clock.
In the SCLK input mode with SC0CR <IOC> set to “1,” rising and falling edges are
detected according to the SC0CR <SCLKS> setting to generate the basic clock.
• Asynchronous (UART) mode :

According to the settings of the serial control mode register SC0MOD0 <SC1:0>, either
the clock from the baud rate register, the system clock (fSYS), the internal output signal of
the TMRB4 timer, or the external clock (SCLKO pin) is selected to generate the basic
clock, SIOCLK.
10.3.4 Receive Counter

The receive counter is a 4-bit binary counter used in the asynchronous (UART) mode and is
up-counted by SIOCLK. Sixteen SIOCLK clock pulses are used in receiving a single data bit
while the data symbol is sampled at the seventh, eighth, and ninth pulses. From these three
samples, majority logic is applied to decide the received data.
10.3.5 Receive Control Unit

• I/O interface mode:
In the SCLK output mode with SC0CR <IOC> set to “0,” the RXD0 pin is sampled on the
falling edge of the shift clock output to the SCLK0 pin.
In the SCLK input mode with SC0CR <IOC> set to “1,” the serial receive data RXD0 pin
is sampled on the rising or falling edge of SCLK input depending on the SC0CR
<SCLKS> setting.
• Asynchronous (UART) mode:

The receive control unit has a start bit detection circuit, which is used to initiate receive
operation when a normal start bit is detected.
10.3.6 Receive Buffer

The receive buffer is of a dual structure to prevent overrun errors. The first receive buffer (a
shift register) stores the received data bit-by-bit. When a complete set of bits have been
stored, they are moved to the second receive buffer (SC0BUF). At the same time, the
receive buffer full flag (SC0MOD2 “RBFLL”) is set to “1” to indicate that valid data is stored
in the second receive buffer. However, if the receive FIFO is set enabled, the receive data is
moved to the receive FIFO and this flag is immediately cleared.
If the receive FIFO has been disabled (SCOFCNF <CNFG> = 0 and SC0MOD1<FDPX1:0>
=01), the INTRX0 interrupt is generated at the same time. If the receive FIFO has been
enabled (SCNFCNF <CNFG> = 1 and SC0MOD1<FDPX1:0> = 01), an interrupt will be
generated according to the SC0RFC <RIL1:0> setting.

TMPM370
The CPU will read the data from either the second receive buffer (SC0BUF) or from the
receive FIFO (the address is the same as that of the receive buffer). If the receive FIFO has
not been enabled, the receive buffer full flag <RBFLL> is cleared to “0” by the read
operation. The next data received can be stored in the first receive buffer even if the CPU
has not read the previous data from the second receive buffer (SC0BUF) or the receive
FIFO.
If SCLK is set to generate clock output in the I/O interface mode, the double buffer control
bit SC0MOD2 <WBUF> can be programmed to enable or disable the operation of the
second receive buffer (SCOBUF).
By disabling the second receive buffer (i.e., the double buffer function) and also disabling
the receive FIFO (SCOFCNF <CNFG> = 0 and <FDPX1:0> = 01), handshaking with the
other side of communication can be enabled and the SCLK output stops each time one
frame of data is transferred. In this setting, the CPU reads data from the first receive buffer.
By the read operation of CPU, the SCLK output resumes.
If the second receive buffer (i.e., double buffering) is enabled but the receive FIFO is not
enabled, the SCLK output is stopped when the first receive data is moved from the first
receive buffer to the second receive buffer and the next data is stored in the first buffer filling
both buffers with valid data. When the second receive buffer is read, the data of the first
receive buffer is moved to the second receive buffer and the SCLK output is resumed upon
generation of the receive interrupt INTRX0. Therefore, no buffer overrun error will be
caused in the I/O interface SCLK output mode regardless of the setting of the double buffer
control bit SC0MOD2 <WBUF>.
If the second receive buffer (double buffering) is enabled and the receive FIFO is also
enabled (SCNFCNF <CNFG> = 1 and <FDPX1:0> = 01/11), the SCLK output will be
stopped when the receive FIFO is full (according to the setting of SCOFNCF <RFST>) and
both the first and second receive buffers contain valid data. Also in this case, if SCOFCNF
<RXTXCNT> has been set to “1,” the receive control bit RXE will be automatically cleared
upon suspension of the SCLK output. If it is set to “0,” automatic clearing will not be
performed.
(Note) In this mode, the SC0CR <OEER> flag is insignificant and the operation is
undefined. Therefore, before switching from the SCLK output mode to
another mode, the SC0CR register must be read to initialize this flag.
In other operating modes, the operation of the second receive buffer is always valid, thus
improving the performance of continuous data transfer. If the receive FIFO is not enabled,
an overrun error occurs when the data in the second receive buffer (SC0BUF) has not been
read before the first receive buffer is full with the next receive data. If an overrun error
occurs, data in the first receive buffer will be lost while data in the second receive buffer and
the contents of SC0CR <RB8> remain intact. If the receive FIFO is enabled, the FIFO must
be read before the FIFO is full and the second receive buffer is written by the next data
through the first buffer. Otherwise, an overrun error will be generated and the receive FIFO
overrun error flag will be set. Even in this case, the data already in the receive FIFO remains
intact.
The parity bit to be added in the 8-bit UART mode as well as the most significant bit in the
9-bit UART mode will be stored in SC0CR <RB8>.
In the 9-bit UART mode, the slave controller can be operated in the wake-up mode by

TMPM370
setting the wake-up function SC0MOD0 <WU> to “1.” In this case, the interrupt INTRX0 will
be generated only when SC0CR <RB8> is set to “1.”
10.3.7 Receive FIFO Buffer

In addition to the double buffer function already described, data may be stored using the
receive FIFO buffer. By setting <CNFG> of the SC0FCNF register and <FDPX1:0> of the
SC0MOD1 register, the 4-byte(maximum) receive buffer can be enabled. Also, in the UART
mode or I/O interface mode, data may be stored up to a predefined fill level. When the
receive FIFO buffer is to be used, be sure to enable the double buffer function.
If data with parity bit is to be received in the UART mode, parity check must be performed
each time a data frame is received.
10.3.8 Receive FIFO Operation

c I/O interface mode with SCLK output:
The following example describes the case a 6-byte data stream is received in the half duplex
mode:
SC0MOD1<6:5>=01: Transfer mode is set to half duplex mode.
SC0FCNF <4:0>=10111: Automatically inhibits continued reception after reaching the fill level.
The number of bytes to be used in the receive FIFO is the same as
the interrupt generation fill level.
SC0RFC<1:0>=00: Sets the interrupt to be generated at fill level 4.
SC0RFC<7:6>=11: Clears receive FIFO and sets the condition of interrupt generation.
In this condition, data reception may be initiated by setting the half duplex transmission mode
and writing “1” to the RXE bit. When the data is stored all in the receive shift register, receive
buffer and receive FIFO, SCxMOD0<RXE> is automatically cleared and the receive
operation is finished.
Receive buffer1 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte
RX FIFO 1 byte 2 byte 3 byte 4 byte 4 byte 4 byte

1 byte 2 byte 3 byte 3 byte 3 byte
1 byte 2 byte 2 byte 2 byte
1 byte 1 byte 1 byte
Receive interrupt
RBFLL
RXE
Fig. 10-3 Receive FIFO Operation

TMPM370
d I/O interface mode with SCLK input:

The following example describes the case a 6-byte data stream is received:
SC0FCNF <1:0> = 10101: Automatically allows continued reception after reaching the fill level.
SC0RFC <1:0> = 00: Sets the interrupt to be generated at fill level 4.
SC0RFC <7:6> = 10: Clears receive FIFO and sets the condition of interrupt generation
The number of bytes to be used in the receive FIFO is the maximum allowable number.
In this condition, 6-byte data reception may be initiated by setting the half duplex transmission
mode and writing “1” to the RXE bit. When the data is stored all in the receive shift register,
receive buffer and receive FIFO, receive FIFO interrupt is generated. This setting enables the
next data reception as well. Data can be received continuously by reading data in FIFO
according to the input clock.
RX FIFO 1 byte 2 byte 3 byte 4 byte 4 byte 4 byte

1 byte 2 byte 3 byte 3 byte 3 byte
1 byte 2 byte 2 byte 2 byte
1 byte 1 byte 1 byte
Receive interrupt
RBFLL
RXE
Fig. 10-4 Receive FIFO Operation

TMPM370
10.3.9 Transmit Counter

The transmit counter is a 4-bit binary counter and is counted by SIOCLK as in the case of
the receive counter. In UART mode, it generates a transmit clock (TXDCLK) on every 16th
clock pulse.
SIOCLK
15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2
TXDCLK
Fig. 10-5 Transmit Clock Generation
10.3.10 Transmit Control Unit

• I/O interface mode:
In the SCLK output mode with SC0CR <IOC> set to “0,” each bit of data in the transmit
buffer is output to the TXD0 pin on the rising edge of the shift clock output from the
SCLK0 pin.
In the SCLK input mode with SC0CR <IOC> set to “1,” each bit of data in the transmit
buffer is output to the TXD0 pin on the rising or falling edge of the input SCLK signal
according to the SC0CR <SCLKS> setting.
• Asynchronous (UART) mode:

When the CPU writes data to the transmit buffer, data transmission is initiated on the
rising edge of the next TXDCLK and the transmit shift clock (TXDSFT) is also generated.

TMPM370
• Handshake function
The CTS pin enables frame by frame data transmission so that overrun errors can be
prevented. This function can be enabled or disabled by SC0MOD0 <CTSE>.
When the CTS0 pin is set to the “H” level, the current data transmission can be completed
but the next data transmission is suspended until the CTS0 pin returns to the “L” level.
However in this case, the INTTX0 interrupt is generated, the next transmit data is requested
to the CPU, data is written to the transmit buffer, and it waits until it is ready to transmit data.
Although no RTS pin is provided, a handshake control function can be easily implemented
by assigning a port for the RTS function. By setting the port to “H” level upon completion of
data reception (in the receive interrupt routine), the transmit side can be requested to
suspend data transmission.
TXD RXD
CTS RTS (Any port)
Transmit side Receive side

Fig. 10-6 Handshake Function
Data write timing to transmit

buffer or shift register
Transmission is
CTS suspended during
this period ②
① 13 14 15 16 1 2 3 14 15 16 1 2 3
SIOCLK
TXDCLK
TXD start bit bit 0
Fig. 10-7 CTS (Clear to Transmit) Signal Timing
(Note 1) If the CTS signal is set to “H” during transmission, the next data transmission is
suspended after the current transmission is completed.
(Note 2) Data transmission starts on the first falling edge of the TXDCLK clock after CTS is set to
“L.”

TMPM370
10.3.11 Transmit Buffer

The transmit buffer (SC0BUF) is in a dual structure. The double buffering function may be
enabled or disabled by setting the double buffer control bit <WBUF> in serial mode control
register 2 (SC0MOD2). If double buffering is enabled, data written to Transmit Buffer 2
(SCOBUF) is moved to Transmit Buffer 1 (shift register).
If the transmit FIFO has been disabled (SCOFCNF <CNFG> = 0 or 1 and SC0MOD1＜
FDPX1:0＞＝01), the INTTX0 interrupt is generated at the same time and the transmit
buffer empty flag <TBEMP> of SC0MOD2 is set to “1.” This flag indicates that Transmit
Buffer 2 is now empty and that the next transmit data can be written. When the next data is
written to Transmit Buffer 2, the <TBEMP> flag is cleared to “0.”
If the transmit FIFO has been enabled (SCNFCNF <CNFG> = 1 and SC0MOD1＜FDPX1:0
＞＝10/11), any data in the transmit FIFO is moved to the Transmit Buffer 2 and <TBEMP>
flag is immediately cleared to “0.” The CPU writes data to Transmit Buffer 2 or to the
transmit FIFO.
If the transmit FIFO is disabled in the I/O interface SCLK input mode and if no data is set in
Transmit Buffer 2 before the next frame clock input, which occurs upon completion of data
transmission from Transmit Buffer 1, an under-run error occurs and a serial control register
(SC0CR) <PERR> parity/under-run flag is set.
If the transmit FIFO is enabled in the I/O interface SCLK input mode, when data
transmission from Transmit Buffer 1 is completed, the Transmit Buffer 2 data is moved to
Transmit Buffer 1 and any data in transmit FIFO is moved to Transmit Buffer 2 at the same
time.
If the transmit FIFO is disabled in the I/O interface SCLK output mode, when data in
Transmit Buffer 2 is moved to Transmit Buffer 1 and the data transmission is completed, the
SCLK output stops. So, no under-run errors can be generated.
If the transmit FIFO is enabled in the I/O interface SCLK output mode, the SCLK output
stops upon completion of data transmission from Transmit Buffer 1 if there is no valid data
in the transmit FIFO.
Note) In the I/O interface SCLK output mode, the SC0CR <PEER> flag is
insignificant. In this case, the operation is undefined. Therefore, to switch
from the SCLK output mode to another mode, SC0CR must be read in
advance to initialize the flag.
If double buffering is disabled, the CPU writes data only to Transmit Buffer 1 and the
transmit interrupt INTTX0 is generated upon completion of data transmission.
If handshaking with the other side is necessary, set the double buffer control bit <WBUF> to
“0” (disable) to disable Transmit Buffer 2; any setting for the transmit FIFO should not be
performed.

TMPM370
10.3.12 Transmit FIFO Buffer

In addition to the double buffer function already described, data may be stored using the
transmit FIFO buffer. By setting <CNFG> of the SC0FCNF register and <FDPX1:0> of the
SC0MOD1 register, the 4-byte transmit buffer can be enabled. In the UART mode or I/O
interface mode, up to 4 bytes of data may be stored.
If data is to be transmitted with a parity bit in the UART mode, parity check must be performed
on the receive side each time a data frame is received.
Note) Please clear transmission FIFO after setting of the forwarding mode of
SIO (half duplex/full duplex) and permission (SC0FCNF<CNFG>="1") of
FIFO when you use transmission FIFO Buffer.
10.3.13 Transmit FIFO Operation

c I/O interface mode with SCLK output (normal mode):

SC0FCNF <4:0> = 01011: Inhibits continued transmission after reaching the fill level.
SC0TFC <1:0> = 00: Sets the interrupt to be generated at fill level 0.
SC0TFC <7:6> =11: Clears transmit FIFO and sets the condition of interrupt generation
In this condition, data transmission can be initiated by setting the transfer mode to half
duplex, writing 5 bytes of data to the transmit buffer and transmit FIFO , and setting the
<TXE> bit to “1.” When the last transmit data is moved to the transmit buffer, the transmit
FIFO interrupt is generated. When transmission of the last data is completed, the clock is
stopped and the transmission sequence is terminated.
Data 5
TX FIFO
Data 4 Data 5
Data 3 Data 4 Data 5
Data 2 Data 3 Data 4 Data 5
Transmit buffer 2 Data 1 Data 2 Data 3 Data 4 Data 5
TBEMP
INTTX0
TXE
Fig. 10-8 Transmit FIFO Operation

TMPM370
d I/O interface mode with SCLK input (normal mode):

SC0FCNF <4:0> = 01001: Allows continued transmission after reaching the fill level.
SC0TFC <1:0> = 00: Sets the interrupt to be generated at fill level 0.
SC0TFC <7:6> = 11: Clears the receive FIFO and sets the condition of interrupt
generation.
In this condition, data transmission can be initiated along with the input clock by setting the
transfer mode to half duplex, writing 5 bytes of data to the transmit buffer and the transmit
FIFO, and setting the <TXE> bit to “1.” When the last transmit data is moved to the transmit
buffer, the transmit FIFO interrupt is generated.
Data 5
TX FIFO
Data 4 Data 5
Data 3 Data 4 Data 5
Data 2 Data 3 Data 4 Data 5
TBEMP
INTTX0
TXE
Fig. 10-9 Transmit FIFO Operation

TMPM370
10.3.14 Parity Control Circuit

If the parity addition bit <PE> of the serial control register SC0CR is set to “1,” data is sent
with the parity bit. Note that the parity bit may be used only in the 7- or 8-bit UART mode.
The <EVEN> bit of SC0CR selects either even or odd parity.
Upon data transmission, the parity control circuit automatically generates the parity with the
data written to the transmit buffer (SC0BUF). After data transmission is complete, the parity
bit will be stored in SC0BUF bit 7 <TB7> in the 7-bit UART mode and in bit 7 <TB8> in the
serial mode control register SC0MOD in the 8-bit UART mode. The <PE> and <EVEN>
settings must be completed before data is written to the transmit buffer.
Upon data reception, the parity bit for the received data is automatically generated while the
data is shifted to receive buffer 1 and moved to receive buffer 2 (SC0BUF). In the 7-bit
UART mode, the parity generated is compared with the parity stored in SC0BUF <RB7>,
while in the 8-bit UART mode, it is compared with the bit 7 <RB8> of the SC0CR register. If
there is any difference, a parity error occurs and the <PERR> flag of the SC0CR register is
set. When the FIFO is used, the <PERR> indicates that one or more data have the parity
error among the receiving data.
In the I/O interface mode, the SC0CR <PERR> flag functions as an under-run error flag, not
as a parity flag.
10.3.15 Error Flag

Three error flags are provided to inprove the reliability of received data.
1. Overrun error <OERR>: Bit 4 of the serial control register SC0CR

In both UART and I/O interface modes, this bit is set to “1” when an error is generated
by completing the reception of the next frame receive data before the receive buffer
has been read. If the receive FIFO is enabled, the received data is automatically
moved to the receive FIFO and no overrun error will be generated until the receive
FIFO is full (or until the usable bytes are fully occupied). This flag is set to “0” when it is
read. In the I/O interface SCLK output mode, no overrun error is generated and
therefore, this flag is inoperative and the operation is undefined.
Note) Changing the mode from I/O interface SCLK output mode to the other
mode, read SC0CR to clear SC0CR<OERR> flag.
2. Parity error/under-run error <PERR>: Bit 3 of the SC0CR register

In the UART mode, this bit is set to “1” when a parity error is generated. A parity error is
generated when the parity generated from the received data is different from the parity
received. This flag is set to “0” when it is read.
In the I/O interface mode, this bit indicates an under-run error. When the double buffer
control bit <WBUF> of the serial mode control register SC0MOD2 is set to “1” in the
SCLK input mode, if no data is set to the transmit double buffer before the next data
transfer clock after completing the transmission from the transmit shift register, this
error flag is set to “1” indicating an under-run error. If the transmit FIFO is enabled, any
data content in the transmit FIFO will be moved to the buffer. When the transmit FIFO
and the double buffer are both empty, an under-run error will be generated. Because
no under-run errors can be generated in the SCLK output mode, this flag is inoperative

TMPM370
and the operation is undefined. If Transmit Buffer 2 is disabled, the under-run flag
<PERR> will not be set. This flag is set to “0” when it is read.
Note) Changing the mode from I/O interface SCLK output mode to the other
mode, read SC0CR to clear SC0CR<PERR> flag.
3. Framing error <FERR>: Bit 2 of the SC0CR register

In the UART mode, this bit is set to “1” when a framing error is generated. This flag is
set to “0” when it is read. A framing error is generated if the corresponding stop bit is
determined to be “0” by sampling the bit at around the center. Regardless of the
<SBLEN> (stop bit length) setting of the serial mode control register 2, SC0MOD2, the
stop bit status is determined by only 1 bit on the receive side.
Operation mode Error flag Function

UART OERR Overrun error flag
PERR Parity error flag
FERR Framing error flag
I/O Interface OERR Overrun error flag
(SCLK input) PERR Underrun error flag (WBUF = 1)
Fixed to 0 (WBUF = 0)
FERR Fixed to 0
I/O Interface OERR Operation undefined
(SCLK output) PERR Operation undefined
FERR Fixed to 0
10.3.16 Direction of Data Transfer

In the I/O interface mode, the direction of data transfer can be switched between “MSB first”
and “LSB first” by the data transfer direction setting bit <DRCHG> of the SC0MOD2 serial
mode control register 2. Don't switch the direction when data is being transferred.
10.3.17 Stop Bit Length

In the UART transmission mode, the stop bit length can be set to either 1 or 2 bits by bit 4
<SBLEN> of the SC0MOD2 register. In the receive side, the stop bit is always regarded as
1 bit.
10.3.18 Status Flag

If the double buffer function is enabled (SC0MOD2 <WBUF> = “1”), the bit 6 flag <RBFLL>
of the SC0MOD2 register indicates the condition of receive buffer full. When one frame of
data has been received and transferred from buffer 1 to buffer 2, this bit is set to “1” to show
that buffer 2 is full (data is stored in buffer 2). When the receive buffer is read by CPU, it is
cleared to “0.” If <WBUF> is set to “0,” this bit is insignificant and must not be used as a
status flag. When double buffering is enabled (SC0MOD2 <WBUF> = “1”), the bit 7 flag
<TBEMP> of the SC0MOD2 register indicates that Transmit Buffer 2 is empty. When data is
moved from Transmit Buffer 2 to Transmit Buffer 1 (shift register), this bit is set to “1”
indicating that Transmit Buffer 2 is now empty. When data is set to the transmit buffer by

TMPM370
CPU, the bit is cleared to “0.” If <WBUF> is set to “0,” this bit is insignificant and must not be
used as a status flag.
10.3.19 Configurations of Transmit/Receive Buffer

<WBUF> = 0 <WBUF> = 1
Transmit buffer Single Double
UART
Receive buffer Double Double
I/O Interface Transmit buffer Single Double
(SCLK input) Receive buffer Double Double
I/O Interface Transmit buffer Single Double
(SCLK output) Receive buffer Single Double
10.3.20 Software reset

Software reset is generated by writing the bits 1 and 0 of SC0MOD2 <SWRST1:0> as “10”
followed by “01”. As a result, SC0MOD0<RXE>, SC0MOD1<TXE>,
SC0MOD2<TBEMP>,<RBFLL>,<TXRUN> of mode registers and SC0CR<OERR>, <PERR>,
<FERR> of control registers and internal circuit is initialized. Other states are maintained.

TMPM370
10.3.21 Interrupt/Error Generation Timing
c RX Interrupts
Fig. 10-10 shows the data flow of receive operation and the route of read.
Fig. 10-10 Receive Buffer/FIFO Configuration Diagram
Single Buffer / Double Buffer

RX interrupts are generated at the time depends on the transfer mode and the buffer
configurations, which are given as follows.
Buffer
UART mode IO interface modes
Configuration
· Immediately after the raising / falling edge of the last

SCLK
Single Buffer -
(Rising or falling is determined according to
SC0CR<SCLKS> setting.)
· Immediately after the raising / falling edge of the last

SCLK
(Rising or falling is determined according to
Double Buffer · Around the center of the first stop bit
SCxCR<SCLKS> setting.)
· On data transfer from the shift register to the buffer

by reading buffer.
(Note) Interrupts are not generated when an overrun error is occurred.
FIFO
In use of FIFO, receive interrupt is generated on the condition that the following either
operation and SC0RFC<RFIS > setting are established.
z Reception completion of all bits of one frame.
z Reading FIFO
Interrupt conditions are decided by the SCxRFC<RFIS> settings as described in Table
10-5.
TMPM370
Table 10-5 Receive Interrupt conditions in use of FIFO

SC0RFC<RFIS> Interrupt conditions
“0” "The fill level of FIFO" is equal to "the fill level of FIFO interruption generation."
"The fill level of FIFO" is greater than or equal to "the fill level of FIFO intrruption
“1”
generation."
d TX Interrupts
Fig. 10-11 shows the data flow of transmit operation and the route of write.
Fig. 10-11 Transmit Buffer/FIFO Configuration Diagram
Single Buffer / Double Buffer

TX interrupts are generated at the time depends on the transfer mode and the buffer
configurations, which are given as follows.
Buffer
UART mode IO interface modes
Configuration
Immediately after the raising / falling edge of the last SCLK

Single Buffer Just before the stop bit is sent (Rising or falling is determined according to
SC0CR<SCLKS> setting.)
Double Buffer When a data is moved from the transmit buffet to the transmit shift register.
(Note) If double buffer is enabled, a interrupt is also generated when the data is
moved from the buffer to the shift register by writing to the buffer.
FIFO
In use of FIFO, transmit interrupt is generated on the condition that the following either
operation and SC0TFC<TFIS> setting are established.
z Transmittion completion of all bits of one frame.

TMPM370
z Writing FIFO
Interrupt conditions are decided by the SC0TFC<TFIS> settings as described in Table
10-6.
Table 10-6 Transmit Interrupt conditions in use of FIFO

SC0TFC<TFIS> Interrupt conditions
“0” "The fill level of FIFO" is equal to "the fill level of FIFO interruption generation."
"The fill level of FIFO" is smaller than or equal to "the fill level of FIFO intrruption
“1”
generation."
③ Error Generation
UART Mode
7 bits
8 bits
mode 9 bits
7bits+Parity
8bits＋Parity
Framing Error
Around the center of stop bit
Overrun Error
Parity Error - Around the center of parity bit
I/O Interface Mode

Immediately after the raising / falling edge of the last SCLK
Overrun Error (Rising or falling is determined according to SC0CR<SCLKS>
setting.)
Immediately after the rising or falling edge of the next SCLK.

Underrun Error (Rising or falling is determined according to SC0CR<SCLKS>
setting.)

TMPM370
10.4 Register Description (Only for Channel 0)
The channel 0 registers are described here. Each register for all the channels operates in the same way.
(Note) Do not modify any control register when data is being transmitted or received.
10.4.1 Enable register
7 6 5 4 3 2 1 0
bit Symbol SIOE
SC0EN Read/Write R R/W
After reset 0 0
“０” is read. SIO
operation
Function
0:disabled
1:enabled
<SIOE>: Specified the SIO operation.

To use the SIO, enable the SIO operation.
When the operation is disabled, no clock is supplied to the other registers in the SIO module.
This can reduce the power consumption.
If the SIO operation is executed and then disabled, the settings of each register are
maintained.
10.4.2 Buffer register
SC0BUF works as a transmit buffer for WR operation and as a receive buffer for
RD operation.
7 6 5 4 3 2 1 0
bit Symbol TB7/RB7 TB6/RB6 TB5/RB5 TB4/RB4 TB3/RB3 TB2/RB2 TB1/RB1 TB0/RB0
SC0BUF Read/Write R/W
After reset 0 0 0 0 0 0 0 0
TB7 to 0 : Transmit buffer/FIFO
Function
RB7 to 0 : Receive buffer/FIFO
<TB7:0> Transmit buffer (at WR operation).
<RB7:0> Receive buffer (at RD operation).

TMPM370
10.4.3 Control register
7 6 5 4 3 2 1 0
bit Symbol RB8 EVEN PE OERR PERR FERR SCLKS IOC
Read/Write R R/W R (Cleared to “0” when read) R/W
SC0CR
After reset 0 0 0 0 0 0 0 0
Receive Parity Add parity 0: Normal operation 0: SCLK0 (For I/O
data bit 8 (For UART) (For UART) 1: Error interface)
(For UART) 0: Odd 0: Disabled 0:Baud rate
Function
1: Even 1: Enabled 1: SCLK0 generator
Overrun Parity/ Framing
1:SCLK0
underrun
pin input
<RB8>: 9th bit of the received data in the 9 bits UART mode.
<EVEN>: Selects even or odd parity.

“0”: odd parity.
“1”: even parity.
The parity bit may be used only in the 7- or 8-bit UART mode.
<PE>: Controls enabling/ disabling parity.

The parity bit may be used only in the 7- or 8-bit UART mode.
<OERR>: Error flag (see note)

<PERR>: Indicate overrun error, parity error, underrun error and framing error.
<FERR>:
<SCLKS>: The input clock edge used by the data sending and receiving is selected.
“0”: Data transmit/receive at rising edges of SCLK0
“1”: Data transmit/receive at falling edges of SCLK0
Please set it to "0" at the clock output mode.
<IOC>: Selects input clock in the I/O interface mode.

“0”: baud rate generator
“1”: SCLK0 pin input.
(Note) Any error flag is cleared when read.

TMPM370
10.4.4 Mode control register 0
7 6 5 4 3 2 1 0
bit Symbol TB8 CTSE RXE WU SM1 SM0 SC1 SC0
Read/Write R/W
SC0MOD0 After reset 0 0 0 0 0 0 0 0
Transmit Handshake Receive Wake-up Serial transfer mode Serial transfer clock
data bit 8 function control function 00: I/O interface mode (for UART)
control 0:Reception 0:Reception 01: 7-bit length 00: TB4OUT
0: CTS disabled disabled UART mode 01: Baud rate generator
Function
diable 1:Reception 1:Reception 10: 8-bit length 10: Internal clock fSYS
1: CTS enabled enabled UART mode 11: External clock
enable 11: 9-bit length (SCLK0 input)
UART mode
<TB8>: Writes the 9th bit of transmit data in the 9 bits UART mode.
<CTSE>: Controls handshake function.

Setting “1” enables handshake function using CTS pin.
<RXE>: Controls reception (see note 1).

Set <RXE> after setting each mode register (SC0MOD0, SC0MOD1 and SC0MOD2).
<WU>: Controls wake-up function.

This function is available only at 9-bit UART mode.
9-bit UART mode Other

modes
0 Interrupt when received
don’t care
1 Interrupt only when RB9=1
<SM1:0>: Specifies transfer mode.
<SC1:0>: Selects the serial transfer clock in the UART mode.

As for the I/O interface mode, the serial transfer clock can be set in the control register
SC0CR. When TMRB output is used for the serial transfer clock, TB4OUT is used in
SIO0,1, and TB7OUT is used in SIO2,3.
(Note 1) With <RXE> set to “0,” set each mode register (SC0MOD0, SC0MOD1 and
SC0MOD2). Then set <RXE> to “1.”
(Note 2) Do not clear SC0MOD0<RXE> to “0” during the receiving data.

TMPM370
7 6 5 4 3 2 1 0
bit Symbol I2S0 FDPX1 FDPX0 TXE SINT2 SINT1 SINT0 -
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
SC0MOD1
After reset 0 0 0 0 0 0 0 0
IDLE Transfer mode setting Transmit Interval time of continuous Write “0”.
Function 0: Stop 00: Transfer prohibited control transmission
1: Start 01: Half duplex(RX) 0:Disabled (for I/O interface)
10:Half duplex(TX) 1: Enabled 000: None 100:8SCLK
11:Full duplex 001:1SCLK 101:16SCLK
010:2SCLK 110:32SCLK
011:4SCLK 111:64SCLK
<I2S0>: Specifies the IDLE mode operation.
<FDPX1:0>: Configures the transfer mode in the I/O interface mode. Also configures the FIFO if it is
enabled. In the UART mode, it is used only to specify the FIFO configuration.
<TXE>: This bit enables transmission and is valid for all the transfer modes (see note 1).
<SINT2:0>: Specifies the interval time of continuous transmission when double buffering or FIFO is
enabled in the I/O interface mode. This parameter is valid only for the I/O interface
mode when SCLK0 pin input is not selected.
(Note 1) Specify the mode first and then specify the <TXE> bit.
(Note 2) Do not stop the transmit operation (by setting <TXE> = "0") when data is being
transmitted.

TMPM370
7 6 5 4 3 2 1 0
bit Symbol TBEMP RBFLL TXRUN SBLEN DRCHG WBUF SWRST1 SWRST0
Read/Write R R/W
SC0MOD2 After reset 1 0 0 0 0 0 0 0
Transmit Receive In STOP bit Setting W-buffer SOFT RESET
buffer Buffer full transmission (for UART) transfer 0: Disabled Overwrite “01” on “10”to
Function empty flag flag flag 0: 1-bit direction 1: Enabled reset.
0: full 0: Empty 0: Stop 1: 2-bit 0: LSB first
1: Empty 1: full 1: Start 1: MSB first
<TBEMP>: This flag shows that the transmit double buffers are empty. When data in the transmit
double buffers is moved to the transmit shift register and the double buffers are empty,
this bit is set to “1.” Writing data again to the double buffers sets this bit to “0.”
If double buffering is disabled, this flag is insignificant.
<RBFLL>: This is a flag to show that the receive double buffers are full. When a receive operation
is completed and received data is moved from the receive shift register to the receive
double buffers, this bit changes to “1” while reading this bit changes it to “0.”
If double buffering is disabled, this flag is insignificant.
<TXRUN>: This is a status flag to show that data transmission is in progress.

<TXRUN> and <TBEMP> bits indicate the following status.
<TXRUN> <TBEMP> Status

1 - Transmission in progress
1 Transmission completed
0
0 Wait state with data in TX buffer
<SBLEN>: This specifies the length of stop bit transmission in the UART mode. On the receive
side, the decision is made using only a single bit regardless of the <SBLEN> setting.
<DRCHG>: Specifies the direction of data transfer in the I/O interface mode. In the UART mode, it is
fixed to LSB first.
<WBUF>: This parameter enables or disables the transmit/receive buffers to transmit (in both
SCLK output/input modes) and receive (in SCLK output mode) data in the I/O interface
mode and to transmit data in the UART. When receiving data in the I/O interface mode (I
SCLK input) and UART mode, double buffering is enabled in both cases that 0 or 1 is
set to <WBUF> bit.
<SWRST1:0>: Overwriting “01” in place of “10” generates a software reset. When this software reset
is executed, the following bits and their internal circuits are initialized (see note 1, 2
and 3).
Register Bit
SC0MOD0 RXE
SC0MOD1 TXE
SC0MOD2 TBEMP,RBFLL,TXRUN,
SC0CR OERR,PERR,FERR

TMPM370
(Note 1) While data transmission is in progress, any software reset operation must be
executed twice in succession.
(Note 2) A software reset requires 2 clocks-duration at the time between the end of
recognition and the start of execution of software reset instruction.
(Note 3) A software reset initializes other bits. Resetting a mode register and a control
register are needed.

TMPM370
10.4.7 Baud rate generator control register(SC0BRCR)

Baud rate generator control register 2(SC0BRADD)
7 6 5 4 3 2 1 0
bit Symbol - BR0ADDE BR0CK1 BR0CK0 BR0S3 BR0S2 BR0S1 BR0S0
Read/Write R/W
SC0BRCR After reset 0 0 0 0 0 0 0 0
Write “0”. N + (16 − K)/ Select input clock to the Division ratio “N”
16 divider baud rate generator 0000: 16
function 00: φT1 0001: 1
Function 0: disabled 01: φT4 0010: 2
1: enabled 10: φT16 :
11: φT64 1111: 15
7 6 5 4 3 2 1 0
bit Symbol BR0K3 BR0K2 BR0K1 BR0K0
Read/Write R R/W
SC0BRADD
“0” is read. Specify K for the “N + (16 − K)/16” division
0000: Prohibited
0001: K=1
Function
0010: K=2
:
1111: K=15
<RB0ADDE>: Specifies N + (16-K)/16 division function.

N + (16-K)/16 division function can only be used in the UART mode.
<RB0CK1:0>: Specifies the baud rate generator input clock.
<RB0S3:0>: Specifies division ratio “N”.
<RB0K3:0>: Specifies K for the “N+(16-K)/16” division.
The division ratio of the baud rate generator can be specified in the registers shown above.
Table 10-5 lists the settings of baud rate generator division ratio.
Table 10-7 Setting division ratio

BR0ADDE=0 BR0ADDE=1 (Note 1)
(Only UART)
BR0S Specify “N” (Note 2) (Note 3)
BR0K No setting required Setting “K” (Note 4)
Division ratio Divide by N N + (16 − K) division
16

TMPM370
(Note 1) To use the “N + (16 - K)/16” division function, be sure to set BR0K <BR0ADDE> to
“1” after setting the K value to BR0K. The “N + (16 - K)/16” division function can
only be used in the UART mode.
(Note 2) The division ratio 1(“0001”) and 16(“0000”) cannot be applied when the “N + (16 -
K)/16” division function is used in the UART mode.
(Note 3) The division ratio 1 (“0001”) is available only for using double buffer in the I/O
interface mode.
(Note 4) Specifying “K = 0” is prohibited.

TMPM370
10.4.8 FIFO configuration register
7 6 5 4 3 2 1 0
bit Symbol Reserved Reserved Reserved RFST TFIE RFIE RXTXCNT CNFG
Read/Write R/W
SC0FCNF After reset 0 0 0 0 0 0 0 0
Bytes used TX interrupt RX interrupt Automatic FIFO
in RX FIFO for TX FIFO for RX FIFO disable of enable
Be sure to write “000”. 0: Maximum 0: Disabled 0:Disabled RXE/TXE 0: Disabled
Function
1:Same as 1: Enabled 1: Enabled 0:None 1: Enabled
FILL level of 1:Auto
RX FIFO disable
<RFST>: When RX FIFO is enabled, the number of RX FIFO bytes to be used is selected (see
note).
0: The maximum number of bytes of the FIFO configured (see also <CNFG>).
1: Same as the fill level for receive interrupt generation specified by SC0RFC <RIL1:0>.
<TFIE>: When TX FIFO is enabled, transmit interrupts are enabled or disabled by this parameter.
<RFIE>: When RX FIFO is enabled, receive interrupts are enabled or disabled by this parameter.
<RXTXCNT>: Controls automatic disabling of transmission and reception.

The mode control register SCOMOD1 <FDPX1:0> is used to set the types of TX/RX.
Setting “1” enables to operate as follows.
Half duplex When the receive shift register, receive buffer and RX FIFO are filled
RX up to the specified number of valid bytes, SC0MOD0<RXE> is
automatically set to “0” to inhibit further reception.
Half duplex When the data transfer in the TX FIFO, the transmit buffer and the
TX transmit shift register is completed, SC0MOD1<TXE> is
automatically set to “0” to inhibit further transmission.
Full duplex When either of the above two conditions is satisfied, TXE/RXE are
automatically set to “0” to inhibit further transmission and
reception.
<CNFG>: Enables FIFO.

If enabled, the SCOMOD1 <FDPX1:0> setting automatically configures FIFO as follows:
(The type of TX/RX can be specified in the mode control register 1
SC0MOD1<FDPX1:0>).
Half duplex RX FIFO 4byte

RX
Half duplex TX FIFO 4byte
TX
Full duplex RX FIFO 2byte＋TX FI O 2byte
(Note1) Regarding TX FIFO, the maximum number of bytes being configured is always
available. The available number of bytes is the bytes already written to the TX FIFO.
(Note2) FIFO cannot be used in the 9bit UART mode.

TMPM370
10.4.9 RX FIFO configuration register
7 6 5 4 3 2 1 0
bit Symbol RFCS RFIS RIL1 RIL0
Read/Write W R/W R R/W
SC0RFC
RX FIFO Select “0” is read. FIFO fill level to generate RX
clear interrupt interrupts
generation
1: Clear condition 00:4byte
0: when the (2 Byte at full duplex)
“0” is read. data reaches 01:1byte
to the 10:2byte
specified fill 11:3byte
Function level.
1: when the
data reaches to
the specified fill
level or the data
exceeds the
specified fill
level at the
time data is
read.
<RFCS>: Clears RX FIFO

Setting “1” clears RX FIFO and “0” is always read.
<RFIS>: Specifies the condition of interrupt generation.

0: An interrupt is generated when it reaches to the specified fill level.
An interrupt is generated when it is reaches to the specified fill level or if it exceeds the
specified fill level at the time data is read.
<RIL1:0>: Specifies FIFO fill level(see note 1).
Half duplex Full duplex

00 4byte 2byte
01 1byte 1byte
10 2byte 2byte
11 3byte 1byte
(Note 1) RIL1 is ignored when FDPX1:0 = 11 (full duplex).

(Note 2) Clearing the receive FIFO should be done after the setting of transfer mode and
enabling FIFO.

TMPM370
10.4.10 TX FIFO configuration register
7 6 5 4 3 2 1 0
bit Symbol TFCS TFIS TIL1 TIL0
Read/Write W R/W R R/W
SC0TFC After reset 0 0 0 0 0
TX FIFO Select “0” is read. FIFO fill level to generate TX
clear interrupt interrupts.
generation
1:Clear condition 00:Empty
Always 0: when the 01:1byte
reads “0”. data reaches 10:2byte
to the 11:3byte
specified fill Note: TIL1 is ignored when
level. FDPX1:0=11 (full duplex).
Function 1: when the
data reaches to
the specified fill
level or the data
cannot reach
the
specified fill
level at the
time new data
is read.
<TFCS>: Clears TX FIFO.

Setting “1” clears TX FIFO and “0” is always read.
<TFIS>: Selects interrupt generation condition.

0: An interrupt is generated when the data reaches to the specified fill level.
1: An interrupt is generated when the data reaches to the specified fill level or the data
cannot reach the
specified fill level at the time new data is read.
<TIL1:0>: Selects FIFO fill level (see note).
Half duplex Full duplex

00 Empty Empty
01 1byte 1byte
10 2byte Empty
11 3byte 1byte
(Note 1) TIL1 is ignored when FDPX1:0 = 11 (full duplex).

(Note 2) Clearing the transmit FIFO should be done after the setting of transfer mode and
enabling FIFO.
(Note 3) Please set SC0TFC again when shifting to standby mode (IDLE,STOP) with
SC0EN<0>=0 (SIO operation prohibition * clock stop) or SC0MOD1<7>=0 (operation
stop * clock stop of the standby mode inside).

TMPM370
10.4.11 RX FIFO status register
7 6 5 4 3 2 1 0
bit Symbol ROR RLVL2 RLVL1 RLVL0
Read/Write R R R
SC0RST After reset 0 0 0 0 0
RX FIFO “0” is read. Status of RX FIFO fill level
Overrun 000:Empty
001:1Byte
Function
1: 010:2Byte
Generated 011:3Byte
100:4Byte
<ROR>: Flags for RX FIFO overrun. When the overrun occurs, these bits are set to “1” (see note).
<RLVL2:0>: Shows the fill level of RX FIFO.
(Note) The <ROR> bit is cleared to “0” when receive data is read from the SC0BUF
register.
10.4.12 TX FIFO status register
7 6 5 4 3 2 １ 0
bit Symbol TUR TLVL2 TLVL1 TLVL0
Read/Write R R R
SC0TST
TX FIFO “0” is read. Status of TX FIFO fill level
Under run 000:Empty
1:Generated 001:1Byte
Function
Cleared by 010:2Byte
writing FIFO 011:3Byte
100:4Byte
<TUR>: Flags for TX FIFO underrun. When the underrun occurs, these bits are set to “1” (see
note).
<TLVL2:0>: Shows the fill level of TX FIFO.
(Note) The <TUR> bit is cleared to “0” when transmit data is written to the SC0BUF
register.

TMPM370
10.5 Operation in Each Mode
10.5.1 Mode 0 (I/O interface mode)

Mode 0 consists of two modes, the “SCLK output” mode to output synchronous clock and
the “SCLK input” mode to accept synchronous clock from an external source. The following
operational descriptions are for the case use of FIFO is disabled. For details of FIFO
operation, refer to the previous sections describing receive/transmit FIFO functions.
c Transmitting data
SCLK output mode
In the SCLK output mode, if SC0MOD2<WBUF> is set to “0” and the transmit double
buffers are disabled, 8 bits of data are output from the TXD0 pin and the synchronous
clock is output from the SCLK0 pin each time the CPU writes data to the transmit buffer.
When all data is output, the INTTX0 interrupt is generated.
If SC0MOD2 <WBUF> is set to “1” and the transmit double buffers are enabled, data is
moved from Transmit Buffer 2 to Transmit Buffer 1 when the CPU writes data to
Transmit Buffer 2 while data transmission is halted or when data transmission from
Transmit Buffer 1 (shift register) is completed. When data is moved from Transmit
Buffer 2 to Transmit Buffer 1, the transmit buffer empty flag SC0MOD2 <TBEMP> is
set to “1,” and the INTTX0 interrupt is generated. If Transmit Buffer 2 has no data to be
moved to Transmit Buffer 1, the INTTX0 interrupt is not generated and the SCLK0
output stops.

TMPM370
Transmit data
write timing
SCLK0 output
TXD0 bit 0 bit 1 bit 6 bit 7 bit 0
(INTTX0 interrupt request)
TXRUN
<WBUF>=“0” (if double buffering is disabled)
Transimit data
write timing
SCLK0 output
TBRUN
TBEMP
<WBUF>=“1” (if double buffering is enabled and there is data in buffer 2)
Transmit data
write timing
SCLK0 output
TXD0 bit 0 bit 1 bit 6 bit 7
TBRUN
TBEMP
<WBUF>=“1” (if double buffering is enabled and there is no data in buffer 2)
Fig. 10-12 Transmit Operation in the I/O Interface Mode (SCLK0 Output Mode)

TMPM370
SCLK input mode

In the SCLK input mode, if SC0MOD2 <WBUF> is set to “0” and the transmit double
buffers are disabled, 8-bit data that has been written in the transmit buffer is output
from the TXD0 pin when the SCLK0 input becomes active. When all 8 bits are sent, the
INTTX0 interrupt is generated. The next transmit data must be written before the
timing point “A” as shown in Fig. 10-13.
If SC0MOD2 <WBUF> is set to “1” and the transmit double buffers are enabled, data is
moved from Transmit Buffer 2 to Transmit Buffer 1 when the CPU writes data to
Transmit Buffer 2 before the SCLK0 becomes active or when data transmission from
Transmit Buffer 1 (shift register) is completed. As data is moved from Transmit Buffer 2
to Transmit Buffer 1, the transmit buffer empty flag SC0MOD2 <TBEMP> is set to “1”
and the INTTX0 interrupt is generated. If the SCLK0 input becomes active while no
data is in Transmit Buffer 2, although the internal bit counter is started, an under-run
error occurs and 8-bit dummy data (FFh) is sent.

TMPM370
Transimit data A
write timing
SCLK0 input
(<SCLKS>=0
Rising edge mode)
SCLK0 input
(<SCLKS>=1
Falling edge mode)
TXD0 bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1
<WBUF>=“0” (if double buffering is disabled
Transimit data A
write timing
SCLK0 input
(<SCLKS>=0
Rising edge more)
SCLK0 input
(<SCLKS>=1
Falling edge mode)
TBRUN
TBEMP
<WBUF>=“1” (if double buffering is enabled and there is data in buffer 2)
Transmit data A
write timing
SCLK0 input
(<SCLKS>=0
Rising edge mode)
SCLK0 input
(<SCLKS>=1
Falling edge mode)
TXD0 bit 0 bit 1 bit 5 bit 6 bit 7 １ 1
(INTTX0 Interrupt request)
TBRUN
TBEMP
PERR(functions to detect under-run errors)
<WBUF>=“1” (if double buffering is enabled and there is no data in buffer 2)
Fig. 10-13 Transmit Operation in the I/O Interface Mode (SCLK0 Input Mode)

TMPM370
d Receiving data
SCLK output mode
In the SCLK output mode, if SC0MOD2 <WBUF> = “0” and receive double buffering is
disabled, a synchronous clock pulse is output from the SCLK0 pin and the next data is
shifted into receive buffer 1 each time the CPU reads received data. When all the 8 bits
are received, the INTRX0 interrupt is generated.
The first SCLK output can be started by setting the receive enable bit SC0MOD0
<RXE> to “1.” If the receive double buffering is enabled with SC0MOD2 <WBUF> set
to “1,” the first frame received is moved to receive buffer 2 and receive buffer 1 can
receive the next frame successively. As data is moved from receive buffer 1 to receive
buffer 2, the receive buffer full flag SC0MOD2 <RBFULL> is set to “1” and the INTRX0
interrupt is generated.
While data is in receive buffer 2, if CPU cannot read data from receive buffer 2 before
completing reception of the next 8 bits, the INTRX0 interrupt is not generated and the
SCLK0 clock stops. In this state, reading data from receive buffer 2 allows data in
receive buffer 1 to move to receive buffer 2 and thus the INTRX0 interrupt is generated
and data reception resumes.
Receive data
write timing
SCLK0 output
RXD0 bit 0 bit 1 bit 6 bit 7 bit 0
(INTRX0 interrupt request)
Receive data
write timing
SCLK0 output
RXD0 bit7 bit 0 bit 1 bit 6 bit 7 bit 0
(INTRX0 Interrupt request)
RBFULL
<WBUF>=“1” (if double buffering is enabled and data is read from buffer 2)
Receive data
write timing
SCLK0 output
RXD0 bit7 bit 0 bit 1 bit 6 bit 7
RBFULL
<WBUF>=“1” (if double buffering is enabled and data cannot be read from buffer 2)
Fig. 10-14 Receive Operation in the I/O Interface Mode (SCLK0 Output Mode)

TMPM370
SCLK input mode

In the SCLK input mode, receiving double buffering is always enabled, the received frame
can be moved to receive buffer 2 and receive buffer 1 can receive the next frame
successively.
The INTRX receive interrupt is generated each time received data is moved to received
buffer 2.
Receive data
read timing
SCLK0 input
(<SCLKS>=0
Rising edge mode)
SCLK0 input
(<SCLKS>=1
Falling edge mode)
RXD0 bit 0 bit 1 bit 5 bit 6 bit 7 bit 0
INTRX0 Interrupt request)
RBFULL
If data is read from buffer 2

Receive data
read timing
SCLK0 input
(<SCLKS>=0
Rising edge mode)
SCLK0 input
(<SCLKS>=1
Falling edge mode)
RXD0 bit 0 bit 1 bit 5 bit 6 bit 7 bit 0
INTRX0 Interrupt request)
RBFULL
OERR
If data cannot be read from buffer 2
Fig. 10-15 Receive Operation in the I/O Interface Mode (SCLK0 Input Mode)
(Note) To receive data, SC0MOD <RXE> must always be set to “1” (receive enable) in the
SCLK output / SCLK input mode.

TMPM370
e Transmit and receive (full-duplex)

The full-duplex mode is enabled by setting bit 6 <FDPX0> of the serial mode control
register 1 (SC0MOD1) to “1”.
SCLK output mode

In the SCLK output mode, if SC0MOD2 <WBUF> is set to “0” and both the transmit
and receive double buffers are disabled, SCLK is output when the CPU writes data to
the transmit buffer. Subsequently, 8 bits of data are shifted into receive buffer 1 and the
INTRX0 receive interrupt is generated. Concurrently, 8 bits of data written to the
transmit buffer are output from the TXD0 pin, the INTTX0 transmit interrupt is
generated when transmission of all data bits has been completed. Then, the SCLK
output stops. In this, the next round of data transmission and reception starts when the
data is read from the receive buffer and the next transmit data is written to the transmit
buffer by the CPU. The order of reading the receive buffer and writing to the transmit
buffer can be freely determined. Data transmission is resumed only when both
conditions are satisfied.
If SC0MOD2 <WBUF> = “1” and double buffering is enabled for both transmission and
reception, SCLK is output when the CPU writes data to the transmit buffer.
Subsequently, 8 bits of data are shifted into receive buffer 1, moved to receive buffer 2,
and the INTRX0 interrupt is generated. While 8 bits of data is received, 8 bits of
transmit data is output from the TXD0 pin. When all data bits are sent out, the INTTX0
interrupt is generated and the next data is moved from the Transmit Buffer 2 to
Transmit Buffer 1. If Transmit Buffer 2 has no data to be moved to Transmit Buffer 1
(SC0MOD2 <TBEMP> = 1) or when receive buffer 2 is full (SC0MOD2 <RBFULL> = 1),
the SCLK clock is stopped. When both conditions, receive data is read and transmit
data is written, are satisfied, the SCLK output is resumed and the next round of data
transmission is started.

TMPM370
Receive data
read timing
Transmit data
write timing
SCLK0 output
RXD0 bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1
Receive data
read timing
Transmit data
write timing
SCLK0 output
<WBUF>=“1” (if double buffering is enabled)
Receive data
read timing
Transmit data
write timing
SCLK0 output
RXD0 bit 0 bit 1 bit 5 bit 6 bit 7
<WBUF>=“1” (if double buffering is enabled)
Fig. 10-16 Transmit/Receive Operation in the I/O Interface Mode (SCLK0 Output Mode)

TMPM370
SCLK input mode

In the SCLK input mode with SC0MOD2 <WBUF> set to “0” and the transmit double
buffers are disabled (double buffering is always enabled for the receive side), 8-bit
data written in the transmit buffer is output from the TXD0 pin and 8 bits of data is
shifted into the receive buffer when the SCLK input becomes active. The INTTX0
interrupt is generated upon completion of data transmission and the INTRX0 interrupt
is generated at the instant the received data is moved from receive buffer 1 to receive
buffer 2. Note that transmit data must be written into the transmit buffer before the
SCLK input for the next frame (data must be written before the point A in Fig. 10-15).
As double buffering is enabled for data reception, data must be read before completing
reception of the next frame data.
If SC0MOD2 <WBUF> = “1” and double buffering is enabled for both transmission and
reception, the interrupt INTRX0 is generated at the timing Transmit Buffer 2 data is
moved to Transmit Buffer 1 after completing data transmission from Transmit Buffer 1.
At the same time, the 8 bits of data received is shifted to buffer 1, it is moved to receive
buffer 2, and the INTRX0 interrupt is generated. Upon the SCLK input for the next
frame, transmission from Transmit Buffer 1 (in which data has been moved from
Transmit Buffer 2) is started while receive data is shifted into receive buffer 1
simultaneously. If data in receive buffer 2 has not been read when the last bit of the
frame is received, an overrun error occurs. Similarly, if there is no data written to
Transmit Buffer 2 when SCLK for the next frame is input, an under-run error occurs.

TMPM370
A
Receive data
read timing
Transmit data
write timing
SCLK0 input

Receive data
read timing
Transmit data
A
write timing
SCLK0 input
<WBUF>=“1” (if double buffering is enabled with no errors)

Receive data
read timing
Transmit data
A
write timing
SCLK0 input
PERR（Under-run errors）
<WBUF>=“1” (if double buffering is enabled with error generation)

Fig. 10-17 Transmit/Receive Operation in the I/O Interface Mode (SCLK0 Input Mode)

TMPM370
10.5.2 Mode 1 (7-bit UART Mode)

The 7-bit UART mode can be selected by setting the serial mode control register (SC0MOD
<SM1, 0>) to “01”.
In this mode, parity bits can be added to the transmit data stream; the serial mode control
register (SC0CR <PE>) controls the parity enable/disable setting. When <PE> is set to “1”
(enable), either even or odd parity may be selected using the SC0CR <EVEN> bit. The
length of the stop bit can be specified using SC0MOD2<SBLEN>.
The following table shows the control register settings for transmitting in the following data
format.
even
start bit 0 1 2 3 4 5 6 parity stop
Transmission direction (Transmission rate of 2400 bps @ fc = 9.8304 MHz)
* Clocking conditions System clock : high- speed (fc)

High-speed clock gear : x1 (fc)

TMPM370
10.5.3 Mode 2 (8-bit UART Mode)

The 8-bit UART mode can be selected by setting SC0MOD0 <SM1:0> to “10.” In this mode,
parity bits can be added and parity enable/disable is controlled using SC0CR <PE>. If <PE>
= “1” (enabled), either even or odd parity can be selected using SC0CR <EVEN>.
The control register settings for receiving data in the following format are as follows:
odd
start bit 0 1 2 3 4 5 6 7 parity stop
Transmission direction (transmission rate of 9600 bps @ fc = 9.8304 MHz)

High-speed clock gear : x1 (fc)

TMPM370
10.5.4 Mode 3 (9-bit UART)

The 9-bit UART mode can be selected by setting SC0MOD0 <SM1:0> to “11.” In this mode,
parity bits must be disabled (SC0CR <PE> = “0”).
The most significant bit (9th bit) is written to bit 7 <TB8> of the serial mode control register 0
(SC0MOD0) for transmitting data. The data is stored in bit 7 <RB8> of the serial control
register SC0CR. When writing or reading data to/from the buffers, the most significant bit
must be written or read first before writing or reading to/from SC0BUF. The stop bit length
can be specified using SC0MOD2 <SBLEN>.
Wakeup function
In the 9-bit UART mode, slave controllers can be operated in the wake-up mode by setting
the wake-up function control bit SC0MOD0 <WU> to “1.” In this case, the interrupt INTRX0
will be generated only when SC0CR <RB8> is set to “1”.
TXD RXD TXD RXD TXD RXD TXD RXD
Master Slave 1 Slave 2 Slave 3
(Note)The TXD pin of the slave controller must be set to the open drain output mode
using the ODE register.
Fig. 10-18 Serial Links to Use Wake-up Function

TMPM370
Protocol
c Select the 9-bit UART mode for the master and slave controllers.
d Set SC0MOD <WU> to “1” for the slave controllers to make them ready to receive data.
e The master controller is to transmit a single frame of data that includes the slave controller
select code (8 bits). In this, the most significant bit (bit 8) <TB8> must be set to “1”.
start bit 0 1 2 3 4 5 6 7 8 stop
Slave controller select code “1”
f Each slave controller receives the above data frame; if the code received matches with the
controller's own select code, it clears the WU bit to “0”.
g The master controller transmits data to the designated slave controller (the controller of
which SC0MOD <WU> bit is cleared to “0”). In this, the most significant bit (bit 8) <TB8>
must be set to “0”.
start bit 0 1 2 3 4 5 6 7 bit 8 stop
Data “0”
h The slave controllers with the <WU> bit set to “1” ignore the receive data because the most
significant bit (bit 8) <RB8> is set to “0” and thus no interrupt (INTRX0) is generated.
Also, the slave controller with the <WU> bit set to “0” can transmit data to the master
controller to inform that the data has been successfully received.
An example: Using the internal clock fSYS as the transfer clock, two slave controllers are
serially linked as follows.
TXD RXD TXD RXD TXD RXD
Master Slave 1 Slave 2
Select code Select code

00000001 00001010

TMPM370
11 Watchdog Timer (Watch Dog Timer)
The watchdog timer (WDT) is for detecting malfunctions (runaways) of the CPU caused by noises or
other disturbances and remedying them to return the CPU to normal operation. If the timer detects a
runaway, it generates a non-maskable interrupt or an internal reset to notify the CPU. The watchdog
timer starts immediately after reset release.
11.1 Configuration
Fig. 11-1 shows the block diagram of the watchdog timer
RESET pin
WDMOD <RESCR>
Internal reset
Non-maskable
interrupt request
(NMI)
WDMOD Selector
<WDTP2:0>
fSYS
Reset
Internal reset
Write
0x4E
Watch dog timer

Control Register WDCR
Internal data bus
Fig. 11-1 Block Diagram of the Watchdog Timer
TMPM370 11-1 Watchdog Timer

TMPM370
11.2 Outline
The watchdog timer consists of the binary counters that are arranged in 25 stages and work using the
fSYS system clock as an input clock. The outputs produced by these binary counters are 215, 217, 219,
221, 223 are 225.By selecting one of these outputs with WDMOD <WDTP2:0>, NMI can be generated
when an overflow occurs, as shown in Fig. 11-2.
11.2.1 Interrupt Mode (WDMOD<RESCR>=0)

When an overflow occurs, the watchdog timer generates NMI to the CPU.
WDT counter n Overflow 0
NMI
Write of a clear code

WDT clear
Fig. 11-2 Interrupt Mode
11.2.2 Reset Mode (WDMOD<RESCR>=1)
When an overflow occurs, resetting the chip itself is an option to choose. If the chip is reset, a reset is
affected for a 32-state time, as shown in Fig. 11-3. If this reset is affected, the clock fSYS that the clock
gear generates by dividing the clock fC of the high-speed oscillator by 1 is used as an input clock fSYS.
Overflow
WDT counter
n
NMI
Internal reset
32-state
(3.2 μs @ fosc = 10 MHz, fC = fsys = 10 MHz,)
Fig. 11-3 Reset Mode

TMPM370
11.3 Control Registers

The watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR.
11.3.1 Watchdog Timer Mode Register (WDMOD)

1. Enabling/disabling the watchdog timer <WDTE>
When resetting, WDMOD <WDTE> is initialized to "1" and the watchdog timer is enabled.
To disable the watchdog timer, this bit must be set to "0" and, at the same time, the disable code
(0xB1) must be written to the WDCR register. This dual setting is intended to minimize the
probability that the watchdog timer may inadvertently be disabled if a runaway occurs.
To change the status of the watchdog timer from "disable" to "enable," set the <WDTE> bit to "1".
2. Specifying the detection time of the watchdog timer <WDTP2: 0>

This is a 3-bit register for specifying the NMI time for runaway detection. When a reset is effected,
this register is initialized to WDMOD <WDTP2: 0> = "000." Fig. 11-4 shows the detection time of
the watchdog timer.
3. Enabling/disabling the watchdog timer in IDLE mode <I2WDT>

Enabling/disabling the watchdog timer in IDLE mode is controlled by this bit. Writing “1” to this bit
enables the watchdog timer and writing “0” to this bit disables the watchdog timer in IDLE mode.
(Note) The watchdog timer is halted in STOP mode.
4. Watchdog timer out reset connection <RESCR>

Setting this bit to "1" enables the watch dog timer to be reset when a runaway is detected. Since a
reset initializes this bit to "1," a counter overflow causes a reset.
11.3.2 Watchdog Timer Control Register (WDCR)

This is a register for disabling the watchdog timer function and controlling the clearing function of
the binary counter.
• Disabling control
By writing the disable code (0xB1) to this WDCR register after setting WDMOD <WDTE> to "0," the
watchdog timer can be disabled.
WDMOD ← 0 − − − − − − − Clears WDTE to "0."

WDCR ← 1 0 1 1 0 0 0 1 Writes the disable code (0xB1).
• Enabling control
Set WDMOD <WDTE> to "1".
• Watchdog timer clearing control

Writing the clear code (0x4E) to the WDCR register clears the binary counter and allows it to
resume counting.
WDCR ← 0 1 0 0 1 1 1 0 Writes the clear code (0x4E)
(Note) Writing the disable code (0xB1) clears the binary counter.

TMPM370
Watchdog Timer Mode Register

7 6 5 4 3 2 1 0
bit Symbol WDTE WDTP2 WDTP1 WDTP0 I2WDT RESCR
WDMOD Read/Write R/W R/W R R/W R/W
(0x4004_0000) After reset 1 0 0 0 0 1 0
Function WDT Selects WDT detection time "0" is read. IDLE WDT Write "0."
control 15 0: Stop Out control
000: 2 /fSYS
17 1: Start 0: Generates
001: 2 /fSYS
0: Disable 19 NMI
010: 2 /fSYS
1: Enable 21
011: 2 /fSYS
23 1: Generates
100: 2 /fSYS
25 reset
101: 2 /fSYS
110: Setting prohibited
111: Setting prohibited
Watchdog timer out control

0 Generates NMI
1 Generates reset
Detection time of watchdog timer @ fc = 80 MHz

SYSCR1 Detection time of watchdog timer
clock gear WDMOD<WDTP2:0>
value 000 001 010 011 100 101
<GEAR2:0>
000 （fc） 0.41 ms 1.64 ms 6.55 ms 26.21 ms 104.21 ms 419.43 ms
100 (fc/2) 0.82 ms 3.28 ms 13.11 ms 52.43 ms 209.72 ms 838.86 ms
101 (fc/4) 1.64 ms 6.55 ms 26.21 ms 104.86 ms 419.43 ms 1.68 s
110 (fc/8) 3.28 ms 13.11 ms 52.43 ms 209.72 ms 838.86 ms 3.36 s
111 (fc/16) 6.55 ms 26.21 ms 104.86 ms 419.43 ms 1.68 s 6.71 s
Enable/disable control of the watchdog timer

0 Disable
1 Enable
Watchdog Timer Control Register

7 6 5 4 3 2 1 0
bit Symbol -
WDCR
Read/Write W
(0x4004_0004)
After reset -
Function 0xB1 : WDT disable code
0x4E : WDT clear code
Disable & clear of WDT

0xB1 WDT disable code
0x4E WDT clear code
Others -
Fig. 11-4 Watchdog Timer Registers

TMPM370
11.4 Operation
The watchdog timer generates the NMI or an internal reset after a lapse of the detection time specified
by the WDMOD <WDTP2: 0> register. Before generating the NMI or an internal reset, the binary
counter for the watchdog timer must be cleared to "0" using software (instruction). If the CPU
malfunctions (runaways) due to noise or other disturbances and cannot execute the instruction to
clear the binary counter, the binary counter overflows and the non-maskable interrupt by the NMI or
an internal reset is generated. The CPU is able to recognize the occurrence of a malfunction
(runaway) by identifying the non-maskable interrupt and to restore the faulty condition to normal by
using a malfunction (runaway) countermeasure program.
The watchdog timer begins operation immediately after a reset is cleared.
In STOP mode, the watchdog timer is reset and in an idle state. In IDLE mode, its operation depends
on the WDMOD <I2WDT> setting. Before putting it in IDLE mode, WDMOD <I2WDT> must be set to
an appropriate setting, as required.
Example:
1. To clear the binary counter
7 6 5 4 3 2 1 0
WDCR ← 0 1 0 0 1 1 1 0 Writes the clear code (0x4E)
2. To set the detection time of the watchdog timer to 217/fSYS.

7 6 5 4 3 2 1 0
WDMOD ← 1 0 0 1 − − − −
3. To disable the watchdog timer.

7 6 5 4 3 2 1 0
WDMOD ← 0 − − − − − − − Clears WDTE to "0"
WDCR ← 1 0 1 1 0 0 0 1 Writes the disable code (0xB1)
(Note 1) The counter of the watchdog timer stops at the debug mode.

TMPM370
12. Oscillation Frequency Detector (OFD)
12.1 Configuration
The oscillation frequency detector generates a reset for I/O if the oscillation of high frequency for CPU
clock OFDMNPLLexceeds the detection frequency range.
The oscillation frequency detection is controlled by OFDCR1, OFDCR2 registers and the detection fre-
quency range is specified by OFDMNPLLOFF/OFDMNPLLON/OFDMXPLLOFF/OFDMXPLLON which
are the detection frequency setting registers. The lower detection frequency is specified by OFDMN-
PLLOFF/OFDMNPLLON registers and the higher detection frequency is specified by OFDMXPLLOFF/
OFDMXPLLON registers. An initial value of detection frequency is shown in Figure 12-1.
When the oscillation frequency detection is enabled, writing to OFDMNPLLOFF/OFDMNPLLON/OFD-
MXPLLOFF/OFDMXPLLON registers is disabled. Therefore, the setting the detection frequency to these
registers should be done when the oscillation frequency detection is disabled. And writing to OFDCR2/
OFDMNPLLOFF/OFDMNPLLON/OFDMXPLLOFF/OFDMXPLLON registers is controlled by OFDCR1
register. To write OFDCR2/OFDMNPLLOFF/OFDMNPLLON/OFDMXPLLOFF/OFDMXPLLON registers,
the write enable code "0xF9" should be set to OFDCR1 beforehand. To enable the oscillation frequency
detector, set "0xE4" to OFDCR2 after setting "0xF9" to OFDCR1. Since the oscillation frequency detection
is disabled after an external reset input, write "0xF9" to OFDCR1 and write "0xE4" to OFDCR2 register to
enable its function.
When the TMPM370 detects the out of frequency by lower and higher detection frequency setting regis-
ters, all I/Os become high impedance by reset. In case of PLLOFF, OFDMNPLLOFF and OFDMXPLLOFF
registers are valid for detection and the setting value of OFDMNPLLON/OFDMXPLLON registers are
ignored. In case of PLLON, OFDMNPLLON and OFDMXPLLON registers are valid for detection and the
setting value of OFDMNPLLOFF/OFDMXPLLOFF registers are ignored. By the oscillation frequency
detection reset, all I/Os except power supply pins, RESET, X1 and X2 become high impedance. If oscilla-
tion frequency detection reset is generated by detecting the stopping of high frequency, the internal circu-
ities such as registers hold the condition at the timing of oscillation stop. To initialize these internal
circuitries, an external re-starting of oscillation is needed.
Since all registers for oscillation frequency detector (OFDCR1/OFDCR2/OFDMNPLLOFF/OFDMN-
PLLON/ OFDMXPLLOFF/OFDMXPLLON) are not initialized by the reset generated from oscillation fre-
quency detector, the detection of oscillation is keeps its function during the reset period of oscillation
frequency detection. Therefore, if the oscillation frequency detection reset occurs, the reset is not
released unless the CPU clock resumes its normal frequency.
Note 1: The oscillation frequency detection reset is available only in NORMAL and IDLE modes. In STOP mode, the oscil-
lation frequency detection reset is disabled automatically.
Note 2: When the PLL is controlled (enabled or disabled) by the CGPLLSEL register, the OFD must be disabled before-
hand. If OFD reset is generated with PLL-ON, the detection frequency setting registers (OFDMNPLLON/OFDMX-
PLLON) are automatically switched over to OFDMNPLLOFF/OFDMXPLLOFF.
TMPM370 12-1 Oscillation Frequency Detector (OFD)

TMPM370
Detection Area
10MHzr
VDD [V] Harmonics
Subharmonics of 10MHz-10%
of 10MHz
5.5
4.5
5 5.5 9 10 11 18 20
fc [MHz]
(a) In case of PLLOFF
Detection Area
80MHzr
VDD [V] Harmonics
Subharmonics of 80MHz-10%
of 80MHz
5.5
4.5
40 44 72 80 88 144 160
fc [MHz]
(b) In case of PLLON
Figure 12-1 Detection frequency range (Initial value)
PLLON
PLLSEL
XEN
PLL Oscillation Frequency

fc Oscillation Detection Reset
X1 High Frequency Frequency
X2 Oscillator Detector
Note: When the PLL is controlled (enabled or disabled) by the CGPLLSEL register, the OFD must be disabled beforehand.
Figure 12-2 Oscillation Frequency Detector

TMPM370
12.2 Control
The oscillation frequency detection is controlled by oscillation frequency detection control register 2
(OFDCR2). The detection frequency is specified by lower/higher detection frequency setting registers
(OFDMNPLLOFF, OFDMNPLLON, OFDMXPLLOFF and OFDMXPLLON). Writing to OFDCR2/OFDMN-
PLLOFF/OFDMNPLLON/OFDMXPLLOFF/OFDMXPLLON is controlled by oscillation frequency control
register 1 (OFDCR1).
Oscillation frequency detection control register 1

31-8
OFDCR1 Bit Symbol -
(0x4004_0800) Read/Write R
After reset 0
7 6 5 4 3 2 1 0
Bit Symbol CLKWEN7 CLKWEN6 CLKWEN5 CLKWEN4 CLKWEN3 CLKWEN2 CLKWEN1 CLKWEN0
After reset 0 0 0 0 0 1 1 0
0x06: Disabling of writing to OFDCR2/OFDMNPLLOFF/OFDMNPLLON/OFDMXPLLOFF/

Function
OFDMXPLLON (Write disable code)
0xF9: Enabling of writing to OFDCR2/OFDMNPLLOFF/OFDMNPLLON/OFDMXPLLOFF/

OFDMXPLLON (Write enable code)
Others: Reserved (Note 1)
Note 1: Only "0x06" and "0xF9" is valid to OFDCR1. If other value than "0x06" and "0xF9" is written to OFDCR1, "0x06" is
written to OFDCR1 automatically.
Note 2: OFDCR1 is not initialized by an internal factor reset including oscillation frequency detection reset. To initialize this
registers, set the RESET pin (external factor reset) to the low level.
Oscillation frequency detection control register 2

31-8
OFDCR2 Bit Symbol -
After reset 0
7 6 5 4 3 2 1 0
Bit Symbol CLKSEN7 CLKSEN6 CLKSEN5 CLKSEN4 CLKSEN3 CLKSEN2 CLKSEN1 CLKSEN0
After reset 0 0 0 0 0 0 0 0
Function 0x00: Disabling of oscillation frequency detection
0xE4: Enabling of oscillation frequency detection
Others: Reserved (Note 1)
Note 1: Only "0x00" and "0xE4" is valid to OFDCR2. Writing other value than "0x00" and "0xE4" to OFDCR2 is ignored.
Note 2: Writing to OFDCR2 is protected by setting "0x06" to OFDCR1 but reading from OFDCR2 is always enabled with-
out setting of OFDCR1.
Note 3: OFDCR2 is not initialized by an internal factor reset including oscillation frequency detection reset. To initialize this
registers, set the RESET pin (external factor reset) to the low level.

TMPM370
Lower detection frequency setting register (In case of PLL OFF)

31-9 8
OFDMNPLLOFF Bit Symbol - OFDMNPLLOFF
After reset 0 0
7 6 5 4 3 2 1 0
Bit Symbol OFDMNPLLOFF
After reset 0 0 0 1 1 1 1 1
Lower detection frequency setting register (In case of PLL ON)

31-9 8
OFDMNPLLON Bit Symbol - OFDMNPLLON
After reset 0 0
7 6 5 4 3 2 1 0
Bit Symbol OFDMNPLLON
After reset 1 1 1 1 0 0 0 1
Higher detection frequency setting register (In case of PLL OFF)

31-9 8
OFDMXPLLOFF Bit Symbol - OFDMXPLLOFF
After reset 0 0
7 6 5 4 3 2 1 0
Bit Symbol OFDMXPLLOFF
After reset 0 0 1 1 0 1 1 1
Higher detection frequency setting register (In case of PLL ON)

31-9 8
OFDMXPLLON Bit Symbol - OFDMXPLLON
After reset 0 0
7 6 5 4 3 2 1 0
Bit Symbol OFDMXPLLON
After reset 1 1 0 0 0 0 0 0
Note 1: OFDMNPLLOFF, OFDMNPLLON, OFDMXPLLOFF and OFDMXPLLON can not be written when the oscillation frequency
detection circuit is enabled (OFDCR2="0xE4") or writing is disabled with OFDCR1="0x06". An attempt to write OFDMN-
PLLOFF, OFDMNPLLON, OFDMXPLLOFF and OFDMXPLLON can not complete a write operation.
Note 2: Writing to OFDMNPLLOFF, OFDMNPLLON, OFDMXPLLOFF and OFDMXPLLON is protected by setting "0x06" to
OFDCR1 but reading from OFDMNPLLOFF, OFDMNPLLON, OFDMXPLLOFF and OFDMXPLLON is always enabled
without setting of OFDCR1.
Note 3: Specify an appropriate value to OFDMNPLLOFF and OFDMXPLLOFF depending on the clock frequency to be used
under the condition of OFDMNPLLOFF<OFDMXPLLOFF. For how to calculate the value, refer to " 12.3.2 Setting the
Lower and Higher Frequency for Detection ".

TMPM370
Note 4: Specify an appropriate value to OFDMNPLLON and OFDMXPLLON depending on the clock frequency to be used under
the condition of OFDMNPLLON<OFDMXPLLON. For how to calculate the value, refer to " 12.3.2 Setting the Lower and
Higher Frequency for Detection ".
Note 5: OFDMNPLLOFF, OFDMNPLLON, OFDMXPLLOFF and OFDMXPLLON are not initialized by an internal factor reset
including oscillation frequency detection reset. To initialize these registers, set the RESET pin (external factor reset) to the
low level.
Note 6: OFDMNPLLOFF/OFDMXPLLOFF and OFDMNPLLON/OFDMXPLLON are automatically switched over by the setting of
PLLON.
12.3 Function
12.3.1 Enabling and Disabling the Oscillation Frequency Detection

Writing "0xE4" to OFDCR2 with OFDCR1="0xF9" enables the oscillation frequency detection, and
writing "0x00" to OFDCR2 with OFDCR1="0xF9" disables the oscillation frequency detection.
Setting "0xF9" to OFDCR1 enables writing to OFDCR2 and setting "0x06" to OFDCR1 disables
writing to OFDCR2. Reading from OFDCR2 is always enabled without setting of OFDCR1. OFDCR1
is initialized to "0x06" by external reset and OFDCR2 is initialized to "0x00" by external reset. How-
ever, OFDCR1 and OFDCR2 are not initialized by internal reset which are SYSRESETREQ reset,
watchdog timer reset and oscillation frequency detection reset.
Note:After writing data to OFDCR2, set "0x06" to OFDCR1 to protect OFDCR2 register.
When STOP mode is executed with OFDCR2=0xE4, the oscillation frequency detection is auto-
matically disabled. After releasing STOP and warming up period, the oscillation frequency detection
is enabled. The oscillation frequency detection is available only in NORMAL and IDLE mode. Table
12-1 shows the availability of oscillation frequency detector.
Table 12-1 Availability of oscillation frequency detector
Oscillation Frequency Detection All I/Os condition after Oscillation Frequency Detection RESET
Operating Mode
(OFDCR2=0xE4) (Except power supply, RESET, X1, X2 pins)
NORMAL Available High impedance
IDLE Available High impedance
STOP
Oscillation Frequency Detection is disabled automatically.
(Including warming up period)
RESET by oscillation frequency

Available High impedance
detection reset
RESET by internal reset (Note 1) Available High impedance
RESET by external reset Disable -
Note 1: Internal reset; Watchdog timer reset, SYSRESETREQ reset
Enabling by writting Enabling by writting

0xE4 to CLKSCR 0xE4 to CLKSCR
Disable Enable Disable Enable Disable Enable
VDD
High-frequency
clock
External RESET
input
Internal RESET
Oscillation Frequency
Detector control
External NORMAL or STOP mode NORMAL or Internal NORMAL or External NORMAL or
RESET IDLE mode including warming up IDLE mode RESET IDLE mode RESET IDLE mode
Figure 12-3 Availability of Oscillation Frequency Detection

TMPM370
12.3.2 Setting the Lower and Higher Frequency for Detection

The detection frequency is specified by OFDMNPLLOFF, OFDMNPLLON, OFDMXPLLOFF and
OFDMXPLLON registers. The relation between the setting value to these registers and the detection
frequency is shown in Table 12-2.
Table 12-2 High frequency and Setting value for detection frequency
Detection frequency Non detection frequency

High frequency Range Setting value Decimal (Hex)
range [MHz] range [MHz]
8MHz Lower ≤ 4.12 ≥ 7.76 OFDMNPLLOFF 24 (0x18)

(PLL OFF) Upper ≥ 15.52 ≤ 8.24 OFDMXPLLOFF 47 (0x2F)
10MHz Lower ≤ 5.15 ≥ 9.7 OFDMNPLLOFF 30 (0x1E)

(PLL OFF) Upper ≥ 19.4 ≤ 10.3 OFDMXPLLOFF 59 (0x3B)
64MHz Lower ≤ 32.96 ≥ 62.08 OFDMNPLLON 190 (0xBE)

(PLL ON) Upper ≥124.16 ≤ 65.92 OFDMXPLLON 379 (0x17B)
80MHz Lower ≤ 41.2 ≥ 77.6 OFDMNPLLON 238 (0xEE)

(PLL ON) Upper ≥ 155.2 ≤ 82.4 OFDMXPLLON 473 (0x1D9)
12.3.3 Oscillation Frequency Detection Reset

If the TMPM370 detects lower frequency specified by OFDMNPLLOFF/OFDMNPLLON or higher
frequency specified by OFDMXPLLOFF/CLKCMXPLLON, the oscillation frequency detector outputs
a reset signal for all I/Os.
a. When the high frequency oscillation becomes abnormal

When an abnormal (lower or higher) frequency oscillation continues for some period
(TOFD), the oscillation frequency detection reset is generated. By oscillation frequency
detection reset initializes all I/Os except power supply pins, RESET, X1 and X2 become
high impedance.
b. When the high frequency oscillation stops
When the high frequency oscillation stops for some period (TOFD), the oscillation fre-
quency detection reset is generated. By oscillation frequency detection reset initializes all I/
Os except power supply pins, RESET, X1 and X2 become high impedance. However, since
the internal circuitries such as CPU are initialized by a reset signal latched by high fre-
quency, the internal circuitries hold the state at the oscillation frequency detection.
When the oscillation resumes its normal frequency and continues for some period (TOFD), the
oscillation frequency detection reset is released.

TMPM370
When the high-frequency clock becomes abnormal

TOFD TOFD
High-frequency
clock
Stable Abnormal Stable
When normal oscillation continues

for some period, the oscillation
Oscillation Frequency frequency detection reset is released.
Detection Reset
Hi-Z
All I/Os
When the high-frequency clock stops

TOFD TOFD
High-frequency
clock
Stable Stop Stable
When normal oscillation continues

for some period, the oscillation
Oscillation Frequency frequency detection reset is released.
Detection Reset
Clocked RESET
Clocked reset is generated
Hi-Z after resuming of frequency.
All I/Os
CPU Address 0x0000_0004
Figure 12-4 Oscillation Frequency Detection Reset Timing

TMPM370

TMPM370
13. Power-on Reset Circuit (POR)

The power-on reset circuit generates a reset when the power is turned on. When the supply voltage is
lower than the detection voltage of the power-on reset circuit, a power-on reset signal is generated.
13.1 Configuration
The power-on reset circuit consists of a reference voltage generation circuit, a comparator and a
power-on counter.
The supply voltage divided by ladder resistor is compared with the voltage generated by the reference
voltage generation circuit by the comparator.
RVDD5
fosc
－
Power-on counter Power-on reset signal
＋
Power-on
Reference voltage detection signal
generation circuit
Figure 13-1 Power-on Reset Circuit

13.2 Function
When power supply voltage goes on, if the supply voltage is equal to or lower than the releasing voltage
of the power-on reset circuit, a power-on reset signal is generated. If the power supply voltage exceeds
the releasing voltage of the power-on reset circuit, power-on counter is activated and 215/fosc (s) later, a
power-on reset signal is released.
When power supply voltage goes down, if the supply voltage is equal to or lower than the detecting
voltage of the power-on reset circuit, a power-on reset signal is generated.
During the generation of power-on reset, the power-on counter circuit, the CPU and peripheral circuits
are reset.
When the power-on reset cuicuit is activated without an external reset input signal, the supply voltage
should be increased to the recommended operating voltage range (Note) within 3ms from the detection
of the releasing voltage of the power-on reset circuit. If the supply voltage does not reach the range, the
TMPM370 cannot operate properly.
(Note） When the supply voltage rises, until the supply voltage (at RVDD5 pin) reach the recommended operating
voltage range (4.5V through 5.5V) and 200μs passes by, the following condition should be satisfied; Port L (PL0
and PL1) is opened or the input voltage is within 0.5 volts.
TMPM370 13-1 Power-on Reset

TMPM370
Supply voltage
4.5V
tPORPW
VPORH
VPORL
Minimum voltage of
POR circuit
Power-on
detection signal
(Low-level enable)
tPORDT1 tPORDT2 tPORDT1
Power-on
counter
・・
tPWUP tPWUP
Power-on reset
signal
(Low-level enable)
Note 1: The power-on reset circuit may operate improperly, depending on fluctuations in the supply voltage. Refer to the electrical
characteristics and take them into consideration when designing equipment.
Note 2: If the supply voltage is lower than the minimum voltage of Power-on Reset circuit in which the circuit cannot operate
properly, the power-on reset signal becomes undefined value.
Figure 13-2 Operation Timing of Power-on Reset
Symbol Parameter Min Typ. Max Unit

VPORH Power-on Reset releasing voltage 2.8 3 3.2 V
VPORL Power-on Reset detection voltage 2.6 2.8 3.0 V
tPORDT1 Power-on Reset release response time 30 μs
tPORDT2 Power-on Reset detection response time 30 μs
tPORPW Power-on Reset minimum pulse width 45 μs
15
tPWUP Power-on counter (Note 2) 2 /fosc s
Note 1 : Since the power-on reset releasing voltage and the power-on reset detection voltage relatively change, the
detection voltage is never reversed.
Note 2 : 3.2ms at 10MHz.
For the details about Power-on sequence, refer to the chapter of “Electrical Characteristics”.
For the details about how to use external reset input, refer to “reset exceptions” in the chapter of
“Exceptions”.
TMPM370 13-2 Power-on Reset

TMPM370
14. Voltage Detection Circuit (VLTD)

The voltage detection circuit detects any decrease in the supply voltage and generates voltage
detection reset signals
Note: The voltage detection circuit may operate improperly, depending on fluctuations in the supply voltage (RVDD5). Refer to
the electrical characteristics and take them into consideration when designing equipment.
14.1 Configuration
The voltage detection circuit consists of a reference voltage generation circuit, a detection voltage
level selection circuit, a comparator and control registers.
The supply voltage (RVDD5) is divided by the ladder resistor and input to the detection voltage
selection circuit. The detection voltage selection circuit selects a voltage according to the specified
detection voltage (VDLVL), and the comparator compares it with the reference voltage.
When the supply voltage (RVDD5) becomes lower than the detection voltage (VDLVL), a voltage
detection reset signal is generated.
RVDD5
level selection circuit
Detection voltage
＋ Voltage detection reset
Reference voltage
generation circuit
VDLVL1
VDLVL0
VDEN
VDCR
Figure 14-1 Voltage Detection Circuit
TMPM370 14-1 Voltage Detection Circuit

TMPM370
14.2 Control
The voltage detection circuit is controlled by voltage detection control registers.
Voltage detection control register
VDCR 7 6 5 4 3 2 1 0
(0x4004_0900) Bit Symbol - - - - - VDLVL1 VDLVL0 VDEN
Read/Write R R R R R R/W R/W
After reset 0 0 0 0 0 00 0
00 : Reserved
01 : 4.1 ± 0.2 V
VDLVL[1:0] Selection for detection voltage
10 : 4.4 ± 0.2 V
11 : 4.6 ± 0.2 V
Enables/disables the operation of 0 : Disables the operation of voltage detection
VDEN
voltage detection 1 : Enables the operation of voltage detection
Note 1: VDCR is initialized by a power-on reset or an external reset input.
14.3 Function
The detection voltage can be selected by VDCR<VDLVL[1:0]>. Enabling/disabling the voltage detection
can be programmed by VDCR<VDEN>.
After the voltage detection operation is enabled, When the supply voltage (RVDD5) becomes lower
than the detection voltage <VDLVL[1:0]>, a voltage detection reset signal is generated.
14.3.1 Enabling/disabling the voltage detection operation

Setting VDCR<VDEN> to "1" enables the voltage detection operation. Setting it to "0" disables the
operation.
VDCR<VDEN> is cleared to "0" immediately after a power-on reset or a reset by an external reset input
is released.
Note: When the supply voltage (RVDD5) is lower than the detection voltage (VDLVL), setting VDCR<VDEN> to "1" generates
reset signal at the time.

TMPM370
14.3.2 Selecting the detection voltage level
Select a detection voltage at VDCR<VDLVL[1:0]>.
Power voltage tVDPW
VLTD
etection Voltage
POR
etection Voltage
Power-on reset
signal tVDEN
tVDEN
Voltage
detection tVDDT1 tVDDT2 tVDDT1
Software Software
Voltage detection
reset signal
Figure 14-2 Voltage Detection Timing
Symbol Parameter Min Typ. Max Unit

tVDEN Setup time after enabling voltage detection 40 μs
tVDDT1 Voltage detection response time 40 μs
tVDDT2 Voltage detection releasing time 40 μs
tVDPW Voltage detection minimum pulse width 45 μs

TMPM370
15. Vector Engine (VE)
15.1 Overview
15.1.1 Features
The Vector Engine provides the following features:
1) Executes basic tasks for vector control (coordinate conversion, phase conversion and SIN/COS
computation).
y Uses fixed-point format data.

Î No need for software to manage the decimal point alignment.
2) Enables interface (output control, trigger generation, input processing) with the motor control circuit
(PMD: Programmable Motor Driver) and AD converter (ADC).
y Converts computation results from fixed-point format to data format usable in the PMD.
y Generates timing data for interactive operation with the PMD and ADC.
y Converts AD conversion results into fixed-point format.
3) Calculates current, voltage and rotation speed by using normalized values with respect to their
maximum values in fixed-point format.
4) Implements PI control in current control.
5) Implements phase interpolation (integration of rotation speed). .
Current control
Id_ref PI control
Phase DUTYa
Vd Coordinate VA conversion DUTYb Output
Iq_ref PI control Vq conversion VB 2→3 DUTYc control PWM output
dq→AB SECTOR setting (PMD)
(SVM)
Trigger Sync. trigger

generation setting (PMD)
SIN/COS computation
θ SIN
Phase sin,cos
ω COS
interpolation
Vdc
Vdc
Input
Iu Current/voltage
Id Coordinate IA Phase processing
Id Iv detection (ADC)
Iq conversion IB conversion
Iq Iw
dq←AB 2←3
Figure 15-1 Block Diagram of Vector Control
TMPM370 15-1 Vector Engine (VE)

TMPM370
15.1.2 Key Specifications

1) Space vector conversion is used for 2-phase-to-3-phase conversion. Both 2-phase modulation and
3-phase modulation are supported.
2) ADC sampling timing can be generated for sensorless current detection. Current detection can be
performed by the 1-shunt, 3-shunt and 2-sensor methods.
3) In current control, PI control is implemented independently for d-axis and q-axis. It is also possible to
directly supply reference voltage information without using current control.
4) SIN/COS computations are performed with approximations using series values.

Phase information can be directly specified or computed from rotation speed by using phase
interpolation.
* For using the Vector Engine, the PMD must be set to the VE mode through the mode select register
(PMDnMODESEL).
It is also necessary to make appropriate settings in the ADC (enabling trigger and selecting AIN and
result registers to be used) for each synchronizing trigger from the PMD.

TMPM370
15.2 Configuration
Figure 15-2 shows the configuration of the Vector Engine.
Schedule management Scheduler Tasks

Schedule control Computation unit
Schedule 0 Current control
Schedule 1 Output voltage Decoder
ADC interrupt Start control
conversion
・
・ Output control
PWM interrupt Error detection ・ Trigger
Schedule 9 generation
Registers
Interrupt control Input processing

VE interrupt
Input voltage
conversion
ADC PMD
Figure 15-2 Configuration of the Vector Engine
15.2.1 Interaction among Vector Engine, Motor Control Circuit and A/D Converter
The Vector Engine can control two motors by interacting with two channels of motor control circuit (PMD)
and two units of AD converter (ADC). Channel 0 of the Vector Engine controls PMD channel 0, and channel
1 of the Vector Engine controls PMD channel 1.
As shown in Figure 15-3, the Vector Engine allows direct interaction with the PMD and ADC.
When the PMD0MODESEL register is set to the VE mode, the PMD channel 0 registers PMD0CMPU,
PMD0CMPV, PMD0CMPW, PMD0MDOUT, PMD0TRGCMP0, PMD0TRGCMP1 and PMD0TRGSEL are
switched to the Vector Engine registers VECMPU0, VECMPV0, VECMPW0, VEOUTCR0, VETRGCMP00,
VETRGCMP10 and VETRGSEL0 respectively. Likewise, the PMD channel 1 registers are switched to
Vector Engine registers VECMPU1, VECMPV1, VECMPW1, VEOUTCR1, VETRGCMP01, VETRGCMP11
and VETRGSEL1. In this case, these registers can only be controlled from the Vector Engine, and cannot
be written from the PMD. Other PMD registers have no read/write restrictions.
The ADC unit A registers ADAREG0, ADAREG1, ADAREG2, ADAREG3 and UVWISx0, UVWISx1,
UVWISx2, UVWISx3 which are the phase information specified by ADAPSETx are read into the Vector
Engine as the Vector Engine registers VEADREG0A, VEADREG1A, VEADREG2A, VEADREG3A,
VEPHNUM0A, VEPNNUM1A, VEPHNUM2A and VEPHNUM3A respectively. (These registers cannot be
accessed from the CPU.) Likewise, the ADC unit B registers are read into the Vector Engine as the Vector
Engine registers VEADREG0B, VEADREG1B, VEADREG2B, VEADREG3B, VEPHNUM0B, VEPNNUM1B,
VEPHNUM2B and VEPHNUM3B. (These registers cannot be accessed from the CPU.) These ADC
registers can be written and read from the ADC.
(x = 0 to 5)

TMPM370
Vector Engine PMD channel 0

MODESEL register
PWM generation Conduction
CMPU register MUX control
Channel 0 output tasks Buffer Port output
VEVCMPU0 register U0
V0
CMPV register MUX
Buffer W0
VEVCMPV0 register X0
Y0
CMPW register MUX
Buffer Z0
VEVCMPW0 register
MDOUT register MUX

Buffer
VEOUTCR0 register
EMGCR<EMGRS MUX Protection

control
VEEMGRS0 register
Trigger generation
TRGCMP0 register MUX
Buffer
VEVTRGCMP00 register
TRGCMP1 register MUX

Buffer
VEVTRGCMP10 register PMD0TRG0-5
MUX
TRGCMP2 register Buffer
TRGCMP2 register Buffer
TRGSEL register MUX
VEVTRGSEL0 register
Channel 1 output tasks PMD channel 1
Channel 0 input tasks AD unit A PMD1TRG0-5

Trigger
VEADREG0A ADREG0 register
detection
VEADREG1A ADREG1 register
VEADREG2A ADREG2 register Monitor

function
VEADREG3A ADREG3 register Analog input
VEPHNUM0A UVWISx0 AD conversion

AINx
VEPHNUM1A UVWISx1 ・
VEPHNUM2A UVWISx2 ・
・
VEPHNUM3A UVWISx3 (x=0 to 5)
Channel 1 input tasks ADC unit B
Figure 15-3 Interaction among Vector Engine, PMD and ADC

TMPM370
15.3 List of Registers
The Vector Engine registers are divided into the following three types:
VE control registers : Vector Engine control registers and temporary registers
Common registers : Registers common to both channels
Channel-specific registers : Computation data and control registers for each channel
Table 15-1 List of Registers (1) – VE Control Registers

Address Register Name Channel Description Read/Write
0x4005-0000 VEEN - VE enable/disable R/W
0x4005-0004 VECPURUNTRG - CPU start trigger selection W
0x4005-0008 VETASKAPP - Task selection R/W
0x4005-000C VEACTSCH - Operation schedule selection R/W
0x4005-0010 VEREPTIME - Schedule repeat count R/W
0x4005-0014 VETRGMODE - Start trigger mode R/W
0x4005-0018 VEERRINTEN - Error interrupt enable/disable R/W
0x4005-001C VECOMPEND - VE forced termination W
0x4005-0020 VEERRDET - Error detection R
0x4005-0024 VESCHTASKRUN - Schedule executing flag/executing task R
0x4005-0028 - - Reserved R
0x4005-002C VETMPREG0 - Temporary register R/W
0x4005-0030 VETMPREG1 - Temporary register R/W
0x4005-003C VETMPREG4 - Temporary register R/W
0x4005-01BC - - Reserved R
Table 15-2 List of Registers (2) – Common Registers

0x4005-0174 - - Reserved R/W
0x4005-0178 VETADC Common ADC conversion time (based on PWM clock) R/W

TMPM370
Table 15-3 List of Registers (3) – Channel-Specific Registers for Channel 0

0x4005-0044 VEMCTLF0 0 Status flags R/W
0x4005-0048 VEMODE0 0 Task control mode R/W
0x4005-004C VEFMODE0 0 Flow control R/W
1
0x4005-0050 VETPWM0 0 PWM period rate (PWM period [s] × maximum speed* × 2^16) R/W
1
0x4005-0054 VEOMEGA0 0 Rotation speed (speed [Hz]÷ maximum speed *1※ × 2^15) R/W
0x4005-0058 VETHETA0 0 Motor phase (motor phase [deg]/360 × 2^16) R/W
2
0x4005-005C VEIDREF0 0 d-axis reference value (current [A] ÷ maximum current* × 2^15) R/W
2
0x4005-0060 VEIQREF0 0 q-axis reference value (current [A] ÷ maximum current * × 2^15) R/W
3
0x4005-0064 VEVD0 0 d-axis voltage (voltage [V] ÷ maximum voltage * × 2^31) R/W
3
0x4005-0068 VEVQ0 0 q-axis voltage (voltage [V] ÷ maximum voltage * × 2^31) R/W
0x4005-006C VECIDKI0 0 Integral coefficient for PI control of d-axis R/W
0x4005-0070 VECIDKP0 0 Proportional coefficient for PI control of d-axis R/W
0x4005-0074 VECIQKI0 0 Integral coefficient for PI control of q-axis R/W
0x4005-0078 VECIQKP0 0 Proportional coefficient for PI control of q-axis R/W
0x4005-007C VEVDIH0 0 Upper 32 bits of integral term (VDI ) of d-axis voltage R/W
0x4005-0080 VEVDILH0 0 Lower 32 bits of integral term (VDI) of d-axis voltage R/W
0x4005-0084 VEVQIH0 0 Upper 32 bits of integral term (VQI) of q-axis voltage R/W
0x4005-0088 VEVQILH0 0 Lower 32 bits of integral term (VQI) of q-axis voltage R/W
0x4005-008C VEFPWMCHG0 0 Switching speed (for 2-phase modulation and shift PWM) R/W
0x4005-0090 VEMDPRD0 0 PWM period (to be set identically with PMD’s PWM period) R/W
0x4005-0094 VEMINPLS0 0 Minimum pulse width R/W
0x4005-0098 VETRGCRC0 0 Synchronizing trigger correction value R/W
0x4005-009C - - Reserved R/W
0x4005-00A0 VECOS0 0 Cosine value at THETA for output conversion (Q15 data) R/W
0x4005-00A4 VESIN0 0 Sine value at THETA for output conversion (Q15 data) R/W
0x4005-00A8 VECOSM0 0 Previous cosine value for input processing (Q15 data) R/W
0x4005-00AC VESINM0 0 Previous sine value for input processing (Q15 data) R/W
0x4005-00B0 VESECTOR0 0 Sector information (0-11) R/W
0x4005-00B4 VESECTORM0 0 Previous sector information for input processing (0-11) R/W
4
0x4005-00B8 VEIA00 0 AD conversion result of a-phase zero-current * R/W
4
0x4005-00BC VEIB00 0 AD conversion result of b-phase zero-current * R/W
4
0x4005-00C0 VEIC00 0 AD conversion result of c-phase zero-current * R/W
4
0x4005-00C4 VEIAADC0 0 AD conversion result of a-phase current * R/W
4
0x4005-00C8 VEIBADC0 0 AD conversion result of b-phase current * R/W
4
0x4005-00CC VEICADC0 0 AD conversion result of c-phase current * R/W
3
0x4005-00D0 VEVDC0 0 DC supply voltage (voltage [V] ÷ maximum voltage * × 2^15) R/W
2
0x4005-00D4 VEID0 0 d-axis current (current [A] ÷ maximum current * × 2^31) R/W
2
0x4005-00D8 VEIQ0 0 q-axis current (current [A] ÷ maximum current * × 2^31) R/W
0x4005-017C VECMPU0 0 PMD control: CMPU setting R/W
0x4005-0180 VECMPV0 0 PMD control: CMPV setting R/W
0x4005-0184 VECMPW0 0 PMD control: CMPW setting R/W
0x4005-0188 VEOUTCR0 0 PMD control: Output control (MDOUT) R/W
0x4005-018C VETRGCMP00 0 PMD control: TRGCMP0 setting R/W
0x4005-0190 VETRGCMP10 0 PMD control: TRGCMP1 setting R/W
0x4005-0194 VETRGSEL0 0 PMD control: Trigger selection R/W
0x4005-0198 VEEMGRS0 0 PMD control: EMG return (EMGCR[EMGRS]) W
*1) Maximum speed: Maximum rotation speed [Hz] that can be controlled or operated
*2) Maximum current: (Phase current value [A] which corresponds to 1 LSB of AD converter) × 2^11
*3) Maximum voltage: (Supply voltage (VDC) value [V] which corresponds to 1 LSB of AD conveter) × 2^12
*4) AD conversion results are stored in the upper 12 bits of each 16-bit register.

TMPM370
Table 15-4 List of Registers (4) – Channel-Specific Registers for Channel 1

0x4005-00DC VEMCTLF1 1 Status flags R/W
0x4005-00E0 VEMODE1 1 Task control mode R/W
0x4005-00E4 VEFMODE1 1 Flow control R/W
1
0x4005-00E8 VETPWM1 1 PWM period rate (PWM period [s] × maximum speed* × 2^16) R/W
※1
0x4005-00EC VEOMEGA1 1 Rotation speed (speed [Hz]÷ maximum speed *1 × 2^15) R/W
0x4005-00F0 VETHETA1 1 Motor phase (motor phase [deg]/360 × 2^16) R/W
2
0x4005-00F4 VEIDREF1 1 d-axis reference value (current [A] ÷ maximum current* × 2^15) R/W
2
0x4005-00F8 VEIQREF1 1 q-axis reference value (current [A] ÷ maximum current * × 2^15) R/W
3
0x4005-00FC VEVD1 1 d-axis voltage (voltage [V] ÷ maximum voltage * × 2^31) R/W
3
0x4005-0100 VEVQ1 1 q-axis voltage (voltage [V] ÷ maximum voltage * × 2^31) R/W
0x4005-0104 VECIDKI1 1 Integral coefficient for PI control of d-axis R/W
0x4005-0108 VECIDKP1 1 Proportional coefficient for PI control of d-axis R/W
0x4005-010C VECIQKI1 1 Integral coefficient for PI control of q-axis R/W
0x4005-0110 VECIQKP1 1 Proportional coefficient for PI control of q-axis R/W
0x4005-0114 VEVDIH1 1 Upper 32 bits of integral term (VDI ) of d-axis voltage R/W
0x4005-0118 VEVDILH1 1 Lower 32 bits of integral term (VDI) of d-axis voltage R/W
0x4005-011C VEVQIH1 1 Upper 32 bits of integral term (VQI) of q-axis voltage R/W
0x4005-0120 VEVQILH1 1 Lower 32 bits of integral term (VQ_I) of q-axis voltage R/W
0x4005-0124 VEFPWMCHG1 1 Switching speed (for 2-phase modulation and shift PWM) R/W
0x4005-0128 VEMDPRD1 1 PWM period (to be set identically with PMD’s PWM period) R/W
0x4005-012C VEMINPLS1 1 Minimum pulse width R/W
0x4005-0130 VETRGCRC1 1 Synchronizing trigger correction value R/W
0x4005-0134 - - Reserved R/W
0x4005-0138 VECOS1 1 Cosine value at THETA for output conversion (Q15 data) R/W
0x4005-013C VESIN1 1 Sine value at THETA for output conversion (Q15 data) R/W
0x4005-0140 VECOSM1 1 Previous cosine value for input processing (Q15 data) R/W
0x4005-0144 VESINM1 1 Previous sine value for input processing (Q15 data) R/W
0x4005-0148 VESECTOR1 1 Sector information (0-11) R/W
0x4005-014C VESECTORM1 1 Previous sector information for input processing (0-11) R/W
4
0x4005-0150 VEIAO1 1 AD conversion result of a-phase zero-current * R/W
4
0x4005-0154 VEIBO1 1 AD conversion result of b-phase zero-current * R/W
4
0x4005-0158 VEICO1 1 AD conversion result of c-phase zero-current * R/W
4
0x4005-015C VEIAADC1 1 AD conversion result of a-phase current * R/W
4
0x4005-0160 VEIBADC1 1 AD conversion result of b-phase current * R/W
4
0x4005-0164 VEICADC1 1 AD conversion result of c-phase current * R/W
3
0x4005-0168 VEVDC1 1 DC supply voltage (voltage [V] ÷ maximum voltage * × 2^15) R/W
2
0x4005-016C VEID1 1 d-axis current (current [A] ÷ maximum current * × 2^31) R/W
2
0x4005-0170 VEIQ1 1 q-axis current (current [A] ÷ maximum current * × 2^31) R/W
0x4005-019C VECMPU1 1 PMD control: CMPU setting R/W
0x4005-01A0 VECMPV1 1 PMD control: CMPV setting R/W
0x4005-01A4 VECMPW1 1 PMD control: CMPW setting R/W
0x4005-01A8 VEOUTCR1 1 PMD control: Output control (MDOUT) R/W
0x4005-01AC VETRGCMP01 1 PMD control: TRGCMP0 setting R/W
0x4005-01B0 VETRGCMP11 1 PMD control: TRGCMP1 setting R/W
0x4005-01B4 VETRGSEL1 1 PMD control: Trigger selection R/W
0x4005-01B8 VEEMGRS1 1 PMD control: EMG return (EMGCR[EMGRS]) W
*1) Maximum speed: Maximum rotation speed [Hz] that can be controlled or operated
*2) Maximum current: (Phase current value [A] which corresponds to 1 LSB of AD converter) × 2^11
*3) Maximum voltage: (Supply voltage (VDC) value [V] which corresponds to 1 LSB of AD conveter) × 2^12
*4) AD conversion results are stored in the upper 12 bits of each 16-bit register.

TMPM370
15.4 Description of Registers
15.4.1 VE Control Registers
15.4.1.1 VEEN Register

31 ・・・ 9 8
VEEN bit Symbol
After reset 0x00000000
Function －
7 ・・・ 3 2 1 0
bit Symbol VEIDLEN VEEN
After reset 000000 0 0
－ Operation in IDLE VE enable
mode 0: Disable
Function
0: Inactive 1: Enable
1: Active
<VEEN> Disables or enables the Vector Engine.

<VEIDLEN> Controls whether or not the clock is supplied to the Vector Engine in IDLE mode.
15.4.1.2 VECPURUNTRG Register

31 ・・・ 9 8
VECPURUNTRG bit Symbol
Function －
7 ・・・ 3 2 1 0
bit Symbol VCPURTB VCPURTA
Read/Write R W W
－ Channel 1 start Channel 0 start
command command
Function
0: － 0: －
1: Start 1: Start
<VCPURTA> Starts channel 0 by programming.

<VCPURTB> Starts channel 1 by programming.
* When “1” is written to these bits, it is cleared in the next cycle. These bits always read as 0.
* The task to be performed is determined by the settings of the ACTSCH and TASKAPP registers.
* If a channel under executing will be restarted, it must be terminated by COMPEND register
before a start command executed.

TMPM370
15.4.1.3 VETASKAPP Register

31 ・・・ 9 8
VETASKAPP bit Symbol
Function －
7 6 5 4 3 2 1 0
bit Symbol VTASKB VTASKA
Read/Write R/W R/W
After reset 0x0 0x0
Channel 1 task selection Channel 0 task selection
0x0: Output control 0x0: Output control
0x1: Trigger generation 0x1: Trigger generation
0x2: Input processing 0x2: Input processing
0x3: Input phase conversion 0x3: Input phase conversion
Function 0x4: Input coordinate axis conversion 0x4: Input coordinate axis conversion
0x5: Current control 0x5: Current control
0x6: SIN/COS computation 0x6: SIN/COS computation
0x7: Output coordinate axis conversion 0x7: Output coordinate axis conversion
0x8: Output phase conversion 0x8: Output phase conversion
0x9 -0xF: Reserved 0x9 -0xF: Reserved
<VTASKA> Specifies the task to be performed when channel 0 is started by programming.

<VTASKB> Specifies the task to be performed when channel 1 is started by programming.
* Only those tasks that are included in schedules can be specified.
15.4.1.4 VEACTSCH Register

31 ・・・ 9 8
VEACTSCH bit Symbol
(0x4005_000C) Read/Write R
Function －
7 6 5 4 3 2 1 0
bit Symbol VACTB VACTA
Read/Write R/W R/W
After reset 0x0 0x0
Channel 1 schedule Channel 0 schedule
0x0: Individual task execution 0x0: Individual task execution
0x1: Schedule 1 0x1: Schedule 1
Function
Other: Reserved Other: Reserved
<VACTA> Specifies an individual task execution or a schedule for channel 0.

<VACTB> Specifies an individual task execution or a schedule for channel 1.

TMPM370
15.4.1.5 VEREPTIME Register

31 ・・・ 9 8
VEREPTIME bit Symbol
Function －
7 6 5 4 3 2 1 0
bit Symbol VREPB VREPA
Read/Write R/W R/W
After reset 0x0 0x0
Channel 1 repeat count Channel 0 repeat count
0: Do not execute schedule 0: Do not execute schedule
Function
1-15: Execute schedule a specified number of 1-15: Execute schedule a specified number of
times times
<VREPA> Specifies the repeat times a schedule is to be executed in channel 0.

<VREPB> Specifies the repeat times a schedule is to be executed in channel 1.
* When “0” is set, no schedule is executed.
15.4.1.6 VETRGMODE Register

31 ・・・ 9 8
VETRGMODE bit Symbol
Function －
7 6 5 4 3 2 1 0
bit Symbol VTRGB VTRGA
After reset 0x0 00 00
－ Channel 1 trigger mode Channel 0 trigger mode
00: Ignore both INTB0 00: Ignore both INTA0
(unit A) and INTB1 (unit A) and INTA1
(unit B) (unit B)
01: Start by INTB0 (unit A) 01: Start by INTA0 (unit A)
Function
10: Start by INTB1 (unit 10: Start by INTA1 (unit B)
B) 11: Start when both
11: Start when both INTA0 (unit A) and
INTB0 (unit A) and INTA1 (unit B) occur
INTB1 (unit B) occur
<VTRGA> Specifies the AD conversion end interrupt that triggers input processing in channel 0.
<VTRGB> Specifies the AD conversion end interrupt that triggers input processing in channel 1.

TMPM370
15.4.1.7 VEERRINTEN Register

31 ・・・ 9 8
VEERRINTEN bit Symbol
Function －
7 ・・・ 3 2 1 0
bit Symbol VERRENB VERRENA
－ Channel 1 error Channel 0 error
interrupt enable interrupt enable
Function
0: Disable 0: Disable
1: Enable 1: Enable
<VERRENA> Enables or disables the error detection interrupt in channel 0.

<VERRENB> Enables or disables the error detection interrupt in channel 1.
15.4.1.8 VECOMPEND Register

31 ・・・ 9 8
VECOMPEND bit Symbol
Function －
7 ・・・ 3 2 1 0
bit Symbol VCENDB VCENDA
Read/Write R W W
－ Channel 1 forced Channel 0 forced
termination termination
Function
0: － 0:
1: Terminate 1: Terminate
<VCENDA> Forcefully terminates the currently executing schedule in channel 0.

<VCENDB> Forcefully terminates the currently executing schedule in channel 1.
* When “1” is written to these bits, it is cleared in the next cycle. These bits always read as "0”.

TMPM370
15.4.1.9 VEERRDET Register

31 ・・・ 9 8
VEERRDET bit Symbol
Function －
7 ・・・ 3 2 1 0
bit Symbol VERRDB VERRDA
Read/Write R R R
－ Channel 1 error flag Channel 0 error flag
Function 0: No error detected 0: No error detected
1: Error detected 1: Error detected
<VERRDA> Channel 0 error flag

<VERRDB> Channel 1 error flag
The error flags are set when a PWM interrupt is detected during execution of a schedule (excluding
standby periods waiting for a start trigger).
* The error flags are cleared by a read of this register.
15.4.1.10 VESCHTASKRUN Register

31 ・・・ 17 16
VESCHTASKRUN bit Symbol
After reset 0x0000
Function －
15 ・・・ 11 10
bit Symbol
Read/Write R
After reset 000000
Function －
9 8 7 6 5 4 3 2 1 0
bit Symbol VRTASKB VRSCHB VRTASKA VRSCHA
Read/Write R R R R
After reset 0x0 0 0x0 0
Task executing in channel 1 Channel 1 Task executing in channel 0 Channel 0
0x0: Output control schedule 0x0: Output control schedule
0x1: Trigger generation status 0x1: Trigger generation status
0x2: Input processing 0x2: Input processing 0: Not
0x3: Input phase conversion 0: Not 0x3: Input phase conversion executing
0x4: Input coordinate axis conversion executing 0x4: Input coordinate axis 1:
Function 0x5: Current control 1: conversion Executing
0x6: SIN/COS computation Executing 0x5: Current control
0x7: Output coordinate axis 0x6: SIN/COS computation
conversion 0x7: Output coordinate axis
0x8: Output phase conversion conversion
0x9 -0xF: Reserved 0x8: Output phase conversion
0x9-0xF: Reserved
<VRSCHA> Schedule execution status in channel 0

<VRTASKA> Task Number currently executing in channel 0
<VRSCHB> Schedule execution status in channel 1
<VRTASKB> Task Number currently executing in channel 1

TMPM370
15.4.1.11 Temporary Registers

31 ・・・ 1 0
VETMPREG0 bit Symbol TMPREG0
Function
31 ・・・ 1 0
Function
31 ・・・ 1 0
Function
31 ・・・ 1 0
Function
31 ・・・ 1 0
Function
31 ・・・ 1 0
Function
<TMPREG0> Temporary register 0


TMPM370
15.4.2 Common Registers
15.4.2.1 VETADC Register

31 ・・・ 17 16
VETADC bit Symbol
After reset 0x0000
Function －
15 ・・・ 1 0
bit Symbol TADC
Read/Write R/W
After reset 0x0000
ADC conversion time
Function
0x0000-0xFFFF
<TADC> The value to be set is:

ADC conversion time [s] ÷ PWM counter clock frequency [s]
* This register is effective when the 1-shunt current detection mode is selected and PWM shift is
enabled.

TMPM370
15.4.3 Channel-Specific Registers
15.4.3.1 VEMODE Register

31 ・・・ 9 8
VEMODE0 bit Symbol
VEMODE1 After reset 0x000000
(0x4005_00E0) Function －
7 6 5 4 3 2 1 0
bit Symbol － OCRMD ZIEN PVIEN
Read/Write R/W R/W R/W R/W
After reset 0 00 0 0
Write as ‘0’ Output control Zero- Phase
00: Output OFF current interpolation
01: Output enable detection 0: Disable
Function
10: Reserved 0: Disable 1: Enable
11: Output OFF and 1: Enable
EMG return
The upper and lower register names correspond to channel 0 and channel 1 respectively.
<PVIEN> Enables or disables phase interpolation.

<ZIEN> Enables or disables zero-current detection.
<OCRMD> Controls output operation (output OFF, output enable or EMG return).

TMPM370
15.4.3.2 VEFMODE Register

31 ・・・ 17 16
VEFMODE0 bit Symbol
VEFMODE1 After reset 0x0000
15 14 13 12 11 10 9 8
bit Symbol － MREGDIS ―
Read/Write R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
Write as ‘0’ Keep the Write as ‘0’
previous
value of
SIN/COS/S
Function
ECTOR
0: effective
1:no_effec
tive
7 6 5 4 3 2 1 0
bit Symbol ADCSEL － PMDSEL IDMODE SPWMEN C2PEN
Read/Write R/W R/W R/W R/W R/W R/W
ADC unit Write as ‘0’ PMD Current detection mode PWM shift Modulation
00: Unit A channel 00: 3-shunt enable mode
01: Unit B 0: Channel 01: 2-sensor 0: Disable 0: 3-phase
Function 10: Unit A,B 0 10: 1-shunt (for up 1: Enable modulation
11: Unit A,B 1: Channel count PMDTRG) 1: 2-phase
1 11: 1-shunt (for down modulation
count PMDTRG)
<C2PEN>: Selects 3-phase or 2-phase modulation.

<SPWMEN>: Enables or disables PWM shift.
<IDMODE>: Selects the 3-shunt, 2-sensor or 1-shunt current detection mode.
When the 1-shunt mode is used, the acceptable PMDTRG is as follows.
VEFMODE0 VEFMODE1 PMD0TRGCR PMD0TRGCR PMD1TRGCR PMD1TRGCR
<IDMODE> <IDMODE> <TRG0MD> <TRG1MD> <TRG0MD> <TRG1MD>
10 - 010 (up-count) 010 (up-count) - -
10 - 101 (carrier bottom) 010 (up-count) - -
11 - 001 (down-count) 001 (down-count) - -
11 - 001 (down-count) 101 (carrier bottom) - -
- 10 - - 010 (up-count) 010 (up-count)
- 10 - - 101 (carrier bottom) 010 (up-count)
- 11 - - 001 (down-count) 001 (down-count)
- 11 - - 001 (down-count) 101 (carrier bottom)
<PMDSEL>: Selects PMD channel 0 or channel 1.

* Select PMD channel 0 when Vector Engine channel 0 is used .
Select PMD channel 1 when Vector Engine channel 1 is used .
<ADCSEL>: Selects the ADC unit to be used.
* Select unit A or unit A/unit B when Vector Engine channel 0 is used .
Select unit B or unit A/unit B when Vector Engine channel 1 is used
＜MREGDIS＞: Keep or Not_keep the previous value of SIN/COS/SECTOR.
* In case of no_effective, SINM=SIN,COSM=COS,SECTORM=SECTOR.

TMPM370
15.4.3.3 VETPWM Register

31 ・・・ 17 16
VETPWM0 bit Symbol
VETPWM1 After reset 0x0000
15 ・・・ 1 0
bit Symbol TPWM
Read/Write R/W
After reset 0x0000
PWM period rate
Function
0x0000 to 0xFFFF
<TPWM> Set a PWM period rate (it is valid when the phase interpolation is enabled,
16-bit fixed-point data: 0.0 to 1.0) as follows:
PWM period [s] × Max_Hz×2^16
* Max_Hz: Maximum rotation speed
* It indicates a ratio between PWM frequency and maximum rotation speed.
15.4.3.4 VEOMEGA Register

31 ・・・ 17 16
VEOMEGA0 bit Symbol
VEOMEGA1 After reset 0x0000
(0x4005_00EC) Function －
15 ・・・ 1 0
bit Symbol OMEGA
Read/Write R/W
After reset 0x0000
Rotation speed
Function
0x0000 to 0xFFFF
<OMEGA> Set a rotation speed (16-bit fixed-point data: -1.0 to 1.0) as follows:
Rotation speed [Hz] ÷ Max_Hz×2^15
* Max_Hz: Maximum rotation speed [Hz]
15.4.3.5 VETHETA Register

31 ・・・ 17 16
VETHETA0 bit Symbol
VETHETA1 After reset 0x0000
(0x4005_00F0) Function －
15 ・・・ 1 0
bit Symbol THETA
Read/Write R/W
After reset 0x0000
Function Phase data
<THETA> Set phase data (16-bit fixed-point data: 0.0 to 1.0) as follows:
Phase [deg] ÷ 360 × 2^16

TMPM370
15.4.3.6 VESIN/COS Registers

31 ・・・ 17 16
VECOS0 bit Symbol
(0x4005_00A0) Read/Write R
VECOS1 After reset 0x0000
(0x4005_0138) Function －
15 ・・・ 1 0
bit Symbol COS
Read/Write R/W
After reset 0x0000
Function Cosine value: 0x0000-0xFFFF
31 ・・・ 17 16
VESIN0 bit Symbol
VESIN1 After reset 0x0000
(0x4005_013C) Function －
15 ・・・ 1 0
bit Symbol SIN
Read/Write R/W
After reset 0x0000
Function Sine value: 0x0000-0xFFFF
31 ・・・ 17 16
VECOSM0 bit Symbol
VECOSM1 After reset 0x0000
(0x4005_0140) Function －
15 ・・・ 1 0
bit Symbol COSM
Read/Write R/W
After reset 0x0000
Function Cosine value (previous value): 0x0000-0xFFFF
31 ・・・ 17 16
VESINM0 bit Symbol
(0x4005_00AC) Read/Write R
VESINM1 After reset 0x0000
(0x4005_0144) Function －
15 ・・・ 1 0
bit Symbol SINM
Read/Write R/W
After reset 0x0000
Function Sine value (previous value): 0x0000-0xFFFF
<COS> Cosine value based on the THETA value (16-bit fixed-point data: -1.0 to 1.0)
<SIN> Sine value based on the THETA value (16-bit fixed-point data: -1.0 to 1.0)
<COSM> Previous value of the COS register
<SINM> Previous value of the SIN register

TMPM370
15.4.3.7 dq Current Reference Registers

31 ・・・ 17 16
VEIDREF0 bit Symbol
VEIDREF1 After reset 0x0000
15 ・・・ 1 0
bit Symbol IDREF
Read/Write R/W
After reset 0x0000
Function Reference value of d-axis current: 0x0000 to 0xFFFF
31 ・・・ 17 16
VEIQREF0 bit Symbol
VEIQREF1 After reset 0x0000
15 ・・・ 1 0
bit Symbol IQREF
Read/Write R/W
After reset 0x0000
Function Reference value of q-axis current: 0x0000 to 0xFFFF
<ID_REF> Reference value of d-axis current (16-bit fixed-point data: -1.0 to 1.0)
<IQ_REF> Reference value of q-axis current (16-bit fixed-point data: -1.0 to 1.0)
The value to be set is:

Axis current reference [A] ÷ Max_I×2^15
* Max_I: (Phase current value [A] which corresponds to 1 LSB of ADC) × 2^11
15.4.3.8 dq Voltage Registers

31 ・・・ 1 0
VEVD0 bit Symbol VD
VEVD1 After reset 0x00000000
(0x4005_00FC) Function d-axis voltage: 0x00000000-0xFFFFFFFF
31 ・・・ 1 0
VEVQ0 bit Symbol VQ
VEVQ1 After reset 0x00000000
(0x4005_0100) Function q-axis voltage: 0x00000000-0xFFFFFFFF
<VD> d-axis voltage (32-bit fixed-point data: -1.0 to 1.0)

<VQ> q-axis voltage (32-bit fixed-point data: -1.0 to 1.0)
The value to be set is as follows:

Axis voltage ÷ Max_V×2^31
* Max_V: (Supply voltage (VDC) value [V] which corresponds to 1 LSB of ADC) × 2^12

TMPM370
15.4.3.9 PI Control Coefficient Registers

31 ・・・ 17 16
VECIDKI0 bit Symbol
VECIDKI1 After reset 0x0000
(0x4005_0104) Function －
15 ・・・ 1 0
bit Symbol CIDKI
Read/Write R/W
After reset 0x0000
Function Integral coefficient for PI control of d-axis: 0x0000-0xFFFF
31 ・・・ 17 16
VECIDKP0 bit Symbol
VECIDKP1 After reset 0x0000
(0x4005_0108) Function －
15 ・・・ 1 0
bit Symbol CIDKP
Read/Write R/W
After reset 0x0000
Function Proportional coefficient for PI control of d-axis: 0x0000-0xFFFF
31 ・・・ 17 16
VECIQKI0 bit Symbol
VECIQKI1 After reset 0x0000
15 ・・・ 1 0
bit Symbol CIQKI
Read/Write R/W
After reset 0x0000
Function Integral coefficient for PI control of q-axis: 0x0000-0xFFFF
31 ・・・ 17 16
VECIQKP0 bit Symbol
VECIQKP1 After reset 0x0000
(0x4005_0110) Function －
15 ・・・ 1 0
bit Symbol CIQKP
Read/Write R/W
After reset 0x0000
Function Proportional coefficient for PI control of q-axis: 0x0000-0xFFFF
<CIDKI> Integral coefficient for PI control of d-axis

<CIDKP> Proportional coefficient for PI control of d-axis
<CIQKI> Integral coefficient for PI control of q-axis
<CIQKP> Proportional coefficient for PI control of q-axis

TMPM370
15.4.3.10 PI Control Integral Term Registers

31 ・・・ 1 0
VEVDIH0 bit Symbol VDIH
VEVD_H1 After reset 0x00000000
(0x4005_0114) Function Upper 32 bits of VDI
31 ・・・ 17 16
VEVDILH0 bit Symbol VDILH
VEVDILH1 After reset 0x0000
(0x4005_0118) Function
15 ・・・ 1 0
bit Symbol
Read/Write R
After reset 0x0000
Function －
31 ・・・ 1 0
VEVQIH0 bit Symbol VQIH
VEVQIH1 After reset 0x00000000
(0x4005_011C) Function
31 ・・・ 17 16
VEVQILH0 bit Symbol VQILH
VEVQILH1 After reset 0x0000
(0x4005_0120) Function
15 ・・・ 1 0
bit Symbol
Read/Write R
After reset 0x0000
Function －
<VDIH> Upper 32 bits of the integral term (VDI) for PI control of d-axis
<VDILH> Bit 31 to 16 of the integral term (VDI) for PI control of d-axis
VDI: 64-bit fixed-point data with 63 fractional bits (-1.0 to 1.0)
<VQIH> Upper 32 bits of the integral term (VQI) for PI control of q-axis
<VQILH> Bit 31 to 16 of the integral term (VQI) for PI control of q-axis
VQI: 64-bit fixed-point data with 63 fractional bits (-1.0 to 1.0)

TMPM370
15.4.3.11 VEMCTLF Register

31 ・・・ 9 8
VEMCTLF0 bit Symbol
VEMCTLF1 After reset 0x000000
(0x4005_00DC) Function －
7 6 5 4 3 2 1 0
bit Symbol － - PLSLFM PLSLF - LVTF LAVFM LAVF
After reset 0 0 0 0 0 0 0 0
Write as ‘0’ Write as ‘0’ Previous Disparity Write as ‘0’ Supply Previous Low-speed
value of of pulse voltage LAVF value flag
PLSLFM width lower flag 0:
Function
small flag High-speed
1:
Low-speed
<LAVF> Low-speed flag OMEGA ≥ FPWMCHG case = 0

OMEGA < FPWMCHG case =1
<LAVFM> Previous LAVF value
<LVTF> Supply voltage lower flag VDC≧0x0100(1/128) case =0,
VDC＜0x0100(1/128) case =1
＜PLSLF> Minimum disparity of pulse width≧MINPLS case =0
Minimum disparity of pulse width＜MINPLS case =1
<PLSLFM> Previous value of PLSLF
15.4.3.12 VEFPWMCHG Register

31 ・・・ 17 16
VEFPWMCHG0 bit Symbol
VEFPWMCHG1 After reset 0x0000
(0x4005_0124) Function －
15 ・・・１０
bit Symbol FPWMCHG
Read/Write R/W
After reset 0x0000
Function Rotation speed when PWM shift is enabled
<FPWMCHG> Rortation speed when PWM shift is enabled. The value to be set is:
Rortation speed [Hz] ÷ Max_Hz×2^15
* Max_Hz: Maximum rotation speed [Hz]

TMPM370
15.4.3.13 PWM Period Register

31 ・・・ 17 16
VEVMDPRD0 bit Symbol
VEVMDPRD1 After reset 0x0000
(0x4005_0128) Function －
15 ・・・ 1 0
bit Symbol VMDPRD
Read/Write R/W
After reset 0x0000
Function PWM period
<VMDPRD> PWM period. Set the value of the PMD’s MDPRD register.
15.4.3.14 VEMINPLS Register

31 ・・・ 17 16
VEMINPLS0 bit Symbol
VEMINPLS1 After reset 0x0000
15 ・・・ 1 0
bit Symbol MINPLS
Read/Write R/W
After reset 0x0000
Function Minimum disparity of pulse width
<MINPLS> Set the minimum disparity of pulse width among the duty of VECMPU, VECMPV,
VECMPW.
Disparity of pulse width [s] ÷ PWM counter clock period [s]

TMPM370
15.4.3.15 Sector Registers

31 ・・・ 9 8
VESECTOR0 bit Symbol
(0x4005_00B0) Read/Write R
VESECTOR1 After reset 0x000000
(0x4005_0148) Function －
7 6 5 4 3 2 1 0
bit Symbol SECTOR
Read/Write R R/W
After reset 0x0 0x0
－ Sector information
Function
0x0-0xF:
31 ・・・ 9 8
VESECTORM0 bit Symbol
VESECTORM1 Function －
(0x4005_014C) After reset 0x000000
7 6 5 4 3 2 1 0
bit Symbol SECTORM
Read/Write R R/W
After reset 0x0 0x0
－ Sector information
Function
0x0-0xF:
<SECTOR> Sector information. Indicates the rotation position at the time of output by 12 sectors
each having 30 degrees.
<SECTORM> Previous sector information. Used in input processing.

TMPM370
15.4.3.16 Zero-Current Registers

31 ・・・ 17 16
VEIA00 bit Symbol
VEIA01 After reset 0x0000
(0x4005_0150) Function －
15 ・・・ 1 0
bit Symbol IA0
Read/Write R/W
After reset 0x0000
Function AD conversion result of U-phase at zero-current
31 ・・・ 17 16
VEIB00 bit Symbol
(0x4005_00BC) Read/Write R
VEIB01 After reset 0x0000
(0x4005_0154) Function －
15 ・・・ 1 0
bit Symbol IB0
Read/Write R/W
After reset 0x0000
Function AD conversion result of V-phase at zero-current
31 ・・・ 17 16
VEIC00 bit Symbol
(0x4005_00C0) Read/Write R
VEIC01 After reset 0x0000
(0x4005_0158) Function －
15 ・・・ 1 0
bit Symbol IC0
Read/Write R/W
After reset 0x0000
Function AD conversion result of W-phase at zero-current
<IA0> Stores the AD conversion result of U-phase current when the motor is at stop.
<IB0> Stores the AD conversion result of V-phase current when the motor is at stop
<IC0> Stores the AD conversion result of W-phase current when the motor is at stop
* When the zero-current detection is enabled, AD conversion results are automatically

stored to these registers.
* AD conversion results are stored in the 15--4 bits, with the 3--0 bits always “0”.

TMPM370
15.4.3.17 Current ADC Result Registers

31 ・・・ 17 16
VEIAADC0 bit Symbol
VEIAADC1 After reset 0x0000
15 ・・・ 1 0
bit Symbol IAADC
Read/Write R/W
After reset 0x0000
Function AD conversion result of U-phase current : 0x0000-0xFFFF
31 ・・・ 17 16
VEIBADC0 bit Symbol
VEIBADC1 After reset 0x0000
(0x4005_0160) Function －
15 ・・・ 1 0
bit Symbol IBADC
Read/Write R/W
After reset 0x0000
Function AD conversion result of V-phase current: 0x0000-0xFFFF
31 ・・・ 17 16
VEICADC0 bit Symbol
(0x4005_00CC) Read/Write R
VEICADC1 After reset 0x0000
(0x4005_0164) Function －
15 ・・・ 1 0
bit Symbol ICADC
Read/Write R/W
After reset 0x0000
Function AD conversion result of W-phase current: 0x0000-0xFFFF
<IAADC> Stores the AD conversion result of U-phase current.

<IBADC> Stores the AD conversion result of V-phase current.
<ICADC> Stores the AD conversion result of W-phase current.
* AD conversion results are stored in the 15--4 bits, with the 3--0 bits always “0”.

TMPM370
15.4.3.18 Supply Voltage Register

31 ・・・ 17 16
VEVDC0 bit Symbol
(0x4005_00D0) Read/Write R
VEVDC1 After reset 0x0000
(0x4005_0168) Function －
15 ・・・ 1 0
bit Symbol VDC
Read/Write R/W
After reset 0x0000
Function Supply voltage: 0x0000-0xFFFF
<VDC> Supply voltage (16-bit fixed-point data: 0 to 1.0)

The actual voltage value is:
VDC value ÷ Max_V value × 2^15
* Max_V: (Supply voltage (VDC) value [V] which corresponds to 1 LSB of ADC) × 2^12
15.4.3.19 dq Current Registers

31 ・・・ 1 0
VEID0 bit Symbol ID
(0x4005_00D4) Read/Write R/W
VEID1 After reset 0x00000000
(0x4005_016C) Function d-axis current: 0x00000000-0xFFFFFFFF
31 ・・・ 1 0
VEIQ0 bit Symbol IQ
(0x4005_00D8) Read/Write R/W
VEIQ1 After reset 0x00000000
(0x4005_0170) Function q-axis current: 0x00000000-0xFFFFFFFF
<ID> d-axis current (32-bit fixed-point data: -1.0 to 1.0)

<IQ> q-axis current (32-bit fixed-point data: -1.0 to 1.0)
The actual current value is:

ID (or IQ) value ÷ Max_I value x 2^31
* Max_I: (Phase current value [A] which corresponds to 1 LSB of ADC) × 2^11

TMPM370
15.4.3.20 PWM Duty Register

31 ・・・ 17 16
VECMPU0 bit Symbol
VECMPU1 After reset 0x0000
15 ・・・ 1 0
bit Symbol VCMPU
Read/Write R/W
After reset 0x0000
Function PWM pulse width of U-phase: 0-0xFFFF
31 ・・・ 17 16
VECMPV0 bit Symbol
VECMPV1 After reset 0x0000
(0x4005_01A0) Function －
15 ・・・ 1 0
bit Symbol VCMPV
Read/Write R/W
After reset 0x0000
Function PWM pulse width of V-phase: 0-0xFFFF
31 ・・・ 17 16
VECMPW0 bit Symbol
VECMPW1 After reset 0x0000
15 ・・・ 1 0
bit Symbol VCMPW
Read/Write R/W
After reset 0x0000
Function PWM pulse width of W-phase: 0-0xFFFF
<VCMPU> PMD setting: PWM setting of U-phase

<VCMPV> PMD setting: PWM setting of V-phase
<VCMPW> PMD setting: PWM setting of W-phase

TMPM370
15.4.3.21 6-Phase Output Control Register

31 ・・・ 17 16
VEOUTCR0 bit Symbol
VEOUTCR1 After reset 0x0000
15 14 13 12 11 10 9 8
bit Symbol WPWM
Read/Write R R/W
After reset 0000000 0
－ PWM of
W-phase
0: ON/OFF
Function
output
1: PWM
output
7 6 5 4 3 2 1 0
bit Symbol VPWM UPWM WOC VOC UOC
Read/Write R/W R/W R/W R/W R/W
PWM of PWM of Output control of Output control of Output control of
V-phase U-phase W-phase V-phase U-phase
(*) (*) (*)
0: ON/OFF 0: ON/OFF 00:W0 OFF, Z0 OFF 00: V0 OFF, Y0 OFF 00: U0 OFF, X0 OFF
output output 01: W0 ON, Z0 OFF 01: V0 ON, Y0 OFF 01: U0 ON, X0 OFF
Function
1: PWM 1: PWM 10: W0 OFF, Z0 ON 10: V0 OFF, Y0 ON 11: 10: U0 OFF, X0 ON
output output 11: W0 ON, Z0 ON V0 ON, Y0 ON 11: U0 ON, X0 ON
*W0 and Z0 are both *V0 and Y0 are both *U0 and X0 are both
ON when WPWM=1. ON when VPWM=1. ON when UPWM=1.
<UPWM>, <U0C> PMD setting: Output control of U-phase (U0,X0)
Setting Output
UPWM U0C U0 X0
0 00 OFF output OFF output
1 00 PWMU PWMU
inverted output output
1 11 PWMU PWMU
output inverted output
*The table shows only those combinations that are used in the VE.
<VPWM>,<V0C> PMD setting: Output control of V-phase (V0,Y0)
Setting Output
VPWM V0C V0 Y0
1 00 PWMV PWMV
1 11 PWMV PWMV
*The table shows only those combinations that are used in the VE.
<WPWM>,<W0C> PMD setting: Output control of W-phase (W0,Z0)
Setting Output
WPWM W0C W0 Z0
1 00 PWMW PWMW
1 11 PWMW PWMW
* The table shows only those combinations that are used in the VE.

TMPM370
15.4.3.22 VETRGCRC Register

31 ・・・ 17 16
VETRGCRC0 bit Symbol
VETRGCRC1 After reset 0x0000
(0x4005_0130) Function －
15 ・・・ 1 0
bit Symbol TRGCRC
Read/Write R/W
After reset 0x0000
Function Trigger correction
<TRGCRC>: Used to correct the synchronizing trigger timing. The value to be set is:
Correction time [s] ÷ PWM counter clock frequency [s]
15.4.3.23 VETRGCMP Register

31 ・・・ 17 16
VETRGCMP00 bit Symbol
VETRGCMP01 After reset 0x0000
(0x4005_01AC) Function －
15 ・・・ 1 0
bit Symbol VTRGCMP0
Read/Write R/W
After reset 0x0000
Trigger timing setting
0x0000: Prohibited
Function
0x0001 to (MDPRD value -1): Trigger timing
MDPRD value to 0xFFFF: Prohibited
31 ・・・ 17 16
VETRGCMP10 bit Symbol
VETRGCMP11 After reset 0x0000
(0x4005_01B0) Function －
15 ・・・ 1 0
bit Symbol VTRGCMP1
Read/Write R/W
After reset 0x0000
Trigger timing setting
0x0000:Prohibited
Function
0x0001 to (MDPRD value-1): Trigger timing
MDPRD value to 0xFFFF: Prohibited
<VTRGCMP0> PMD setting: Specifies the trigger timing for sampling ADC in synchronization with
PMD.
<VTRGCMP1> PMD setting: Specifies the trigger timing for sampling ADC in synchronization with
PMD.
* These registers are effective when one of the following PMD trigger modes is selected:
count-down match, count-up match, count-up/-down match
* These registers are ineffective when the PMD trigger output mode is set to trigger select output
(TRGOUT=1).

TMPM370
15.4.3.24 VETRGSEL Register

31 ・・・ 9 8
VETRGSEL0 bit Symbol
VETRGSEL1 After reset 0x000000
7 6 5 4 3 2 1 0
bit Symbol VTRGSEL
Read/Write R R/W
－ Synchronizing trigger
Function 0-5: Output trigger number
6-7: Prohibited
<VTRGSEL> PMD setting: Specifies the synchronizing trigger number to be output at the timing
specified in the VTRGCMP0 register.
* These registers are effective when the PMD trigger output mode is set to trigger select output
(TRGOUT= 1).
15.4.3.25 VEEMGRS Register

31 ・・・ 9 8
VEEMGRS0 bit Symbol
VEEMGRS1 After reset 0x000000
7 ・・・ 2 1 0
bit Symbol EMGRS
Read/Write R R/W
ー EMG return
0: Nop
Function
1: EMG return
command
<EMGRS> PMD setting : EMG return command for returning from the EMG state

TMPM370
15.5 Description of Operations
15.5.1 Schedule Management
Figure 15-4 shows a flowchart for motor control. The Vector Engine makes state transitions according to the
schedule and mode settings which are programmed through the relevant registers.
RESET
Initial setting
VE/PMD/ADC
Enable VE
Stop Change
Initial input
VEMODE
Change VEACTSCH
Positioning
Change VEMODE
Change VEACTSCH
Change VEMODE
Forced
commutation
Change VEACTSCH Change VEACTSCH

EMG return
Change VEMODE Change VEMODE
Speed control by
current feedback
Change VEACTSCH
Change VEMODE
Brake
Change VEACTSCH :Executed by the VE

: Software control
Figure 15-4 Example of Motor Control Flow
RESET : Microcontroller reset

Initial setting : Initial setting by a user-created program
Stop : Stop the motor.
Initial input : Sample and store zero-current data when the motor is at stop
Positioning : Determine the initial motor position.
Forced commutation : Start the motor. For a specified period, the motor is rotated at a specified
speed, not controlled by current feedback.
Speed control by
current feedback : Control motor rotation by current feedback.
Brake : Deceleration control
EMG return : Return from the EMG state.

TMPM370
15.5.1.1 Schedule Control
The VEACTSCH register is used to select the schedule to be executed. A schedule is comprised of an
output schedule handling output-related tasks and an input schedule handling input-related tasks. Table
15-5 shows the tasks that are executed in each schedule.
The VEMODE register is used to enable or disable phase interpolation, control output operation, and
enable or disable zero-current detection as appropriate for each step of the motor control flow (see Table
15-6).
Table 15-5 Tasks To Be Executed in Each Schedule

Output Schedule Input Schedule
Output Input
Schedule Selection Output
Current SIN/COS coordinate Output Trigger Input Input phase coordinate
(VEACTSCH) phase
control computation axis control generation processing conversion axis
conversion
conversion conversion
Individual
0 *1 *1 *1 *1 *1 *1 *1 *1 *1
execution
1 Schedule 1 *2 *3 *4
4 Schedule 4 － *2 *3 *4
9 Schedule 9 －－－－ *3 *4 －－
*1: Each task is executed only when it is specified.

*2: Phase interpolation
*3: Output OFF/EMGRS
*4: Task operation to be switched by zero-current detection
Table 15-6 Typical Setting Example

Register Setting
Zero-current
Motor Control Flow Schedule selection Task specification Phase interpolation Output control
detection
(VEACTSCH) (VETASKAPP) (VEMODE) (VEMODE)
(VEMODE)
Stop 9 0 x 00 0
Initial input 9 0 x 00 1
Positioning 1 5 0 01 0
Forced commutation 1 5 1 01 0
Speed control by current 5
1 1 01 0
feedback
Brake 4 6 0 01 0
EMG return 9 0 x 11 0

TMPM370
An output schedule begins executing by the VECPURUNTRG command. When all output-related tasks
are completed, the Vector Engine enters a standby state and waits for a start trigger for input-related tasks.
At this time, schedules of the other channel can be executed.
An input schedule begins executing by a start trigger. When all input-related tasks are completed, the
Vector Engine generates an interrupt to the CPU and enters a halt state. However, if the schedule has its
repeat count (VEREPTIME) set to “2” or more, an interrupt is not generated until the schedule is executed
the specified number of times.
Start command
Execute
output schedule
Wait for
start trigger
Start trigger
Execute
input schedule
Repeated specified N
number of times?
Schedule end
Figure 15-5 Schedule Execution Flow

TMPM370
15.5.1.2 Start Control
Enable the Vector Engine with the VEEN register. Specify a schedule (VEACTSCH register), task to be
executed (VETASKAPP register) and repeat count (VEREPTIME register).
A schedule of the Vector Engine is comprised of an output schedule and an input schedule. Typically, the
Vector Engine executes an output schedule first, enters a standby state, and then starts executing an input
schedule by a start trigger.
An output schedule is started:
i) By the VECPURUNTRG command. In this case, the task specified in the VETASKAPP register is
executed.
ii) On a repeat start (when VEREPTIME ≥ 2) after the corresponding input schedule is completed.
An input schedule is started:
i) By a start trigger (selected in the VETRGMODE register) after the corresponding output schedule is
completed.
ii) By the VECPURUNTRG command. In this case, the task specified in the VETASKAPP register is
executed.
15.5.2 Summary of Tasks
Table 15-7 gives a summary of tasks executed in output and input schedules. When each task is to be
executed individually or specified as a startup task, use the task number shown in this table.
Table 15-7 List of Tasks

Task Description Task Number
Current control Controls dq currents. 5
Performs sine/cosine computation and
SIN/COS computation 6
phase interpolation.
Output coordinate axis
Output Converts dq coordinates to αβ coordinates. 7
conversion
schedule
Output phase conversion Converts 2-phase to 3-phase. 8
Converts data to PMD setting format.
Output control 0
Switches PWM shift.
Trigger generation Generates synchronization trigger timing. 1
Captures AD conversion results and
Input processing 2
converts them into fixed-point format
Input
Input phase conversion Converts 2-phase to 3-phase. 3
schedule
Input coordinate axis
Converts αβ coordinates to dq coordinates. 4
conversion

TMPM370
15.5.2.1 Current Control
The current control unit is comprised of a PI control unit for d-axis and a PI control unit for q-axis, and
calculates d-axis and q-axis voltages.
i) PI control of d-axis current

[Equations]
ΔID = VEIDREF ×2^16 - ID : Difference between current reference value and current feedback
VDI = VECIDKI ×2^16 × ΔID ×2+ VDI : Integral term computation
VEVD = (VECIDKP ×2^16 × ΔID ×2+ VDI) / 2^32 : Voltage calculation using proportional term
Register Name Description

VEIDn d-axis current 32-bit fixed-point data (31 fractional bits)
Input VEIDREFn Reference value of d-axis 16-bit fixed-point data (15 fractional bits)
current
VECIDKPn Proportional coefficient 16-bit data
VECIDKIn Integral coefficient 16-bit data
Output VEVDn d-axis voltage 32-bit fixed-point data (31 fractional bits)
Internal VDIn Integral term of d-axis voltage 64-bit fixed-point data (63 fractional bits)
n = channel number
ii) PI control of q-axis current

[Equations]
ΔIQ = VEIQREF×2^16 - IQ : Difference between current reference value and current feedback
VQI = VECIQKI ×2^16 ×ΔIQ ×2+ VQI : Integral term computation
VEVQ = (VECIQKP ×2^16 × ΔIQ ×2 + VQI) / 2^32 : Voltage calculation using proportional term

VEIQn q-axis current 32-bit fixed-point data (31 fractional bits)
Input VEIQREFn Reference value of q-axis 16-bit fixed-point data (15 fractional bits)
current
VECIQKPn Proportional coefficient 16-bit data
VECIQKIn Integral coefficient 16-bit data
Output VEVQn q-axis voltage 32-bit fixed-point data (31 fractional bits)
Internal VQIn Integral term of q-axis voltage 64-bit fixed-point data (63 fractional bits)
n = channel number

TMPM370
15.5.2.2 SIN/COS Computation
The SIN/COS computation unit is comprised of a phase interpolation unit and a SIN/COS computation
unit.
Phase interpolation calculates the rotation speed by integrating with the PWM period. It is executed only
when phase interpolation is enabled.
i) Phase interpolation
[Equations]
VETHEATA = (VEOMEGA ×VETPWM + VETHEATA × 2^31) / 2^31 : Integration of rotation speed.
Only when phase interpolation is enabled.

VETHETAn Phase θ 16-bit fixed-point data (0.0 to1.0, 16 fractional bits)
Input VEOMEGAn Rotation speed 16-bit fixed-point data (-1.0 to 1.0, 15 fractional bits)
VETPWM PWM period rate 16-bit data
VEMODEn Phase interpolation enable Mode settings
Output VETHETAn Phase θ 16-bit fixed-point data (0.0 to 1.0, 16 fractional bits))
n = channel number
ii) SIN/COS computation

[Equations]
VESINM = VESIN : Saves previous value (for input processing).
VECOSM = VECOS : Saves previous value (for input processing).
VESIN = sin(VETHETA × π／2^15) ×2^15 : SIN/COS computation
VECOS = sin((VETHETA＋0x4000)×π／2^15) ×2^15

Input VETHETAn Phase θ 16-bit fixed-point data (0.0 to 1.0, 16 fractional bits)
VESINn Sine value at θ 16-bit fixed-point data (-1.0 to 1.0, 15 fractional bits)
Output VECOSn Cosine value at θ 16-bit fixed-point data (-1.0 to 1.0, 15 fractional bits)
VESINMn Previous sine value 16-bit fixed-point data (-1.0 to 1.0, 15 fractional bits)
VECOSMn Previous cosine value 16-bit fixed-point data (-1.0 to 1.0, 15 fractional bits)
n = channel number

TMPM370
15.5.2.3 Output Voltage Conversion (Coordinate axis Conversion/Phase Conversion)
Output voltage conversion is comprised of dq-to-αβ coordinate axis conversion and 2-phase-to-3-phase
conversion.
The dq-to-αβ coordinate axis conversion calculates Vα and Vβ from Vd, Vq in SIN and COS.
The 2-phase-to-3-phase conversion performs segmentation by using Vα and Vβ and performs space
vector conversion to calculate Va, Vb and Vc.
For the 2-phase-to-3-phase conversion, either 2-phase modulation or 3-phase modulation can be
selected.
(1) dq-to-αβ coordinate conversion

[Equations]
VETMPREG3 = (VECOS ×VEVD - VESIN ×VEVQ) / 2^15 : Calculates Vα.
VETMPREG4 = (VESIN ×VEVD + VECOS ×VEVQ) / 2^15 : Calculates Vβ.

VEVDn d-axis voltage 32-bit fixed-point data (-1.0 to 1.0, 31 fractional bits)
Input VEVQn q-axis voltage 32-bit fixed-point data (-1.0 to 1.0, 31 fractional bits)
VESINn Sine value at θ 16-bit fixed-point data (-1.0 to 1.0, 15 fractional bits)
VECOSn Cosine value at θ 16-bit fixed-point data (-1.0 to 1.0, 15 fractional bits)
Output VETMPREG3 α-axis voltage 32-bit fixed-point data (-1.0 to 1.0, 31 fractional bits)
VETMPREG4 β-axis voltage 32-bit fixed-point data (-1.0 to 1.0, 31 fractional bits)
n = channel number
(2) 2-phase-to-3-phase conversion (space vector conversion)

i) Segmentation
[Equations]
VESECTORM = VESECTOR : Saves previous sector.
if(Vα≥0 & Vβ≥0)
if(|Vα|≥|Vβ|÷√3)
if(|Vα|÷√3≥|Vβ|) SECTOR=0
else SECTOR=1
else SECTOR=2
else if(Vα<0 & Vβ≥0)
if(|Vα|<|Vβ|÷√3) SECTOR=3
else if(|Vα|÷√3<|Vβ|) SECTOR=4
else SECTOR=5
else if(Vα<0 & Vβ<0)
if(|Vα| ≥ |Vβ|÷√3)
if(|Vα|÷√3≥|Vβ|) SECTOR=6
else SECTOR=7
else SECTOR=8
else if(Vα≥0 & Vβ<0)
if(|Vα| < |Vβ|÷√3) SECTOR=9
else if(|Vα|÷√3<|Vβ|) SECTOR=10
else SECTOR=11

Input VETMPREG3 α-axis voltage 32-bit fixed-point data (-1.0 to 1.0, 31 fractional bits)
VETMPREG4 β-axis voltage 32-bit fixed-point data (-1.0 to 1.0, 31 fractional bits)
Output VESECTORn Sector 4-bit data
VESECTORMn Previous sector 4-bit data
n = channel number

TMPM370
ii) 3-phase voltage calculation (when 3-phase modulation is selected and SECTOR=0 )
[Equations]
t1 = √3/VEVDC ×2^15 ×(√3/2×Vα - 1/2×Vβ) : Calculates V1 period.
t2 = √3/VEVDC ×2^15 ×Vβ : Calculates V2 period.
t3 = 1 - t1 - t2 : Calculates V0+V7 period.
VETMPREG0 ＝ t1 + t2 + t3 ÷ 2 : Calculates Va.
VETMPREG1 ＝ t1 + t3 ÷ 2 : Calculates Vb.
VETMPREG2 ＝ t3 ÷ 2 : Calculates Vc.

VETMPREG3 α-axis voltage 32-bit fixed-point data (-1.0 to 1.0, 31 fractional bits)
Input VETMPREG4 β-axis voltage 32-bit fixed-point data (-1.0 to 1.0, 31 fractional bits)
VEVDCn Supply voltage 16-bit fixed-point data (0.0 to 1.0, 15 fractional bits)
VESECTORn Sector 4-bit data
VEFMODEn Modulation mode Mode settings
Output VETMPREG0 a-phase voltage 32-bit fixed-point data (0.0 to 1.0, 31 fractional bits)
VETMPREG1 b-phase voltage 32-bit fixed-point data (0.0 to 1.0, 31 fractional bits)
VETMPREG2 c-phase voltage 32-bit fixed-point data (0.0 to 1.0, 31 fractional bits)
n = channel number
15.5.2.4 Output Control
The output control unit converts 3-phase voltage values into PWM setting format (VECMPU, VECMPV
and VECMPW ), and sets the VEOUTCR register to control output operation.
When 1-shunt current detection and 2-phase modulation are selected and PWM is enabled, if the rotation
speed is slower than the PWM shift switching reference value, output is switched to shift PWM output.

VETMPREG0 a-phase voltage 32-bit fixed-point data (0.0 to 1.0, 31 fractional bits)
Input VETMPREG1 b-phase voltage 32-bit fixed-point data (0.0 to 1.0, 31 fractional bits)
VETMPREG2 c-phase voltage 32-bit fixed-point data (0.0 to 1.0, 31 fractional bits)
VEMDPRDn PWM period 16-bit data (PMD PWM period )
VEOMEGAn Rotation speed 16-bit fixed-point data (-1.0 to 1.0, 15 fractional bits)
VEFPWMCHGn PWM shift switching reference 16-bit fixed-point data (0 to 1.0, 15 fractional bits)
VEMODEn Output control operation Mode settings
VEFMODEn PMD channel/ shift enable/ Mode settings
modulation mode/ detection
mode
VECMPUn PMD U-phase PMW setting 16- bit data (0 to MDPRD value)
Output VECMPVn PMD V-phase PWM setting 16-bit data (0 to MDPRD value)
VECMPWn PMD W-phase PWM setting 16-bit data (0 to MDPRD value)
VEOUTCRn PMD output control setting 9-bit setting
VEEMGRSn PMD EMG return 1-bit setting
VEMCTLFn Shift switching flag Status
n = channel number

TMPM370
15.5.2.5 Trigger Generation
The trigger generation unit calculates the trigger timing from the PWM setting values (VECMPU, VECMPV
and VECMPW) as appropriate to the current detection method, and sets the VETRGCMP0 and
VETRGCMP1 registers.

VECMPUn PMD U-phase PWM setting 16-bit data (0 to MDPRD value)
Input VECMPVn PMD V-phase PWM setting 16-bit data (0 to MDPRD value)
VECMPWn PMD W-phase PWM setting 16- bit data (0 to MDPRD value)
VEMDPRDn PWM period setting 16-bit data (PMD PWM period)
VETADC AD conversion time 16-bit data (0 to MDPRD value)
VETRGCRCn Trigger correction value 16-bit data (0 to MDPRD value)
VEMODEn Output control operation Mode settings
VEFMODEn PMD channel/ shift enable/ Mode settings
modulation mode/ detection
mode
VETRGCMP0 PMD trigger 0 timing 16-bit data (0 to MDPRD value)
Output VETRGCMP1 PMD trigger 1 timing 16-bit data (0 to MDPRD value)
VETRGSELn PMD trigger selection 3-bit data
n = channel number

TMPM370
15.5.2.6 Input Processing
The input processing unit saves segmented 3-phase current conversion results, and converts the current
and voltage conversion results into fixed-point data.
It saves zero-current conversion results in the initial input processing..

VEADREG0A ADC unit A conversion result 0 16-bit data (The upper 12 bits are used.)
Input VEADREG1A ADC unit A conversion result 1 16-bit data (The upper 12 bits are used.)
VEADREG0B ADC unit B conversion result 0 16-bit data (The upper 12 bits are used.)
VEPHNUM0A ADREG0A detected phase information 2-bit data
VEPHNUM0B ADREG0B detected phase information 2-bit data
VESECTORMn Sector information 4-bit data
VEMODEn Zero-current detection Mode settings
VEFMODEn PMD channel /current detection mode / Mode settings
ADC unit /shift enable
VEVDCn Supply voltage 16-bit fixed-point data (0.0 to 1.0, 15 fractional bits)
Output VETMPREG0 a-phase current 32-bit fixed-point data (-1.0 to 1.0, 31 fractional bits)
VETMPREG1 b-phase current 32-bit fixed-point data (-1.0 to 1.0, 31 fractional bits)
VETMPREG2 c-phase current 32-bit fixed-point data (-1.0 to 1.0, 31 fractional bits)
IA0n a-phase zero-current conversion result 16-bit data (The upper 12 bits are used.)
Internal IB0n b-phase zero-current conversion result 16-bit data (The upper 12 bits are used.)
IC0n c-phase zero-current conversion result 16-bit data (The upper 12 bits are used.)
IAADCn a-phase current conversion result 16-bit data (The upper 12 bits are used.)
IBADCn b-phase current conversion result 16-bit data (The upper 12 bits are used.)
ICADCn c-phase current conversion result 16-bit data (The upper 12 bits are used.)
n = channel number

TMPM370
15.5.2.7 Input Current Conversion (Phase Conversion/Coordinate axis Conversion)
Input current conversion is comprised of 3-phase-to-2-phase conversion and αβ-to-dq coordinate axis
conversion.
The 3-phase-to-2-phase conversion calculates Iα and Iβ from la, lb and lc.
The αβ-to-dq coordinate axis conversion calculates ld and lq from Iα, Iβ, VESINM and VECOSM.
(1) 3-phase-to-2-phase conversion

[Equations]
VETMPREG3 = VETMPREG0 : Calculates Iα.
VETMPREG4 = 1/√3 ×VETMPREG1 - 1/√3 ×VETMPREG2 : Calculates Iβ.

Input VETMPREG0 a-phase current 32-bit fixed-point data (-1.0 to 1.0, 31 fractional bits)
VETMPREG1 b-phase current 32-bit fixed-point data (-1.0 to 1.0, 31 fractional bits)
VETMPREG2 c-phase current 32-bit fixed-point data (-1.0 to 1.0, 31 fractional bits)
Output VETMPREG3 α-axis current 32-bit fixed-point data (-1.0 to 1.0, 31 fractional bits)
VETMPREG4 β-axis current 32-bit fixed-point data (-1.0 to 1.0, 31 fractional bits)
n = channel number
(2) αβ-to-dq coordinate conversion

[Equations]
VEID = VECOSM×VETMPREG3 + VESINM×VETMPREG4 : Calculates Id.
VEIQ = -VESINM×VETMPREG3 + VECOSM×VETMPREG4 : Calculates Iq.

Input VETMPREG3 α-axis current 32-bit fixed-point data (-1.0 to 1.0, 31 fractional bits)
VETMPREG4 Β-axis current 32-bit fixed-point data (-1.0 to 1.0, 31 fractional bits)
VESINMn Sine value at θ 16-bit fixed-point data (-1.0～1.0, 15 fractional bits)
VECOSMn Cosine value at θ 16-bit fixed-point data (-1.0～1.0, 15 fractional bits)
Output VEIDn d-axis current 32-bit fixed-point data (-1.0 to 1.0, 31 fractional bits)
VEIQn q-axis current 32-bit fixed-point data (-1.0 to 1.0, 31 fractional bits)
n = channel number

TMPM370
15.6 Combinations of VE Channel, ADC Unit and PMD Channel
Table 15-8 and Table 15-9 show the combinations of AD unit and PMD channel that can be used with each
Vector Engine channel depending on the current detection mode to be used.
The Vector Engine calculates the stored value in AD conversion result register 0 to 2 (ADxREG0 to 2) as
a current data and calculates the sotred value in AD conversion result register 3 (ADxREG3) as a voltage
data. Therefore, please specify it with proper setting, referring to Table 15-9.
(x=A or B)
Table 15-8 Combination of VE and PMD

Vector Engine PMD
Channel 0 Channel 0
Channel 1 Channel 1
Table 15-9 Combination of VE and ADC

Vector Engine ADC Unit A ADC Unit B
VEMODE(Note 1)
Current ADC
Channel ADAREG0 ADAREG1ADAREG2ADAREG3ADBREG0ADBREG1 ADBREG2ADBREG3
detection selection
<IDMODE> <ADCSEL>
Current Current
00 Note 2 VDC data - - - -
data 1 data 2
0x
Current Current
0 1x - Note 2 VDC data - - -
data 1 data 2
Current Current
1x 00 - VDC data - - - -
data 1 data 2
Current Current
01 - - - - Note 2 VDC data
data 1 data 2
0x
Current Current
1 1x - - - - Note 2 VDC data
data 2 data 1
Current Current
1x 01 - - - - - VDC data
data 1 data 2
Note 1: Please do not use the combination of VE and ADC which is not allowed in the table.
Note 2: Specifying the phase information to the register is necessary. However the AD conversion result of its
register is not used for calculation.

TMPM370
16. Motor Control Circuit (PMD: Programmable Motor Driver)

The TMPM370 contains a two-channel programmable motor driver (PMD). The PMD of this product has
newly added features of conduction output control and DC overvoltage detection to realize sensorless
motor control and supports interaction with the AD converter.
CPU
IO Bus I/F
Interrupt Interrupt Interrupt
VE
PMD PW M/Trigger setting Conversion Result ADC
ADC Trigger
EMG detection input Overvoltage Detection Input Conduction output Analog Input
/EMG /OVV U,V,W,X,Y,Z Motor current,Motor voltage
Figure 16-1 Motor Control-related Block Constitution
TMPM370 16-1 Motor control circuit

TMPM370
16.1 PMD Input/Output Signals
The table below shows the signals that are input to and output from each PMD.
Table 16-1 Input/Output Signals

Channel Pin Name PMD Signal Name Description
PC7/OVV0 OVV 0 OVV state signal
PC6/EMG0 EMG 0 EMG state signal
PC0/UO0 UO 0 U-phase output
PC1/XO0 X O0 X-phase output
PMD0
PC2/VO0 V O0 V-phase output
PC3/YO0 Y O0 Y- phase output
PC4/WO0 W O0 W-phase output
PC5/ZO0 Z O0 Z-phase output
PG7/OVV1 OVV 1 OVV state signal

PG6/EMG1 EMG 1 EMG state signal
PG0/UO1 UO 1 U-phase output
PG1/XO1 X O1 X-phase output
PMD1
PG2/VO1 V O1 V-phase output
PG3/YO1 Y O1 Y-phase output
PG4/WO1 W O1 W-phase output
PG5/ZO1 Z O1 Z-phase output

TMPM370
16.2 PMD Registers

The table below shows the registers related to the PMD. (The Address column shows a PMD0 address
first followed by a PMD1 address on the next line.)
Table 16-2 PMD Registers

Address Mnemonic Register Name
0x4005 0400 PMD0MDEN
PMD Enable Register
0x4005 0480 PMD1MDEN
0x4005 0404 PMD0PORTMD
Port Output Mode Register
0x4005 0484 PMD1PORTMD
0x4005 0408 PMD0MDCR
PMD Control Register
0x4005 0488 PMD1MDCR
0x4005 040C PMD0CNTSTA
PWM Counter Status Register
0x4005 048C PMD1CNTSTA
0x4005 0410 PMD0MDCNT
PWM Counter Register
0x4005 0490 PMD1MDCNT
0x4005 0414 PMD0MDPRD
PWM Period Register
0x4005 0494 PMD1MDPRD
0x4005 0418 PMD0CMPU
PMD Compare U Register
0x4005 0498 PMD1CMPU
0x4005 041C PMD0CMPV
PMD Compare V Register
0x4005 049C PMD1CMPV
0x4005 0420 PMD0CMPW
PMD Compare W Register
0x4005 04A0 PMD1CMPW
0x4005 0424 PMD0MODESEL
Mode Select Register
0x4005 04A4 PMD1MODESEL
0x4005 0428 PMD0MDOUT
PMD Output Control Register
0x4005 04A8 PMD1MDOUT
0x4005 042C PMD0MDPOT
PMD Output Setting Register
0x4005 04AC PMD1MDPOT
0x4005 0430 PMD0EMGREL
EMG Release Register
0x4005 04B0 PMD1EMGREL
0x4005 0434 PMD0EMGCR
EMG Control Register
0x4005 04B4 PMD1EMGCR
0x4005 0438 PMD0EMGSTA
EMG Status Register
0x4005 04B8 PMD1EMGSTA
0x4005 043C PMD0OVVCR
OVV Control Register
0x4005 04BC PMD1OVVCR
0x4005 0440 PMD0OVVSTA
OVV Status Register
0x4005 04C0 PMD1OVVSTA
0x4005 0444 PMD0DTR
Dead Time Register
0x4005 04C4 PMD1DTR
0x4005 0448 PMD0TRGCMP0
Trigger Compare 0 Register
0x4005 04C8 PMD1TRGCMP0
0x4005 044C PMD0TRGCMP1
0x4005 04CC PMD1TRGCMP1
0x4005 04D0 PMD1TRGCMP2
0x4005 04D4 PMD1TRGCMP3
0x4005 0458 PMD0TRGCR
Trigger Control Register
0x4005 04D8 PMD1TRGCR
0x4005 045C PMD0TRGMD
Trigger Output Mode Setting Register
0x4005 04DC PMD1TRGMD
0x4005 0460 PMD0TRGSEL
Trigger Output Select Register
0x4005 04E0 PMD1TRGSEL
0x4005 047C
Reserved -
0x4005 04FC
Note: Do not access to “Reserved” address.

TMPM370
16.3 PMD Circuit
Wave G eneration Circuit

PMDnEMGCR
PMDnMDCR PMDnMDOUT PMDnOVVCR PMDnEMGR PMDnDTR PMDnMDPOT
VE
pwmb.0 uo
PMDnMDPR UO
pwmb.1 xo
D Pulse Width Con duction Protection Dead XO
POUTU
PMDnCMPU Modulati on Control Control Time
POUTV pwmb.2 vo
Control VO
pwmb.3 yo
PMDnCMPV YO
POUTW
pwmb.4 wo
PMDnCMPW WO
pwmb.5 zo
ZO
EMG
VE
UPEQUS OVV
DNEQUS INTEMG
PTENC INTOVV
INTPWM
PORTEN
MDCNT
Sync Trigger G eneration Circuit
PMDnTRGCMP0
PMDTRG0
Sync
PMDnTRGCMP1 Trigger PMDTRG1
Generation
PMDnTRGCMP2 PMDTRG2
PMDnTRGCMP3 PMDTRG3
PMDTRG4
PMDnTRGCR
PMDTRG5
VE
Figure 16-2 Block diagram of PMD Circuit
The PMD circuit consists of two blocks of a wave generation circuit and a sync trigger generation circuit.
The wave generation circuit includes a pulse width modulation circuit, a conduction control circuit, a
protection control circuit, a dead time control circuit.
- The pulse width modulation circuit generates independent 3-phase PWM waveforms with the same
PWM frequency.
- The conduction control circuit determines the output pattern for each of the upper and lower sides of
the U, V and W phases.
- The protection control circuit controls emergency output stop by EMG input and OVV input.
- The dead time control circuit prevents a short circuit which may occur when the upper side and lower
side are switched.
- The sync trigger generation circuit generates sync trigger signals to the AD converter.

TMPM370
16.3.1 PMD mode control registers

16.3.1.1 PMD Enable Register (PMDnMDEN)
(PMD0:0x4005 0400, PMD1:0x4005 0480)
31 30 29 28 27 26 25 24
Bit Symbol - - - - - - - -
Read/Write R→0 R→0 R→0 R→0 R→0 R→0 R→0 R→0
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit Symbol - - - - - - - PWMEN
Read/Write R→0 R→0 R→0 R→0 R→0 R→0 R→0 R/W
After reset 0 0 0 0 0 0 0 0
<PWMEN>: Enables or disables waveform synthesis.

0: Disable
1: Enable
Output ports that are used for the PMD become high impedance when the PMD is disabled.
Before enabling the PMD, Setting <PWMEN>=”1”(enable) other relevant settings, such as output
port polarity.
16.3.1.2 Port Output Mode Register (PMDnPORTMD)

(PMD0:0x4005 0404, PMD1:0x4005 0484)
31 30 29 28 27 26 25 24
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit Symbol - - - - - - PORTMD
Read/Write R→0 R→0 R→0 R→0 R→0 R→0 R/W
After reset 0 0 0 0 0 0 0 0
<PORTMD>: Port control setting

00: Upper phases = High-Z, lower phases = High-Z
01: Upper phases = High-Z, lower phases = PMD output
10: Upper phases = PMD output, lower phases = High-Z
11: Upper phases = PMD output, lower phases = PMD output
The <PORTMD> setting controls external port outputs of the upper phases (U, V and W phases) and
the lower phases (X, Y and Z phases). When a tool break occurs while “High-Z” is selected, the upper
and lower phases of external output ports are set to high impedance. In other cases, external port
outputs depend on PMD outputs.
* When PWMEN=0, output ports are set to high impedance regardless of the output port setting.
* When an EMG input occurs, external port outputs are controlled depending on the EMGMD setting.

TMPM370
16.3.1.3 Mode Select Register (PMDnMODESEL)

(PMD0:0x4005 0424, PMD1:0x4005 04A4)
31 30 29 28 27 26 25 24
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit Symbol - - - - - - - MDSEL
Read/Write R→0 R→0 R→0 R→0 R→0 R→0 R→0 R/W
After reset 0 0 0 0 0 0 0 0
<MDSEL>: Mode select register

0: Bus mode
1: VE mode
This bit selects whether to load the second buffer of each double-buffered register with the register
value set via the bus (bus mode) or the value supplied from the Vector Engine (VE mode). The PWM
compare registers (CMPU, CMPV, CMPW), trigger compare registers (TRGCMP0, TRGCMP1) and
MDOUT register are double-buffered, and the second buffers are loaded in synchronization with the
PMD’s internal update timing.

TMPM370
16.3.2 Pulse Width Modulation Circuit
PMD Counter Status Register PWM Counter Register
PMDnCNTSTA PMDnMDCR PMDnMDCNT
4
PWM Sync Clock
UPEQUS,DNEQUS PWM
PWM nterrupt Request
INTPWM
Control
CMPRLD Up/Down
PWM Counter
fsys Clock control
MDCNT
Selector
0x0001
PWM Period Register A＝B

Selector/Latch
PMDnMDPRD
PWM Compare Register

PMDnCMPU A≦B pwmu
BufferU
VE:VCMPU
PMDnCMPV A≦B pwmv

BufferV
VE:VCMPV
PMDnCMPW A≦B pwmw

BufferW
VE:VCMPW
PMDnMODESEL
Figure 16-3 Pulse Width Modulation Circuit
The pulse width modulation circuit has a 16-bit PMD up-/down-counter and generates PWM carrier
waveforms with a resolution of 12.5 nsec at 80 MHz. The PWM carrier waveform mode can be selected
from mode 0 (edge-aligned PWM, sawtooth wave modulation) and mode 1 (center-aligned PWM,
triangular wave modulation).
The PWM period extension mode (MDCR<PWMCK> = 1) is also available. When this mode is selected,
the PWM counter generates PWM carrier waveforms with a resolution of 50 nsec.

TMPM370
(1) Setting the PWM period

The PWM period is determined by the MDPRD register. This register is double-buffered. Comparator
input is updated at every PWM period. It is also possible to update comparator input at every half PWM
period.
Oscillation frequency [Hz]

Sawtooth wave PWM: MDPRD register value =
PWM frequency [Hz]
Oscillation frequency [Hz]

Triangular wave PWM: MDPRD register value =
PWM frequency [Hz] × 2
(2) Compare function

The pulse width modulation circuit compares the PWM compare registers of the 3 phases (PMDnCMPU/
V/W) and the carrier wave generated by the PWM counter (PMDnMDCNT) to determine which is larger to
generate PWM waveforms with the desired duty.
The PWM compare register of each phase has a double-buffered compare register. The PWM compare
register value is loaded at every PWM period (when the internal counter value matches the MDPRD value).
It is also possible to update the compare register at every 0.5 PWM period.
［Sawtooth wave］
MDCNT counts up to MDPRD and
MDCNT is cleared to 1 in the next cycle.
[MDPRD]
[CMPU
Time
PWMU on
waveform
off
When switching from counting
When switching from counting down to counting up,
[Triangular down
MDCNT
to counting up, MDCNT=peak value (MDPRD)
wave] MDCNT=1 in two cycles. in two cycles.
[MDPRD]
[CMPU
Time
PWMU on
waveform
off
Figure 16-4 PWM Waveforms

TMPM370
(3) Waveform mode

Three-phase PWM waveforms can be generated in the following two modes:
i) 3-phase independent mode:

Each of the PWM compare registers for the three phases is set independently to generate
independent PWM waveforms for each phase. This mode is used to generate drive waveforms
such as sinusoidal waves.
ii) 3-phase common mode:

Only the U-phase PWM compare register is set to generate identical PWM waveforms for all the
three phases. This mode is used for rectangular wave drive of brushless DC motors.
(4) Interrupt processing

The pulse width modulation circuit generates PWM interrupt requests in synchronization with PWM
waveforms. The PWM interrupt period can be set to half a PWM period, one PWM period, two PWM
periods or four PWM periods.

TMPM370
16.3.2.1 PMD Control Register (PMDnMDCR)

(PMD0:0x4005 0408, PMD1:0x4005 0488)
31 30 29 28 27 26 25 24
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit Symbol - PWMCK SYNTMD DTYMD PINT INTPRD PWMMD
Read/Write R→0 R/W
After reset 0 0 0 0 0 0 0 0
<PWMMD>: PWM carrier waveform

0: PWM mode 0 (edge-aligned PWM, sawtooth wave)
1: PWM mode 1(center-aligned PWM, triangular wave)
This bit selects the PWM mode. PWM mode 0 is edge-aligned PWM and PWM mode 1 is
center-aligned PWM.
<INTPRD>: PWM interrupt period
00: Interrupt request at every 0.5 PWM period (PWM mode 1 only)
01: Interrupt request at every PWM period
10: Interrupt request at every 2 PWM periods
11: Interrupt request at every 4 PWM periods
This field selects the PWM interrupt period from 0.5 PWM period, one PWM period, two PWM periods
and four PWM periods.
When <INTPRD>=00, the contents of the compare registers (CMPU, CMPV, CMPW) and period
register (MDPRD) are updated into their respective buffers when the internal counter equals 1 or the
MDPRD value.
<PINT>: PWM interrupt timing
0: Interrupt request when PWM counter = 1
1: Interrupt request when PWM counter = MDPRD
This bit selects whether to generate an interrupt request when the PWM counter equals its minimum or
maximum value. When the edge-aligned PWM mode is selected, an interrupt request is generated
when the PWM counter equals the MDPRD value. When the PWM interrupt period is set to every 0.5
PWM period, an interrupt request is generated when the PWM counter equals 1 or MDPRD.)
<DTYMD>: Duty mode
0: 3-phase common mode
1: 3-phase independent mode
This bit selects whether to make duty setting independently for each phase or to use the CMPU
register for all three phases.
<SYNTMD>: Port output mode
This bit specifies the port output setting of the U, V and W phases. (See Table 16-4.)
<PWMCK>: PWM period extension mode
0: Normal period
1: 4x period
When <PWMCK>=0, the PWM counter operates with a resolution of 12.5 ns at fsys=80 MHz.
* Sawtooth wave: 12.5 ns, triangular wave: 25 ns
When <PWMCK>=1, the PWM counter operates with a resolution of 50 ns at fsys=80 MHz.
* Sawtooth wave: 50 ns, triangular wave: 100 ns

TMPM370
16.3.2.2 PWM Counter Status Register (PMDnCNTSTA)

(PMD0:0x4005 040C, PMD1:0x4005 048C)
31 30 29 28 27 26 25 24
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit Symbol - - - - - - - UPDWN
Read/Write R→0 R→0 R→0 R→0 R→0 R→0 R→0 R
After reset 0 0 0 0 0 0 0 0
<UPDWN>: PWM counter flag

0: Up-counting
1: Down-counting
This bit indicates whether the PWM counter is up-counting or down-counting.
When the edge-aligned PWM mode is selected, this bit is always read as 0.
16.3.2.3 PWM Counter Register (PMDnMDCNT)

(PMD0:0x4005 0410, PMD1:0x4005 0490)
31 30 29 28 27 26 25 24
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol MDCNT
Read/Write R
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit Symbol MDCNT
Read/Write R
After reset 0 0 0 0 0 0 0 1
<MDCNT>: PWM counter

PMD counter value (resolution: 12.5 ns at fsys = 80 MHz)
* When MDCR<PWMCK>=1, the counter resolution becomes 50 ns.
A16-bit counter for reading the PWM period count value. It is read-only.
* When the PMD is disabled (PWMEN=0), the value of PWM counter depends on the setting of
PWMMD (PWM carrier waveform). The value is as follows.
In case of PWMMD=0: 0x0001
In case of PWMMD=1: the value of MDPRD

TMPM370
16.3.2.4 PWM Period Register (PMDnMDPRD)

(PMD0:0x4005 0414, PMD1:0x4005 0494)
31 30 29 28 27 26 25 24
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol MDPRD
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit Symbol MDPRD
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
<MDPRD>: PWM period

MDPRD≧0x0010
A 16-bit register for specifying the PWM period. This register is double-buffered and can be changed
even when the PWM counter is operating. The buffer is loaded at every PWM period. (That is, when the
PWM counter matches the MDPRD value. When 0.5 PWM period is selected, loading is performed
when the PWM counter matches 1 or MDPRD. The least significant bit must be set as 0.)
If <MDPRD> is set to a value less than 0x0010, it is automatically assumed to be 0x0010. (The register
retains the actual value that is written.)
* Do not write to this register in byte units. If the upper 8 bits [15:8] and the lower 8 bits [7:0] are written
separately, operation cannot be guaranteed.

TMPM370
16.3.2.5 PWM Compare Registers (PMDnCMPU, PMDnCMPV, PMDnCMPW)

PMD0(0x4005 0418-041B),PMD1( 0x4005 0498-049B)
31 30 29 28 27 26 25 24
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol CMPU0,1
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit Symbol CMPU0,1
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
PMD0(0x4005 041C-041F),PMD1( 0x4005 049C-049F)

31 30 29 28 27 26 25 24
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol CMPV0,1
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit Symbol CMPV0,1
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
PMD0(0x4005 0420-0423),PMD1( 0x4005 04A0-04A3)

31 30 29 28 27 26 25 24
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol CMPW0,1
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit Symbol CMPW0,1
Read/Write R/W
After reset 0 0 0 0 0 0 0 0

TMPM370
<CMPU, CMPV, CMPW>: PWM pulse width

Compare registers (resolution : 12.5 ns at fsys =80 MHz)
* When MDCR<PWMCK>=1, the counter resolution becomes 50 ns.
CMPU, CMPV and CMPW are compare registers for determining the output pulse width of the U, V
and W phases. Theses registers are double-buffered. Pulse width is determined by comparing the
buffer and the PWM counter to evaluate which is larger. (To be loaded when the PWM counter value
matches the MDPRD value. When 0.5 PWM period is selected, loading is performed when the PWM
counter matches 1 or MDPRD.) When this register is read, the value of the first buffer (data set via the
bus) is returned.
* To load the second buffer with the value in the compare register updated via the bus, select the bus
mode (default) by setting MODESEL<MDSEL> to 0.
* Do not write to these registers in byte units. If the upper 8 bits [15:8] and the lower 8 bits [7:0] are
written separately, operation cannot be guaranteed.

TMPM370
16.3.3 Conduction Control Circuit
PMDnMODESEL
PMDnMDOUT
VE:OUTCR
PMDnMDCR Decoder
UPWM
DTYMD FF FF xpwm U
UOC
outd
PWMU MUX mddec
pwmin X
pwminx
PWMV 1 VPWM
FF FF Decoder
VOC V
PWMW
WPWM
FF FF Decoder
0 WOC W
Sync
FF rel
Figure 16-5 Conduction Control Circuit
The conduction control circuit performs output port control according to the settings made in the PMD
output register (MDOUT). The MDOUT register bits are divided into two parts: settings for the
synchronizing signal for port output and settings for port output. The latter part is double-buffered and
update timing can be set as synchronous or asynchronous to PWM.
The output settings for six port lines are made independently for each of the upper and lower phases
through the bits 10 to 8 of the MDOUT register and bits 3 and 2 of the MDPOT register. In addition, bits 10
to 8 of the MDOUT register select PWM or H/L output for each of the U, V and W phases. When PWM
output is selected, PWM waveforms are output. When H/L output is selected, output is fixed to either a
high or low level. Table 16-3 shows a summary of port outputs according to port output settings in the
MDOUT register and polarity settings in the MDCR register.

TMPM370
16.3.3.1 PMD Output Setting Register (PMDnMDPOT)

(PMD0:0x4005 042C, PMD1:0x4005 04AC)
31 30 29 28 27 26 25 24
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit Symbol - - - - POLH POLL PSYNCS
Read/Write R→0 R→0 R→0 R→0 R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
<PSYNCS>: MDOUT transfer timing

00: Async to PWM
01: Load when PWM counter = 1
10: Load when PWM counter= MDPRD
11: Load when PWM counter = 1 or MDPRD
PSYNCS selects the timing when the U-, V- and W-phase output settings are reflected in port outputs
(sync or async to the PWM counter peak, bottom or peak/bottom).
When “00” (Async to PWM) is selected, the changing of MDOUT register is applied to the U-, V- and
W-phase output immediately. The <PSYNCS> is also available in the vector engine.
* This field must be set while MDEN<PWMEN>=0.
<POLL>: Lower phase port polarity
0: Active low
1: Active high
POLL selects the output port polarity of the lower phases.
* This bit must be set while MDEN<PWMEN>=0.
<POLH>: Upper phase port polarity
0: Active low
1: Active high
POLH selects the output port polarity of the upper phases.
* This bit must be set while MDEN<PWMEN>=0.

TMPM370
16.3.3.2 PMD Output Control Register (PMDnMDOUT)

(PMD0:0x4005 0428, PMD1:0x4005 04A8)
31 30 29 28 27 26 25 24
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol - - - - - WPWM VPWM UPWM
Read/Write R→0 R→0 R→0 R→0 R→0 R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit Symbol - - WOC VOC UOC
Read/Write R→0 R→0 R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
<UOC, VOC, WOC>,<UPWM, VPWM,WPWM>: U-, V-, and W-phase output control
The MDOUT register controls the port outputs of the U, V and W phases (see Table 16-3 below.)
* To load the second buffer of MDOUT with a value updated via the bus, select the bus mode (default)
by setting MODESEL<MDSEL> to 0.
* Do not write to this register in byte units. If the upper 8 bits [15:8] and the lower 8 bits [7:0] are written
separately, operation cannot be guaranteed.
○PMDnMDCR<SYNTMD>=0
Polarity: Active high (MDPOT bits 3, 2=1) Polarity: Active low (MDPOT bits 3, 2=0)
MDOUT MDOUT Bits 10, 9, 8 MDOUT MDOUT Bits 10, 9, 8
Output Control H/L or PWM Output Select Output Control H/L or PWM Output Select
Bits 5, 3, 1 Bits 4, 2, 0 0: H/L output 1: PWM output Bits 5,3,1 Bits 4,2,0 0: H/L output 1: PWM output
Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower
phase phase phase phase phase phase phase phase phase phase phase phase
output output output output output output output output
0 0 L L /PWM PWM 0 0 H H PWM /PWM
0 1 L H L PWM 0 1 H L H /PWM
1 0 H L PWM L 1 0 L H /PWM H
1 1 H H PWM /PWM 1 1 L L /PWM PWM
○PMDnMDCR<SYNTMD>=1
Polarity: Active high (MDPOT bits 3, 2=1) Polarity: Active low (MDPOT bits 3, 2=0)
MDOUT MDOUT Bits 10, 9, 8 MDOUT MDOUT Bits 10, 9, 8
Output Control H/L or PWM Output Select Output Control H/L or PWM Output Select
Bits 5, 3, 1 Bits 4, 2, 0 0: H/L output 1: PWM output Bits 5,3,1 Bits 4,2,0 0: H/L output 1: PWM output
Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower
phase phase phase phase phase phase phase phase phase phase phase phase
output output output output output output output output
0 0 L L /PWM PWM 0 0 H H PWM /PWM
0 1 L H L /PWM 0 1 H L H PWM
1 0 H L PWM L 1 0 L H /PWM H
1 1 H H PWM /PWM 1 1 L L /PWM PWM
Table 16-3 Port Outputs according to the UOC, VOC, WOC, UPWM, VPWM and WPWM Settings

TMPM370
Output Settings for Center-off PWM

Center-off PWM can be supported by the following settings.
Table 16-4 Register Settings for Center-off PWM

Normal PWM U-Phase PWM V-Phase PWM W-Phase PWM
cennter on center off centert off center offt
CMPU duty_U MDPRD-duty_U duty_U duty_U
CMPV duty_V duty_V MDPRD-duty_V duty_V
CMPW duty_W duty_W duty_W MDPRD-duty_W
UOC 11 00 11 11
VOC 11 11 00 11
WOC 11 11 11 00

TMPM370
16.3.4 Protection Control Circuit
EMG Control OVV Control EMG Release

Register Reg ister Register
PMDnEMGCR PMDnOVVCR PMDnE MGREL
8
6 6
Protection Control EMG EMG input

INTEMG EMG interrupt
EMGST EMG port input enable
PTENC
OVV OVV input
INTOVV OVV interrupt
PTEN_P Upper phase outpu t enable

PTEN_N Lower phase outpu t enable
u’
U
x’
X
v’
V
y’
Y
w’
W
z’
Z
Figure 16-6 Protection Control Circuit
The protection control circuit consists of an EMG protection control circuit and an OVV protection control
circuit.

TMPM370
16.3.4.1 EMG Protection Circuit
The EMG protection circuit consists of an EMG protection control unit and a port output disable unit. This
circuit is activated when the EMG input becomes low. The EMG protection circuit offers an emergency
stop mechanism: when the EMG input is asserted (H → L), all six port outputs are immediately disabled
(depending on the EMGCR<EMGMD> setting) and an EMG interrupt (INTEMG) is generated.
EMGCR<EMGMD> can be set to output a control signal that sets external output ports to high impedance
in case of an emergency.
A tool break also disables all six PWM output lines depending on the EMGCR<EMGMD> setting. When a
tool break occurs, external output ports can be set to high impedance through the setting of the PORTMD
register.
EMG protection is set through the EMG Control Register (EMGCR). A read value of 1 in
EMGSTA<EMGST> indicates that the EMG protection circuit is active. In this state, EMG protection can
be released by setting all the port output lines inactive (MDOUT[10:8][5:0]) and then setting
EMGCR<EMGRS> to 1.
To disable the EMG protection function, write 0x5A and 0xA5 in this order to the EMGREL register and
then clear EMGCR<EMGEN> to 0. (These three instructions must be executed consecutively.) While the
EMG protection input is low, any attempt to release the EMG protection state is ignored. Before setting
EMGCR<EMGRS> to 1 to release EMG protection, make sure that EMGST<EMGI> is high.
The EMG protection circuit can be disabled only after the specified key codes (0x5A, 0xA5) are written in
the EMGREL register to prevent it from being inadvertently disabled.
Note: Initial procedure for EMG function
After reset, the EMG function is enabled but EMG pin is configured as a normal port.
Therefore, as the EMG protection might be valid, release the EMG protection by the following
procedure at the initial sequence.
① Selects EMG function by PxFC register.
② Reads PMDnEMGSTA<EMGI> to confirm it as “1”.
③ Sets PMDnMDOUT<10:8、5:0> to ”0” to make all ports in-active (“L” output).
④ Releases EMG protection by setting PMDnEMGCR<EMGRS> to ”1”.
If the EMG protection is to be disabled, continue the following procedure.

⑤ Writes the key codes to PMDnEMGREL. (In order of 0x5A and 0xA5)
⑥ Sets PMDnEMGCR<EMGEN> to ”0” to disable the EMG protection.
16.3.4.2 EMG Release Register (PMDnEMGREL)

(PMD0:0x4005 0430, PMD1:0x4005 04B0)
31 30 29 28 27 26 25 24
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit Symbol EMGREL
Read/Write W
After reset 0 0 0 0 0 0 0 0
<EMGREL>: EMG disable code

The EMG and OVV protection functions can be disabled by setting 5A and A5 in this order to bits 7 to 0
of the EMGREL register.
When disabling these functions, EMGCR<EMGEN> and OVVCR<OVVEN> must be cleared to 0.
* This register is used for both the EMG and OVV functions.

TMPM370
16.3.4.3 EMG Control Register (PMDnEMGCR)

(PMD0:0x4005 0434, PMD1:0x4005 04B4)
31 30 29 28 27 26 25 24
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol - - - - EMGCNT
Read/Write R→0 R→0 R→0 R→0 R/W
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit Symbol - - INHEN EMGMD EMGISEL EMGRS EMGEN
Read/Write R→0 R→0 R/W R/W R/W W R/W
After reset 0 0 1 1 1 0 0 1
<EMGEN>: EMG protection circuit enable/disable

0: Disable
1: Enable
The EMG protection circuit is enabled by setting this bit to 1. In the initial state, the EMG protection
circuit is enabled.
To disable this circuit, write 5A and A5 in this order to the EMGREL register and then clear the EMGEN
bit to 0.
<EMGRS>: EMG protection release
0: -
1: Release protection
EMG protection can be released by setting the MDOUT register to 0 and then setting the EMGRS bit
to 1.
This bit is always read as 0.
* Be sure to write 0 to both the upper bits [10:8] and lower bits [5:0].
* Before releasing EMG protection, make sure that the EMG input has returned to high.
<EMGISEL>: EMG input select
0: Port input
1: Comparator output
This bit selects whether to use port input or comparator output as the EMG signal to be input to the
protection circuit.
<EMGMD>: EMG protection mode select
00: PWM output control disabled / Port output = All phases High-Z
01: All upper phases ON, all lower phases OFF / Port output = Lower phases High-Z
10: All upper phases OFF, all lower phases ON / Port output = Upper phases High-Z
11: All phases OFF / Port output = All phases High-Z
* ON = PWM output (no output control), OFF = Low [when <POLL>,<POLH>=1 (active high)]
This field controls PWM output and port output of the upper and lower phases in case of an emergency.
<INHEN>: Tool break enable/disable
0: Disable
1: Enable
This bit selects whether or not to stop the PMD when the PMD stop signal is input from the tool. In the
initial state, tool breaks are enabled.
<EMGCNT>: EMG input detection time
0 to 15 (When <EMGCNT=0, the noise filter is bypassed.)
EMGCNT×16/fsys (resolution: 200[nsec] at 80 MHz)

TMPM370
16.3.4.4 EMG Status Register (PMDnEMGSTA)

(PMD0:0x4005 0438, PMD1:0x4005 04B8)
31 30 29 28 27 26 25 24
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit Symbol - - - - - - EMGI EMGST
Read/Write R→0 R→0 R→0 R→0 R→0 R→0 R R
After reset 0 0 0 0 0 0 - 0
<EMGST>: EMG protection state

0: Normal operation
1: Protected
The EMG protection state can be known by reading this bit.
<EMGI>: EMG input

EMG protection state
The EMG input state can be known by reading this bit.

TMPM370
16.3.4.5 OVV Protection Control Circuit (OVV)
The OVV protection control circuit consists of an OVV protection control unit and a port output disable
unit. This circuit is activated when the OVV input port is asserted.
When the OVV input is asserted (H → L) for a specified period (set in OVVCR<OVVCNT>), the OVV
protection circuit fixes the six port output lines in the conduction control circuit to high or low. At this time,
an OVV interrupt (INTOV) is generated. It is possible to turn off only the upper or lower phases or all
phases.
OVV protection is set through the OVV Control Register (OVVCR). A read value of 1 in
OVVSTA<OVVST> indicates that the OVV protection circuit is active.
The release of the OVV protection state is enabled by setting OVVCR<OVVEN> to 1. Then, OVV
protection is automatically released after the OVV protection circuit completes its operation.
* The OVV protection state is not released while the OVV protection input is low. The state of this port
input can be checked by reading OVVSTA<OVVI>.
The OVV protection state is released in synchronization with the PWM period (when the PWM count
matches the MDPRD value). (When 0.5 PWM period is selected, the release timing is when the PWM
counter equals 1 or MDPRD.)
To disable the OVV protection function, write 0x5A and 0xA5 in this order to the EMGREL register and
then clear OVVCR<OVVEN> to 0. (These three instructions must be executed consecutively.)
The OVV protection circuit can be disabled only after the specified key codes (0x5A, 0xA5) are written in
the EMGREL register to prevent it from being inadvertently disabled.
16.3.4.6 OVV Control Register (PMDnOVVCR)

(PMD0:0x4005 043C, PMD1:0x4005 04BC)
31 30 29 28 27 26 25 24
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol - - - - OVVCNT
Read/Write R→0 R→0 R→0 R→0 R/W
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit Symbol - ADIN1EN ADIN0EN OVVMD OVVISEL OVVRS OVVEN
Read/Write R→0 R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
<OVVEN>: OVV protection circuit enable/disable

0: Disable
1: Enable
The OVV protection circuit is enabled by setting this bit to 1. In the initial state, the OVV protection
circuit is disabled.
To disable this circuit, write 5A and A5 in this order to the EMGREL register and then clear this bit to 0.
(These three instructions must be executed consecutively.)
<OVVRS>: OVV protection release
0: Disable automatic release of OVV protection
1: Disable automatic release of OVV protection
The OVV protection state is entered when the overvoltage detection signal makes a high-to-low
transition. After the overvoltage detection signal returns high, the OVV protection state can be
automatically released by a match between the PWM counter and the MDPRD register by setting this bit
to 1.
* When 0.5 PWM period is selected (MDCR<INTPRD>=00), the OVV protection state is released
when the PWM counter equals 1 or MDPRD.

TMPM370
<OVVISEL>: OVV input select

0: Port input
1: ADC monitor signal
This bit selects whether to use port input or the monitor signal from the ADC as the OVV signal to be
input to the protection circuit.
When the ADC monitor signal is selected, <OVVCNT> becomes invalid.
<OVVMD>: OVV protection mode
00: No output control
01: All upper phases ON, all lower phases OFF
10: All upper phases OFF, all lower phases ON
11: All phases OFF
* ON=High, OFF=Low [when <POLL>,<POLH>=1 (active high)]
This field controls the outputs of the upper and lower phases when an OVV condition occurs.
* If OVV and EMG conditions occur simultaneously, the protection mode settings in the EMGCR
register become effective.
<ADIN0EN>: ADC A monitor interrupt input enable
0: Disable
1: Enable
This bit selects whether to enable or disable the monitor signal input from ADC A.
When this bit is set to enable and <OVVISEL>=1, the PMD is placed in a protection state (if OVV
protection is enabled) by an interrupt signal from ADC A that is generated by a match between an AD
conversion result and the specified compare value.
* For details, see the chapter on the ADC.
<ADIN1EN>: ADC B monitor interrupt input enable
0: Disable input
1: Enable input
This bit selects whether to enable or disable the monitor signal input from ADC B.
When this bit is set to enable and <OVVISEL>=1, the PMD is placed in a protection state (if OVV
protection is enabled) by an interrupt signal from ADC B that is generated by a match between an AD
conversion result and the specified compare value.
* For details, see the chapter on the ADC.
<OVVCNT>: OVV input detection time
1-15 (If 0 is set, it is handled as 1.)
OVVCNT×16/fsys (resolution: 200[nsec] at 80 MHz )
* OVVCNT is effective only when port input is selected as the OVV signal (<OVVISEL>=1).

TMPM370
16.3.4.7 OVV Status Register (PMDnOVVSTA)

(PMD0:0x4005 0440, PMD1:0x4005 04C0)
31 30 29 28 27 26 25 24
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit Symbol - - - - - - OVVI OVVST
Read/Write R→0 R→0 R→0 R→0 R→0 R→0 R R
After reset 0 0 0 0 0 0 - 0
<OVVST>: OVV protection state

0: Normal operation
1: Protected
The OVV state can be known by reading this bit.
<OVVI>: OVVI input
OVVI state
The OVV input state (selected by OVVCR<OVVISEL>) can be known by reading this bit.

TMPM370
16.3.5 Dead Time Circuit
MDPOT MDPOT
PMDnDTR <POLL> <POLH>
fsys/8
ON Delay Circuit
U
u’ X
x’
ON Delay Circuit
V
v’ Y
y’
ON Delay Circuit
W
w’ Z
z’
Figure 16-6 Dead Time Circuit
The dead time circuit consists of a dead time unit and an output polarity switching unit.
For each of the U, V and W phases, the ON delay circuit introduces a delay (dead time) when the upper
and lower phases are switched to prevent a short circuit. The dead time is set to the Dead Time Register
(DTR) as an 8-bit value with a resolution of 100 ns at 80 MHz.
The output polarity switching circuit allows the polarity (active high or active low) of the upper and lower
phases to be independently set through MDPOT<POLH> and <POLL>.
16.3.5.1 Dead Time Register (PMDnDTR)

(PMD0:0x4005 0444, PMD1:0x4005 04C4)
31 30 29 28 27 26 25 24
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit Symbol DTR
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
<DTR>: Dead time

100 nsec × 8 bits (up to 25.5 μsec at fsys = 80 MHz)
* Do not change this register while MDEN<PWMEN>=1.

TMPM370
16.3.6 Sync Trigger Generation Circuit

PW MSync Signal
updn PTENC
MD CNT PMDn TRGCR

PMD nMODES EL
T RG0
PMD nT RGCM P0 A=B S lo pe S elect Trigg er Outp ut
Buffer
Select
VE:VTRGC MP 0
PM DTRG0
PM DTRG1
TRG 1
PMD nT RGCM P1 A=B
Buffer
VE:VTRGC MP 1 PM DTRG2
PM DTRG3
TRG 2
A=B
PM DnTRGC MP2 Buffer
PM DTRG4
PM DTRG5
TRG 3
A=B
PM DnTRGC MP3 Buffer
Trigger Output Sector Inform ation

Mode
Figure 16-7 Sync Trigger Generation Circuit
The sync trigger generation circuit generates trigger signals for starting ADC sampling in synchronization
with PWM. The ADC trigger signal (PMDTRG) is generated by a match between MDCNT and TRGCMP.
The signal generation timing can be selected from up-count match, down-count match and
up-/down-count match. When the edge-aligned PWM mode is selected, the ADC trigger signal is
generated on an up-count match. When PWM output is disabled (MDEN<PWMEN>=0), trigger output is
also disabled.
When the trigger select output mode is selected, the trigger output port is switched according to the
TRGSEL register setting or sector information from the Vector Engine.

TMPM370
16.3.6.1 Trigger Compare Registers (PMDnTRGCMP0 ~3)

PMD0 (0x4005 0448-044B) , PMD1 (0x4005 04C8-04CB)
31 30 29 28 27 26 25 24
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol TRGCMP0
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit Symbol TRGCMP0
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
PMD0 (0x4005 044C-044F) , PMD1 (0x4005 04CC-04CF)

31 30 29 28 27 26 25 24
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol TRGCMP1
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit Symbol TRGCMP1
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
PMD0 (0x4005 0450-0453) , PMD1 (0x4005 04D0-04D3)

31 30 29 28 27 26 25 24
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol TRGCMP2
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit Symbol TRGCMP2
Read/Write R/W
After reset 0 0 0 0 0 0 0 0

TMPM370
PMD0 (0x4005 0454-0458) , PMD1 (0x4005 04D4-04D7)

31 30 29 28 27 26 25 24
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol TRGCMP3
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit Symbol TRGCMP3
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
<TRGCMP0-3>: Trigger output compare registers
When the PMD counter value (MDCNT) matches the value set in TRGCMPx, PMDTRG is output.
When TRGCMPx is read, the value in the first buffer of the double buffers (data set via the bus) is
returned.
TRGCMPx should be set in a range of 1 to [MDPRD set value – 1].
* It is prohibited to set TRGCMPx to 0 or the MDPRD value.
* To load the data in TRGCMP0 and TRGCMP1 to the second buffers, select the bus mode (default)
by setting MODESEL<MDSEL> to 0.
* Do not write to these registers in byte units. If the upper 8 bits [15:8] and the lower 8 bits [7:0] are
written separately, operation cannot be guaranteed.
* When TRGCMPx is set to 0x0001, no trigger output is made only in the first cycle after PWM
start (MDEN<PWMEN>1).
Update Timing of the Trigger Compare Register (TRGCMPx)

The Trigger Compare Register (TRGCMPx) is double-buffered. The timing at which the data written to
TRGCMPx is loaded to the second buffer depends on the setting of TRGCR<TRGxMD>. When
TRGCR<TRGxBE> is set to 1, data written to TRGCMPx is immediately loaded to the second buffer.
Table 16-6 TRGCMPx Buffer Update Timing according to Trigger Output Mode Setting
TRGxMD TBUFx Update Timing
000:Trigger output disabled Always updated
001:Trigger output on down-count match Updated when PWM counter equals MDPRD (PWM carrier peak)
010:Trigger output on up-count match Updated when PWM counter equals 1 (PWM carrier bottom)
Updated when PWM counter equals 1 or MDPRD
011:Trigger output on up-/down-count match
(PWM carrier peak/bottom)
100:Trigger output at PWM carrier peak
101:Trigger output at PWM carrier bottom
Always updated
110:Trigger output at PWM carrier peak/bottom
111:Trigger output disabled

TMPM370
16.3.6.2 Trigger Control Register (PMDnTRGCR)

(PMD0:0x4005 0458, PMD1:0x4005 04D8)
31 30 29 28 27 26 25 24
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol TRG3BE TRG3MD TRG2BE TRG2MD
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit Symbol TRG1BE TRG1MD TRG0BE TRG0MD
After reset 0 0 0 0 0 0 0 0
<TRG0MD, TRG1MD, TRG2MD, TRG3MD>: PMDTRG0 to PMDTRG3 mode setting

000: Trigger output disabled
001: Trigger output at down-count match
010: Trigger output at up-count match
011: Trigger output at up-/down-count match
100: Trigger output at PWM carrier peak
101: Trigger output at PWM carrier bottom
110: Trigger output at PWM carrier peak/bottom
111: Trigger output disabled
This register selects trigger output timing.

When the PMD is set to the edge-aligned mode, trigger outputs are made on up-count match or at
PWM carrier peak even if down-count match or PWM carrier bottom is selected.
* When <TRGxMD>=011, TRGCMPx=0x0001 and MDCR<PWMMD>=1 (triangular wave),

one trigger output is made per period.
When the 1-shunt mode is used, the acceptable PMDTRG is as follows.

VEFMODE0 VEFMODE1 PMD0TRGCR PMD0TRGCR PMD1TRGCR PMD1TRGCR
<IDMODE> <IDMODE> <TRG0MD> <TRG1MD> <TRG6MD> <TRG7MD>
10 - 010 (up-count) 010 (up-count) - -
10 - 101 (carrier bottom) 010 (up-count) - -
11 - 001 (down-count) 001 (down-count) - -
11 - 001 (down-count) 101 (carrier bottom) - -
- 10 - - 010 (up-count) 010 (up-count)
- 10 - - 101 (carrier bottom) 010 (up-count)
- 11 - - 001 (down-count) 001 (down-count)
- 11 - - 001 (down-count) 101 (carrier bottom)
< TRG0BE､TRG1BE､TRG2BE､TRG3BE >: PMDTRG0 to PMDTRG3 buffer update timing

0: Sync
1: Async (The value written to PMDTRGx is immediately reflected.)
This bit enables asynchronous updating of the PMDTRG0 to PMDTRG3 buffers.

TMPM370
16.3.6.3 Trigger Output Mode Setting Register (PMDnTRGMD)

(PMD0:0x4005 045C, PMD1:0x4005 04DC)
31 30 29 28 27 26 25 24
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit Symbol - - - - - - TRGOUT EMGTGE
Read/Write R→0 R→0 R→0 R→0 R→0 R→0 R/W R/W
After reset 0 0 0 0 0 0 0 0
<EMGTGE>: Output enable in EMG protection state
0: Disable trigger output in the protection state
1: Enable trigger output in the protection state
This bit enables or disables trigger output in the EMG protection state.
<TRGOUT>: Trigger output mode

0: Fixed trigger output
1: Variable trigger output
When <TRGOUT>=0, trigger outputs PMDTRG0 to PMDTRG3 output the trigger signals generated by
a match with TRGCMP0 to TRGCMP3 respectively.PMDTRG4 and PMDTRG5 are fixed to a low level.
When <TRGOUT>=1, trigger output by TRGCMP0 is switched according to the TRGSEL register
setting or sector information from the Vector Engine. For details, see the table below.
Table 16-7 Trigger Output Patterns

TRGOUT Setting Compare Register TRGSEL Setting Trigger Output
TRGCMP0 PMDTRG0
TRGCMP1 PMDTRG1
TRGOUT=0 X
TRGCMP2 PMDTRG2
TRGCMP3 PMDTRG3
0 PMDTRG0
1 PMDTRG1
2 PMDTRG2
TRGCMP0
3 PMDTRG3
TRGOUT=1 4 PMDTRG4
5 PMDTRG5
TRGCMP1 x No trigger output

TMPM370
16.3.6.4 Trigger Output Select Register (PMDnTRGSEL)

(PMD0:0x4005 0460 ､ PMD1:0x4005 04E0)
31 30 29 28 27 26 25 24
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit Symbol - - - - - TRGSEL
Read/Write R→0 R→0 R→0 R→0 R→0 R/W
After reset 0 0 0 0 0 0 0 0
<TRGSEL>: Trigger output select

000: Output from PMDTRG0
110: No trigger output
111: No trigger output
This field is effective when the variable trigger output mode is selected (TRGMD<TRGOUT>=1). The
selected trigger is output by a match between the PMD counter and the TRGCMP0 value. (See Table
16-6.)

TMPM370
17. 12-Bit Analog-to-Digital Converters
The TMPM370 FY contains two 12-bit successive-approximation analog-to-digital converters (ADCs).

The ADC unit A (ADC A) has 15 analog inputs. Six inputs are able to use for shunt resistor currents of
motor 0. Three of six inputs are connected with operational amp/ comparator outputs. Thus twelve
inputs can use for external input.
The ADC unit B (ADC B) has 17 analog inputs. Six inputs are able to use for shunt resistor currents of
motor 0. And two inputs are able to use for shut resistor currents of motor 1. four of eight inputs are
connected with operational amp/ comparator outputs. Thus thirteen inputs can use for external input.
Twenty two external analog input pins (AINA0 to AINA8, AINA9/AINB0, AINA10/AINB1,
AINA11/AINB2, AINB3 to AINB12) can also be used as input/output ports.
Functions and features
(1) It can select analog input and start AD conversion when receiving trigger signal from PMD or
TMRB(interrupt).
(2) It can select analog input, in the Software Trigger Program and the Constant Trigger Program.
(3) The ADCs has twelve register for AD conversion result.
(4) The ADCs generate interrupt signal at the end of the program which was started by PMD trigger
and TMRB trigger.
(5) The ADCs generate interrupt signal at the end of the program which are the Software Trigger
Program and the Constant Trigger Program.
(6) The ADCs have the AD conversion monitoring function. When this function is enabled, an interrupt
is generated when a conversion result matches the specified comparison value.
TMPM370 17-1 Analog/ Digital Converter

TMPM370
17.1 Block Diagram

The following shows a block diagram of the ADCs.
AVDDA
/ VREFHA
PH0 (AINA0) AINA0

PH1 (AINA1) AINA1 AVSSA
CPU / VREFLA
: :
: : ADC A VE
: : PMD0 TRG0 to 5
P10 (AINA8) AINA8 PMD1 TRG0 to 5
AINA9 INTTB51
AINA10 INTADAPDA/ B
AINA11 INTADACPA/ B
AINA12 (AMP A) INTADASFT
AINA13 (AMP B) INTADATMR
AINA14 (AMP C) PMD0 OVV
PI1 (AINA9/ AINB0) AMP A
1-shunt or CMP A
3-shunt resistor
circuit for Motor-1 PI2 (AINA10/ AINB1) AMP B PMD0 EMG
current CMP B
PI3 (AINA11/ AINB2) AMP C

CMP C
CMP A/ B/ C Ref. Voltage PMD1 EMG

(CVREFABC)
AINB0 PMD1 OVV
Common VDD/VSS for AMPVD
AINB1 INTADBSFT
AMPs and CMPs
AMPVSS AINB2 INTADBTMR
1-shunt resistor ANIB3
PJ0 (AINB3) AMP D INTADBPDA/ B
circuit for Motor-2 CMP D INTADBCPA / B
current CMP D Ref. Voltage
(CVREFD) ADC B INTTB51
PJ1 (AINB4) PMD0 TRG0 to 5
AINB4
PMD1 TRG0 to 5
: :
: : CPU
: :
PK1 (AINB12) AINB12 VE AVDDB
AINB13 (AMP A) / VREFHB
AINB14 (AMP B)
AINB15 (AMP C)
AVSSB
AINB16 (AMP D)
/ VREFLB
Fig 17.1 AD converters Block Diagram

TMPM370
17.2 List of Registers
The ADCs have the following registers.

Table 17.1 ADC Registers
Address(Unit A) Address(Unit B) Register Name Description
4003_00_00 4003_02_00 ADxCLK ADC Clock Setting Register
4003_00_04 4003_02_04 ADxMOD0 ADC Mode Setting Register 0
4003_00_08 4003_02_08 ADxMOD1 ADC Mode Setting Register 1
4003_00_0C 4003_02_0C ADxMOD2 ADC Mode Setting Register 2
4003_00_10 4003_02_10 ADxCMPCR0 Monitoring Setting Register 0
4003_00_14 4003_02_14 ADxCMPCR1 Monitoring Setting Register 1
4003_00_18 4003_02_18 ADxCMP0 AD Conversion Result Compare Register 0
4003_00_1C 4003_02_1C ADxCMP1 AD Conversion Result Compare Register 1
4003_00_20 4003_02_20 ADxREG0 AD Conversion Result Register 0
4003_00_2C 4003_02_2C ADxREG3 AD Conversion Result Register 3
4003_00_50 4003_02_50 ADxPSEL0 PMD Trigger Program Number Select Register 0
4003_00_5C 4003_02_5C ADxPSEL3 PMD Trigger Program Number Select Register 3
4003_00_80 4003_02_80 ADxPINTS0 PMD Trigger Interrupt Select Register 0
4003_00_8C 4003_02_8C ADxPINTS3 PMD Trigger Interrupt Select Register 3
4003_00_98 4003_02_98 ADxPSET0_REG PMD Trigger Program Register 0
4003_00_9C 4003_02_9C ADxPSET1_REG PMD Trigger Program Register 1
4003_00_A0 4003_02_A0 ADxPSET2_REG PMD Trigger Program Register 2
4003_00_AC 4003_02_AC ADxPSET5_REG PMD Trigger Program Register 5
4003_00_B0 4003_02_B0 ADxTSET_REG03 Timer Trigger Program Registers 0 to 3
4003_00_BC 4003_02_BC ADxSSET_REG03 Software Trigger Program Registers 0 to 3
4003_00_C0 4003_02_C0 ADxSSET_REG47 Software Trigger Program Registers 4 to 7
4003_00_C4 4003_02_C4 ADxSSET_REG811 Software Trigger Program Registers 8 to 11

TMPM370
Address(Unit A) Address(Unit B) Register Name Description

4003_00_C8 4003_02_C8 ADxASET_REG03 Constant Conversion Program Registers 0 to 3
4003_00_CC 4003_02_CC ADxASET_REG47 Constant Conversion Program Registers 4 to 7
4003_00_D0 4003_02_D0 ADxASET_REG811 Constant Conversion Program Registers 8 to 11
4003_00_D4 4003_02_D4 ADxMOD3 ADC Mode Setting Register 3
(Note) x= A or B : ADC Unit

TMPM370
17.3 Register Descriptions
AD conversion is performed at the clock frequency selected in the ADC Clock Setting Register.
17.3.1 ADC Clock Setting Register (ADxCLK)
ADACLK 7 6 5 4 3 2 1 0
0x4003_0000 Bit symbol - TSH3 TSH2 TSH1 TSH0 ADCLK2 ADCLK1 ADCLK0
ADBCLK After reset 0 1011 000
0x4003_0200 Function Always read AD prescaler output (SCLK) select
Write “1001”
as 0. 000: fc (Note1) 001: fc/2
010: fc/4 011: fc/8
1XX: fc/16
000 001 010 011 1XX VADCLK[2:0]

fc
FC
÷1 ÷2 ÷4 ÷8 ÷16
SCLK
sclk_vadc
Note 1: Frequency of SCLK can be use up to 40MHz. Do not set ADCLK[2:0] to “000” when fc=80MHz.
Note 2: AD conversion is performed at the clock frequency selected in this register. The conversion clock frequency must be selected to
ensure the guaranteed accuracy.
Note 3: The conversion clock must not be changed while AD conversion is in progress.
17.3.2 Mode Setting Registers
The ADC Mode Setting Registers (ADxMOD0, ADxMOD1, ADxMOD2 and ADxMOD3) are used to select
how AD conversion is started. (x=A , B : ADC unit)
ADxMOD0
ADAMOD0 7 6 5 4 3 2 1 0
0x4003_0004 Bit symbol - DACON ADSS
Read/Write R R/W W
ADBMOD0 After reset 0 0 0
0x4003_0204 Function Always read as 0. DAC control Software
triggered
0: off conversion
1: On
0：Don't care
1: Start
Setting <DACON> to “1”, when using the ADC.

Setting <ADSS> to “1” starts AD conversion (software triggered conversion). Receiving trigger signal from
PMD or TMRB(interrupt) starts AD conversion also.
For detail setting, please read the chapter about PMD and TMRB.

TMPM370
ADxMOD1
ADAMOD1 7 6 5 4 3 2 1 0
0xc4003_0008 Bit symbol ADEN - ADAS
Read/Write R/W R R/W
0x4003_0208 Function AD Always read as 0. Constant
conversion AD
control conversion
control
0: Disable 0: Disable
1: Enable 1: Enable
Setting <ADEN> to “1”, when using the ADC. After Setting <ADEN> to “1”, setting <ADAS> to “1” starts AD
conversion and repeat conversion.
ADxMOD2
ADAMOD2 7 6 5 4 3 2 1 0
0x4003_000C Bit symbol - ADSFN ADBFN
Read/Write R R R
0x4003_020C Function Always read as 0. Software AD
conversion conversion
busy flag busy flag
0: 0:
Conversion Conversion
completed not in
1: progress
Conversion 1:
in progress Conversion
in progress
The <ADBFN> is an AD conversion busy flag. When AD conversion is started regardless of conversion
factor (PMD, Timer, Software, Constant), <ADBFN> is set to “1”. When finished AD conversion, <ADBFN> is
cleared to “0”.
The <ADSFN> is a software AD conversion busy flag. After <ADSS> was set to “1”, when AD conversion is
actually started, <ADSFN> is set to “1”. When finished AD conversion, <ADSFN> is cleared to “0”.
ADxMOD3
ADAMOD3 7 6 5 4 3 2 1 0
0x4003_00D4 Bit symbol - - PMODE2 PMODE1 PMODE0 - - -
ADBMOD3 After reset 0 1 0 1 1 0 0 0
0x4003_02D4 Function Write “0” Write “1” Write “100” Write “0” Write “0” Write “0”
15 14 13 12 11 10 9 8
Bit symbol - - - - - - - -
After reset 0 0 0 0 0 1 0 0
Function Write “0” Write “0” Write “0” Write “0” Write “0” Write “1” Write “0” Write “0”
Note : <PMODE[2:0]> must be set to “100”. And do not change other bits in ADxMOD3 register.

TMPM370
17.3.3 Monitoring Setting Registers
The ADCs have the AD conversion result monitoring function.
17.3.3.1 ADxCMPCR0, ADxCMPCR1
The ADxCMPCR0 and ADxCMPCR1 registers are used to enable or disable comparison between an AD
conversion result and the specified comparison value, to select the register to be compared with an AD
conversion result and to set how many times comparison should be performed to determine the result.
After fixing the conversion result, the interrupt signal (INTADxCPA, INTADxCPB) is generated.
(x=A , B : ADC unit)
ADxCMPCR0
ADACMPCR0 7 6 5 4 3 2 1 0
0x4003_0010 Bit symbol CMP0EN - - ADBIG0 REGS03 REGS02 REGS01 REGS00
Read/Write R/W R R R/W R/W R/W R/W R/W
ADBCMPR0 After reset 0 0 0 0 0 0 0 0
0x4003_0210 Function Monitoring Always read Always read Comparison AD conversion result register to be compared
condition
function as 0. as 0.
0: Larger than or 0000: ADREG0 0100: ADREG4 1000: ADREG8
0: Disable equal to compare 0001: ADREG1 0101: ADREG5 1001: ADREG9
1: Enable register 0010: ADREG2 0110: ADREG6 1010: ADREG10
1: Smaller than or
0011: ADREG3 0111: ADREG7 1011: ADREG11
equal to compare
register
15 14 13 12 11 10 9 8
Bit symbol - - - - CMPCNT03 CMPCNT02 CMPCNT01 CMPCNT00
Read/Write R R R R R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
Function Always read Always read Always read Always read as Comparison count for determining the result
as 0. as 0. as 0. 0. 0000: After every comparison
0001: After two comparisons
・
・
1111: After 16 comparisons
ADxCMPCR1
ADACMPCR1 7 6 5 4 3 2 1 0
0x4003_0014 Bit symbol CMP1EN - - ADBIG1 REGS13 REGS12 REGS11 REGS10
Read/Write R/W R R R/W R/W R/W R/W R/W
ADBCMPR1 After reset 0 0 0 0 0 0 0 0
0x4003_0214 Function Monitoring Always read Always read Comparison AD conversion result register to be compared
condition
function as 0. as 0.
0: Larger than or 0000: ADREG0 0100: ADREG4 1000: ADREG8
0: Disable equal to compare 0001: ADREG1 0101: ADREG5 1001: ADREG9
1: Enable register 0010: ADREG2 0110: ADREG6 1010: ADREG10
1: Smaller than or
0011: ADREG3 0111: ADREG7 1011: ADREG11
equal to compare
register
15 14 13 12 11 10 9 8
Bit symbol - - - - CMPCNT13 CMPCNT12 CMPCNT11 CMPCNT10
Read/Write R R R R R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
Function Always read Always read Always read Always read as Comparison count for determining the result
as 0. as 0. as 0. 0. 0000: After every comparison
0001: After two comparisons
・
・
1111: After 16 comparisons

TMPM370
17.3.3.2 Conversion Result Compare Register
The ADxCMP0 and ADxCMP1 registers specify the value to be compared with an AD conversion result. The
upper 12 bits (bits 4 to 15) are used. (x=A , B : ADC unit)
ADxCMP0
ADACMP0 7 6 5 4 3 2 1 0
0x4003_0018 Bit symbol AD0CMP03 AD0CMP02 AD0CMP01 AD0CMP00 - - - -
Read/Write R/W R/W R/W R/W R R R R
ADBCMP0 After reset 0 0 0 0 0 0 0 0
0x4003_0218 Function Bits 0 to 3 of the value to be compared with an AD conversion Always read as 0.
result
15 14 13 12 11 10 9 8
Bit symbol AD0CMP11 AD0CMP10 AD0CMP09 AD0CMP08 AD0CMP07 AD0CMP06 AD0CMP05 AD0CMP04
After reset 0 0 0 0 0 0 0 0
Function Bits 4 to 11 of the value to be compared with an AD conversion result
ADxCMP1
ADACMP1 7 6 5 4 3 2 1 0
0x4003_001C Bit symbol AD1CMP03 AD1CMP02 AD1CMP01 AD1CMP00 - - - -
Read/Write R/W R/W R/W R/W R R R R
ADBCMP1 After reset 0 0 0 0 0 0 0 0
0x4003_021C Function Bits 0 to 3 of the value to be compared with an AD conversion Always read as 0.
result
15 14 13 12 11 10 9 8
Bit symbol AD1CMP11 AD1CMP10 AD1CMP09 AD1CMP08 AD1CMP07 AD1CMP06 AD1CMP05 AD1CMP04
After reset 0 0 0 0 0 0 0 0
Function Bits 4 to 11 of the value to be compared with an AD conversion result

TMPM370
17.3.4 AD Conversion Result Registers
17.3.4.1 ADxREG0 to ADxREG11
The ADxREGn (n = 0 to 11) register is used to store the result of an AD conversion. Bit 0 <ADRnRF> is
a flag that is set when an AD conversion result is stored in the ADxREGn register and is cleared when the
low-order byte of ADxREGn is read. Bit 1 <OVRn> is an overrun flag. This flag is set when a new AD
conversion result is stored before the low-order byte of ADxREGn is read and is cleared when the
low-order byte of ADxREGn is read.
There are twelve ADxREGn registers, which are all functionally equivalent.
AD Conversion Result Register (ADxREG0)

ADAREG0 7 6 5 4 3 2 1 0
0x4003_0020 Bit symbol ADR003 ADR002 ADR001 ADR000 - - OVR0 ADR0RF
ADBREG0 After reset 0 0 0 0 0 0 0 0
0x4003_0220 Function Bits 0 to 3 of an AD conversion result Always read Always read Overrun flag AD conversion
as 0. as 0. result store
0: No flag
overrun 0: No result
occurred stored
1: Overrun 1: Result
occurred stored
15 14 13 12 11 10 9 8
Bit symbol ADR011 ADR010 ADR009 ADR008 ADR007 ADR006 ADR005 ADR004
After reset 0 0 0 0 0 0 0 0
Function Bits 4 to 11 of an AD conversion result

ADAREG1 7 6 5 4 3 2 1 0
0: No flag
occurred stored
occurred stored
15 14 13 12 11 10 9 8
After reset 0 0 0 0 0 0 0 0

TMPM370

ADAREG2 7 6 5 4 3 2 1 0
0: No flag
occurred stored
occurred stored
15 14 13 12 11 10 9 8
After reset 0 0 0 0 0 0 0 0

ADAREG3 7 6 5 4 3 2 1 0
0x4003_002C Bit symbol ADR303 ADR302 ADR301 ADR300 - - OVR3 ADR3RF
0x4003_022C Function Bits 0 to 3 of an AD conversion result Always read Always read Overrun flag AD conversion
0: No flag
occurred stored
occurred stored
15 14 13 12 11 10 9 8
After reset 0 0 0 0 0 0 0 0

ADAREG4 7 6 5 4 3 2 1 0
0x4003_0030 Bit symbol ADR403 ADR402 ADR401 ADR400 - - OVR4 ADR0R4
0: No flag
occurred stored
occurred stored
15 14 13 12 11 10 9 8
After reset 0 0 0 0 0 0 0 0

TMPM370

ADAREG5 7 6 5 4 3 2 1 0
0: No flag
occurred stored
occurred stored
15 14 13 12 11 10 9 8
After reset 0 0 0 0 0 0 0 0

ADAREG6 7 6 5 4 3 2 1 0
0: No flag
occurred stored
occurred stored
15 14 13 12 11 10 9 8
After reset 0 0 0 0 0 0 0 0

ADAREG7 7 6 5 4 3 2 1 0
0: No flag
occurred stored
occurred stored
15 14 13 12 11 10 9 8
After reset 0 0 0 0 0 0 0 0

TMPM370

ADAREG8 7 6 5 4 3 2 1 0
0: No flag
occurred stored
occurred stored
15 14 13 12 11 10 9 8
After reset 0 0 0 0 0 0 0 0

ADAREG9 7 6 5 4 3 2 1 0
0: No flag
occurred stored
occurred stored
15 14 13 12 11 10 9 8
After reset 0 0 0 0 0 0 0 0

ADAREG10 7 6 5 4 3 2 1 0
0: No flag
occurred stored
occurred stored
15 14 13 12 11 10 9 8
After reset 0 0 0 0 0 0 0 0

TMPM370

ADAREG11 7 6 5 4 3 2 1 0
0: No flag
occurred stored
occurred stored
15 14 13 12 11 10 9 8
After reset 0 0 0 0 0 0 0 0

TMPM370
17.3.5 PMD Trigger Program Registers
AD conversion can be started by a trigger from the PMD (programmable motor driver).
The PMD trigger program registers are used to specify the program to be started by each of twelve
triggers generated by the PMD, to select the interrupt to be generated upon completion of the program
and to select the AIN input to be used.
The PMD trigger program registers include three types of registers: PMD Trigger Program Number Select
Register (ADxPSELp), PMD Trigger Interrupt Select Register (ADxPINTSn) and PMD Trigger Program Setting
Register (ADxPSETnm). (x=A , B : ADC unit , p=0 to 11, n=0 to 5, m=0 to 3)
PMD Trigger Program Registers

PMD Trigger Program Number
Select Registers
ADPSEL10
ADPSEL11
ADPSEL0
ADPSEL1
ADPSEL2
ADPSEL3
ADPSEL4
ADPSEL5
ADPSEL6
ADPSEL7
ADPSEL8
ADPSEL9
PMD Trigger Interrupt

Program 0 Program 1 Program 2 Program 3 Program 4 Program 5 Setting Registers
ADPINTS0 ADPINTS1 ADPINTS2 ADPINTS3 ADPINTS4 ADPINTS5
PMD Trigger Program

Setting Registers 0-5
ADPST00 ADPST10 ADPST20 ADPST30 ADPST40 ADPST50 Conversion Result Register 0
The PMD Trigger Program Number Select Register (ADxPSELn) specifies the program to be started
by each of twelve AD conversion start signals corresponding to twelve triggers generated by the PMD.
Programs 0 to 5 are available.
The PMD Trigger Interrupt Select Register (ADxPINTSn) selects the interrupt to be generated upon
completion of each program, and enables or disables the interrupt.
The PMD Trigger Program Setting Register (ADxPSETnm) specifies the settings for each of
programs 0 to 5. Each PMD Trigger Program Register is comprised of four registers for specifying the
AIN input to be converted. The conversion results corresponding to the ADxPSETn0 to ADxPSETn3
registers are stored in the Conversion Result Registers 0 to 3 (ADxREG0 to ADxREG3).

TMPM370
17.3.5.1 PMD Trigger Program Number Select Registers

The PMD Trigger Program Number Select Registers (ADxPSEL0 to ADxPSEL11) select the
program to be started (from among programs 0 to 5) by each of trigger inputs PMD0 to PMD11.
PMD Trigger Program Number Select Register 0 (ADxPSEL0)
ADAPSEL0 7 6 5 4 3 2 1 0
0x4003_0050 Bit symbol PENS0 PMDS02 PMDS01 PMDS00
ADBPSEL0 After reset 0 0 0 0 0 0 0 0
0x4003_0250 Function PMD Trigger Always read Always read Always read Always read Program number select
Program as 0. as 0. as 0. as 0.
Select 000: Program 0 100: Program 4
Register 0 001: Program 1 101: Program 5
enable 010 Program 2 110,111: Reserved
011: Program 3
0: Disable
1: Enable

ADAPSEL1 7 6 5 4 3 2 1 0
011: Program 3
0: Disable
1: Enable

ADAPSEL2 7 6 5 4 3 2 1 0
011: Program 3
0: Disable
1: Enable

ADAPSEL3 7 6 5 4 3 2 1 0
0x4003_005C Bit symbol PENS3 PMDS32 PMDS31 PMDS30
0x4003_025C Function PMD Trigger Always read Always read Always read Always read Program number select
011: Program 3
0: Disable
1: Enable

TMPM370

ADAPSEL4 7 6 5 4 3 2 1 0
011: Program 3
0: Disable
1: Enable

ADAPSEL5 7 6 5 4 3 2 1 0
011: Program 3
0: Disable
1: Enable

ADAPSEL6 7 6 5 4 3 2 1 0
011: Program 3
0: Disable
1: Enable

ADAPSEL7 7 6 5 4 3 2 1 0
011: Program 3
0: Disable
1: Enable

TMPM370

ADAPSEL8 7 6 5 4 3 2 1 0
011: Program 3
0: Disable
1: Enable

ADAPSEL9 7 6 5 4 3 2 1 0
011: Program 3
0: Disable
1: Enable

ADAPSEL10 7 6 5 4 3 2 1 0
011: Program 3
0: Disable
1: Enable

ADAPSEL11 7 6 5 4 3 2 1 0
enable 010: Program 2 110, 111: Reserved
011: Program 3
0: Disable
1: Enable

TMPM370
17.3.5.2 PMD Trigger Interrupt Select Registers
The PMD Trigger Interrupt Select Registers (ADxPINTS0 to ADxPINTS5) select the interrupt to
be generated for each of programs 0 to 5.
ADxPINTS0 (for program 0)
ADAPINTS0 7 6 5 4 3 2 1 0
0x4003_0080 Bit symbol INTSEL01 INTSEL00
Read/Write R R/W
ADBPINTS0 After reset 0 ０
0x4003_0280 Function Always read as 0. Interrupt select
00: No interrupt output
01: INTADPDA
10: INTADPDB
11: Reserved
Note: When <INTSEL> = 11, no interrupt is generated.

ADAPINTS1 7 6 5 4 3 2 1 0
Read/Write R R/W
01: INTADPDA
10: INTADPDB
11: Reserved

ADAPINTS2 7 6 5 4 3 2 1 0
Read/Write R R/W
01: INTADPDA
10: INTADPDB
11: Reserved

ADAPINTS3 7 6 5 4 3 2 1 0
0x4003_008C Bit symbol INTSEL31 INTSEL30
Read/Write R R/W
0x4003_028C Function Always read as 0. Interrupt select
01: INTADPDA
10: INTADPDB
11: Reserved

TMPM370

ADAPINTS4 7 6 5 4 3 2 1 0
Read/Write R R/W
01: INTADPDA
10: INTADPDB
11: Reserved

ADAPINTS5 7 6 5 4 3 2 1 0
Read/Write R R/W
01: INTADPDA
10: INTADPDB
11: Reserved

TMPM370
17.3.5.3 PMD Trigger Program Setting Registers 0 to 5
Each of the PMD Trigger Program Registers (ADxPSET0 to 5) are comprised of four registers.
These four registers are used to select the AD conversion input pin (AINA0 to AINA14, AINB0 to
AINB16) to be used and select phase of the Vector Engine. The numbers of these registers
correspond to those of the Conversion Result Registers.
Setting the <ENSPnm> to 1 enables the ADxPSETnm register. The <UVWISnm> bits are used to
select phase-U, phase-V or phase-W. The <AINSPnm> bits are used to select the AIN pin to be
used. The numbers of the PMD Trigger Program Setting Registers correspond to those of the
Conversion Result Registers. (n= 0 to 5 , m= 0 to 3)

TMPM370
PMD Trigger Program Register 0 (ADxPSET0)

ADAPSET0 7 6 5 4 3 2 1 0
0x4003_0098 Bit symbol ENSP00 UVWIS001 UVWIS000 AINSP004 AINSP003 AINSP002 AINSP001 AINSP000
ADBPSET0 After reset 0 0 0
0x4003_0298 Function REG0 Phase select AIN select (ADC unit A) in case of ADAPSET0
enable (for Vector Engine) 00000: AINA0
00001: AINA1
0: Disable 00: Not specified :
1: Enable 01: U 01110: AINA14 (01111 to 11111: Reserved)
10: V AIN select (ADC unit B) in case of ADBPSET0
11: W 00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
15 14 13 12 11 10 9 8
Bit symbol ENSP01 UVWIS011 UVWIS010 AINSP014 AINSP013 AINSP012 AINSP011 AINSP010
After reset 0 0 0
Function REG1 Phase select AIN select (ADC unit A) in case of ADAPSET0
00001: AINA1
11: W 00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
23 22 21 20 19 18 17 16
After reset 0 0 0
00001: AINA1
11: W 00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
31 30 29 28 27 26 25 24
After reset 0 0 0
00001: AINA1
11: W 00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
Note: When AIN24 to AIN 31 (set value: 11000 to 11111) are set in the AIN select field, AIN0 is selected.

TMPM370
PMD Trigger Program Register 1 (ADxPSET1)

ADAPSET1 7 6 5 4 3 2 1 0
0x4003_009C Bit symbol ENSP10 UVWIS101 UVWIS100 AINSP104 AINSP103 AINSP102 AINSP101 AINSP100
0x4003_029C Function REG0 Phase select AIN select (ADC unit A) in case of ADAPSET1
00001: AINA1
11: W 00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
15 14 13 12 11 10 9 8
After reset 0 0 0０
00001: AINA1
11: W 00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
23 22 21 20 19 18 17 16
After reset 0 0 0
00001: AINA1
10 : V AIN select (ADC unit B) in case of ADBPSET1
11: W 00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
31 30 29 28 27 26 25 24
After reset 0 0 ０
00001: AINA1
11: W 00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)

TMPM370
PMD Trigger Program Register 2(ADxPSET2)

ADAPSET2 7 6 5 4 3 2 1 0
0x4003_00A0 Bit symbol ENSP20 UVWIS201 UVWIS200 AINSP204 AINSP203 AINSP202 AINSP201 AINSP200
ADBPSET2 After reset 0 0 0０
0x4003_02A0 Function REG0 Phase select AIN select (ADC unit A) in case of ADAPSET2
00001: AINA1
11: W 00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
15 14 13 12 11 10 9 8
After reset 0 0 0
00001: AINA1
11: W 00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
23 22 21 20 19 18 17 16
After reset 0 0 0
00001: AINA1
11: W 00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
31 30 29 28 27 26 25 24
After reset 0 0 ０
00001: AINA1
11: W 00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)

TMPM370

ADAPSET3 7 6 5 4 3 2 1 0
0x4003_00A4 Bit symbol ENSP30 UVWIS301 UVWIS300 AINSP304 AINSP303 AINSP302 AINSP301 AINSP300
00001: AINA1
11: W 00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
15 14 13 12 11 10 9 8
After reset 0 0 ０
00001: AINA1
11: W 00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
23 22 21 20 19 18 17 16
After reset 0 0 ０
00001: AINA1
11: W 00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
31 30 29 28 27 26 25 24
After reset 0 0 ０
00001: AINA1
11: W 00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)

TMPM370

ADAPSET4 7 6 5 4 3 2 1 0
0x4003_00A8 B t symbol ENSP40 UVWIS401 UVWIS400 AINSP404 AINSP403 AINSP402 AINSP401 AINSP400
00001: AINA1
11: W 00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
15 14 13 12 11 10 9 8
After reset 0 0 0
00001: AINA1
11: W 00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
23 22 21 20 19 18 17 16
Bit symbol ENSP42 UVWIS421 UVWIS420 AINSP424 AINSP423 AINSP422 AINSP421 AINSP4_0
After reset 0 0 0
00001: AINA1
11: W 00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
31 30 29 28 27 26 25 24
After reset 0 0 0
00001: AINA1
11: W 00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)

TMPM370

ADAPSET5 7 6 5 4 3 2 1 0
0x4003_00AC Bit symbol ENSP50 UVWIS501 UVWIS500 AINSP504 AINSP503 AINSP502 AINSP501 AINSP500
Read/Write R/W R/W R R/W
ADBPSET5 After reset 0 0 ０
0x4003_02AC Function REG0 Phase select AIN select (ADC unit A) in case of ADAPSET5
00001: AINA1
11: W 00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
15 14 13 12 11 10 9 8
After reset 0 0 ０
00001: AINA1
11: W 00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
23 22 21 20 19 18 17 16
After reset 0 0 ０
00001: AINA1
11: W 00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
31 30 29 28 27 26 25 24
After reset 0 0 ０
00001: AINA1
11: W 00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)

TMPM370
17.3.6 Timer Trigger Program Registers
AD conversion can be started by INTTB51 generated from Timer5(TMRB5) as a trigger. There

are twelve 8-bit registers for programming timer triggers. Setting the <ENSTm> to “1” enables the
ADxTSETm register. The <AINSTmn> are used to select the AIN pin to be used. The numbers of
the Timer Trigger Program Registers correspond to those of the AD Conversion Result Registers.
When finished this AD conversion, interrupt : INTADxTMR is generated.
(x=A , B : ADC unit , m= 0 to 11, n= 0 to 4)

TMPM370
Timer Trigger Program Register 03 (ADxTSET03)

ADATSET03 7 6 5 4 3 2 1 0
0x4003_00B0 Bit symbol ENST0 - - AINST04 AINST03 AINST02 AINST01 AINST00
Read/Write R/W R R R/W
ADBTSET03 After reset 0 0 0 0
0x4003_02B0 Function REG0 Always read Always read AIN select (ADC unit A) in case of ADATSET03
enable as 0. as 0. 00000: AINA0
00001: AINA1
0: Disable :
1: Enable 01110: AINA14 (01111 to 11111: Reserved)
AIN select (ADC unit B) in case of ADBTSET03
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
15 14 13 12 11 10 9 8
Bit symbol ENST1 - - AINST14 AINST13 AINST12 AINST11 AINST10
After reset 0 0 0 0
Function REG1 Always read Always read AIN select (ADC unit A) in case of ADATSET03
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
23 22 21 20 19 18 17 16
After reset 0 0 0 0
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
31 30 29 28 27 26 25 24
After reset 0 0 0 0
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)

TMPM370

ADATSET47 7 6 5 4 3 2 1 0
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
15 14 13 12 11 10 9 8
After reset 0 0 0 0
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
23 22 21 20 19 18 17 16
After reset 0 0 0 0
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
31 30 29 28 27 26 25 24
After reset 0 0 0 0
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)

TMPM370

ADATSET811 7 6 5 4 3 2 1 0
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
15 14 13 12 11 10 9 8
After reset 0 0 0 0
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
23 22 21 20 19 18 17 16
After reset 0 0 0 0
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
31 30 29 28 27 26 25 24
After reset 0 0 0 0
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)

TMPM370
17.3.7 Software Trigger Program Registers
AD conversion can be started by software. There are twelve 8-bit registers for programming
software triggers. Setting the <ENSSn> to “1” enables the ADxSSETn register. The <AINSSnm>
are used to select the AIN pin to be used. The numbers of the Software Trigger Program
Registers correspond to those of the Conversion Result Registers.
When finished this AD conversion, interrupt :INTADxSFT is generated.
(x=A , B : ADC unit , n= 0 to 11, m= 0 to 4)

TMPM370
Software Trigger Program Register 03 (ADxSSET03)

ADASSET03 7 6 5 4 3 2 1 0
0x4003_00BC Bit symbol ENSS0 - - AINSS04 AINSS03 AINSS02 AINSS01 AINSS00
ADBSSET03 After reset 0 0 0 ０
0x4003_02BC Function REG0 Always read Always read AIN select (ADC unit A) in case of ADASSET03
00001: AINA1
0: Disable :
AIN select (ADC unit B) in case of ADASSET03
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
15 14 13 12 11 10 9 8
Bit symbol ENSS1 - - AINSS14 AINSS13 AINSS12 AINSS11 AINSS10
After reset 0 0 0 ０
Function REG1 Always read Always read AIN select (ADC unit A) in case of ADASSET03
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
23 22 21 20 19 18 17 16
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
31 30 29 28 27 26 25 24
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)

TMPM370

ADASSET47 7 6 5 4 3 2 1 0
0x4003_00C0 Bit symbol ENSS4 - - AINSS44 AINSS43 AINSS42 AINSS41 AINSS40
0x4003_02C0 Function REG4 Always read Always read AIN select (ADC unit A) in case of ADASSET47
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
15 14 13 12 11 10 9 8
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
23 22 21 20 19 18 17 16
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
31 30 29 28 27 26 25 24
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)

TMPM370

ADASSET811 7 6 5 4 3 2 1 0
0x4003_00C4 Bit symbol ENSS8 - - AINSS84 AINSS83 AINSS82 AINSS81 AINSS80
0x4003_02C4 Function REG8 Always read Always read AIN select (ADC unit A) in case of ADASSET811
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
15 14 13 12 11 10 9 8
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
23 22 21 20 19 18 17 16
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
31 30 29 28 27 26 25 24
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)

TMPM370
17.3.8 Constant Conversion Program Registers
The ADCs allow conversion triggers to be constantly enabled. There are twelve 8-bit registers for
programming constant triggers. Setting the <ENSAm> to “1” enables the ADxASETm register. The
<AINSAnm> are used to select the AIN pin to be used. The numbers of the Constant Trigger
Program Registers correspond to those of the Conversion Result Registers.
(x=A , B : ADC unit , m= 0 to 11, n= 0 to 4)

TMPM370
Constant Conversion Program Register 03 (ADxASET03)

ADAASET0 7 6 5 4 3 2 1 0
0x4003_00C8 Bit symbol ENSA0 - - AINSA04 AINSA03 AINSA02 AINSA01 AINSA00
ADBASET0 After reset 0 0 0 0
0x4003_02C8 Function REG0 Always read Always read AIN select (ADC unit A) in case of ADAASET03
00001: AINA1
0: Disable :
AIN select (ADC unit B) in case of ADBASET03
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
7 6 5 4 3 2 1 0
Bit symbol ENSA1 - - AINSA14 AINSA13 AINSA12 AINSA11 AINSA10
After reset 0 0 0 0
Function REG1 Always read Always read AIN select (ADC unit A) in case of ADAASET03
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
7 6 5 4 3 2 1 0
After reset 0 0 0 0
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
7 6 5 4 3 2 1 0
After reset 0 0 0 0
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)

TMPM370

ADAASET47 7 6 5 4 3 2 1 0
0x4003_00CC Bit symbol ENSA4 - - AINSA44 AINSA43 AINSA42 AINSA41 AINSA40
0x4003_02CC Function REG4 Always read Always read AIN select (ADC unit A) in case of ADAASET47
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
7 6 5 4 3 2 1 0
After reset 0 0 0 0
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
7 6 5 4 3 2 1 0
After reset 0 0 0 0
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
7 6 5 4 3 2 1 0
After reset 0 0 0 0
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)

TMPM370

ADAASET8 31 30 29 28 27 26 25 24
0x4003_00D0 Bit symbol ENSA8 - - AINSA84 AINSA83 AINSA82 AINSA81 AINSA80
0x4003_02D0 Function REG8 Always read Always read AIN select (ADC unit A) in case of ADAASET811
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
31 30 29 28 27 26 25 24
After reset 0 0 0 0
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
31 30 29 28 27 26 25 24
After reset 0 0 0 0
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)
31 30 29 28 27 26 25 24
After reset 0 0 0 0
00001: AINA1
0: Disable :
00000: AINB0
00001:AINB1
:
10000: AIN16 (10001 to 11111: Reserved)

TMPM370
17.4 Operation Descriptions
17.4.1 Analog Reference Voltages
For the High-level and Low-level analog reference voltages, the AVDD5A and AVSSA pins are
used in ADC A and the AVDD5B and AVSSB pins are used in ADC B. There are no registers for
controlling current between AVDD5x and AVSSx. Inputs to these pins are fixed. (x=A,B:ADC unit)
The internal amplifiers and comparators share the power supply and GND, which are connected
to AMPVDD and AMPVSS respectively.
(Note 1) During AD conversion, do not change the output data of port H/I/J/K, to avoid the
influence on the conversion result.
(Note 2) AD conversion results might be unstable by the following conditions.
Input operation is executed.
Output operation is executed.
Output current of port varies.
Take a countermeasure such as averaging the multiple conversion results, to get
precise value.

TMPM370
17.4.2 Starting AD Conversion

AD conversion is started by software or one of the following three trigger signals.
・PMD trigger (See “17.3.5 PMD Trigger Program Setting Registers.”)

・ Timer trigger (TMRB5) (See “17.3.6 Timer Trigger Program Setting Registers.”)
・Software trigger (See “17.3.7 Software Trigger Program Registers.”）
These start triggers are given priorities as shown below.
PMD trigger 0 > y y y > PMD trigger 5 > Timer trigger > Software trigger > constant trigger
If the PMD trigger occurs while an AD conversion is in progress, the PMD trigger is handled stop
the ongoing program and start AD conversion correspond to PMD trigger number.
If a higher-priority trigger occurs while an AD conversion is in progress, the higher-priority trigger
is handled after the ongoing program is completed.
It has some delay from generation of trigger to start of AD conversion. The delay depends on the
trigger. The following timing chart and table show the delay.
Trigger
1st conversion 2nd conversion

Busy flag
ADBFN
AD conversion result
Result of 1st conversion
register0 (ADxREG0)
AD conversion result
Result of 2nd conversion
register1 (ADxREG1)
AD conversion time AD conversion time

Delay time to the next
Delay time from trigger
conversion
Figure Timing chart of A/D conversion
Table A/D conversion time (SCLK=40MHz)

[μs]
fsys=80MHz fsys=40MHz
Trigger MIN MAX MIN MAX
Delay time from PMD 0.125 0.163 0.225 0.3
trigger TMRB 0.125 0.263 0.225 0.5
(Note 1) Software, Constant 0.138 0.275 0.25 0.525
AD conversion time － 1.85 1.85
Delay time to the PMD 0.1 0.125 0.175 0.225
next conversion TMRB, Software, Constant 0.1 0.238 0.175 0.425
(Note 2)
Note 1: Delay time from trigger to start of AD conversion.
Note 2: Delay time to the 2nd or after conversion in plural conversions with one trigger.

TMPM370
17.4.3 AD Conversion Monitoring Function
The ADCs have the AD conversion monitoring function. When this function is enabled, an
interrupt is generated when a conversion result matches the specified comparison value.
To enable the monitoring function, set ADxCMPCR0<CMP0EN> or ADxCMPCR1<CMP1EN> to
“1”. In the monitoring function, if the value of AD conversion result register to which the monitoring
function is assigned corresponds to the comparison condition specified by ADxCMCR< ADBIG0>,
the interrupt (INTADxCPA for ADxCMPCR0, INTADxCPB for ADxCMPCR1) is generated. The
comparison is executed at the timing of storing the conversion result into the register.
Note 1: The AD conversion result store flag (ADRxRF) is not cleared by the comparison function.
Note 2: The comparison function differs from reading the conversion result by software. Therefore, if
the next conversion is completed without reading the previous result, the overrun flag (OVRs)
is set.

TMPM370
17.5 Timing chart of AD conversion
The following shows a timing chart of software trigger conversion, constant conversion and acceptance of
trigger.
17.5.1 Software trigger Conversion
In the software trigger conversion, the interrupt is generated after completion of conversion programmed by
ADxSSET03, ADxSSET47 and ADxSSET811.
If the ADxMOD1<ADEN> is cleared to “0” during AD conversion, the ongoing conversion stops without storing
to the result register.
Fig 17-3 Software trigger AD conversion
Fig 17-4 Writing “0” to ADEN during the software trigger AD conversion

TMPM370
17.5.2 Constant Conversion
In the constant conversion, if the next conversion completes without reading the previous result from the
conversion result register, the overrun flag is set to “1”. In this case, the previous conversion result in the
conversion result register is overwritten by the next result. The overrun flag is cleared by reading of the
conversion result.
Fig 17-5 Constant conversion

TMPM370
17.5.3 AD conversion by trigger
If the PMD trigger is occurred during the software trigger conversion, the ongoing conversion stops
immediately.
If the timer trigger is occurred during the software trigger conversion, the ongoing conversion stops after the
completion of ongoing conversion. After the completion of conversion by trigger, the software trigger
conversion starts from the beginning programmed by ADxSSET03, ADxxSSET47 and ADxxSSET811.
Fig 17-6 AD conversion by PMD trigger
Fig 17-7 AD conversion by timer trigger (1)

TMPM370
Fig 17-8 AD conversion by timer trigger (2)

TMPM370
17.6 Usage Examples
17.6.1 Successive Conversion Using PMD A (Three Shunts) and One ADC
The following shows a circuit diagram for AD conversion using one PMD for three shunts and
one ADC.
U AINA0 PMD0TRGn
(n = 0～5)
V AINA1 ADC A
W AINA2
6 PMD 0
INTADAPDA
Example ADC settings are shown below.
Program 0 1 2 3 4 5
reg0 U V W V W U
reg1 V W U U V W
INT A A A A A A
Programs 0 to 5 are assigned to trigger inputs PMD0TRG0 to 5. “reg0” and “reg1” indicate the
PMD Trigger Program Registers ADAPSETn0 and ADAPSETn1. “U”, “V” and “W” indicate the
phases of a motor. AIN inputs are selected to obtain these phases.
When a trigger input occurs, AD conversion is performed based on reg0 and reg1 sequentially, and
then the interrupt signal (INTADAPDA) is generated.

TMPM370
17.6.2 Simultaneous Conversion Using One PMD (Three Shunts) and Two ADCs
The following shows a block diagram for AD conversion using one PMD for three shunts and two
ADCs.
U AINA0 PMD0TRGn
(n = 0～2)
V AINA1
W AINA2
ADC A 3 PMD 0
INTADAPDA
PMD0TRGn
(n = 0～2)
AINB0
AINB1
ADC B 3
AINB2
INTADBPDA
ADC A
Program 0 1 2
reg0 U V W
INT A A A
ADC B
Program 0 1 2
reg0 V W U
INT A A A
Programs 0 to 2 are assigned to three trigger inputs to ADC A and ADC B. “reg0” indicates the
PMD Trigger Program Register ADAPSETn0 and ADBPSETn0. “U”, “V” and “W” indicate the
phases of a motor. AIN inputs are selected to obtain these phases.
When a trigger input occurs, ADC A and ADC B are started simultaneously to perform AD
conversion based on reg0, and the interrupt signals (INTADAPDA , INTADBPDA) are output to
ADC A and ADC B.

TMPM370
17.6.3 Successive Conversion Using PMD A (Three Shunts), PMD B (One Shunt)
and Two ADCs
The following shows a circuit diagram for AD conversion using one PMD for three shunts, one
PMD for one shunt and two ADCs.
U AIN0 PMD0TRGn
(n = 0～5)
V AIN1
W AIN2
ADC A 6 PMD 0
R AIN5C
INTADAPDA
INTADAPDB
PMD1TRGn
(n = 6, 7)
AIN0 2
AIN1 PMD 1
ADC B
AIN2C

ADC A
PMD0 PMD0 PMD0 PMD1 PMD1

Trigger
0 ,3 1,4 2,5 6 7
Program 0 1 2 3 4
reg0 PMD0 U PMD0 V PMD0 W
reg1 R
reg2 R
INT A A A - B
ADC B
PMD0 PMD0 PMD0
Trigger
0 ,3 1,4 2,5
Program 0 1 2
reg0 PMD0 V PMD0 W PMD0 U
INT - - -
In ADC A, programs 0 to 2 are assigned to six trigger signals from PMD0 and programs 3 and 4
are assigned to two trigger signals from PMD1. In ADC B, programs 0 to 2 are assigned to six
trigger signals from PMD0. “reg0”, “reg1” and “reg2” indicate the PMD Trigger Program Registers
ADxPSETn0, ADxPSETn1 and ADxPSETn2 (x=A,B : ADC Unit). “U”, “V” and “W” indicate the

TMPM370
phases of a motor. AIN inputs are selected to obtain these phases. “R” indicates a resistor, where
the AIN that is connected to that resistor is set.
When a trigger input occurs, ADC A or ADC B is started to perform AD conversion. In ADC A, the
interrupt (INTADAPDA) is generated for a trigger from PMD0 and the interrupt (INTADAPDB) is
generated for a trigger from PMD1. In ADC B, interrupt generation is disabled in this example.
17.6.4 Successive Conversion Using One PMD (One Shunt) and One ADC
The following shows a circuit diagram for AD conversion using one PMD for one shunt and one
ADC.
R AINA0 PMD0TRGn
(n = 0, 1)
ADC A 2 PMD 0
INTADAPDA
PMD0 PMD0
Trigger
0 1
Program 0 1
reg0 R -
reg1 - R
INT - A
Programs 0 and 1 are assigned to two trigger signals from PMD0. “reg0” and “reg1” indicate the
PMD Trigger Program Registers ADAPSETn0 and ADAPSETn1. “R” indicates a resistor, where
the AIN input that is connected to that resistor is set.
When a trigger input occurs, the ADC is started to execute programs 0 and 1 sequentially. When
program 1 is completed, the interrupt (INTADAPDA) is generated.

TMPM370
18．Op-Amps/Analog Comparators
The TMPM370 has four op-amps and analog comparators. Each op-amp amplifies a voltage
received via an input port and feeds its output voltage into a 12-bit successive-approximation
analog-to-digital (A/D) converter(s). These op-amps are used to amplify voltage differentials
across shunt resistors for motor current measurement. The output of each op-amp is also fed into
an analog comparator and compared to the corresponding reference voltage derived from an
external resistor. The comparator provides an abnormal current indication to the EMG logic.
Figure 18-1 shows the block diagram of the op-amps/analog converters.
AVDDA
/ VREFHA
PH0 (AINA0) AINA0

PH1 (AINA1) AINA1 AVSSA
CPU / VREFLA
: :
: : ADC A VE
: : PMD0 TRG0 to 5
P10 (AINA8) AINA8 PMD1 TRG0 to 5
AINA9 INTTB51
AINA10 INTADAPDA/ B
AINA11 INTADACPA/ B
AINA12 (AMP A) INTADASFT
AINA13 (AMP B) INTADATMR
AINA14 (AMP C) PMD0 OVV
PI1 (AINA9/ AINB0) AMP A
1-shunt or CMP A
3-shunt resistor
circuit for PI2 (AINA10/ AINB1) AMP B PMD0 EMG
Channel-0 CMP B
current
PI3 (AINA11/ AINB2) AMP C
CMP C
CMP A/ B/ C Ref. Voltage PMD1 EMG

(CVREFABC)
AINB0 PMD1 OVV
Common VDD/VSS for AMPVDD
AINB1 INTADBSFT
AMPs and CMPs
AMPVSS AINB2 INTADBTMR
1-shunt resistor ANIB3 INTADBPDA/ B
PJ0 (AINB3) AMP D
circuit for CMP D INTADBCPA / B
Channel-1 CMP D Ref. Voltage
(CVREFD) ADC B INTTB51
current
PJ1 (AINB4) PMD0 TRG0 to 5
AINB4
PMD1 TRG0 to 5
: :
: : CPU
: :
PK1 (AINB12) AINB12 VE AVDDB
AINB13 (AMP A) / VREFHB
AINB14 (AMP B)
AINB15 (AMP C)
AVSSB
AINB16 (AMP D)
/ VREFLB
Figure 18-1 Op-Amps/Analog Converters Block Diagram
TMPM370 18-1 Op-Amps/Analog Converters

TMPM370
Op-amps A, B and C (AMP A/B/C) are intended to be used for 3-shunt current sensing. The
amplified voltages from AMP A/B/C are fed into two A/D converters to allow simultaneous
conversions of two shunt voltages out of three corresponding to the U, V and W phases of a motor.
The inputs of AMP A/B/C are also connected with the A/D converters (AINA 9/10/11, AINB13/
14/15) directly; thus, even if AMP A/B/C are disabled, two shunt voltages can be converted into
digital values at a time.
Op-amp D (AMP D) only supports 1-shunt current sensing. The amplified voltage from AMP D is
fed into one A/D converter (AINB16).
See the block diagram of the op-amps/analog converters shown in Figure 18-1.
Analog comparators A/B/C/D are all connected to op-amps A/B/C/D; thus the comparators can
compare an amplified voltage against the reference voltage. Each op-amp can be individually
disabled by software; if disabled, the corresponding comparator takes as input a shunt voltage
from an input port.
Analog comparators A/B/C, designed to be connected to a 3-shunt resistor circuit, have a
common reference voltage (CMPREFABC).
Analog comparator D is designed to be connected to a 1-shunt resistor circuit; it has an
independent reference voltage (CMPREFD).
ADC
AIN
CMPCTL<CMPSEL>
Analog Port
Input AMP
AMPCTL<AMPGLIN>
CMP PMD
Port Input EMG Signal
CMPREF
Figure 08-2 Op-Amp/Analog Comparator

TMPM370
18.1 Register List

The following table lists the control registers and their addresses for the op-amps and
analog comparators.
Register Address
Amp A Control Register AMPCTLA 0x4003_0400
Amp B Control Register AMPCTLB 0x4003_0408
Amp C Control Register AMPCTLC 0x4003_0410
Amp D Control Register AMPCTLD 0x4003_0418
Comparator A Control Register CMPCTLA 0x4003_0420
Comparator B Control Register CMPCTLB 0x4003_0428
Comparator C Control Register CMPCTLC 0x4003_0430
Comparator D Control Register CMPCTLD 0x4003_0438
18.2 Register Description

The op-amps are individually programmable through the Amp A/B/C/D Control Registers
(AMPCTLA/AMPCTLB/AMPCTLC/AMPCTLD), which allow software to enable and disable
each op-amp and select a voltage gain from eight levels.
The comparators are individually programmable through the Comparator A/B/C/D Control
Registers (CMPCTLA/CMPCTLB/CMPCTLC/CMPCTLD), which allow software to enable
and disable each comparator and select its input source (a port input or an op-amp output).
If an external op-amp is used instead of an on-chip op-amp, the on-chip op-amp should be
disabled (AMPENx = 0) and the comparator should be configured to accept the input port
voltage, bypassing the associated op-amp (CMPSELx = 0).
The following describes each control register.

TMPM370
Amp A/B/C/D Control Registers

7 6 5 4 3 2 1 0
AMPCTLx Bit Symbol AMPGLIN2 AMPG LIN1 AMPGLIN0 AMPEN
(x: A,B,C,D) Read/Write R R R R R/W R/W
Default 0 0 0 0 000 0
Reading Reading Reading Reading Gain Select AMP
this bit this bit this bit this bit 000: 1.5x 100: 4.0x Enable
Description returns a returns a returns a returns a 001: 2.5x 101: 6.0x 0: Standby
0. 0. 0. 0. 010: 3.0x 110: 8.0x 1: Enables
011: 3.5x 111: 10.0x AMP.
Note: When AMPEN is set to “1”, it takes approx. 10us to stabilize the circuit.
Comparator A/B/C/D Control Registers

7 6 5 4 3 2 1 0
CMPCTLx Bit Symbol CMPSEL CMPEN
(x: A,B,C,D) Read/Write R R R R R R R/W R/W
Default 0 0 0 0 0 0 0 0
Reading Reading Reading Reading Reading Reading Input CMP
this bit this bit this bit this bit this bit this bit Select Enable
returns a returns a returns a returns a returns a returns a 0: Input 0: Standby
Description port 1: Enables
0. 0. 0. 0. 0. 0.
1: Op-amp CMP.
output
Note: When CMPEN is set to “1”, it takes approx. 10us to stabilize the circuit.

TMPM370
19. Encoder Input Circuit (ENC)

The TMPM370FY has a two-channel incremental encoder interface (ENC0,1), which can determine the
direction and the absolute position of a motor, based on input signals from an incremental encoder.
The discussions in this chapter apply to ENC0. For ENC1, the names of registers, interrupt signals and
pins in the following text should be replaced as appropriate, as shown in Table 19.1 to Table 19.3.
Table 19.1 List of the ENC Registers
ENC0 ENC1
Register Register Register
Address Address
Symbol Symbol
Encoder Input Control Register EN0TNCR 0x4001_0400 EN1TNCR 0x4001_0500
Encoder Counter Reload Register EN0RELOAD 0x4001_0404 EN1RELOAD 0x4001_0504
Encoder Compare Register EN0INT 0x4001_0408 EN1INT 0x4001_0508
Encoder Counter EN0CNT 0x4001_040C EN1CNT 0x4001_050C
Table 19.2 Interrupt Sources
Interrupt Source ENC0 ENC1

ENC interrupt INTENC0 INTENC1
Table 19.3 Pin Names
Pin ENC0 ENC1

Channel A input pin PD0/ENCA0 PF2/ENCA1
Channel B input pin PD1/ENCB0 PF3/ENCB1
Channel Z input pin PD2/ENCZ0 PF4/ENCZ1
TMPM370 19-1 Encoder Input Circuit

TMPM370
19.1 Outline
The ENC can be configured to operate in one of four different modes: Encoder mode, two Sensor
modes (Event count mode, Timer count mode) and Timer mode. And it also has some functions as
below.
z Supports incremental encoders and Hall sensor ICs. (signals of Hall sensor IC can be input
directly)
z 24-bit general-purpose timer mode
z Multiply-by-4 (multiply-by-6) logic
z Direction discriminator
z 24-bit counter
z Comparator enable/disable
z Interrupt request output
z Digital noise filters for input signals
Noise
ENCA0
Filter
Interrupt
Request Interrupt
Noise Input Decoder Counter
ENCB0 Request
Filter Selector Control
INTENC0
Noise
ENCZ0
Filter
Figure 19.1 ENC Block Diagram

TMPM370
19.1.1 Encoder Mode
In Encoder mode, the ENC provides high-speed position tracking, based on the A/B or A/B/Z input
signals from an incremental encoder.
z Event (rotation pulse) sensing: Programmable to generate an interrupt on each event.

z Event counter: Programmable to generate an interrupt at a preset count (for positional
displacement calculation).
z Direction discrimination
z Up/down counting (dynamically selectable)
z Programmable counter period
19.1.2 Sensor Modes
In Sensor modes, the ENC provides low-speed position (zero-cross) tracking, based on either the
U/V or U/V/W input signals from a Hall sensor.
There are two operating modes: Event Count mode and Timer Count mode (which runs with fsys).
19.1.2.1 Event Count Mode

z Event counter: Programmable to generate an interrupt at a preset count (for positional
displacement calculation).
19.1.2.2 Timer Count Mode

z Timer counting operation
z Input capture functions
Event capture (event interval measurement): Programmable to generate an interrupt.
Software capture
z Event timeout error (timer compare): Programmable to generate an interrupt at a preset
count.
z Revolution error: Error flag that indicates a change of the rotation direction
19.1.3 Timer Mode
The ENC can serve as a 24-bit general-purpose timer.
z 24-bit up-counter
z Counter clear: via a software clear bit, or at a preset count, or by an external trigger input, or on
overflow of the free-running counter.

TMPM370
z Timer compare: Programmable to generate an interrupt at a preset count.

z Input capture functions
External trigger capture: Programmable to generate an interrupt.
Software capture

TMPM370
19.2 Control Registers
Encoder 0 Input Control Register

EN0TNCR 31 30 29 28 27 26 25 24
(0x4001_0400) Bit Symbol - - - - - - - -
Default 0 0 0 0 0 0 0 0
Description Reading these bits returns a 0.
23 22 21 20 19 18 17 16
Bit Symbol - - - - - MODE1 MODE0 P3EN
Read/Write R R R R R R/W R/W R/W
Default 0 0 0 0 0 0 0 0
ENC Operating Mode [In Sensor
00: Encoder mode mode]
01: Sensor Event Count mode 2/3-Phase
Description Reading these bits returns a 0. 10: Sensor Timer Count mode Input Select
0: 2-phase
11: Timer mode 1: 3-phase
15 14 13 12 11 10 9 8
Bit Symbol CMP REVERR UD ZDET SFTCAP ENCLR ZESEL CMPEN
Read/Write R R R R W W R/W R/W
Default 0 0 0 0 0 0 0 0
Compare [In Sensor Rotation Z_ Detected [In Sensor Encoder [In Timer Compare
Flag Timer Count Direction 0: Not Timer Count Counter mode] Enable
0: － mode] 0: CCW detected and Timer Clear Z Trigger 0: Compare
1: Counter Revolution 1: CW 1: Z phase modes] 0: － Edge Select disabled
compared Error detected Software 1: Clears the 0: Rising 1: Compare
0: － Capture counter. edge enabled
Description This bit is 1: Error 0: － 1: Falling
cleared on a occurred. 1: Software edge
read. capture
This bit is
cleared on a
read.
7 6 5 4 3 2 1 0
Bit Symbol ZEN ENRUN NR1 NR0 INTEN ENDEV2 ENDEV1 ENDEV0
Default 0 0 0 0 0 0 0 0
Z Phase ENC Run Noise Filter ENC Encoder Pulse Division Factor
Enable 0: Disabled 00: No filtering Interrupt 000: ÷ 1
0: Disabled 1: Enabled 01: Filters out pulses narrower Enable
1: Enabled than 31/fsys (387.5 ns@80 0: Disabled 001: ÷ 2
MHz). 1: Enabled 010: ÷ 4
Description 10: Filters out pulses narrower 011: ÷ 8
than 63/fsys(787.5 ns@80 100: ÷ 16
MHz).
11: Filters out pulses narrower 101: ÷ 32
than 127/fsys(1587 ns@80 110: ÷ 64
MHz). 111: ÷ 128
Description:
<MODE1:0>: ENC Operating Mode

00: Encoder mode
01: Sensor Event Count mode
10: Sensor Timer Count mode
11: Timer mode
<MODE1:0> selects an operating mode for the ENC.

TMPM370
Operating modes are defined by <MODE1:0>, <P3EN> and <ZEN> as shown in the following table.
There are a total of eight operating modes.
Input signal
<MODE1> <MODE0> <ZEN> <P3EN> Operating Mode
Used
0 A, B Encoder mode
0 0 0
1 A, B, Z Encoder mode (using Z)
0 U, V Sensor Event Count mode (2 phase inputs)
0 1 0
1 U, V, W Sensor Event Count mode (3 phase inputs)
0 U, V Sensor Timer Count mode (2 phase inputs)
1 0 0
1 U, V, W Sensor Timer Count mode (3 phase inputs)
0 - Timer mode
1 1 0
1 Z Timer mode (using Z)
<P3EN>: 2/3-Phase Input Select

0: 2-phase
1: 3-phase
<P3EN> selects the number of phase input pins used.

If <P3EN> is cleared to 0, the ENC decodes two phase inputs.
If <P3EN> is set to 1, the ENC decodes three phase inputs.
Note: <P3EN> must always be cleared in Encoder mode and Timer mode , irrespective of the number
of phase input pins used.
<CMP>: Compare Flag

0: －
1: Counter compared
<CMP> is set to 1 when the counter value has been compared to the value programmed in the
EN0INT register.
<CMP> is cleared to 0 on a read. <CMP> remains cleared when <ENRUN> = 0. Writing to <CMP> has
no effect.
<REVERR>: Revolution Error

0: －
1: Error occurred.
In Sensor Timer Count mode, <REVERR> is set to 1 when a change in the rotation direction has been
detected. <REVERR> is cleared to 0 on a read. <REVERR> remains cleared when <ENRUN> = 0.
Writing to <REVERR> has no effect.
This bit has an effect only in Sensor Timer Count mode.
Note: Once software has changed the operating mode of the ENC, <REVERR> must be cleared by
reading it.
<UD>: Rotation Direction

0: Counterclockwise (CCW)
1: Clockwise (CW)
The quadrature signals A and B identify the motor rotation direction. <UD> is set to 1 when the CW
direction is indicated (signal A of the incremental encoder signal is ahead of signal B). <UD> is cleared
to 0 when the CCW direction is indicated (signal A is behind signal B). <UD> remains cleared while
<ENRUN> = 0.

TMPM370
<ZDET>: Z Detected
0: Not detected
1: Detected
<ZDET> is set to 1 on the first edge of Z input signal (ENCZ) after <ENRUN> is written from 0 to 1. This
occurs on a rising edge of the signal Z during CW rotation or on a falling edge of Z during CCW rotation.
<ZDET> remains cleared while <ENRUN> = 0.
<ZEN> has no influence on the value of <ZDET>.
<ZDET> remains cleared in Sensor Event Count and Sensor Timer Count modes.
<SFTCAP>: Software Capture

0: －
1: Software capture
If <SFTCAP> is set to 1, the value of the encoder counter is captured into the EN0CNT register.
Writing a 0 to <SFTCAP> has no effect. Reading <SFTCAP> always returns a 0.
In Encoder and Sensor Event Count modes, <SFTCAP> has no effect; a write of a 1 to this bit is
ignored.
<ENCLR>: Encoder Counter Clear

0: －
1: Clears the encoder counter.
Writing a 1 to <ENCLR> clears the encoder counter to 0. Once cleared, the encoder counter restarts
counting from 0. Writing a 0 to <ENCLR> has no effect. Reading <ENCLR> always returns a 0.
<ZESEL>: Z Trigger Edge Select

0: Uses a rising edge of the ENCZ as an external trigger input.
1: Uses a falling edge of the ENCZ as an external trigger input.
<ZESEL> selects the edge of the ENCZ that should be used as an external trigger in Timer mode.
In the other operating modes, <ZESEL> has no effect.
<CMPEN>: Compare Enable

0: Compare disabled
1: Compare enabled
If <CMPEN> is set to 1, the value of the encoder counter is compared to the value programmed in the
EN0INT register. If <CMPEN> is cleared to 0, this comparison is not done.
<ZEN>: Z Phase Enable

0: Disabled
1: Enabled
・ In Encoder mode
<ZEN> controls whether to clear the encoder counter (EN0CNT) on the rising or falling edge of Z.
When <ZEN> = 1, the encoder counter is cleared on the rising edge of the ENCZ input if the
motor is rotating in the CW direction; the encoder counter is cleared on the falling edge of ENCZ if
the motor is rotating in the CCW direction. If the edges of ENCLK (multiply_by_4 clock derived from
the decoded A and B signals) and the edge of ENCZ coincide, the encoder counter is cleared to 0
without incrementing or decrementing (i.e., the clear takes precedence).

TMPM370
・ In Timer mode
<ZEN> controls whether to use the ENCZ signal as an external trigger input.
When <ZEN> = 1, the value of the encoder counter is captured into the EN0INT register and
cleared to 0 on the edge of ENCZ selected by <ZESEL>.
In the other operating modes, <ZEN> has no effect.
<ENRUN>: ENC Run

0: Disabled
1: Enabled
Setting <ENRUN> to 1 and clearing <ZDET> to 0 enables the encoder operation.

Clearing <ENRUN> to 0 disables the encoder operation.
There are counters and flags that are and are not cleared even if the <ENRUN> bit is cleared to 0.
The following table shows the states of the counters and flags, depending on the value of <ENRUN>.
When <ENRUN> = When <ENRUN> = 1

When <ENRUN> = 0 How to clear a counter or flag
Internal Counter / Flag 0 (During active
(During idle mode) when <ENRUN> = 0
(After reset) operation)
Encoder counter Keeps the current Software clear

0x000000 Counting
value. (Write a 1 to <ENCLR>.)
Counting up
Noise filter counter
0y0000000 Counting up (Continues with noise Cleared only by reset.
filtering.)
Encoder pulse division
0x00 Counting down Stopped and cleared Cleared when <ENRUN> = 0.
counter
Set to 1 upon
Compare flag
0 comparison; cleared Cleared Cleared when <ENRUN> = 0.
<CMP>
to 0 on a read.
Revolution Error flag Set to 1 upon an error;
0 Cleared Cleared when <ENRUN> = 0.
<REVERR> cleared to 0 on a read.
Z Detected flag Set to 1 on detection
0 Cleared Cleared when <ENRUN> = 0.
<ZDET> of Z.
Set or cleared
Rotation Direction Bit
0 according to rotation Cleared Cleared when <ENRUN> = 0.
<UD>
direction.
<NR1:0>: Noise Filter

00: No filtering
01: Filters out pulses narrower than 31/fsys as noises.
The digital noise filters remove pulses narrower than the width selected by <NR1:0>.
<INTEN>: ENC Interrupt Enable

0: Disabled
1: Enabled
<INTEN> enables and disables the ENC interrupt.

Setting <INTEN> to 1 enables interrupt generation. Clearing <INTEN> to 0 disables interrupt
generation.

TMPM370
<ENDEV2:0>: Encoder Pulse Division Factor

000: ÷1
001: ÷2
010: ÷4
011: ÷8
100: ÷16
101: ÷32
110: ÷64
111: ÷128
The frequency of the encoder pulse is divided by the factor specified by <ENDEV2:0>.
The divided signal determines the interval of the event interrupt.
Encoder 0 Counter Reload Register

EN0RELOAD 31 30 29 28 27 26 25 24
(0x4001_0404) Bit Symbol - - - - - - - -
Default 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol - - - - - - - -
Default 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit Symbol RELOAD15 RELOAD14 RELOAD13 RELOAD12 RELOAD11 RELOAD10 RELOAD9 RELOAD8
Default 0 0 0 0 0 0 0 0
Description (See the description below.)
7 6 5 4 3 2 1 0
Bit Symbol RELOAD7 RELOAD6 RELOAD5 RELOAD4 RELOAD3 RELOAD2 RELOAD1 RELOAD0
Default 0 0 0 0 0 0 0 0
Setting the Encoder Counter Period (Multiplied by 4 (or 6))
0x0000 thru. 0xFFFF
Description When Z is used: Specifies the number of counter pulses per revolution.
When Z is not used: Specifies the number of counter pulses per revolution minus 1.
Description:
<RELOAD15:0>: setting the Encoder Counter Period
Note: EN0RELOAD register should be accessed with 32-bit instructions.
・ In Encoder mode
<RELOAD15:0> defines the encoder counter period multiplied by 4.
If the encoder counter is configured as an up-counter, it increments up to the value programmed
in <RELOAD15:0> and then wraps around to 0 on the next ENCLK. If the encoder counter is
configured as a down-counter, it decrements to 0 and then is reloaded with the value of
<RELOAD15:0> on the next ENCLK.
The EN0RELOAD register is only used in Encoder mode.

TMPM370
Encoder 0 Compare Register
EN0INT 31 30 29 28 27 26 25 24
(0x4001_0408) Bit Symbol - - - - - - - -
Default 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol INT23 INT22 INT21 INT20 INT19 INT18 INT17 INT16
Default 0 0 0 0 0 0 0 0
See the description below.
Description <INT23:16> are used only in Sensor Timer Count mode and Timer mode
15 14 13 12 11 10 9 8
Default 0 0 0 0 0 0 0 0
Description See the description below.
7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0
In Encoder mode:
Generates an interrupt at the programmed encoder pulse count (0x0000 thru. 0xFFFF).
In Sensor Event Count mode:
Generates an interrupt at the programmed encoder pulse count (0x0000 thru. 0xFFFF).
Description In Sensor Timer Count mode:
Generates an interrupt when the counter has reached the programmed value without detecting a pulse (0x000000
thru. 0xFFFFFF).
In Timer mode:
Generates an interrupt when the counter value has reached the programmed value (0x000000 thru. 0xFFFFFF).
Description:
<INT23:0>: Counter Compare Value
Note: EN0INT register should be accessed with 32-bit instructions.
・ In Encoder mode
<CMP> is set to 1 when the value of the encoder counter has reached the value of <INT15:0>,
provided <CMPEN> is set to 1. At this time, the event counter interrupt (INTENC0) is asserted if
<INTEN> is set to 1.
However, when <ZEN> = 1, INTENC is not asserted until <ZDET> is set to 1. In Encoder mode,
<INT23:16> are not used (and are ignored even if programmed).
・ In Sensor Event Count mode

provided <CMPEN> is set to 1. At this time, the interrupt request (INTENC0) is asserted if
<INTEN> is set to 1. The value of <ZEN> has no effect on this interrupt generation.
In Sensor Event Count mode, <INT23:16> are not used (and are ignored even if programmed).
・ In Sensor Timer Count mode

provided <CMPEN> is set to 1. This indicates the absence of a pulse for an abnormally long period.
At this time, the interrupt request (INTENC0) is asserted if <INTEN> is set to 1. The value of <ZEN>
has no effect on this interrupt generation.
・ In Timer mode
provided <CMPEN> is set to 1. At this time, the timer compare interrupt (INTENC0) is asserted if
<INTEN> is set to 1. The value of <ZEN> has no effect on this interrupt generation.

TMPM370
Encoder 0 Counter Register
EN0CNT 31 30 29 28 27 26 25 24
(0x4001_040C Bit Symbol - - - - - - - -
Default 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit Symbol CNT23 CNT22 CNT21 CNT20 CNT19 CNT18 CNT17 CNT16
Default 0 0 0 0 0 0 0 0
See the description below.
Description <CNT23:16> are used only in Sensor Timer Count mode and Timer mode.
In Encoder mode and Sensor Event Count mode, reading these bits returns a 0.
15 14 13 12 11 10 9 8
Default 0 0 0 0 0 0 0 0
Description See the description below.
7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0
In Encoder mode:
Number of encoder pulses
0x0000 thru. 0xFFFF
In Sensor mode:
Description Pulse detection time or the encoder counter value captured under software control
0x000000 thru. 0xFFFFFF
In Timer mode:
Iencoder counter value captured by hardware signaling or under software control
0x000000 thru. 0xFFFFFF
Description:
<CNT23:0>: Encoder Counter/Captured Value
Note: EN0CNT register should be accessed with 32-bit instructions.
・ In Encoder mode
The value of encoder count.can be read out from <CNT15:0>.
In Encoder mode, the encoder counter counts up or down on each encoder pulse (ENCLK).
During CW rotation, encoder counter counts up; when it has reached the value of
<RELOAD15:0>, it wraps around to 0 on the next ENCLK.
During CCW rotation, encoder counter counts down; when it has reached 0, it is reloaded with the
value of <RELOAD15:0> on the next ENCLK.
・ In Sensor Event Count mode

The value of encoder count.can be read out from <CNT15:0>.
In Sensor Event Count mode, the encoder counter counts up or down on each encoder pulse
(ENCLK).
During CW rotation, encoder counter counts up; when it has reached0xFFFF, it wraps around to
0 on the next ENCLK.
During CCW rotation, encoder counter counts down; when it has reached 0, it wraps around to
0xFFFF on the next ENCLK.

TMPM370
・ In Sensor Timer Count mode

<CNT23:0> contains the value of the encoder counter captured by either the encoder pulse
(ENCLK) or software setting <SFTCAP> to 1. The captured value in <CNT23:0> is cleared to 0 on
system reset. It can also be cleared by clearing the counter via setting <ENCLR> to 1 and then
setting <SFTCAP> to 1.
In Sensor Timer Count mode, the encoder counter is configured as a free-running counter that
counts up with fsys. The encoder counter is cleared to 0 when the encoder pulse (ENCLK) is
detected. When it has reached 0xFFFFFF, it wraps around to 0 automatically.
・ In Timer mode
<CNT23:0> contains the value of the encoder counter captured by software setting <SFTCAP> to
1. When <ZEN> = 1, the value of the encoder counter is also captured into <CNT23:0> on the Z
ENCZ edge selected by <ZESEL>.
In Timer mode, the encoder counter is configured as a free-running counter that counts up with
fsys. When it has reached 0xFFFFFF, it wraps around to 0 automatically.

TMPM370
19.3 Functional Description
19.3.1 Operating Modes

19.3.1.1 Encoder Mode
(1) When <ZEN> = 1 (<RELOAD> = 0x0380, <EN0INT> = 0x0002)
fsys
Encoder Input, A
Encoder Input, B
Encoder Input, Z
Encoder Pulse, ENCLK
Internal Z_Detected
Z Detect, <ZDET>
dir
CW CCW
Rotation Direction
Counter Clear, ENCLR
(÷2) TIMPLS
Encoder Counter 110 111 112 0 1 2 3 0 1 0 380 37E 37D 0 380 37F
Interrupt, INTENC0
(2) When <ZEN> = 0 (<RELOAD> = 0x0380, <EN0INT> = 0x0002)
ｆｓｙｓ
Encoder Input, A
Encoder Input, B
Encoder Input, Z
Internal Z_Detected
Z Detect, <ZDET>
dir
CW CCW
Rotation Direction
(÷2) TIMPLS
Encoder Counter, encnt 110 111 112 113 0 1 2 0 1 0 380 37F 37E 37D 37C
Interrupt, INTENC0
・ In Encoder mode, the incremental encoder inputs of the TMPM370 should be connected to the A,
B and Z channels. The encoder counter counts pulses of ENCLK, which is multiplied_by_4 clock
derived from the decoded A and B quadrature signals.
・ During CW rotation (i.e., when A leads B), the encoder counter counts up; when it has reached
the value of <RELOAD>, it wraps around to 0 on the next ENCLK.
・ During CCW rotation (i.e., when A lags B), the encoder counter counts down; when it has reached
0x0000, it is reloaded with the value of <RELOAD> on the next ENCLK.
・ Additionally, when <ZEN> = 1, the encoder counter is cleared to 0 on the rising edge of Z during
CW rotation and on the falling edge of Z during CCW rotation (at the internal Z_Detected timing).

TMPM370
If the ENCLK and Z edges coincide, the encoder counter is cleared to 0 without incrementing or
decrementing.
・ When <ENCLR> is set to 1, causing the encoder counter to be cleared to 0.
・ <UD> is set to 1 during CW rotation and cleared to 0 during CCW rotation.
・ TIMPLS, which is derived by dividing ENCLK by a programmed factor, can be driven out
externally.
・ If <CMPEN> is set to 1, an interrupt is generated when the value of the encoder counter has
reached the value of <EN0INT>. When <ZEN> = 1, however, an interrupt does not occur while
<ZDET> = 0.
・ Clearing <ENRUN> to 0 clears <ZDET> and <UD> to 0.
19.3.1.2 Sensor Event Count Mode
(1) When <P3EN> = 1 (<EN0INT> = 0x0002)
fsys
Encoder Input, U
Encoder Input, V
Encoder Input, W
dir
CW CCW
Rotation Direction
(÷2) TIMPLS
Encoder Counter FFFC FFFD FFFE FFFF 0 1 2 3 2 1 0 FFFF FFFE FFFD FFFC FFFB FFFA
Interrupt, INTENC0
(2) When <P3EN> = 0 (<EN0INT> = 0x0002)

fsys
Encoder Input, U
Encoder Input, V
Encoder Input, W
dir
CW CCW
Rotation Direction
(÷2) TIMPLS
Encoder Counter FFFC FFFD FFFE FFFF 0 1 2 3 2 1 0 FFFF FFFE FFFD FFFC FFFB FFFA
Interrupt, INTENC0
・ In Sensor Event Count mode, the Hall sensor inputs of the TMPM370 should be connected to the
U, V and W channels. The encoder counter counts the pulses of ENCLK, which is either
multiplied_by_4 clock (when <P3EN> = 0) derived from the decoded U and V signals or
multiplied_by_6 clock (when <P3EN> = 1) derived from the decoded U, V and W signals.
・ During CW rotation, the encoder counter counts up; when it has reached 0xFFFF, it wraps around
to 0 on the next ENCLK.
・ During CCW rotation, the encoder counter counts down; when it has reached 0x0000, it wraps
TMPM370
around to 0xFFFF on the next ENCLK.
・ When <ENCLR> is set to 1, causing the internal counter to be cleared to 0.
・ TIMPLS, which is derived by dividing ENCLK by a programmed factor, can be driven out
externally.
・ If <CMPEN> is set to 1, an interrupt is generated when the value of the internal counter has
reached the value of <EN0INT>.
・ Clearing <ENRUN> to 0 clears <UD> to 0.
19.3.1.3 Sensor Timer Count Mode
(1) When <P3EN> = 1 (<EN0INT> = 0x0002)
fsys
Encoder Input, U
Encoder Input, V
Encoder Input, W
dir
CW CCW
Rotation Direction
(÷2) TIMPLS
Encoder Counter 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 2 3 0 1 2 0 １ 2 3 0 １ 2 3 0 １ 2 3 0 １ 2
Capture Register, EN0CNT 0 (ini) 3 3 2 3
Interrupt, INTENC0
Revolution Error, REVERR
(2) When <P3EN> = 0 (<EN0INT> = 0x0002)

fsys
Encoder Input, U
Encoder Input, V
Encoder Input, W
dir
CW CCW
Rotation Direction
(÷2) TIMPLS
Encoder Counter 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 2 3 0 1 2 0 １ 2 3 0 １ 2 3 0 １ 2 3 0 １ 2
Capture Register, EN0CNT 0 (ini) 3 3 2 3
Interrupt, INTENC0
Revolution Error, REVERR
・ In Sensor Timer Count mode, the Hall sensor inputs of the TMPM370 should be connected to the
U, V and W channels. The encoder counter measures the interval between two contiguous
pulses of ENCLK, which is either multiplied_by_4 clock (when <P3EN> = 0) derived from the
decoded U and V signals or multiplied_by_6 clock (when <P3EN> = 1) derived from the decoded
U, V and W signals.
・ The encoder counter always counts up; it is cleared to 0 on ENCLK. When the encoder counter
has reached 0xFFFFFF, it wraps around to 0.
TMPM370
・ ENCLK causes the value of the encoder counter to be captured into the EN0CNT register. The
captured counter value can be read out of EN0CNT.
・ Setting the software capture bit, <SFTCAP>, to 1 causes the value of the encoder counter to be
captured into the ENCNT register. This capture operation can be performed at any time. The
captured counter value can be read out of ENCNT.
reached the value of <EN0INT>.
・ <REVERR> is set to 1 when the rotation direction has changed. This bit is cleared to 0 on a read.
・ The value of the ENCNT register (the captured value) is retained, regardless of the value of
<ENRUN>. The ENCNT register is only cleared by a reset.

TMPM370
19.3.1.4 Timer Mode
(1) When <ZEN> = 1 (<EN0INT> = 0x0006)
ｆｓｙｓ
Encoder Input, A
Encoder Input, B
Encoder Input, Z
IEncoder Pulse, ENCLK
Internal Z_Detected
dir
CW CCW
Rotation Direction
Z Edge Select, ZESEL
(÷2) TIMPLS
Encoder Counter 2 3 4 5 6 7 8 9 A B 0 1 2 3 4 31 32 33 34 35 36 37 38 39 40 41 0 1 2 3 4 5 6 7 8
Capture Register, EN0CNT 0 (ini) B B 41
Interrupt, INTENC0
Compare Interrupt Capture Interrupt Capture Interrupt Compare Interrupt
(2) When <ZEN> = 0 (<EN0INT> = 0x0006)
ｆｓｙｓ
Encoder Input, A
Encoder Input, B
Encoder Input, Z
Internal Z_Detected
dir
CW CCW
Rotation Direction
Z Edge Select, ZESEL
Soft Capture SFTCAP
(÷2) TIMPLS
Encoder Counter 2 3 4 5 6 7 8 9 A B C D E F 10 31 32 33 34 35 36 0 1 2 3 4 5 6 7 8 9 A B C D
Capture Register, EN0CNT 0 (ini) A A
Interrupt, INTENC0
Compare Interrupt Compare Interrupt
・ When <ZEN> = 1, the Z input pin is used as an external trigger. When <ZEN> = 0, no external
input is used to trigger the timer.
・ The encoder counter always counts up. If <ZEN> = 1, the counter is cleared to 0 on the selected
edge of Z (at the internal Z_Detected timing): a rising edge when <ZESEL> = 0 and a falling edge
when <ZESEL> = 1. When the encoder counter has reached 0xFFFFFF, it wraps around to 0.
・ Z_Detected causes the value of the encoder counter to be captured into the ENCNT register. The
・ Setting the software capture bit, <SFTCAP>, to 1 causes the value of the encoder counter to be
TMPM370
captured into the ENCNT register. This capture operation can be performed at any time. The
reached the value of <ENINT>.
・ The value of the ENCNT register (the captured value) is retained, regardless of the value of
<ENRUN>. The ENCNT register is only cleared by a reset.

TMPM370
19.3.2 Counter Operation and Interrupt Generation When <CMPEN> =1
ｆｓｙｓ
Encoder Input, A
Encoder Input, B

The counter is cleared when its value
has reached the value of <RELOAD>.
ENRELOAD reg ＝0x0151
EN0INT reg ＝0x0150 Encoder Counter 0 1 2 3 14C 14D 14E 14F 150 131 0 1
(Compare Register) INTENC0 The counter is cleared when its value

(compare) has reached the value of <RELOAD>.
ENRELOAD reg ＝0xFFFF
EN0INT reg ＝0xFFFF Encoder Counter 0 1 2 3 14C 14D 14E 14F 150 151 152 FFFD FFFE FFFF 0 1 2
(Compare Register) INTENC0

(compare)
ｆｓｙｓ
Encoder Input, U
Encoder Input, V

The counter wraps
around to 0 on overflow.
EN0INT reg ＝0x0150
Encoder Counter 0 1 2 3 14C 14D 14E 14F 150 151 152 FFFD FFFE FFFF 0 1 2
(Compare Register)
Rotation Pulse Count INTENC0
(compare)
ｆｓｙｓ
U/V/W

• No event timeout error The counter is cleared by a rotation pulse.
EN0INT reg ＝0x0150 Encoder Counter 0 1 2 3 9E 9F 0 1 2 3 4 5
(Compare Register)
Event timeout period INTENC0
(Capture)
INTENC0
(compare)
• Event timeout error The counter wraps around to 0 on overflow.
EN0INT reg ＝0x0150 Encoder Counter 0 1 2 3 14C 14D 14E 14F 150 151 152 FFFD FFFE FFFF 0 1 2

Event timeout period (compare) The counter wraps around to 0 on overflow.
EN0INT reg ＝0xFFFF Encoder Counter 0 1 2 3 14C 14D 14E 14F 150 151 152 FFFD FFFE FFFF 0 1 2

Event timeout period (compare)
19.3.2.4 Timer Mode
ｆｓｙｓ
The counter is cleared when it
has reached the value of <INT>
EN0INT reg ＝0x0150 Encoderl Counter 0 1 2 3 14F 150 0 1 2
(Compare Register) INTENC0 The counter is cleared when it

(compare) has reached the value of <INT>
EN0INT reg ＝0xFFFF Encoder Counter 0 1 2 3 14F 150 151 152 FFFD FFFE FFFF 0 1 2

(compare)

TMPM370
19.3.3 Counter Operation and Interrupt Generation When <CMPEN> = 0

ｆｓｙｓ
<ENDEV> = 000
Encoder Input, A
Encoder Input, B

The counter is cleared when its value
ENRELOAD reg ＝0x0151 Encoder Counter 0 1 2 3 14C 14D 14E 14F 150 151 0 1
EN0INT reg ＝0x0150

INTENC0
(Compare Register) The counter is cleared when its value
(event)
ENRELOAD reg ＝0xFFFF Encoder Counter 0 1 2 3 14C 14D 14E 14F 150 151 152 FFFD FFFE FFFF 0 1 2
EN0INT reg ＝0xFFFF

(event)

ｆｓｙｓ
<ENDEV> = 000
Encoder Input, U
Encoder Input, V
Encoder Pulse, enclk

The counter wraps
around to 0 on overflow.
EN0INT reg ＝0x0150 Encoder Counter 0 1 2 3 14C 14D 14E 14F 150 151 152 FFFD FFFE FFFF 0 1 2

Rotation Pulse Count (event)
ｆｓｙｓ
U/V/W

• No event timeout error The counter is cleared by a rotation pulse
EN0INT reg ＝0x0150 Encoder Counter 0 1 2 3 9E 9F 0 1 2 3 4 5
(Compare Register)
Event timeout period INT ENC0
(compare)
INTENC0
(compare)
• Event timeout error The counter wraps around to 0 on overflow.
ENINT reg ＝0x0150 Encoder Counter 0 1 2 3 14C 14D 14E 14F 150 151 152 FFFD FFFE FFFF 0 1 2

Event timeout period (compare) The counter wraps around to 0 on overflow.
ENINT reg ＝0xFFFF Encoder Counter 0 1 2 3 14C 14D 14E 14F 150 151 152 FFFD FFFE FFFF 0 1 2

Event timeout period (compare)
19.3.3.4 Timer Mode
ｆｓｙｓ
ENINT reg ＝0x0150 Encode Counter 0 1 2 3 14F 150 0 1 2

(compare)
ENINT reg ＝0xFFFF Encoder 0 1 2 3 14F 150 151 152 FFFD FFFE FFFF 0 1 2
(Compare Register) C t
INTENC0
(compare)

TMPM370
19.3.4 Encoder Rotation Direction
The following diagrams illustrate the phase shifting of the A, B and Z channels.
The ENC can interface with both two-phase (A/B) and three-phase (A/B/Z) encoder inputs. For
three-phase encoder inputs, <P3EN> should be set to 1.
(1) Here are possible combinations of values of the A (U), B (V) and Z (W) signals during CW
rotation.
・For two-phase inputs
A 0 1 1 0 0 1
B 0 0 1 1 0 0
・For three-phase inputs
A 0 1 1 1 0 0 0 1 1
B 0 0 0 1 1 1 0 0 0
Z 1 1 0 0 0 1 1 1 0
(2) Here are possible combinations of values of the A (U), B (V) and Z (W) signals during CCW
rotation.
・For two-phase inputs
A 0 0 1 1 0 0
B 0 1 1 0 0 1
・For three-phase inputs
A 1 1 0 0 0 1 1 1 0
B 0 0 0 1 1 1 0 0 0
Z 0 1 1 1 0 0 0 1 1

TMPM370
19.3.5 Counter Block
The counter block consists of a 24-bit up/down counter and its control logic.
19.3.5.1 Overview
The counter is configured as an up-counter or a down-counter, cleared and reloaded with a programmed value,
according to the selected operating mode.
Table 19.4 summarizes how the counter is controlled.
Table 19.4 Counter Control

Counter
<P3EN>
<ZEN>
Operating Mode Input Counter Reload Range

Count Up/Down Counter Clear Conditions
<MODE1:0> Pins Conditions (Reload
Value)
[1] <ENCLR> is set to 1.

Encoder pulse Up -
0 A, B [2] counter=<RELOAD>
(ENCLK)
Down [1] <ENCLR> is set to 1. [1] counter=0x0000
Encoder Mode 0x0000 thru.
0
00 [1] <ENCLR> is set to 1. <RELOAD>
Encoder pulse Up [2] counter=<RELOAD> -
1 A, B, Z [3] Z trigger
(ENCLK)

Encoder pulse Up -
0 U, V [2] counter=16’hFFFF
(ENCLK)
Sensor Event Count Down [1] <ENCLR> is set to 1. [1] counter=0x0000 0x0000 thru.
Mode 0
0xFFFF
01 [1] <ENCLR> is set to 1.
Encoder pulse Up -
1 U, V, W [2] counter=0xFFFF
(ENCLK)
Sensor Timer Count 0 U, V fsys Up [1] <ENCLR> is set to 1.

0x000000
[2] counter=0xFFFFFF
Mode 0 thru.
[3] Encoder pulse
10 1 U, V, W fsys Up 0xFFFFFF
(ENCLK)

0 - fsys Up [2] counter=0xFFFFFF
[3] counter=<EN0INT> 0x000000
Timer Mode
X thru.
11 [1] <ENCLR> is set to 1. 0xFFFFFF
[2] counter=0xFFFFFF
1 Z fsys Up
[3] counter=<EN0INT>
[4] Z trigger
Note: Clearing <ENRUN> to 0 does not clear the counter.

Setting <ENRUN> to 1 again causes the counter to restart from the current count.
The counter should be cleared by software setting <ENCLR> to 1.

TMPM370
19.3.6 Interrupts
The ENC has these interrupts: event (divided-clock/capture) interrupt, event timeout interrupt, timer
compare interrupt and capture interrupt.
19.3.6.1 Overview
When <INTEN> = 1, the ENC generates interrupt requests, based on the counter value and the
detection of a encoder pulse.
There are six interrupt sources, depending on the operating mode, and the settings of
<CMPEN> and <ZEN>, as shown in Table 19.5 .
Table19.5 Interrupt Sources
Interrupt Status
Interrupt Source Description Operating Mode
Generation Flag
When <CMPEN> = 1, the encoderl counter

counts events (encoder pulses). When it has When <INTEN> = 1
1 Event counter interrupt reached the value programmed in and <CMP>
Encoder mode and <CMPEN> = 1
<EN0INT>, an interrupt occurs.
Sensor Event Count
An interrupt occurs on each divided clock modes
Event interrupt pulse, which is derived by dividing the
2 When <INTEN> = 1 None
(Divided clock pulse) encoder pulse by a factor programmed in
<ENDEV>.
An interrupt occurs to indicate that an event
Event interrupt (encoder pulse) has occurred, causing the
3 When <INTEN> = 1 None
(Capture interrupt) counter value to be captured.
When <CMPEN> = 1, the ENC uses a Sensor Timer Count
counter that counts up with fsys and is mode When <INTEN> = 1
cleared by an event (encoder pulse). If no
4 Event timeout interrupt and <CMP>
event occurs for a period of time
<CMPEN> = 1
programmed in <EN0INT>, an interrupt
occurs.
When <CMPEN> = 1, an interrupt occurs When <INTEN> = 1
5 Timer compare interrupt when the timer has reached the value and <CMP>
programmed in <EN0INT>. <CMPEN> = 1
Timer mode
An interrupt occurs when the counter value
6 Capture interrupt has been captured on an external trigger (Z When <INTEN> = 1 None
input).
In Sensor Timer Count mode and Timer mode, the value of the encoder counter can be
captured into the ENCNT register.
The captured counter value can be read out of the ENCNT register.
In Sensor Timer Count mode, the value of the encoder counter is captured into the ENCNT
register upon occurrence of an event (encoder pulse). The counter value can also be captured by
writing a 1 to <SFTCAP>.
In Timer mode, the counter value can be captured by writing a 1 to <SFTCAP>. If <ZEN> is set
to 1, the counter value can also be captured by an edge of the Z signal input selected via
<ZESEL>.

TMPM370
20. Flash Memory Operation

This section describes the hardware configuration and operation of the flash memory.
20.1 Flash Memory
20.1.1 Features
1) Memory capacity
The TMPM370FY contains flash memory. The memory sizes and configurations are shown
in the table below. Independent write access to each block is available. When the CPU is to
access the internal flash memory, 32-bit data bus width is used.
2) Write/erase time
Writing is executed per page. The TMPM370FY contains 64 words in a page.
Page writing requires 1.25ms (typical) regardless of number of words.
A block erase requires 0.1 sec. (typical).
The following table shows write and erase time per chip.
Product Memory Block Configuration # of Write Erase

Name Size 128KB 64KB 32KB 16KB Words Time Time
TMPM370FY 256KB 0 3 1 2 64 1.28sec 0.4sec
(Note) The above values are theoretical values not including data transfer time.
The write time per chip depends on the write method to be used by the user.
3) Programming method
The onboard programming mode is available for the user to program (rewrite) the device
while it is mounted on the user's board.
・The onboard programming mode
3-1) User boot mode
The user's original rewriting method can be supported.
3-2) Single boot mode
The rewriting method to use serial data transfer (Toshiba's unique method) can
be supported.
4) Rewriting method
The flash memory included in this device is generally compliant with the applicable JEDEC
standards except for some specific functions. Therefore, if the user is currently using an
external flash memory device, it is easy to implement the functions into this device.
Furthermore, the user is not required to build his/her own programs to realize complicated
write and erase functions because such functions are automatically performed using the
circuits already built-in the flash memory chip.
JEDEC compliant functions Modified, added, or deleted functions

• Automatic programming
• Automatic chip erase <Modified> Block protect (only software protection is supported)
• Automatic block erase <Deleted> Erase resume - suspend function
• Data polling/toggle bit
TMPM370 20-1 Flash Memory Operation

TMPM370
5) Protect/Security function
This device is also implemented with a read-protect function to inhibit reading flash memory
data from any external writer device. On the other hand, rewrite protection is available only
through command-based software programming; any hardware setting method to apply
+12VDC is not supported. See chapter 20 for details of ROM protection and security
function.
20.1.2 Block Diagram of the Flash Memory Section
Internal address bus
Internal data bus
Internal control bus
ROM controller
Control Address Data

Flash memory
Control Address latch Data latch

circuit
(includes
automatic Column decoder/sense amplifier
sequence
control)
Row decoder
Command
Flash memory cell
register
Erase block decoder
Fig. 20-1 Block Diagram of the Flash Memory Section

TMPM370
20.2 Operation Mode

This device has three operation modes including the mode not to use the internal flash memory.
Table 20-1 Operation Modes

Operation mode Operation details
Single chip mode After reset is cleared, it starts up from the internal flash memory.
Normal mode In this operation mode, two different modes, i.e., the mode to execute user application programs and the
mode to rewrite the flash memory onboard the user’s card, are defined. The former is referred to as
"normal mode" and the latter "user boot mode.
User boot mode The user can uniquely configure the system to switch between these two modes.
For example, the user can freely design the system such that the normal mode is selected when the port
"PA0" is set to "1" and the user boot mode is selected when it is set to "0."
The user should prepare a routine as part of the application program to make the decision on the
selection of the modes.
Single boot mode After reset is cleared, it starts up from the internal Boot ROM (Mask ROM). In the Boot ROM, an
algorithm to enable flash memory rewriting on the user’s set through the serial port of this device is
programmed. By connecting to an external host computer through the serial port, the internal flash
memory can be programmed by transferring data in accordance with predefined protocols.
Among the flash memory operation modes listed in the above table, the User Boot mode and the
Single Boot mode are the programmable modes. These two modes, the User Boot mode and the
Single Boot mode, are referred to as "Onboard Programming" modes where onboard rewriting of
internal flash memory can be made on the user's card.
Note: Regardless using or not using Single Boot mode, password must be written in password area.

TMPM370
Either the Single Chip or Single Boot operation mode can be selected by externally setting the level
of the BOOT (PF0) pin while the device is in reset status.
After the level is set, the CPU starts operation in the selected operation mode when the reset
condition is removed. Regarding the BOOT (PF0) pin, be sure not to change the levels during
operation once the mode is selected.
The mode setting method and the mode transition diagram are shown below:
Table 20-2 Operation Mode Setting

Pin
Operation mode
RESET BOOT (PF0)
Single chip mode 0→1 1
Single boot mode 0→1 0
Reset state
Single chip mode
Single
boot mode
User
Normal mode boot mode
Onboard
programming mode
User to set the
switch method
Fig. 20-2 Mode Transition Diagram
20.2.1 Reset Operation

To reset the device, ensure that the power supply voltage is within the operating voltage range,
that the internal oscillator has been stabilized, and that the RESET input is held at "0" for a
minimum duration of 12 system clocks (0.15 μs with 80MHz operation; the "1/1" clock gear
mode is applied after reset).
(Note 1) Regarding to power-on, refer to section “Power On Reset” and “Electric

Characteristics”.
(Note 2) While flash auto programming or deletion is in progress, at least 0.5 microseconds
of reset period is required regardless of the system clock frequency. In this
condition, it takes approx. 2 ms to enable reading after reset.

TMPM370
20.2.2 User Boot Mode (Single chip mode)

User Boot mode is to use flash memory programming routine defined by users. It is used when
the data transfer buses for flash memory program code on the old application and for serial I/O
are different. It operates at the single chip mode; therefore, a switch from normal mode in which
user application is activated at the single chip mode to User Boot Mode for programming flash is
required. Specifically, add a mode judgment routine to a reset program in the old application.
The condition to switch the modes needs to be set by using the I/O of TMPM370 in conformity
with the user’s system setup condition. Also, flash memory programming routine that the user
uniquely makes up needs to be set in the new application. This routine is used for
programming after being switched to User Boot Mode. The execution of the programming
routine must take place while it is stored in the area other than the flash memory since the
data in the internal flash memory cannot be read out during delete/ writing mode. Once
re-programming is complete, it is recommended to protect relevant flash blocks from
accidental corruption during subsequent Single-Chip (Normal mode) operations. All the
interruption including a non-maskable are inhibited at User Boot Mode.
(1-A) and (1-B) are the examples of programming with routines in the internal flash memory
and in the external memory. For a detailed description of the erase and program sequence,
refer to 19.3 On-board Programming of Flash Memory (Rewrite/Erase).

TMPM370
User Boot Mode

(1-A) Method 1: Storing a Programming Routine in the Flash Memory
(Step-1)
Determine the conditions (e.g., pin states) required for the flash memory to enter User Boot mode and
the I/O bus to be used to transfer new program code. Create hardware and software accordingly. Before
installing the TMPM370 on a printed circuit board, write the following program routines into an arbitrary
flash block using programming equipment.
(a) Mode judgment routine: Code to determine whether or not to switch to User Boot mode
(b) Programming routine: Code to download new program code from a host controller and
re-program the flash memory
(c) Copy routine: Code to copy the data described in (b) from the TMPM370 flash memory to either
the TMPM370 on-chip RAM or external memory device.
New Application
(Host) Program Code
(I/O)
(TMPM370)
Flash memory
Old Application Program
Code
[Reset Procedure]
(a) Mode Judgment Routine
(b) Programming Routine

RAM
(c) Copy routine
(Step-2)
After RESET is released, the reset procedure determines whether to put the TMPM370 flash memory in
User Boot mode. If mode switching conditions are met, the flash memory enters User Boot mode. (All
interrupts including NMI must be disabled while in User Boot mode.)
New Application
Flash memory (Host) Program Code
(TMPM370) (I/O)
0 → 1 RESET
Code
[Reset Procedure]
Conditions for
(a) Mode Judgment Routine entering User Boot
mode (defined by
(b) Programming routine
the user)
(c) Copy routine RAM

TMPM370
(Step-3)
Once transition to User Boot mode is occurred, execute the copy routine (c) to copy the flash
programming routine (b) to the TMPM370 on-chip RAM.
New Application
(Host) Program Code
(I/O)
(TMPM370)
Flash memory
Code

[Reset procedure]
(a) Mode judgment routine
RAM
(c) Copy routine
(Step-4)
Jump program execution to the flash programming routine in the on-chip RAM to erase a flash block
containing the old application program code.
New Application
(Host) Program Code
(I/O)
(TMPM370)
Flash memory
(Erased)
書き替えルーチン
[Reset procedure]
(c) Copy routine RAM

TMPM370
(Step-5)
Continue executing the flash programming routine to download new program code from the host
controller and program it into the erased flash block. Once programming is complete, turn on the
protection of that flash block.
New Application
(Host) Program Code
(I/O)
(TMPM370)
Flash memory
New Application
Program Code
書き替えルーチン
[Reset procedure]
RAM
(c) Copy routine
(Step-6)
Set RESET to “0” to reset the TMPM370. Upon reset, the on-chip flash memory is put in Normal mode.
After RESET is released, the CPU will start executing the new application program code.
(Host)
(TMPM370) (I/O)
Flash memory 0 → 1 RESET

New application
program code
[Reset procedure] Set to normal mode

RAM
(c) Copy routine

TMPM370
(1-B) Method 2: Transferring a Programming Routine from an External Host

(Step-1)
Determine the conditions (e.g., pin states) required for the flash memory to enter User Boot mode and
the I/O bus to be used to transfer new program code. Create hardware and software accordingly. Before
installing the TMPM370 on a printed circuit board, write the following program routines into an arbitrary
flash block using programming equipment.
(a) Mode judgment routine: Code to determine whether or not to switch to User Boot mode
(b) Transfer routine: Code to download new program code from a host controller
Also, prepare a programming routine shown below on the host controller:

(c) Programming routine: Code to download new program code from an external host controller and
re-program the flash memory
New application
(Host) program code
(I/O)
(c) Programming routine
(TMPM370)
Flash memory
Old application
program code
[Reset procedure]
RAM
(b) Transfer routine
(Step-2)
After RESET is released, the reset procedure determines whether to put the TMPM370 flash memory in
User Boot mode. If mode switching conditions are met, the flash memory enters User Boot mode. (All
interrupts including NMI must be disabled while in User Boot mode).
New application
(Host) program code
(I/O)
(TMPM370)
0 → 1 RESET
Flash memory
Old application
program code
Conditions for
[Reset procedure] entering User Boot
mode (defined by
(a) Mode judgment routine the user)
RAM

TMPM370
(Step-3)
Once User Boot mode is entered, execute the transfer routine (b) to download the flash programming
routine (c) from the host controller to the TMPM370 on-chip RAM.
New application
(Host) Program code
(I/O)
(TMPM370)
Flash memory
Old application
program code
[Reset procedure]
RAM
(Step-4)
Jump program execution to the flash programming routine in the on-chip RAM to erase a flash block
containing the old application program code.
New application
(Host) program code
(I/O)
(TMPM370)
Flash memory
(Erased)
[Reset procedure]
RAM

TMPM370
(Step-5)
Continue executing the flash programming routine to download new program code from the host
controller and program it into the erased flash block. Once programming is complete, turn on the
protection of that flash block.
New application
(Host) program code
(I/O)
(TMPM370)
Flash memory
New application
Program code
[Reset procedure]
RAM
(Step-6)
Set RESET to “0” low to reset the TMPM370. Upon reset, the on-chip flash memory is put in Normal
mode. After RESET is released, the CPU will start executing the new application program code.
(Host)
(I/O)
(TMPM370)
0 → 1 RESET
Flash memory
New application
program code
Set to normal mode
[Reset procedure]
RAM

TMPM370
20.2.3 Single Boot Mode

In Single Boot mode, the flash memory can be re-programmed by using a program contained in
the TMPM370 on-chip boot ROM. This boot ROM is a masked ROM. When Single Boot mode is
selected upon reset, the boot ROM is mapped to the address region including the interrupt
vector table while the flash memory is mapped to an address region different from it.
Single Boot mode allows for serial programming of the flash memory. Channel 0 of the SIO
(SIO0) of the TMPM370 is connected to an external host controller. Via this serial link, a
programming routine is downloaded from the host controller to the TMPM370 on-chip RAM.
Then, the flash memory is re-programmed by executing the programming routine. The host
sends out both commands and programming data to re-program the flash memory.
Communications between the SIO0 and the host must follow the protocol described later. To
secure the contents of the flash memory, the validity of the application’s password is checked
before a programming routine is downloaded into the on-chip RAM. If password matching fails,
the transfer of a programming routine itself is aborted.
As in the case of User Boot mode, all interrupts including the non-maskable interrupt (NMI) must
be disabled in Single Boot mode while the flash memory is being erased or programmed. In
SingleBoot mode, the boot-ROM programs are executed in Normal mode.
Once re-programming is complete, it is recommended to protect relevant flash blocks from
accidental corruption during subsequent Single-Chip (Normal mode) operations.
−−−−−−−−−−−−
Note : When use Single Boot Mode, it is necessary to reset TMPM370FY from the RESET
terminal.

TMPM370
Single Boot Mode
(2-A) Using the Program in the On-Chip Boot ROM
(Step-1)
The flash block containing the older version of the program code need not be erased before executing
the programming routine. Since a programming routine and programming data are transferred via the
SIO (SIO0), the SIO0 must be connected to a host controller. Prepare a programming routine (a) on the
host controller.
New application
(Host) program code
(I/O)
(a) Programming routine
(TMPM370)
Boot ROM SIO0

Flash memory
Old application
program code
(or erased state)
RAM
(Step-2)
Cancel the reset of the TMPM370 by setting the Single Boot mode pin to “0”, so that the CPU re-boots
from the on-chip boot ROM. The 12-byte password transferred from the host controller via SIO0 is first
compared to the contents of the special flash memory locations. (If the flash block has already been
erased, the password is 0xFFFF).
New application
(Host) program code
(I/O)
(TMPM370)
0 → 1 RESET
Boot ROM SIO0
Flash memory
0 BOOT
Old application
program code
(or erased state)
RAM

TMPM370
(Step-3)
If the password was correct, the boot program downloads, via the SIO0, the programming routine (a)
from the host controller into the on-chip RAM of the TMPM370. The programming routine must be
stored in the address range 0x2000_0400 to the end address of RAM.
New application
(Host) program code
(I/O)
(TMPM370) (a) Programming routine
Boot ROM SIO0

Flash memory
Old application
Program code
(or erased state)
RAM
(Step-4)
The CPU jumps to the programming routine (a) in the on-chip RAM to erase the flash block containing
the old application program code. The Block Erase or Chip Erase command may be used.
New application
(Host) Program code
(I/O)
(TMPM370)
Boot ROM SIO0

Flash memory

Erased
RAM

TMPM370
(Step-5)
Next, the programming routine (a) downloads new application program code from the host controller
and programs it into the erased flash block. Once programming is complete, protection of that flash
block is turned on. It is not allowed to move program control from the programming routine (a) back to
the boot ROM.
In the example below, new program code comes from the same host controller via the same SIO0
channel as for the programming routine. However, once the programming routine has begun to
execute, it is free to change the transfer path and the source of the transfer. Create board hardware
and a programming routine to suit your particular needs.
New application
(Host) program code
(I/O)
(TMPM370)
Boot ROM SIO0

Flash memory
(a)Programming routine
New application
program code
RAM
(Step-6)
When programming of the flash memory is complete, power off the board and disconnect the cable
leading from the host to the target board. Turn on the power again so that the TMPM370 re-boots in
Single-Chip (Normal) mode to execute the new program.
(Host)
(TMPM370)
0 → 1 RESET
Boot ROM SIO0
Flash memory
Set to Single-Chip
New application Normal) mode
program code (BOOT=1)
RAM

TMPM370
(1) Configuration for Single Boot Mode

To execute the on-board programming, boot the TMPM370 with Single Boot mode following the
configuration shown below.
BOOT (PF0) =0
RESET =0→1
Set the RESET input to 0, and set the each BOOT (PF0) pins to values shown above, and then release
RESET (high).
(2) Memory Map

Fig. 20-3 shows a comparison of the memory maps in Normal and Single Boot modes. In Single Boot
mode, the internal flash memory is mapped to 0x3F80_0000 through 0x3F83_FFFF, and the Internal
boot ROM (Mask ROM) is mapped to 0x0000_0000 through 0x0000_0FFF.
Flash RAM Flash Address

Product Name RAM Address
Size Size (Single Chip/ Single Boot Mode)
0x0000_0000 - 0x0003_FFFF
TMPM370FY 256KB 10KB 0x2000_0000 - 0x2000_27FF
0x3F80_0000 - 0x3F83_FFFF

TMPM370
Single Chip Mode Single Boot Mode

0xFFFF_FFFF 0xFFFF_FFFF
Internal I/O 0x41FF_F000

Internal I/O 0x41FF_F000
0x4000_0000
0x4000_0000
Internal Flash_ROM 0x3F83_FFFF

(256KB) 0x3F80_0000
Internal RAM 0x2000_27FF Internal RAM 0x2000_27FF

(10KB) (10KB)
0x2000_0000 0x2000_0000
Internal Flash_ROM 0x0003_FFFF Internal 0x0000_0FFF

(256KB) BOOT_ROM (4KB)
0x0000_0000 0x0000_0000
Fig. 20-3 Memory Maps for TMPM370FY

TMPM370
(3) Interface specification

In Single Boot mode, an SIO channel is used for communications with a programming controller. The
same configuration is applied to a communication format on a programming controller to execute the
on-board programming. Both UART (asynchronous) and I/O Interface (synchronous) modes are
supported. The communication formats are shown below.
• UART communication
Communication channel : SIO channel 0
Serial transfer mode : UART (asynchronous), half -duplex, LSB first
Data length : 8 bit
Parity bits : None
STOP bits : 1 bit
Baud rate : Arbitrary baud rate

Communication channel : SIO channel 0
Serial transfer mode : I/O interface mode, full -duplex, LSB first
Synchronization clock (SCLK0) : Input mode
Handshaking signal : PE4 configured as an output mode
Baud rate : Arbitrary baud rate
•
Table 20-3 Required Pin Connections

Pins Interface
UART I/O Interface Mode
Power supply DVDD5 ○ ○
pins AVDD5 ○ ○
RVDD5 ○ ○
DVSS ○ ○
AVSS ○ ○
Mode-setting pin BOOT (PF0) ○ ○
Reset pin RESET ○ ○
Communication TXD0(PE0) ○ ○
pins RXD0(PE1) ○ ○
SCLK0(PE2) x ○ (Input mode)
PE4 x ○ (Output mode)

TMPM370
(4) Data Transfer Format

Table 20-4 and Table 20-6 to Table 20-10 illustrate the operation commands and data transfer formats
at each operation mode. In conjunction with this section, refer to (6) Operation of Boot Program.
Table 20-4 Single Boot Mode Commands

Code Command
0x10 RAM transfer
0x20 Show Flash Memory SUM
0x30 Show Product Information
0x40 Chip and protection bit erase
(5) Restrictions on internal memories

Single Boot Mode places restrictions on the internal RAM and ROM as shown in Table 20-5.
Table 20-5 Restrictions in Single Boot Mode

Memory Details
BOOT ROM is mapped from 0x2000_0000 to 0x2000_03FF.
Internal RAM Store the RAM transfer program from 0x2000_0400 through the end address of
RAM.
The following addresses are assigned for storing software ID information and
Internal ROM passwords. Storing program in these addresses is not recommendable.
TMPM370FY ：0x3F83_FFF0 to 0x3F83_FFFF

TMPM370
Table 20-6 Transfer Format for the RAM Transfer Command

Byte Data Transferred from the Controller Baud rate Data Transferred from the TMPM370FY
to the TMPM370FY to the Controller
Boot ROM 1 byte Serial operation mode and baud rate Desired baud -
For UART mode 0x86 rate
For I/O Interface mode 0x30 (Not
e 1)
2 byte - ACK for the serial operation mode byte
For UART mode
-Normal acknowledge 0x86
(The boot program aborts if the baud rate
can not be set correctly.)
For I/O Interface mode
3 byte Command code (0x10) -
4 byte - ACK for the command code byte (Note 2)
-Negative acknowledge 0xN1
-Communication error 0xN8
5 byte - Password sequence (12 bytes) ⎯
16 byte 0x3F83_FFF4 to 0x3F83_FFFF
17 byte Check SUM value for bytes 5 - 16 -
18 byte - ACK for the checksum byte (Note 2)
-Negative acknowledge 0ｘN1
-Communication error 0ｘN8
19 byte RAM storage start address 31 - 24 -
23 byte RAM storage byte count 15 - 8 -
24 byte RAM storage byte count 7 - 0 -
25 byte Check SUM value for bytes 19 - 24 -
26 byte - ACK for the checksum byte (Note 2)
27 byte RAM storage data -
∼
m byte
m + byte Checksum value for bytes 27 - m -
m + byte - ACK for the checksum byte (Note 2)
RAM m + byte - Jump to RAM storage start address
(Note 1) In I/O Interface mode, the baud rate for the transfers of the first and second bytes must
be 1/16 of the desired baud rate.
(Note 2) In case of any negative acknowledge, the boot program returns to a state in which it
waits for a command code (3rd byte). In I/O Interface mode, if a communication error
occurs, a negative acknowledge does not occur.
(Note 3) The 19th to 25th bytes must be within the RAM address range from 0x2000_0400 through
the end address of RAM.

TMPM370
Table 20-7 Transfer Format for the Show Flash Memory Sum Command
Byte Data Transferred from the Controller Baud rate Data Transferred from the
to the TMPM370FY TMPM370FY to the Controller
For UART mode 0x86 rate (Note 1)
For I/O Interface mode 0x30
For UART mode
5 byte - SUM (upper byte)
6 byte - SUM (lower byte)
7 byte - Checksum value for bytes 5 and 6
8 byte (Wait for the next command code.) -
(Note 1) In I/O Interface mode, the baud rate for the transfers of the first and second bytes must be
1/16 of the desired baud rate.
(Note 2) In case of any negative acknowledge, the boot program returns to a state in which it waits
for a command code (3rd byte). In I/O Interface mode, if a communication error occurs, a
negative acknowledge does not occur.

TMPM370
Table 20-8 Transfer Format for the Show Product Information Command (1/2)
Byte Data Transferred from the Controller Baud rate Data Transferred from the TMPM370FY to the
to the TMPM370FY Controller
For UART mode 0x86
rate (Note 1)
For UART mode
(The boot program aborts if the baud rate can not
be set correctly.)
5 byte - Flash memory data
at address 0x3F83_FFF0



9 byte - - Product name (12-byte ASCII code)

20 byte From the 9th byte: ‘TMPM370FY_[ ] _’
(where [ ] is a space)
21 byte - - Password comparison start address (4 bytes)
st
24 byte From the 21 byte: 0xF4, 0xFF, 0x83, 0x3F
25 byte - - RAM start address (4 bytes)

th
28 byte 0x00, 0x00, 0x00 and 0x20 from the 25 byte
29 byte - - Dummy data (4 bytes)
th
33 byte - - RAM end address (4 bytes)

rd
36 byte From the 33 byte: 0xFF, 0x27, 0x00, 0x20
(Note 3)
37 byte- - Dummy data (4 bytes)

th
40 byte 0x00, 0x00, 0x00 and 0x00 from the 37 byte.
41 byte - - Dummy data (4 bytes)

st
45 byte – - Fuse information (2 bytes)

th
46 byte 0x00 and 0x00 from the 45 byte.
47 byte - - Flash memory start address (4 bytes)

th
50 byte 0x00, 0x00, 0x80 and 0x3F from the 47 byte
51 byte - - Flash memory end address (4 bytes)

st
54 byte From the 51 byte: 0xFF, 0xFF, 0x83, 0x3F
(Note 4)
55 byte- - Flash memory block count (2 bytes)
th
56 byte From the 55 byte: 0x06, 0x00

TMPM370
Table 20-8 Transfer Format for the Show Product Information Command (2/2)
Byte Data Transferred from the Controller Baud rate Data Transferred from the
to the TMPM370FY TMPM370FY to the Controller
57 byte - - Start address of a group of the same-size
60 byte (16K) flash blocks (4 bytes)
th
From 57 byte: 0x00, 0x00, 0x80, 0x3F
Boot ROM 61 byte - - Size (in halfwords) of the same-size (16K)

64 byte flash blocks (4 bytes)
st
0x00, 0x20, 0x00 and 0x00 from the 61
byte
65 byte - Number of flash blocks of the same size
(16K) (1 byte)
0x02
66 byte - - Start address of a group of the same-size
(32K) flash blocks (4 bytes)
69 byte th
From 66 byte: 0x00, 0x80, 0x80, 0x3F
70 byte - Size (in halfwords) of the same-size (32K)

th
0x00, 0x40, 0x00 and 0x00 from the 70
byte
74 byte Number of flash blocks of the same size
(32K) (1 byte)
0x01
75 byte - Start address of a group of the same-size
78 byte th
0x00, 0x00, 0x81 and 0x3F from 75 byte
th
0x00, 0x80, 0x00 and 0x00 from the 79
byte
(64K) (1 byte)
rd
From 83 byte: 0x03
84 byte - Start address of a group of the same-size
87 byte th
From 84 byte: 0x00, 0x00, 0x82, 0x3F

th
0x00, 0x00, 0x00 and 0x00 from the 88
byte
(128K) (1 byte)
0x00 (Note 5)
93 byte Checksum value for bytes 5 - 92

94 byte (Wait for the next command code.) -
(Note 2) In case of any negative acknowledge, the boot program returns to a state in which it waits
for a command code (3rd byte). In I/O Interface mode, if a communication error occurs, a
negative acknowledge does not occur.

TMPM370
Table 20-9 Transfer Format for the Chip and Protection Bit Erase Command
Byte Data Transferred from the Controller Baud rate Data Transferred from the TMPM370FY
to the TMPM370FY to the Controller
Boot ROM 1 byte Serial operation mode and baud rate Desired baud ⎯
For UART mode 0x86
rate (Note 1)
2 byte ⎯ ACK for the serial operation mode byte
For UART mode
3 byte Command code (0x40) ⎯

4 byte ⎯ ACK for the command code byte (Note 2)
5 byte Chip erase command code (0x54) ⎯
6 byte ⎯ ACK for the command code byte (Note 2)
7 byte ⎯ ACK for the chip erase command code byte
-Normal acknowledge 0x4F

-Negative acknowledge 0x4C
8 byte (Wait for the next command code.) ⎯
(Note 2) In case of any negative acknowledge, the boot program returns to a state in which it
waits for a command code (3rd byte). In I/O Interface mode, if a communication error
occurs, a negative acknowledge does not occur.

TMPM370
(6) Operation of Boot Program

When Single Boot mode is selected, the boot program is automatically executed on startup. The
boot program offers these three commands, of which the details are provided on the following
subsections. The addresses described in this section are the virtual unless otherwise noted.
1. RAM Transfer command

The RAM Transfer command stores program code transferred from a host controller to the
on-chip RAM and executes the program once the transfer is successfully completed. The
user program RAM space can be assigned to the range from 0x2000_0400 to the end
address of RAM, whereas the boot program area (0x2000_0000 ～ 0x2000_03FF) is
unavailable. The user program starts at the assigned RAM address.
The RAM Transfer command can be used to download a flash programming routine of your
own; this provides the ability to control on-board programming of the flash memory in a
unique manner. The programming routine must utilize the flash memory command
sequences described in Section 20.3.
Before initiating a transfer, the RAM Transfer command verifies a password sequence
coming from the controller against that stored in the flash memory.
Note: If a password is set to 0xFF (erased data), it is difficult to protect data securely to
due to an easy-to-guess password. Even if Single Boot mode is not used, it is
recommended to set a unique value as a password.
2. Show Flash Memory Sum command

The Show Flash Memory Sum command adds the entire contents of the flash memory
together. The boot program does not provide a command to read out the contents of the
flash memory. Instead, the Flash Memory Sum command can be used for software revision
management.
3. Show Product Information command

The Show Product Information command provides the product name, on-chip memory
configuration and the like. This command also reads out the contents of the flash memory
locations at addresses shown below. In addition to the Show Flash Memory Sum command,
these locations can be used for software revision management.
Product name Area
TMPM370FY 0x3F83_FFF0 – 0x3F87_FFF3
4. Chip and Protection Bit Erase command

This command erases the entire area of the flash memory automatically without verifying a
password. All the blocks in the memory cell and their protection conditions are erased even
when any of the blocks are prohibited from writing and erasing. When the command is
completed, the FCSECBIT <SECBIT> bit is set to “1”.
This command serves to recover boot programming operation when a user forgets the
password. Therefore password verification is not executed.

TMPM370
1) RAM Transfer Command (See Table 20-6)
1. The 1st byte specifies which one of the two serial operation modes is used. For a
detailed description of how the serial operation mode is determined, see
Determination of a Serial Operation Mode described later. If it is determined as UART
mode, the boot program then checks if the SIO0 is programmable to the baud rate at
which the 1st byte was transferred. During the first-byte interval, the RXE bit in the
HSC0MOD register is cleared.
• To communicate in UART mode

Send, from the controller to the target board, 86H in UART data format at the
desired baud rate. If the serial operation mode is determined as UART, then the
boot program checks if the SIO0 can be programmed to the baud rate at which the
first byte was transferred. If that baud rate is not possible, the boot program aborts,
disabling any subsequent communications.
• To communicate in I/O Interface mode

Send, from the controller to the target board, 0x30 in I/O Interface data format at
1/16 of the desired baud rate. Also send the 2nd byte at the same baud rate. Then
send all subsequent bytes at a rate equal to the desired baud rate.
In I/O Interface mode, the CPU sees the serial receive pin as if it were a general
input port in monitoring its logic transitions. If the baud rate of the incoming data is
high or the chip’s operating frequency is high, the CPU may not be able to keep up
with the speed of logic transitions. To prevent such situations, the 1st and 2nd
bytes must be transferred at 1/16 of the desired baud rate; then the boot program
calculates 16 times that as the desired baud rate. When the serial operation mode
is determined as I/O Interface mode, the SIO0 is configured for SCLK Input mode.
Beginning with the third byte, the controller must ensure that its AC timing
restrictions are satisfied at the selected baud rate. In the case of I/O Interface
mode, the boot program does not check the receive error flag; thus there is no
such thing as error acknowledge (bit 3, 0xN8).
2. The 2nd byte, transmitted from the target board to the controller, is an acknowledge
response to the 1st byte. The boot program echoes back the first byte: 0x86 for UART
mode and 0x30 for I/O Interface mode.
UART mode
If the SIO0 can be programmed to the baud rate at which the 1st byte was transferred,
the boot program programs the SC0BRCR and sends back 0x86 to the controller as an
acknowledge. If the SIO0 is not programmable at that baud rate, the boot program
simply aborts with no error indication. Following the 1st byte, the controller should allow
for a time-out period of five seconds. If it does not receive 0x86 within the allowed
time-out period, the controller should give up the communication. The boot program
sets the RXE bit in the SC0MOD0 register to enable reception (1) before loading the
SIO transmit buffer with 0x86.
• I/O Interface mode

The boot program programs the SC0MOD0 and SC0CR registers to configure the
SIO0 in I/O Interface mode (clocked by the rising edge of SCLK0), writes 0x30 to

TMPM370
the SC0BUF. Then, the SIO0 waits for the SCLK0 signal to come from the
controller. Following the transmission of the 1st byte, the controller should send
the SCLK clock to the target board after a certain idle time (several microseconds).
This must be done at 1/16 the desire baud rate. If the 2nd byte, which is from the
target board to the controller, is 0x30, then the controller should take it as a
go-ahead. The controller must then deliver the 3rd byte to the target board at a
rate equal to the desired baud rate. The boot program sets the RXE bit in the
SC0MOD register to enable reception before loading the SIO transmit buffer with
0x30.
3. The 3rd byte transmitted from the controller to the target board is a command. The
code for the RAM Transfer command is 0x10.
4. The 4th byte, transmitted from the target board to the controller, is an acknowledge
response to the 3rd byte. Before sending back the acknowledge response, the boot
program checks for a receive error. If there was a receive error, the boot program
transmits x8H (bit 3) and returns to the state in which it waits for a command (the third
byte) again. In this case, the upper four bits of the acknowledge response are
undefined - they hold the same values as the upper four bits of the previously issued
command. When the SIO0 is configured for I/O Interface mode, the boot program does
not check for a receive error.
If the 3rd byte is equal to any of the command codes listed in Table 20-4, the boot
program echoes it back to the controller. When the RAM Transfer command was
received, the boot program echoes back a value of 0x10 and then branches to the
RAM Transfer routine. Once this branch is taken, password verification is done.
Password verification is detailed in a later section “Password”. If the 3rd byte is not a
valid command, the boot program sends back 0xN1 (bit 0) to the controller and returns
to the state in which it waits for a command (the third byte) again. In this case, the
upper four bits of the acknowledge response are undefined - they hold the same
values as the upper four bits of the previously issued command.
5. The 5th to 16th bytes transmitted from the controller to the target board, are a 12-byte
password. Each byte is compared to the contents of following addresses in the flash
memory. The verification is started with the 5th byte and the smallest address in the
designated area. If the password verification fails, the RAM Transfer routine sets the
password error flag.
Product name Area

TMPM370FY 0x3F83_FFF4 – 0x3F83_FFFF
Note: Regardless using or not using Single Boot mode, password must be
written in password area.
6. The 17th byte is a checksum value for the password sequence (5th to 16th bytes). To
calculate the checksum value for the 12-byte password, add the 12 bytes together,
drop the carries and take the two’s complement of the total sum. Transmit this
checksum value from the controller to the target board. The checksum calculation is
described in details in a later section “Checksum Calculation”.

TMPM370
response to the 5th to 17th bytes. First, the RAM Transfer routine checks for a receive
error in the 5th to 17th bytes. If there was a receive error, the boot program sends back
18H (bit 3) and returns to the state in which it waits for a command (i.e., the 3rd byte)
again. In this case, the upper four bits of the acknowledge response are the same as
those of the previously issued command (i.e., all 1s). When the SIO0 is configured for
I/O Interface mode, the RAM Transfer routine does not check for a receive error.
Next, the RAM Transfer routine performs the checksum operation to ensure data
integrity. Adding the series of the 5th to 16th bytes must result in 0x00 (with the carry
dropped). If it is not 0x00, one or more bytes of data has been corrupted. In case of a
checksum error, the RAM Transfer routine sends back 0x11 to the controller and
returns to the state in which it waits for a command (i.e., the 3rd byte) again.
Finally, the RAM Transfer routine examines the result of the password verification. The
following two cases are treated as a password error. In these cases, the RAM Transfer
routine sends back 0x11 (bit 0) to the controller and returns to the state in which it waits
for a command (i.e., the 3rd byte) again.
• Irrespective of the result of the password comparison, all the 12 bytes of a

password in the flash memory are the same value other than 0xFF.
Not the entire password bytes transmitted from the controller matched those contained
in the flash memory.
When all the above verification has been successful, the RAM Transfer routine returns
a normal acknowledge response (0x10) to the controller.
8. The 19th to 22nd bytes, transmitted from the controller the target board, indicate the
start address of the RAM region where subsequent data (e.g., a flash programming
routine) should be stored. The 19th byte corresponds to bits 31–24 of the address and
the 22nd byte corresponds to bits 7–0 of the address.
9. The 23rd and 24th bytes, transmitted from the controller to the target board, indicate
the number of bytes that will be transferred from the controller to be stored in the RAM.
The 23rd byte corresponds to bits 15–8 of the number of bytes to be transferred, and
the 24th byte corresponds to bits 7–0 of the number of bytes.
10. The 25th byte is a checksum value for the 19th to 24th bytes. To calculate the
checksum value, add all these bytes together, drop the carries and take the two’s
complement of the total sum. Transmit this checksum value from the controller to the
target board. The checksum calculation is described in details in a later section
“Checksum Calculation”.
response to the 19th to 25th bytes of data. First, the RAM Transfer routine checks for a
receive error in the 19th to 25th bytes. If there was a receive error, the RAM Transfer
routine sends back 0x18 and returns to the command wait state (i.e., the 3rd byte)
again. In this case, the upper four bits of the acknowledge response are the same as
those of the previously issued command (i.e., all 1s). When the SIO0 is configured for
I/O Interface mode, the RAM Transfer routine does not check for a receive error.

TMPM370
integrity. Adding the series of the 19th to 25th bytes must result in 00H (with the carry
dropped). If it is not 00H, one or more bytes of data has been corrupted. In case of a
checksum error, the RAM Transfer routine sends back 0x11 to the controller and
returns to the state in which it waits for a command (i.e., the 3rd byte) again.
• The RAM storage start address must be within the range of 0x2000_0400 to the
end address of RAM.
When the above checks have been successful, the RAM Transfer routine returns a
normal acknowledge response (0x10) to the controller.
12. The 27th to mth bytes from the controller are stored in the on-chip RAM of the
TMPM370FY. Storage begins at the address specified by the 19th–22nd bytes and
continues for the number of bytes specified by the 23rd–24th bytes.

TMPM370
13. The (m+1) th byte is a checksum value. To calculate the checksum value, add the 27th
to mth bytes together, drop the carries and take the two’s complement of the total sum.
Transmit this checksum value from the controller to the target board. The checksum
calculation is described in details in a later section “Checksum Calculation”.
14. The (m+2) th byte is a acknowledge response to the 27th to (m+1) th bytes.
First, the RAM Transfer routine checks for a receive error in the 27th to (m+1) th bytes.
If there was a receive error, the RAM Transfer routine sends back 18H (bit 3) and
returns to the state in which it waits for a command (i.e., the 3rd byte) again. In this
case, the upper four bits of the acknowledge response are the same as those of the
previously issued command (i.e., all 1s). When the SIO0 is configured for I/O Interface
mode, the RAM Transfer routine does not check for a receive error.
integrity. Adding the series of the 27th to (m+1) th bytes must result in 0x00 (with the
carry dropped). If it is not 0x00, one or more bytes of data has been corrupted. In case
of a checksum error, the RAM Transfer routine sends back 0x11 (bit 0) to the controller
and returns to the command wait state (i.e., the 3rd byte) again. When the above
checks have been successful, the RAM Transfer routine returns a normal
acknowledge response (0x10) to the controller.
15. If the (m+2) th byte was a normal acknowledge response, a branch is made to the address
specified by the 19th to 22nd bytes.

TMPM370
2) Show Flash Memory Sum Command (See Table 20-7)
1. The processing of the 1st and 2nd bytes are the same as for the RAM Transfer
command.
2. The 3rd byte, which the target board receives from the controller, is a command. The
code for the Show Flash Memory Sum command is 20H.
transmits x8H (bit 3) and returns to the command wait state again. In this case, the
values as the upper four bits of the previously issued command. When the SIO0 is
configured for I/O Interface mode, the boot program does not check for a receive error.
program echoes it back to the controller. When the Show Flash Memory Sum
command was received, the boot program echoes back a value of 0x20 and then
branches to the Show Flash Memory Sum routine. If the 3rd byte is not a valid
command, the boot program sends back 0xN1 (bit 0) to the controller and returns to
the command wait state (the third byte) again. In this case, the upper four bits of the
acknowledge response are undefined - they hold the same values as the upper four
bits of the previously issued command.
4. The Show Flash Memory Sum routine adds all the bytes of the flash memory together.
The 5th and 6th bytes, transmitted from the target board to the controller, indicate the
upper and lower bytes of this total sum, respectively. For details on sum calculation,
see a later section “Calculation of the Show Flash Memory Sum Command”.
5. The 7th byte is a checksum value for the 5th and 6th bytes. To calculate the checksum
value, add the 5th and 6th bytes together, drop the carry and take the two’s
complement of the sum. Transmit this checksum value from the controller to the target
board.
6. The 8th byte is the next command code.

TMPM370
3) Show Product Information Command (See Table 20-8)
command.
code for the Show Product Information command is 30H.
transmits 0xN8 (bit 3) and returns to the command wait state again. In this case, the
values as the upper four bits of the previously issued command. When the SIO0 is
configured for I/O Interface mode, the boot program does not check for a receive error.
branches to the Show Flash Memory Sum routine. If the 3rd byte is not a valid
command, the boot program sends back 0xN1 (bit 0) to the controller and returns to
the state in which it waits for a command (the third byte) again. In this case, the upper
four bits of the acknowledge response are undefined - they hold the same values as
the upper four bits of the previously issued command.
4. The 5th to 8th bytes, transmitted from the target board to the controller, are the data
read from addresses shown below in the flash memory. Software version
management is possible by storing a software ID in these locations.
Product name Area
TMPM370FY 0x3F87_FFF0 – 0x3F87_FFF3
5. The 9th to 20th bytes, transmitted from the target board to the controller, indicate the
product name as shown below (where [ ] is a space) in ASCII code.
Product name Code
TMPM370FY T,M,P,M,3,7,0,F,Y,_,[ ],_
6. The 21st to 24th bytes, transmitted from the target board to the controller, indicate the
start address of the flash memory area containing the password. Each product has
own start address shown below.
Product name Address
TMPM370FY 0xF4, 0xFF, 0x87, 0x3F

TMPM370
start address of the on-chip RAM, are 0x00, 0x00, 0x00 and 0x20.
8. The 29th to 32nd bytes, transmitted from the target board to the controller, are dummy
data (0x00, 0x00, 0x00 and 0x00).
9. The 33rd to 36th bytes, transmitted from the target board to the controller, indicate the
end address of the on-chip RAM, are 0xFF, 0x27, 0x00 and 0x20.
10. The 37th to 40th bytes, transmitted from the target board to the controller, are 0x00,
0x00, 0x00 and 0x00. The 41st to 44th bytes, transmitted from the target board to the
controller, are 0x00, 0x00, 0x00 and 0x00.
11. The 45th and 46th bytes transmitted are 0x00, 0x00.
start address of the on-chip flash memory, are 0x00, 0x00, 0x80, and 0x3F.
13. The 51st to 54th bytes, transmitted from the target board to the controller, indicate the
end address of the on-chip flash memory, are 0xFF, 0xFF, 0x83 and 0x3F.
number of flash blocks available, are 0x06 and 0x00.
15. The 57th to 83rd bytes, transmitted from the target board to the controller, contain
information about the flash blocks. Flash blocks of the same size are treated as a
group. Information about the flash blocks indicate the start address of a group, the size
of the blocks in that group (in halfwords) and the number of the blocks in that group.
The 57th to 65th bytes are the information about the 16-kbyte blocks. The 66th to 74th
bytes are the information about the 32-kbyte blocks. The 75th to 83rd bytes are the
information about the 64-kbyte blocks. The 84th to 92nd bytes are the information
about the 128-kbyte blocks. See Table 20-8 for the values of bytes transmitted.
16. The 93rd byte, transmitted from the target board to the controller, is a checksum value
for the 5th to 92nd bytes. The checksum value is calculated by adding all these bytes
together, dropping the carry and taking the two’s complement of the total sum.

TMPM370
4) Chip and Protection Bit Erase command (See Table 20-9)
command.
code for the Show Product Information command is 0x40.
transmits x8H (bit 3) and returns to the command wait state again. In this case, the
command was received, the boot program echoes back a value of 0x40. If the 3rd byte
is not a valid command, the boot program sends back 0xN1 (bit 0) to the controller and
returns to the state in which it waits for a command (the third byte) again. In this case,
the upper four bits of the acknowledge response are undefined - they hold the same
4. The 5th byte, transmitted from the target board to the controller, is the Chip Erase
Enable command code (0x54).
response to the 5th byte.
Before sending back the acknowledge response, the boot program checks for a
receive error. If there was a receive error, the boot program transmits 0xN8 (bit 3) and
returns to the command wait state again. In this case, the upper four bits of the
If the 5th byte is equal to any of the command codes to enable erasing, the boot
branches to the Chip Erase routine. If the 5th byte is not a valid command, the boot
program sends back 0xN1 (bit 0) to the controller and returns to the state in which it
waits for a command (the third byte) again. In this case, the upper four bits of the

TMPM370
6. The 7th byte indicates whether the Chip Erase command is normally completed or not.
At normal completion, completion code (0x4F) is sent.
When an error was detected, error code (0x4C) is sent.

TMPM370
5) Acknowledge Responses
The boot program represents processing states with specific codes. Table 20-10 to Table 20-13 show
the values of possible acknowledge responses to the received data. The upper four bits of the
acknowledge response are equal to those of the command being executed. Bit 3 of the code indicates
a receive error. Bit 0 indicates an invalid command error, a checksum error or a password error. Bit 1
and bit 2 are always 0. Receive error checking is not done in I/O Interface mode.
Table 20-10 ACK Response to the Serial Operation Mode Byte

Return Value Meaning
0x86 The SIO can be configured to operate in UART mode. (See Note)
0x30 The SIO can be configured to operate in I/O Interface mode.
(Note) If the serial operation mode is determined as UART, the boot program checks if the SIO can
be programmed to the baud rate at which the operation mode byte was transferred. If that
baud rate is not possible, the boot program aborts, without sending back any response.
Table 20-11 ACK Response to the Command Byte

0xN8 (See Note) A receive error occurred while getting a command code.
0xN1 (See Note) An undefined command code was received. (Reception was completed normally.)
0x10 The RAM Transfer command was received.
0x20 The Show Flash Memory Sum command was received.
0x30 The Show Product Information command was received.
0x40 The Chip Erase command was received.
(Note) The upper four bits of the ACK response are the same as those of the previous command
code.
Table 20-12 ACK Response to the Checksum Byte

0xN8 (See Note) A receive error occurred.
0xN1 (See Note) A checksum or password error occurred.
0xN0 (See Note) The checksum was correct.
(Note) The upper four bits of the ACK response are the same as those of the operation command
code. It is 1 ( N＝RAM transfer command data [7:4] ) when password error occurs.
Table 20-13 ACK Response to Chip and Protection Bit Erase Byte
0x54 The Chip Erase enabling command was received.
0x4F The Chip Erase command was completed.
0x4C The Chip Erase command was abnormally completed.

TMPM370
6) Determination of a Serial Operation Mode
The first byte from the controller determines the serial operation mode. To use UART mode for
communications between the controller and the target board, the controller must first send a value of
0x86 at a desired baud rate to the target board. To use I/O Interface mode, the controller must send a
value of 0x30 at 1/16 the desired baud rate. Fig. 20-4 shows the waveforms for the first byte.
Start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop
A B C D
UART (0x86)
tAB
tAC tCD
tAD
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7

A B C D
I/O Interface
(0x30) tAB
tAC tCD
tAD
Fig. 20-4 Serial Operation Mode Byte
After RESET is released, the boot program monitors the first serial byte from the controller, with the
SIO reception disabled, and calculates the intervals of tAB, tAC and tAD. Fig. 20-5 shows a flowchart
describing the steps to determine the intervals of tAB, tAC and tAD. As shown in the flowchart, the boot
program captures timer counts each time a logic transition occurs in the first serial byte. Consequently,
the calculated tAB, tAC and tAD intervals are bound to have slight errors. If the transfer goes at a high
baud rate, the CPU might not be able to keep up with the speed of logic transitions at the serial receive
pin. In particular, I/O Interface mode is more prone to this problem since its baud rate is generally much
higher than that for UART mode. To avoid such a situation, the controller should send the first serial
byte at 1/16 the desired baud rate.
The flowchart in Fig. 20-5 shows how the boot program distinguishes between UART and I/O Interface
modes. If the length of tAB is equal to or less than the length of tCD, the serial operation mode is
determined as UART mode. If the length of tAB is greater than the length of tCD, the serial operation
mode is determined as I/O Interface mode. Bear in mind that if the baud rate is too high or the timer
operating frequency is too low, the timer resolution will be coarse, relative to the intervals between
logic transitions. This becomes a problem due to inherent errors caused by the way in which timer
counts are captured by software; consequently the boot program might not be able to determine the
serial operation mode correctly. To prevent this problem, reset UART mode within the programming
routine.
For example, the serial operation mode may be determined to be I/O Interface mode when the
intended mode is UART mode. To avoid such a situation, when UART mode is utilized, the controller
should allow for a time-out period within which it expects to receive an echo-back (0x86) from the
target board. The controller should give up the communication if it fails to get that echo-back within the
allowed time. When I/O Interface mode is utilized, once the first serial byte has been transmitted, the
controller should send the SCLK clock after a certain idle time to get an acknowledge response. If the
received acknowledge response is not 0x30, the controller should give up further communications.
When the intended mode is I/O interface mode, the first byte does not have to be 0x30 as long as tAB is

TMPM370
greater than tCD as shown above. 0x91, 0xA1 or 0xB1 can be sent as the first byte code to determine
the falling edges of Point A and Point C and the rising edges of Point B and Point D. If tAB is greater
than tCD and SIO is selected by the resolution of the operation mode determination, the second byte
code is 0x30 even though the transmitted code on the first byte is not 0x30 (The first byte code to
determine I/O interface mode is described as 0x30).
Start
Initialize TMRB0
Prescaler is on. (source clock: φT1 )
High-to-low transition
Point A
on serial receive pin?
YES
TMRB0 starts counting up
Low-to-high transition
Point B
YES
Software-capture and save timer value (tAB)
Point C on serial receive pin?
YES
Software-capture and save timer value (tAC)
Point D
YES
Software-capture and save timer value (tAD)
16-bit Timer 0 stops counting
YES
tAC ≥ tAD?
Make backup copy of tAD value
Stop operation
Done (infinite loop)
Fig. 20-5 Serial Operation Mode Byte Reception Flow

TMPM370
Start
tCD ← tAD − tAC
YES
tAB > tCD?
UART mode I/O interface mode
Fig. 20-6 Serial Operation Mode Determination Flow
7) Password
The RAM Transfer command (0x10) causes the boot program to perform password verification.
Following an echo-back of the command code, the boot program verifies the contents of the 12-byte
password area within the flash memory. The following table shows the password area.
Product name Area

TMPM370FY 0x3F83_FFF4 – 0x3F83_FFFF
Note: If a password is set to 0xFF (erased data), it is difficult to protect data securely to
due to an easy-to-guess password. Even if Single Boot mode is not used, it is
recommended to set a unique value as a password.
If all these address locations contain the same bytes of data other than 0xFF, a password area error
occurs as shown in Fig. 20-7.
In this case, the boot program returns an error acknowledge (0x11) in response to the checksum byte
(the 17th byte), regardless of whether the password sequence sent from the controller is all 0xFFs.
The password sequence received from the controller (5th to 16th bytes) is compared to the password
stored in the flash memory. All of the 12 bytes must match to pass the password verification. Otherwise, a
password error occurs, which causes the boot program to reply an error acknowledge in response to the
checksum byte (the 17th byte).
The password verification is performed even if the security function is enabled.

TMPM370
Start
Are all bytes the

same?
YES
Are all bytes YES

equal to 0xFF?
Password area error Password area is normal.
Fig. 20-7 Password Area Verification Flow

TMPM370
8) Calculation of the Show Flash Memory Sum Command
The result of the sum calculation “byte + byte + byte + …“ is responded by a word quantity. The Show Flash
Memory Sum command adds all 256 Kbytes of the flash memory together and provides the total sum as a word
quantity. The sum is sent to the controller, with the upper eight bits first, followed by the lower eight bits.
Example) For the interest of simplicity, assume the depth of the flash
0xA1
memory is four locations. Then the sum of the four bytes is
0xB2 calculated as:
0xA1 + 0xB2 + 0xC3 + 0xD4 = 0x02EA
0xC3 Hence, 0x02 is first sent to the controller, followed by 0xEA.
0xD4
9) Checksum Calculation
The checksum byte for a series of bytes of data is calculated by adding the bytes together, dropping
the carries, and taking the two’s complement of the total sum. The Show Flash Memory Sum
command and the Show Product Information command perform the checksum calculation. The
controller must perform the same checksum operation in transmitting checksum bytes.
Example) Assume the Show Flash Memory Sum command provides the upper and lower bytes of the
sum as 0xE5 and 0xF6. To calculate the checksum for a series of 0xE5 and 0xF6:
Add the bytes together

0xE5 + 0xF6 = 0x1DB
Take the two’s complement of the sum, and that is the checksum byte.
0 − 0xDB = 0x25

TMPM370
(7) General Boot Program Flowchart
Fig. 20-8 shows an overall flowchart of the boot program.
Single Boot
program starts
Initialize
Get SIO operation mode
SIO operation UART Baud rate Cannot be set

mode? setting ?
I/O interface Can be set
Program UART mode and
Set I/O interface mode Stop operation
baud rate
ACK data← received data ACK data← received data

(0x30) (0x86@UART)
(Send 0x30) (Send 0x86)

Normal response Normal response
Prepare to get a command
ACK data← ACK data &

0xF0
Receive routine
Get a command
Yes ACK data Transmission routine

Receive error ? ← ACK data 0x08 (Send0xN8:receive error)
No normally
RAM transfer? SUM ? Show product Chip erase?

information?
YES (0x10) YES (0x20) YES (0x30) YES (0x40)
ACK data ACK data ACK data ACK data
← Received data (0x10) ← Received data (0x20) ← Received data (0x30) ← Received data (0x40)
Transmission routine Transmission routine Transmission routine Transmission routine

(Send 0x10: normal response) (Send 0x20: normal response) (Send 0x30: normal response) (Send 0x40: normal response)
Show Flash Memory Sum Show Product Information

RAM transfer processing processing Chip erase processing
processing
Command error
ACK data
← Received data | 0x01
Transmission routine
(Send 0xN1: Command
Processed
normally?
Yes normally
Jump to RAM
Fig. 20-8 Overall Boot Program Flow

TMPM370
20.3 On-board Programming of Flash Memory (Rewrite/Erase)

In on-board programming, the CPU is to execute software commands for rewriting or erasing the
flash memory. The rewrite/erase control program should be prepared by the user beforehand.
Because the flash memory content cannot be read while it is being written or erased, it is necessary
to run the rewrite/erase program from the internal RAM or from an external memory device after
shifting to the user boot mode.
20.3.1 Flash Memory

Except for some functions, writing and erasing flash memory data are in accordance with the
standard JEDEC commands. In writing or erasing, use 32-bit data transfer command of the CPU to
enter commands to the flash memory. Once the command is entered, the actual write or erase
operation is automatically performed internally.
Table 20-14 Flash Memory Functions

Major functions Description
Automatic page program Writes data automatically per page.
Automatic chip erase Erases the entire area of the flash memory automatically.
Automatic block erase Erases a selected block automatically.
Protect function By writing a 4-bit protection code, the write or erase function can be individually inhibited for
each block.
Note that addressing of operation commands is different from the case of standard commands due to the
specific interface arrangements with the CPU. Also note that the flash memory is written in 32-bit blocks. So,
32-bit (word) data transfer commands must be used in writing the flash memory.
(1) Block configuration

User Boot Mode Single Boot Mode
Page Configuration
0x0003_FFFF 0x3F87_FFFF
64K bytes (BLOCK0) 64 words x 256
0x0003_0000 0x3F86_0000
0x0002_0000 0x3F82_0000
0x0001_0000 0x3F81_0000

0x0001_8000 0x3F80_8000

0x0000_4000 0x3F80_4000

0x0000_0000 0x3F80_0000
Fig. 20-9 Block Configuration of Flash Memory (TMPM370FY)

TMPM370
(2) Basic operation

Generally speaking, this flash memory device has the following two operation modes:
• The mode to read memory data (Read mode)
• The mode to automatically erase or rewrite memory data (Automatic operation)
Transition to the automatic mode is made by executing a command sequence while it is in the
memory read mode. In the automatic operation mode, flash memory data cannot be read and
any commands stored in the flash memory cannot be executed. In the automatic operation
mode, any interrupt or exception generation cannot set the device to the read mode except
when a hardware reset is generated. During automatic operation, be sure not to cause any
exceptions other than debug exceptions and reset while a debug port is connected. Any
exception generation cannot set the device to the read mode except when a hardware reset is
generated.
1) Read
When data is to be read, the flash memory must be set to the read mode. The flash memory
will be set to the read mode immediately after power is applied, when CPU reset is removed,
or when an automatic operation is normally terminated. In order to return to the read mode
from other modes or after an automatic operation has been abnormally terminated, either
the Read/reset command (a software command to be described later) or a hardware reset is
used. The device must also be in the read mode when any command written on the flash
memory is to be executed.
• Read/reset command and Read command (software reset)

When ID-Read command is used, the reading operation is terminated instead of
automatically returning to the read mode. In this case, the Read/reset command can be
used to return the flash memory to the read mode. Also, when a command that has not been
completely written has to be canceled, the Read/reset command must be used. The Read
command is used to return to the read mode after executing 32-bit data transfer command
to write the data "0x0000_00F0" to an arbitrary address of the flash memory.
• With the Read/reset command, the device is returned to the read mode after
completing the third bus write cycle.
2) Command write
This flash memory uses the command control method. Commands are executed by
executing a command sequence to the flash memory. The flash memory executes
automatic operation commands according to the address and data combinations applied
(refer to Command Sequence).
If it is desired to cancel a command write operation already in progress or when any
incorrect command sequence has been entered, the Read/reset command is to be
executed. Then, the flash memory will terminate the command execution and return to the
read
While commands are generally comprised of several bus cycles, the operation to apply 32-bit
data transmit command to the flash memory is called "bus write cycle." The bus write cycles are
to be in a specific sequential order and the flash memory will perform an automatic operation
when the sequence of the bus write cycle data and address of a command write operation is in
accordance with a predefined specific sequence. If any bus write cycle does not follow a

TMPM370
predefined command write sequence, the flash memory will terminate the command execution
and return to the read mode.
(Note 1) Command sequences are executed from outside the flash memory area.
(Note 2) Each bus write cycle must be sequentially executed by 32-bit data transmit
command. While a command sequence is being executed, access to the flash
memory is prohibited. Also, don't generate any interrupt (except debug exceptions
when a Debugging probe is connected).If such an operation is made, it can result in
an unexpected read access to the flash memory and the command sequencer may
not be able to correctly recognize the command. While it could cause an abnormal
termination of the command sequence, it is also possible that the written command
is incorrectly recognized.
(Note 3) For the command sequencer to recognize a command, the device must be in the
read mode prior to executing the command. Be sure to check before the first bus
write cycle that the FCFLCS RDY/BSY bit is set to "1." It is recommended to
subsequently execute a Read command.
(Note 4) Upon issuing a command, if any address or data is incorrectly written, be sure to
perform a software reset to return to the read mode again.
(3) Reset
Hardware reset
A hardware reset is used to cancel the operational mode set by the command write
operation when forcibly termination during auto programming/ erasing or abnormal
termination during auto operations occurs. The flash memory has a reset input as the
----------------------
memory block and it is connected to the CPU reset signal. Therefore, when the RESET
input pin of this device is set to “Low” level or when the CPU is reset due to any overflow of
the watch dog timer, the flash memory will return to the read mode terminating any
automatic operation that may be in progress. It should also be noted that applying a
hardware reset during an automatic operation can result in incorrect rewriting of data. In
such a case, be sure to perform the rewriting again.
Refer to Section 20.2.1 "Reset Operation" for CPU reset operations. After a given reset
input, the CPU will read the reset vector data from the flash memory and starts operation
after the reset is removed.

TMPM370
(4) Commands
1) Automatic Page Programming
Writing to a flash memory device is to make "1" data cells to "0" data cells. Any "0" data cell
cannot be changed to a "1" data cell. For making "0" data cells to "1" data cells, it is
necessary to perform an erase operation.
The automatic page programming function of this device writes data of each page. The
TMPM370FY contains 64 words in a page. A 64 word block is defined by a same [31:8]
address and it starts from the address [7:0] = 0 and ends at the address [7:0] = 0xFF. This
programming unit is hereafter referred to as a "page."
Writing to data cells is automatically performed by an internal sequencer and no external

control by the CPU is required. The state of automatic page programming (whether it is in
writing operation or not) can be checked by the FCFLCS [0] <RDY/BSY> register.
Also, any new command sequence is not accepted while it is in the automatic page
programming mode. If it is desired to interrupt the automatic page programming, use the
hardware reset function. If the operation is stopped by a hardware reset operation, it is
necessary to once erase the page and then perform the automatic page programming
again because writing to the page has not been normally terminated.
The automatic page programming operation is allowed only once for a page already erased.
No programming can be performed twice or more times irrespective of the data cell value
whether it is "1" or "0." Note that rewriting to a page that has been once written requires
execution of the automatic block erase or automatic chip erase command before executing
the automatic page programming command again. Note that an attempt to rewrite a page
two or more times without erasing the content can cause damages to the device.
No automatic verify operation is performed internally to the device. So, be sure to read the
data programmed to confirm that it has been correctly written.
The automatic page programming operation starts when the third bus write
cycle of the command cycle is completed. On and after the fifth bus write cycle, data will be
written sequentially starting from the next address of the address specified in the fourth bus
write cycle (in the fourth bus write cycle, the page top address will be command written) (32
bits of data is input at a time). Be sure to use the 32-bit data transfer command in writing
commands on and after the fourth bus cycle. In this, any 32-bit data transfer commands
shall not be placed across word boundary. On and after the fifth bus write cycle, data is
command written to the same page area. Even if it is desired to write the page only partially,
it is required to perform the automatic page programming for the entire page. In this case,
the address input for the fourth bus write cycle shall be set to the top address of the page.
Be sure to perform command write operation with the input data set to "1" for the data cells
not to be set to "0." For example, if the top address of a page is not to be written, set the
input data of the fourth bus write cycle to 0xFFFFFFFF to command write the data.
Once the fourth bus cycle is executed, it is in the automatic programming operation. This
condition can be checked by monitoring the register bit FCFLCS [0] <RDY/BSY> (See
Table 20-15). Any new command sequence is not accepted while it is in automatic page
programming mode. If it is desired to stop operation, use the hardware reset function. Be
careful in doing so because data cannot be written normally if the operation is interrupted.

TMPM370
When a single page has been command written normally terminating the automatic page
writing process, the FCFLCS [0] <RDY/BSY> bit is set to "1" and it returns to the read
mode.
When multiple pages are to be written, it is necessary to execute the page programming
command for each page because the number of pages to be written by a single execution of
the automatic page program command is limited to only one page. It is not allowed for
automatic page programming to process input data across pages.
Data cannot be written to a protected block. When automatic programming is finished, it

automatically returns to the read mode. This condition can be checked by monitoring
FCFLCS [0] <RDY/BSY> (Table 20-15). If automatic programming has failed, the flash
memory is locked in the mode and will not return to the read mode. For returning to the read
mode, it is necessary to execute hardware reset to reset the flash memory or the device. In
this case, while writing to the address has failed, it is recommended not to use the device or
not to use the block that includes the failed address.
(Note) Software reset becomes ineffective in bus write cycles on and after the fourth
bus write cycle of the automatic page programming command.
2) Automatic chip erase

The automatic chip erase operation starts when the sixth bus write cycle of the command
cycle is completed.
This condition can be checked by monitoring FCFLCS [0] <RDY/BSY> (See Table 20-15).
While no automatic verify operation is performed internally to the device, be sure to read the
data to confirm that data has been correctly erased. Any new command sequence is not
accepted while it is in an automatic chip erase operation. If it is desired to stop operation,
use the hardware reset function. If the operation is forced to stop, it is necessary to perform
the automatic chip erase operation again because the data erasing operation has not been
normally terminated.
Also, any protected blocks cannot be erased. If all the blocks are protected, the automatic
chip erase operation will not be performed and it returns to the read mode after completing
the sixth bus read cycle of the command sequence. When an automatic chip erase
operation is normally terminated, it automatically returns to the read mode. If an automatic
chip erase operation has failed, the flash memory is locked in the mode and will not return to
the read mode.
For returning to the read mode, it is necessary to execute hardware reset to reset the device.
In this case, the failed block cannot be detected. It is recommended not to use the device
anymore or to identify the failed block by using the block erase function for not to use the
identified block anymore.
3) Automatic block erase (fro aech block)

The automatic block erase operation starts when the sixth bus write cycle of the command
cycle is completed.
This status of the automatic block erase operation can be checked by monitoring FCFLCS
<RDY/BSY> (See Table 20-15). While no automatic verify operation is performed internally
to the device, be sure to read the data to confirm that data has been correctly erased. Any
new command sequence is not accepted while it is in an automatic block erase operation. If

TMPM370
it is desired to stop operation, use the hardware reset function. In this case, it is necessary
to perform the automatic block erase operation again because the data erasing operation
has not been normally terminated.
Also, any protected blocks cannot be erased. If an automatic block erase operation has
failed, the flash memory is locked in the mode and will not return to the read mode. In this
case, execute hardware reset to reset the device.
4) Automatic programming of protection bits (for each block)

This device is implemented with protection bits. This protection can be set for each block.
See Table 20-20 for table of protection bit addresses. This device assigns 1 bit to 1 block as
a protection bit. The applicable protection bit is specified by PBA in the seventh bus write
cycle. By automatically programming the protection bits, write and/or erase functions can be
inhibited (for protection) individually for each block. The protection status of each block can
be checked by the FCFLCS <BLPRO> register to be described later. This status of the
automatic programming operation to set protection bits can be checked by monitoring
FCFLCS <RDY/BSY> (See Table 20-15). Any new command sequence is not accepted
while automatic programming is in progress to program the protection bits. If it is desired to
stop the programming operation, use the hardware reset function. In this case, it is
necessary to perform the programming operation again because the protection bits may not
have been correctly programmed. If all the protection bits have been programmed, all the
FCFLCS <BLPRO> bits are set to "1" indicating that it is in the protected state (See Table
20-15). This disables subsequent writing and erasing of all blocks.
(Note) Software reset is ineffective in the seventh bus write cycle of the automatic
protection bit programming command. The FLCS <RDY/BSY> bit turns to
"0" after entering the seventh bus write cycle.

TMPM370
5) Automatic erasing of protection bits

Different results will be obtained when the automatic protection bit erase command is
executed depending on the status of the protection bits and the security bits. It depends on
the status of FCFLCS <BLPRO> whether all the <BLPRO> bits are set to "1" or not if
FCSECBIT<SECBIT> is 0x1. Be sure to check the value of FCFLCS <BLPRO> before
executing the automatic protection bit erase command. See chapter 17 for details.
・When all the FCFLCS <BLPRO> bits are set to "1" (all the protection bits are
programmed):
When the automatic protection bit erase command is command written, the flash memory is
automatically initialized within the device. When the seventh bus write cycle is completed,
the entire area of the flash memory data cells is erased and then the protection bits are
erased. This operation can be checked by monitoring FCFLCS <RDY/BSY>. If the
automatic operation to erase protection bits is normally terminated, FCFLCS will be set to
"0x00000001." While no automatic verify operation is performed internally to the device, be
sure to read the data to confirm that it has been correctly erased. For returning to the read
mode while the automatic operation after the seventh bus cycle is in progress, it is
necessary to use the hardware reset to reset the device. If this is done, it is necessary to
check the status of protection bits by FCFLCS <BLPRO> after retuning to the read mode
and perform either the automatic protection bit erase, automatic chip erase, or automatic
block erase operation, as appropriate.
・When the FCFLCS <BLPRO> bits include "0" (not all the protection bits are
programmed):
The protection condition can be canceled by the automatic protection bit erase operation.
With this device, protection bits set by an individual block can be erased handling all the
blocks at a time as shown in Table 20-21. The target bits are specified in the seventh bus
write cycle and when the command is completed, the device is in a condition all the blocks
are erased. The protection status of each block can be checked by FCFLCS <BLPRO> to
be described later. This status of the programming operation for automatic protection bits
can be checked by monitoring FCFLCS <RDY/BSY>. When the automatic operation to
erase protection bits is normally terminated, the protection bits of FCFLCS <BLPRO>
selected for erasure are set to "0."
In any case, any new command sequence is not accepted while it is in an automatic
operation to erase protection bits. If it is desired to stop the operation, use the hardware
reset function. When the automatic operation to erase protection bits is normally terminated,
it returns to the read mode.
(Note) The FLCS <RDY/BSY> bit is "0" while in automatic operation and it
turns to "1" when the automatic operation is terminated.

TMPM370
6) ID-Read
Using the ID-Read command, you can obtain the type and other information on the flash
memory contained in the device. The data to be loaded will be different depending on the
address [15:14] of the fourth and subsequent bus write cycles (recommended input data is
0x00). On and after the fourth bus write cycle, when an arbitrary flash memory area is read,
the ID value will be loaded. Once the fourth bus write cycle of an ID-Read command has
passed, the device will not automatically return to the read mode. In this condition, the set of
the fourth bus write cycle and ID-Read commands can be repetitively executed. For returning
to the read mode, use the Read/reset command or hardware reset command.

TMPM370
(5) Flash control/ status register

This resister is used to monitor the status of the flash memory and to indicate the protection status of
each block.
Table 20-15 Flash Control Register

31 30 29 28 27 26 25 24
bit Symbol - - - - - - - -
FCFLCS Read/Write R
0x41FF_F020 After reset 0
Function “0”is read.
23 22 21 20 19 18 17 16
bit Symbol - - BLPRO5 BLPRO4 BLPRO3 BLPRO2 BLPRO1 BLPRO0
Read/Write R R R R R R R
After reset 0 （Note 2）（Note 2）（Note 2）（Note 2）（Note 2）（Note 2）
“0”is read. Protection Protection Protection Protection Protection Protection
for Block 5 for Block 4 for Block 3 for Block 2 for Block 1 for Block 0
Function
0: disabled 0: disabled 0: disabled 0: disabled 0: disabled 0: disabled
1:enabled 1:enabled 1:enabled 1:enabled 1:enabled 1:enabled
15 14 13 12 11 10 9 8
bit Symbol - - - - - - - -
Read/Write R
After reset 0
Function “0”is read.
7 6 5 4 3 2 1 0
bit Symbol - - - - - - - RDY/BSY
Read/Write R R
After reset 0 1
“0”is read. Ready/Bus
y (Note 1)
0:Auto
Function operating
1:Auto
operation
terminated
Bit 0: Ready/Busy flag bit

The RDY/BSY output is provided as a means to monitor the status of automatic operation.
This bit is a function bit for the CPU to monitor the function. When the flash memory is in
automatic operation, it outputs "0" to indicate that it is busy. When the automatic operation
is terminated, it returns to the ready state and outputs "1" to accept the next command. If
the automatic operation has failed, this bit maintains the "0" output. By applying a
hardware reset, it returns to "1."
Bit [21:16]: Protection status bits

Each of the protection bits represents the protection status of the corresponding block.
When a bit is set to "1," it indicates that the block corresponding to the bit is protected.
When the block is protected, data cannot be written to it.

TMPM370
(Note 1) This command must be issued in the ready state. Issuing the command in
the busy state may disable both correct command transmission and further
command input. To exit from the condition, execute system reset. System
reset requires at least 0.5 microseconds regardless of the system clock
frequency. In this condition, it takes approx. 2 ms to enable reading after
reset.
(Note 2) The value varies depending on protection applied.
Table 20-16 Security bit register

31 30 29 28 27 26 25 24
bit Symbol - - - - - - - -
FCSECBIT Read/Write R
Function “0”is read
23 22 21 20 19 18 17 16
bit Symbol - - - - - - - -
Read/Write R
After reset 0
15 14 13 12 11 10 9 8
bit Symbol - - - - - - - -
Read/Write R
After reset 0
7 6 5 4 3 2 1 0
bit Symbol - - - - - - - SECBIT
Read/Write R R/W
After reset 0 1
“0”is read Security
bits
Function
0:disabled
1:enabled
(Note) This register is initialized only by power-on reset.

TMPM370
(6) List of Command Sequences
Table 20-17 Flash Memory Access from the Internal CPU

First bus Second bus Third bus Fourth bus Fifth bus Sixth bus Seventh bus
Command cycle cycle cycle cycle cycle cycle cycle
sequence Addr. Addr. Addr. Addr. Addr. Addr. Addr.
Data Data Data Data Data Data Data
Read 0xXX －－－－－－
0xF0 －－－－－－
Read/Reset 0x54XX 0xAAXX 0x54XX RA －－－
0xAA 0x55 0xF0 RD －－－
ID-Read 0x54XX 0xAAXX 0x54XX IA 0xXX －－
0xAA 0x55 0x90 0x00 ID －－
Automatic page 0x54XX 0xAAXX 0x54XX PA PA PA PA
programming 0xAA 0x55 0xA0 PD0 PD1 PD2 PD3
Automatic chip 0x54XX 0xAAXX 0x54XX 0x54XX 0xAAXX 0x54XX －
erase 0xAA 0x55 0x80 0xAA 0x55 0x10 －
Auto 0x54XX 0xAAXX 0x54XX 0x54XX 0xAAXX BA －
Block erase 0xAA 0x55 0x80 0xAA 0x55 0x30 －
Protection bit 0x54XX 0xAAXX 0x54XX 0x54XX 0xAAXX 0x54XX PBA
programming 0xAA 0x55 0x9A 0xAA 0x55 0x9A 0x9A
Protection bit 0x54XX 0xAAXX 0x54XX 0x54XX 0xAAXX 0x54XX PBA
erase 0xAA 0x55 0x6A 0xAA 0x55 0x6A 0x6A
Supplementary explanation
• RA: Read address
• RD: Read data
• IA: ID address
• ID: ID data
• PA: Program page address
PD: Program data (32 bit data)
After the fourth bus cycle, enter data in the order of the address for a page.
• BA: Block address
• PBA: Protection bit address
(Note 1) Always set "0" to the address bits [1:0] in the entire bus cycle. (Recommendable setting
values to bits [7:2] are ”0”.)
(Note 2) Bus cycles are "bus write cycles" except for the second bus cycle of the Read command,
the fourth bus cycle of the Read/reset command, and the fifth bus cycle of the ID-Read
command. Bus write cycles are executed by 32-bit data transfer commands. The address
[31:16] in each bus write cycle should be the target flash memory address [31:16] of the
command sequence. Use "Addr." in the table for the address [15:0].

TMPM370
(7) Address bit configuration for bus write cycles

Table 20-18 Address Bit Configuration for Bus Write Cycles
Addr Addr Addr Addr Addr Addr Addr Addr Addr Addr Addr
Address
[31:19] [18] [17] [16] [15] [14] [13:11] [10] [9] [8] [7:0]
Normal bus write cycle address configuration

Normal
Addr[1:0]=“0” (fixed)
commands
Flash area “0” is recommended. Command Others:0
(recommended)
ID IA: ID address (Set the fourth bus write cycle address for ID-Read operation)
-READ
Flash area “0” is recommended. ID address Addr[1:0]=“0” (fixed) , Others:0 (recommended)
Block erase
BA: Block address (Set the sixth bus write cycle address for block erase operation)
Block selection (Table 20-19) Addr[1:0]=“0” (fixed) , Others:0 (recommended)
Auto page
PA: Program page address (Set the fourth bus write cycle address for page programming operation)
programming Addr[1:0]=“0” (fixed)
Page selection
Others:0 (recommended)
PBA: Protection bit address (Set the seventh bus erase cycle address for protection bit erasure)
Protection bit
Protection bit
programming Protection bit selection Addr[1:0]=“0” (fixed)
Flash area Fixed to “0”. selection
(Table 20-20) Others:0 (recommended)
(Table 20-20)
PBA: Protection bit address (Set the seventh bus erase cycle address for protection bit erasure)
Protection bit
Protection bit Protection bit
erase Addr[1:0]=“0” (fixed)
Flash area selection “0” is recommended. selection
Others:0 (recommended)
(Table 20-21) (Table 20-21)
Block erase
BA: Block address (Set the sixth bus write cycle address for block erase operation)
Block selection (Table 20-19) Addr[1:0]=“0” (fixed) , Others:0 (recommended)
(Note 1) Table 20-17 "Flash Memory Access from the Internal CPU" can also be used.
(Note 2) Address setting can be performed according to the "Normal bus write cycle address
configuration" from the first bus cycle.
(Note 3) "0" is recommended" can be changed as necessary.

TMPM370
Table 20-19 Block Address Table
Size
Block
Address Address (Kbyte)
(User boot mode) (Single boot mode)
4 0x0000_0000-0x0000_3FFF 0x3F80_0000-0x3F80_3FFF 16
5 0x0000_4000-0x0000_7FFF 0x3F80_4000-0x3F80_7FFF 16
3 0x0000_8000-0x0000_FFFF 0x3F80_8000-0x3F80_FFFF 32
2 0x0001_0000-0x0001_FFFF 0x3F81_0000-0x3F81_FFFF 64
1 0x0002_0000-0x0002_FFFF 0x3F82_0000-0x3F82_FFFF 64
0 0x0003_0000-0x0003_FFFF 0x3F83_8000-0x3F83_FFFF 64
As block address, specify any address in the block to be erased.
(Note) As for the addresses from the first to the fifth bus cycles, specify the upper 4
bit with the corresponding flash memory addresses of the blocks to be
erased.

TMPM370
Table 20-20 Protection Bit Programming Address Table

The seventh bus write cycle address
Block Protection bit Address Address Address Address Address Address Address
[18] [17] [16] [15:11] [10] [9] [8]
[TMPM370FY]
Block0 BLPRO0 0 0 0 0
Fixed to “0”.
Table 20-21 Protection Bit Erase Address Table

Block Protection The seventh bus write cycle address [18:17]
bit Address [18] Address [17]
Block0～3 BLPRO0～3 0 0
Block4～5 BLPRO4～5 0 1
(Note) The protection bit erase command cannot erase by individual block.
Table 20-22 The ID-Read command's fourth bus write cycle ID address (IA) and
the data to be read by the following 32-bit data transfer command (ID)
IA [15:14] ID [7: 0 ] Code
Manufact
00b 0x98
urer code
Device
01b 0x5A
code
10b Reserved ---
Macro
11b 0x13
code

TMPM370
(8) Flowchart
Start
Automatic page programming command sequence

(see the flowchart shown below)
Address = Address + 0x200 No The address of the

(set by a page) last page?
YES
Automatic page programming
Automatic Page Programming Command Sequence (Address/ Command)
0x54xx/0xAA
0xAAxx/0x55
0x54xx/0xA0
Programming address (page address)/

Programming data (32 bit data)
(Note) Command sequence is executed by
0x54xx or 0x55xx.
Fig. 20-10 Automatic Programming

TMPM370
Start
Automatic chip erase command sequence

(see the flowchart shown below)
Automatic chip erase completed
Automatic chip erase command sequence Automatic block/ multi-block erase command sequence
(address/ command) (address/ command)
0x54xx/0xAA 0x54xx/0xAA
0xAAxx/0x55 0xAAxx/0x55
0x54xx/0x80 0x54xx/0x80
0x54xx/0xAA 0x54xx/0xAA
0xAAxx/0x55 0xAAxx/0x55
0x54xx/0x10 Block address/0x30
(Note) Command sequence is executed by

0x54xx or 0x55xx.
Fig. 20-11 Automatic Erase

TMPM370
21. Protect/security function

21.1 OutLine
The TMPM370FY offers two kinds of ROM protect/ security functions. One is a write/ erase-protect
function for the internal flash ROM data. The other is a security function that restricts internal flash
ROM data readout and debugging.
21.2 Feature
21.2.1 Internal Flash ROM write/erase protect
The write/ erase-protect function enables the internal flash to prohibit the writing and erasing
operation for each block.
This function is available with a single chip mode, single boot mode and writer mode. To activate
the function, write “1” to the corresponding bits to a block to protect. Writing “0” to the bits cancels
the protection. The protection status of the bits can be monitored by the FCFLCS <BLPRO> bit.
TMPM370 21-1 Protect/security function

TMPM370
21.2.2 Security function

The security function restricts flash ROM data readout and debugging.
This function is available under the conditions shown below.
1) The FCSECBIT <SECBIT> bit is set to”1”.

2) All the protection bits (the FCFLCS<BLPRO> bits) used to the write/erase-protect function
are set to “1”.
Note) The FCSECBIT <SECBIT> bit is set to “1” at a power-on reset right after power-on.
Table 21-1 shows details of the restrictions by the security function.
Table 21-1 Restrictions by the security function

Item Details
1) ROM data readout The ROM reading operation from CPU is available.
2) Debug port Communication of JTAG/Seria Wire and trace are
prohibited.
3) Command for flash memory Writing a command to the flash memory is prohibited. An
attempt to erase the contents in the bits used for the
write/erase-protection will erase all the contents of flash
memory include protection bits.

TMPM370
21.3 Resisters
The flash control register shows the status of the flash memory operation and the protection of each
block.
Table 21-2 Flash control resister
31 30 29 28 27 26 25 24
bit Symbol - - - - - - - -
FCFLCS Read/Write R
function “0”is read
23 22 21 20 19 18 17 16
bit Symbol - - BLPRO5 BLPRO4 BLPRO3 BLPRO2 BLPRO1 BLPRO0
Read/Write R R R R R R R
after Reset 0 (note2) (note2) (note2) (note2) (note2) (note2)
Block5 Block4 Block3 Block2 Block1 Block0
Reading data is “0” protect protect protect protect protect protect
status status status status status status
function 0: no 0: no 0: no 0: no 0: no 0: no
protect protect protect protect protect protect
status. status. status. status. status. status.
1: protect 1: protect 1: protect 1: protect 1: protect 1: protect
status. status. status. status. status. status.
15 14 13 12 11 10 9 8
bit Symbol - - - - - - - -
Read/Write R
after reset 0
function reading data is “0”
7 6 5 4 3 2 1 0
bit Symbol - - - - - - - RDY/BSY
Read/Write R R
after reset 0 1
reading data is “0” Ready/

Busy
(note1)
0:under
Function auto
operation
1:fauto
operation
is finished
Bit 0: Ready/Busy flag bit

The RDY/BSY output is provided as a means to monitor the status of automatic operation. .
When the flash memory is in automatic operation, it outputs "0" to indicate that it is busy.
When the automatic operation is terminated, it returns to the ready state and outputs "1" to
accept the next command. If the automatic operation has failed, this bit maintains the "0"
output. By applying a hardware reset, it returns to "1."
Bit [21:16]: Protection status bits

Each of the protection bits (6 bits) represents the protection status of the corresponding block.
When a bit is set to "1," it indicates that the block corresponding to the bit is protected. When
the block is protected, data cannot be written to it.

TMPM370
(Note 1) This command must be issued in the ready state. Issuing the command in the
busy state may disable both correct command transmission and further
command input. To exit from the condition, execute system reset. System reset
requires at least 0.5 microseconds regardless of the system clock frequency.
In this condition, it takes approx. 2 ms to enable reading after reset.
(Note 2) The value varies depending on protection status.
Table 21-3 security bit resister

31 30 29 28 27 26 25 24
bit Symbol - - - - - - - -
FCSECBIT Read/Write R
0x41FF_F010 after reset 0
23 22 21 20 19 18 17 16
bit Symbol - - - - - - - -
Read/Write R
after reset 0
reading data is “0”
function
15 14 13 12 11 10 9 8
bit Symbol - - - - - - - -
Read/Write R
after reset 0
7 6 5 4 3 2 1 0
bit Symbol - - - - - - - SECBIT
Read/Write R R/W
after reset 0 1
reading data is “0” security bit
0:
function disable
1:
enable
(Note) This register is initialized only by power-on reset.

TMPM370
21.4 Writing and erasing

21.4.1 Protection bits
Writing and erasing protection bits are available with a single chip mode, single boot mode and
writer mode.
Writing to the protection bits is done on block-by-block basis.
Erasing of the protection bits is done by two groups of the blocks: block 0 through 3 and block 4
through 5. When the settings for all the blocks are “1”, erasing must be done after clearing the
FCSECBIT <SECBIT> bit to “0”. An attempt to erase protection bits when <SECBIT> bit is “1”, it will
erases all the contents of flash memory include protection bits. To write and erase the protection bits,
command sequence is used.
See chapter 18 for details.
21.4.2 Security bit

The FCSECBIT <SECBIT> bit that activates security function is set to “1” at a power-on reset right
after power-on. It can be Rewritten at single chip mode and single boot mode.by the following
procedure.
1) Write the code 0xa74a9d23 to FCSECBIT register.

2) Write data within 16 clocks from the writing above.
Note) The above procedure is enabled only when using 32-bit data transfer command.

TMPM370
22 Special Function Registers
[1] Port registers
[2] 16-bit timer (TMRB)
[3] Encoder input (ENC)
[4] Serial interface (UART/SIO)
[5] 12-bit A/D converter (A/DC)
[6] OP-amp (AMP), Comparator (CMP)
[7] Watchdog timer (WDT)
[8] Clock generator (CG)
[9] Oscillation frequency detector (OFD)
[10] Power on reset (POR), Voltage detecting circuit (VLTD)
[11] Vector engine (VE)
[12] Programmable motor driver (PMD)
[13] Flash
[14] Reserved area
(Note 1) As for the internal I/O areas (0x4000_0000~0x4007_FFFF), reading the areas not
described in this chapter yields undefined value. Writing these areas is ignored.
(Note 2) <R0> means 0(zero) is read. Writing data is disregarded.
(Note3) Access to the <Reserved> areas is prohibited.
TMPM370 22-1 Special Function Registers

TMPM370
22.1 Addresses
22.1.1 [1] Port [1/4]
<PORT A>
ADR Register ADR Register ADR Register ADR Register
name name name name
0x4000_0000 PADATA 0x4000_0010 0x4000_0020 0x4000_0030 PAPDN
0x4000_0001 <R0> 0x4000_0011 0x4000_0021 0x4000_0031 <R0>
0x4000_0002 <R0> 0x4000_0012 0x4000_0022 0x4000_0032 <R0>
0x4000_0003 <R0> 0x4000_0013 0x4000_0023 0x4000_0033 <R0>
0x4000_0004 PACR 0x4000_0014 0x4000_0024 0x4000_0034
0x4000_0005 <R0> 0x4000_0015 0x4000_0025 0x4000_0035
0x4000_0006 <R0> 0x4000_0016 0x4000_0026 0x4000_0036
0x4000_0007 <R0> 0x4000_0017 0x4000_0027 0x4000_0037
0x4000_0008 PAFR1 0x4000_0018 0x4000_0028 PAOD 0x4000_0038 PAIE
0x4000_0009 <R0> 0x4000_0019 0x4000_0029 <R0> 0x4000_0039 <R0>
0x4000_000A <R0> 0x4000_001A 0x4000_002A <R0> 0x4000_003A <R0>
0x4000_000B <R0> 0x4000_001B 0x4000_002B <R0> 0x4000_003B <R0>
0x4000_000C PAFR2 0x4000_001C 0x4000_002C PAPUP 0x4000_003C
0x4000_000D <R0> 0x4000_001D 0x4000_002D <R0> 0x4000_003D
0x4000_000E <R0> 0x4000_001E 0x4000_002E <R0> 0x4000_003E
0x4000_000F <R0> 0x4000_001F 0x4000_002F <R0> 0x4000_003F
<PORT B>
name name name name
0x4000_0040 PBDATA 0x4000_0050 0x4000_0060 0x4000_0070 PBPDN
0x4000_0041 <R0> 0x4000_0051 0x4000_0061 0x4000_0071 <R0>
0x4000_0042 <R0> 0x4000_0052 0x4000_0062 0x4000_0072 <R0>
0x4000_0043 <R0> 0x4000_0053 0x4000_0063 0x4000_0073 <R0>
0x4000_0044 PBCR 0x4000_0054 0x4000_0064 0x4000_0074
0x4000_0045 <R0> 0x4000_0055 0x4000_0065 0x4000_0075
0x4000_0046 <R0> 0x4000_0056 0x4000_0066 0x4000_0076
0x4000_0047 <R0> 0x4000_0057 0x4000_0067 0x4000_0077
0x4000_0048 PBFR1 0x4000_0058 0x4000_0068 PBOD 0x4000_0078 PBIE
0x4000_0049 <R0> 0x4000_0059 0x4000_0069 <R0> 0x4000_0079 <R0>
0x4000_004A <R0> 0x4000_005A 0x4000_006A <R0> 0x4000_007A <R0>
0x4000_004B <R0> 0x4000_005B 0x4000_006B <R0> 0x4000_007B <R0>
0x4000_004C 0x4000_005C 0x4000_006C PBPUP 0x4000_007C
0x4000_004D 0x4000_005D 0x4000_006D <R0> 0x4000_007D
0x4000_004E 0x4000_005E 0x4000_006E <R0> 0x4000_007E
0x4000_004F 0x4000_005F 0x4000_006F <R0> 0x4000_007F
<PORT C>
name name name name
0x4000_0080 PCDATA 0x4000_0090 0x4000_00A0 0x4000_00B0 PCPDN
0x4000_0081 <R0> 0x4000_0091 0x4000_00A1 0x4000_00B1 <R0>
0x4000_0082 <R0> 0x4000_0092 0x4000_00A2 0x4000_00B2 <R0>
0x4000_0083 <R0> 0x4000_0093 0x4000_00A3 0x4000_00B3 <R0>
0x4000_0084 PCCR 0x4000_0094 0x4000_00A4 0x4000_00B4
0x4000_0085 <R0> 0x4000_0095 0x4000_00A5 0x4000_00B5
0x4000_0086 <R0> 0x4000_0096 0x4000_00A6 0x4000_00B6
0x4000_0087 <R0> 0x4000_0097 0x4000_00A7 0x4000_00B7
0x4000_0088 PCFR1 0x4000_0098 0x4000_00A8 PCOD 0x4000_00B8 PCIE
0x4000_0089 <R0> 0x4000_0099 0x4000_00A9 <R0> 0x4000_00B9 <R0>
0x4000_008A <R0> 0x4000_009A 0x4000_00AA <R0> 0x4000_00BA <R0>
0x4000_008B <R0> 0x4000_009B 0x4000_00AB <R0> 0x4000_00BB <R0>
0x4000_008C 0x4000_009C 0x4000_00AC PCPUP 0x4000_00BC
0x4000_008D 0x4000_009D 0x4000_00AD <R0> 0x4000_00BD
0x4000_008E 0x4000_009E 0x4000_00AE <R0> 0x4000_00BE
0x4000_008F 0x4000_009F 0x4000_00AF <R0> 0x4000_00BF

TMPM370
[1] Port [2/4]
<PORT D>
name name name name
0x4000_00C0 PDDATA 0x4000_00D0 0x4000_00E0 0x4000_00F0 PDPDN
0x4000_00C1 <R0> 0x4000_00D1 0x4000_00E1 0x4000_00F1 <R0>
0x4000_00C2 <R0> 0x4000_00D2 0x4000_00E2 0x4000_00F2 <R0>
0x4000_00C3 <R0> 0x4000_00D3 0x4000_00E3 0x4000_00F3 <R0>
0x4000_00C4 PDCR 0x4000_00D4 0x4000_00E4 0x4000_00F4
0x4000_00C5 <R0> 0x4000_00D5 0x4000_00E5 0x4000_00F5
0x4000_00C6 <R0> 0x4000_00D6 0x4000_00E6 0x4000_00F6
0x4000_00C7 <R0> 0x4000_00D7 0x4000_00E7 0x4000_00F7
0x4000_00C8 PDFR1 0x4000_00D8 0x4000_00E8 PDOD 0x4000_00F8 PDIE
0x4000_00C9 <R0> 0x4000_00D9 0x4000_00E9 <R0> 0x4000_00F9 <R0>
0x4000_00CA <R0> 0x4000_00DA 0x4000_00EA <R0> 0x4000_00FA <R0>
0x4000_00CB <R0> 0x4000_00DB 0x4000_00EB <R0> 0x4000_00FB <R0>
0x4000_00CC PDFR2 0x4000_00DC 0x4000_00EC PDPUP 0x4000_00FC
0x4000_00CD <R0> 0x4000_00DD 0x4000_00ED <R0> 0x4000_00FD
0x4000_00CE <R0> 0x4000_00DE 0x4000_00EE <R0> 0x4000_00FE
0x4000_00CF <R0> 0x4000_00DF 0x4000_00EF <R0> 0x4000_00FF
<PORT E>
name name name name
0x4000_0100 PEDATA 0x4000_0110 0x4000_0120 0x4000_0130 PEPDN
0x4000_0101 <R0> 0x4000_0111 0x4000_0121 0x4000_0131 <R0>
0x4000_0102 <R0> 0x4000_0112 0x4000_0122 0x4000_0132 <R0>
0x4000_0103 <R0> 0x4000_0113 0x4000_0123 0x4000_0133 <R0>
0x4000_0104 PECR 0x4000_0114 0x4000_0124 0x4000_0134
0x4000_0105 <R0> 0x4000_0115 0x4000_0125 0x4000_0135
0x4000_0106 <R0> 0x4000_0116 0x4000_0126 0x4000_0136
0x4000_0107 <R0> 0x4000_0117 0x4000_0127 0x4000_0137
0x4000_0108 PEFR1 0x4000_0118 0x4000_0128 PEOD 0x4000_0138 PEIE
0x4000_0109 <R0> 0x4000_0119 0x4000_0129 <R0> 0x4000_0139 <R0>
0x4000_010A <R0> 0x4000_011A 0x4000_012A <R0> 0x4000_013A <R0>
0x4000_010B <R0> 0x4000_011B 0x4000_012B <R0> 0x4000_013B <R0>
0x4000_010C PEFR2 0x4000_011C 0x4000_012C PEPUP 0x4000_013C
0x4000_010D <R0> 0x4000_011D 0x4000_012D <R0> 0x4000_013D
0x4000_010E <R0> 0x4000_011E 0x4000_012E <R0> 0x4000_013E
0x4000_010F <R0> 0x4000_011F 0x4000_012F <R0> 0x4000_013F
<PORT F>
name name name name
0x4000_0140 PFDATA 0x4000_0150 PFFR3 0x4000_0160 0x4000_0170 PFPDN
0x4000_0141 <R0> 0x4000_0151 <R0> 0x4000_0161 0x4000_0171 <R0>
0x4000_0142 <R0> 0x4000_0152 <R0> 0x4000_0162 0x4000_0172 <R0>
0x4000_0143 <R0> 0x4000_0153 <R0> 0x4000_0163 0x4000_0173 <R0>
0x4000_0144 PFCR 0x4000_0154 0x4000_0164 0x4000_0174
0x4000_0145 <R0> 0x4000_0155 0x4000_0165 0x4000_0175
0x4000_0146 <R0> 0x4000_0156 0x4000_0166 0x4000_0176
0x4000_0147 <R0> 0x4000_0157 0x4000_0167 0x4000_0177
0x4000_0148 PFFR1 0x4000_0158 0x4000_0168 PFOD 0x4000_0178 PFIE
0x4000_0149 <R0> 0x4000_0159 0x4000_0169 <R0> 0x4000_0179 <R0>
0x4000_014A <R0> 0x4000_015A 0x4000_016A <R0> 0x4000_017A <R0>
0x4000_014B <R0> 0x4000_015B 0x4000_016B <R0> 0x4000_017B <R0>
0x4000_014C PFFR2 0x4000_015C 0x4000_016C PFPUP 0x4000_017C
0x4000_014D <R0> 0x4000_015D 0x4000_016D <R0> 0x4000_017D
0x4000_014E <R0> 0x4000_015E 0x4000_016E <R0> 0x4000_017E
0x4000_014F <R0> 0x4000_015F 0x4000_016F <R0> 0x4000_017F

TMPM370
[1] Port [3/4]
<PORT G>
name name name name
0x4000_0180 PGDATA 0x4000_0190 0x4000_01A0 0x4000_01B0 PGPDN
0x4000_0181 <R0> 0x4000_0191 0x4000_01A1 0x4000_01B1 <R0>
0x4000_0182 <R0> 0x4000_0192 0x4000_01A2 0x4000_01B2 <R0>
0x4000_0183 <R0> 0x4000_0193 0x4000_01A3 0x4000_01B3 <R0>
0x4000_0184 PGCR 0x4000_0194 0x4000_01A4 0x4000_01B4
0x4000_0185 <R0> 0x4000_0195 0x4000_01A5 0x4000_01B5
0x4000_0186 <R0> 0x4000_0196 0x4000_01A6 0x4000_01B6
0x4000_0187 <R0> 0x4000_0197 0x4000_01A7 0x4000_01B7
0x4000_0188 PGFR1 0x4000_0198 0x4000_01A8 PGOD 0x4000_01B8 PGIE
0x4000_0189 <R0> 0x4000_0199 0x4000_01A9 <R0> 0x4000_01B9 <R0>
0x4000_018A <R0> 0x4000_019A 0x4000_01AA <R0> 0x4000_01BA <R0>
0x4000_018B <R0> 0x4000_019B 0x4000_01AB <R0> 0x4000_01BB <R0>
0x4000_018C 0x4000_019C 0x4000_01AC PGPUP 0x4000_01BC
0x4000_018D 0x4000_019D 0x4000_01AD <R0> 0x4000_01BD
0x4000_018E 0x4000_019E 0x4000_01AE <R0> 0x4000_01BE
0x4000_018F 0x4000_019F 0x4000_01AF <R0> 0x4000_01BF
<PORT H>
name name name name
0x4000_01C0 PHDATA 0x4000_01D0 0x4000_01E0 0x4000_01F0 PHPDN
0x4000_01C1 <R0> 0x4000_01D1 0x4000_01E1 0x4000_01F1 <R0>
0x4000_01C2 <R0> 0x4000_01D2 0x4000_01E2 0x4000_01F2 <R0>
0x4000_01C3 <R0> 0x4000_01D3 0x4000_01E3 0x4000_01F3 <R0>
0x4000_01C4 PHCR 0x4000_01D4 0x4000_01E4 0x4000_01F4
0x4000_01C5 <R0> 0x4000_01D5 0x4000_01E5 0x4000_01F5
0x4000_01C6 <R0> 0x4000_01D6 0x4000_01E6 0x4000_01F6
0x4000_01C7 <R0> 0x4000_01D7 0x4000_01E7 0x4000_01F7
0x4000_01C8 PHFR1 0x4000_01D8 0x4000_01E8 PHOD 0x4000_01F8 PHIE
0x4000_01C9 <R0> 0x4000_01D9 0x4000_01E9 <R0> 0x4000_01F9 <R0>
0x4000_01CA <R0> 0x4000_01DA 0x4000_01EA <R0> 0x4000_01FA <R0>
0x4000_01CB <R0> 0x4000_01DB 0x4000_01EB <R0> 0x4000_01FB <R0>
0x4000_01CC 0x4000_01DC 0x4000_01EC PHPUP 0x4000_01FC
0x4000_01CD 0x4000_01DD 0x4000_01ED <R0> 0x4000_01FD
0x4000_01CE 0x4000_01DE 0x4000_01EE <R0> 0x4000_01FE
0x4000_01CF 0x4000_01DF 0x4000_01EF <R0> 0x4000_01FF
<PORT I>
name name name name
0x4000_0200 PIDATA 0x4000_0210 0x4000_0220 0x4000_0230 PIPDN
0x4000_0201 <R0> 0x4000_0211 0x4000_0221 0x4000_0231 <R0>
0x4000_0202 <R0> 0x4000_0212 0x4000_0222 0x4000_0232 <R0>
0x4000_0203 <R0> 0x4000_0213 0x4000_0223 0x4000_0233 <R0>
0x4000_0204 PICR 0x4000_0214 0x4000_0224 0x4000_0234
0x4000_0205 <R0> 0x4000_0215 0x4000_0225 0x4000_0235
0x4000_0206 <R0> 0x4000_0216 0x4000_0226 0x4000_0236
0x4000_0207 <R0> 0x4000_0217 0x4000_0227 0x4000_0237
0x4000_0208 0x4000_0218 0x4000_0228 PIOD 0x4000_0238 PIIE
0x4000_0209 0x4000_0219 0x4000_0229 <R0> 0x4000_0239 <R0>
0x4000_020A 0x4000_021A 0x4000_022A <R0> 0x4000_023A <R0>
0x4000_020B 0x4000_021B 0x4000_022B <R0> 0x4000_023B <R0>
0x4000_020C 0x4000_021C 0x4000_022C PIPUP 0x4000_023C
0x4000_020D 0x4000_021D 0x4000_022D <R0> 0x4000_023D
0x4000_020E 0x4000_021E 0x4000_022E <R0> 0x4000_023E
0x4000_020F 0x4000_021F 0x4000_022F <R0> 0x4000_023F

TMPM370
[1] Port [4/4]
<PORT J>
name name name name
0x4000_0240 PJDATA 0x4000_0250 0x4000_0260 0x4000_0270 PJPDN
0x4000_0241 <R0> 0x4000_0251 0x4000_0261 0x4000_0271 <R0>
0x4000_0242 <R0> 0x4000_0252 0x4000_0262 0x4000_0272 <R0>
0x4000_0243 <R0> 0x4000_0253 0x4000_0263 0x4000_0273 <R0>
0x4000_0244 PJCR 0x4000_0254 0x4000_0264 0x4000_0274
0x4000_0245 <R0> 0x4000_0255 0x4000_0265 0x4000_0275
0x4000_0246 <R0> 0x4000_0256 0x4000_0266 0x4000_0276
0x4000_0247 <R0> 0x4000_0257 0x4000_0267 0x4000_0277
0x4000_0248 PJFR1 0x4000_0258 0x4000_0268 PJOD 0x4000_0278 PJIE
0x4000_0249 <R0> 0x4000_0259 0x4000_0269 <R0> 0x4000_0279 <R0>
0x4000_024A <R0> 0x4000_025A 0x4000_026A <R0> 0x4000_027A <R0>
0x4000_024B <R0> 0x4000_025B 0x4000_026B <R0> 0x4000_027B <R0>
0x4000_024C 0x4000_025C 0x4000_026C PJPUP 0x4000_027C
0x4000_024D 0x4000_025D 0x4000_026D <R0> 0x4000_027D
0x4000_024E 0x4000_025E 0x4000_026E <R0> 0x4000_027E
0x4000_024F 0x4000_025F 0x4000_026F <R0> 0x4000_027F
<PORT K>
name name name name
0x4000_0280 PKDATA 0x4000_0290 0x4000_02A0 0x4000_02B0 PKPDN
0x4000_0281 <R0> 0x4000_0291 0x4000_02A1 0x4000_02B1 <R0>
0x4000_0282 <R0> 0x4000_0292 0x4000_02A2 0x4000_02B2 <R0>
0x4000_0283 <R0> 0x4000_0293 0x4000_02A3 0x4000_02B3 <R0>
0x4000_0284 PKCR 0x4000_0294 0x4000_02A4 0x4000_02B4
0x4000_0285 <R0> 0x4000_0295 0x4000_02A5 0x4000_02B5
0x4000_0286 <R0> 0x4000_0296 0x4000_02A6 0x4000_02B6
0x4000_0287 <R0> 0x4000_0297 0x4000_02A7 0x4000_02B7
0x4000_0288 PKFR1 0x4000_0298 0x4000_02A8 PKOD 0x4000_02B8 PKIE
0x4000_0289 <R0> 0x4000_0299 0x4000_02A9 <R0> 0x4000_02B9 <R0>
0x4000_028A <R0> 0x4000_029A 0x4000_02AA <R0> 0x4000_02BA <R0>
0x4000_028B <R0> 0x4000_029B 0x4000_02AB <R0> 0x4000_02BB <R0>
0x4000_028C 0x4000_029C 0x4000_02AC PKPUP 0x4000_02BC
0x4000_028D 0x4000_029D 0x4000_02AD <R0> 0x4000_02BD
0x4000_028E 0x4000_029E 0x4000_02AE <R0> 0x4000_02BE
0x4000_028F 0x4000_029F 0x4000_02AF <R0> 0x4000_02BF
<PORT L>
name name name name
0x4000_02C0 PLDATA 0x4000_02D0 0x4000_02E0 0x4000_02F0
0x4000_02C1 <R0> 0x4000_02D1 0x4000_02E1 0x4000_02F1
0x4000_02C2 <R0> 0x4000_02D2 0x4000_02E2 0x4000_02F2
0x4000_02C3 <R0> 0x4000_02D3 0x4000_02E3 0x4000_02F3
0x4000_02C4 0x4000_02D4 0x4000_02E4 0x4000_02F4
0x4000_02C5 0x4000_02D5 0x4000_02E5 0x4000_02F5
0x4000_02C6 0x4000_02D6 0x4000_02E6 0x4000_02F6
0x4000_02C7 0x4000_02D7 0x4000_02E7 0x4000_02F7
0x4000_02C8 PLFR1 0x4000_02D8 0x4000_02E8 0x4000_02F8 PLIE
0x4000_02C9 <R0> 0x4000_02D9 0x4000_02E9 0x4000_02F9 <R0>
0x4000_02CA <R0> 0x4000_02DA 0x4000_02EA 0x4000_02FA <R0>
0x4000_02CB <R0> 0x4000_02DB 0x4000_02EB 0x4000_02FB <R0>
0x4000_02CC 0x4000_02DC 0x4000_02EC 0x4000_02FC
0x4000_02CD 0x4000_02DD 0x4000_02ED 0x4000_02FD
0x4000_02CE 0x4000_02DE 0x4000_02EE 0x4000_02FE
0x4000_02CF 0x4000_02DF 0x4000_02EF 0x4000_02FF

TMPM370
22.1.2 [2] 16-bit timer [1/3]

<TMRB0>
name name name name
0x4001_0000 TB0EN 0x4001_0010 TB0FFCR 0x4001_0020 TB0RG0 0x4001_0030
0x4001_0001 <R0> 0x4001_0011 <R0> 0x4001_0021 “ 0x4001_0031
0x4001_0002 <R0> 0x4001_0012 <R0> 0x4001_0022 <R0> 0x4001_0032
0x4001_0003 <R0> 0x4001_0013 <R0> 0x4001_0023 <R0> 0x4001_0033
0x4001_0004 TB0RUN 0x4001_0014 TB0ST 0x4001_0024 TB0RG1 0x4001_0034
0x4001_0005 <R0> 0x4001_0015 <R0> 0x4001_0025 “ 0x4001_0035
0x4001_0006 <R0> 0x4001_0016 <R0> 0x4001_0026 <R0> 0x4001_0036
0x4001_0007 <R0> 0x4001_0017 <R0> 0x4001_0027 <R0> 0x4001_0037
0x4001_0008 TB0CR 0x4001_0018 TB0IM 0x4001_0028 TB0CP0 0x4001_0038
0x4001_0009 <R0> 0x4001_0019 <R0> 0x4001_0029 “ 0x4001_0039
0x4001_000A <R0> 0x4001_001A <R0> 0x4001_002A <R0> 0x4001_003A
0x4001_000B <R0> 0x4001_001B <R0> 0x4001_002B <R0> 0x4001_003B
0x4001_000C TB0MOD 0x4001_001C TB0UC 0x4001_002C TB0CP1 0x4001_003C
0x4001_000D <R0> 0x4001_001D " 0x4001_002D " 0x4001_003D
0x4001_000E <R0> 0x4001_001E <R0> 0x4001_002E <R0> 0x4001_003E
0x4001_000F <R0> 0x4001_001F <R0> 0x4001_002F <R0> 0x4001_003F
<TMRB1>
name name name name
0x4001_0041 <R0> 0x4001_0051 <R0> 0x4001_0061 " 0x4001_0071
0x4001_0042 <R0> 0x4001_0052 <R0> 0x4001_0062 <R0> 0x4001_0072
0x4001_0043 <R0> 0x4001_0053 <R0> 0x4001_0063 <R0> 0x4001_0073
0x4001_0045 <R0> 0x4001_0055 <R0> 0x4001_0065 " 0x4001_0075
0x4001_0046 <R0> 0x4001_0056 <R0> 0x4001_0066 <R0> 0x4001_0076
0x4001_0047 <R0> 0x4001_0057 <R0> 0x4001_0067 <R0> 0x4001_0077
0x4001_0049 <R0> 0x4001_0059 <R0> 0x4001_0069 " 0x4001_0079
0x4001_004A <R0> 0x4001_005A <R0> 0x4001_006A <R0> 0x4001_007A
0x4001_004B <R0> 0x4001_005B <R0> 0x4001_006B <R0> 0x4001_007B
0x4001_004D <R0> 0x4001_005D " 0x4001_006D " 0x4001_007D
0x4001_004E <R0> 0x4001_005E <R0> 0x4001_006E <R0> 0x4001_007E
0x4001_004F <R0> 0x4001_005F <R0> 0x4001_006F <R0> 0x4001_007F
<TMRB2>
name name name name
0x4001_0080 TB2EN 0x4001_0090 TB2FFCR 0x4001_00A0 TB2RG0 0x4001_00B0

0x4001_0081 <R0> 0x4001_0091 <R0> 0x4001_00A1 " 0x4001_00B1
0x4001_0082 <R0> 0x4001_0092 <R0> 0x4001_00A2 <R0> 0x4001_00B2
0x4001_0083 <R0> 0x4001_0093 <R0> 0x4001_00A3 <R0> 0x4001_00B3
0x4001_0084 TB2RUN 0x4001_0094 TB2ST 0x4001_00A4 TB2RG1 0x4001_00B4
0x4001_0085 <R0> 0x4001_0095 <R0> 0x4001_00A5 " 0x4001_00B5
0x4001_0086 <R0> 0x4001_0096 <R0> 0x4001_00A6 <R0> 0x4001_00B6
0x4001_0087 <R0> 0x4001_0097 <R0> 0x4001_00A7 <R0> 0x4001_00B7
0x4001_0088 TB2CR 0x4001_0098 TB2IM 0x4001_00A8 TB2CP0 0x4001_00B8
0x4001_0089 <R0> 0x4001_0099 <R0> 0x4001_00A9 " 0x4001_00B9
0x4001_008A <R0> 0x4001_009A <R0> 0x4001_00AA <R0> 0x4001_00BA
0x4001_008B <R0> 0x4001_009B <R0> 0x4001_00AB <R0> 0x4001_00BB
0x4001_008C TB2MOD 0x4001_009C TB2UC 0x4001_00AC TB2CP1 0x4001_00BC
0x4001_008D <R0> 0x4001_009D " 0x4001_00AD " 0x4001_00BD
0x4001_008E <R0> 0x4001_009E <R0> 0x4001_00AE <R0> 0x4001_00BE
0x4001_008F <R0> 0x4001_009F <R0> 0x4001_00AF <R0> 0x4001_00BF

TMPM370
[2] 16-bit timer [2/3]
<TMRB3>
name name name name
0x4001_00C0 TB3EN 0x4001_00D0 TB3FFCR 0x4001_00E0 TB3RG0 0x4001_00F0
0x4001_00C1 <R0> 0x4001_00D1 <R0> 0x4001_00E1 " 0x4001_00F1
0x4001_00C2 <R0> 0x4001_00D2 <R0> 0x4001_00E2 <R0> 0x4001_00F2
0x4001_00C3 <R0> 0x4001_00D3 <R0> 0x4001_00E3 <R0> 0x4001_00F3
0x4001_00C4 TB3RUN 0x4001_00D4 TB3ST 0x4001_00E4 TB3RG1 0x4001_00F4
0x4001_00C5 <R0> 0x4001_00D5 <R0> 0x4001_00E5 " 0x4001_00F5
0x4001_00C6 <R0> 0x4001_00D6 <R0> 0x4001_00E6 <R0> 0x4001_00F6
0x4001_00C7 <R0> 0x4001_00D7 <R0> 0x4001_00E7 <R0> 0x4001_00F7
0x4001_00C8 TB3CR 0x4001_00D8 TB3IM 0x4001_00E8 TB3CP0 0x4001_00F8
0x4001_00C9 <R0> 0x4001_00D9 <R0> 0x4001_00E9 " 0x4001_00F9
0x4001_00CA <R0> 0x4001_00DA <R0> 0x4001_00EA <R0> 0x4001_00FA
0x4001_00CB <R0> 0x4001_00DB <R0> 0x4001_00EB <R0> 0x4001_00FB
0x4001_00CC TB3MOD 0x4001_00DC TB3UC 0x4001_00EC TB3CP1 0x4001_00FC
0x4001_00CD <R0> 0x4001_00DD " 0x4001_00ED " 0x4001_00FD
0x4001_00CE <R0> 0x4001_00DE <R0> 0x4001_00EE <R0> 0x4001_00FE
0x4001_00CF <R0> 0x4001_00DF <R0> 0x4001_00EF <R0> 0x4001_00FF
<TMRB4>
name name name name
0x4001_0101 <R0> 0x4001_0111 <R0> 0x4001_0121 " 0x4001_0131
0x4001_0102 <R0> 0x4001_0112 <R0> 0x4001_0122 <R0> 0x4001_0132
0x4001_0103 <R0> 0x4001_0113 <R0> 0x4001_0123 <R0> 0x4001_0133
0x4001_0105 <R0> 0x4001_0115 <R0> 0x4001_0125 " 0x4001_0135
0x4001_0106 <R0> 0x4001_0116 <R0> 0x4001_0126 <R0> 0x4001_0136
0x4001_0107 <R0> 0x4001_0117 <R0> 0x4001_0127 <R0> 0x4001_0137
0x4001_0109 <R0> 0x4001_0119 <R0> 0x4001_0129 " 0x4001_0139
0x4001_010A <R0> 0x4001_011A <R0> 0x4001_012A <R0> 0x4001_013A
0x4001_010B <R0> 0x4001_011B <R0> 0x4001_012B <R0> 0x4001_013B
0x4001_010D <R0> 0x4001_011D " 0x4001_012D " 0x4001_013D "
0x4001_010E <R0> 0x4001_011E <R0> 0x4001_012E <R0> 0x4001_013E
0x4001_010F <R0> 0x4001_011F <R0> 0x4001_012F <R0> 0x4001_013F
<TMRB5>
name name name name
0x4001_0141 <R0> 0x4001_0151 <R0> 0x4001_0161 " 0x4001_0171
0x4001_0142 <R0> 0x4001_0152 <R0> 0x4001_0162 <R0> 0x4001_0172
0x4001_0143 <R0> 0x4001_0153 <R0> 0x4001_0163 <R0> 0x4001_0173
0x4001_0145 <R0> 0x4001_0155 <R0> 0x4001_0165 " 0x4001_0175
0x4001_0146 <R0> 0x4001_0156 <R0> 0x4001_0166 <R0> 0x4001_0176
0x4001_0147 <R0> 0x4001_0157 <R0> 0x4001_0167 <R0> 0x4001_0177
0x4001_0149 <R0> 0x4001_0159 <R0> 0x4001_0169 " 0x4001_0179
0x4001_014A <R0> 0x4001_015A <R0> 0x4001_016A <R0> 0x4001_017A
0x4001_014B <R0> 0x4001_015B <R0> 0x4001_016B <R0> 0x4001_017B
0x4001_014D <R0> 0x4001_015D " 0x4001_016D " 0x4001_017D
0x4001_014E <R0> 0x4001_015E <R0> 0x4001_016E <R0> 0x4001_017E
0x4001_014F <R0> 0x4001_015F <R0> 0x4001_016F <R0> 0x4001_017F

TMPM370
[2] 16-bit timer [3/3]
<TMRB6>
name name name name
0x4001_0180 TB6EN 0x4001_0190 TB6FFCR 0x4001_01A0 TB6RG0 0x4001_01B0
0x4001_0181 <R0> 0x4001_0191 <R0> 0x4001_01A1 " 0x4001_01B1
0x4001_0182 <R0> 0x4001_0192 <R0> 0x4001_01A2 <R0> 0x4001_01B2
0x4001_0183 <R0> 0x4001_0193 <R0> 0x4001_01A3 <R0> 0x4001_01B3
0x4001_0184 TB6RUN 0x4001_0194 TB6ST 0x4001_01A4 TB6RG1 0x4001_01B4
0x4001_0185 <R0> 0x4001_0195 <R0> 0x4001_01A5 " 0x4001_01B5
0x4001_0186 <R0> 0x4001_0196 <R0> 0x4001_01A6 <R0> 0x4001_01B6
0x4001_0187 <R0> 0x4001_0197 <R0> 0x4001_01A7 <R0> 0x4001_01B7
0x4001_0188 TB6CR 0x4001_0198 TB6IM 0x4001_01A8 TB6CP0 0x4001_01B8
0x4001_0189 <R0> 0x4001_0199 <R0> 0x4001_01A9 " 0x4001_01B9
0x4001_018A <R0> 0x4001_019A <R0> 0x4001_01AA <R0> 0x4001_01BA
0x4001_018B <R0> 0x4001_019B <R0> 0x4001_01AB <R0> 0x4001_01BB
0x4001_018C TB6MOD 0x4001_019C TB6UC 0x4001_01AC TB6CP1 0x4001_01BC
0x4001_018D <R0> 0x4001_019D " 0x4001_01AD " 0x4001_01BD
0x4001_018E <R0> 0x4001_019E <R0> 0x4001_01AE <R0> 0x4001_01BE
0x4001_018F <R0> 0x4001_019F <R0> 0x4001_01AF <R0> 0x4001_01BF
<TMRB7>
name name name name
0x4001_01C0 TB7EN 0x4001_01D0 TB7FFCR 0x4001_01E0 TB7RG0 0x4001_01F0
0x4001_01C1 <R0> 0x4001_01D1 <R0> 0x4001_01E1 " 0x4001_01F1
0x4001_01C2 <R0> 0x4001_01D2 <R0> 0x4001_01E2 <R0> 0x4001_01F2
0x4001_01C3 <R0> 0x4001_01D3 <R0> 0x4001_01E3 <R0> 0x4001_01F3
0x4001_01C4 TB7RUN 0x4001_01D4 TB7ST 0x4001_01E4 TB7RG1 0x4001_01F4
0x4001_01C5 <R0> 0x4001_01D5 <R0> 0x4001_01E5 " 0x4001_01F5
0x4001_01C6 <R0> 0x4001_01D6 <R0> 0x4001_01E6 <R0> 0x4001_01F6
0x4001_01C7 <R0> 0x4001_01D7 <R0> 0x4001_01E7 <R0> 0x4001_01F7
0x4001_01C8 TB7CR 0x4001_01D8 TB7IM 0x4001_01E8 TB7CP0 0x4001_01F8
0x4001_01C9 <R0> 0x4001_01D9 <R0> 0x4001_01E9 " 0x4001_01F9
0x4001_01CC TB7MOD 0x4001_01DC TB7UC 0x4001_01EC TB7CP1 0x4001_01FC
0x4001_01CD <R0> 0x4001_01DD " 0x4001_01ED " 0x4001_01FD

TMPM370
22.1.3 [3] Encoder input (ENC)

<ENC0>
name name name name
0x4001_0400 EN0TNCR 0x4001_0410 0x4001_0420 0x4001_0430
0x4001_0401 " 0x4001_0411 0x4001_0421 0x4001_0431
0x4001_0402 " 0x4001_0412 0x4001_0422 0x4001_0432
0x4001_0403 <R0> 0x4001_0413 0x4001_0423 0x4001_0433
0x4001_0404 EN0RELOAD 0x4001_0414 0x4001_0424 0x4001_0434
0x4001_0405 " 0x4001_0415 0x4001_0425 0x4001_0435
0x4001_0406 <R0> 0x4001_0416 0x4001_0426 0x4001_0436
0x4001_0407 <R0> 0x4001_0417 0x4001_0427 0x4001_0437
0x4001_0408 EN0INT 0x4001_0418 0x4001_0428 0x4001_0438
0x4001_0409 " 0x4001_0419 0x4001_0429 0x4001_0439
0x4001_040A " 0x4001_041A 0x4001_042A 0x4001_043A
0x4001_040B <R0> 0x4001_041B 0x4001_042B 0x4001_043B
0x4001_040C EN0CNT 0x4001_041C 0x4001_042C 0x4001_043C
0x4001_040D " 0x4001_041D 0x4001_042D 0x4001_043D
0x4001_040E " 0x4001_041E 0x4001_042E 0x4001_043E
0x4001_040F <R0> 0x4001_041F 0x4001_042F 0x4001_043F
<ENC1>
name name name name
0x4001_0500 EN1TNCR 0x4001_0510 0x4001_0520 0x4001_0530
0x4001_0501 " 0x4001_0511 0x4001_0521 0x4001_0531
0x4001_0502 " 0x4001_0512 0x4001_0522 0x4001_0532
0x4001_0503 <R0> 0x4001_0513 0x4001_0523 0x4001_0533
0x4001_0504 EN1RELOAD 0x4001_0514 0x4001_0524 0x4001_0534
0x4001_0505 " 0x4001_0515 0x4001_0525 0x4001_0535
0x4001_0506 <R0> 0x4001_0516 0x4001_0526 0x4001_0536
0x4001_0507 <R0> 0x4001_0517 0x4001_0527 0x4001_0537
0x4001_0508 EN1INT 0x4001_0518 0x4001_0528 0x4001_0538
0x4001_0509 " 0x4001_0519 0x4001_0529 0x4001_0539
0x4001_050A " 0x4001_051A 0x4001_052A 0x4001_053A
0x4001_050B <R0> 0x4001_051B 0x4001_052B 0x4001_053B
0x4001_050C EN1CNT 0x4001_051C 0x4001_052C 0x4001_053C
0x4001_050D " 0x4001_051D 0x4001_052D 0x4001_053D
0x4001_050E " 0x4001_051E 0x4001_052E 0x4001_053E
0x4001_050F <R0> 0x4001_051F 0x4001_052F 0x4001_053F

TMPM370
22.1.4 [4] Serial interface (UART/SIO) [1/2]

<SIO0>
name name name name
0x4002_0080 SC0EN 0x4002_0090 SC0BRCR 0x4002_00A0 SC0RFC 0x4002_00B0 SC0FCNF
0x4002_0081 <R0> 0x4002_0091 <R0> 0x4002_00A1 <R0> 0x4002_00B1 <R0>
0x4002_0082 <R0> 0x4002_0092 <R0> 0x4002_00A2 <R0> 0x4002_00B2 <R0>
0x4002_0083 <R0> 0x4002_0093 <R0> 0x4002_00A3 <R0> 0x4002_00B3 <R0>
0x4002_0084 SC0BUF 0x4002_0094 SC0BRADD 0x4002_00A4 SC0TFC 0x4002_00B4
0x4002_0085 <R0> 0x4002_0095 <R0> 0x4002_00A5 <R0> 0x4002_00B5
0x4002_0086 <R0> 0x4002_0096 <R0> 0x4002_00A6 <R0> 0x4002_00B6
0x4002_0087 <R0> 0x4002_0097 <R0> 0x4002_00A7 <R0> 0x4002_00B7
0x4002_0088 SC0CR 0x4002_0098 SC0MOD1 0x4002_00A8 SC0RST 0x4002_00B8
0x4002_0089 <R0> 0x4002_0099 <R0> 0x4002_00A9 <R0> 0x4002_00B9
0x4002_008A <R0> 0x4002_009A <R0> 0x4002_00AA <R0> 0x4002_00BA
0x4002_008B <R0> 0x4002_009B <R0> 0x4002_00AB <R0> 0x4002_00BB
0x4002_008C SC0MOD0 0x4002_009C SC0MOD2 0x4002_00AC SC0TST 0x4002_00BC
0x4002_008D <R0> 0x4002_009D <R0> 0x4002_00AD <R0> 0x4002_00BD
0x4002_008E <R0> 0x4002_009E <R0> 0x4002_00AE <R0> 0x4002_00BE
0x4002_008F <R0> 0x4002_009F <R0> 0x4002_00AF <R0> 0x4002_00BF
<SIO1>
name name name name
0x4002_00C0 SC1EN 0x4002_00D0 SC1BRCR 0x4002_00E0 SC1RFC 0x4002_00F0 SC1FCNF
0x4002_00C1 <R0> 0x4002_00D1 <R0> 0x4002_00E1 <R0> 0x4002_00F1 <R0>
0x4002_00C2 <R0> 0x4002_00D2 <R0> 0x4002_00E2 <R0> 0x4002_00F2 <R0>
0x4002_00C3 <R0> 0x4002_00D3 <R0> 0x4002_00E3 <R0> 0x4002_00F3 <R0>
0x4002_00C4 SC1BUF 0x4002_00D4 SC1BRADD 0x4002_00E4 SC1TFC 0x4002_00F4
0x4002_00C5 <R0> 0x4002_00D5 <R0> 0x4002_00E5 <R0> 0x4002_00F5
0x4002_00C6 <R0> 0x4002_00D6 <R0> 0x4002_00E6 <R0> 0x4002_00F6
0x4002_00C7 <R0> 0x4002_00D7 <R0> 0x4002_00E7 <R0> 0x4002_00F7
0x4002_00C8 SC1CR 0x4002_00D8 SC1MOD1 0x4002_00E8 SC1RST 0x4002_00F8
0x4002_00C9 <R0> 0x4002_00D9 <R0> 0x4002_00E9 <R0> 0x4002_00F9
0x4002_00CC SC1MOD0 0x4002_00DC SC1MOD2 0x4002_00EC SC1TST 0x4002_00FC
0x4002_00CD <R0> 0x4002_00DD <R0> 0x4002_00ED <R0> 0x4002_00FD

TMPM370
[4] Serial interface (UART/SIO) [2/2]

<SIO2>
name name name name
0x4002_0100 SC2EN 0x4002_0110 SC2BRCR 0x4002_0120 SC2RFC 0x4002_0130 SC2FCNF
0x4002_0101 <R0> 0x4002_0111 <R0> 0x4002_0121 <R0> 0x4002_0131 <R0>
0x4002_0102 <R0> 0x4002_0112 <R0> 0x4002_0122 <R0> 0x4002_0132 <R0>
0x4002_0103 <R0> 0x4002_0113 <R0> 0x4002_0123 <R0> 0x4002_0133 <R0>
0x4002_0104 SC2BUF 0x4002_0114 SC2BRADD 0x4002_0124 SC2TFC 0x4002_0134
0x4002_0105 <R0> 0x4002_0115 <R0> 0x4002_0125 <R0> 0x4002_0135
0x4002_0106 <R0> 0x4002_0116 <R0> 0x4002_0126 <R0> 0x4002_0136
0x4002_0107 <R0> 0x4002_0117 <R0> 0x4002_0127 <R0> 0x4002_0137
0x4002_0108 SC2CR 0x4002_0118 SC2MOD1 0x4002_0128 SC2RST 0x4002_0138
0x4002_0109 <R0> 0x4002_0119 <R0> 0x4002_0129 <R0> 0x4002_0139
0x4002_010A <R0> 0x4002_011A <R0> 0x4002_012A <R0> 0x4002_013A
0x4002_010B <R0> 0x4002_011B <R0> 0x4002_012B <R0> 0x4002_013B
0x4002_010C SC2MOD0 0x4002_011C SC2MOD2 0x4002_012C SC2TST 0x4002_013C
0x4002_010D <R0> 0x4002_011D <R0> 0x4002_012D <R0> 0x4002_013D
0x4002_010E <R0> 0x4002_011E <R0> 0x4002_012E <R0> 0x4002_013E
0x4002_010F <R0> 0x4002_011F <R0> 0x4002_012F <R0> 0x4002_013F
<SIO3>
name name name name
0x4002_0140 SC3EN 0x4002_0150 SC3BRCR 0x4002_0160 SC3RFC 0x4002_0170 SC3FCNF
0x4002_0141 <R0> 0x4002_0151 <R0> 0x4002_0161 <R0> 0x4002_0171 <R0>
0x4002_0142 <R0> 0x4002_0152 <R0> 0x4002_0162 <R0> 0x4002_0172 <R0>
0x4002_0143 <R0> 0x4002_0153 <R0> 0x4002_0163 <R0> 0x4002_0173 <R0>
0x4002_0144 SC3BUF 0x4002_0154 SC3BRADD 0x4002_0164 SC3TFC 0x4002_0174
0x4002_0145 <R0> 0x4002_0155 <R0> 0x4002_0165 <R0> 0x4002_0175
0x4002_0146 <R0> 0x4002_0156 <R0> 0x4002_0166 <R0> 0x4002_0176
0x4002_0147 <R0> 0x4002_0157 <R0> 0x4002_0167 <R0> 0x4002_0177
0x4002_0148 SC3CR 0x4002_0158 SC3MOD1 0x4002_0168 SC3RST 0x4002_0178
0x4002_0149 <R0> 0x4002_0159 <R0> 0x4002_0169 <R0> 0x4002_0179
0x4002_014A <R0> 0x4002_015A <R0> 0x4002_016A <R0> 0x4002_017A
0x4002_014B <R0> 0x4002_015B <R0> 0x4002_016B <R0> 0x4002_017B
0x4002_014C SC3MOD0 0x4002_015C SC3MOD2 0x4002_016C SC3TST 0x4002_017C
0x4002_014D <R0> 0x4002_015D <R0> 0x4002_016D <R0> 0x4002_017D
0x4002_014E <R0> 0x4002_015E <R0> 0x4002_016E <R0> 0x4002_017E
0x4002_014F <R0> 0x4002_015F <R0> 0x4002_016F <R0> 0x4002_017F

TMPM370
22.1.5 [5] 12-bit A/D converter (A/DC) [1/4]

<ADC A>
ADR Register name ADR Register name ADR Register name ADR Register name
0x4003_0000 ADACLK 0x4003_0010 ADACMPCR0 0x4003_0020 ADAREG0 0x4003_0030 ADAREG4
0x4003_0001 " 0x4003_0011 " 0x4003_0021 " 0x4003_0031 "
0x4003_0002 " 0x4003_0012 " 0x4003_0022 " 0x4003_0032 "
0x4003_0003 " 0x4003_0013 " 0x4003_0023 " 0x4003_0033 "
0x4003_0004 ADAMOD0 0x4003_0014 ADACMPCR1 0x4003_0024 ADAREG1 0x4003_0034 ADAREG5
0x4003_0005 " 0x4003_0015 " 0x4003_0025 " 0x4003_0035 "
0x4003_0006 " 0x4003_0016 " 0x4003_0026 " 0x4003_0036 "
0x4003_0007 " 0x4003_0017 " 0x4003_0027 " 0x4003_0037 "
0x4003_0008 ADAMOD1 0x4003_0018 ADACMP0 0x4003_0028 ADAREG2 0x4003_0038 ADAREG6
0x4003_0009 " 0x4003_0019 " 0x4003_0029 " 0x4003_0039 "
0x4003_000A " 0x4003_001A " 0x4003_002A " 0x4003_003A "
0x4003_000B " 0x4003_001B " 0x4003_002B " 0x4003_003B "
0x4003_000C ADAMOD2 0x4003_001C ADACMP1 0x4003_002C ADAREG3 0x4003_003C ADAREG7
0x4003_000D " 0x4003_001D " 0x4003_002D " 0x4003_003D "
0x4003_000E " 0x4003_001E " 0x4003_002E " 0x4003_003E "
0x4003_000F " 0x4003_001F " 0x4003_002F " 0x4003_003F "
0x4003_0040 ADAREG8 0x4003_0050 ADAPSEL0 0x4003_0060 ADAPSEL4 0x4003_0070 ADAPSEL8
0x4003_0041 " 0x4003_0051 " 0x4003_0061 " 0x4003_0071 "
0x4003_0042 " 0x4003_0052 " 0x4003_0062 " 0x4003_0072 "
0x4003_0043 " 0x4003_0053 " 0x4003_0063 " 0x4003_0073 "
0x4003_0045 " 0x4003_0055 " 0x4003_0065 " 0x4003_0075 "
0x4003_0046 " 0x4003_0056 " 0x4003_0066 " 0x4003_0076 "
0x4003_0047 " 0x4003_0057 " 0x4003_0067 " 0x4003_0077 "
0x4003_0049 " 0x4003_0059 " 0x4003_0069 " 0x4003_0079 "
0x4003_004A " 0x4003_005A " 0x4003_006A " 0x4003_007A "
0x4003_004B " 0x4003_005B " 0x4003_006B " 0x4003_007B "
0x4003_004C ADAREG11 0x4003_005C ADAPSEL3 0x4003_006C ADAPSEL7 0x4003_007C ADAPSEL11
0x4003_004D " 0x4003_005D " 0x4003_006D " 0x4003_007D "
0x4003_004E " 0x4003_005E " 0x4003_006E " 0x4003_007E "
0x4003_004F " 0x4003_005F " 0x4003_006F " 0x4003_007F "
0x4003_0080 ADAPINTS0 0x4003_0090 ADAPINTS4 0x4003_00A0 ADAPSET2 0x4003_00B0 ADATSET03
0x4003_0081 " 0x4003_0091 " 0x4003_00A1 " 0x4003_00B1 "
0x4003_0082 " 0x4003_0092 " 0x4003_00A2 " 0x4003_00B2 "
0x4003_0083 " 0x4003_0093 " 0x4003_00A3 " 0x4003_00B3 "
0x4003_0084 ADAPINTS1 0x4003_0094 ADAPINTS5 0x4003_00A4 ADAPSET3 0x4003_00B4 ADATSET47
0x4003_0085 " 0x4003_0095 " 0x4003_00A5 " 0x4003_00B5 "
0x4003_0086 " 0x4003_0096 " 0x4003_00A6 " 0x4003_00B6 "
0x4003_0087 " 0x4003_0097 " 0x4003_00A7 " 0x4003_00B7 "
0x4003_0088 ADAPINTS2 0x4003_0098 ADAPSET0 0x4003_00A8 ADAPSET4 0x4003_00B8 ADATSET811
0x4003_0089 " 0x4003_0099 " 0x4003_00A9 " 0x4003_00B9 "
0x4003_008A " 0x4003_009A " 0x4003_00AA " 0x4003_00BA "
0x4003_008B " 0x4003_009B " 0x4003_00AB " 0x4003_00BB "
0x4003_008C ADAPINTS3 0x4003_009C ADAPSET1 0x4003_00AC ADAPSET5 0x4003_00BC ADASSET03
0x4003_008D " 0x4003_009D " 0x4003_00AD " 0x4003_00BD "
0x4003_008E " 0x4003_009E " 0x4003_00AE " 0x4003_00BE "
0x4003_008F " 0x4003_009F " 0x4003_00AF " 0x4003_00BF "

TMPM370
[5] 12-bit A/D converter (A/DC) [2/4]
0x4003_00C0 ADASSET47 0x4003_00D0 ADAASET811 0x4003_00E0 0x4003_00F0
0x4003_00C1 " 0x4003_00D1 " 0x4003_00E1 0x4003_00F1
0x4003_00C2 " 0x4003_00D2 " 0x4003_00E2 0x4003_00F2
0x4003_00C3 " 0x4003_00D3 " 0x4003_00E3 0x4003_00F3
0x4003_00C4 ADASSET811 0x4003_00D4 ADAMOD3 0x4003_00E4 0x4003_00F4
0x4003_00C5 " 0x4003_00D5 " 0x4003_00E5 0x4003_00F5
0x4003_00C6 " 0x4003_00D6 " 0x4003_00E6 0x4003_00F6
0x4003_00C7 " 0x4003_00D7 " 0x4003_00E7 0x4003_00F7
0x4003_00C8 ADAASET03 0x4003_00D8 0x4003_00E8 0x4003_00F8
0x4003_00C9 " 0x4003_00D9 0x4003_00E9 0x4003_00F9
0x4003_00CA " 0x4003_00DA 0x4003_00EA 0x4003_00FA
0x4003_00CB " 0x4003_00DB 0x4003_00EB 0x4003_00FB
0x4003_00CC ADAASET47 0x4003_00DC 0x4003_00EC 0x4003_00FC
0x4003_00CD " 0x4003_00DD 0x4003_00ED 0x4003_00FD
0x4003_00CE " 0x4003_00DE 0x4003_00EE 0x4003_00FE
0x4003_00CF " 0x4003_00DF 0x4003_00EF 0x4003_00FF

TMPM370
[5]12-bit A/D converter (A/DC) [3/4]
<ADC B>
0x4003_0200 ADBCLK 0x4003_0210 ADBCMPCR0 0x4003_0220 ADBREG0 0x4003_0230 ADBREG4
0x4003_0201 " 0x4003_0211 " 0x4003_0221 " 0x4003_0231 "
0x4003_0202 " 0x4003_0212 " 0x4003_0222 " 0x4003_0232 "
0x4003_0203 " 0x4003_0213 " 0x4003_0223 " 0x4003_0233 "
0x4003_0204 ADBMOD0 0x4003_0214 ADBCMPCR1 0x4003_0224 ADBREG1 0x4003_0234 ADBREG5
0x4003_0205 " 0x4003_0215 " 0x4003_0225 " 0x4003_0235 "
0x4003_0206 " 0x4003_0216 " 0x4003_0226 " 0x4003_0236 "
0x4003_0207 " 0x4003_0217 " 0x4003_0227 " 0x4003_0237 "
0x4003_0208 ADBMOD1 0x4003_0218 ADBCMP0 0x4003_0228 ADBREG2 0x4003_0238 ADBREG6
0x4003_0209 " 0x4003_0219 " 0x4003_0229 " 0x4003_0239 "
0x4003_020A " 0x4003_021A " 0x4003_022A " 0x4003_023A “
0x4003_020B " 0x4003_021B " 0x4003_022B " 0x4003_023B "
0x4003_020C ADBMOD2 0x4003_021C ADBCMP1 0x4003_022C ADBREG3 0x4003_023C ADBREG7
0x4003_020D " 0x4003_021D " 0x4003_022D " 0x4003_023D "
0x4003_020E " 0x4003_021E 0x4003_022E " 0x4003_023E "
0x4003_020F " 0x4003_021F 0x4003_022F " 0x4003_023F "
0x4003_0240 ADBREG8 0x4003_0250 ADBPSEL0 0x4003_0260 ADBPSEL4 0x4003_0270 ADBPSEL8
0x4003_0241 " 0x4003_0251 " 0x4003_0261 " 0x4003_0271 "
0x4003_0242 " 0x4003_0252 " 0x4003_0262 " 0x4003_0272 "
0x4003_0243 " 0x4003_0253 " 0x4003_0263 " 0x4003_0273 "
0x4003_0245 " 0x4003_0255 " 0x4003_0265 " 0x4003_0275 "
0x4003_0246 " 0x4003_0256 " 0x4003_0266 " 0x4003_0276 "
0x4003_0247 " 0x4003_0257 " 0x4003_0267 " 0x4003_0277 "
0x4003_0249 " 0x4003_0259 " 0x4003_0269 " 0x4003_0279 "
0x4003_024A " 0x4003_025A " 0x4003_026A " 0x4003_027A "
0x4003_024B " 0x4003_025B " 0x4003_026B " 0x4003_027B "
0x4003_024C ADBREG11 0x4003_025C ADBPSEL3 0x4003_026C ADBPSEL7 0x4003_027C ADBPSEL11
0x4003_024D " 0x4003_025D " 0x4003_026D " 0x4003_027D "
0x4003_024E " 0x4003_025E " 0x4003_026E " 0x4003_027E "
0x4003_024F " 0x4003_025F " 0x4003_026F " 0x4003_027F "
0x4003_0280 ADBPINTS0 0x4003_0290 ADBPINTS4 0x4003_02A0 ADBPSET2 0x4003_02B0 ADBTSET03
0x4003_0281 " 0x4003_0291 " 0x4003_02A1 " 0x4003_02B1 "
0x4003_0282 " 0x4003_0292 " 0x4003_02A2 " 0x4003_02B2 "
0x4003_0283 " 0x4003_0293 " 0x4003_02A3 " 0x4003_02B3 "
0x4003_0284 ADBPINTS1 0x4003_0294 ADBPINTS5 0x4003_02A4 ADBPSET3 0x4003_02B4 ADBTSET47
0x4003_0285 " 0x4003_0295 " 0x4003_02A5 " 0x4003_02B5 "
0x4003_0286 " 0x4003_0296 " 0x4003_02A6 " 0x4003_02B6 "
0x4003_0287 " 0x4003_0297 " 0x4003_02A7 " 0x4003_02B7 "
0x4003_0288 ADBPINTS2 0x4003_0298 ADBPSET0 0x4003_02A8 ADBPSET4 0x4003_02B8 ADBTSET811
0x4003_0289 " 0x4003_0299 " 0x4003_02A9 " 0x4003_02B9 "
0x4003_028A " 0x4003_029A " 0x4003_02AA " 0x4003_02BA "
0x4003_028B " 0x4003_029B " 0x4003_02AB " 0x4003_02BB "
0x4003_028C ADBPINTS3 0x4003_029C ADBPSET1 0x4003_02AC ADBPSET5 0x4003_02BC ADBSSET03
0x4003_028D " 0x4003_029D " 0x4003_02AD " 0x4003_02BD "
0x4003_028E " 0x4003_029E " 0x4003_02AE " 0x4003_02BE "
0x4003_028F " 0x4003_029F " 0x4003_02AF " 0x4003_02BF "

TMPM370
[5] 12-bit A/D converter (A/DC) [4/4]
0x4003_02C0 ADBSSET47 0x4003_02D0 ADBASET811 0x4003_02E0 0x4003_02F0
0x4003_02C1 " 0x4003_02D1 " 0x4003_02E1 0x4003_02F1
0x4003_02C2 " 0x4003_02D2 " 0x4003_02E2 0x4003_02F2
0x4003_02C3 " 0x4003_02D3 " 0x4003_02E3 0x4003_02F3
0x4003_02C4 ADBSSET811 0x4003_02D4 ADBMOD3 0x4003_02E4 0x4003_02F4
0x4003_02C5 " 0x4003_02D5 " 0x4003_02E5 0x4003_02F5
0x4003_02C6 " 0x4003_02D6 " 0x4003_02E6 0x4003_02F6
0x4003_02C7 " 0x4003_02D7 " 0x4003_02E7 0x4003_02F7
0x4003_02C8 ADBASET03 0x4003_02D8 0x4003_02E8 0x4003_02F8
0x4003_02C9 " 0x4003_02D9 0x4003_02E9 0x4003_02F9
0x4003_02CA " 0x4003_02DA 0x4003_02EA 0x4003_02FA
0x4003_02CB " 0x4003_02DB 0x4003_02EB 0x4003_02FB
0x4003_02CC ADBASET47 0x4003_02DC 0x4003_02EC 0x4003_02FC
0x4003_02CD " 0x4003_02DD 0x4003_02ED 0x4003_02FD
0x4003_02CE " 0x4003_02DE 0x4003_02EE 0x4003_02FE
0x4003_02CF " 0x4003_02DF 0x4003_02EF 0x4003_02FF
22.1.6 [6] OP-amp / Comparator (AMP/CMP)

0x4003_0400 AMPCTLA 0x4003_0410 AMPCTLC 0x4003_0420 CMPCTLA 0x4003_0430 CMPCTLC
0x4003_0401 0x4003_0411 0x4003_0421 0x4003_0431
0x4003_0402 0x4003_0412 0x4003_0422 0x4003_0432
0x4003_0403 0x4003_0413 0x4003_0423 0x4003_0433
0x4003_0404 Reserved 0x4003_0414 Reserved 0x4003_0424 Reserved 0x4003_0434 Reserved
0x4003_0405 0x4003_0415 0x4003_0425 0x4003_0435
0x4003_0406 0x4003_0416 0x4003_0426 0x4003_0436
0x4003_0407 0x4003_0417 0x4003_0427 0x4003_0437
0x4003_0408 AMPCTLB 0x4003_0418 AMPCTLD 0x4003_0428 CMPCTLB 0x4003_0438 CMPCTLD
0x4003_0409 0x4003_0419 0x4003_0429 0x4003_0439
0x4003_040A 0x4003_041A 0x4003_042A 0x4003_043A
0x4003_040B 0x4003_041B 0x4003_042B 0x4003_043B
0x4003_040C Reserved 0x4003_041C Reserved 0x4003_042C Reserved 0x4003_043C Reserved
0x4003_040D 0x4003_041D 0x4003_042D 0x4003_043D
0x4003_040E 0x4003_041E 0x4003_042E 0x4003_043E
0x4003_040F 0x4003_041F 0x4003_042F 0x4003_043F

TMPM370
22.1.7 [7] Watchdog timer (WDT)

name name name name
0x4004_0000 WDMOD 0x4004_0010 0x4004_0020 0x4004_0030
0x4004_0001 <R0> 0x4004_0011 0x4004_0021 0x4004_0031
0x4004_0002 <R0> 0x4004_0012 0x4004_0022 0x4004_0032
0x4004_0003 <R0> 0x4004_0013 0x4004_0023 0x4004_0033
0x4004_0004 WDCR 0x4004_0014 0x4004_0024 0x4004_0034
0x4004_0005 <R0> 0x4004_0015 0x4004_0025 0x4004_0035
0x4004_0006 <R0> 0x4004_0016 0x4004_0026 0x4004_0036
0x4004_0007 <R0> 0x4004_0017 0x4004_0027 0x4004_0037
0x4004_0008 0x4004_0018 0x4004_0028 0x4004_0038
0x4004_0009 0x4004_0019 0x4004_0029 0x4004_0039
0x4004_000A 0x4004_001A 0x4004_002A 0x4004_003A
0x4004_000B 0x4004_001B 0x4004_002B 0x4004_003B
0x4004_000C 0x4004_001C 0x4004_002C 0x4004_003C
0x4004_000D 0x4004_001D 0x4004_002D 0x4004_003D
0x4004_000E 0x4004_001E 0x4004_002E 0x4004_003E
0x4004_000F 0x4004_001F 0x4004_002F 0x4004_003F
22.1.8 [8] Clock generator (CG)

name name name name
0x4004_0200 CGSYSCR 0x4004_0210 CGCKSEL 0x4004_0220 CGIMCGA 0x4004_0230
0x4004_0201 " 0x4004_0211 <R0> 0x4004_0221 " 0x4004_0231
0x4004_0202 " 0x4004_0212 <R0> 0x4004_0222 " 0x4004_0232
0x4004_0203 <R0> 0x4004_0213 <R0> 0x4004_0223 " 0x4004_0233
0x4004_0204 CGOSCCR 0x4004_0214 CGICRCG 0x4004_0224 CGIMCGB 0x4004_0234
0x4004_0205 " 0x4004_0215 <R0> 0x4004_0225 " 0x4004_0235
0x4004_0206 " 0x4004_0216 <R0> 0x4004_0226 " 0x4004_0236
0x4004_0207 " 0x4004_0217 <R0> 0x4004_0227 " 0x4004_0237
0x4004_0208 CGSTBYCR 0x4004_0218 CGNMIFLG 0x4004_0228 CGIMCGC 0x4004_0238
0x4004_0209 " 0x4004_0219 <R0> 0x4004_0229 " 0x4004_0239
0x4004_020A " 0x4004_021A <R0> 0x4004_022A " 0x4004_023A
0x4004_020B <R0> 0x4004_021B <R0> 0x4004_022B " 0x4004_023B
0x4004_020C CGPLLSEL 0x4004_021C CGRSTFLG 0x4004_022C CGIMCGD 0x4004_023C
0x4004_020D " 0x4004_021D <R0> 0x4004_022D " 0x4004_023D
0x4004_020E <R0> 0x4004_021E <R0> 0x4004_022E " 0x4004_023E
0x4004_020F <R0> 0x4004_021F <R0> 0x4004_022F " 0x4004_023F

TMPM370
22.1.9 [9] Oscillation frequency detector (OFD)

0x4004_0800 OFDCR1 0x4004_0810 CLKSMX PLLOFF 0x4004_0820 0x4004_0830
0x4004_0801 <R0> 0x4004_0811 " 0x4004_0821 0x4004_0831
0x4004_0802 <R0> 0x4004_0812 <R0> 0x4004_0822 0x4004_0832
0x4004_0803 <R0> 0x4004_0813 <R0> 0x4004_0823 0x4004_0833
0x4004_0804 OFDCR2 0x4004_0814 CLKSMX PLLON 0x4004_0824 0x4004_0834
0x4004_0805 <R0> 0x4004_0815 " 0x4004_0825 0x4004_0835
0x4004_0806 <R0> 0x4004_0816 <R0> 0x4004_0826 0x4004_0836
0x4004_0807 <R0> 0x4004_0817 <R0> 0x4004_0827 0x4004_0837
0x4004_0808 OFDMIN PLLOFF 0x4004_0818 0x4004_0828 0x4004_0838
0x4004_0809 " 0x4004_0819 0x4004_0829 0x4004_0839
0x4004_080A <R0> 0x4004_081A 0x4004_082A 0x4004_083A
0x4004_080B <R0> 0x4004_081B 0x4004_082B 0x4004_083B
0x4004_080C CLKSMIN PLLON 0x4004_081C 0x4004_082C 0x4004_083C
0x4004_080D " 0x4004_081D 0x4004_082D 0x4004_083D
0x4004_080E <R0> 0x4004_081E 0x4004_082E 0x4004_083E
0x4004_080F <R0> 0x4004_081F 0x4004_082F 0x4004_083F
22.1.10 [10] Power on reset (POR), Voltage detecting circuit (VLTD)

name name name name
0x4004_0900 VDCR 0x4004_0910 0x4004_0920 0x4004_0930
0x4004_0901 0x4004_0911 0x4004_0921 0x4004_0931
0x4004_0902 0x4004_0912 0x4004_0922 0x4004_0932
0x4004_0903 0x4004_0913 0x4004_0923 0x4004_0933
0x4004_0904 Ｒｅｓｅｒｖｅｄ 0x4004_0914 0x4004_0924 0x4004_0934
0x4004_0905 0x4004_0915 0x4004_0925 0x4004_0935
0x4004_0906 0x4004_0916 0x4004_0926 0x4004_0936
0x4004_0907 0x4004_0917 0x4004_0927 0x4004_0937
0x4004_0908 0x4004_0918 0x4004_0928 0x4004_0938
0x4004_0909 0x4004_0919 0x4004_0929 0x4004_0939
0x4004_090A 0x4004_091A 0x4004_092A 0x4004_093A
0x4004_090B 0x4004_091B 0x4004_092B 0x4004_093B
0x4004_090C 0x4004_091C 0x4004_092C 0x4004_093C
0x4004_090D 0x4004_091D 0x4004_092D 0x4004_093D
0x4004_090E 0x4004_091E 0x4004_092E 0x4004_093E
0x4004_090F 0x4004_091F 0x4004_092F 0x4004_093F

TMPM370
22.1.11 [11] Vector engine (VE) [1/3]

name name name name
0x4005_0000 VEEN 0x4005_0010 VEREPTIME 0x4005_0020 VEERRDET 0x4005_0030 VETMPREG1
0x4005_0001 <R0> 0x4005_0011 <R0> 0x4005_0021 <R0> 0x4005_0031 "
0x4005_0002 <R0> 0x4005_0012 <R0> 0x4005_0022 <R0> 0x4005_0032 "
0x4005_0003 <R0> 0x4005_0013 <R0> 0x4005_0023 <R0> 0x4005_0033 "
0x4005_0004 VECPURUNTRG 0x4005_0014 VETRGMODE 0x4005_ 0024 VESCHTASKRUN 0x4005_0034 VETMPREG2
0x4005_0005 <R0> 0x4005_0015 <R0> 0x4005_0025 " 0x4005_0035 "
0x4005_0006 <R0> 0x4005_0016 <R0> 0x4005_0026 <R0> 0x4005_0036 "
0x4005_0007 <R0> 0x4005_0017 <R0> 0x4005_0027 <R0> 0x4005_0037 "
0x4005_0008 VETASKAPP 0x4005_0018 VEERRINTEN 0x4005_0028 Reserved 0x4005_0038 VETMPREG3
0x4005_0009 <R0> 0x4005_0019 <R0> 0x4005_0029 Reserved 0x4005_0039 "
0x4005_000A <R0> 0x4005_001A <R0> 0x4005_002A Reserved 0x4005_003A "
0x4005_000B <R0> 0x4005_001B <R0> 0x4005_002B Reserved 0x4005_003B "
0x4005_000C VEACTSCH 0x4005_001C VECOMPEND 0x4005_002C VETMPREG0 0x4005_003C VETMPREG4
0x4005_000D <R0> 0x4005_001D <R0> 0x4005_002D “ 0x4005_003D “
0x4005_000E <R0> 0x4005_001E <R0> 0x4005_002E “ 0x4005_003E “
0x4005_000F <R0> 0x4005_001F <R0> 0x4005_002F “ 0x4005_003F “

name name name name
0x4005_0040 VETMPREG5 0x4005_0050 VETPWM0 0x4005_0060 VEIQREF0 0x4005_0070 VECIDKP0
0x4005_0041 " 0x4005_0051 " 0x4005_0061 " 0x4005_0071 "
0x4005_0042 " 0x4005_0052 <R0> 0x4005_0062 <R0> 0x4005_0072 <R0>
0x4005_0043 " 0x4005_0053 <R0> 0x4005_0063 <R0> 0x4005_0073 <R0>
0x4005_0044 VEMCTLF0 0x4005_0054 VEOMEGA0 0x4005_0064 VEVD0 0x4005_0074 VECIQKI0
0x4005_0045 " 0x4005_0055 " 0x4005_0065 <R0> 0x4005_0075 "
0x4005_0046 <R0> 0x4005_0056 <R0> 0x4005_0066 <R0> 0x4005_0076 <R0>
0x4005_0047 <R0> 0x4005_0057 <R0> 0x4005_0067 <R0> 0x4005_0077 <R0>
0x4005_0048 VEMODE0 0x4005_0058 VETHETA0 0x4005_0068 VEVQ0 0x4005_0078 VECIQKP0
0x4005_0049 <R0> 0x4005_0059 " 0x4005_0069 <R0> 0x4005_0079 "
0x4005_004A <R0> 0x4005_005A <R0> 0x4005_006A <R0> 0x4005_007A <R0>
0x4005_004B <R0> 0x4005_005B <R0> 0x4005_006B <R0> 0x4005_007B <R0>
0x4005_004C VEFMODE0 0x4005_005C VEIDREF0 0x4005_006C VECIDKI0 0x4005_007C VEVDIH0
0x4005_004D “ 0x4005_005D “ 0x4005_006D “ 0x4005_007D “
0x4005_004E <R0> 0x4005_005E <R0> 0x4005_006E <R0> 0x4005_007E <R0>
0x4005_004F <R0> 0x4005_005F <R0> 0x4005_006F <R0> 0x4005_007F <R0>

name name name name
0x4005_0080 VEVDILH0 0x4005_0090 VEVMDPRD0 0x4005_00A0 VECOS0 0x4005_00B0 VESECTOR0
0x4005_0081 " 0x4005_0091 " 0x4005_00A1 " 0x4005_00B1 <R0>
0x4005_0082 <R0> 0x4005_0092 <R0> 0x4005_00A2 <R0> 0x4005_00B2 <R0>
0x4005_0083 <R0> 0x4005_0093 <R0> 0x4005_00A3 <R0> 0x4005_00B3 <R0>
0x4005_0084 VEVQIH0 0x4005_0094 VEMINPLS0 0x4005_00A4 VESIN0 0x4005_00B4 VESECTORM0
0x4005_0085 " 0x4005_0095 " 0x4005_00A5 " 0x4005_00B5 <R0>
0x4005_0086 <R0> 0x4005_0096 <R0> 0x4005_00A6 <R0> 0x4005_00B6 <R0>
0x4005_0087 <R0> 0x4005_0097 <R0> 0x4005_00A7 <R0> 0x4005_00B7 <R0>
0x4005_0088 VEVQILH0 0x4005_0098 VETRGCRC0 0x4005_00A8 VECOSM0 0x4005_00B8 VEIAO0
0x4005_0089 " 0x4005_0099 “ 0x4005_00A9 " 0x4005_00B9 "
0x4005_008A <R0> 0x4005_009A <R0> 0x4005_00AA <R0> 0x4005_00BA <R0>
0x4005_008B <R0> 0x4005_009B <R0> 0x4005_00AB <R0> 0x4005_00BB <R0>
0x4005_008C VEFPWMCHG0 0x4005_009C Reserved 0x4005_00AC VESINM0 0x4005_00BC VEIBO0
0x4005_008D “ 0x4005_009D Reserved 0x4005_00AD “ 0x4005_00BD “
0x4005_008E <R0> 0x4005_009E Reserved 0x4005_00AE <R0> 0x4005_00BE <R0>
0x4005_008F <R0> 0x4005_009F Reserved 0x4005_00AF <R0> 0x4005_00BF <R0>

TMPM370
[11] Vector engine (VE) [2/3]
name name name name
0x4005_00C0 VEICO0 0x4005_00D0 VEVDC0 0x4005_00E0 VEMODE1 0x4005_00F0 VETHETA1
0x4005_00C1 " 0x4005_00D1 " 0x4005_00E1 <R0> 0x4005_00F1 "
0x4005_00C2 <R0> 0x4005_00D2 <R0> 0x4005_00E2 <R0> 0x4005_00F2 <R0>
0x4005_00C3 <R0> 0x4005_00D3 <R0> 0x4005_00E3 <R0> 0x4005_00F3 <R0>
0x4005_00C4 VEIAADC0 0x4005_00D4 VEID0 0x4005_00E4 VEFMODE1 0x4005_00F4 VEIDREF1
0x4005_00C5 " 0x4005_00D5 " 0x4005_00E5 " 0x4005_00F5 "
0x4005_00C6 <R0> 0x4005_00D6 " 0x4005_00E6 <R0> 0x4005_00F6 <R0>
0x4005_00C7 <R0> 0x4005_00D7 " 0x4005_00E7 <R0> 0x4005_00F7 <R0>
0x4005_00C8 VEIBADC0 0x4005_00D8 VEIQ0 0x4005_00E8 VETPWM1 0x4005_00F8 VEIQREF1
0x4005_00C9 " 0x4005_00D9 " 0x4005_00E9 " 0x4005_00F9 "
0x4005_00CA <R0> 0x4005_00DA " 0x4005_00EA <R0> 0x4005_00FA <R0>
0x4005_00CB <R0> 0x4005_00DB " 0x4005_00EB <R0> 0x4005_00FB <R0>
0x4005_00CC VEICADC0 0x4005_00DC VEMCTLF1 0x4005_00EC VEOMEGA1 0x4005_00FC VEVD1
0x4005_00CD “ 0x4005_00DD <R0> 0x4005_00ED “ 0x4005_00FD <R0>
0x4005_00CE <R0> 0x4005_00DE <R0> 0x4005_00EE <R0> 0x4005_00FE <R0>
0x4005_00CF <R0> 0x4005_00DF <R0> 0x4005_00EF <R0> 0x4005_00FF <R0>

name name name name
0x4005_0100 VEVQ1 0x4005_0110 VECIQKP1 0x4005_0120 VEVQILH1 0x4005_0130 VETRGCRC1
0x4005_0101 <R0> 0x4005_0111 " 0x4005_0121 " 0x4005_0131 "
0x4005_0102 <R0> 0x4005_0112 <R0> 0x4005_0122 <R0> 0x4005_0132 <R0>
0x4005_0103 <R0> 0x4005_0113 <R0> 0x4005_0123 <R0> 0x4005_0133 <R0>
0x4005_0104 VECIDKI1 0x4005_0114 VEVDIH1 0x4005_0124 VEFPWMCHG1 0x4005_0134 Reserved
0x4005_0105 " 0x4005_0115 " 0x4005_0125 " 0x4005_0135 Reserved
0x4005_0106 <R0> 0x4005_0116 <R0> 0x4005_0126 <R0> 0x4005_0136 Reserved
0x4005_0108 VECIDKP1 0x4005_0118 VEVDILH1 0x4005_0128 VEVMDPRD1 0x4005_0138 VECOS1
0x4005_0109 " 0x4005_0119 " 0x4005_0129 " 0x4005_0139 "
0x4005_010A <R0> 0x4005_011A <R0> 0x4005_012A <R0> 0x4005_013A <R0>
0x4005_010B <R0> 0x4005_011B <R0> 0x4005_012B <R0> 0x4005_013B <R0>
0x4005_010C VECIQKI1 0x4005_011C VEVQIH1 0x4005_012C VEMINPLS1 0x4005_013C VESIN1
0x4005_010D “ 0x4005_011D “ 0x4005_012D “ 0x4005_013D “
0x4005_010E <R0> 0x4005_011E <R0> 0x4005_012E <R0> 0x4005_013E <R0>
0x4005_010F <R0> 0x4005_011F <R0> 0x4005_012F <R0> 0x4005_013F <R0>

name name name name
0x4005_0140 VECOSM1 0x4005_0150 VEIAO1 0x4005_0160 VEIBADC1 0x4005_0170 VEIQ1
0x4005_0141 " 0x4005_0151 " 0x4005_0161 " 0x4005_0171 "
0x4005_0142 <R0> 0x4005_0152 <R0> 0x4005_0162 <R0> 0x4005_0172 "
0x4005_0143 <R0> 0x4005_0153 <R0> 0x4005_0163 <R0> 0x4005_0173 "
0x4005_0144 VESINM1 0x4005_0154 VEIBO1 0x4005_0164 VEICADC1 0x4005_0174 Reserved
0x4005_0145 " 0x4005_0155 " 0x4005_0165 " 0x4005_0175 Reserved
0x4005_0148 VESECTOR1 0x4005_0158 VEICO1 0x4005_0168 VEVDC1 0x4005_0178 VEADC
0x4005_0149 <R0> 0x4005_0159 " 0x4005_0169 " 0x4005_0179 "
0x4005_014A <R0> 0x4005_015A <R0> 0x4005_016A <R0> 0x4005_017A <R0>
0x4005_014B <R0> 0x4005_015B <R0> 0x4005_016B <R0> 0x4005_017B <R0>
0x4005_014C VESECTORM1 0x4005_015C VEIAADC1 0x4005_016C VEID1 0x4005_017C VEVCMPU0
0x4005_014D <R0> 0x4005_015D “ 0x4005_016D “ 0x4005_017D “
0x4005_014E <R0> 0x4005_015E <R0> 0x4005_016E “ 0x4005_017E <R0>
0x4005_014F <R0> 0x4005_015F <R0> 0x4005_016F “ 0x4005_017F <R0>

TMPM370
[11] Vector engine (VE) [3/3]
name name name name
0x4005_0180 VEVCMPV0 0x4005_0190 VEVTRGCMP10 0x4005_01A0 VEVCMPV1 0x4005_01B0 VEVTRGCMP11
0x4005_0181 " 0x4005_0191 " 0x4005_01A1 " 0x4005_01B1 "
0x4005_0182 <R0> 0x4005_0192 <R0> 0x4005_01A2 <R0> 0x4005_01B2 <R0>
0x4005_0183 <R0> 0x4005_0193 <R0> 0x4005_01A3 <R0> 0x4005_01B3 <R0>
0x4005_0184 VEVCMPW0 0x4005_0194 VEVTRGSEL0 0x4005_01A4 VEVCMPW1 0x4005_01B4 VEVTRGSEL1
0x4005_0185 " 0x4005_0195 <R0> 0x4005_01A5 " 0x4005_01B5 <R0>
0x4005_0186 <R0> 0x4005_0196 <R0> 0x4005_01A6 <R0> 0x4005_01B6 <R0>
0x4005_0187 <R0> 0x4005_0197 <R0> 0x4005_01A7 <R0> 0x4005_01B7 <R0>
0x4005_0188 VEOUTCR0 0x4005_0198 VEEMGRS0 0x4005_01A8 VEOUTCR1 0x4005_01B8 VEEMGRS1
0x4005_0189 " 0x4005_0199 <R0> 0x4005_01A9 " 0x4005_01B9 <R0>
0x4005_018A <R0> 0x4005_019A <R0> 0x4005_01AA <R0> 0x4005_01BA <R0>
0x4005_018B <R0> 0x4005_019B <R0> 0x4005_01AB <R0> 0x4005_01BB <R0>
0x4005_018C VEVTRGCMP00 0x4005_019C VEVCMPU1 0x4005_01AC VEVTRGCMP01 0x4005_01BC Reserved
0x4005_018D “ 0x4005_019D “ 0x4005_01AD “ 0x4005_01BD Reserved
0x4005_018E <R0> 0x4005_019E <R0> 0x4005_01AE <R0> 0x4005_01BE Reserved
0x4005_018F <R0> 0x4005_019F <R0> 0x4005_01AF <R0> 0x4005_01BF Reserved

name name name name
0x4005_01C0 Reserved 0x4005_01D0 Reserved 0x4005_01E0 Reserved 0x4005_01F0 Reserved
0x4005_01CA Reserved 0x4005_01DA Reserved 0x4005_01EA Reserved 0x4005_01FA Reserved
0x4005_01CB Reserved 0x4005_01DB Reserved 0x4005_01EB Reserved 0x4005_01FB Reserved
0x4005_01CC Reserved 0x4005_01DC Reserved 0x4005_01EC Reserved 0x4005_01FC Reserved
0x4005_01CD Reserved 0x4005_01DD Reserved 0x4005_01ED Reserved 0x4005_01FD Reserved
0x4005_01CE Reserved 0x4005_01DE Reserved 0x4005_01EE Reserved 0x4005_01FE Reserved
0x4005_01CF Reserved 0x4005_01DF Reserved 0x4005_01EF Reserved 0x4005_01FF

TMPM370
22.1.12 [12] Programmable motor driver (PMD) [1/2]

name name name name
PMD0MDCNT PMD0EMGR
0x4005_0400 PMD0MDEN 0x4005_0410 0x4005_0420 PMD0CMPW 0x4005_0430
0 EL
0x4005_0401 <R0> 0x4005_0411 " 0x4005_0421 " 0x4005_0431 <R0>
0x4005_0402 <R0> 0x4005_0412 <R0> 0x4005_0422 <R0> 0x4005_0432 <R0>
0x4005_0403 <R0> 0x4005_0413 <R0> 0x4005_0423 <R0> 0x4005_0433 <R0>
PMD0MDPR PMD0MODESE PMD0EMGC
0x4005_0404 PMD0PORTMD 0x4005_0414 0x4005_0424 L
0x4005_0434
D R
0x4005_0405 <R0> 0x4005_0415 " 0x4005_0425 <R0> 0x4005_0435 "
0x4005_0406 <R0> 0x4005_0416 <R0> 0x4005_0426 <R0> 0x4005_0436 <R0>
0x4005_0407 <R0> 0x4005_0417 <R0> 0x4005_0427 <R0> 0x4005_0437 <R0>
PMD0MDOU PMD0EMGST
0x4005_0408 PMD0MDCR 0x4005_0418 PMD0CMPU 0x4005_0428 0x4005_0438
T A
0x4005_0409 <R0> 0x4005_0419 " 0x4005_0429 " 0x4005_0439 <R0>
0x4005_040A <R0> 0x4005_041A <R0> 0x4005_042A <R0> 0x4005_043A <R0>
0x4005_040B <R0> 0x4005_041B <R0> 0x4005_042B <R0> 0x4005_043B <R0>
PMD0CNTST
0x4005_040C 0x4005_041C PMD0CMPV 0x4005_042C PMDMDPOT 0x4005_043C PMDOVVCR
A
0x4005_040D <R0> 0x4005_041D " 0x4005_042D " 0x4005_043D "
0x4005_040E <R0> 0x4005_041E " 0x4005_042E <R0> 0x4005_043E <R0>
0x4005_040F <R0> 0x4005_041F " 0x4005_042F <R0> 0x4005_043F <R0>

name name name name
0x4005_0440 PMD0OVVSTA 0x4005_0450 PMD0TRGCMP2 0x4005_0460 PMD0TRGSEL 0x4005_0470 Reserved
0x4005_0441 <R0> 0x4005_0451 " 0x4005_0461 " 0x4005_0471 Reserved
0x4005_0442 <R0> 0x4005_0452 <R0> 0x4005_0462 " 0x4005_0472 Reserved
0x4005_0443 <R0> 0x4005_0453 <R0> 0x4005_0463 " 0x4005_0473 Reserved
0x4005_0444 PMD0DTR 0x4005_0454 PMD0TRGCMP3 0x4005_0464 Reserved 0x4005_0474 Reserved
0x4005_0445 <R0> 0x4005_0455 " 0x4005_0465 Reserved 0x4005_0475 Reserved
0x4005_0446 <R0> 0x4005_0456 <R0> 0x4005_0466 Reserved 0x4005_0476 Reserved
0x4005_0447 <R0> 0x4005_0457 <R0> 0x4005_0467 Reserved 0x4005_0477 Reserved
0x4005_0448 PMD0TRGCMP0 0x4005_0458 PMD0TRGCR 0x4005_0468 Reserved 0x4005_0478 Reserved
0x4005_0449 " 0x4005_0459 " 0x4005_0469 Reserved 0x4005_0479 Reserved
0x4005_044A <R0> 0x4005_045A <R0> 0x4005_046A Reserved 0x4005_047A Reserved
0x4005_044B <R0> 0x4005_045B <R0> 0x4005_046B Reserved 0x4005_047B Reserved
0x4005_044C PMD0TRGCMP1 0x4005_045C PMD0TRGMD 0x4005_046C Reserved 0x4005_047C Reserved
0x4005_044D " 0x4005_045D " 0x4005_046D Reserved 0x4005_047D Reserved
0x4005_044E <R0> 0x4005_045E " 0x4005_046E Reserved 0x4005_047E Reserved
0x4005_044F <R0> 0x4005_045F " 0x4005_046F Reserved 0x4005_047F Reserved

TMPM370
[12] Programmable motor driver (PMD) [2/2]

name name name name
0x4005_0480 PMD1MDEN 0x4005_0490 PMD1MDCNT 0x4005_04A0 PMD1CMPW 0x4005_04B0 PMD1EMGREL
0x4005_0481 <R0> 0x4005_0491 " 0x4005_04A1 " 0x4005_04B1 <R0>
0x4005_0482 <R0> 0x4005_0492 <R0> 0x4005_04A2 <R0> 0x4005_04B2 <R0>
0x4005_0483 <R0> 0x4005_0493 <R0> 0x4005_04A3 <R0> 0x4005_04B3 <R0>
PMD1MODESE PMD1EMGC
0x4005_0484 PMD1PORTMD 0x4005_0494 PMD1MDPRD 0x4005_04A4 L
0x4005_04B4
R
0x4005_0485 <R0> 0x4005_0495 " 0x4005_04A5 <R0> 0x4005_04B5 "
0x4005_0486 <R0> 0x4005_0496 <R0> 0x4005_04A6 <R0> 0x4005_04B6 <R0>
0x4005_0487 <R0> 0x4005_0497 <R0> 0x4005_04A7 <R0> 0x4005_04B7 <R0>
0x4005_0488 PMD1MDCR 0x4005_0498 PMD1CMPU 0x4005_04A8 PMD1MDOUT 0x4005_04B8 PMD1EMGSTA
0x4005_0489 <R0> 0x4005_0499 " 0x4005_04A9 " 0x4005_04B9 <R0>
0x4005_048A <R0> 0x4005_049A <R0> 0x4005_04AA <R0> 0x4005_04BA <R0>
0x4005_048B <R0> 0x4005_049B <R0> 0x4005_04AB <R0> 0x4005_04BB <R0>
0x4005_048C PMD1CNTSTA 0x4005_049C PMD1CMPV 0x4005_04AC PMD1MDPOT 0x4005_04BC PMD1OVVCR
0x4005_048D <R0> 0x4005_049D " 0x4005_04AD <R0> 0x4005_04BD "
0x4005_048E <R0> 0x4005_049E <R0> 0x4005_04AE <R0> 0x4005_04BE <R0>
0x4005_048F <R0> 0x4005_049F <R0> 0x4005_04AF <R0> 0x4005_04BF <R0>

name name name name
0x4005_04C0 PMD1OVVSTA 0x4005_04D0 PMD1TRGCMP2 0x4005_04E0 PMD1TRGSEL 0x4005_04F0 Reserved
0x4005_04C1 <R0> 0x4005_04D1 " 0x4005_04E1 " 0x4005_04F1 Reserved
0x4005_04C2 <R0> 0x4005_04D2 <R0> 0x4005_04E2 " 0x4005_04F2 Reserved
0x4005_04C3 <R0> 0x4005_04D3 <R0> 0x4005_04E3 " 0x4005_04F3 Reserved
0x4005_04C4 PMD1DTR 0x4005_04D4 PMD1TRGCMP3 0x4005_04E4 Reserved 0x4005_04F4 Reserved
0x4005_04C5 <R0> 0x4005_04D5 " 0x4005_04E5 Reserved 0x4005_04F5 Reserved
0x4005_04C6 <R0> 0x4005_04D6 <R0> 0x4005_04E6 Reserved 0x4005_04F6 Reserved
0x4005_04C7 <R0> 0x4005_04D7 <R0> 0x4005_04E7 Reserved 0x4005_04F7 Reserved
0x4005_04C8 PMD1TRGCMP0 0x4005_04D8 PMD1TRGCR 0x4005_04E8 Reserved 0x4005_04F8 Reserved
0x4005_04C9 " 0x4005_04D9 " 0x4005_04E9 Reserved 0x4005_04F9 Reserved
0x4005_04CA <R0> 0x4005_04DA <R0> 0x4005_04EA Reserved 0x4005_04FA Reserved
0x4005_04CB <R0> 0x4005_04DB <R0> 0x4005_04EB Reserved 0x4005_04FB Reserved
0x4005_04CC PMD1TRGCMP1 0x4005_04DC PMD1TRGMD 0x4005_04EC Reserved 0x4005_04FC Reserved
0x4005_04CD " 0x4005_04DD " 0x4005_04ED Reserved 0x4005_04FD Reserved
0x4005_04CE <R0> 0x4005_04DE " 0x4005_04EE Reserved 0x4005_04FE Reserved
0x4005_04CF <R0> 0x4005_04DF " 0x4005_04EF Reserved 0x4005_04FF Reserved

TMPM370
22.1.13 [13] Flash
name name name name
0x41FF_F000 Reserved 0x41FF_F010 FCSECBIT 0x41FF_F020 FCFLCS 0x41FF_F030 Reserved
0x41FF_F001 Reserved 0x41FF_F011 <R0> 0x41FF_F021 " 0x41FF_F031 Reserved
0x41FF_F004 Reserved 0x41FF_F014 Reserved 0x41FF_F024 Reserved 0x41FF_F034 Reserved
0x41FF_F00A Reserved 0x41FF_F01A Reserved 0x41FF_F02A Reserved 0x41FF_F03A Reserved
0x41FF_F00B Reserved 0x41FF_F01B Reserved 0x41FF_F02B Reserved 0x41FF_F03B Reserved
0x41FF_F00C Reserved 0x41FF_F01C Reserved 0x41FF_F02C Reserved 0x41FF_F03C Reserved
0x41FF_F00D Reserved 0x41FF_F01D Reserved 0x41FF_F02D Reserved 0x41FF_F03D Reserved
0x41FF_F00E Reserved 0x41FF_F01E Reserved 0x41FF_F02E Reserved 0x41FF_F03E Reserved
0x41FF_F00F Reserved 0x41FF_F01F Reserved 0x41FF_F02F Reserved 0x41FF_F03F Reserved
22.1.14 [14] Reserved area
name name name name
0x41FF_F04A Reserved 0x41FF_F05A Reserved 0x41FF_F06A Reserved 0x41FF_F07A Reserved
0x41FF_F04B Reserved 0x41FF_F05B Reserved 0x41FF_F06B Reserved 0x41FF_F07B Reserved
0x41FF_F04C Reserved 0x41FF_F05C Reserved 0x41FF_F06C Reserved 0x41FF_F07C Reserved
0x41FF_F04D Reserved 0x41FF_F05D Reserved 0x41FF_F06D Reserved 0x41FF_F07D Reserved
0x41FF_F04E Reserved 0x41FF_F05E Reserved 0x41FF_F06E Reserved 0x41FF_F07E Reserved
0x41FF_F04F Reserved 0x41FF_F05F Reserved 0x41FF_F06F Reserved 0x41FF_F07F Reserved
ADR Register name ADR Register ADR Register ADR Register

name name name
0x41FF_F080 Reserved 0x41FF_F090 Reserved 0x41FF_F0A0 Reserved 0x41FF_F0B0 Reserved
0x41FF_F08A Reserved 0x41FF_F09A Reserved 0x41FF_F0AA Reserved 0x41FF_F0BA Reserved
0x41FF_F08B Reserved 0x41FF_F09B Reserved 0x41FF_F0AB Reserved 0x41FF_F0BB Reserved
0x41FF_F08C Reserved 0x41FF_F09C Reserved 0x41FF_F0AC Reserved 0x41FF_F0BC Reserved
0x41FF_F08D Reserved 0x41FF_F09D Reserved 0x41FF_F0AD Reserved 0x41FF_F0BD Reserved
0x41FF_F08E Reserved 0x41FF_F09E Reserved 0x41FF_F0AE Reserved 0x41FF_F0BE Reserved
0x41FF_F08F Reserved 0x41FF_F09F Reserved 0x41FF_F0AF Reserved 0x41FF_F0BF Reserved

TMPM370
23. Port Section Equivalent Circuit Schematics

• How to read the schematics
Basically, the gate symbols written are the same as those used for the standard CMOS logic IC
[74HCXX] series.
The input protection resistance ranges from several tens of ohms to several hundreds of ohms.
Damping resistor and Feedback resistor are shown with a typical value.
• PA0-7 PC0-7, PD0-6, PE0-7, PF0-4, PG0-7
Output Data
P-ch
Output
Outputcontrol
Enable I/O
N-ch
Schmitt
Input Data
Input Enable Programmable

Pull-up Resistor
Pull-up Enable
Pull-down Enable
Programmable
Pull-down Resistor
• PH0-7, PI0-3, PJ0-7, PK0-1

Input AIN
Output Data
P-ch
Output
Outputcontrol
Enable I/O
N-ch
Schmitt
Input Data

Pull-up Resistor
Pull-up Enable
Pull-down Enable
Programmable
Pull-down Resistor
TMPM370 23-1 Equivalent Circuit

TMPM370
• PB0-3, PB5-7
Output Data
P-ch
Outputcontrol
Output Enable I/O
N-ch
Schmitt
Input Data

Pull-up Resistor
Pull-up Enable
• PB4
Output Data
P-ch
Output
Output control
Enable I/O
N-ch
Schmitt
Input Data
Input Enable
Programmable
Pull-down Resistor
Pull-down Enable
• PL0-1
Schmitt
I/O
Input
Input Data
Input Enable
• X1, X2
Clock
Oscillator Circuit
X2
1 KΩ
500 KΩ
High-frequency
Oscillation Enable
X1

TMPM370
• RESET
Pull-up Resistor
Schimitt
Reset Input
• MODE
Schimitt
Input MODE
Data Input
Note : MODE must be connected with GND.
• AVDD5A / VREFHA , AVSSA / VREFLA , AVDD5B / VREFHB , AVSSB / VREFLB

AVDD AVDD5/VREFH
ADC
VREFH
String
Resistor
VREFL
AVSS AVSS/VREFL
• CVREFABC, CVREFD
CVREF Input

TMPM370
24 Electrical Characteristics
24.1 Absolute Maximum Ratings
Parameter Symbol Rating Unit

DVDD5 − 0.3 to 6
DVDD5E − 0.3 to 6
Supply voltage RVDD5 − 0.3 to 6
AVDD5A/B − 0.3 to 6 V
AMPVDD5 − 0.3 to 6
VOUT15 − 0.3 to 3
Capacitor voltage
VOUT3 − 0.3 to 3.9
Input voltage VIN − 0.3 to VDD+0.3(Note1) V

Low-level Per pin IOL 5
output
current Total ΣIOL 50
mA
High-level Per pin IOH −5
output
current Total ΣIOH －50
Power consumption (Ta = 85°C) PD 600 mW
Soldering temperature (10s) TSOLDER 260 °C
Storage temperature TSTG − 55 to 125 °C
Operating Temperature TOPR − 40 to 85 °C
(Note) Absolute maximum ratings are limiting values of operating and environmental conditions
which should not be exceeded under the worst possible conditions. The equipment
manufacturer should design so that no Absolute maximum rating value is exceeded with
respect to current, voltage, power consumption, temperature, etc. Exposure to conditions
beyond those listed above may cause permanent damage to the device or affect device
reliability, which could increase potential risks of personal injury due to IC blowup and/or
burning.
(Note 1) VDD = DVDD5 = DVDD5E = AVDD5A = AVDD5B = RVDD5 = AMPVDD5
TMPM370 24-1 Electrical Characteristics

TMPM370
24.2 DC Electrical Characteristics (1/2)
DVSS = AVSSA/B = AMPVSS = 0V , Ta= −40 to 85°C

Typ.
Parameter Symbol Rating Min. Max. Unit
(Note 1)
DVDD5
DVDD5E
fosc = 8 to 10MHz
Supply voltage AVDD5A
fsys = 1 to 80MHz 4.5 − 5.5 V
(Note2) AVDD5B
RVDD5
AMPVDD5
DVDD5
DVDD5E
Supply voltage fosc = 8 to 10MHz
AVDD5A
(during Flash W/E) fsys = 1 to 80MHz 4.5 − 5.5 V
AVDD5B
(Note2) （Ta（°C）= 0 to 70）
RVDD5
AMPVDD5
input voltage
Low-level
Schmitt-Input VIL1 VDD = 4.5 to 5.5V −0.3 0.25 VDD
V
input voltage
Hight-level
Schmitt-Input VIH1 VDD = 4.5V to 5.5V 0.75 VDD VDD
Capacitance for VOUT15 and RVDD5 = 4.5V to 5.5V

Cout 3.3 4.7 μF
VOUT3 (Note 3) VOUT15,VOUT3
VOL IOL= 1.6mA VDD≧4.5V

Low-level output voltage − − 0.4 V
(Note4)
VOH IOH=−1.6mA VDD≧4.5V

High-level output voltage 4.1 − − V
(Note4)
Input leakage 0.0 ≦ VIN ≦ VDD (Note4)
ILI − 0.02 ±5
current
μA
0.2 ≦ VIN ≦ VDD − 0.2
Output leakage current ILO − 0.05 ± 10
(Note4)
Pull-up resister at Reset RRST 4.5V ≦ VDD ≦ 5.5V (Note4) − 50 150 kΩ
Schmitt-Triggered port VTH 4.5V ≦ VDD ≦ 5.5V (Note4) 0.3 0.6 - V
Programmable pull-up/
PKH 4.5V ≦ VDD ≦ 5.5V (Note4) − 50 150 kΩ
pull-down resistor
Pin capacitance
CIO fc = 1MHz − − 10 pF
(Except power supply pins)
(Note 1) Ta = 25°C, DVDD5 = DVDD5E = AVDD5A = AVDD5B = RVDD5 = AMVDD5 = 5V, unless
otherwise noted.
(Note 2) The same voltage must be supplied to DVDD5, DVDD5E, AVDD5A/B, RVDD5 and AMPVDD5.
(Note 3) VOUT15 and VOUT3 pin should be connected to GND via same value of capacitance. The IC
outside can not have the power supply from VOUT15 and VOUT3.
(Note4) VDD = DVDD5E = DVDD5 = AVDD5A = AVDD5B = AMPVDD5

TMPM370
24.3 DC Electrical Characteristics (2/2)

Ta= −40 to 85°C DVDD5 = DVDD5E = RVDD5 = AVDD5A/B = AMPVDD5 = 4.5V to 5.5V
Typ.
Parameter Symbol Rating Min. Max. Unit
(Note 1)
NORMAL (Note 2) Gear 1/1 70 80
fsys =80MHz (fosc = 10MHz) mA
IDLE (Note 2) Gear 1/1 ICC 21 30
STOP 7 11 mA
(Note 1) Ta = 25°C, DVDD5 = DVDD5E = AVDD5A/B = RVDD5 = AMPVDD5 = 5V, unless otherwise
noted.
(Note 2) ICC NORMAL, IDLE: All functions operates excluding A/D, Op amp and Comparator.
(Note 3) A/D reference voltage supply can not go into off state.
24.4 12-bit ADC Electrical Characteristics

DVDD5=RVDD5=AVDD5A/VREFHA=AVDD5B/VREFHB = 4.5V to 5.5V,
DVSS=AVSSA/VREFLA=AVSSB/VREFLB=0V, Ta = -40 to 85°C
Parameter Symbol Rating Min. Typ. Max. Unit
VREFHA
Analog reference voltage (+) − AVDD V
VREFHB
Analog input voltage VAIN − AVSS − AVDD V
Analog supply current
IREF DVSS = AVSS − 3.5 4.5 mA
(Note 1) (Note 2)
Supply current A/D
− Except IREF (Note2) − − 3 mA
(Note 1) conversion
INL error ±6
DNL error AIN resistance ≤600Ω ±5

AIN load
Offset error − ±5 LSB
capacitance ≦0.1μF
Full-scale error Conversion time ≧2μs ±5
Total error +5 to -10
(Note 1) Current for one unit of ADC.

(Note 2) A/D reference voltage supply can not go into off state.
(Note 3) 1LSB = (AVDD − AVSS) / 4096[V]
(Note 4) AVDD = AVDD5A = AVDD5B, AVSS = AVSSA = AVSSB
(Note 5) The characteristic is measured under the condition in which the only ADC is operating.

TMPM370
24.5 Op-Amps Electrical Characteristics

DVDD5 = RVDD5 = AVDD5A/VREFHA = AVDD5B/VREFHB = AMPVDD5 = 4.5V to 5.5V,
DVSS = AVSSA/VREFLA = AVSSB/VREFLB = AMPVSS = 0V, Ta = -40 to 85°C
Gain (Note 1) VGAIN ×1.5 − ×10
AVDD = 4.5 to 5.5V
AVSS = 0V (AVDD×0.1) (AVDD×0.9)
Input voltage range VAMPIN − V
VGAIN VGAIN
VGAIN ≧ 3.5
VOFF1 − 6×VGAIN ＋6×VGAIN
Offset voltage VGAIN ≦ 3 Ta < 70℃ − mV
VOFF2 Ta≧ 70℃ −20 +20
Gain error − ±1 ±3 %
AVDD = 4.5 to 5.5V
Slew rate (Note 2) Vthr AVSS = 0V 2 − − V/μs
5pF、VGAIN = ×2.5
(Note 1) Gain can be selected among ×2.5, ×3, ×3.5, ×4, ×6 and ×8 by register setting.
(Note 2) Slew rate means a slant til the output of amplifier reaches AVDD-0.001×AVDD.
(Note 3) AVDD = AVDD5A = AVDD5B = AMPVDD5, AVSS = AVSSA = AVSSB = AMPVSS
24.6 Comparator Electrical Characteristics

DVDD5 = RVDD5 = AVDD5A/VREFHA = AVDD5B/VREFHB = AMPVDD5 = 4.5V to 5.5V,
DVSS = AVSSA/VREFLA = AVSSB/VREFLB = 0V, Ta = -40 to 85°C
Offset voltage VOFF − ±4 − %
AIN input voltage range VIN AVDD = 4.5 to 5.5V AVSS − AVDD V
AVSS = 0V
Reference voltage range VREF 0.9 − AVDD−0.2 V
Response time (Note 1) (Note2) − − 1 μs
(Note 1) 1.0V≦VREF≦AVDD-0.2V
(Note 2) The case that VIN varies from VREF-100mv to VREF+100mv or from VREF+100mv to
VREF-100mv.
(Note 3) AVDD = AVDD5A = AVDD5B = AMPVDD5, AVSS = AVSSA = AVSSB = AMPVSS

TMPM370
24.7 AC Electrical Characteristics
AC measuremetn condition
Output levels: High 0.8VDD V/Low 0.2VDD, CL=30pF
Input levels: Refer to low-level input voltage and high-level input voltage in DC Electrical
Characteristics.
In the table below, the letter x represents the period of the system clock (fsys). It varies depending on
the programming of the clock gear function.
(Note 1) VDD = DVDD5E = DVDD5 = AVDD5A = AVDD5B = AMPVDD5
24.7.1 Serial Channel Timing (SIO)
(1) I/O Interface mode

SCLK input mode (VDD = 4.5V to 5.5V, Ta = −40 to 85°C)
Equation 80MHz
Parameter Symbol Unit
Min. Max. Min. Max.
SCLK Clock High width (input) tSCH 3x 37.5 ns
SCLK Clock Low width (input) tSCL 3x 37.5 ns
SCLK cycle tSCY tSCH + tSCL 75 ns
In case of OutputData to SCLK rise or fall (Note 1) tOSS tSCY/2 − 4x − 45 0 (Note 2) ns

transfer
OutputData hold or fall after SCLK
mode tOHS tSYC/2 37.5 ns
rising (Note 1)
Input Data valid SCLK rise or fall (Note
In case of tSRD 30 30 ns
1)
receive
InputData hold or fall after SCLK rising
mode tHSR x + 30 42.5 ns
(Note 1)
(Note 1) SCLK rise or fall:Measured relative to the programmed active edge of SCLK.
(Note 2) toss should be always positive. Therefore, set proper SCLK parameters (tSCY, tSCL and tSCY) to
keep toss positive. (toss > 0)
SCLK output mode (VDD = 4.5V to 5.5V, Ta = −40 to 85°C)

Equation 80MHz
Min. Max. Min. Max.
SCLK cycle (programmable) tSCY 4x 50 ns
In case of OutputData to SCLK rise tOSS tscy/2 − 20 5 ns

transfer
mode OutputData hold after SCLK rising tOHS tscy/2 − 20 5 ns
In case of InputData valid to SCLK rise tSRD 45 45 ns

receive
mode InputData hold after SCLK rising tHSR 0 0 ns

TMPM370
SCLK tSCY tSCH

Output Mode/ tSCL
Input High Mode
SCLK
Input Low Mode
tOSS tOHS
OUTPUT DATA 0 1 2 3
TxD
tSRD tHSR
INPUT DATA
0 1 2 3
RxD
VALID VALID VALID VALID
Fig 24-1 Ｓｅｒｉａｌ channel timing(SIO)
24.7.2 Event Counter
Ta = −40 to 85°C
Equation 80MHz
Min. Max. Min. Max.
Clock low pulse width tVCKL 2x + 100 125 ns
Clock high pulse width tVCKH 2x + 100 125 ns
24.7.3 Capture
Ta = −40 to 85°C
Equation 80MHz
Min. Max. Min. Max.
Low pulse width tCPL 2x + 100 125 ns
High pulse width tCPH 2x + 100 125 ns
24.7.4 General Interrupts

Ta = −40 to 85°C
Equation 80MHz
Min. Max. Min. Max.
Low pulse width for INT0 to F tINTAL x + 100 112.5 ns
High pulse width for INT0 to F tINTAH x + 100 112.5 ns

TMPM370
24.7.5 STOP Release Interrupts

Ta = −40 to 85°C
Equation 80MHz
Min. Max. Min. Max.
Low pulse width for INT0 to F tINTBL 100 100 ns
High pulse width for INT0 to F tINTBH 100 100 ns
24.7.6 Debug Communication
(1) SWD Interface
Parameter Symbol Min. Max. Unit
CLK cycle Tdck 100 - ns
DATA hold after CLK rising Td1 4 - ns
DATA valid after CLK rising Td2 - 37 ns

DATA valid to CLK rising Tds 20 - ns
DATA hold after CLK falling Tdh 15 - ns
(2) JTAG Interface
CLK cycle Tdck 100 - ns

DATA hold after CLK falling Td3 4 - ns
DATA valid after CLK falling Td4 - 37 ns
DATA valid to CLK rising Tds 20 - ns
DATA hold after CLK rising Tdh 15 - ns
Tdck
CLK input
(SWCLK)
(TCK) Td2
Td1
Output Data
(SWDIO)
Td4
Output Data Td3
(TDO)
Input Data
(SWDIO)
(TMS/TDI)
Tds Tdh
Fig 24-2 JTAG and SWD communication timing

TMPM370
24.7.7 TRACE Output
AC measuremetn condition
Output levels: High 0.7VDD V/Low 0.3VDD
Load capacitance: TRACECLK CL=25pF, TRACEDATA CL=20pF
TRACECLK cycle ttclk 25 - ns
DATA valid after CLK rising tsetupr 2 - ns
DATA hold after CLK rising tholdr 1 - ns
DATA valid after CLK falling tsetupf 2 - ns
DATA hold after CLK falling tholdf 1 - ns
t tclk
TRACE CLK
tsetupf tholdf t setupr t holdr
TRACEDATA 0 1 2 3
0 to 1
Fig 24-3 TRACE communication timing
24.8 Flash Characteristics
Ta = 0 to 70°C
Parameter Rating Min. Typ. Max. Unit
Flash memory erase/write times 100 times

TMPM370
24.9 Oscillation Circuit
The TMPM370 has been evaluated by the oscillator vender below. Use this information when
selecting external parts.
Note1: The load value of the oscillator is the sum of loads (C1 and C2) and the floating load of the
actual assembled board. There is a possibility of operating error when using C1 and C2
values in the table below. When designing the board, design the minimum length pattern
around the oscillator. We also recommend that oscillator evaluation be carried out using
the actual board.
Note2: Do not be driven X1/X2 by external driver.
(1) Connection example

X1 X2
Rd
C1 C2
Fig 24-4 High-frequency oscillation connection
(2) Recommended ceramic oscillator
The TMPM370 recommends the high-frequency oscillator by Murata Manufacturing Co., Ltd.
Please refer to the following URL for details.
http://www.murata.co.jp
24.10 Handling Precaution
Solderability
Test Test condition Note

parameter
Solderability Use of Sn-37Pb solder Bath Pass:
Solder bath temperature = 230°C, Dipping time = 5 seconds solderability rate until forming ≧ 95%
The number of times = one, Use of R-type flux
Use of Sn-3.0Ag-0.5Cu solder bath

Solder bath temperature = 245°C, Dipping time = 5 seconds
The number of times = one, Use of R-type flux

TMPM370
24.11 Note the power on

Note for usage of Port L(PL0,PL1) when power on.
When power on, until VDDs reach operation voltage and passed 200μs, port L(PL0,PL1) must be
OPEN or to supply “Low” level(less than 0.5V).
It is necessary to same measures that the power supply voltage dropped during operating, reset
signal is generated by power on reset circuit, and power supply line rising again.
(Note) VDDs : DVDD5, DVDD5E, RVDD5, AVDD5A/B, AMPVDD5 must be supplied same voltage.
24.11.1 Using Power On Reset only
Table 24.1．Warming-up time and Rising time of power line (POR only)
Symbol Rating Min Typ. Max Unit
tPWUP Warming-up time after reset released 215/fosc s
tDVDD Rising time of power line 3 ms
Voltage ｔＤＶＤＤ
4.5V
VDDs
PL0,PL1
VPORH
0.5V
Power on 200μs(min)
Detection Signal
Power on
Reset Signal
ｔＰＷＵＰ
Power On
Counter ・・
Internal Reset
Signal
(Note) VDDs are DVDD5, RVDD5, AVDD5A/B and AMPVDD5.
Fig 24.4 Power on Sequence(Using POR only)

TMPM370
24.11.2 Using External reset
(1) In case of the time of external reset shorter than POR
4.5V
VDDs
PL0,PL1
VPORH
0.5V
Detection Signal
Power on
Reset Signal
ｔＰＷＵＰ
Power on Counter ・・
--------------------------
RESET pin
Internal Reset
Signal Depend on ｔＰＷＵＰ
Fig 24.5 Power on Sequence(Using POR and External reset)(1)
(2) In case of the time of external reset longer than tPWUP
4.5V
VDDs
PL0,PL1
VPORH
0.5V
Detection Signal
Power on
Reset Signal
ｔＰＷＵＰ
Power on Counter
・・
--------------------------
RESET pin
Internal Reset
Signal Depend on the time of exterenal reset
Fig 24.6 Power on Sequence(Using POR and External reset)(2)

TMPM370
(3) In case of the rising time of power line longer than tPWUP
------------------------------
(Note) In this case, must be reset from RESET pin.
4.5V
VDDs PL0,PL1
VPORH
0.5V
Detection Signal
Power on
Reset Signal
VDDs must reach operating voltage and after
200μs, external reset can released.
Power on Counter ・・
--------------------------
RESET pin
Internal Reset
Signal
Fig 24.7 Power on Sequence (tDVDD > tPWUP)

TMPM370
25. Package
Type：LQFP100-P-1414-0.50H
Dimensions
Unit : mm
TMPM370 25-1 Package

TMPM370
Pin detail
(Note 1) For more dimensional information, please contact any one of our representatives
(Note 2) The package is palladized

TMPM370
Type：QFP100-P-1420-0.65Q
Dimensions
Unit : mm
Pin detail

TMPM370
Pin detail
(Note1) For more dimensional information, please contact any one of our representatives
(Note2) The package is palladized

TMPM370
RESTRICTIONS ON PRODUCT USE

• Toshiba Corporation, and its subsidiaries and affiliates (collectively “TOSHIBA”), reserve the right to make changes to the information
in this document, and related hardware, software and systems (collectively “Product”) without notice.
• This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with
TOSHIBA’s written permission, reproduction is permissible only if reproduction is without alteration/omission.
• Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are
responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the Product,
or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all
relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for
Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for
the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their own product
design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such design or
applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams,
programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for
such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR APPLICATIONS.
• Product is intended for use in general electronics applications (e.g., computers, personal equipment, office equipment, measuring
equipment, industrial robots and home electronics appliances) or for specific applications as expressly stated in this document.
Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or
reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public
impact (“Unintended Use”). Unintended Use includes, without limitation, equipment used in nuclear facilities, equipment used in the
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equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric
power, and equipment used in finance-related fields. Do not use Product for Unintended Use unless specifically permitted in this
document.
• Do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy Product, whether in whole or in part.
• Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any
applicable laws or regulations.
• The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any
infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to
any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise.
• ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE
FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY
WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR
LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND
LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO
SALE, USE OF PRODUCT, OR INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT.
• Do not use or otherwise make available Product or related software or technology for any military purposes, including without limitation,
for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology
products (mass destruction weapons). Product and related software and technology may be controlled under the Japanese Foreign
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or technology are strictly prohibited except in compliance with all applicable export laws and regulations.
• Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product.
Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances,
including without limitation, the EU RoHS Directive. TOSHIBA assumes no liability for damages or losses occurring as a result of
noncompliance with applicable laws and regulations.
TMPM370

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32-bit RISC Microcontroller

32-bit RISC microcontroller TX03 series

Product No. On chip Flash ROM On chip RAM Package

( 1 ) ARM Cortex-M3 microcontroller core

 Low power consumption

3) High-speed interrupt response suitable for real-time control

( 3 ) Input/ output ports

( 4 ) Watchdog timer (WDT): 1 channel

( 5 ) Power_On reset function(POR)

( 6 ) Voltage detect function(VLTD)

( 7 ) Oscillation frequency detect function(OFD)

TMPM370 1-2 Overview and Features

( 8 ) Vector engine(VE): 1 unit

( 9 ) Programmable motor driver(PMD): 2channel

( 10 ) Encoder input circuit(ENC): 2 channel

( 11 ) 16-bit timer(TMRB): 8 channel

( 12 ) General-purpose serial interface(SIO): 4 channel

( 13 ) 12-bit A/D converter (ADC): 2unit( 22 channel for analog input)

( 15 ) comparator(CMP): 3+1 channel

( 19 ) Maximum operating frequency

( 20 ) Operating voltage range

TMPM370 1-3 Overview and Features

1.2 Block Diagram

PMD OFD On_chip oscillator

ADC SIO (4ch)

ADC TMRB (8ch)

AMP/CMP (4ch) PORT A - L

Fig1.1 TMPM370FYDFG/ FYFG block diagram

TMPM370 1-4 Overview and Features

2. Pin Layout and Pin Functions

2.1 Pin Layout (Top view)

Fig 2-1 Pin layout (TMPM370FYFG)

TMPM370 2-1 Pin layout and pin function

Fig 2-2 Pin layout (TMPM370FYDFG)

TMPM370 2-2 Pin layout and pin function

2.2 Pin function

TMPM370 2-3 Pin layout and pin function

Table 2.1 Pin functions (2/5)

TMPM370 2-4 Pin layout and pin function

Table 2.1 Pin functions (3/5)

TMPM370 2-5 Pin layout and pin function

Table 2.1 Pin functions (4/5)

TMPM370 2-6 Pin layout and pin function

Table 2.1 Pin function (5/5)

Table 2.2 Operating voltage of each Pin

X1,X2 Internal 1.5V/CVSS Do not be driven by external circuit.

Compare(reference) voltage input for

Table 2.3 voltage range of each pin

DVDD5 For I/O ports

RVDD5 For internal circuit

AVDD5A,AVDD5B 4.5 to 5.5V For ADCs

AMPVDD5 For operational amp and comparator

DVDD5E DVDD5E must be connect with DVDD5

TMPM370 2-7 Pin layout and pin function

3.1 Processor Core

Product Name Core Revision

3.2 Optional block

Optional block Implementation

TMPM370FY is not support SLEEPDEEP. Do not set SLEEPDEEP bit.

Low power consumption