Big Buddha DBG Arch SCH
Big Buddha DBG Arch SCH
Big Buddha DBG Arch SCH
WS-3548-XL
11/11/99
Presenter - Fred Schindler
• Ethernet Switch
48 Ports, 10Mbit/100Mbit
2 GBIC Ports, 1000Mb
• 8 Layer PCB
vs 6
• Rpacks
vs single Resistors
CPU
BUFFER Data RCVR
BUFFERS
RAM
DRAM
Buffer
FWD
RAM
Santa 2 CHANNELS
I/O Buffer
Cruz Avalon
Frank 1 GBIC
64
LED
RCVR
AVR NOTIFY
1 pair = channel RAM
FLASH RAM 14 channels
Ports 41-48
Ports 1-8
Big Buddha
Cisco Systems Confidential FRS B2
7
Current Testing Methods
• Engineering
boot -post (Internal loop-back)
Perf 5 (Internal & External loop-back)
Debug Monitor Diagnostics
EMI 100 - Internal & external loop-back
• Manufacturing
Boot -post
Perf 5
BST (SmartBits)
• U72 = Processor
• U76, U77 = EDO DRAM
• U68 = Flash Memory
• U106 = I/O Buffer
• U105, U39 = System LED Buffers
• U85 = RS232 Driver
• U75 = Muscle ASIC
• U69, U70, U73, U74 = Santa Cruz PCI
Buffers
• U4-U9 = PHY
• T1-T12 = Quad Transformers
• J1-2 = 8 over 8 -16 Gang RJ45
Connectors
• U51 = 67MHz Oscillator
• U41, U38 = 50 MHz clock buffer
Wait until all port LEDs are either GREEN (even port)
or AMBER (odd port).
• External SSRAM
Forwarding RAM - contains Address Table,
Notification Tables, and Distribution FIFO
Receiving RAM - Receive FIFOs