Blackfin Embedded Processor ADSP-BF534/ADSP-BF536/ADSP-BF537

Blackfin
Embedded Processor
ADSP-BF534/ADSP-BF536/ADSP-BF537
FEATURES PERIPHERALS
Up to 600 MHz high performance Blackfin processor IEEE 802.3-compliant 10/100 Ethernet MAC (ADSP-BF536 and
Three 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, ADSP-BF537 only)
40-bit shifter Controller area network (CAN) 2.0B interface
RISC-like register and instruction model for ease of Parallel peripheral interface (PPI), supporting ITU-R 656
programming and compiler-friendly support video data formats
Advanced debug, trace, and performance monitoring 2 dual-channel, full-duplex synchronous serial ports
Wide range of operating voltages. See Operating Conditions (SPORTs), supporting 8 stereo I2S channels
on Page 23 12 peripheral DMAs, 2 mastered by the Ethernet MAC
Programmable on-chip voltage regulator 2 memory-to-memory DMAs with external request lines
182-ball and 208-ball CSP_BGA packages Event handler with 32 interrupt inputs
MEMORY Serial peripheral interface (SPI) compatible
2 UARTs with IrDA support
Up to 132K bytes of on-chip memory
2-wire interface (TWI) controller
Instruction SRAM/cache and instruction SRAM
Eight 32-bit timer/counters with PWM support
Data SRAM/cache plus additional dedicated data SRAM
Real-time clock (RTC) and watchdog timer
Scratchpad SRAM (see Table 1 on Page 3 for available
32-bit core timer
memory configurations)
48 general-purpose I/Os (GPIOs), 8 with high current drivers
External memory controller with glueless support for SDRAM
On-chip PLL capable of 0.5ⴛ to 64ⴛ frequency multiplication
and asynchronous 8-bit and 16-bit memories
Debug/JTAG interface
Flexible booting options from external flash, SPI and TWI
memory or from SPI, TWI, and UART host devices
Memory management unit providing memory protection
VOLTAGE REGULATOR JTAG TEST AND EMULATION
PERIPHERAL ACCESS BUS

WATCHDOG TIMER
RTC
B INTERRUPT
CONTROLLER CAN
TWI PORT J
SPORT0
L1 L1
DMA
INSTRUCTION DATA SPORT1
CONTROLLER
MEMORY MEMORY GPIO
PPI PORT G
EXTERNAL
DMA
BUS
DMA CORE BUS UART0-1

EXTERNAL ACCESS BUS GPIO
SPI
PORT F
EXTERNAL PORT
FLASH, SDRAM CONTROL TIMER7-0
ETHERNET MAC GPIO

16 (See Table 1) PORT H
BOOT ROM
Figure 1. Functional Block Diagram
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Rev. G
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TABLE OF CONTENTS
Features ................................................................. 1 Voltage Regulation .............................................. 14
Memory ................................................................ 1 Clock Signals ...................................................... 15
Peripherals ............................................................. 1 Booting Modes ................................................... 16
Table Of Contents .................................................... 2 Instruction Set Description .................................... 17
Revision History ...................................................... 2 Development Tools .............................................. 17
General Description ................................................. 3 Designing an Emulator-Compatible Processor Board ... 18
Portable Low Power Architecture ............................. 3 Related Documents .............................................. 18
System Integration ................................................ 3 Pin Descriptions .................................................... 19
Blackfin Processor Peripherals ................................. 3 Specifications ........................................................ 23
Blackfin Processor Core .......................................... 4 Operating Conditions ........................................... 23
Memory Architecture ............................................ 5 Electrical Characteristics ....................................... 25
DMA Controllers .................................................. 8 Absolute Maximum Ratings ................................... 29
Real-Time Clock ................................................... 9 ESD Sensitivity ................................................... 29
Watchdog Timer .................................................. 9 Package Information ............................................ 29
Timers ............................................................... 9 Timing Specifications ........................................... 30
Serial Ports (SPORTs) .......................................... 10 Output Drive Currents ......................................... 52
Serial Peripheral Interface (SPI) Port ....................... 10 Test Conditions .................................................. 54
UART Ports ...................................................... 10 Thermal Characteristics ........................................ 57
Controller Area Network (CAN) ............................ 11 182-Ball CSP_BGA Ball Assignment ........................... 58
TWI Controller Interface ...................................... 11 208-Ball CSP_BGA Ball Assignment ........................... 61
10/100 Ethernet MAC .......................................... 11 Outline Dimensions ................................................ 64
Ports ................................................................ 12 Surface-Mount Design .......................................... 65
Parallel Peripheral Interface (PPI) ........................... 12 Automotive Products .............................................. 66
Dynamic Power Management ................................ 13 Ordering Guide ..................................................... 66
REVISION HISTORY
2/09—Rev. E to Rev. G Revised SPI master timing specifications and diagram.
The revision F data sheet was never released publicly. The fol- See Serial Peripheral Interface Port—Master Timing ....... 42
lowing revisions include those from both revision E to F and Revised SPI slave timing specifications and diagram.
from revision F to G. See Serial Peripheral Interface Port—Slave Timing ......... 43
Revised the IDDSLEEP, IDDDEEPSLEEP, and IDDINT specifications. See Revised timer cycle timing specifications tTIS and tTOD. See Timer
Electrical Characteristics .......................................... 25 Cycle Timing ......................................................... 46
Removed the Power Dissipation section. See Estimating Power Revised Figure 61 and Figure 62 (added NC pin). ............59
for the ADSP-BF534/BF536/BF537 Blackfin Processors (EE-297)
and Table 16 and Table 15 ........................................ 27
Added tNOBOOT specification to Clock and Reset Timing ... 30
Removed DATA15–0 from footnote 1 in Asynchronous Mem-
ory Write Cycle Timing ........................................... 32
Revised SDRAM tENSDAT specification. See SDRAM Interface
Timing ................................................................ 34
Revised serial ports internal clock timing specifications tSFSI
and tSDRI. See Serial Ports ......................................... 39
Rev. G | Page 2 of 68 | February 2009

GENERAL DESCRIPTION
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors are PORTABLE LOW POWER ARCHITECTURE
members of the Blackfin® family of products, incorporating the
Blackfin processors provide world-class power management
Analog Devices, Inc./Intel Micro Signal Architecture (MSA).
and performance. They are produced with a low power and low
Blackfin processors combine a dual-MAC, state-of-the-art sig-
voltage design methodology and feature on-chip dynamic
nal processing engine, the advantages of a clean, orthogonal
power management, which is the ability to vary both the voltage
RISC-like microprocessor instruction set, and single-instruc-
and frequency of operation to significantly lower overall power
tion, multiple-data (SIMD) multimedia capabilities into a single
consumption. This capability can result in a substantial reduc-
instruction-set architecture.
tion in power consumption, compared with just varying the
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors are frequency of operation. This allows longer battery life for
completely code and pin compatible. They differ only with portable appliances.
respect to their performance, on-chip memory, and presence of
the Ethernet MAC module. Specific performance, memory, and SYSTEM INTEGRATION
feature configurations are shown in Table 1. The Blackfin processor is a highly integrated system-on-a-chip
solution for the next generation of embedded network-con-
Table 1. Processor Comparison nected applications. By combining industry-standard interfaces
with a high performance signal processing core, cost-effective
ADSP-BF534
ADSP-BF536
ADSP-BF537
applications can be developed quickly, without the need for

costly external components. The system peripherals include an
IEEE-compliant 802.3 10/100 Ethernet MAC (ADSP-BF536 and
Features ADSP-BF537 only), a CAN 2.0B controller, a TWI controller,
Ethernet MAC — 1 1 two UART ports, an SPI port, two serial ports (SPORTs), nine
general-purpose 32-bit timers (eight with PWM capability), a
CAN 1 1 1
real-time clock, a watchdog timer, and a parallel peripheral
TWI 1 1 1 interface (PPI).
SPORTs 2 2 2
UARTs 2 2 2 BLACKFIN PROCESSOR PERIPHERALS
SPI 1 1 1 The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors con-
GP Timers 8 8 8 tain a rich set of peripherals connected to the core via several
high bandwidth buses, providing flexibility in system configura-
Watchdog Timers 1 1 1
tion as well as excellent overall system performance (see
RTC 1 1 1 Figure 1). The processors contain dedicated network communi-
Parallel Peripheral Interface 1 1 1 cation modules and high speed serial and parallel ports, an
GPIOs 48 48 48 interrupt controller for flexible management of interrupts from
L1 Instruction 16K bytes 16K bytes 16K bytes the on-chip peripherals or external sources, and power manage-
SRAM/Cache ment control functions to tailor the performance and power
characteristics of the processor and system to many application
L1 Instruction 48K bytes 48K bytes 48K bytes
scenarios.
SRAM
Memory L1 Data 32K bytes 32K bytes 32K bytes All of the peripherals, except for the general-purpose I/O, CAN,
Configuration SRAM/Cache TWI, real-time clock, and timers, are supported by a flexible
DMA structure. There are also separate memory DMA channels
L1 Data SRAM 32K bytes — 32K bytes
dedicated to data transfers between the processor’s various
L1 Scratchpad 4K bytes 4K bytes 4K bytes memory spaces, including external SDRAM and asynchronous
L3 Boot ROM 2K bytes 2K bytes 2K bytes memory. Multiple on-chip buses running at up to 133 MHz
Maximum Speed Grade 500 MHz 400 MHz 600 MHz provide enough bandwidth to keep the processor core running
Package Options: along with activity on all of the on-chip and external
CSP_BGA 208-Ball 208-Ball 208-Ball peripherals.
CSP_BGA 182-Ball 182-Ball 182-Ball The Blackfin processors include an on-chip voltage regulator in
support of the processors’ dynamic power management capabil-
By integrating a rich set of industry-leading system peripherals ity. The voltage regulator provides a range of core voltage levels
and memory, the Blackfin processors are the platform of choice when supplied from VDDEXT. The voltage regulator can be
for next-generation applications that require RISC-like pro- bypassed at the user’s discretion.
grammability, multimedia support, and leading-edge signal
processing in one integrated package.

BLACKFIN PROCESSOR CORE instructions include byte alignment and packing operations,
16-bit and 8-bit adds with clipping, 8-bit average operations,
As shown in Figure 2, the Blackfin processor core contains two
and 8-bit subtract/absolute value/accumulate (SAA) operations.
16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,
Also provided are the compare/select and vector search
four video ALUs, and a 40-bit shifter. The computation units
instructions.
process 8-, 16-, or 32-bit data from the register file.
For certain instructions, two 16-bit ALU operations can be per-
The compute register file contains eight 32-bit registers. When
formed simultaneously on register pairs (a 16-bit high half and
performing compute operations on 16-bit operand data, the
16-bit low half of a compute register). If the second ALU is used,
register file operates as 16 independent 16-bit registers. All
quad 16-bit operations are possible.
operands for compute operations come from the multiported
register file and instruction constant fields. The 40-bit shifter can perform shifts and rotates, and is used to
support normalization, field extract, and field deposit
Each MAC can perform a 16-bit by 16-bit multiply in each
instructions.
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation The program sequencer controls the flow of instruction execu-
are supported. tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
The ALUs perform a traditional set of arithmetic and logical
indirect conditional jumps (with static branch prediction), and
operations on 16-bit or 32-bit data. In addition, many special
subroutine calls. Hardware is provided to support zero-over-
instructions are included to accelerate various signal processing
head looping. The architecture is fully interlocked, meaning that
tasks. These include bit operations such as field extract and pop-
the programmer need not manage the pipeline when executing
ulation count, modulo 232 multiply, divide primitives, saturation
instructions with data dependencies.
and rounding, and sign/exponent detection. The set of video
ADDRESS ARITHMETIC UNIT
SP
I3 L3 B3 M3 FP
I2 L2 B2 M2 P5
I1 L1 B1 M1 DAG1 P4
I0 L0 B0 M0 P3
DAG0
P2
DA1 32
P1
DA0 32
P0
TO MEMORY
32 32
RAB PREG
SD 32
LD1 32 32 ASTAT
LD0 32
32
SEQUENCER
R7.H R7.L
R6.H R6.L
R5.H R5.L ALIGN
16 16
R4.H R4.L
8 8 8 8
R3.H R3.L
R2.H R2.L DECODE
R1.H R1.L BARREL
R0.H R0.L SHIFTER 40 40 LOOP BUFFER
40 40
A0 A1 CONTROL
UNIT
32
32
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core

The address arithmetic unit provides two addresses for simulta- The memory DMA controller provides high bandwidth data-
neous dual fetches from memory. It contains a multiported movement capability. It can perform block transfers of code or
register file consisting of four sets of 32-bit index, modify, data between the internal memory and the external
length, and base registers (for circular buffering), and eight memory spaces.
additional 32-bit pointer registers (for C-style indexed stack
manipulation). Internal (On-Chip) Memory
Blackfin processors support a modified Harvard architecture in The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors have
combination with a hierarchical memory structure. Level 1 (L1) three blocks of on-chip memory providing high-bandwidth
memories are those that typically operate at the full processor access to the core.
speed with little or no latency. At the L1 level, the instruction The first block is the L1 instruction memory, consisting of
memory holds instructions only. The two data memories hold 64K bytes SRAM, of which 16K bytes can be configured as a
data, and a dedicated scratchpad data memory stores stack and four-way set-associative cache. This memory is accessed at full
local variable information. processor speed.
In addition, multiple L1 memory blocks are provided, offering a The second on-chip memory block is the L1 data memory, con-
configurable mix of SRAM and cache. The memory manage- sisting of up to two banks of up to 32K bytes each. Each memory
ment unit (MMU) provides memory protection for individual bank is configurable, offering both cache and SRAM functional-
tasks that may be operating on the core and can protect system ity. This memory block is accessed at full processor speed.
registers from unintended access.
The third memory block is a 4K byte scratchpad SRAM, which
The architecture provides three modes of operation: user mode, runs at the same speed as the L1 memories, but is only accessible
supervisor mode, and emulation mode. User mode has as data SRAM, and cannot be configured as cache memory.
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has External (Off-Chip) Memory
unrestricted access to the system and core resources. External memory is accessed via the EBIU. This 16-bit interface
The Blackfin processor instruction set has been optimized so provides a glueless connection to a bank of synchronous DRAM
that 16-bit opcodes represent the most frequently used instruc- (SDRAM) as well as up to four banks of asynchronous memory
tions, resulting in excellent compiled code density. Complex devices including flash, EPROM, ROM, SRAM, and memory
DSP instructions are encoded into 32-bit opcodes, representing mapped I/O devices.
fully featured multifunction instructions. Blackfin processors The PC133-compliant SDRAM controller can be programmed
support a limited multi-issue capability, where a 32-bit instruc- to interface to up to 512M bytes of SDRAM. A separate row can
tion can be issued in parallel with two 16-bit instructions, be open for each SDRAM internal bank, and the SDRAM con-
allowing the programmer to use many of the core resources in a troller supports up to 4 internal SDRAM banks, improving
single instruction cycle. overall performance.
The Blackfin processor assembly language uses an algebraic syn- The asynchronous memory controller can be programmed to
tax for ease of coding and readability. The architecture has been control up to four banks of devices with very flexible timing
optimized for use in conjunction with the C/C++ compiler, parameters for a wide variety of devices. Each bank occupies a
resulting in fast and efficient software implementations. 1M byte segment regardless of the size of the devices used, so
that these banks are only contiguous if each is fully populated
MEMORY ARCHITECTURE with 1M byte of memory.
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors view
memory as a single unified 4G byte address space, using 32-bit I/O Memory Space
addresses. All resources, including internal memory, external The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors do
memory, and I/O control registers, occupy separate sections of not define a separate I/O space. All resources are mapped
this common address space. The memory portions of this through the flat 32-bit address space. On-chip I/O devices have
address space are arranged in a hierarchical structure to provide their control registers mapped into memory-mapped registers
a good cost/performance balance of some very fast, low latency (MMRs) at addresses near the top of the 4G byte address space.
on-chip memory as cache or SRAM, and larger, lower cost, and These are separated into two smaller blocks, one which contains
performance off-chip memory systems. (See Figure 3). the control MMRs for all core functions, and the other which
The on-chip L1 memory system is the highest performance contains the registers needed for setup and control of the on-
memory available to the Blackfin processor. The off-chip mem- chip peripherals outside of the core. The MMRs are accessible
ory system, accessed through the external bus interface unit only in supervisor mode and appear as reserved space to on-
(EBIU), provides expansion with SDRAM, flash memory, and chip peripherals.
SRAM, optionally accessing up to 516M bytes of
physical memory.

ADSP-BF534/ADSP-BF537 MEMORY MAP ADSP-BF536 MEMORY MAP
0xFFFF FFFF 0xFFFF FFFF

CORE MMR REGISTERS (2M BYTES) CORE MMR REGISTERS (2M BYTES)
0xFFE0 0000 0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTES) SYSTEM MMR REGISTERS (2M BYTES)
0xFFC0 0000 0xFFC0 0000
RESERVED RESERVED
0xFFB0 1000 0xFFB0 1000
SCRATCHPAD SRAM (4K BYTES) SCRATCHPAD SRAM (4K BYTES)
INTERNAL MEMORY MAP

0xFFB0 0000 0xFFB0 0000
RESERVED RESERVED
0xFFA1 4000
INTERNAL MEMORY MAP

0xFFA1 4000
INSTRUCTION SRAM/CACHE (16K BYTES) INSTRUCTION SRAM/CACHE (16K BYTES)
0xFFA1 0000 0xFFA1 0000
RESERVED RESERVED
0xFFA0 C000 0xFFA0 C000
INSTRUCTION BANK B SRAM (16K BYTES) INSTRUCTION BANK B SRAM (16K BYTES)
0xFFA0 8000 0xFFA0 8000
INSTRUCTION BANK A SRAM (32K BYTES) INSTRUCTION BANK A SRAM (32K BYTES)
0xFFA0 0000 0xFFA0 0000
RESERVED RESERVED
0xFF90 8000 0xFF90 8000
DATA BANK B SRAM/CACHE (16K BYTES) DATA BANK B SRAM/CACHE (16K BYTES)
0xFF90 4000 0xFF90 4000
DATA BANK B SRAM (16K BYTES) RESERVED
0xFF90 0000 0xFF90 0000
RESERVED RESERVED
0xFF80 8000 0xFF80 8000
DATA BANK A SRAM/CACHE (16K BYTES) DATA BANK A SRAM/CACHE (16K BYTES)
0xFF80 4000 0xFF80 4000
DATA BANK A SRAM (16K BYTES) RESERVED
0xFF80 0000 0xFF80 0000
RESERVED
RESERVED
0xEF00 0800 0xEF00 0800
EXTERNAL MEMORY MAP

BOOT ROM (2K BYTES)
EXTERNAL MEMORY MAP
BOOT ROM (2K BYTES)

0xEF00 0000 0xEF00 0000
RESERVED
RESERVED
0x2040 0000
0x2040 0000
ASYNC MEMORY BANK 3 (1M BYTES)
0x2030 0000 0x2030 0000
0x2020 0000
0x2020 0000
0x2010 0000 0x2010 0000
0x2000 0000
0x2000 0000
SDRAM MEMORY (16M BYTES TO 512M BYTES) SDRAM MEMORY (16M BYTES TO 512M BYTES)
0x0000 0000 0x0000 0000
Figure 3. ADSP-BF534/ADSP-BF536/ADSP-BF537 Memory Maps
Booting • Nonmaskable Interrupt (NMI) – The NMI event can be

generated by the software watchdog timer or by the NMI
The Blackfin processor contains a small on-chip boot kernel,
input signal to the processor. The NMI event is frequently
which configures the appropriate peripheral for booting. If the
used as a power-down indicator to initiate an orderly shut-
Blackfin processor is configured to boot from boot ROM mem-
down of the system.
ory space, the processor starts executing from the on-chip boot
ROM. For more information, see Booting Modes on Page 16. • Exceptions – Events that occur synchronously to program
flow (in other words, the exception is taken before the
Event Handling instruction is allowed to complete). Conditions such as
The event controller on the Blackfin processor handles all asyn- data alignment violations and undefined instructions cause
chronous and synchronous events to the processor. The exceptions.
Blackfin processor provides event handling that supports both • Interrupts – Events that occur asynchronously to program
nesting and prioritization. Nesting allows multiple event service flow. They are caused by input pins, timers, and other
routines to be active simultaneously. Prioritization ensures that peripherals, as well as by an explicit software instruction.
servicing of a higher priority event takes precedence over servic-
Each event type has an associated register to hold the return
ing of a lower priority event. The controller provides support for
address and an associated return-from-event instruction. When
five different types of events:
an event is triggered, the state of the processor is saved on the
• Emulation – An emulation event causes the processor to supervisor stack.
enter emulation mode, allowing command and control of
The Blackfin processor event controller consists of two stages:
the processor via the JTAG interface.
the core event controller (CEC) and the system interrupt con-
• Reset – This event resets the processor. troller (SIC). The core event controller works with the system
interrupt controller to prioritize and control all system events.

Conceptually, interrupts from the peripherals enter into the Table 3. System Interrupt Controller (SIC)
SIC, and are then routed directly into the general-purpose inter-
rupts of the CEC. Default Peripheral
Peripheral Interrupt Event Mapping Interrupt ID
Core Event Controller (CEC) PLL Wakeup IVG7 0
The CEC supports nine general-purpose interrupts (IVG15–7), DMA Error (Generic) IVG7 1
in addition to the dedicated interrupt and exception events. Of DMAR0 Block Interrupt IVG7 1
these general-purpose interrupts, the two lowest priority
DMAR1 Block Interrupt IVG7 1
interrupts (IVG15–14) are recommended to be reserved for
software interrupt handlers, leaving seven prioritized interrupt DMAR0 Overflow Error IVG7 1
inputs to support the peripherals of the Blackfin processor. DMAR1 Overflow Error IVG7 1
Table 2 describes the inputs to the CEC, identifies their names CAN Error IVG7 2
in the event vector table (EVT), and lists their priorities. Ethernet Error (ADSP-BF536 and IVG7 2
ADSP-BF537 only)
Table 2. Core Event Controller (CEC)
SPORT 0 Error IVG7 2
Priority SPORT 1 Error IVG7 2
(0 Is Highest) Event Class EVT Entry PPI Error IVG7 2
0 Emulation/Test Control EMU SPI Error IVG7 2
1 Reset RST UART0 Error IVG7 2
2 Nonmaskable Interrupt NMI UART1 Error IVG7 2
3 Exception EVX Real-Time Clock IVG8 3
4 Reserved — DMA Channel 0 (PPI) IVG8 4
5 Hardware Error IVHW DMA Channel 3 (SPORT 0 Rx) IVG9 5
6 Core Timer IVTMR DMA Channel 4 (SPORT 0 Tx) IVG9 6
7 General-Purpose Interrupt 7 IVG7 DMA Channel 5 (SPORT 1 Rx) IVG9 7
8 General-Purpose Interrupt 8 IVG8 DMA Channel 6 (SPORT 1 Tx) IVG9 8
9 General-Purpose Interrupt 9 IVG9 TWI IVG10 9
10 General-Purpose Interrupt 10 IVG10 DMA Channel 7 (SPI) IVG10 10
11 General-Purpose Interrupt 11 IVG11 DMA Channel 8 (UART0 Rx) IVG10 11
12 General-Purpose Interrupt 12 IVG12 DMA Channel 9 (UART0 Tx) IVG10 12
13 General-Purpose Interrupt 13 IVG13 DMA Channel 10 (UART1 Rx) IVG10 13
14 General-Purpose Interrupt 14 IVG14 DMA Channel 11 (UART1 Tx) IVG10 14
15 General-Purpose Interrupt 15 IVG15 CAN Rx IVG11 15
CAN Tx IVG11 16
System Interrupt Controller (SIC) DMA Channel 1 (Ethernet Rx, IVG11 17
The system interrupt controller provides the mapping and rout- ADSP-BF536 and ADSP-BF537 only)
ing of events from the many peripheral interrupt sources to the Port H Interrupt A IVG11 17
prioritized general-purpose interrupt inputs of the CEC. DMA Channel 2 (Ethernet Tx, IVG11 18
Although the processor provides a default mapping, the user ADSP-BF536 and ADSP-BF537 only)
can alter the mappings and priorities of interrupt events by writ-
ing the appropriate values into the interrupt assignment Port H Interrupt B IVG11 18
registers (IAR). Table 3 describes the inputs into the SIC and the Timer 0 IVG12 19
default mappings into the CEC. Timer 1 IVG12 20
Timer 2 IVG12 21
Event Control
Timer 3 IVG12 22
The Blackfin processor provides a very flexible mechanism to
Timer 4 IVG12 23
control the processing of events. In the CEC, three registers are
used to coordinate and control events. Each register is Timer 5 IVG12 24
16 bits wide: Timer 6 IVG12 25
• CEC interrupt latch register (ILAT) – Indicates when Timer 7 IVG12 26
events have been latched. The appropriate bit is set when Port F, G Interrupt A IVG12 27
the processor has latched the event and cleared when the Port G Interrupt B IVG12 28

Table 3. System Interrupt Controller (SIC) (Continued) event already detected on this interrupt input. The IPEND reg-
ister contents are monitored by the SIC as the interrupt
Default Peripheral acknowledgement.
Peripheral Interrupt Event Mapping Interrupt ID
The appropriate ILAT register bit is set when an interrupt rising
DMA Channels 12 and 13 IVG13 29 edge is detected (detection requires two core clock cycles). The
(Memory DMA Stream 0) bit is cleared when the respective IPEND register bit is set. The
DMA Channels 14 and 15 IVG13 30 IPEND bit indicates that the event has entered into the proces-
(Memory DMA Stream 1) sor pipeline. At this point the CEC recognizes and queues the
Software Watchdog Timer IVG13 31 next rising edge event on the corresponding event input. The
Port F Interrupt B IVG13 31 minimum latency from the rising edge transition of the general-
purpose interrupt to the IPEND output asserted is three core
event has been accepted into the system. This register is clock cycles; however, the latency can be much higher, depend-
updated automatically by the controller, but it can be writing on the activity within and the state of the processor.
ten only when its corresponding IMASK bit is cleared.
DMA CONTROLLERS
• CEC interrupt mask register (IMASK) – Controls the
masking and unmasking of individual events. When a bit is The Blackfin processors have multiple, independent DMA
set in the IMASK register, that event is unmasked and is channels that support automated data transfers with minimal
processed by the CEC when asserted. A cleared bit in the overhead for the processor core. DMA transfers can occur
IMASK register masks the event, preventing the processor between the processor’s internal memories and any of its DMA-
from servicing the event even though the event may be capable peripherals. Additionally, DMA transfers can be accom-
latched in the ILAT register. This register can be read or plished between any of the DMA-capable peripherals and
written while in supervisor mode. (Note that general-pur- external devices connected to the external memory interfaces,
pose interrupts can be globally enabled and disabled with including the SDRAM controller and the asynchronous mem-
the STI and CLI instructions, respectively.) ory controller. DMA-capable peripherals include the Ethernet
MAC (ADSP-BF536 and ADSP-BF537 only), SPORTs, SPI port,
• CEC interrupt pending register (IPEND) – The IPEND UARTs, and PPI. Each individual DMA-capable peripheral has
register keeps track of all nested events. A set bit in the at least one dedicated DMA channel.
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically The DMA controller supports both one-dimensional (1-D) and
by the controller but can be read while in supervisor mode. two-dimensional (2-D) DMA transfers. DMA transfer initial-
ization can be implemented from registers or from sets of
The SIC allows further control of event processing by providing parameters called descriptor blocks.
three 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt The 2-D DMA capability supports arbitrary row and column
events shown in Table 3 on Page 7. sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
• SIC interrupt mask register (SIC_IMASK) – Controls the column step size can be less than the row step size, allowing
masking and unmasking of each peripheral interrupt event. implementation of interleaved data streams. This feature is
When a bit is set in the register, that peripheral event is especially useful in video applications where data can be de-
unmasked and is processed by the system when asserted. A interleaved on the fly.
cleared bit in the register masks the peripheral event, pre-
venting the processor from servicing the event. Examples of DMA types supported by the DMA controller
include
• SIC interrupt status register (SIC_ISR) – As multiple
peripherals can be mapped to a single event, this register • A single, linear buffer that stops upon completion
allows the software to determine which peripheral event • A circular, auto-refreshing buffer that interrupts on each
source triggered the interrupt. A set bit indicates the full or fractionally full buffer
peripheral is asserting the interrupt, and a cleared bit indi- • 1-D or 2-D DMA using a linked list of descriptors
cates the peripheral is not asserting the event.
• 2-D DMA using an array of descriptors, specifying only the
• SIC interrupt wake-up enable register (SIC_IWR) – By base DMA address within a common page.
enabling the corresponding bit in this register, a peripheral
can be configured to wake up the processor, should the In addition to the dedicated peripheral DMA channels, there are
core be idled when the event is generated. (For more infor- two memory DMA channels provided for transfers between the
mation, see Dynamic Power Management on Page 13.) various memories of the processor system. This enables trans-
fers of blocks of data between any of the memories—including
Because multiple interrupt sources can map to a single general- external SDRAM, ROM, SRAM, and flash memory—with mini-
purpose interrupt, multiple pulse assertions can occur simulta- mal processor intervention. Memory DMA transfers can be
neously, before or during interrupt processing for an interrupt controlled by a very flexible descriptor-based methodology or
by a standard register-based autobuffer mechanism.

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors also
have an external DMA controller capability via dual external RTXI RTXO
DMA request pins when used in conjunction with the external R1

bus interface unit (EBIU). This functionality can be used when a
high speed interface is required for external FIFOs and high
X1
bandwidth communications peripherals such as USB 2.0. It
allows control of the number of data transfers for memDMA. C1 C2
The number of transfers per edge is programmable. This feature
can be programmed to allow memDMA to have an increased
priority on the external bus relative to the core.
SUGGESTED COMPONENTS:
REAL-TIME CLOCK ECLIPTEK EC38J (THROUGH-HOLE PACKAGE)
EPSON MC405 12pF LOAD (SURFACE-MOUNT PACKAGE)
C1 = 22pF
The real-time clock (RTC) provides a robust set of digital watch C2 = 22pF
features, including current time, stopwatch, and alarm. The R1 = 10M⍀
RTC is clocked by a 32.768 kHz crystal external to the NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
processor. The RTC peripheral has dedicated power supply pins SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3pF.
so that it can remain powered up and clocked even when the
rest of the processor is in a low power state. The RTC provides Figure 4. External Components for RTC
several programmable interrupt options, including interrupt
per second, minute, hour, or day clock ticks, interrupt on pro- If configured to generate a hardware reset, the watchdog timer
grammable stopwatch countdown, or interrupt at a resets both the core and the processor peripherals. After a reset,
programmed alarm time. software can determine if the watchdog was the source of the
The 32.768 kHz input clock frequency is divided down to a 1 Hz hardware reset by interrogating a status bit in the watchdog
signal by a prescaler. The counter function of the timer consists timer control register.
of four counters: a 60-second counter, a 60-minute counter, a The timer is clocked by the system clock (SCLK), at a maximum
24-hour counter, and an 32,768-day counter. frequency of fSCLK.
When enabled, the alarm function generates an interrupt when
TIMERS
the output of the timer matches the programmed value in the
alarm control register. There are two alarms: The first alarm is There are nine general-purpose programmable timer units in
for a time of day, while the second alarm is for a day and time of the processor. Eight timers have an external pin that can be con-
that day. figured either as a pulse-width modulator (PWM) or timer
output, as an input to clock the timer, or as a mechanism for
The stopwatch function counts down from a programmed
measuring pulse widths and periods of external events. These
value, with one-second resolution. When the stopwatch is
timers can be synchronized to an external clock input to the sev-
enabled and the counter underflows, an interrupt is generated.
eral other associated PF pins, to an external clock input to the
Like the other peripherals, the RTC can wake up the processor PPI_CLK input pin, or to the internal SCLK.
from sleep mode upon generation of any RTC wake-up event.
The timer units can be used in conjunction with the two UARTs
Additionally, an RTC wake-up event can wake up the processor
and the CAN controller to measure the width of the pulses in
from deep sleep mode, and wake up the on-chip internal voltage
the data stream to provide a software auto-baud detect function
regulator from the hibernate operating mode.
for the respective serial channels.
Connect RTC pins RTXI and RTXO with external components
The timers can generate interrupts to the processor core provid-
as shown in Figure 4.
ing periodic events for synchronization, either to the system
WATCHDOG TIMER clock or to a count of external signals.
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors In addition to the eight general-purpose programmable timers,
include a 32-bit timer that can be used to implement a software a ninth timer is also provided. This extra timer is clocked by the
watchdog function. A software watchdog can improve system internal processor clock and is typically used as a system tick
availability by forcing the processor to a known state through clock for generating periodic interrupts in an operating system.
generation of a system reset, nonmaskable interrupt (NMI), or
general-purpose interrupt, if the timer expires before being reset
by software. The programmer initializes the count value of the
timer, enables the appropriate interrupt, then enables the timer.
Thereafter, the software must reload the counter before it
counts to zero from the programmed value. This protects the
system from remaining in an unknown state where software,
which would normally reset the timer, has stopped running due
to an external noise condition or software error.

SERIAL PORTS (SPORTs) port provides a full-duplex, synchronous serial interface, which
supports both master/slave modes and multimaster
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors
environments.
incorporate two dual-channel synchronous serial ports
(SPORT0 and SPORT1) for serial and multiprocessor commu- The SPI port’s baud rate and clock phase/polarities are pro-
nications. The SPORTs support the following features: grammable, and it has an integrated DMA controller,
configurable to support transmit or receive data streams. The
• I2S capable operation.
SPI’s DMA controller can only service unidirectional accesses at
• Bidirectional operation – Each SPORT has two sets of inde- any given time.
pendent transmit and receive pins, enabling eight channels
The SPI port’s clock rate is calculated as:
of I2S stereo audio.
• Buffered (8-deep) transmit and receive ports – Each port f SCLK
SPI Clock Rate = ------------------------------------
has a data register for transferring data words to and from 2 × SPI_BAUD
other processor components and shift registers for shifting
data in and out of the data registers. where the 16-bit SPI_BAUD register contains a value of 2
to 65,535.
• Clocking – Each transmit and receive port can either use an
external serial clock or generate its own, in frequencies During transfers, the SPI port simultaneously transmits and
ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz. receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sam-
• Word length – Each SPORT supports serial data words
pling of data on the two serial data lines.
from 3 bits to 32 bits in length, transferred most significant
bit first or least significant bit first. UART PORTS
• Framing – Each transmit and receive port can run with or The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pro-
without frame sync signals for each data word. Frame sync vide two full-duplex universal asynchronous receiver and
signals can be generated internally or externally, active high transmitter (UART) ports, which are fully compatible with PC-
or low, and with either of two pulse widths and early or late standard UARTs. Each UART port provides a simplified UART
frame sync. interface to other peripherals or hosts, supporting full-duplex,
• Companding in hardware – Each SPORT can perform DMA-supported, asynchronous transfers of serial data. A
A-law or μ-law companding according to ITU recommen- UART port includes support for five to eight data bits, one or
dation G.711. Companding can be selected on the transmit two stop bits, and none, even, or odd parity. Each UART port
and/or receive channel of the SPORT without additional supports two modes of operation:
latencies. • PIO (programmed I/O) – The processor sends or receives
• DMA operations with single-cycle overhead – Each SPORT data by writing or reading I/O mapped UART registers.
can automatically receive and transmit multiple buffers of The data is double-buffered on both transmit and receive.
memory data. The processor can link or chain sequences of • DMA (direct memory access) – The DMA controller trans-
DMA transfers between a SPORT and memory. fers both transmit and receive data. This reduces the
• Interrupts – Each transmit and receive port generates an number and frequency of interrupts required to transfer
interrupt upon completing the transfer of a data word or data to and from memory. The UART has two dedicated
after transferring an entire data buffer, or buffers, DMA channels, one for transmit and one for receive. These
through DMA. DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
• Multichannel capability – Each SPORT supports 128 chan-
nels out of a 1024-channel window and is compatible with Each UART port’s baud rate, serial data format, error code gen-
the H.100, H.110, MVIP-90, and HMVIP standards. eration and status, and interrupts are programmable:
• Supporting bit rates ranging from (fSCLK/1,048,576) to
SERIAL PERIPHERAL INTERFACE (SPI) PORT
(fSCLK/16) bits per second.
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors have
• Supporting data formats from 7 bits to 12 bits per frame.
an SPI-compatible port that enables the processor to communi-
cate with multiple SPI-compatible devices. • Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
The SPI interface uses three pins for transferring data: two data
pins (Master Output-Slave Input, MOSI, and Master Input- The UART port’s clock rate is calculated as:
Slave Output, MISO) and a clock pin (serial clock, SCK). An SPI
f SCLK
chip select input pin (SPISS) lets other SPI devices select the UART Clock Rate = --------------------------------------------------
processor, and seven SPI chip select output pins (SPISEL7–1) let 16 × UARTx_Divisor
the processor select other SPI devices. The SPI select pins are
where the 16-bit UARTx_Divisor comes from the UARTx_DLH
reconfigured programmable flag pins. Using these pins, the SPI
register (most significant 8 bits) and UARTx_DLL register (least
significant 8 bits).

In conjunction with the general-purpose timer functions, auto- 10/100 ETHERNET MAC
baud detection is supported.
The ADSP-BF536 and ADSP-BF537 processors offer the capa-
The capabilities of the UARTs are further extended with sup- bility to directly connect to a network by way of an embedded
port for the infrared data association (IrDA®) serial infrared fast Ethernet Media Access Controller (MAC) that supports
physical layer link specification (SIR) protocol. both 10-BaseT (10 Mbps) and 100-BaseT (100 Mbps) operation.
The 10/100 Ethernet MAC peripheral is fully compliant to the
CONTROLLER AREA NETWORK (CAN) IEEE 802.3-2002 standard, and it provides programmable fea-
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors offer tures designed to minimize supervision, bus use, or message
a CAN controller that is a communication controller imple- processing by the rest of the processor system.
menting the CAN 2.0B (active) protocol. This protocol is an Some standard features are
asynchronous communications protocol used in both industrial
and automotive control systems. The CAN protocol is well- • Support of MII and RMII protocols for external PHYs.
suited for control applications due to its capability to communi- • Full duplex and half duplex modes.
cate reliably over a network, since the protocol incorporates
• Data framing and encapsulation: generation and detection
CRC checking message error tracking, and fault node
of preamble, length padding, and FCS.
confinement.
• Media access management (in half-duplex operation): col-
The CAN controller offers the following features:
lision and contention handling, including control of
• 32 mailboxes (eight receive only, eight transmit only, 16 retransmission of collision frames and of back-off timing.
configurable for receive or transmit).
• Flow control (in full-duplex operation): generation and
• Dedicated acceptance masks for each mailbox. detection of PAUSE frames.
• Additional data filtering on first two bytes. • Station management: generation of MDC/MDIO frames
• Support for both the standard (11-bit) and extended for read-write access to PHY registers.
(29-bit) identifier (ID) message formats. • SCLK operating range down to 25 MHz (active and sleep
• Support for remote frames. operating modes).
• Active or passive network support. • Internal loopback from Tx to Rx.
• CAN wake-up from hibernation mode (lowest static power Some advanced features are
consumption mode). • Buffered crystal output to external PHY for support of a
• Interrupts, including: Tx complete, Rx complete, error, single crystal system.
global. • Automatic checksum computation of IP header and IP
The electrical characteristics of each network connection are payload fields of Rx frames.
very demanding so the CAN interface is typically divided into • Independent 32-bit descriptor-driven Rx and Tx DMA
two parts: a controller and a transceiver. This allows a single channels.
controller to support different drivers and CAN networks. The
• Frame status delivery to memory via DMA, including
CAN module represents only the controller part of the interface.
frame completion semaphores, for efficient buffer queue
The controller interface supports connection to 3.3 V high-
management in software.
speed, fault-tolerant, single-wire transceivers.
• Tx DMA support for separate descriptors for MAC header
TWI CONTROLLER INTERFACE and payload to eliminate buffer copy operations.
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors • Convenient frame alignment modes support even 32-bit
include a 2-wire interface (TWI) module for providing a simple alignment of encapsulated Rx or Tx IP packet data in mem-
exchange method of control data between multiple devices. The ory after the 14-byte MAC header.
TWI is compatible with the widely used I2C® bus standard. The • Programmable Ethernet event interrupt supports any com-
TWI module offers the capabilities of simultaneous master and bination of
slave operation, support for both 7-bit addressing and multime-
dia data arbitration. The TWI interface utilizes two pins for • Any selected Rx or Tx frame status conditions.
transferring clock (SCL) and data (SDA) and supports the • PHY interrupt condition.
protocol at speeds up to 400 kbps. The TWI interface pins are
• Wake-up frame detected.
compatible with 5 V logic levels.
• Any selected MAC management counter(s) at
Additionally, the processor’s TWI module is fully compatible
half-full.
with serial camera control bus (SCCB) functionality for easier
control of various CMOS camera sensor devices. • DMA descriptor error.
• 47 MAC management statistics counters with selectable
clear-on-read behavior and programmable interrupts on
half maximum value.

• Programmable Rx address filters, including a 64-bit GPIO pins defined as inputs can be configured to generate
address hash table for multicast and/or unicast frames, and hardware interrupts, while output pins can be triggered by
programmable filter modes for broadcast, multicast, uni- software interrupts.
cast, control, and damaged frames. • GPIO interrupt sensitivity registers – The two GPIO inter-
• Advanced power management supporting unattended rupt sensitivity registers specify whether individual pins are
transfer of Rx and Tx frames and status to/from external level- or edge-sensitive and specify—if edge-sensitive—
memory via DMA during low power sleep mode. whether just the rising edge or both the rising and falling
• System wake-up from sleep operating mode upon magic edges of the signal are significant. One register selects the
packet or any of four user-definable wake-up frame filters. type of sensitivity, and one register selects which edges are
significant for edge-sensitivity.
• Support for 802.3Q tagged VLAN frames.
• Programmable MDC clock rate and preamble suppression. PARALLEL PERIPHERAL INTERFACE (PPI)
• In RMII operation, 7 unused pins can be configured as The processor provides a parallel peripheral interface (PPI) that
GPIO pins for other purposes. can connect directly to parallel ADC and DAC converters, video
encoders and decoders, and other general-purpose peripherals.
PORTS The PPI consists of a dedicated input clock pin, up to three
frame synchronization pins, and up to 16 data pins. The input
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors
clock supports parallel data rates up to half the system clock rate
group the many peripheral signals to four ports—Port F, Port G,
and the synchronization signals can be configured as either
Port H, and Port J. Most of the associated pins are shared by
inputs or outputs.
multiple signals. The ports function as multiplexer controls.
Eight of the pins (Port F7–0) offer high source/high sink current The PPI supports a variety of general-purpose and ITU-R 656
capabilities. modes of operation. In general-purpose mode, the PPI provides
half-duplex, bidirectional data transfer with up to 16 bits of
General-Purpose I/O (GPIO) data. Up to three frame synchronization signals are also pro-
The processors have 48 bidirectional, general-purpose I/O vided. In ITU-R 656 mode, the PPI provides half-duplex
(GPIO) pins allocated across three separate GPIO modules— bidirectional transfer of 8- or 10-bit video data. Additionally,
PORTFIO, PORTGIO, and PORTHIO, associated with Port F, on-chip decode of embedded start-of-line (SOL) and start-of-
Port G, and Port H, respectively. Port J does not provide GPIO field (SOF) preamble packets is supported.
functionality. Each GPIO-capable pin shares functionality with
General-Purpose Mode Descriptions
other processor peripherals via a multiplexing scheme; however,
the GPIO functionality is the default state of the device upon The general-purpose modes of the PPI are intended to suit a
power-up. Neither GPIO output or input drivers are active by wide variety of data capture and transmission applications.
default. Each general-purpose port pin can be individually con- Three distinct submodes are supported:
trolled by manipulation of the port control, status, and interrupt 1. Input mode – Frame syncs and data are inputs into the PPI.
registers:
2. Frame capture mode – Frame syncs are outputs from the
• GPIO direction control register – Specifies the direction of PPI, but data are inputs.
each individual GPIO pin as input or output.
3. Output mode – Frame syncs and data are outputs from the
• GPIO control and status registers – The processors employ PPI.
a “write one to modify” mechanism that allows any combi-
nation of individual GPIO pins to be modified in a single Input Mode
instruction, without affecting the level of any other GPIO Input mode is intended for ADC applications, as well as video
pins. Four control registers are provided. One register is communication with hardware signaling. In its simplest form,
written in order to set pin values, one register is written in PPI_FS1 is an external frame sync input that controls when to
order to clear pin values, one register is written in order to read data. The PPI_DELAY MMR allows for a delay (in
toggle pin values, and one register is written in order to PPI_CLK cycles) between reception of this frame sync and the
specify a pin value. Reading the GPIO status register allows initiation of data reads. The number of input data samples is
software to interrogate the sense of the pins. user programmable and defined by the contents of the
• GPIO interrupt mask registers – The two GPIO interrupt PPI_COUNT register. The PPI supports 8-bit and 10-bit
mask registers allow each individual GPIO pin to function through 16-bit data, programmable in the PPI_CONTROL
as an interrupt to the processor. Similar to the two GPIO register.
control registers that are used to set and clear individual
pin values, one GPIO interrupt mask register sets bits to
enable interrupt function, and the other GPIO interrupt
mask register clears bits to disable interrupt function.

Frame Capture Mode Full-On Operating Mode—Maximum Performance
Frame capture mode allows the video source(s) to act as a slave In the full-on mode, the PLL is enabled and is not bypassed,
(for frame capture for example). The ADSP-BF534/ providing capability for maximum operational frequency. This
ADSP-BF536/ADSP-BF537 processors control when to read is the power-up default execution state in which maximum per-
from the video source(s). PPI_FS1 is an HSYNC output and formance can be achieved. The processor core and all enabled
PPI_FS2 is a VSYNC output. peripherals run at full speed.
Output Mode Active Operating Mode—Moderate Dynamic Power
Output mode is used for transmitting video or other data with Savings
up to three output frame syncs. Typically, a single frame sync is In the active mode, the PLL is enabled but bypassed. Because the
appropriate for data converter applications, whereas two or PLL is bypassed, the processor’s core clock (CCLK) and system
three frame syncs could be used for sending video with hard- clock (SCLK) run at the input clock (CLKIN) frequency. In this
ware signaling. mode, the CLKIN to CCLK multiplier ratio can be changed,
ITU-R 656 Mode Descriptions although the changes are not realized until the full-on mode is
entered. DMA access is available to appropriately configured
The ITU-R 656 modes of the PPI are intended to suit a wide L1 memories.
variety of video capture, processing, and transmission applica-
In the active mode, it is possible to disable the PLL through the
tions. Three distinct submodes are supported:
PLL control register (PLL_CTL). If disabled, the PLL must be
1. Active video only mode re-enabled before transitioning to the full-on or sleep modes.
2. Vertical blanking only mode
Sleep Operating Mode—High Dynamic Power Savings
3. Entire field mode
The sleep mode reduces dynamic power dissipation by disabling
Active Video Mode the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi-
Active video only mode is used when only the active video por-
cally an external event or RTC activity wakes up the processor.
tion of a field is of interest and not any of the blanking intervals.
When in the sleep mode, asserting wake-up causes the processor
The PPI does not read in any data between the end of active
to sense the value of the BYPASS bit in the PLL control register
video (EAV) and start of active video (SAV) preamble symbols,
(PLL_CTL). If BYPASS is disabled, the processor transitions to
or any data present during the vertical blanking intervals. In this
the full on mode. If BYPASS is enabled, the processor transi-
mode, the control byte sequences are not stored to memory;
tions to the active mode.
they are filtered by the PPI. After synchronizing to the start of
Field 1, the PPI ignores incoming samples until it sees an SAV System DMA access to L1 memory is not supported in
code. The user specifies the number of active video lines per sleep mode.
frame (in PPI_COUNT register).
Table 4. Power Settings
Vertical Blanking Interval Mode
In this mode, the PPI only transfers vertical blanking interval Core System Internal
(VBI) data. PLL Clock Clock Power
Mode PLL Bypassed (CCLK) (SCLK) (VDDINT)
Entire Field Mode Full On Enabled No Enabled Enabled On
In this mode, the entire incoming bit stream is read in through Active Enabled/ Yes Enabled Enabled On
the PPI. This includes active video, control preamble sequences, Disabled
and ancillary data that may be embedded in horizontal and ver- Sleep Enabled — Disabled Enabled On
tical blanking intervals. Data transfer starts immediately after
Deep Disabled — Disabled Disabled On
synchronization to Field 1. Data is transferred to or from the
Sleep
synchronous channels through eight DMA engines that work
autonomously from the processor core. Hibernate Disabled — Disabled Disabled Off
DYNAMIC POWER MANAGEMENT Deep Sleep Operating Mode—Maximum Dynamic Power

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pro- Savings
vide five operating modes, each with a different performance The deep sleep mode maximizes dynamic power savings by dis-
and power profile. In addition, dynamic power management abling the clocks to the processor core (CCLK) and to all
provides the control functions to dynamically alter the proces- synchronous peripherals (SCLK). Asynchronous peripherals,
sor core supply voltage, further reducing power dissipation. such as the RTC, may still be running but cannot access internal
Control of clocking to each of the peripherals also reduces resources or external memory. This powered-down mode can
power consumption. See Table 4 for a summary of the power only be exited by assertion of the reset interrupt (RESET) or by
settings for each mode. Also, see Table 16, Table 15 and an asynchronous interrupt generated by the RTC. When in deep
Table 17. sleep mode, an RTC asynchronous interrupt causes the

processor to transition to the active mode. Assertion of RESET reduction in power dissipation, while reducing the voltage by
while in deep sleep mode causes the processor to transition to 25% reduces power dissipation by more than 40%. Further,
the full-on mode. these power savings are additive, in that if the clock frequency
and supply voltage are both reduced, the power savings can be
Hibernate State—Maximum Static Power Savings dramatic, as shown in the following equations.
The hibernate state maximizes static power savings by disabling The power savings factor (PSF) is calculated as:
the voltage and clocks to the processor core (CCLK) and to all of
the synchronous peripherals (SCLK). The internal voltage regu-
f CCLKRED  V DDINTRED  2  t RED 
lator for the processor can be shut off by writing b#00 to the - × -------------------------- × -----------
PSF = --------------------
FREQ bits of the VR_CTL register. This disables both CCLK f CCLKNOM  V DDINTNOM  t NOM 
and SCLK. Furthermore, it sets the internal power supply volt-
age (VDDINT) to 0 V to provide the greatest power savings. To where:
preserve the processor state, prior to removing power, any criti- fCCLKNOM is the nominal core clock frequency
cal information stored internally (memory contents, register
contents, etc.) must be written to a nonvolatile storage device. fCCLKRED is the reduced core clock frequency
Since VDDEXT is still supplied in this state, all of the external pins VDDINTNOM is the nominal internal supply voltage
three-state, unless otherwise specified. This allows other devices VDDINTRED is the reduced internal supply voltage
that are connected to the processor to still have power applied
tNOM is the duration running at fCCLKNOM
without drawing unwanted current.
tRED is the duration running at fCCLKRED
The Ethernet or CAN modules can wake up the internal supply
regulator. If the PH6 pin does not connect as the PHYINT sig- The percent power savings is calculated as
nal to an external PHY device, it can be pulled low by any other
device to wake the processor up. The regulator can also be % power savings = ( 1 – PSF ) × 100%
woken up by a real-time clock wake-up event or by asserting the
RESET pin. All hibernate wake-up events initiate the hardware VOLTAGE REGULATION
reset sequence. Individual sources are enabled by the VR_CTL
register. The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pro-
vide an on-chip voltage regulator that can generate appropriate
With the exception of the VR_CTL and the RTC registers, all
VDDINT voltage levels from the VDDEXT supply. See Operating
internal registers and memories lose their content in the hiber-
Conditions on Page 23 for regulator tolerances and acceptable
nate state. State variables can be held in external SRAM or
VDDEXT ranges for specific models.
SDRAM. The SCKELOW bit in the VR_CTL register controls
whether SDRAM operates in self-refresh mode, which allows it
to retain its content while the processor is in reset. VDDEXT
SET OF DECOUPLING
(LOW-INDUCTANCE) CAPACITORS
Power Savings
VDDEXT
As shown in Table 5, the processors support three different +
power domains which maximizes flexibility, while maintaining
100μF
compliance with industry standards and conventions. By isolat-
ing the internal logic of the processor into its own power 100nF 10μH
VDDINT
domain, separate from the RTC and other I/O, the processor + +
can take advantage of dynamic power management, without 100μF
FDS9431A
affecting the RTC or other I/O devices. There are no sequencing
10μF 100μF
requirements for the various power domains. LOW ESR ZHCS1000
VROUT
Table 5. Power Domains
SHORT AND LOW- VROUT
Power Domain VDD Range INDUCTANCE WIRE
All internal logic, except RTC VDDINT NOTE: DESIGNER SHOULD MINIMIZE
TRACE LENGTH TO FDS9431A. GND
RTC internal logic and crystal I/O VDDRTC
All other I/O VDDEXT
The dynamic power management feature allows both the pro- Figure 5. Voltage Regulator Circuit
cessor’s input voltage (VDDINT) and clock frequency (fCCLK) to be
dynamically controlled. Figure 5 shows the typical external components required to
The power dissipated by a processor is largely a function of its complete the power management system. The regulator con-
clock frequency and the square of the operating voltage. For trols the internal logic voltage levels and is programmable with
example, reducing the clock frequency by 25% results in a 25% the voltage regulator control register (VR_CTL) in increments

of 50 mV. To reduce standby power consumption, the internal
voltage regulator can be programmed to remove power to the BLACKFIN
processor core while keeping I/O power supplied. While in CLKOUT

hibernate state, VDDEXT can still be applied, eliminating the need TO PLL CIRCUITRY
for external buffers. The voltage regulator can be activated from EN
this power-down state by asserting the RESET pin, which then CLKBUF
initiates a boot sequence. The regulator can also be disabled and

EN
bypassed at the user’s discretion. For additional information on 3506
voltage regulation, see Switching Regulator Design Consider-
VDDEXT
ations for the ADSP-BF533 Blackfin Processors (EE-228).
CLKIN XTAL
CLOCK SIGNALS 3306* 1M6
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors can

be clocked by an external crystal, a sine wave input, or a buff-
18pF* 18pF* FOR OVERTONE
ered, shaped clock derived from an external clock oscillator. OPERATION ONLY
If an external clock is used, it should be a TTL compatible signal

and must not be halted, changed, or operated below the speci- NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED
fied frequency during normal operation. This signal is DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE
ANALYZE CAREFULLY
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Figure 6. External Crystal Connections
Alternatively, because the processors include an on-chip oscilla-
tor circuit, an external crystal can be used. For fundamental with 25 MHz clock input options. The CLKBUF output is active
frequency operation, use the circuit shown in Figure 6. A by default and can be disabled using the VR_CTL register for
parallel-resonant, fundamental frequency, microprocessor- power savings.
grade crystal is connected across the CLKIN and XTAL pins.
The Blackfin core runs at a different clock rate than the on-chip
The on-chip resistance between CLKIN and the XTAL pin is in
peripherals. As shown in Figure 7, the core clock (CCLK) and
the 500 kΩ range. Further parallel resistors are typically not rec-
system peripheral clock (SCLK) are derived from the input
ommended. The two capacitors and the series resistor shown in
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
Figure 6 fine-tune phase and amplitude of the sine frequency.
the CLKIN signal by a programmable 0.5× to 64× multiplication
The capacitor and resistor values shown in Figure 6 are typical factor (bounded by specified minimum and maximum VCO
values only. The capacitor values are dependent upon the crystal frequencies). The default multiplier is 10×, but it can be modi-
manufacturers’ load capacitance recommendations and the PCB fied by a software instruction sequence in the PLL_CTL register.
physical layout. The resistor value depends on the drive level
On-the-fly CCLK and SCLK frequency changes can be effected
specified by the crystal manufacturer. The user should verify the
by simply writing to the PLL_DIV register. Whereas the maxi-
customized values based on careful investigations of multiple
mum allowed CCLK and SCLK rates depend on the applied
devices over temperature range.
voltages VDDINT and VDDEXT, the VCO is always permitted to run
A third-overtone crystal can be used for frequencies above up to the frequency specified by the part’s speed grade. The
25 MHz. The circuit is then modified to ensure crystal operation CLKOUT pin reflects the SCLK frequency to the off-chip world.
only at the third overtone, by adding a tuned inductor circuit as It belongs to the SDRAM interface, but it functions as a refer-
shown in Figure 6. A design procedure for third-overtone oper- ence signal in other timing specifications as well. While active
ation is discussed in detail in the application note Using Third by default, it can be disabled using the EBIU_SDGCTL and
Overtone Crystals with the ADSP-218x DSP (EE-168). EBIU_AMGCTL registers.
The CLKBUF pin is an output pin, and is a buffer version of the
input clock. This pin is particularly useful in Ethernet applica-
FINE ADJUSTMENT COURSE ADJUSTMENT
tions to limit the number of required clock sources in the REQUIRES PLL SEQUENCING ON-THE-F LY
system. In this type of application, a single 25 MHz or 50 MHz
crystal can be applied directly to the processors. The 25 MHz or
50 MHz output of CLKBUF can then be connected to an exter- ⴜ 1, 2, 4, 8 CCLK
nal Ethernet MII or RMII PHY device. CLKIN

PLL
VCO
0.5x TO 64x
Because of the default 10× PLL multiplier, providing a 50 MHz ⴜ 1 TO 15 SCLK
CLKIN exceeds the recommended operating conditions of the
lower speed grades. Because of this restriction, an RMII PHY
requiring a 50 MHz clock input cannot be clocked directly from SCLK ≤ CCLK
the CLKBUF pin for the lower speed grades. In this case, either SCLK ≤ 133MHz
provide a separate 50 MHz clock source, or use an RMII PHY
Figure 7. Frequency Modification Methods

All on-chip peripherals are clocked by the system clock (SCLK). Table 8. Booting Modes
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed BMODE2–0 Description
into the SSEL fields define a divide ratio between the PLL output 000 Execute from 16-bit external memory (bypass
(VCO) and the system clock. SCLK divider values are 1 through boot ROM)
15. Table 6 illustrates typical system clock ratios. 001 Boot from 8-bit or 16-bit memory
Note that the divisor ratio must be chosen to limit the system (EPROM/flash)
clock frequency to its maximum of fSCLK. The SSEL value can be 010 Reserved
changed dynamically without any PLL lock latencies by writing 011 Boot from serial SPI memory (EEPROM/flash)
the appropriate values to the PLL divisor register (PLL_DIV). 100 Boot from SPI host (slave mode)
Table 6. Example System Clock Ratios 101 Boot from serial TWI memory (EEPROM/flash)
110 Boot from TWI host (slave mode)
Example Frequency Ratios 111 Boot from UART host (slave mode)
Signal Name Divider Ratio (MHz)
SSEL3–0 VCO:SCLK VCO SCLK The BMODE pins of the reset configuration register, sampled
0001 1:1 100 100 during power-on resets and software-initiated resets, imple-
0110 6:1 300 50 ment the following modes:
1010 10:1 500 50 • Execute from 16-bit external memory – Execution starts
from address 0x2000 0000 with 16-bit packing. The boot
The core clock (CCLK) frequency can also be dynamically ROM is bypassed in this mode. All configuration settings
changed by means of the CSEL1–0 bits of the PLL_DIV register. are set for the slowest device possible (3-cycle hold time;
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in 15-cycle R/W access times; 4-cycle setup).
Table 7. This programmable core clock capability is useful for • Boot from 8-bit and 16-bit external flash memory – The
fast core frequency modifications. 8-bit or 16-bit flash boot routine located in Boot ROM
memory space is set up using asynchronous memory
Table 7. Core Clock Ratios bank 0. All configuration settings are set for the slowest
device possible (3-cycle hold time; 15-cycle R/W access
Example Frequency Ratios times; 4-cycle setup). The Boot ROM evaluates the first
Signal Name Divider Ratio (MHz) byte of the boot stream at address 0x2000 0000. If it is 0x40,
CSEL1–0 VCO:CCLK VCO CCLK 8-bit boot is performed. A 0x60 byte assumes a 16-bit
00 1:1 300 300 memory device and performs 8-bit DMA. A 0x20 byte also
01 2:1 300 150 assumes 16-bit memory but performs 16-bit DMA.
10 4:1 500 125 • Boot from serial SPI memory (EEPROM or flash) – 8-, 16-,
11 8:1 200 25 or 24-bit addressable devices are supported as well as
AT45DB041, AT45DB081, AT45DB161, AT45DB321,
The maximum CCLK frequency not only depends on the part’s AT45DB642, and AT45DB1282 DataFlash® devices from
speed grade (see Ordering Guide on Page 65), it also depends on Atmel. The SPI uses the PF10/SPI SSEL1 output pin to
the applied VDDINT voltage (see Table 10, Table 11, and Table 12 select a single SPI EEPROM/flash device, submits a read
on Page 24 for details). The maximal system clock rate (SCLK) command and successive address bytes (0x00) until a valid
depends on the chip package and the applied VDDEXT voltage (see 8-, 16-, or 24-bit, or Atmel addressable device is detected,
Table 14 on Page 24). and begins clocking data into the processor.
• Boot from SPI host device – The Blackfin processor oper-
BOOTING MODES ates in SPI slave mode and is configured to receive the bytes
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processor has six of the .LDR file from an SPI host (master) agent. To hold
mechanisms (listed in Table 8) for automatically loading inter- off the host device from transmitting while the boot ROM
nal and external memory after a reset. A seventh mode is is busy, the Blackfin processor asserts a GPIO pin, called
provided to execute from external memory, bypassing the boot host wait (HWAIT), to signal the host device not to send
sequence. any more bytes until the flag is deasserted. The flag is cho-
sen by the user and this information is transferred to the
Blackfin processor via bits 10:5 of the FLAG header.
• Boot from UART – Using an autobaud handshake
sequence, a boot-stream-formatted program is downloaded
by the host. The host agent selects a baud rate within the
UART’s clocking capabilities. When performing the auto-
baud, the UART expects an “@” (boot stream) character

(8 bits data, 1 start bit, 1 stop bit, no parity bit) on the RXD The assembly language, which takes advantage of the proces-
pin to determine the bit rate. It then replies with an sor’s unique architecture, offers the following advantages:
acknowledgement that is composed of 4 bytes: 0xBF, the • Seamlessly integrated DSP/MCU features are optimized for
value of UART_DLL, the value of UART_DLH, and 0x00. both 8-bit and 16-bit operations.
The host can then download the boot stream. When the
processor needs to hold off the host, it deasserts CTS. • A multi-issue load/store modified-Harvard architecture,
Therefore, the host must monitor this signal. which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
• Boot from serial TWI memory (EEPROM/flash) – The
Blackfin processor operates in master mode and selects the • All registers, I/O, and memory are mapped into a unified
TWI slave with the unique ID 0xA0. It submits successive 4G byte memory space, providing a simplified program-
read commands to the memory device starting at 2-byte ming model.
internal address 0x0000 and begins clocking data into the • Microcontroller features, such as arbitrary bit and bit-field
processor. The TWI memory device should comply with manipulation, insertion, and extraction; integer operations
Philips I2C Bus Specification version 2.1 and have the capa- on 8-, 16-, and 32-bit data-types; and separate user and
bility to auto-increment its internal address counter such supervisor stack pointers.
that the contents of the memory device can be read
• Code density enhancements, which include intermixing of
sequentially.
16-bit and 32-bit instructions (no mode switching, no code
• Boot from TWI host – The TWI host agent selects the slave segregation). Frequently used instructions are encoded
with the unique ID 0x5F. The processor replies with an in 16 bits.
acknowledgement and the host can then download the
boot stream. The TWI host agent should comply with DEVELOPMENT TOOLS
Philips I2C Bus Specification version 2.1. An I2C multi- Blackfin processors are supported with a complete set of
plexer can be used to select one processor at a time when CROSSCORE®† software and hardware development tools,
booting multiple processors from a single TWI. including Analog Devices emulators and the VisualDSP++®‡
For each of the boot modes, a 10-byte header is first brought in development environment. The same emulator hardware that
from an external device. The header specifies the number of supports other Analog Devices processors also fully emulates
bytes to be transferred and the memory destination address. the Blackfin processor family.
Multiple memory blocks can be loaded by any boot sequence. The VisualDSP++ project management environment lets pro-
Once all blocks are loaded, program execution commences from grammers develop and debug an application. This environment
the start of L1 instruction SRAM. includes an easy to use assembler that is based on an algebraic
In addition, Bit 4 of the reset configuration register can be set by syntax, an archiver (librarian/library builder), a linker, a loader,
application code to bypass the normal boot sequence during a a cycle-accurate instruction-level simulator, a C/C++ compiler,
software reset. For this case, the processor jumps directly to the and a C/C++ runtime library that includes DSP and mathemati-
beginning of L1 instruction memory. cal functions. A key point for these tools is C/C++ code
efficiency. The compiler has been developed for efficient
To augment the boot modes, a secondary software loader can be
translation of C/C++ code to Blackfin assembly. The Blackfin
added to provide additional booting mechanisms. This second-
processor has architectural features that improve the efficiency
ary loader could provide the capability to boot from flash,
of compiled C/C++ code.
variable baud rate, and other sources. In all boot modes except
bypass, program execution starts from on-chip L1 memory The VisualDSP++ debugger has a number of important fea-
address 0xFFA0 0000. tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
INSTRUCTION SET DESCRIPTION tion of user data enables the programmer to quickly determine
The Blackfin processor family assembly language instruction set the performance of an algorithm. As algorithms grow in com-
employs an algebraic syntax designed for ease of coding and plexity, this capability can have increasing significance on the
readability. The instructions have been specifically tuned to pro- designer’s development schedule, increasing productivity. Sta-
vide a flexible, densely encoded instruction set that compiles to tistical profiling enables the programmer to nonintrusively poll
a very small final memory size. The instruction set also provides the processor as it is running the program. This feature, unique
fully featured multifunction instructions that allow the to VisualDSP++, enables the software developer to passively
programmer to use many of the processor core resources in a gather important code execution metrics without interrupting
single instruction. Coupled with many features more often seen the real-time characteristics of the program. Essentially, the
on microcontrollers, this instruction set is very efficient when developer can identify bottlenecks in software quickly and
compiling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of opera-
tion, allowing multiple levels of access to core processor
resources. †
CROSSCORE is a registered trademark of Analog Devices, Inc.
‡
VisualDSP++ is a registered trademark of Analog Devices, Inc.

efficiently. By using the profiler, the programmer can focus on Analog Devices emulators use the IEEE 1149.1 JTAG test access
those areas in the program that impact performance and take port of the Blackfin to monitor and control the target board
corrective action. processor during emulation. The emulator provides full-speed
Debugging both C/C++ and assembly programs with the emulation, allowing inspection and modification of memory,
VisualDSP++ debugger, programmers can registers, and processor stacks. Nonintrusive in-circuit emula-
tion is assured by the use of the processor’s JTAG interface—the
• View mixed C/C++ and assembly code (interleaved source emulator does not affect target system loading or timing.
and object information).
In addition to the software and hardware development tools
• Insert breakpoints. available from Analog Devices, third parties provide a wide
• Set conditional breakpoints on registers, memory, and range of tools supporting the Blackfin processor family. Third
stacks. party software tools include DSP libraries, real-time operating
systems, and block diagram design tools.
• Trace instruction execution.
• Perform linear or statistical profiling of program execution. EZ-KIT Lite® Evaluation Board
• Fill, dump, and graphically plot the contents of memory. For evaluation of ADSP-BF534/ADSP-BF536/ADSP-BF537
processors, use the ADSP-BF537 EZ-KIT Lite board available
• Perform source level debugging.
from Analog Devices. Order part number
• Create custom debugger windows. ADDS-BF537-EZLITE. The board comes with on-chip
The VisualDSP++ IDE lets programmers define and manage emulation capabilities and is equipped to enable software
software development. Its dialog boxes and property pages let development. Multiple daughter cards are available.
programmers configure and manage all development tools,
including color syntax highlighting in the VisualDSP++ editor.
DESIGNING AN EMULATOR-COMPATIBLE
These capabilities permit programmers to PROCESSOR BOARD
• Control how the development tools process inputs and The Analog Devices family of emulators are tools that every sys-
generate outputs. tem developer needs in order to test and debug hardware and
software systems. Analog Devices has supplied an IEEE 1149.1
• Maintain a one-to-one correspondence with the tool’s
JTAG Test Access Port (TAP) on each JTAG processor. The
command line switches.
emulator uses the TAP to access the internal features of the pro-
The VisualDSP++ Kernel (VDK) incorporates scheduling and cessor, allowing the developer to load code, set breakpoints,
resource management tailored specifically to address the mem- observe variables, observe memory, and examine registers. The
ory and timing constraints of embedded, real-time processor must be halted to send data and commands, but once
programming. These capabilities enable engineers to develop an operation has been completed by the emulator, the processor
code more effectively, eliminating the need to start from the system is set running at full speed with no impact on
very beginning when developing new application code. The system timing.
VDK features include threads, critical and unscheduled regions,
To use these emulators, the target board must include a header
semaphores, events, and device flags. The VDK also supports
that connects the processor’s JTAG port to the emulator.
priority-based, pre-emptive, cooperative, and time-sliced sched-
uling approaches. In addition, the VDK was designed to be For details on target board design issues including mechanical
scalable. If the application does not use a specific feature, the layout, single processor connections, multiprocessor scan
support code for that feature is excluded from the target system. chains, signal buffering, signal termination, and emulator pod
logic, see Analog Devices JTAG Emulation Technical Reference
Because the VDK is a library, a developer can decide whether to
(EE-68) on the Analog Devices website under
use it or not. The VDK is integrated into the VisualDSP++
www.analog.com/ee-notes. This document is updated regularly
development environment, but can also be used with standard
to keep pace with improvements to emulator support.
command line tools. When the VDK is used, the development
environment assists the developer with many error prone tasks RELATED DOCUMENTS
and assists in managing system resources, automating the gen-
eration of various VDK-based objects, and visualizing the The following publications that describe the ADSP-BF534/
system state when debugging an application that uses the VDK. ADSP-BF536/ADSP-BF537 processors (and related processors)
can be ordered from any Analog Devices sales office or accessed
The expert linker can be used to visually manipulate the place- electronically on our website:
ment of code and data in the embedded system. Memory
utilization can be viewed in a color-coded graphical form. Code • Getting Started with Blackfin Processors
and data can be easily moved to different areas of the processor • ADSP-BF537 Blackfin Processor Hardware Reference
or external memory with the drag of the mouse. Runtime stack • ADSP-BF53x/ADSP-BF56x Blackfin Processor Program-
and heap usage can be examined. The expert linker is fully com- ming Reference
patible with existing linker definition file (LDF), allowing the
developer to move between the graphical and textual • ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Proces-
environments. sor Anomaly List

PIN DESCRIPTIONS
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pin control and address lines are driven high, with the exception of
definitions are listed in Table 9. In order to maintain maximum CLKOUT, which toggles at the system clock rate. If, however
functionality and reduce package size and pin count, some pins the BR pin is asserted, then the memory pins are also three-
have dual, multiplexed functions. In cases where pin function is stated.
reconfigurable, the default state is shown in plain text, while the All I/O pins have their input buffers disabled with the exception
alternate function is shown in italics. Pins shown with an aster- of the pins noted in the data sheet that need pull-ups or pull-
isk after their name (*) offer high source/high sink current downs if unused.
capabilities.
The SDA (serial data) and SCL (serial clock) pins are open drain
All pins are three-stated during and immediately after reset, and therefore require a pull-up resistor. Consult version 2.1 of
with the exception of the external memory interface, asynchro- the I2C specification for the proper resistor value.
nous and synchronous memory control, and the buffered XTAL
output pin (CLKBUF). On the external memory interface, the
Table 9. Pin Descriptions
Driver
Pin Name Type Function Type1
Memory Interface
ADDR19–1 O Address Bus for Async Access A
DATA15–0 I/O Data Bus for Async/Sync Access A
ABE1–0/SDQM1–0 O Byte Enables/Data Masks for Async/Sync Access A
BR I Bus Request (This pin should be pulled high when not used.)
BG O Bus Grant A
BGH O Bus Grant Hang A
Asynchronous Memory Control
AMS3–0 O Bank Select A
ARDY I Hardware Ready Control
AOE O Output Enable A
ARE O Read Enable A
AWE O Write Enable A
Synchronous Memory Control
SRAS O Row Address Strobe A
SCAS O Column Address Strobe A
SWE O Write Enable A
SCKE O Clock Enable (This pin is three-stated during hibernate.) A
CLKOUT O Clock Output B
SA10 O A10 Pin A
SMS O Bank Select A

Table 9. Pin Descriptions (Continued)
Driver
Port F: GPIO/UART1–0/Timer7–0/SPI/
External DMA Request/PPI
(* = High Source/High Sink Pin)
PF0* – GPIO/UART0 TX/DMAR0 I/O GPIO/UART0 Transmit/DMA Request 0 C
PF1* – GPIO/UART0 RX/DMAR1/TACI1 I/O GPIO/UART0 Receive/DMA Request 1/Timer1 Alternate Input Capture C
PF2* – GPIO/UART1 TX/TMR7 I/O GPIO/UART1 Transmit/Timer7 C
PF3* – GPIO/UART1 RX/TMR6/TACI6 I/O GPIO/UART1 Receive/Timer6/Timer6 Alternate Input Capture C
PF4* – GPIO/TMR5/SPI SSEL6 I/O GPIO/Timer5/SPI Slave Select Enable 6 C
PF7* – GPIO/TMR2/PPI FS3 I/O GPIO/Timer2/PPI Frame Sync 3 C
PF8 – GPIO/TMR1/PPI FS2 I/O GPIO/Timer1/PPI Frame Sync 2 C
PF9 – GPIO/TMR0/PPI FS1 I/O GPIO/Timer0/PPI Frame Sync 1 C
PF10 – GPIO/SPI SSEL1 I/O GPIO/SPI Slave Select Enable 1 C
PF11 – GPIO/SPI MOSI I/O GPIO/SPI Master Out Slave In C
PF12 – GPIO/SPI MISO I/O GPIO/SPI Master In Slave Out (This pin should be pulled high through a 4.7 kΩ C
resistor if booting via the SPI port.)
PF13 – GPIO/SPI SCK I/O GPIO/SPI Clock D
PF14 – GPIO/SPI SS/TACLK0 I/O GPIO/SPI Slave Select/Alternate Timer0 Clock Input C
PF15 – GPIO/PPI CLK/TMRCLK I/O GPIO/PPI Clock/External Timer Reference C
Port G: GPIO/PPI/SPORT1
PG0 – GPIO/PPI D0 I/O GPIO/PPI Data 0 C
PG8 – GPIO/PPI D8/DR1SEC I/O GPIO/PPI Data 8/SPORT1 Receive Data Secondary C
PG9 – GPIO/PPI D9/DT1SEC I/O GPIO/PPI Data 9/SPORT1 Transmit Data Secondary C
PG10 – GPIO/PPI D10/RSCLK1 I/O GPIO/PPI Data 10/SPORT1 Receive Serial Clock D
PG11 – GPIO/PPI D11/RFS1 I/O GPIO/PPI Data 11/SPORT1 Receive Frame Sync C
PG12 – GPIO/PPI D12/DR1PRI I/O GPIO/PPI Data 12/SPORT1 Receive Data Primary C
PG13 – GPIO/PPI D13/TSCLK1 I/O GPIO/PPI Data 13/SPORT1 Transmit Serial Clock D
PG14 – GPIO/PPI D14/TFS1 I/O GPIO/PPI Data 14/SPORT1 Transmit Frame Sync C
PG15 – GPIO/PPI D15/DT1PRI I/O GPIO/PPI Data 15/SPORT1 Transmit Data Primary C

Driver
Port H: GPIO/10/100 Ethernet MAC (On
ADSP-BF534, these pins are GPIO only)
PH0 – GPIO/ETxD0 I/O GPIO/Ethernet MII or RMII Transmit D0 E
PH1 – GPIO/ETxD1 I/O GPIO/Ethernet MII or RMII Transmit D1 E
PH2 – GPIO/ETxD2 I/O GPIO/Ethernet MII Transmit D2 E
PH3 – GPIO/ETxD3 I/O GPIO/Ethernet MII Transmit D3 E
PH4 – GPIO/ETxEN I/O GPIO/Ethernet MII or RMII Transmit Enable E
PH5 – GPIO/MII TxCLK/RMII REF_CLK I/O GPIO/Ethernet MII Transmit Clock/RMII Reference Clock E
PH6 – GPIO/MII PHYINT/RMII MDINT I/O GPIO/Ethernet MII PHY Interrupt/RMII Management Data Interrupt (This pin E
should be pulled high when used as a hibernate wake-up.)
PH7 – GPIO/COL I/O GPIO/Ethernet Collision E
PH8 – GPIO/ERxD0 I/O GPIO/Ethernet MII or RMII Receive D0 E
PH9 – GPIO/ERxD1 I/O GPIO/Ethernet MII or RMII Receive D1 E
PH10 – GPIO/ERxD2 I/O GPIO/Ethernet MII Receive D2 E
PH11 – GPIO/ERxD3 I/O GPIO/Ethernet MII Receive D3 E
PH12 – GPIO/ERxDV/TACLK5 I/O GPIO/Ethernet MII Receive Data Valid/Alternate Timer5 Input Clock E
PH13 – GPIO/ERxCLK/TACLK6 I/O GPIO/Ethernet MII Receive Clock/Alternate Timer6 Input Clock E
PH14 – GPIO/ERxER/TACLK7 I/O GPIO/Ethernet MII or RMII Receive Error/Alternate Timer7 Input Clock E
PH15 – GPIO/MII CRS/RMII CRS_DV I/O GPIO/Ethernet MII Carrier Sense/Ethernet RMII Carrier Sense and Receive Data E
Valid
Port J: SPORT0/TWI/SPI Select/CAN
PJ0 – MDC O Ethernet Management Channel Clock (On ADSP-BF534 processors, do not E
connect this pin.)
PJ1 – MDIO I/O Ethernet Management Channel Serial Data (On ADSP-BF534 processors, tie this E
pin to ground.)
PJ2 – SCL I/O TWI Serial Clock (This pin is an open-drain output and requires a pull-up F
resistor.)
PJ3 – SDA I/O TWI Serial Data (This pin is an open-drain output and requires a pull-up F
resistor.)
PJ4 – DR0SEC/CANRX/TACI0 I SPORT0 Receive Data Secondary/CAN Receive/Timer0 Alternate Input Capture
PJ5 – DT0SEC/CANTX/SPI SSEL7 O SPORT0 Transmit Data Secondary/CAN Transmit/SPI Slave Select Enable 7 C
PJ6 – RSCLK0/TACLK2 I/O SPORT0 Receive Serial Clock/Alternate Timer2 Clock Input D
PJ7 – RFS0/TACLK3 I/O SPORT0 Receive Frame Sync/Alternate Timer3 Clock Input C
PJ8 – DR0PRI/TACLK4 I SPORT0 Receive Data Primary/Alternate Timer4 Clock Input
PJ9 – TSCLK0/TACLK1 I/O SPORT0 Transmit Serial Clock/Alternate Timer1 Clock Input D
PJ10 – TFS0/SPI SSEL3 I/O SPORT0 Transmit Frame Sync/SPI Slave Select Enable 3 C
PJ11 – DT0PRI/SPI SSEL2 O SPORT0 Transmit Data Primary/SPI Slave Select Enable 2 C
Real-Time Clock
RTXI I RTC Crystal Input (This pin should be pulled low when not used.)
RTXO O RTC Crystal Output

Driver
JTAG Port
TCK I JTAG Clock
TDO O JTAG Serial Data Out C
TDI I JTAG Serial Data In
TMS I JTAG Mode Select
TRST I JTAG Reset (This pin should be pulled low if the JTAG port is not used.)
EMU O Emulation Output C
Clock
CLKIN I Clock/Crystal Input
XTAL O Crystal Output
CLKBUF O Buffered XTAL Output E
Mode Controls
RESET I Reset
NMI I Nonmaskable Interrupt (This pin should be pulled high when not used.)
BMODE2–0 I Boot Mode Strap 2-0
Voltage Regulator
VROUT0 O External FET Drive
VROUT1 O External FET Drive
Supplies
VDDEXT P I/O Power Supply
VDDINT P Internal Power Supply
VDDRTC P Real-Time Clock Power Supply
GND G External Ground
1
See Output Drive Currents on Page 51 for more information about each driver types.

SPECIFICATIONS
Note that component specifications are subject to change
without notice.
OPERATING CONDITIONS
Parameter Conditions Min Nominal Max Unit

VDDINT Internal Supply Voltage1 Non automotive 300 MHz, 400 MHz, and 500 MHz speed 0.8 1.2 1.32 V
grade models2
VDDINT Internal Supply Voltage1 Non automotive 533 MHz speed grade models2 0.8 1.25 1.375 V
VDDINT Internal Supply Voltage1 Non automotive 600 MHz speed grade models2 0.8 1.3 1.43 V
VDDINT Internal Supply Voltage1 Automotive grade models and +105°C non automotive 0.95 1.2 1.32 V
grade models2
VDDEXT External Supply Voltage Non automotive grade models2 2.25 2.5 or 3.3 3.6 V
VDDEXT External Supply Voltage Automotive grade models and +105°C non automotive 2.7 3.0 or 3.3 3.6 V
grade models2
VDDRTC Real-Time Clock Power 2.25 3.6 V
Supply Voltage
VIH High Level Input Voltage3, 4 VDDEXT = Maximum 2.0 3.6 V
VIHCLKIN High Level Input Voltage5 VDDEXT = Maximum 2.2 3.6 V
VIH5V 5.0 V Tolerant Pins, High 0.7 × VDDEXT 5.5 V
Level Input Voltage6
VIH5V 5.0 V Tolerant Pins, High VDDEXT = Maximum 2.0 5.5 V
VIL Low Level Input Voltage3, 8 VDDEXT = Minimum –0.3 +0.6 V
VIL5V 5.0 V Tolerant Pins, Low –0.3 0.3 × VDDEXT V
VIL5V 5.0 V Tolerant Pins, Low VDDEXT = Minimum –0.3 +0.8 V
TJ Junction Temperature 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @ –40 +120 °C
TAMBIENT = –40°C to +105°C
TJ Junction Temperature 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @ 0 +95 °C
TAMBIENT = 0°C to +70°C
TJ Junction Temperature 182-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @ 0 +100 °C
TAMBIENT = 0°C to +70°C
1
The regulator can generate VDDINT at levels of 0.85 V to 1.2 V with –5% to +10% tolerance, 1.25 V with –4% to +10% tolerance, and 1.3 V with –0% to +10% tolerance. The
required VDDINT is a function of speed grade and operating frequency. See Table 10, Table 11, and Table 12 for details.
2
See Ordering Guide on Page 65.
3
Bidirectional pins (DATA15–0, PF15–0, PG15–0, PH15–0, TFS0, TSCLK0, RSCLK0, RFS0, MDIO) and input pins (BR, ARDY, DR0PRI, DR0SEC, RTXI, TCK, TDI, TMS,
TRST, CLKIN, RESET, NMI, and BMODE2–0) of the ADSP-BF534/ADSP-BF536/ADSP-BF537 are 3.3 V-tolerant (always accept up to 3.6 V maximum VIH). Voltage
compliance (on outputs, VOH) is limited by the VDDEXT supply voltage.
4
Parameter value applies to all input and bidirectional pins except CLKIN, SDA, and SCL.
5
Parameter value applies to CLKIN pin only.
6
Applies to pins PJ2/SCL and PJ3/SDA which are 5.0 V tolerant (always accept up to 5.5 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply
voltage.
7
Applies to pin PJ4/DR0SEC/CANRX/TACI0 which is 5.0 V tolerant (always accepts up to 5.5 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT
supply voltage.
8
Parameter value applies to all input and bidirectional pins except SDA and SCL.

Table 10 through Table 12 describe the voltage/frequency ratios so as not to exceed the maximum core clock and system
requirements for the ADSP-BF534/ADSP-BF536/ADSP-BF537 clock. Table 13 describes phase-locked loop operating
processor clocks. Take care in selecting MSEL, SSEL, and CSEL conditions.
Table 10. Core Clock Requirements—500 MHz, 533 MHz, and 600 MHz Speed Grades1
Parameter Internal Regulator Setting Max Unit

fCCLK Core Clock Frequency (VDDINT =1.30 V Minimum)2 1.30 V 600 MHz
fCCLK Core Clock Frequency (VDDINT = 1.20 V Minimum)3 1.25 V 533 MHz
fCCLK Core Clock Frequency (VDDINT =1.14 V Minimum) 1.20 V 500 MHz
fCCLK Core Clock Frequency (VDDINT = 0.95 V Minimum) 1.00 V 400 MHz
1
2
Applies to 600 MHz models only. See Ordering Guide on Page 65.
3
Applies to 533 MHz and 600 MHz models only. See Ordering Guide on Page 65.
Table 11. Core Clock Requirements—400 MHz Speed Grade1
120°C ≥ TJ > 105°C All2 Other TJ

Parameter Internal Regulator Setting Max Max Unit
fCCLK Core Clock Frequency (VDDINT =1.14 V Minimum) 1.20 V 400 400 MHz
fCCLK Core Clock Frequency (VDDINT =1.045 V Minimum) 1.10 V 333 363 MHz
fCCLK Core Clock Frequency (VDDINT = 0.95 V Minimum) 1.00 V 295 333 MHz
1
2
See Operating Conditions on Page 23.
Table 12. Core Clock Requirements—300 MHz Speed Grade1
Parameter Internal Regulator Setting Max Unit

1
Table 13. Phase-Locked Loop Operating Conditions
Parameter Min Max Unit

fVCO Voltage Controlled Oscillator (VCO) Frequency 50 Speed Grade1 MHz
1
Table 14. System Clock Requirements
Parameter Condition Max Unit

fSCLK1 VDDEXT = 3.3 V or 2.5 V, VDDINT ≥ 1.14 V 1332 MHz
fSCLK1 VDDEXT = 3.3 V or 2.5 V, VDDINT < 1.14 V 100 MHz
1
fSCLK must be less than or equal to fCCLK and is subject to additional restrictions for SDRAM interface operation. See Table 26 on Page 34.
2
Rounded number. Actual test specification is SCLK period of 7.5 ns. See Table 26 on Page 34.

ELECTRICAL CHARACTERISTICS
300 MHz/400 MHz1 500 MHz/533 MHz/600 MHz2

Parameter Test Conditions Min Typ Max Min Typ Max Unit
3
VOH High Level VDDEXT = 2.5 V/3.0 V/ 3.3 V ± VDDEXT – 0.5 VDDEXT – 0.5 V
Output Voltage 10%, IOH = –0.5 mA
VOH4 VDDEXT = 3.3 V ± 10%, VDDEXT – 0.5 VDDEXT – 0.5 V
IOH = –8 mA
VDDEXT = 2.5 V/3.0 V ± 10%, VDDEXT – 0.5 VDDEXT – 0.5 V
IOH = –6 mA
5
VOH VDDEXT = 2.5 V/3.0 V/ 3.3 V ± VDDEXT – 0.5 VDDEXT – 0.5 V
10%, IOH = –2.0 mA
IOH6 High Level VOH = VDDEXT – 0.5 V Min –64 –64 mA
Output Current
IOH7 VOH = VDDEXT – 0.5 V Min –144 –144 mA
VOL3 Low Level VDDEXT = 2.5 V/3.0 V/ 3.3 V ± 0.4 0.4 V

Output Voltage 10%, IOL = 2.0 mA
VOL4 VDDEXT = 3.3 V ± 10%, 0.5 0.5 V
IOL = 8 mA
VDDEXT = 2.5 V/3.0 V ± 10%, 0.5 0.5 V
IOL = 6 mA
VOL5 VDDEXT = 2.5 V/3.0 V/ 3.3 V ± 0.5 0.5 V
10%, IOL = 2.0 mA
IOL6 Low Level VOL = 0.5 V Max 64 64 mA
Output Current
IOL7 VOL = 0.5 V Max 144 144 mA
IIH High Level Input VDDEXT =3.6 V, VIN = 3.6 V 10 10 μA
Current8
IIH5V High Level Input VDDEXT =3.6 V, VIN = 5.5 V 10 10 μA
Current9
IIL Low Level Input VDDEXT =3.6 V, VIN = 0 V 10 10 μA
Current2
IIHP High Level Input VDDEXT = 3.6 V, VIN = 3.6 V 50 50 μA
Current JTAG10
IOZH Three-State VDDEXT = 3.6 V, VIN = 3.6 V 10 10 μA
Leakage
Current11
IOZH5V Three-State VDDEXT =3.6 V, VIN = 5.5 V 10 10 μA
Leakage
Current12
IOZL Three-State VDDEXT = 3.6 V, VIN = 0 V 10 10 μA
Leakage
Current5
CIN Input fIN = 1 MHz, TAMBIENT = 25°C, 8 8 pF
Capacitance13, 14 VIN = 2.5 V

300 MHz/400 MHz1 500 MHz/533 MHz/600 MHz2
Parameter Test Conditions Min Typ Max Min Typ Max Unit
IDDDEEPSLEEP15 VDDINT Current in VDDINT = 1.0 V, fCCLK = 0 MHz, TJ 6 16 mA
Deep Sleep = 25°C, ASF = 0.00
Mode
IDDSLEEP VDDINT Current in VDDINT = 1.0 V, fSCLK = 25 MHz, TJ 9.5 19.5 mA
Sleep Mode = 25°C
IDD-IDLE VDDINT Current in VDDINT = 1.0 V, fCCLK = 50 MHz, TJ 14 24 mA
Idle = 25°C, ASF = 0.43
IDD-TYP VDDINT Current VDDINT = 1.14 V, fCCLK = 300 MHz, 100 113 mA
TJ = 25°C, ASF = 1.00
IDD-TYP VDDINT Current VDDINT = 1.14 V, fCCLK = 400 MHz, 125 138 mA
TJ = 25°C, ASF = 1.00
IDD-TYP VDDINT Current VDDINT = 1.20 V, fCCLK = 533 MHz, 185 mA
TJ = 25°C, ASF = 1.00
IDD-TYP VDDINT Current VDDINT = 1.30 V, fCCLK = 600 MHz, 227 mA
TJ = 25°C, ASF = 1.00
IDDHIBERNATE15, 16 VDDEXT Current in VDDEXT = 3.60 V, CLKIN=0 MHz, 50 100 50 100 μA
Hibernate State TJ = maximum, with voltage
regulator off (VDDINT = 0 V)
IDDRTC VDDRTC Current VDDRTC = 3.3 V, TJ= 25°C 20 20 μA
IDDDEEPSLEEP15 VDDINT Current in fCCLK = 0 MHz, fSCLK = 0 MHz Table 16 Table 15 mA
Deep Sleep
Mode
IDDSLEEP15, 17 VDDINT Current in fCCLK = 0 MHz, fSCLK > 0 MHz IDDDEEPSLEEP + (0.14 × IDDDEEPSLEEP + (0.14 × mA
Sleep Mode VDDINT × fSCLK) VDDINT × fSCLK)
IDDINT18 VDDINT Current fCCLK > 0 MHz, fSCLK > 0 MHz IDDSLEEP + (Table 18 IDDSLEEP + (Table 18 mA
× ASF) × ASF)
1
Applies to all 300 MHz and 400 MHz speed grade models. See Ordering Guide on Page 65.
2
Applies to all 500 MHz, 533 MHz, and 600 MHz speed grade models. See Ordering Guide on Page 65.
3
Applies to all output and bidirectional pins except port F pins, port G pins, and port H pins.
4
Applies to port F pins PF7–0.
5
Applies to port F pins PF15–8, all port G pins, and all port H pins.
6
Maximum combined current for Port F7–0.
7
Maximum total current for all port F, port G, and port H pins.
8
Applies to all input pins except PJ4.
9
Applies to input pin PJ4 only.
10
Applies to JTAG input pins (TCK, TDI, TMS, TRST).
11
Applies to three-statable pins.
12
Applies to bidirectional pins PJ2 and PJ3.
13
Applies to all signal pins.
14
Guaranteed, but not tested.
15
See the ADSP-BF537 Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes.
16
CLKIN must be tied to VDDEXT or GND during hibernate.
17
In the equations, the fSCLK parameter is the system clock in MHz.
18
See Table 17 for the list of IDDINT power vectors covered.

System designers should refer to Estimating Power for the current dissipation for internal circuitry (VDDINT). IDDDEEPSLEEP speci-
ADSP-BF534/BF536/BF537 Blackfin Processors (EE-297), which fies static power dissipation as a function of voltage (VDDINT) and
provides detailed information for optimizing designs for lowest temperature (see Table 16 or Table 15), and IDDINT specifies the
power. All topics discussed in this section are described in detail total power specification for the listed test conditions, including
in EE-297. Total power dissipation has two components: the dynamic component as a function of voltage (VDDINT) and fre-
1. Static, including leakage current quency (Table 18).
2. Dynamic, due to transistor switching characteristics The dynamic component is also subject to an Activity Scaling
Factor (ASF) which represents application code running on the
Many operating conditions can also affect power dissipation, processor (Table 17).
including temperature, voltage, operating frequency, and pro-
cessor activity. Electrical Characteristics on Page 25 shows the
Table 15. Static Current–500 MHz, 533 MHz, and 600 MHz Speed Grade Devices (mA)1
Voltage (VDDINT)
TJ (°C) 0.80 V 0.85 V 0.90 V 0.95 V 1.00 V 1.05 V 1.10 V 1.15 V 1.20 V 1.25 V 1.30 V 1.32 V 1.375 V 1.43 V
–40 3.9 4.7 6.8 8.2 9.9 12.0 14.6 17.3 20.3 24.1 27.1 28.6 36.3 44.4
0 17.0 19.2 21.9 25.0 28.2 32.1 36.9 41.8 47.7 53.8 61.0 63.8 73.2 84.1
25 35.0 39.2 44.3 50.8 56.1 63.3 69.1 76.4 84.7 93.5 104.5 109.1 123.4 138.8
40 53.0 59.2 65.3 71.9 79.1 88.0 96.6 108.0 120.0 130.7 142.6 148.5 166.5 185.6
55 76.7 84.6 93.6 103.1 113.7 123.9 136.3 148.3 162.8 178.4 194.4 201.4 223.7 247.5
70 110.1 120.0 130.9 142.2 156.5 171.3 185.2 201.7 220.6 239.7 259.8 268.8 295.9 325.2
85 150.1 164.5 178.7 193.2 210.4 228.9 247.7 268.8 291.4 314.1 341.1 351.2 384.6 420.3
100 202.3 219.2 236.5 255.8 277.8 299.8 323.8 351.2 378.8 407.5 440.4 453.4 494.3 538.2
105 223.8 241.4 260.4 282.0 303.4 328.7 354.5 381.7 410.8 443.6 477.8 492.2 535.1 581.5
1
Values are guaranteed maximum IDDDEEPSLEEP specifications.
Table 16. Static Current–300 MHz and 400 MHz Speed Grade Devices (mA)1
Voltage (VDDINT)
TJ (°C) 0.80 V 0.85 V 0.90 V 0.95 V 1.00 V 1.05 V 1.10 V 1.15 V 1.20 V 1.25 V 1.30 V 1.32 V
–40 2.6 3.2 3.7 4.5 5.5 6.6 7.9 9.3 10.5 12.5 13.9 14.8
0 6.6 7.8 8.4 9.9 10.9 12.3 13.8 15.5 17.5 19.6 21.7 23.1
25 12.2 13.5 14.8 16.4 18.2 19.9 22.7 25.6 28.4 31.8 35.7 37.2
40 17.2 19.0 20.6 22.9 25.9 28.2 31.6 34.9 38.9 42.9 47.6 49.5
55 25.7 27.8 30.9 33.7 37.3 41.4 44.8 50.0 54.8 59.4 66.1 68.4
70 37.6 41.3 44.8 48.9 53.9 58.6 63.9 69.7 76.9 84.0 92.2 94.9
85 53.7 58.3 63.7 69.0 75.9 82.9 90.5 98.4 106.4 115.3 124.6 128.1
100 75.1 82.3 88.5 95.8 104.0 112.5 121.8 130.6 141.3 153.2 164.8 169.7
105 84.5 91.2 98.2 106.0 114.2 123.0 132.4 143.3 155.0 167.4 179.8 185.4
1152 103.8 111.8 120.3 127.6 138.0 148.5 159.6 171.4 184.6 198.8 213.4 219.6
1202 115.5 123.6 132.2 141.9 152.3 163.7 175.6 189.3 202.8 217.7 232.3 238.6
1
Values are guaranteed maximum IDDDEEPSLEEP specifications.
2
Applies to automotive grade models only.

Table 17. Activity Scaling Factors
IDDINT Power Vector1 Activity Scaling Factor (ASF)2

IDD-PEAK 1.33
IDD-HIGH 1.29
IDD-TYP 1.00
IDD-APP 0.88
IDD-NOP 0.72
IDD-IDLE 0.43
1
See EE-297 for power vector definitions.
2
All ASF values determined using a 10:1 CCLK:SCLK ratio.
Table 18. Dynamic Current (mA, with ASF = 1.0)1
Voltage (VDDINT)
Frequency
(MHz) 0.80 V 0.85 V 0.90 V 0.95 V 1.00 V 1.05 V 1.10 V 1.15 V 1.20 V 1.25 V 1.30 V 1.32 V 1.375 V 1.43 V
50 11.0 13.7 19.13 18.2 18.67 19.13 19.6 21.2 24.1 25.5 28.5 28.6 28.85 29.2
100 27.9 22.7 30.8 28.4 29.3 30.8 32.9 35.3 37.8 40.6 43.5 43.7 44.1 45.8
200 36.9 42.6 55.0 49.2 51.5 55.0 58.3 62.9 67.0 69.7 73.0 74.0 75.7 80.7
300 N/A 61.5 79.2 70.4 74.6 79.2 84.4 90.7 94.3 99.1 103.9 105.5 108.0 113.4
400 N/A N/A N/A 92.4 97.2 104.3 109.8 116.5 121.9 128.0 134.6 136.6 139.8 145.1
500 N/A N/A N/A N/A N/A N/A N/A 142.3 149.3 157.5 164.7 166.7 169.8 176.9
533 N/A N/A N/A N/A N/A N/A N/A N/A 158.6 167.0 174.3 176.6 180.1 187.9
600 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 193.7 196.5 200.7 210.0
1
The values are not guaranteed as stand-alone maximum specifications, they must be combined with static current per the equations of Electrical Characteristics on Page 25.

ABSOLUTE MAXIMUM RATINGS PACKAGE INFORMATION
Stresses greater than those listed in Table 19 may cause perma- The information presented in Figure 8 and Table 21 provide
nent damage to the device. These are stress ratings only. details about the package branding for the Blackfin processors.
Functional operation of the device at these or any other condi- For a complete listing of product availability, see Ordering
tions greater than those indicated in the operational sections of Guide on Page 65.
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
a
Table 19. Absolute Maximum Ratings ADSP-BF5xx
tppZccc
Parameter Rating
vvvvvv.x n.n
Internal (Core) Supply Voltage (VDDINT) –0.3 V to +1.43 V
#yyww country_of_origin
External (I/O) Supply Voltage (VDDEXT) –0.3 V to +3.8 V
B
Input Voltage1 –0.5 V to +3.6 V
Input Voltage1, 2 –0.5 V to +5.5 V
Figure 8. Product Information on Package
Output Voltage Swing –0.5 V to VDDEXT + 0.5 V
Load Capacitance3 200 pF Table 21. Package Brand Information
Storage Temperature Range –65°C to +150°C
Brand Key Field Description
Junction Temperature Underbias +125°C
1
t Temperature Range
Applies only when VDDEXT is within specifications. When VDDEXT is outside specifi-
cations, the range is VDDEXT ± 0.2 V. pp Package Type
2
Applies to 5 V tolerant pins SCL, SDA, and PJ4. For duty cycles, see Table 20. Z RoHS Compliant Designation
3
For proper SDRAM controller operation, the maximum load capacitance is 50 pF
(at 3.3 V) or 30 pF (at 2.5 V) for ADDR19–1, DATA15–0, ABE1–0/SDQM1–0, ccc See Ordering Guide
CLKOUT, SCKE, SA10, SRAS, SCAS, SWE, and SMS. vvvvvv.x Assembly Lot Code
n.n Silicon Revision
Table 20. Maximum Duty Cycle for Input1 Transient Voltage # RoHS Compliant Designation
VIN Min (V) VIN Max (V)2 Maximum Duty Cycle yyww Date Code
–0.50 +3.80 100%
–0.70 +4.00 40%
–0.80 +4.10 25%
–0.90 +4.20 15%
–1.00 +4.30 10%
1
Applies to all signal pins with the exception of CLKIN, XTAL, and VROUT1–0.
2
Only one of the listed options can apply to a particular design.
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.

TIMING SPECIFICATIONS
Clock and Reset Timing
Table 22. Clock Input and Reset Timing

Timing Requirements
tCKIN CLKIN Period1, 2, 3, 4 20.0 100.0 ns
tCKINL CLKIN Low Pulse 8.0 ns
tCKINH CLKIN High Pulse 8.0 ns
tBUFDLAY CLKIN to CLKBUF Delay 10 ns
tWRST RESET Asserted Pulse Width Low5 11 tCKIN ns
tNOBOOT RESET Deassertion to First External Access Delay6 3 tCKIN 5 tCKIN ns
1
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 10 through Table 14. Since
by default the PLL is multiplying the CLKIN frequency by 10, 300 MHz and 400 MHz speed grade parts can not use the full CLKIN period range.
2
Applies to PLL bypass mode and PLL non bypass mode.
3
CLKIN frequency must not change on the fly.
4
If the DF bit in the PLL_CTL register is set, then the maximum tCKIN period is 50 ns.
5
Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET is asserted,
assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).
6
Applies when processor is configured in No Boot Mode (BMODE2-0 = b#000).
t CKIN
CLKIN
t CKINL t CKINH
t
t BUFDLAY BUFDLAY
CLKBUF
t WRST
RESET
t NOBOOT
AOE
Figure 9. Clock and Reset Timing

Asynchronous Memory Read Cycle Timing
Table 23. Asynchronous Memory Read Cycle Timing

Timing Requirements
tSDAT DATA15–0 Setup Before CLKOUT 2.1 ns
tHDAT DATA15–0 Hold After CLKOUT 0.8 ns
tSARDY ARDY Setup Before CLKOUT 4.0 ns
tHARDY ARDY Hold After CLKOUT 0.0 ns
Switching Characteristics
tDO Output Delay After CLKOUT1 6.0 ns
tHO Output Hold After CLKOUT 1 0.8 ns
1
Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
HOLD
1 CYCLE
SETUP PROGRAMMED READ ACCESS ACCESS EXTENDED
2 CYCLES 4 CYCLES 3 CYCLES
CLKOUT
tDO tHO
AMSx
ABE1–0
BE, ADDRESS
ADDR19–1
AOE
tDO
tHO
ARE
tHARDY
tSARDY tHARDY
ARDY
tSARDY tSDAT
tHDAT
DATA15–0 READ
Figure 10. Asynchronous Memory Read Cycle Timing

Asynchronous Memory Write Cycle Timing
Table 24. Asynchronous Memory Write Cycle Timing

Timing Requirements
tSARDY ARDY Setup Before CLKOUT 4.0 ns
tHARDY ARDY Hold After CLKOUT 0.0 ns
tDDAT DATA15–0 Disable After CLKOUT 6.0 ns
tENDAT DATA15–0 Enable After CLKOUT 1.0 ns
tDO Output Delay After CLKOUT1 6.0 ns
tHO Output Hold After CLKOUT 1 0.8 ns
1
Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, AWE.
ACCESS
SETUP PROGRAMMED WRITE EXTENDED HOLD
2 CYCLES ACCESS 2 CYCLES 1 CYCLE 1 CYCLE
CLKOUT
t DO t HO
AMSx
ABE1–0
BE, ADDRESS
ADDR19–1
tDO
tHO
AWE
t SARDY t HARDY
ARDY
tSARDY
t ENDAT t DDAT
DATA15–0 WRITE DATA
Figure 11. Asynchronous Memory Write Cycle Timing

External Port Bus Request and Grant Cycle Timing
Table 25 and Figure 12 describe external port bus request and
bus grant operations.
Table 25. External Port Bus Request and Grant Cycle Timing
Parameter1, 2 Min Max Unit

Timing Requirements
tBS BR Asserted to CLKOUT Low Setup 4.6 ns
tBH CLKOUT Low to BR Deasserted Hold Time 0.0 ns
tSD CLKOUT Low to AMSx, Address, and ARE/AWE Disable 4.5 ns
tSE CLKOUT Low to AMSx, Address, and ARE/AWE Enable 4.5 ns
tDBG CLKOUT High to BG Asserted Setup 3.6 ns
tEBG CLKOUT High to BG Deasserted Hold Time 3.6 ns
tDBH CLKOUT High to BGH Asserted Setup 3.6 ns
tEBH CLKOUT High to BGH Deasserted Hold Time 3.6 ns
1
These timing parameters are based on worst-case operating conditions.
2
The pad loads for these timing parameters are 20 pF.
CLKOUT
tBS tBH
BR
tSD
tSE
AMSx
tSD
tSE
ADDR19-1
ABE1-0
tSD
tSE
AWE
ARE
tDBG
tEBG
BG
tDBH
tEBH
BGH
Figure 12. External Port Bus Request and Grant Cycle Timing

SDRAM Interface Timing
Table 26. SDRAM Interface Timing

Timing Requirements
tSSDAT DATA15–0 Setup Before CLKOUT 1.5 ns
tHSDAT DATA15–0 Hold After CLKOUT 0.8 ns
tDCAD COMMAND1, ADDR19–1, DATA15–0 Delay After CLKOUT 4.0 ns
tHCAD COMMAND1, ADDR19–1, DATA15–0 Hold After CLKOUT 1.0 ns
tDSDAT DATA15–0 Disable After CLKOUT 6.0 ns
tENSDAT DATA15–0 Enable After CLKOUT 0.5 ns
tSCLK2 CLKOUT Period when TJ ≤ +105°C 7.5 ns
tSCLK 2
CLKOUT Period when TJ > +105°C 10 ns
tSCLKH CLKOUT Width High 2.5 ns
tSCLKL CLKOUT Width Low 2.5 ns
1
Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
2
These limits are specific to the SDRAM interface only. In addition, CLKOUT must always comply with the limits in Table 14 on Page 24.
tSCLK tSCLKH
CLKOUT
tSSDAT
tSCLKL
tHSDAT
DATA15-0 (IN)
tDCAD tDSDAT
tENSDAT tHCAD
DATA15-0 (OUT)
tDCAD
COMMAND ADDR19-1
(OUT)
tHCAD
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 13. SDRAM Interface Timing

External DMA Request Timing
Table 27 and Figure 14 describe the external DMA request
operations.
Table 27. External DMA Request Timing

Timing Requirements
tDR DMARx Asserted to CLKOUT High Setup 6.0 ns
tDH CLKOUT High to DMARx Deasserted Hold Time 0.0 ns
tDMARACT DMARx Active Pulse Width 1.0 × tSCLK ns
tDMARINACT DMARx Inactive Pulse Width 1.75 × tSCLK ns
CLKOUT
tDR tDH
DMAR0/1
tDMARACT tDMARINACT
(ACTIVE LOW)
DMAR0/1 tDMARACT tDMARINACT

(ACTIVE HIGH)
Figure 14. External DMA Request Timing

Parallel Peripheral Interface Timing
Table 28 and Figure 15 on Page 36, Figure 19 on Page 40, and
Figure 20 on Page 41 describe parallel peripheral interface
operations.
Table 28. Parallel Peripheral Interface Timing

Timing Requirements
tPCLKW PPI_CLK Width1 6.0 ns
tPCLK PPI_CLK Period1 15.0 ns
Timing Requirements—GP Input and Frame Capture Modes
tSFSPE External Frame Sync Setup Before PPI_CLK 6.7 ns
(Nonsampling Edge for Rx, Sampling Edge for Tx)
tHFSPE External Frame Sync Hold After PPI_CLK 1.0 ns
tSDRPE Receive Data Setup Before PPI_CLK 3.5 ns
tHDRPE Receive Data Hold After PPI_CLK 1.5 ns
Switching Characteristics—GP Output and Frame Capture Modes
tDFSPE Internal Frame Sync Delay After PPI_CLK 8.0 ns
tHOFSPE Internal Frame Sync Hold After PPI_CLK 1.7 ns
tDDTPE Transmit Data Delay After PPI_CLK 8.0 ns
tHDTPE Transmit Data Hold After PPI_CLK 1.8 ns
1
PPI_CLK frequency cannot exceed fSCLK/2.
FRAME
SYNC IS DATA0
DRIVEN IS
OUT SAMPLED
POLC = 0
PPI_CLK
PPI_CLK
POLC = 1
t
DFSPE
tHOFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
tSDRPE tHDRPE
PPI_DATA
Figure 15. PPI GP Rx Mode with Internal Frame Sync Timing

DATA0 IS DATA1 IS
SAMPLED SAMPLED
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
tSFSPE tHFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
tSDRPE tHDRPE
PPI_DATA
Figure 16. PPI GP Rx Mode with External Frame Sync Timing
FRAME
SYNC IS
DRIVEN DATA0 IS
OUT DRIVEN
OUT
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
t
DFSPE
t
HOFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
t
DDTPE
t
HDTPE
PPI_DATA DATA0
Figure 17. PPI GP Tx Mode with Internal Frame Sync Timing

DATA DATA
DRIVING/ DRIVING/
FRAME FRAME
SYNC SYNC
SAMPLING SAMPLING
EDGE EDGE
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
tHFSPE
tSFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
tDDTPE
t
HDTPE
PPI_DATA
Figure 18. PPI GP Tx Mode with External Frame Sync Timing

Serial Ports
Table 29 through Table 32 on Page 40 and Figure 19 on Page 40
through Figure 20 on Page 41 describe serial port operations.
Table 29. Serial Ports—External Clock

Timing Requirements
tSFSE TFSx/RFSx Setup Before TSCLKx/RSCLKx1 3.0 ns
tHFSE TFSx/RFSx Hold After TSCLKx/RSCLKx1 3.0 ns
tSDRE Receive Data Setup Before RSCLKx1 3.0 ns
tSCLKEW TSCLKx/RSCLKx Width 4.5 4.5
tSCLKE TSCLKx/RSCLKx Period 15.0 15.0
tDFSE TFSx/RFSx Delay After TSCLKx/RSCLK (Internally Generated TFSx/RFSx)2 10.0 ns
tHOFSE TFSx/RFSx Hold After TSCLKx/RSCLK (Internally Generated TFSx/RFSx)2 0 ns
tDDTE Transmit Data Delay After TSCLKx2 10.0 ns
tHDTE Transmit Data Hold After TSCLKx2 0 ns
1
Referenced to sample edge.
2
Referenced to drive edge.
Table 30. Serial Ports—Internal Clock
2.25 V ≤ VDDEXT < 2.70 V 2.70 V ≤ VDDEXT ≤ 3.60 V

or and
0.80 V ≤ VDDINT < 0.95 V1 0.95 V ≤ VDDINT ≤ 1.43 V2, 3
Parameter Min Max Min Max Unit
Timing Requirements
tSFSI TFSx/RFSx Setup Before TSCLKx/RSCLKx4 8.5 8.0 ns
tHFSI TFSx/RFSx Hold After TSCLKx/RSCLKx4 –1.5 –1.5 ns
tSDRI Receive Data Setup Before RSCLKx4 8.5 8.0 ns
tHDRI Receive Data Hold After RSCLKx4 –1.5 –1.5 ns
tDFSI TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated 3.0 3.0 ns
TFSx/RFSx)5
tHOFSI TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated −1.0 −1.0 ns
TFSx/RFSx)5
tDDTI Transmit Data Delay After TSCLKx5 3.0 3.0 ns
tHDTI Transmit Data Hold After TSCLKx5 −1.0 −1.0 ns
tSCLKIW TSCLKx/RSCLKx Width 4.5 4.5 ns
1
Applies to all non automotive-grade devices when operated within either of these voltage ranges.
2
Applies to all non automotive-grade devices when operated within these voltage ranges.
3
All automotive-grade devices are within these specifications.
4
Referenced to sample edge.
5

Table 31. Serial Ports—Enable and Three-State

tDTENE Data Enable Delay from External TSCLKx1 0 ns
tDDTTE Data Disable Delay from External TSCLKx1 10.0 ns
tDTENI Data Enable Delay from Internal TSCLKx1 –2.0 ns
tDDTTI Data Disable Delay from Internal TSCLKx1 3.0 ns
1
Table 32. External Late Frame Sync

tDDTLFSE Data Delay from Late External TFSx or External RFSx with MCE = 1, MFD = 01, 2 10.0 ns
tDTENLFS Data Enable from Late FS or MCE = 1, MFD = 01, 2 0 ns
1
MCE = 1, TFSx enable and TFSx valid follow tDDTENFS and tDDTLFS.
2
If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2, then tDDTE/I and tDTENE/I apply, otherwise tDDTLFSE and tDTENLFS apply.
DATA RECEIVE—INTERNAL CLOCK DATA RECEIVE—EXTERNAL CLOCK

DRIVE SAMPLE DRIVE SAMPLE
EDGE EDGE EDGE EDGE
tSCLKIW tSCLKEW
RSCLKx RSCLKx
tDFSI tDFSE
tHOFSI tSFSI tHFSI tHOFSE tSFSE tHFSE
RFSx RFSx
tSDRI tHDRI tSDRE tHDRE
DRx DRx
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT—INTERNAL CLOCK DATA TRANSMIT—EXTERNAL CLOCK

DRIVE SAMPLE DRIVE SAMPLE
EDGE EDGE EDGE EDGE
tSCLKIW tSCLKEW
TSCLKx TSCLKx
tDFSI tDFSE
tHOFSI tSFSI tHFSI tHOFSE tSFSE tHFSE
TFSx TFSx
tDDTI tDDTE
tHDTI tHDTE
DTx DTx
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.
Figure 19. Serial Ports

EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE SAMPLE DRIVE
RSCLKx
tSFSE/I tHOFSE/I
RFSx
tDDTTE/I
tDTENLFS
tDTENE/
I
DTx 1ST BIT 2ND BIT
tDDTLFSE
LATE EXTERNAL TFS
DRIVE SAMPLE DRIVE
TSCLKx tHOFSE/I
tSFSE/I
TFSx
tDDTTE/I
tDTENLFS
tDTENE/I
1ST BIT 2ND BIT

DTx
tDDTLFSE
Figure 20. External Late Frame Sync

Serial Peripheral Interface Port—Master Timing
Table 33 and Figure 21 describe SPI port master operations.
Table 33. Serial Peripheral Interface (SPI) Port—Master Timing

or and
Timing Requirements
tSSPIDM Data Input Valid to SCK Edge (Data Input Setup) 8.7 7.5 ns
tHSPIDM SCK Sampling Edge to Data Input Invalid –1.5 –1.5 ns
tSDSCIM SPISELx Low to First SCK Edge 2 × tSCLK –1.5 2 × tSCLK –1.5 ns
tSPICHM Serial Clock High Period 2 × tSCLK –1.5 2 × tSCLK –1.5 ns
tSPICLM Serial Clock Low Period 2 × tSCLK –1.5 2 × tSCLK –1.5 ns
tSPICLK Serial Clock Period 4 × tSCLK –1.5 4 × tSCLK –1.5 ns
tHDSM Last SCK Edge to SPISELx High 2 × tSCLK –1.5 2 × tSCLK –1.5 ns
tSPITDM Sequential Transfer Delay 2 × tSCLK –1.5 2 × tSCLK –1.5 ns
tDDSPIDM SCK Edge to Data Out Valid (Data Out Delay) 6 6 ns
tHDSPIDM SCK Edge to Data Out Invalid (Data Out Hold) –1.0 –1.0 ns
1
2
3
SPIxSELy
(OUTPUT)
tSDSCIM tSPICHM tSPICLM tSPICLK tHDSM tSPITDM
SCKx
(CPOL = 0)
(OUTPUT)
tSPICLM tSPICHM
SCKx
(CPOL = 1)
(OUTPUT)
tHDSPIDM tDDSPIDM
MOSIx
MSB LSB
(OUTPUT)
CPHA=1 tHSPIDM
tSSPIDM
MISOx MSB LSB

(INPUT) VALID VALID
tHDSPIDM tDDSPIDM
MOSIx
MSB LSB
(OUTPUT)
CPHA=0 tHSPIDM
tSSPIDM
MISOx MSB LSB

(INPUT) VALID VALID
Figure 21. Serial Peripheral Interface (SPI) Port—Master Timing

Serial Peripheral Interface Port—Slave Timing
Table 34 and Figure 22 describe SPI port slave operations.
Table 34. Serial Peripheral Interface (SPI) Port—Slave Timing

Timing Requirements
tSPICHS Serial Clock High Period 2 × tSCLK –1.5 ns
tSPICLS Serial Clock Low Period 2 × tSCLK –1.5 ns
tSPICLK Serial Clock Period 4 × tSCLK ns
tHDS Last SCK Edge to SPISS Not Asserted 2 × tSCLK –1.5 ns
tSPITDS Sequential Transfer Delay 2 × tSCLK –1.5 ns
tSDSCI SPISS Assertion to First SCK Edge 2 × tSCLK –1.5 ns
tSSPID Data Input Valid to SCK Edge (Data Input Setup) 1.6 ns
tHSPID SCK Sampling Edge to Data Input Invalid 1.6 ns
tDSOE SPISS Assertion to Data Out Active 0 8 ns
tDSDHI SPISS Deassertion to Data High Impedance 0 8 ns
tDDSPID SCK Edge to Data Out Valid (Data Out Delay) 10 ns
tHDSPID SCK Edge to Data Out Invalid (Data Out Hold) 0 ns
SPIxSS
(INPUT)
tSPICHS tSPICLS tSPICLK tHDS tSPITDS

SCKx
(CPOL = 0)
(INPUT)
tSDSCI tSPICLS tSPICHS
SCKx
(CPOL = 1)
(INPUT)
tDDSPID
tDSOE tHDSPID tDDSPID tDSDHI
MISOx
MSB LSB
(OUTPUT)
CPHA=1 tHSPID
tSSPID
MOSIx MSB LSB

(INPUT) VALID VALID
tDSOE tHDSPID tDDSPID tHDSPID tDSDHI
MISOx
MSB LSB
(OUTPUT)
tHSPID
CPHA=0
tSSPID
MOSIx MSB LSB

(INPUT) VALID VALID
Figure 22. Serial Peripheral Interface (SPI) Port—Slave Timing

Universal Asynchronous Receiver-Transmitter
(UART) Ports—Receive and Transmit Timing
Figure 23 describes the UART ports receive and transmit opera- internal UART interrupts and the external data operations.
tions. The maximum baud rate is SCLK/16. As shown in These latencies are negligible at the data transmission rates for
Figure 23 there is some latency between the generation of the UART.
CLK OUT
(SAMPLE CLOCK )
Rx DATA (5–8)
STOP
RECEIVE
INTERNAL
UART RECEIVE UART RECEIVE BIT SET BY DATA STOP;
INTERRUPT CLEARED BY FIFO READ
START
Tx
DATA (5–8) STOP (1ñ2)
TRANSMIT
INTERNAL UART TRANSMIT BIT SET BY PROGRAM;

UART TRANSMIT CLEARED BY WRITE TO TRANSMIT
INTERRUPT
Figure 23. UART Ports—Receive and Transmit Timing

General-Purpose Port Timing
Table 35 and Figure 24 describe general-purpose
port operations.
Table 35. General-Purpose Port Timing

Timing Requirement
tWFI General-Purpose Port Pin Input Pulse Width tSCLK + 1 ns
Switching Characteristic
tGPOD General-Purpose Port Pin Output Delay from CLKOUT Low 0 6 ns
CLKOUT
tGPOD
GPP OUTPUT
tWFI
GPP INPUT
Figure 24. General-Purpose Port Timing
Timer Clock Timing

Table 36 and Figure 25 describe timer clock timing.
Table 36. Timer Clock Timing

Switching Characteristic
tTODP Timer Output Update Delay After PPI_CLK High 12 ns
PPI CLOCK
tTODP
TIMER OUTPUT
Figure 25. Timer Clock Timing

Timer Cycle Timing
Table 37 and Figure 26 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of (fSCLK/2) MHz.
Table 37. Timer Cycle Timing

or and
Timing Characteristics
tWL Timer Pulse Width Input Low (Measured In SCLK Cycles)4 1 × tSCLK 1 × tSCLK ns
tWH Timer Pulse Width Input High (Measured In SCLK Cycles)4 1 × tSCLK 1 × tSCLK ns
tTIS Timer Input Setup Time Before CLKOUT Low5 5.5 5.0 ns
tTIH Timer Input Hold Time After CLKOUT Low5 –2 –2 ns
tHTO Timer Pulse Width Output (Measured In SCLK Cycles) 1 × tSCLK (232–1) × tSCLK 1 × tSCLK (232–1) × tSCLK ns
tTOD Timer Output Update Delay After CLKOUT High 6.5 6.0 ns
1
2
3
4
The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode.
5
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
CLKOUT
tTOD
TIMER OUTPUT
tHTO
tTIS tTIH
TIMER INPUT
tWH, tWL
Figure 26. Timer Cycle Timing

JTAG Test and Emulation Port Timing
Table 38 and Figure 27 describe JTAG port operations.
Table 38. JTAG Port Timing

Timing Parameters
tTCK TCK Period 20 ns
tSTAP TDI, TMS Setup Before TCK High 4 ns
tHTAP TDI, TMS Hold After TCK High 4 ns
tSSYS System Inputs Setup Before TCK High1 4 ns
tHSYS System Inputs Hold After TCK High1 5 ns
tTRSTW TRST Pulse Width2 (Measured in TCK Cycles) 4 TCK
tDTDO TDO Delay From TCK Low 10 ns
tDSYS System Outputs Delay After TCK Low3 0 12 ns
1
System Inputs = DATA15–0, BR, ARDY, SCL, SDA, TFS0, TSCLK0, RSCLK0, RFS0, DR0PRI, DR0SEC, PF15–0, PG15–0, PH15–0, MDIO, TCK, TRST, RESET, NMI, RTXI,
BMODE2–0.
2
50 MHz maximum
3
System Outputs = DATA15–0, ADDR19–1, ABE1–0, BG, BGH, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, MDC, MDIO,
TSCLK0, TFS0, RFS0, RSCLK0, DT0PRI, DT0SEC, PF15–0, PG15–0, PH15–0, RTXO, TDO, EMU, XTAL, VROUT1–0.
tTCK
TCK
tSTAP tHTAP
TMS
TDI
tDTDO
TDO
tSSYS tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 27. JTAG Port Timing

10/100 Ethernet MAC Controller Timing
Table 39 through Table 44 and Figure 28 through Figure 33
describe the 10/100 Ethernet MAC controller operations. This
feature is only available on the ADSP-BF536 and ADSP-BF537
processors.
Table 39. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
Parameter1 Min Max Unit

fERXCLK ERxCLK Frequency (fSCLK = SCLK Frequency) None 25 + 1% MHz
fSCLK + 1%
tERXCLKW ERxCLK Width (tERxCLK = ERxCLK Period) tERxCLK × 35% tERxCLK × 65% ns
tERXCLKIS Rx Input Valid to ERxCLK Rising Edge (Data In Setup) 7.5 ns
tERXCLKIH ERxCLK Rising Edge to Rx Input Invalid (Data In Hold) 7.5 ns
1
MII inputs synchronous to ERxCLK are ERxD3–0, ERxDV, and ERxER.
Table 40. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal

fETXCLK ETxCLK Frequency (fSCLK = SCLK Frequency) None 25 + 1% MHz
fSCLK + 1%
tETXCLKW ETxCLK Width (tETXCLK = ETxCLK Period) tETxCLK × 35% tETxCLK × 65% ns
tETXCLKOV ETxCLK Rising Edge to Tx Output Valid (Data Out Valid) 20 ns
tETXCLKOH ETxCLK Rising Edge to Tx Output Invalid (Data Out Hold) 0 ns
1
MII outputs synchronous to ETxCLK are ETxD3–0.
Table 41. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal

fREFCLK REF_CLK Frequency (fSCLK = SCLK Frequency) None 50 + 1% MHz
2 × fSCLK + 1%
tREFCLKW REF_CLK Width (tREFCLK = REFCLK Period) tREFCLK × 35% tREFCLK × 65% ns
tREFCLKIS Rx Input Valid to RMII REF_CLK Rising Edge (Data In Setup) 4 ns
tREFCLKIH RMII REF_CLK Rising Edge to Rx Input Invalid (Data In Hold) 2 ns
1
RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER.
Table 42. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal

tREFCLKOV RMII REF_CLK Rising Edge to Tx Output Valid (Data Out Valid) 7.5 ns
tREFCLKOH RMII REF_CLK Rising Edge to Tx Output Invalid (Data Out Hold) 2 ns
1
RMII outputs synchronous to RMII REF_CLK are ETxD1–0.

Table 43. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal
Parameter1, 2 Min Max Unit

tECOLH COL Pulse Width High tETxCLK × 1.5 ns
tERxCLK × 1.5 ns
tECOLL COL Pulse Width Low tETxCLK × 1.5 ns
tERxCLK × 1.5 ns
tECRSH CRS Pulse Width High tETxCLK × 1.5 ns
tECRSL CRS Pulse Width Low tETxCLK × 1.5 ns
1
MII/RMII asynchronous signals are COL, CRS. These signals are applicable in both MII and RMII modes. The asynchronous COL input is synchronized separately to both
the ETxCLK and the ERxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of the slower of the two clocks.
2
The asynchronous CRS input is synchronized to the ETxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of ETxCLK.
Table 44. 10/100 Ethernet MAC Controller Timing: MII Station Management

tMDIOS MDIO Input Valid to MDC Rising Edge (Setup) 10 ns
tMDCIH MDC Rising Edge to MDIO Input Invalid (Hold) 10 ns
tMDCOV MDC Falling Edge to MDIO Output Valid 25 ns
tMDCOH MDC Falling Edge to MDIO Output Invalid (Hold) –1 ns
1
MDC/MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. MDC is an output clock whose minimum period is programmable as a multiple
of the system clock SCLK. MDIO is a bidirectional data line.
tERXCLK
ERxCLK
tERXCLKW
ERxD3- 0
ERxDV
ERxER
tERXCLKIS tERXCLKIH
Figure 28. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
tETXCLK
MII TxCLK tETXCLKW
tETXCLKOH
ETxD3-0
ETxEN
tETXCLKOV
Figure 29. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal

tREFCLK
RMII_REF_CLK tREFCLKW
ERxD1-0
ERxDV
ERxER
tREFCLKIS tREFCLKIH
Figure 30. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
tREFCLK
RMII REF_CLK
tREFCLKOH
ETxD1-0
ETxEN
tREFCLKOV
Figure 31. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
MII CRS, COL
tECRSH tECRSL
tECOLH tECOLL
Figure 32. 10/100 Ethernet MAC Controller Timing: Asynchronous Signal
MDC (OUTPUT)
tMDCOH
MDIO (OUTPUT)
tMDCOV
MDIO (INPUT)
tMDIOS tMDCIH
Figure 33. 10/100 Ethernet MAC Controller Timing: MII Station Management

OUTPUT DRIVE CURRENTS
Figure 34 through Figure 45 show typical current-voltage char-
150
acteristics for the output drivers of the processors. The curves
VD D EX T = 2. 25V @ 95°C
represent the current drive capability of the output drivers as a V DD E XT = 2.50V @ 25° C
100
function of output voltage. See Table 9 on Page 19 for informa- VD DE XT = 2.75V @ -40°C
tion about which driver type corresponds to a particular pin.
SOURCE CURRENT (mA)

50
V OH
120 0
V D DE XT = 2.25V @ 95°C
100
V D DE XT = 2.50V @ 25°C
80 -50
V D DE XT = 2.75V @ -40°C
SOURCE CURRENT (mA)
60 V OL
V OH -100
40
20
-150
0 0 0.5 1.0 1.5 2.0 2. 5 3.0
-20 SOURCE VOLTAGE (V)

-40
V OL
-60
Figure 36. Drive Current B (Low VDDEXT)
-80
-100
200
0 0.5 1.0 1.5 2.0 2.5 3.0
V DD E XT = 3.0V @ 95°C
SOURCE VOL TAGE (V) 150
V DD E XT = 3.3V @ 25°C
VD D EX T = 3.6V @ - 40°C
100
Figure 34. Drive Current A (Low VDDEXT)
SOURCE CURRENT (mA)
VO H
50
150 0
VD D EX T = 3.0V @ 95°C
-50
VD D EX T = 3.3V @ 25°C
100
VD D EX T = 3.6V @ -40°C
-100
SOURCE CURRENT (mA)
VOL
50
-150
VO H
0 -200
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
SOURCE VOLTAGE (V)
-50
VOL
Figure 37. Drive Current B (High VDDEXT)
-100
-150 80
0 0. 5 1.0 1.5 2.0 2.5 3. 0 3.5 4.0
VD D EXT = 2.25V @ 95°C
SOURCE VOLTAGE (V) 60 VD D EXT = 2.50V @ 25°C
VD D EX T = 2.75V @ -40°C
Figure 35. Drive Current A (High VDDEXT) 40
SOURCE CURRENT (mA)
V OH
20
-20
VOL
-40
-60
0 0.5 1.0 1.5 2.0 2. 5 3.0
SOURCE VOLTAGE (V)
Figure 38. Drive Current C (Low VDDEXT)

100 50
VD D EX T = 3.0V @ 95° C VD D EX T = 2.25V @ 95° C
80 40
VD D EX T = 3.3V @ 25° C VD D EX T = 2.50V @ 25° C
V DD E XT = 3.6V @ -40°C 30 VD D EX T = 2.75V @ - 40°C
60
SOURCE CURRENT (mA)

SOURCE CURRENT (mA)
20
40
VOH VOH
10
20
0
0
-10
-20
-20
-40 -30
VO L V OL
-60 -40
-80 -50
0 0. 5 1.0 1.5 2.0 2.5 3. 0 3.5 4.0 0 0.5 1.0 1.5 2.0 2.5 3.0
SOURCE VOLTAGE (V) SOURCE VOL TAGE (V)
Figure 39. Drive Current C (High VDDEXT) Figure 42. Drive Current E (Low VDDEXT)
100 80
V D DE XT = 2.25V @ 95°C
80 60 VD D EX T = 3. 0V @ 95°C
V D DE XT = 2.50V @ 25°C
VD D EX T = 3. 3V @ 25°C
VD D E XT = 2.75V @ -40°C
60 V DD E XT = 3.6V @ -40°C
40
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
40
20
VOH
20 VO H
0
0
-20
-20
-40
-40
VOL
V OL
-60 -60
-80 -80
0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
SOURCE VOLTAGE (V) SOURCE VOLTAGE (V)
Figure 40. Drive Current D (Low VDDEXT) Figure 43. Drive Current E (High VDDEXT)
150 0
V D DE XT = 3.0V @ 95° C
V DD E XT = 2.25V @ 95°C
V D DE XT = 3.3V @ 25° C V DD E XT = 2.50V @ 25°C
100 - 10
V DD E XT = 3.6V @ -40°C VD D EX T = 2.75V @ -40° C
SOURCE CURRENT (mA)
50
SOURCE CURRENT (mA)
- 20
VOH
0 - 30
V OL
-50 - 40
V OL
-100 - 50
-150 - 60
0 0. 5 1.0 1.5 2.0 2.5 3. 0 3.5 4.0 0 0.5 1.0 1.5 2.0 2.5 3.0
SOURCE VOLTAGE (V) SOURCE VOLTAGE (V)
Figure 41. Drive Current D (High VDDEXT) Figure 44. Drive Current F (Low VDDEXT)

Output Disable Time
0
Output pins are considered to be disabled when they stop driv-
VD D EX T = 3.0V @ 95°C
-10
VD D EX T = 3.3V @ 25°C
ing, go into a high impedance state, and start to decay from their
-20
V D D EXT = 3.6V @ -40°C output high or low voltage. The time for the voltage on the bus
to decay by ΔV is dependent on the capacitive load, CL, and the
SOURCE CURRENT (mA)
-30 load current, IL. This decay time can be approximated by

the equation:
-40
VOL
-50 t DECAY = ( C L ΔV ) ⁄ I L
-60
The output disable time tDIS is the difference between
-70
tDIS_MEASURED and tDECAY as shown in Figure 47. The time
-80 tDIS_MEASURED is the interval from when the reference signal
0 0. 5 1.0 1.5 2.0 2.5 3. 0 3.5 4.0
switches to when the output voltage decays ΔV from the mea-
SOURCE VOLTAGE (V) sured output-high or output-low voltage. The time tDECAY is
calculated with the test loads CL and IL, and with ΔV
Figure 45. Drive Current F (High VDDEXT) equal to 0.5 V.
TEST CONDITIONS
All timing parameters appearing in this data sheet were REFERENCE
measured under the conditions described in this section. SIGNAL
Figure 46 shows the measurement point for ac measurements

tDIS_MEASURED tENA_MEASURED
(other than output enable/disable). The measurement point is
tDIS tENA
VMEAS = VDDEXT/2.
VOH VOH(MEASURED)
(MEASURED) VOH (MEASURED) ⴚ ⌬V VTRIP (HIGH)
VOL (MEASURED) + ⌬V VTRIP (LOW)
VOL
INPUT VOL (MEASURED)
OR VMEAS VMEAS (MEASURED)
OUTPUT tDECAY tTRIP
OUTPUT STOPS DRIVING OUTPUT STARTS DRIVING

Figure 46. Voltage Reference Levels for AC Measurements (Except
HIGH IMPEDANCE STATE
Output Enable/Disable)
Figure 47. Output Enable/Disable

Output Enable Time
Output pins are considered to be enabled when they have made Example System Hold Time Calculation
a transition from a high impedance state to the point when they
start driving. The output enable time tENA is the interval from To determine the data output hold time in a particular system,
the point when a reference signal reaches a high or low voltage first calculate tDECAY using the equation given above. Choose ΔV
level to the point when the output starts driving as shown in the to be the difference between the processor’s output voltage and
Output Enable/Disable diagram (Figure 47). The time the input threshold for the device requiring the hold time. A
tENA_MEASURED is the interval from when the reference signal typical ΔV is 0.4 V. CL is the total bus capacitance (per data line),
switches to when the output voltage reaches 2.0 V (output high) and IL is the total leakage or three-state current (per data line).
or 1.0 V (output low). Time tTRIP is the interval from when the The hold time is tDECAY plus the minimum disable time (for
output starts driving to when the output reaches the 1.0 V or example, tDSDAT for an SDRAM write cycle).
2.0 V trip voltage. Time tENA is calculated as shown in Capacitive Loading
the equation:
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 48). Figure 49 through Figure 58 on
t ENA = t ENA_MEASURED – t TRIP Page 55 show how output rise time varies with capacitance. The
delay and hold specifications given should be derated by a factor
If multiple pins (such as the data bus) are enabled, the measure- derived from these figures. The graphs in these figures may not
ment value is that of the first pin to start driving. be linear outside the ranges shown.

50⍀ 12
TO
OUTPUT VLOAD
RISE AND FALL TIME ns (10% to 90%)

PIN
10
30pF
RISE TIME
8
Figure 48. Equivalent Device Loading for AC Measurements 6

FALL TIME
(Includes All Fixtures)
4
14
2
12
RISE TIME
10 0
0 50 100 150 200 250
LOAD CAPACITANCE (pF)
FALL TIME
8
Figure 51. Typical Output Delay or Hold for Driver B at VDDEXT Min
6
4 10

9
2
8
RISE TIME
0 7
0 50 100 150 200 250
LOAD CAPACITANCE (pF) 6
FALL TIME
5
Figure 49. Typical Output Delay or Hold for Driver A at VDDEXT Min
4
12 3
2
10 1
RISE TIME
0
8 0 50 100 150 200 250
FALL TIME
6
Figure 52. Typical Output Delay or Hold for Driver B at VDDEXT Max
4
30
2
25
0 RISE TIME
0 50 100 150 200 250
20
Figure 50. Typical Output Delay or Hold for Driver A at VDDEXT Max 15
FALL TIME
10
0
0 50 100 150 200 250
Figure 53. Typical Output Delay or Hold for Driver C at VDDEXT Min

20 36

18 32
16 28
RISE TIME RISE TIME
14 24
12
20
FALL TIME FALL TIME
10
16
8
12
6
8
4
4
2
0 0
0 50 100 150 200 250 0 50 100 150 200 250
LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF)
Figure 54. Typical Output Delay or Hold for Driver C at VDDEXT Max Figure 57. Typical Output Delay or Hold for Driver E at VDDEXT Min
36

18 32
16 28
RISE TIME
14 24
RISE TIME
12 20
10 16
FALL TIME FALL TIME
8 12
6 8
4 4
2 0
0 50 100 150 200 250
0 LOAD CAPACITANCE (pF)
0 50 100 150 200 250
LOAD CAPACITANCE (pF) Figure 58. Typical Output Delay or Hold for Driver E at VDDEXT Max
Figure 55. Typical Output Delay or Hold for Driver D at VDDEXT Min
36
32
14
28
12 RISE TIME
24
RISE TIME
10
20
FALL TIME
8 16
FALL TIME
12
6
8
4
4
2 0
0 50 100 150 200 250
0
0 50 100 150 200 250
LOAD CAPACITANCE (pF) Figure 59. Typical Output Delay or Hold for Driver F at VDDEXT Min
Figure 56. Typical Output Delay or Hold for Driver D at VDDEXT Max

Industrial applications using the 208-ball BGA package require
36
thermal vias, to an embedded ground plane, in the PCB. Refer to
32 JEDEC standard JESD51-9 for printed circuit board thermal

28
ball land and thermal via design information.
RISE TIME
24 Table 45. Thermal Characteristics (182-Ball BGA)
20
Parameter Condition Typical Unit
16 θJA 0 linear m/s air flow 32.80 ⴗC/W
FALL TIME
12 θJMA 1 linear m/s air flow 29.30 ⴗC/W
8
θJMA 2 linear m/s air flow 28.00 ⴗC/W
θJB 20.10 ⴗC/W
4
θJC 7.92 ⴗC/W
0
0 50 100 150 200 250 ΨJT 0 linear m/s air flow 0.19 ⴗC/W
ΨJT 1 linear m/s air flow 0.35 ⴗC/W
Figure 60. Typical Output Delay or Hold for Driver F at VDDEXT Max ΨJT 2 linear m/s air flow 0.45 ⴗC/W
THERMAL CHARACTERISTICS Table 46. Thermal Characteristics (208-Ball BGA Without

Thermal Vias in PCB)
To determine the junction temperature on the application
printed circuit board use: Parameter Condition Typical Unit
θJA 0 linear m/s air flow 23.30 ⴗC/W
T J = T CASE + ( Ψ JT × P D ) θJMA 1 linear m/s air flow 20.20 ⴗC/W
where: θJB 13.05 ⴗC/W
TJ = Junction temperature (ⴗC) θJC 6.92 ⴗC/W
TCASE = Case temperature (ⴗC) measured by customer at top ΨJT 0 linear m/s air flow 0.18 ⴗC/W
center of package. ΨJT 1 linear m/s air flow 0.27 ⴗC/W
ΨJT = From Table 45 ΨJT 2 linear m/s air flow 0.32 ⴗC/W
PD = Power dissipation (see the power dissipation discussion Table 47. Thermal Characteristics (208-Ball BGA with
and the tables on Page 27 for the method to calculate PD). Thermal Vias in PCB)
Values of θJA are provided for package comparison and printed
circuit board design considerations. θJA can be used for a first Parameter Condition Typical Unit
order approximation of TJ by the equation: θJA 0 linear m/s air flow 22.60 ⴗC/W
T J = T A + ( θ JA × P D ) θJMA 2 linear m/s air flow 18.40 ⴗC/W
θJB 13.20 ⴗC/W
where: θJC 6.85 ⴗC/W
TA = Ambient temperature (ⴗC)
Values of θJC are provided for package comparison and printed
circuit board design considerations when an external heat sink
is required. Values of θJB are provided for package comparison
and printed circuit board design considerations.
In Table 45 through Table 47, airflow measurements comply
with JEDEC standards JESD51-2 and JESD51-6, and the junc-
tion-to-board measurement complies with JESD51-8. Test
board and thermal via design comply with JEDEC standards
JESD51-9 (BGA). The junction-to-case measurement complies
with MIL-STD-883 (Method 1012.1). All measurements use a
2S2P JEDEC test board.

182-BALL CSP_BGA BALL ASSIGNMENT
Table 48 lists the CSP_BGA ball assignment by signal mne-
monic. Table 49 on Page 58 lists the CSP_BGA ball assignment
by ball number.
Table 48. 182-Ball CSP_BGA Ball Assignment (Alphabetically by Signal Mnemonic)
Mnemonic Ball No. Mnemonic Ball No. Mnemonic Ball No. Mnemonic Ball No. Mnemonic Ball No.
ABE0 H13 CLKOUT B14 GND L6 PG8 E3 SRAS D13
ABE1 H12 DATA0 M9 GND L8 PG9 E4 SWE D12
ADDR1 J14 DATA1 N9 GND L10 PH0 C2 TCK P2
ADDR10 M13 DATA10 N6 GND M4 PH1 C3 TDI M3
ADDR11 M14 DATA11 P6 GND M10 PH10 B6 TDO N3
ADDR12 N14 DATA12 M5 GND P14 PH11 A2 TMS N2
ADDR13 N13 DATA13 N5 NMI B10 PH12 A3 TRST N1
ADDR14 N12 DATA14 P5 PF0 M1 PH13 A4 VDDEXT A1
ADDR15 M11 DATA15 P4 PF1 L1 PH14 A5 VDDEXT C12
ADDR16 N11 DATA2 P9 PF10 J2 PH15 A6 VDDEXT E6
ADDR17 P13 DATA3 M8 PF11 J3 PH2 C4 VDDEXT E11
ADDR18 P12 DATA4 N8 PF12 H1 PH3 C5 VDDEXT F4
ADDR19 P11 DATA5 P8 PF13 H2 PH4 C6 VDDEXT F12
ADDR2 K14 DATA6 M7 PF14 H3 PH5 B1 VDDEXT H5
ADDR3 L14 DATA7 N7 PF15 H4 PH6 B2 VDDEXT H10
ADDR4 J13 DATA8 P7 PF2 L2 PH7 B3 VDDEXT J11
ADDR5 K13 DATA9 M6 PF3 L3 PH8 B4 VDDEXT J12
ADDR6 L13 EMU M2 PF4 L4 PH9 B5 VDDEXT K7
ADDR7 K12 GND A10 PF5 K1 PJ0 C7 VDDEXT K9
ADDR8 L12 GND A14 PF6 K2 PJ1 B7 VDDEXT L7
ADDR9 M12 GND D4 PF7 K3 PJ10 D10 VDDEXT L9
AMS0 E14 GND E7 PF8 K4 PJ11 D11 VDDEXT L11
AMS1 F14 GND E9 PF9 J1 PJ2 B11 VDDEXT P1
AMS2 F13 GND F5 PG0 G1 PJ3 C11 VDDINT E5
AMS3 G12 GND F6 PG1 G2 PJ4 D7 VDDINT E8
AOE G13 GND F10 PG10 D1 PJ5 D8 VDDINT E10
ARDY E13 GND F11 PG11 D2 PJ6 C8 VDDINT G10
ARE G14 GND G4 PG12 D3 PJ7 B8 VDDINT K5
AWE H14 GND G5 PG13 D5 PJ8 D9 VDDINT K8
BG P10 GND G11 PG14 D6 PJ9 C9 VDDINT K10
BGH N10 GND H11 PG15 C1 RESET C10 VDDRTC B9
BMODE0 N4 GND J4 PG2 G3 RTXO A8 VROUT0 A13
BMODE1 P3 GND J5 PG3 F1 RTXI A9 VROUT1 B12
BMODE2 L5 GND J9 PG4 F2 SA10 E12 XTAL A11
BR D14 GND J10 PG5 F3 SCAS C14
CLKBUF A7 GND K6 PG6 E1 SCKE B13
CLKIN A12 GND K11 PG7 E2 SMS C13

Table 49. 182-Ball CSP_BGA Ball Assignment (Numerically by Ball Number)
Ball No. Mnemonic Ball No. Mnemonic Ball No. Mnemonic Ball No. Mnemonic Ball No. Mnemonic
A1 VDDEXT C10 RESET F5 GND J14 ADDR1 M9 DATA0
A2 PH11 C11 PJ3 F6 GND K1 PF5 M10 GND
A3 PH12 C12 VDDEXT F10 GND K2 PF6 M11 ADDR15
A4 PH13 C13 SMS F11 GND K3 PF7 M12 ADDR9
A5 PH14 C14 SCAS F12 VDDEXT K4 PF8 M13 ADDR10
A6 PH15 D1 PG10 F13 AMS2 K5 VDDINT M14 ADDR11
A7 CLKBUF D2 PG11 F14 AMS1 K6 GND N1 TRST
A8 RTXO D3 PG12 G1 PG0 K7 VDDEXT N2 TMS
A9 RTXI D4 GND G2 PG1 K8 VDDINT N3 TDO
A10 GND D5 PG13 G3 PG2 K9 VDDEXT N4 BMODE0
A11 XTAL D6 PG14 G4 GND K10 VDDINT N5 DATA13
A12 CLKIN D7 PJ4 G5 GND K11 GND N6 DATA10
A13 VROUT0 D8 PJ5 G10 VDDINT K12 ADDR7 N7 DATA7
A14 GND D9 PJ8 G11 GND K13 ADDR5 N8 DATA4
B1 PH5 D10 PJ10 G12 AMS3 K14 ADDR2 N9 DATA1
B2 PH6 D11 PJ11 G13 AOE L1 PF1 N10 BGH
B3 PH7 D12 SWE G14 ARE L2 PF2 N11 ADDR16
B4 PH8 D13 SRAS H1 PF12 L3 PF3 N12 ADDR14
B5 PH9 D14 BR H2 PF13 L4 PF4 N13 ADDR13
B6 PH10 E1 PG6 H3 PF14 L5 BMODE2 N14 ADDR12
B7 PJ1 E2 PG7 H4 PF15 L6 GND P1 VDDEXT
B8 PJ7 E3 PG8 H5 VDDEXT L7 VDDEXT P2 TCK
B9 VDDRTC E4 PG9 H10 VDDEXT L8 GND P3 BMODE1
B10 NMI E5 VDDINT H11 GND L9 VDDEXT P4 DATA15
B11 PJ2 E6 VDDEXT H12 ABE1 L10 GND P5 DATA14
B12 VROUT1 E7 GND H13 ABE0 L11 VDDEXT P6 DATA11
B13 SCKE E8 VDDINT H14 AWE L12 ADDR8 P7 DATA8
B14 CLKOUT E9 GND J1 PF9 L13 ADDR6 P8 DATA5
C1 PG15 E10 VDDINT J2 PF10 L14 ADDR3 P9 DATA2
C2 PH0 E11 VDDEXT J3 PF11 M1 PF0 P10 BG
C3 PH1 E12 SA10 J4 GND M2 EMU P11 ADDR19
C4 PH2 E13 ARDY J5 GND M3 TDI P12 ADDR18
C5 PH3 E14 AMS0 J9 GND M4 GND P13 ADDR17
C6 PH4 F1 PG3 J10 GND M5 DATA12 P14 GND
C7 PJ0 F2 PG4 J11 VDDEXT M6 DATA9
C8 PJ6 F3 PG5 J12 VDDEXT M7 DATA6
C9 PJ9 F4 VDDEXT J13 ADDR4 M8 DATA3

Figure 61 shows the top view of the CSP_BGA
ball configuration. Figure 62 shows the bottom view of the
CSP_BGA ball configuration.
14 13 12 11 10 9 8 7 6 5 4 3 2 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
L
L
M
M
N
N
P
P
KEY:
KEY:
VDDINT GND VDDRTC
VDDINT GND VDDRTC
VDDEXT I/O VROUT
VDDEXT I/O VROUT
Figure 62. 182-Ball CSP_BGA Configuration (Bottom View)

Figure 61. 182-Ball CSP_BGA Configuration (Top View)

208-BALL CSP_BGA BALL ASSIGNMENT
Table 50 lists the CSP_BGA ball assignment by signal mne-
monic. Table 51 on Page 61 lists the CSP_BGA ball assignment
by ball number.
Table 50. 208-Ball CSP_BGA Ball Assignment (Alphabetically by Signal Mnemonic)
Mnemonic Ball No. Mnemonic Ball No. Mnemonic Ball No. Mnemonic Ball No. Mnemonic Ball No.
ABE0 P19 DATA12 Y4 GND M13 PG6 E2 TDI V1
ABE1 P20 DATA13 W4 GND N9 PG7 D1 TDO Y2
ADDR1 R19 DATA14 Y3 GND N10 PG8 D2 TMS U2
ADDR10 W18 DATA15 W3 GND N11 PG9 C1 TRST U1
ADDR11 Y18 DATA2 Y9 GND N12 PH0 B4 VDDEXT G7
ADDR12 W17 DATA3 W9 GND N13 PH1 A5 VDDEXT G8
ADDR13 Y17 DATA4 Y8 GND P11 PH10 B9 VDDEXT G9
ADDR14 W16 DATA5 W8 GND V2 PH11 A10 VDDEXT G10
ADDR15 Y16 DATA6 Y7 GND W2 PH12 B10 VDDEXT H7
ADDR16 W15 DATA7 W7 GND W19 PH13 A11 VDDEXT H8
ADDR17 Y15 DATA8 Y6 GND Y1 PH14 B11 VDDEXT J7
ADDR18 W14 DATA9 W6 GND Y13 PH15 A12 VDDEXT J8
ADDR19 Y14 EMU T1 GND Y20 PH2 B5 VDDEXT K7
ADDR2 T20 GND A1 NMI C20 PH3 A6 VDDEXT K8
ADDR3 T19 GND A13 PF0 T2 PH4 B6 VDDEXT L7
ADDR4 U20 GND A20 PF1 R1 PH5 A7 VDDEXT L8
ADDR5 U19 GND B2 PF10 L2 PH6 B7 VDDEXT M7
ADDR6 V20 GND G11 PF11 K1 PH7 A8 VDDEXT M8
ADDR7 V19 GND H9 PF12 K2 PH8 B8 VDDEXT N7
ADDR8 W20 GND H10 PF13 J1 PH9 A9 VDDEXT N8
ADDR9 Y19 GND H11 PF14 J2 PJ0 B12 VDDEXT P7
AMS0 M20 GND H12 PF15 H1 PJ1 B13 VDDEXT P8
AMS1 M19 GND H13 PF2 R2 PJ10 B19 VDDEXT P9
AMS2 G20 GND J9 PF3 P1 PJ11 C19 VDDEXT P10
AMS3 G19 GND J10 PF4 P2 PJ2 D19 VDDINT G12
AOE N20 GND J11 PF5 N1 PJ3 E19 VDDINT G13
ARDY J19 GND J12 PF6 N2 PJ4 B18 VDDINT G14
ARE N19 GND J13 PF7 M1 PJ5 A19 VDDINT H14
AWE R20 GND K9 PF8 M2 PJ6 B15 VDDINT J14
BG Y11 GND K10 PF9 L1 PJ7 B16 VDDINT K14
BGH Y12 GND K11 PG0 H2 PJ8 B17 VDDINT L14
BMODE0 W13 GND K12 PG1 G1 PJ9 B20 VDDINT M14
BMODE1 W12 GND K13 PG10 C2 RESET D20 VDDINT N14
BMODE2 W11 GND L9 PG11 B1 RTXO A15 VDDINT P12
BR F19 GND L10 PG12 A2 RTXI A14 VDDINT P13
CLKBUF B14 GND L11 PG13 A3 SA10 L20 VDDINT P14
CLKIN A18 GND L12 PG14 B3 SCAS K20 VDDRTC A16
CLKOUT H19 GND L13 PG15 A4 SCKE H20 VROUT0 E20
DATA0 Y10 GND M9 PG2 G2 SMS J20 VROUT1 F20
DATA1 W10 GND M10 PG3 F1 SRAS K19 XTAL A17
DATA10 Y5 GND M11 PG4 F2 SWE L19
DATA11 W5 GND M12 PG5 E1 TCK W1

Table 51 lists the CSP_BGA ball assignment by ball number.
Table 50 on Page 60 lists the CSP_BGA ball assignment by sig-
nal mnemonic.
Table 51. 208-Ball CSP_BGA Ball Assignment (Numerically by Ball Number)
Ball No. Mnemonic Ball No. Mnemonic Ball No. Mnemonic Ball No. Mnemonic Ball No. Mnemonic
A1 GND C19 PJ11 J9 GND M19 AMS1 W1 TCK
A2 PG12 C20 NMI J10 GND M20 AMS0 W2 GND
A3 PG13 D1 PG7 J11 GND N1 PF5 W3 DATA15
A4 PG15 D2 PG8 J12 GND N2 PF6 W4 DATA13
A5 PH1 D19 PJ2 J13 GND N7 VDDEXT W5 DATA11
A6 PH3 D20 RESET J14 VDDINT N8 VDDEXT W6 DATA9
A7 PH5 E1 PG5 J19 ARDY N9 GND W7 DATA7
A8 PH7 E2 PG6 J20 SMS N10 GND W8 DATA5
A9 PH9 E19 PJ3 K1 PF11 N11 GND W9 DATA3
A10 PH11 E20 VROUT0 K2 PF12 N12 GND W10 DATA1
A11 PH13 F1 PG3 K7 VDDEXT N13 GND W11 BMODE2
A12 PH15 F2 PG4 K8 VDDEXT N14 VDDINT W12 BMODE1
A13 GND F19 BR K9 GND N19 ARE W13 BMODE0
A14 RTXI F20 VROUT1 K10 GND N20 AOE W14 ADDR18
A15 RTXO G1 PG1 K11 GND P1 PF3 W15 ADDR16
A16 VDDRTC G2 PG2 K12 GND P2 PF4 W16 ADDR14
A17 XTAL G7 VDDEXT K13 GND P7 VDDEXT W17 ADDR12
A18 CLKIN G8 VDDEXT K14 VDDINT P8 VDDEXT W18 ADDR10
A19 PJ5 G9 VDDEXT K19 SRAS P9 VDDEXT W19 GND
A20 GND G10 VDDEXT K20 SCAS P10 VDDEXT W20 ADDR8
B1 PG11 G11 GND L1 PF9 P11 GND Y1 GND
B2 GND G12 VDDINT L2 PF10 P12 VDDINT Y2 TDO
B3 PG14 G13 VDDINT L7 VDDEXT P13 VDDINT Y3 DATA14
B4 PH0 G14 VDDINT L8 VDDEXT P14 VDDINT Y4 DATA12
B5 PH2 G19 AMS3 L9 GND P19 ABE0 Y5 DATA10
B6 PH4 G20 AMS2 L10 GND P20 ABE1 Y6 DATA8
B7 PH6 H1 PF15 L11 GND R1 PF1 Y7 DATA6
B8 PH8 H2 PG0 L12 GND R2 PF2 Y8 DATA4
B9 PH10 H7 VDDEXT L13 GND R19 ADDR1 Y9 DATA2
B10 PH12 H8 VDDEXT L14 VDDINT R20 AWE Y10 DATA0
B11 PH14 H9 GND L19 SWE T1 EMU Y11 BG
B12 PJ0 H10 GND L20 SA10 T2 PF0 Y12 BGH
B13 PJ1 H11 GND M1 PF7 T19 ADDR3 Y13 GND
B14 CLKBUF H12 GND M2 PF8 T20 ADDR2 Y14 ADDR19
B15 PJ6 H13 GND M7 VDDEXT U1 TRST Y15 ADDR17
B16 PJ7 H14 VDDINT M8 VDDEXT U2 TMS Y16 ADDR15
B17 PJ8 H19 CLKOUT M9 GND U19 ADDR5 Y17 ADDR13
B18 PJ4 H20 SCKE M10 GND U20 ADDR4 Y18 ADDR11
B19 PJ10 J1 PF13 M11 GND V1 TDI Y19 ADDR9
B20 PJ9 J2 PF14 M12 GND V2 GND Y20 GND
C1 PG9 J7 VDDEXT M13 GND V19 ADDR7
C2 PG10 J8 VDDEXT M14 VDDINT V20 ADDR6

Figure 63 shows the top view of the CSP_BGA ball configura-
tion. Figure 64 shows the bottom view of the CSP_BGA ball
configuration.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
KEY: KEY:
VDDINT GND VDDRTC
VDDINT GND VDDRTC
VDDEXT VROUT VDDEXT I/O VROUT
I/O
Figure 63. 208-Ball CSP_BGA Configuration (Top View) Figure 64. 208-Ball CSP_BGA Configuration (Bottom View)

OUTLINE DIMENSIONS
Dimensions in Figure 65 and Figure 66 are shown in
millimeters.
A1 CORNER
12.00 BSC SQ INDEX AREA
14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
PIN A1 C
INDICATOR D
LOCATION E
10.40 F
BSC G
SQ H
0.80 J
BSC K
TYP L
M
N
P
TOP VIEW BOTTOM VIEW
DETAIL A 1.31
1.70 MAX
1.21
1.10
0.25 MIN
0.50
SEATING 0.12
0.45 COPLANARITY
PLANE
NOTES: 0.40
1. COMPLIANT TO JEDEC STANDARD MO-205-AE, (BALL
EXCEPT FOR BALL DIAMETER. DIAMETER)
2. CENTER DIMENSIONS ARE NOMINAL. DETAIL A
3. THE ACTUAL POSITION OF THE BALL GRID IS
WITHIN 0.15 OF ITS IDEAL POSITION RELATIVE
TO THE PACKAGE EDGES
Figure 65. 182-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-182)
Dimensions shown in millimeters

17.10 A1 CORNER
17.00 SQ INDEX AREA
20 18 16 14 12 10 8 6 4 2
16.90 19 17 15 13 11 9 7 5 3 1
A
B
C
D
A1 BALL E
CORNER F
15.20 G
BSC SQ H
J
K
L
M
N
P
0.80 R
BSC T
U
V
W
Y
TOP VIEW BOTTOM VIEW
DETAIL A
*1.75 1.36
1.61 DETAIL A 1.26
1.46 1.16
0.35 NOM
0.30 MIN
*0.50 COPLANARITY
SEATING 0.45 0.12
PLANE 0.40
BALL
DIAMETER
*COMPLIANT TO JEDEC STANDARDS MO-205-AM WITH
EXCEPTION TO PACKAGE HEIGHT AND BALL DIAMETER.
Figure 66. 208-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-208-2)
Dimensions shown in millimeters
SURFACE-MOUNT DESIGN
The following table is provided as an aid to PCB design. For
industry-standard design recommendations, refer to IPC-7351,
Generic Requirements for Surface Mount Design and Land Pat-
tern Standard.
Package Ball Attach Type Solder Mask Opening Ball Pad Size
182-Ball CSP_BGA (BC-182) Solder Mask Defined 0.40 mm diameter 0.55 mm diameter
208-Ball CSP_BGA (BC-208-2) Solder Mask Defined 0.40 mm diameter 0.55 mm diameter

AUTOMOTIVE PRODUCTS
Some ADSP-BF534 models are available for automotive appli- The automotive grade products shown in Table 52 are available
cations with controlled manufacturing. Note that these special for use in automotive applications. Contact your local ADI
models may have specifications that differ from the general account representative or authorized ADI product distributor
release models. for specific product ordering information. Note that all automo-
tive products are RoHS compliant.
Table 52. Automotive Products
Package
Product Family1 Temperature Range2 Speed Grade (Max) Package Description Option
ADBF534WBBCZ4Axx –40°C to +85°C 400 MHz 182-Ball CSP_BGA BC-182
ADBF534WBBCZ4Bxx –40°C to +85°C 400 MHz 208-Ball CSP_BGA BC-208-2
ADBF534WYBCZ4Bxx –40°C to +105°C 400 MHz 208-Ball CSP_BGA BC-208-2
1
xx denotes silicon revision.
2
Referenced temperature is ambient temperature.
ORDERING GUIDE
In the following table CSP_BGA = Chip Scale Package Ball Grid
Array.
Package
Model Temperature Range1 Speed Grade (Max) Package Description Option
ADSP-BF534BBC-4A –40°C to +85°C 400 MHz 182-Ball CSP_BGA BC-182
ADSP-BF534BBCZ-4A2 –40°C to +85°C 400 MHz 182-Ball CSP_BGA BC-182
ADSP-BF534BBCZ-4B2 –40°C to +85°C 400 MHz 208-Ball CSP_BGA BC-208-2
ADSP-BF534YBCZ-4B2 –40°C to +105°C 400 MHz 208-Ball CSP_BGA BC-208-2
ADSP-BF537BBCZ-5AV2 –40°C to +85°C 533 MHz 182-Ball CSP_BGA BC-182
ADSP-BF537BBCZ-5BV2 –40°C to +85°C 533 MHz 208-Ball CSP_BGA BC-208-2
ADSP-BF537KBCZ-6AV2 0°C to +70°C 600 MHz 182-Ball CSP_BGA BC-182
ADSP-BF537KBCZ-6BV2 0°C to +70°C 600 MHz 208-Ball CSP_BGA BC-208-2
1
Referenced temperature is ambient temperature.
2
Z = RoHS compliant part.



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Blackfin

VOLTAGE REGULATOR JTAG TEST AND EMULATION

PERIPHERAL ACCESS BUS

DMA CORE BUS UART0-1

ETHERNET MAC GPIO

Figure 1. Functional Block Diagram

Rev. G | Page 2 of 68 | February 2009

applications can be developed quickly, without the need for

Rev. G | Page 3 of 68 | February 2009

ADDRESS ARITHMETIC UNIT

DATA ARITHMETIC UNIT

Figure 2. Blackfin Processor Core

Rev. G | Page 4 of 68 | February 2009

Rev. G | Page 5 of 68 | February 2009

ADSP-BF534/ADSP-BF537 MEMORY MAP ADSP-BF536 MEMORY MAP

0xFFFF FFFF 0xFFFF FFFF

INTERNAL MEMORY MAP

INTERNAL MEMORY MAP

EXTERNAL MEMORY MAP

BOOT ROM (2K BYTES)

Figure 3. ADSP-BF534/ADSP-BF536/ADSP-BF537 Memory Maps

Booting • Nonmaskable Interrupt (NMI) – The NMI event can be

Rev. G | Page 6 of 68 | February 2009

Rev. G | Page 7 of 68 | February 2009

Rev. G | Page 8 of 68 | February 2009

DMA request pins when used in conjunction with the external R1

Rev. G | Page 9 of 68 | February 2009

Rev. G | Page 10 of 68 | February 2009

Rev. G | Page 11 of 68 | February 2009

Rev. G | Page 12 of 68 | February 2009

DYNAMIC POWER MANAGEMENT Deep Sleep Operating Mode—Maximum Dynamic Power

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processor core while keeping I/O power supplied. While in CLKOUT

initiates a boot sequence. The regulator can also be disabled and

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors can

If an external clock is used, it should be a TTL compatible signal

nal Ethernet MII or RMII PHY device. CLKIN

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Table 9. Pin Descriptions

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Parameter Conditions Min Nominal Max Unit

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Parameter Internal Regulator Setting Max Unit

Table 11. Core Clock Requirements—400 MHz Speed Grade1

120°C ≥ TJ > 105°C All2 Other TJ

Table 12. Core Clock Requirements—300 MHz Speed Grade1

Parameter Internal Regulator Setting Max Unit

Table 13. Phase-Locked Loop Operating Conditions

Parameter Min Max Unit

Table 14. System Clock Requirements

Parameter Condition Max Unit

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