Solutions for Powering

Intel and AMD SoCs

Presenter: Mario Willeit
April 22, 2020
Presenter Intro: Mario Willeit

Senior Field Applications Engineer

South East Germany / Austria

[email protected]
Agenda

Solutions for Powering Intel and AMD SoCs

• Solution Overview
• Digital Multi-Phase Controller
• Powerstage / DrMOS / IntelliPhase
• Design Tools
• TGL-UP3 Example
• Summary
• Q&A
MPS Solution Overview

MPS GUI Software POL regulators with pin

selectable voltages and
SoC dedicated timing as
Single / Multiphase well as universal regulators
PMBUS System
Management
3.3V Digital-Controller SVI2/3, PVID Buck
SVID (IMVP8/9/9.1, VR13/14) NB6xx
MP28/29xx
INTEL (EHL, TGL, …)
Differential Voltage Sense AMD (Ryzen, …)
Current TEMP/
PWM
sense Fault Buck
NB6xx

3.3V-20V Intelliphase
SDRAM
MP86xxx DDR3/4,
Buck / LDOs
NB68x
N-phases LPDDR3/4/4X/5
Single/ All SDRAM voltages +
multi rail, power up/down sequencing
Single/ All ceramics or mixed
multi phase ceramic/POSCAP
 Digital Multi-Phase Controller
FEATURES

• Single/Multiple Loop
(Flexible Phase Assignment)
• Patented Constant on-time Control:
Best Transient in the Market
• All Digital Control via PMBUS
• Minimal External Components
• Telemetry
• Vin, Vo, Iin, Iout, Pin, Pout, Temperature
• Peak Current Detection
• Advanced Fault Handling
• OCP, OVP, UVP, OTP
• Cycle-by-cycle OC/UC
• Catastrophic Failure Protection
 Powerstage / DrMOS / IntelliPhase
FEATURES
• Continuous Current up to 80A, Peak Current
up to 125A (MP86998)
• Package Options:
• Common Footprint (CFP)
• MPS Proprietary Footprint
• Supports Wide Fsw Range
• From 100kHz to 3MHz
• Balanced Between Transient and Efficiency
• Built-In ZCD, OCP, NOCP, OTP, SCP
• Current Sense Tolerance ±3%
• Single-End Current Sensing Output
• Minimal External Components
• Immune to Noise
 Powerstage / DrMOS / IntelliPhase
Monolithic Design On-Die Current Sensing Flip-Chip Package
• Distributed Gate Driver (DGD) • CS pin is a current output of • High Reliability
minimizes the Gate Delay, 10µA x Iout
• Small Form Factor
significantly reduces the dead • Tracks current cycle by cycle
time • Good Thermal Design
• Independent of the
• Minimized path from driver to • Low Parasitic Inductance
Temperature, Rdson, and
FET cells, strong driving Inductor DC resistance
capability with fast turn-on/off variations (±3%)
speed
• No thermal compensation
needed
Design Tools : Reference Designs / Layout Guidelines and EVBs
• Reference schematic for most SoCs from Intel/AMD
(either from MPS or SoC vendor)
• Proven and detailed layout guidelines in each DrMOS/POL regulator datasheet
• Evaluation Boards for many digital controller/DrMOS and POL regulator

Input Capacitor: 0805 package (top side & bottom side)

Inductor: 6.5 × 6.5 (mm)
VCC/BST capacitor: 0402 package
Via size: 20/10 mils
Design Tools : Digital Controller Configuration
• MPS provides design/SoC specific initial configuration for digital controller
• Based on experience, validated with SoC vendor tools on MPS evaluation boards (e.g. Intel VRTT)
• Customer can further optimize the design with MPS Excel Design tool and GUI software

Configuration File GUI Software (Windows)

Excel Design File

• Design Target Specification
• Detailed Configuration
(Design Tuning)
Programming Adapter
Digital Controller Example : MP2940A (INTEL IMVP8/9)
Digital Controller Example : MP2945 (AMD SVI2)

MP2945 MP2845
6-phase/4-rail AMD Has Chosen MPS
5-phase/2rail
Controller SVI3 As SVI3 Development
Next Gen AMD
5x5 PKG Partner!
DrMOS Examples
MP86979 MP86949 MPQ86940
MP86909

50A

4X4 MP86941/71 5X6 4X6 5X6

(w/PFO)
MP86902B

VTEMP/FAULT
AGND

SYNC
PWM
VCC
BST

CS
21 20 19 18 17 16 15
5X6 CF Version of MP86949 4.5-22V / 45A 3-22V / 40A
25A 3X4 4.5-16V / 50A VIN 1 14 VIN

SW 2
MP86901C
SW 3
3X5 13 PGND

MP86901B
12 PGND

SW 4

3-12V / 35A
5 6 7 8 9 10 11
MP86902A 3X4

PGND
PGND
PGND
PGND
PGND
PGND
PGND
3X4 MP86901A
4.5-22V / 30A
3X3
12A
4.5-22V / 30A 3X3
3-12V / 15A
4.5-22V / 20A
4.5-22V / 12A
12V 16V 22V
Intel TGL-UP3 Design Example (VCCIN, VCCIN_AUX)
Intel TGL-UP3 Example (VCCIN, VCCIN_AUX) 3x47uF Bulk Capacitance
at the input

10x22uF + 1x220uF
15x22uF + 1x330uF
Intel TGL-UP3 Example (Other Rails)
 Summary – Q&A

• Complete Power Solution from a single vendor

• Digital Controller eases design process and verfication

• Fast Control Loop allows reduction of output capacitors to fullfill ripple/transient specifications

• High efficiency Monolithic DrMOS devices with low thermal resistance Flip-Chip packages
supports space constraints designs

• Accurate DrMOS on-die current sense leads to better overall system performance and much less
engineering effort (no inductor DCR sensing and temperature compensation required)

• Design Support (initial controller configuration, layout guides, schematic/layout review)

Reduces risk and saves development time