PIC16 (L) F1933 Datasheet

PIC16(L)F1933
28-Pin Flash-Based, 8-Bit CMOS Microcontrollers with

LCD Driver with XLP Technology
High-Performance RISC CPU: PIC16LF1933 Low-Power Features:
• Only 49 Instructions to Learn: • Standby Current:
- All single-cycle instructions except branches - 60 nA @ 1.8V, typical
• Operating Speed: • Operating Current:
- DC – 32 MHz oscillator/clock input - 75 A/MHz, 1.8V, typical
- DC – 125 ns instruction cycle • Timer1 Oscillator Current:
• Up to 16K x 14 Words of Flash Program Memory - 600 nA @ 32 kHz, 1.8V, typical
• Up to 1024 Bytes of Data Memory (RAM) • Low-Power Watchdog Timer Current:
• Interrupt Capability with Automatic Context - 500 nA @ 1.8V, typical
Saving
• 16-Level Deep Hardware Stack Peripheral Features:
• Direct, Indirect and Relative Addressing modes • Up to 35 I/O Pins and 1 Input-only pin:
• Processor Read Access to Program Memory - High-current source/sink for direct LED drive
• Pinout Compatible to other 28-pin PIC16CXXX - Individually programmable interrupt-on-pin
and PIC16FXXX Microcontrollers change pins
- Individually programmable weak pull-ups
Special Microcontroller Features: • Integrated LCD Controller:
• Precision Internal Oscillator: - Up to 96 segments
- Factory calibrated to ±1%, typical - Variable clock input
- Software selectable frequency range from - Contrast control
32 MHz to 31 kHz - Internal voltage reference selections
• Power-Saving Sleep mode • Capacitive Sensing module (mTouchTM)
• Power-on Reset (POR) - Up to 16 selectable channels
• Power-up Timer (PWRT) and Oscillator Start-up • A/D Converter:
Timer (OST) - 10-bit resolution and up to 14 channels
• Brown-out Reset (BOR) - Selectable 1.024/2.048/4.096V voltage
- Selectable between two trip points reference
- Disable in Sleep option • Timer0: 8-Bit Timer/Counter with 8-Bit
• Multiplexed Master Clear with Pull-up/Input Pin Programmable Prescaler
• Programmable Code Protection • Enhanced Timer1
• Wide Operating Voltage Range: - Dedicated low-power 32 kHz oscillator driver
- 1.8V-5.5V (PIC16F1933) - 16-bit timer/counter with prescaler
- 1.8V-3.6V (PIC16LF1933) - External Gate Input mode with Toggle and
Single Shot modes
- Interrupt-on-gate completion
• Timer2, 4, 6: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
• Two Capture, Compare, PWM modules (CCP)
- 16-bit Capture, max. resolution 125 ns
- 16-bit Compare, max. resolution 125 ns
- 10-bit PWM, max. frequency 31.25 kHz
• Three Enhanced Capture, Compare, PWM
modules (ECCP)
- 3 PWM time-base options
- Auto-shutdown and auto-restart
- PWM steering
- Programmable dead-band delay
 2011-2012 Microchip Technology Inc. DS41575C-page 1

PIC16(L)F1933
Peripheral Features (Continued):
• Master Synchronous Serial Port (MSSP) with SPI
and I2 CTM with:
- 7-bit address masking
- SMBus/PMBusTM compatibility
- Auto-wake-up on start
• Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART)
- RS-232, RS-485 and LIN compatible
- Auto-Baud Detect
• SR Latch (555 Timer):
- Multiple Set/Reset input options
- Emulates 555 Timer applications
• 2 Comparators:
- Rail-to-rail inputs/outputs
- Power mode control
- Software enable hysteresis
• Voltage Reference module:
- Fixed Voltage Reference (FVR) with 1.024V,
2.048V and 4.096V output levels
- 5-bit rail-to-rail resistive DAC with positive
and negative reference selection
PIC16(L)F193X/194X Family Types
Program Memory
MSSP (I2C™/SPI)
Data Sheet Index
(Com/Seg/Total)
10-bit ADC (ch)
CapSense (ch)
Data EEPROM
Flash (words)
Comparators
Data SRAM
(8/16-bit)
EUSART
Debug(1)
(bytes)
(bytes)
Timers
I/O’s(2)
ECCP
CCP
LCD
XLP
Device
PIC16(L)F1933 (1) 4096 256 256 25 11 8 2 4/1 1 1 3 2 4/16/60(3) I/H Y

PIC16(L)F1934 (2) 4096 256 256 36 14 16 2 4/1 1 1 3 2 4/24/96 I/H Y
PIC16(L)F1936 (2) 8192 256 512 25 11 8 2 4/1 1 1 3 2 4/16/60(3) I/H Y
PIC16(L)F1937 (2) 8192 256 512 36 14 16 2 4/1 1 1 3 2 4/24/96 I/H Y
PIC16(L)F1938 (3) 16384 256 1024 25 11 8 2 4/1 1 1 3 2 4/16/60(3) I/H Y
PIC16(L)F1939 (3) 16384 256 1024 36 14 16 2 4/1 1 1 3 2 4/24/96 I/H Y
PIC16(L)F1946 (4) 8192 256 512 54 17 17 3 4/1 2 2 3 2 4/46/184 I Y
PIC16(L)F1947 (4) 16384 256 1024 54 17 17 3 4/1 2 2 3 2 4/46/184 I Y
Note 1: I - Debugging, Integrated on Chip; H - Debugging, available using Debug Header.
2: One pin is input-only.
3: COM3 and SEG15 share the same physical pin, therefore SEG15 is not available when using 1/4 multiplex
displays.
Data Sheet Index: (Unshaded devices are described in this document.)
1: DS41575 PIC16(L)F1933 Data Sheet, 28-Pin Flash, 8-bit Microcontrollers.
2: DS41364 PIC16(L)F1934/6/7 Data Sheet, 28/40/44-Pin Flash, 8-bit Microcontrollers.
3: DS41574 PIC16(L)F1938/9 Data Sheet, 28/40/44-Pin Flash, 8-bit Microcontrollers.
4: DS41414 PIC16(L)F1946/1947 Data Sheet, 64-Pin Flash, 8-bit Microcontrollers.
Note: For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
DS41575C-page 2  2011-2012 Microchip Technology Inc.

PIC16(L)F1933
Pin Diagram – 28-Pin SPDIP/SOIC/SSOP (PIC16F1933, PIC16LF1933)
28-pin SPDIP, SOIC, SSOP
VPP/MCLR/RE3 1 28 RB7/ICSPDAT
RA0 2 27 RB6/ICSPCLK
RA1 3 26 RB5
RA2 4 25 RB4
RA3 5 24 RB3
PIC16LF1933
PIC16F1933
RA4 6 23 RB2
RA5 7 22 RB1
VSS 8 21 RB0
RA7 9 20 VDD
10 19 VSS
RA6
RC0 11 18 RC7
RC1 12 17 RC6
RC2 13 16 RC5
RC3 14 15 RC4
Pin Diagram – 28-Pin QFN/UQFN (PIC16F1933, PIC16LF1933)
28-pin QFN/UQFN
RE3/MCLR/VPP
RB6/ICSPCLK
RB7/ICSPDAT
RA1
RA0
RB5
RB4
28
27
26
24
23
22
25
RA2 1 21 RB3
RA3 2 20 RB2
RA4 3 PIC16F1933 19 RB1
RA5 4 PIC16LF1933 18 RB0
VSS 5 17 VDD
RA7 6 16 VSS
RA6 7 15 RC7
10
12
13
14
11
8
9
RC0
RC1
RC2
RC3
RC4
RC5
RC6

PIC16(L)F1933
TABLE 1: 28-PIN SUMMARY (PIC16F1933, PIC16LF1933)
SPDIP/SOIC/SSOP
Comparator
QFN/UQFN
Cap Sense
SR Latch
EUSART
Interrupt
ANSEL
Pull-up
Timers
28-Pin
28-Pin
MSSP
Basic
CCP
LCD
A/D
I/O
RA0 2 27 Y AN0 — C12IN0-/ — — — SEG12 — — VCAP(2)

SRNQ(1) SS(1)
C2OUT(1)
RA1 3 28 Y AN1 — C12IN1- — — — — — SEG7 — — —
RA2 4 1 Y AN2/ — C2IN+/ — — — — — COM2 — — —
VREF- DACOUT
RA3 5 2 Y AN3/ — C1IN+ — — — — — SEG15/ — — —
VREF+ COM3
RA4 6 3 Y — CPS6 C1OUT SRQ T0CKI CCP5 — — SEG4 — — —
RA5 7 4 Y AN4 CPS7 C2OUT(1) SRNQ(1) — — — SS(1) SEG5 — — VCAP(2)
RA6 10 7 — — — — — — — — — SEG1 — — OSC2/
CLKOUT
VCAP(2)
RA7 9 6 — — — — — — — — — SEG2 — — OSC1/
CLKIN
RB0 21 18 Y AN12 CPS0 — SRI — CCP4 — — SEG0 INT/ Y —
IOC
RB1 22 19 Y AN10 CPS1 C12IN3- — — P1C — — VLCD1 IOC Y —
RB2 23 20 Y AN8 CPS2 — — — P1B — — VLCD2 IOC Y —
RB3 24 21 Y AN9 CPS3 C12IN2- — — CCP2(1)/ — — VLCD3 IOC Y —
P2A(1)
RB4 25 22 Y AN11 CPS4 — — — P1D — — COM0 IOC Y —
RB5 26 23 Y AN13 CPS5 — — T1G(1) P2B(1) — — COM1 IOC Y —
CCP3(1)/
P3A(1)
RB6 27 24 — — — — — — — — — SEG14 IOC Y ICSPCLK/
ICDCLK
RB7 28 25 — — — — — — — — — SEG13 IOC Y ICSPDAT/
ICDDAT
RC0 11 8 — — — — — T1OSO/ P2B(1) — — — — — —
T1CKI
RC1 12 9 — — — — — T1OSI CCP2(1)/ — — — — — —
P2A(1)
RC2 13 10 — — — — — — CCP1/ — — SEG3 — — —
P1A
RC3 14 11 — — — — — — — — SCK/SCL SEG6 — — —
RC4 15 12 — — — — — T1G(1) — — SDI/SDA SEG11 — — —
RC5 16 13 — — — — — — — — SDO SEG10 — — —
RC6 17 14 — — — — — — CCP3(1) TX/CK — SEG9 — — —
P3A(1)
RC7 18 15 — — — — — — P3B RX/DT — SEG8 — — —
RE3 1 26 — — — — — — — — — — — Y MCLR/VPP
VDD 20 17 — — — — — — — — — — — — VDD
Vss 8, 5,16 — — — — — — — — — — — — VSS
19
Note 1: Pin functions can be moved using the APFCON register.
2: PIC16F1933 devices only.

PIC16(L)F1933
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 13
3.0 Memory Organization ................................................................................................................................................................. 15
4.0 Device Configuration .................................................................................................................................................................. 45
5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 51
6.0 Resets ........................................................................................................................................................................................ 69
7.0 Interrupts .................................................................................................................................................................................... 77
8.0 Low Dropout (LDO) Voltage Regulator ...................................................................................................................................... 91
9.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 93
10.0 Watchdog Timer (WDT) ............................................................................................................................................................. 95
11.0 Data EEPROM and Flash Program Memory Control ................................................................................................................. 99
12.0 I/O Ports ................................................................................................................................................................................... 113
13.0 Interrupt-On-Change ................................................................................................................................................................ 129
14.0 Fixed Voltage Reference.......................................................................................................................................................... 133
15.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 137
16.0 Temperature Indicator Module ................................................................................................................................................. 151
17.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 153
18.0 Comparator Module.................................................................................................................................................................. 157
19.0 SR Latch................................................................................................................................................................................... 167
20.0 Timer0 Module ......................................................................................................................................................................... 171
21.0 Timer1 Module with Gate Control............................................................................................................................................. 175
22.0 Timer2/4/6 Modules.................................................................................................................................................................. 187
23.0 Capture/Compare/PWM Modules (ECCP1, ECCP2, ECCP3, CCP4, CCP5).......................................................................... 191
24.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 219
25.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 275
26.0 Capacitive Sensing Module...................................................................................................................................................... 305
27.0 Liquid Crystal Display (LCD) Driver Module............................................................................................................................. 313
28.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 347
29.0 Instruction Set Summary .......................................................................................................................................................... 351
30.0 Electrical Specifications............................................................................................................................................................ 365
31.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 397
32.0 Development Support............................................................................................................................................................... 433
33.0 Packaging Information.............................................................................................................................................................. 437
Appendix A: Data Sheet Revision History.......................................................................................................................................... 449
Appendix B: Migrating From Other PIC® Devices.............................................................................................................................. 449
Index .................................................................................................................................................................................................. 451
The Microchip Web Site ..................................................................................................................................................................... 459
Customer Change Notification Service .............................................................................................................................................. 459
Customer Support .............................................................................................................................................................................. 459
Reader Response .............................................................................................................................................................................. 460
Product Identification System ............................................................................................................................................................ 461

PIC16(L)F1933
TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System

Register on our web site at www.microchip.com to receive the most current information on all of our products.

PIC16(L)F1933
1.0 DEVICE OVERVIEW
The PIC16(L)F1933 are described within this data
sheet. They are available in 28-pin packages.
Figure 1-1 shows a block diagram of the
PIC16(L)F1933 devices. Table 1-2 shows the pinout
descriptions.
Reference Table 1-1 for peripherals available per
device.
TABLE 1-1: DEVICE PERIPHERAL

SUMMARY
PIC16LF1933
Peripheral PIC16F1933
ADC ● ●
Capacitive Sensing Module ● ●
Digital-to-Analog Converter (DAC) ● ●
EUSART ● ●
Fixed Voltage Reference (FVR) ● ●
LCD ● ●
SR Latch ● ●
Temperature Indicator ● ●
Capture/Compare/PWM Modules
ECCP1 ● ●
ECCP2 ● ●
ECCP3 ● ●
CCP4 ● ●
CCP5 ● ●
Comparators
C1 ● ●
C2 ● ●
Master Synchronous Serial Ports
MSSP1 ● ●
Timers
Timer0 ● ●
Timer1 ● ●
Timer2 ● ●
Timer4 ● ●
Timer6 ● ●

PIC16(L)F1933
FIGURE 1-1: PIC16(L)F1933 BLOCK DIAGRAM
Program
Flash Memory
RAM EEPROM
PORTA
OSC2/CLKOUT Timing
Generation
OSC1/CLKIN CPU PORTB

INTRC
Oscillator
Figure 2-1
PORTC
MCLR
PORTE
SR ADC
Latch 10-Bit Timer0 Timer1 Timer2 Timer4 Timer6 Comparators
LCD ECCP1 ECCP2 ECCP3 CCP4 CCP5 MSSP EUSART
Note 1: See applicable chapters for more information on peripherals.

PIC16(L)F1933
TABLE 1-2: PIC16(L)F1933 PINOUT DESCRIPTION

Input Output
Name Function Description
Type Type
RA0/AN0/C12IN0-/C2OUT(1)/ RA0 TTL CMOS General purpose I/O.

SRNQ(1)/SS(1)/VCAP(2)/SEG12 AN0 AN — A/D Channel input.
C12IN0- AN — Comparator negative input.
C2OUT — CMOS Comparator output.
SRNQ — CMOS SR latch inverting output.
SS ST — Slave Select input.
VCAP Power Power Filter capacitor for Voltage Regulator (PIC16F1933 only).
SEG12 — AN LCD Analog output.
RA1/AN1/C12IN1-/SEG7 RA1 TTL CMOS General purpose I/O.
AN1 AN — A/D Channel input.
RA2/AN2/C2IN+/VREF-/ RA2 TTL CMOS General purpose I/O.
DACOUT/COM2 AN2 AN — A/D Channel input.
C2IN+ AN — Comparator positive input.
VREF- AN — A/D Negative Voltage Reference input.
DACOUT — AN Voltage Reference output.
COM2 — AN LCD Analog output.
RA3/AN3/C1IN+/VREF+/ RA3 TTL CMOS General purpose I/O.
COM3/SEG15 AN3 AN — A/D Channel input.
C1IN+ AN — Comparator positive input.
VREF+ AN — A/D Voltage Reference input.
RA4/C1OUT/CPS6/T0CKI/SRQ/ RA4 TTL CMOS General purpose I/O.
CCP5/SEG4 C1OUT — CMOS Comparator output.
CPS6 AN — Capacitive sensing input.
T0CKI ST — Timer0 clock input.
SRQ — CMOS SR latch non-inverting output.
CCP5 ST CMOS Capture/Compare/PWM.
RA5/AN4/C2OUT(1)/CPS7/ RA5 TTL CMOS General purpose I/O.
SRNQ(1)/SS(1)/VCAP(2)/SEG5 AN4 AN — A/D Channel input.
C2OUT — CMOS Comparator output.
SRNQ — CMOS SR latch inverting output.
SS ST — Slave Select input.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: Pin function is selectable via the APFCON register.

PIC16(L)F1933
TABLE 1-2: PIC16(L)F1933 PINOUT DESCRIPTION (CONTINUED)
Input Output
Type Type
RA6/OSC2/CLKOUT/VCAP(2)/ RA6 TTL CMOS General purpose I/O.
SEG1 OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).
CLKOUT — CMOS FOSC/4 output.
RA7/OSC1/CLKIN/SEG2 RA7 TTL CMOS General purpose I/O.
OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes).
CLKIN CMOS — External clock input (EC mode).
RB0/AN12/CPS0/CCP4/SRI/INT/ RB0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
SEG0 Individually enabled pull-up.
SRI — ST SR latch input.
INT ST — External interrupt.
SEG0 — AN LCD analog output.
RB1/AN10/C12IN3-/CPS1/P1C/ RB1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
VLCD1 Individually enabled pull-up.
P1C — CMOS PWM output.
VLCD1 AN — LCD analog input.
RB2/AN8/CPS2/P1B/VLCD2 RB2 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
P1B — CMOS PWM output.
RB3/AN9/C12IN2-/CPS3/ RB3 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
CCP2(1)/P2A(1)/VLCD3 Individually enabled pull-up.
P2A — CMOS PWM output.
RB4/AN11/CPS4/P1D/COM0 RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
P1D — CMOS PWM output.

PIC16(L)F1933
Input Output
Type Type
RB5/AN13/CPS5/P2B/CCP3(1)/ RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
P3A(1)/T1G(1)/COM1 Individually enabled pull-up.
T1G ST — Timer1 gate input.
RB6/ICSPCLK/ICDCLK/SEG14 RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
ICSPCLK ST — Serial Programming Clock.
ICDCLK ST — In-Circuit Debug Clock.
RB7/ICSPDAT/ICDDAT/SEG13 RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
ICSPDAT ST CMOS ICSP™ Data I/O.
ICDDAT ST CMOS In-Circuit Data I/O.
RC0/T1OSO/T1CKI/P2B(1) RC0 ST CMOS General purpose I/O.
T1OSO XTAL XTAL Timer1 oscillator connection.
T1CKI ST — Timer1 clock input.
RC1/T1OSI/CCP2(1)/P2A(1) RC1 ST CMOS General purpose I/O.
T1OSI XTAL XTAL Timer1 oscillator connection.
RC2/CCP1/P1A/SEG3 RC2 ST CMOS General purpose I/O.
RC3/SCK/SCL/SEG6 RC3 ST CMOS General purpose I/O.
SCK ST CMOS SPI clock.
SCL I2C OD I2C™ clock.
RC4/SDI/SDA/T1G(1)/SEG11 RC4 ST CMOS General purpose I/O.
SDI ST — SPI data input.
SDA I2C OD I2C™ data input/output.
T1G ST — Timer1 gate input.
RC5/SDO/SEG10 RC5 ST CMOS General purpose I/O.
SDO — CMOS SPI data output.

PIC16(L)F1933
Input Output
Type Type
RC6/TX/CK/CCP3/P3A/SEG9 RC6 ST CMOS General purpose I/O.
TX — CMOS USART asynchronous transmit.
CK ST CMOS USART synchronous clock.
RC7/RX/DT/P3B/SEG8 RC7 ST CMOS General purpose I/O.
RX ST — USART asynchronous input.
DT ST CMOS USART synchronous data.
RE3/MCLR/VPP RE3 TTL — General purpose input.
MCLR ST — Master Clear with internal pull-up.
VPP HV — Programming voltage.
VDD VDD Power — Positive supply.
VSS VSS Power — Ground reference.

PIC16(L)F1933
2.0 ENHANCED MID-RANGE CPU
This family of devices contain an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect, and
Relative addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.
• Automatic Interrupt Context Saving
• 16-level Stack with Overflow and Underflow
• File Select Registers
• Instruction Set
2.1 Automatic Interrupt Context

Saving
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 7.5 “Automatic Context Saving”,
for more information.
2.2 16-level Stack with Overflow and

Underflow
These devices have an external stack memory 15 bits
wide and 16 words deep. A Stack Overflow or
Underflow will set the appropriate bit (STKOVF or
STKUNF) in the PCON register, and if enabled will
cause a software Reset. See section Section 3.5
“Stack” for more details.
2.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one Data Pointer for all memory. When an
FSR points to program memory, there is one additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See
Section 3.6 “Indirect Addressing” for more details.
2.4 Instruction Set

There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See
Section 29.0 “Instruction Set Summary” for more
details.

PIC16(L)F1933
FIGURE 2-1: CORE BLOCK DIAGRAM
15
Configuration
Configuration 8
15 Data Bus
Program Counter
Flash
MUX
Program
Memory 16-Level
8 Level Stack
Stack
RAM
(13-bit)
(15-bit)
Program
14 Program Memory 12 RAM Addr
Bus
Read (PMR)
Addr MUX
Instruction
Instruction Reg
reg Indirect
Direct Addr 7 Addr
5 12 12
15 BSR
FSR Reg
reg
FSR0reg
FSR Reg
FSR1 Reg
FSR reg
15 STATUS Reg
STATUS reg
8
3 MUX
Power-up
Timer
Instruction Oscillator
Decodeand
Decode & Start-up Timer ALU
Control
OSC1/CLKIN Power-on
Reset 8
Timing Watchdog
OSC2/CLKOUT Generation Timer W reg
Brown-out
Reset
Internal
Oscillator
Block
VDD VSS

PIC16(L)F1933
3.0 MEMORY ORGANIZATION The following features are associated with access and
control of program memory and data memory:
These devices contain the following types of memory:
• PCL and PCLATH
• Program Memory • Stack
- Configuration Words • Indirect Addressing
- Device ID
- User ID 3.1 Program Memory Organization
- Flash Program Memory
The enhanced mid-range core has a 15-bit program
• Data Memory
counter capable of addressing a 32K x 14 program
- Core Registers memory space. Table 3-1 shows the memory sizes
- Special Function Registers implemented for the PIC16(L)F1933 family. Accessing a
- General Purpose RAM location above these boundaries will cause a
- Common RAM wrap-around within the implemented memory space.
The Reset vector is at 0000h and the interrupt vector is
• Data EEPROM memory(1)
at 0004h (see Figure 3-1).
Note 1: The Data EEPROM Memory and the

method to access Flash memory through
the EECON registers is described in
Section 11.0 “Data EEPROM and Flash
Program Memory Control”.
TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device Program Memory Space (Words) Last Program Memory Address
PIC16(L)F1933 4,096 0FFFh

PIC16(L)F1933
FIGURE 3-1: PROGRAM MEMORY MAP 3.1.1 READING PROGRAM MEMORY AS
AND STACK FOR DATA
4 KW PARTS There are two methods of accessing constants in
program memory. The first method is to use tables of
PC<14:0> RETLW instructions. The second method is to set an
FSR to point to the program memory.
CALL, CALLW 15
RETURN, RETLW
Interrupt, RETFIE 3.1.1.1 RETLW Instruction
Stack Level 0 The RETLW instruction can be used to provide access
Stack Level 1 to tables of constants. The recommended way to create
such a table is shown in Example 3-1.
Stack Level 15 EXAMPLE 3-1: RETLW INSTRUCTION

constants
Reset Vector 0000h BRW ;Add Index in W to
;program counter to
;select data
Interrupt Vector 0004h RETLW DATA0 ;Index0 data
0005h RETLW DATA1 ;Index1 data
RETLW DATA2
Page 0
On-chip 07FFh RETLW DATA3
Program
Memory 0800h
Page 1 my_function
0FFFh ;… LOTS OF CODE…
1000h MOVLW DATA_INDEX
Rollover to Page 0 call constants
;… THE CONSTANT IS IN W
The BRW instruction makes this type of table very

simple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available so the older table read
method must be used.
Rollover to Page 1
7FFFh

PIC16(L)F1933
3.1.1.2 Indirect Read with FSR 3.2.1 CORE REGISTERS
The program memory can be accessed as data by The core registers contain the registers that directly
setting bit 7 of the FSRxH register and reading the affect the basic operation of the PIC16(L)F1933. These
matching INDFx register. The MOVIW instruction will registers are listed below:
place the lower eight bits of the addressed word in the • INDF0
W register. Writes to the program memory cannot be
• INDF1
performed via the INDF registers. Instructions that
access the program memory via the FSR require one • PCL
extra instruction cycle to complete. Example 3-2 • STATUS
demonstrates accessing the program memory via an • FSR0 Low
FSR. • FSR0 High
The HIGH directive will set bit<7> if a label points to a • FSR1 Low
location in program memory. • FSR1 High
• BSR
EXAMPLE 3-2: ACCESSING PROGRAM
• WREG
MEMORY VIA FSR
• PCLATH
constants
RETLW DATA0 ;Index0 data • INTCON
RETLW DATA1 ;Index1 data Note: The core registers are the first 12
RETLW DATA2 addresses of every data memory bank.
RETLW DATA3
my_function
;… LOTS OF CODE…
MOVLW LOW constants
MOVWF FSR1L
MOVLW HIGH constants
MOVWF FSR1H
MOVIW 0[FSR1]
;THE PROGRAM MEMORY IS IN W
3.2 Data Memory Organization

The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(Figure 3-2):
• 12 core registers
• 20 Special Function Registers (SFR)
• Up to 80 bytes of General Purpose RAM (GPR)
• 16 bytes of common RAM
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.6 “Indirect
Addressing” for more information.

PIC16(L)F1933
3.2.1.1 STATUS Register For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
The STATUS register, shown in Register 3-1, contains:
as ‘000u u1uu’ (where u = unchanged).
• the arithmetic status of the ALU
It is recommended, therefore, that only BCF, BSF,
• the Reset status SWAPF and MOVWF instructions are used to alter the
The STATUS register can be the destination for any STATUS register, because these instructions do not
instruction, like any other register. If the STATUS affect any Status bits. For other instructions not
register is the destination for an instruction that affects affecting any Status bits (Refer to Section 29.0
the Z, DC or C bits, then the write to these three bits is “Instruction Set Summary”).
disabled. These bits are set or cleared according to the
Note 1: The C and DC bits operate as Borrow
device logic. Furthermore, the TO and PD bits are not
and Digit Borrow out bits, respectively, in
writable. Therefore, the result of an instruction with the
subtraction.
STATUS register as destination may be different than
intended.
3.3 Register Definitions: Status
REGISTER 3-1: STATUS: STATUS REGISTER
U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u
— — — TO PD Z DC(1) C(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7-5 Unimplemented: Read as ‘0’

bit 4 TO: Time-Out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.

PIC16(L)F1933
3.3.1 SPECIAL FUNCTION REGISTER FIGURE 3-2: BANKED MEMORY
The Special Function Registers (SFRs) are registers PARTITIONING
used by the application to control the desired operation
of peripheral functions in the device. The Special Memory Region
7-bit Bank Offset
Function Registers occupy the 20 bytes after the core
registers of every data memory bank (addresses
x0Ch/x8Ch through x1Fh/x9Fh). The registers associ- 00h
ated with the operation of the peripherals are described Core Registers
in the appropriate peripheral chapter of this data sheet. (12 bytes)
0Bh
3.3.2 GENERAL PURPOSE RAM 0Ch
There are up to 80 bytes of GPR in each data memory Special Function Registers
bank. (20 bytes maximum)
1Fh
3.3.2.1 Linear Access to GPR
20h
The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.6.2
“Linear Data Memory” for more information.
3.3.3 COMMON RAM General Purpose RAM

There are 16 bytes of common RAM accessible from all (80 bytes maximum)
banks.
6Fh
70h
Common RAM
(16 bytes)
7Fh
3.3.4 DEVICE MEMORY MAPS

The memory maps for the device family are as shown
in Table 3-2.
TABLE 3-2: MEMORY MAP TABLES

Device Banks Table No.
PIC16F1933 0-7 Table 3-3
PIC16LF1933 8-15 Table 3-4,Table 3-7
16-23 Table 3-5
23-31 Table 3-6, Table 3-8

TABLE 3-3: PIC16(L)F1933 MEMORY MAP, BANKS 0-7
DS41575C-page 20
PIC16(L)F1933
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h INDF0 080h INDF0 100h INDF0 180h INDF0 200h INDF0 280h INDF0 300h INDF0 380h INDF0
002h PCL 082h PCL 102h PCL 182h PCL 202h PCL 282h PCL 302h PCL 382h PCL
003h STATUS 083h STATUS 103h STATUS 183h STATUS 203h STATUS 283h STATUS 303h STATUS 383h STATUS
004h FSR0L 084h FSR0L 104h FSR0L 184h FSR0L 204h FSR0L 284h FSR0L 304h FSR0L 384h FSR0L
005h FSR0H 085h FSR0H 105h FSR0H 185h FSR0H 205h FSR0H 285h FSR0H 305h FSR0H 385h FSR0H
008h BSR 088h BSR 108h BSR 188h BSR 208h BSR 288h BSR 308h BSR 388h BSR
009h WREG 089h WREG 109h WREG 189h WREG 209h WREG 289h WREG 309h WREG 389h WREG
00Ah PCLATH 08Ah PCLATH 10Ah PCLATH 18Ah PCLATH 20Ah PCLATH 28Ah PCLATH 30Ah PCLATH 38Ah PCLATH
00Bh INTCON 08Bh INTCON 10Bh INTCON 18Bh INTCON 20Bh INTCON 28Bh INTCON 30Bh INTCON 38Bh INTCON
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch — 28Ch — 30Ch — 38Ch —
00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh — 30Dh — 38Dh —
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh — 20Eh — 28Eh — 30Eh — 38Eh —
00Fh — 08Fh — 10Fh — 18Fh — 20Fh — 28Fh — 30Fh — 38Fh —
010h PORTE 090h TRISE 110h — 190h — 210h WPUE 290h — 310h — 390h —
011h PIR1 091h PIE1 111h CM1CON0 191h EEADRL 211h SSPBUF 291h CCPR1L 311h CCPR3L 391h —
012h PIR2 092h PIE2 112h CM1CON1 192h EEADRH 212h SSPADD 292h CCPR1H 312h CCPR3H 392h —
013h PIR3 093h PIE3 113h CM2CON0 193h EEDATL 213h SSPMSK 293h CCP1CON 313h CCP3CON 393h —
014h — 094h — 114h CM2CON1 194h EEDATH 214h SSPSTAT 294h PWM1CON 314h PWM3CON 394h IOCBP
015h TMR0 095h OPTION_REG 115h CMOUT 195h EECON1 215h SSPCON1 295h CCP1AS 315h CCP3AS 395h IOCBN
016h TMR1L 096h PCON 116h BORCON 196h EECON2 216h SSPCON2 296h PSTR1CON 316h PSTR3CON 396h IOCBF
017h TMR1H 097h WDTCON 117h FVRCON 197h — 217h SSPCON3 297h — 317h — 397h —
018h T1CON 098h OSCTUNE 118h DACCON0 198h — 218h — 298h CCPR2L 318h CCPR4L 398h —
019h T1GCON 099h OSCCON 119h DACCON1 199h RCREG 219h — 299h CCPR2H 319h CCPR4H 399h —
01Ah TMR2 09Ah OSCSTAT 11Ah SRCON0 19Ah TXREG 21Ah — 29Ah CCP2CON 31Ah CCP4CON 39Ah —
01Bh PR2 09Bh ADRESL 11Bh SRCON1 19Bh SPBRGL 21Bh — 29Bh PWM2CON 31Bh — 39Bh —
01Ch T2CON 09Ch ADRESH 11Ch — 19Ch SPBRGH 21Ch — 29Ch CCP2AS 31Ch CCPR5L 39Ch —
01Dh — 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh — 29Dh PSTR2CON 31Dh CCPR5H 39Dh —
01Eh CPSCON0 09Eh ADCON1 11Eh — 19Eh TXSTA 21Eh — 29Eh CCPTMRS0 31Eh CCP5CON 39Eh —
 2011-2012 Microchip Technology Inc.
01Fh CPSCON1 09Fh — 11Fh — 19Fh BAUDCTR 21Fh — 29Fh CCPTMRS1 31Fh — 39Fh —
020h 0A0h 120h 1A0h 220h 2A0h 320h 3A0h
General General General
Purpose Purpose Purpose Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented
Register Register Register Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’
80 Bytes 80 Bytes 80 Bytes
06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh

070h 0F0h 170h 1F0h 270h 2F0h 370h 3F0h
Accesses Accesses Accesses Accesses Accesses Accesses Accesses
Common RAM
70h – 7Fh 70h – 7Fh 70h – 7Fh) 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh
Legend: = Unimplemented data memory locations, read as ‘0’.

DS41575C-page 21
PIC16(L)F1933
402h PCL 482h PCL 502h PCL 582h PCL 602h PCL 682h PCL 702h PCL 782h PCL
403h STATUS 483h STATUS 503h STATUS 583h STATUS 603h STATUS 683h STATUS 703h STATUS 783h STATUS
408h BSR 488h BSR 508h BSR 588h BSR 608h BSR 688h BSR 708h BSR 788h BSR
409h WREG 489h WREG 509h WREG 589h WREG 609h WREG 689h WREG 709h WREG 789h WREG
40Ah PCLATH 48Ah PCLATH 50Ah PCLATH 58Ah PCLATH 60Ah PCLATH 68Ah PCLATH 70Ah PCLATH 78Ah PCLATH
40Bh INTCON 48Bh INTCON 50Bh INTCON 58Bh INTCON 60Bh INTCON 68Bh INTCON 70Bh INTCON 78Bh INTCON
40Ch — 48Ch — 50Ch — 58Ch — 60Ch — 68Ch — 70Ch — 78Ch —
40Dh — 48Dh — 50Dh — 58Dh — 60Dh — 68Dh — 70Dh — 78Dh —
40Eh — 48Eh — 50Eh — 58Eh — 60Eh — 68Eh — 70Eh — 78Eh —
40Fh — 48Fh — 50Fh — 58Fh — 60Fh — 68Fh — 70Fh — 78Fh —
410h — 490h — 510h — 590h — 610h — 690h — 710h — 790h —
411h — 491h — 511h — 591h — 611h — 691h — 711h — 791h
412h — 492h — 512h — 592h — 612h — 692h — 712h — 792h
413h — 493h — 513h — 593h — 613h — 693h — 713h — 793h
414h — 494h — 514h — 594h — 614h — 694h — 714h — 794h
415h TMR4 495h — 515h — 595h — 615h — 695h — 715h — 795h
416h PR4 496h — 516h — 596h — 616h — 696h — 716h — 796h
417h T4CON 497h — 517h — 597h — 617h — 697h — 717h — 797h
418h — 498h — 518h — 598h — 618h — 698h — 718h — 798h
419h — 499h — 519h — 599h — 619h — 699h — 719h — 799h
41Ah — 49Ah — 51Ah — 59Ah — 61Ah — 69Ah — 71Ah — 79Ah
41Bh — 49Bh — 51Bh — 59Bh — 61Bh — 69Bh — 71Bh — 79Bh See Table 3-7
41Ch TMR6 49Ch — 51Ch — 59Ch — 61Ch — 69Ch — 71Ch — 79Ch
41Dh PR6 49Dh — 51Dh — 59Dh — 61Dh — 69Dh — 71Dh — 79Dh
41Eh T6CON 49Eh — 51Eh — 59Eh — 61Eh — 69Eh — 71Eh — 79Eh
41Fh — 49Fh — 51Fh — 59Fh — 61Fh — 69Fh — 71Fh — 79Fh

420h 4A0h 520h 5A0h 620h 6A0h 720h 7A0h
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented

Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’
46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh

470h 4F0h 570h 5F0h 670h 6F0h 770h 7F0h
Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses
70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh
47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh

DS41575C-page 22
PIC16(L)F1933
800h INDF0 880h INDF0 900h INDF0 980h INDF0 A00h INDF0 A80h INDF0 B00h INDF0 B80h INDF0
801h INDF1 881h INDF1 901h INDF1 981h INDF1 A01h INDF1 A81h INDF1 B01h INDF1 B81h INDF1
802h PCL 882h PCL 902h PCL 982h PCL A02h PCL A82h PCL B02h PCL B82h PCL
803h STATUS 883h STATUS 903h STATUS 983h STATUS A03h STATUS A83h STATUS B03h STATUS B83h STATUS
804h FSR0L 884h FSR0L 904h FSR0L 984h FSR0L A04h FSR0L A84h FSR0L B04h FSR0L B84h FSR0L
805h FSR0H 885h FSR0H 905h FSR0H 985h FSR0H A05h FSR0H A85h FSR0H B05h FSR0H B85h FSR0H
806h FSR1L 886h FSR1L 906h FSR1L 986h FSR1L A06h FSR1L A86h FSR1L B06h FSR1L B86h FSR1L
807h FSR1H 887h FSR1H 907h FSR1H 987h FSR1H A07h FSR1H A87h FSR1H B07h FSR1H B87h FSR1H
808h BSR 888h BSR 908h BSR 988h BSR A08h BSR A88h BSR B08h BSR B88h BSR
809h WREG 889h WREG 909h WREG 989h WREG A09h WREG A89h WREG B09h WREG B89h WREG
80Ah PCLATH 88Ah PCLATH 90Ah PCLATH 98Ah PCLATH A0Ah PCLATH A8Ah PCLATH B0Ah PCLATH B8Ah PCLATH
80Bh INTCON 88Bh INTCON 90Bh INTCON 98Bh INTCON A0Bh INTCON A8Bh INTCON B0Bh INTCON B8Bh INTCON
80Ch — 88Ch — 90Ch — 98Ch — A0Ch — A8Ch — B0Ch — B8Ch —
80Dh — 88Dh — 90Dh — 98Dh — A0Dh — A8Dh — B0Dh — B8Dh —
80Eh — 88Eh — 90Eh — 98Eh — A0Eh — A8Eh — B0Eh — B8Eh —
80Fh — 88Fh — 90Fh — 98Fh — A0Fh — A8Fh — B0Fh — B8Fh —
810h — 890h — 910h — 990h — A10h — A90h — B10h — B90h —
811h — 891h — 911h — 991h — A11h — A91h — B11h — B91h —
812h — 892h — 912h — 992h — A12h — A92h — B12h — B92h —
813h — 893h — 913h — 993h — A13h — A93h — B13h — B93h —
814h — 894h — 914h — 994h — A14h — A94h — B14h — B94h —
815h — 895h — 915h — 995h — A15h — A95h — B15h — B95h —
816h — 896h — 916h — 996h — A16h — A96h — B16h — B96h —
817h — 897h — 917h — 997h — A17h — A97h — B17h — B97h —
818h — 898h — 918h — 998h — A18h — A98h — B18h — B98h —
819h — 899h — 919h — 999h — A19h — A99h — B19h — B99h —
81Ah — 89Ah — 91Ah — 99Ah — A1Ah — A9Ah — B1Ah — B9Ah —
81Bh — 89Bh — 91Bh — 99Bh — A1Bh — A9Bh — B1Bh — B9Bh —
81Ch — 89Ch — 91Ch — 99Ch — A1Ch — A9Ch — B1Ch — B9Ch —
81Dh — 89Dh — 91Dh — 99Dh — A1Dh — A9Dh — B1Dh — B9Dh —
81Eh — 89Eh — 91Eh — 99Eh — A1Eh — A9Eh — B1Eh — B9Eh —
81Fh — 89Fh — 91Fh — 99Fh — A1Fh — A9Fh — B1Fh — B9Fh —

820h 8A0h 920h 9A0h A20h AA0h B20h BA0h
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented

Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’
86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh

870h 8F0h 970h 9F0h A70h AF0h B70h BF0h
87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh

DS41575C-page 23
PIC16(L)F1933
C00h INDF0 C80h INDF0 D00h INDF0 D80h INDF0 E00h INDF0 E80h INDF0 F00h INDF0 F80h INDF0
C01h INDF1 C81h INDF1 D01h INDF1 D81h INDF1 E01h INDF1 E81h INDF1 F01h INDF1 F81h INDF1
C02h PCL C82h PCL D02h PCL D82h PCL E02h PCL E82h PCL F02h PCL F82h PCL
C03h STATUS C83h STATUS D03h STATUS D83h STATUS E03h STATUS E83h STATUS F03h STATUS F83h STATUS
C04h FSR0L C84h FSR0L D04h FSR0L D84h FSR0L E04h FSR0L E84h FSR0L F04h FSR0L F84h FSR0L
C05h FSR0H C85h FSR0H D05h FSR0H D85h FSR0H E05h FSR0H E85h FSR0H F05h FSR0H F85h FSR0H
C06h FSR1L C86h FSR1L D06h FSR1L D86h FSR1L E06h FSR1L E86h FSR1L F06h FSR1L F86h FSR1L
C07h FSR1H C87h FSR1H D07h FSR1H D87h FSR1H E07h FSR1H E87h FSR1H F07h FSR1H F87h FSR1H
C08h BSR C88h BSR D08h BSR D88h BSR E08h BSR E88h BSR F08h BSR F88h BSR
C09h WREG C89h WREG D09h WREG D89h WREG E09h WREG E89h WREG F09h WREG F89h WREG
C0Ah PCLATH C8Ah PCLATH D0Ah PCLATH D8Ah PCLATH E0Ah PCLATH E8Ah PCLATH F0Ah PCLATH F8Ah PCLATH
C0Bh INTCON C8Bh INTCON D0Bh INTCON D8Bh INTCON E0Bh INTCON E8Bh INTCON F0Bh INTCON F8Bh INTCON
C0Ch — C8Ch — D0Ch — D8Ch — E0Ch — E8Ch — F0Ch — F8Ch
C0Dh — C8Dh — D0Dh — D8Dh — E0Dh — E8Dh — F0Dh — F8Dh
C0Eh — C8Eh — D0Eh — D8Eh — E0Eh — E8Eh — F0Eh — F8Eh
C0Fh — C8Fh — D0Fh — D8Fh — E0Fh — E8Fh — F0Fh — F8Fh
C10h — C90h — D10h — D90h — E10h — E90h — F10h — F90h
C18h — C98h — D18h — D98h — E18h — E98h — F18h — F98h See Table 3-8
C1Ah — C9Ah — D1Ah — D9Ah — E1Ah — E9Ah — F1Ah — F9Ah
C1Bh — C9Bh — D1Bh — D9Bh — E1Bh — E9Bh — F1Bh — F9Bh
C1Ch — C9Ch — D1Ch — D9Ch — E1Ch — E9Ch — F1Ch — F9Ch
C1Dh — C9Dh — D1Dh — D9Dh — E1Dh — E9Dh — F1Dh — F9Dh
C1Eh — C9Eh — D1Eh — D9Eh — E1Eh — E9Eh — F1Eh — F9Eh
C1Fh — C9Fh — D1Fh — D9Fh — E1Fh — E9Fh — F1Fh — F9Fh

C20h CA0h D20h DA0h E20h EA0h F20h FA0h
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented

Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’
C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh

C70h CF0h D70h DF0h E70h EF0h F70h FF0h
CFFh CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh

PIC16(L)F1933
TABLE 3-7: PIC16(L)F1933 MEMORY MAP, TABLE 3-8: PIC16(L)F1933 MEMORY MAP,
BANK 15 BANK 31
Bank 15 Bank 31
791h LCDCON F8Ch
792h LCDPS
Unimplemented
793h LCDREF
Read as ‘0’
794h LCDCST
795h LCDRL FE3h
796h — FE4h STATUS_SHAD
797h — FE5h WREG_SHAD
798h LCDSE0 BSR_SHAD
FE6h
799h LCDSE1 PCLATH_SHAD
FE7h
79Ah — FSR0L_SHAD
FE8h
79Bh — FSR0H_SHAD
FE9h
79Ch — FSR1L_SHAD
FEAh
79Dh — FSR1H_SHAD
FEBh
79Eh — —
FECh
79Fh —
FEDh STKPTR
7A0h LCDDATA0
7A1h LCDDATA1 FEEh TOSL
7A2h — FEFh TOSH
7A3h LCDDATA3 Legend: = Unimplemented data memory locations, read
7A4h LCDDATA4 as ‘0’.
7A5h —
7A6h LCDDATA6
7A7h LCDDATA7
7A8h — 3.3.5 SPECIAL FUNCTION REGISTERS
7A9h LCDDATA9 SUMMARY
7AAh LCDDATA10
7ABh — The Special Function Register Summary for the device
7ACh — family are as follows:
7ADh —
7AEh — Device Bank(s) Page No.
7AFh —
—
0 25
7B0h
7B1h — 1 26
7B2h —
2 27
7B3h —
7B4h — 3 28
7B5h — 4 29
7B6h —
7B7h — 5 30
7B8h PIC16(L)F1933 6 31
Unimplemented 7 32
Read as ‘0’
8 33
7EFh 9-14 34
Legend: = Unimplemented data memory locations, read 15 35
as ‘0’.
16-30 36
31 37

PIC16(L)F1933
=
TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY
Value on all
Value on
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other
POR, BOR
Resets
Bank 0
000h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
002h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
003h(2) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
004h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
005h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
008h(2) BSR — — — BSR<4:0> ---0 0000 ---0 0000
009h(2) WREG Working Register 0000 0000 uuuu uuuu
00Ah(1, 2) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
00Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
00Ch PORTA PORTA Data Latch when written: PORTA pins when read xxxx xxxx uuuu uuuu
00Dh PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
00Eh PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
00Fh — Unimplemented — —
010h PORTE — — — — RE3 — — — ---- x--- ---- u---
011h PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
012h PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF — CCP2IF 0000 00-0 0000 00-0
013h PIR3 — CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF — -000 0-0- -000 0-0-
014h — Unimplemented — —
015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
018h T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 0000 00-0 uuuu uu-u
019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu
DONE
01Ah TMR2 Timer 2 Module Register 0000 0000 0000 0000
01Bh PR2 Timer 2 Period Register 1111 1111 1111 1111
01Ch T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000
01Dh — Unimplemented — —
01Eh CPSCON0 CPSON CPSRM — — CPSRNG1 CPSRNG0 CPSOUT T0XCS 00-- 0000 00-- 0000
01Fh CPSCON1 — — — — — CPSCH<2:0> ---- -000 ---- -000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.

PIC16(L)F1933
TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
Value on
POR, BOR
Resets
Bank 1
088h(2) BSR — — — BSR<4:0> ---0 0000 ---0 0000
08Ch TRISA PORTA Data Direction Register 1111 1111 1111 1111
08Dh TRISB PORTB Data Direction Register 1111 1111 1111 1111
08Eh TRISC PORTC Data Direction Register 1111 1111 1111 1111
090h TRISE — — — — —(3) — — — ---- 1--- ---- 1---
091h PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
092h PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE 0000 00-0 0000 00-0
093h PIE3 — CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE — -000 0-0- -000 0-0-
095h OPTION_REG WPUEN INTEDG TMROCS TMROSE PSA PS<2:0> 1111 1111 1111 1111
096h PCON STKOVF STKUNF — — RMCLR RI POR BOR 00-- 11qq qq-- qquu
097h WDTCON — — WDTPS<4:0> SWDTEN --01 0110 --01 0110
098h OSCTUNE — — TUN<5:0> --00 0000 --00 0000
099h OSCCON SPLLEN IRCF<3:0> — SCS<1:0> 0011 1-00 0011 1-00
09Ah OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 00q0 0q0- qqqq qq0-
09Bh ADRESL A/D Result Register Low xxxx xxxx uuuu uuuu
09Ch ADRESH A/D Result Register High xxxx xxxx uuuu uuuu
09Dh ADCON0 — CHS<4:0> GO/DONE ADON -000 0000 -000 0000
09Eh ADCON1 ADFM ADCS<2:0> — ADNREF ADPREF1 ADPREF0 0000 -000 0000 -000

PIC16(L)F1933
Value on all
Value on
POR, BOR
Resets
Bank 2
108h(2) BSR — — — BSR<4:0> ---0 0000 ---0 0000
10Ch LATA PORTA Data Latch xxxx xxxx uuuu uuuu
10Dh LATB PORTB Data Latch xxxx xxxx uuuu uuuu
10Eh LATC PORTC Data Latch xxxx xxxx uuuu uuuu
111h CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 0000 -100 0000 -100
112h CM1CON1 C1INTP C1INTN C1PCH1 C1PCH0 — — C1NCH<1:0> 0000 --00 0000 --00
113h CM2CON0 C2ON C2OUT C2OE C2POL — C2SP C2HYS C2SYNC 0000 -100 0000 -100
114h CM2CON1 C2INTP C2INTN C2PCH1 C2PCH0 — — C2NCH<1:0> 0000 --00 0000 --00
115h CMOUT — — — — — — MC2OUT MC1OUT ---- --00 ---- --00
116h BORCON SBOREN — — — — — — BORRDY 1--- ---q u--- ---u
117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR<1:0> 0q00 0000 0q00 0000
118h DACCON0 DACEN DACLPS DACOE --- DACPSS<1:0> --- DACNSS 000- 00-0 000- 00-0
119h DACCON1 --- --- --- DACR<4:0> ---0 0000 ---0 0000
11Ah SRCON0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 0000 0000 0000 0000
11Bh SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 0000 0000
11Ch — Unimplemented — —
11Dh APFCON — CCP3SEL T1GSEL P2BSEL SRNQSEL C2OUTSEL SSSEL CCP2SEL -000 0000 -000 0000
11Eh — Unimplemented — —

PIC16(L)F1933
Value on all
Value on
POR, BOR
Resets
Bank 3
188h(2) BSR — — — BSR<4:0> ---0 0000 ---0 0000
18Ch ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 --11 1111 --11 1111
18Dh ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111
191h EEADRL EEPROM / Program Memory Address Register Low Byte 0000 0000 0000 0000
192h EEADRH —(3) EEPROM / Program Memory Address Register High Byte 1000 0000 1000 0000
193h EEDATL EEPROM / Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu
194h EEDATH — — EEPROM / Program Memory Read Data Register High Byte --xx xxxx --uu uuuu
195h EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 0000 x000 0000 q000
196h EECON2 EEPROM control register 2 0000 0000 0000 0000
199h RCREG USART Receive Data Register 0000 0000 0000 0000
19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000
19Bh SPBRGL BRG<7:0> 0000 0000 0000 0000
19Ch SPBRGH BRG<15:8> 0000 0000 0000 0000
19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
19Fh BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00

PIC16(L)F1933
Value on all
Value on
POR, BOR
Resets
Bank 4
208h(2) BSR — — — BSR<4:0> ---0 0000 ---0 0000
20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111
210h WPUE — — — — WPUE3 — — — ---- 1--- ---- 1---
211h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
212h SSPADD ADD<7:0> 0000 0000 0000 0000
213h SSPMSK MSK<7:0> 1111 1111 1111 1111
214h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
215h SSPCON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000
216h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
217h SSPCON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
21Ah — Unimplemented — —
21Bh — Unimplemented — —

PIC16(L)F1933
Value on all
Value on
POR, BOR
Resets
Bank 5
288h(2) BSR — — — BSR<4:0> ---0 0000 ---0 0000
291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
293h CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 0000 0000 0000 0000
294h PWM1CON P1RSEN P1DC<6:0> 0000 0000 0000 0000
295h CCP1AS CCP1ASE CCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 0000 0000 0000 0000
296h PSTR1CON — — — STR1SYNC STR1D STR1C STR1B STR1A ---0 0001 ---0 0001
29Ah CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 0000 0000 0000 0000
29Bh PWM2CON P2RSEN P2DC<6:0> 0000 0000 0000 0000
29Ch CCP2AS CCP2ASE CCP2AS<2:0> PSS2AC<1:0> PSS2BD<1:0> 0000 0000 0000 0000
29Dh PSTR2CON — — — STR2SYNC STR2D STR2C STR2B STR2A ---0 0001 ---0 0001
29Eh CCPTMRS0 C4TSEL1 C4TSEL0 C3TSEL1 C3TSEL0 C2TSEL1 C2TSEL0 C1TSEL1 C1TSEL0 0000 0000 0000 0000
29Fh CCPTMRS1 — — — — — — C5TSEL<1:0> ---- --00 ---- --00

PIC16(L)F1933
Value on all
Value on
POR, BOR
Resets
Bank 6
308h(2) BSR — — — BSR<4:0> ---0 0000 ---0 0000
313h CCP3CON P3M<1:0> DC3B<1:0> CCP3M<1:0> 0000 0000 0000 0000
314h PWM3CON P3RSEN P3DC<6:0> 0000 0000 0000 0000
315h CCP3AS CCP3ASE CCP3AS<2:0> PSS3AC<1:0> PSS3BD<1:0> 0000 0000 0000 0000
316h PSTR3CON — — — STR3SYNC STR3D STR3C STR3B STR3A ---0 0001 ---0 0001
31Ah CCP4CON — — DC4B<1:0> CCP4M<3:0> --00 0000 --00 0000
31Ch CCPR5L Capture/Compare/PWM Register 5 (LSB) xxxx xxxx uuuu uuuu
31Dh CCPR5H Capture/Compare/PWM Register 5 (MSB) xxxx xxxx uuuu uuuu
31Eh CCP5CON — — DC5B<1:0> CCP5M<3:0> --00 0000 --00 0000

PIC16(L)F1933
Value on all
Value on
POR, BOR
Resets
Bank 7
388h(2) BSR — — — BSR<4:0> ---0 0000 ---0 0000
394h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 0000 0000 0000 0000
395h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 0000 0000 0000 0000
396h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 0000 0000 0000 0000

PIC16(L)F1933
Value on all
Value on
POR, BOR
Resets
Bank 8
408h(2) BSR — — — BSR<4:0> ---0 0000 ---0 0000
415h TMR4 Timer 4 Module Register 0000 0000 0000 0000
416h PR4 Timer 4 Period Register 1111 1111 1111 1111
417h T4CON — T4OUTPS<3:0> TMR4ON T4CKPS<1:0> -000 0000 -000 0000
41Ch TMR6 Timer 6 Module Register 0000 0000 0000 0000
41Dh PR6 Timer 6 Period Register 1111 1111 1111 1111
41Eh T6CON — T6OUTPS<3:0> TMR6ON T6CKPS<1:0> -000 0000 -000 0000

PIC16(L)F1933
Value on all
Value on
POR, BOR
Resets
Banks 9-14
x00h/ INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
x80h(2) (not a physical register)
x02h/ PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
x82h(2)
x03h/ STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
x83h(2)
x04h/ FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
x84h(2)
x05h/ FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
x85h(2)
x86h(2)
x87h(2)
x08h/ BSR — — — BSR<4:0> ---0 0000 ---0 0000
x88h(2)
x09h/ WREG Working Register 0000 0000 uuuu uuuu
x89h(2)
x0Ah/ PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
x8Ah(1),(2)
x0Bh/ INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
x8Bh(2)
x0Ch/ — Unimplemented — —
x8Ch
—
x1Fh/
x9Fh

PIC16(L)F1933
Value on all
Value on
POR, BOR
Resets
Bank 15
788h(2) BSR — — — BSR<4:0> ---0 0000 ---0 0000
—
790h
791h LCDCON LCDEN SLPEN WERR — CS<1:0> LMUX<1:0> 000- 0011 000- 0011
792h LCDPS WFT BIASMD LCDA WA LP<3:0> 0000 0000 0000 0000
793h LCDREF LCDIRE LCDIRS LCDIRI — VLCD3PE VLCD2PE VLCD1PE — 000- 000- 000- 000-
794h LCDCST — — — — — LCDCST<2:0> ---- -000 ---- -000
795h LCDRL LRLAP<1:0> LRLBP<1:0> — LRLAT<2:0> 0000 -000 0000 -000
798h LCDSE0 SE<7:0> 0000 0000 uuuu uuuu
799h LCDSE1 SE<15:8> 0000 0000 uuuu uuuu
—
79Fh
7A0h LCDDATA0 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 xxxx xxxx uuuu uuuu
COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0
7A2h — Unimplemented — —
7AAh LCDDATA10 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 xxxx xxxx uuuu uuuu
7ABh — Unimplemented — —
—
7EFh

PIC16(L)F1933
Value on all
Value on
POR, BOR
Resets
Banks 16-30
x02h/ PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
x82h(2)
x03h/ STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
x83h(2)
x84h(2)
x85h(2)
x86h(2)
x87h(2)
x08h/ BSR — — — BSR<4:0> ---0 0000 ---0 0000
x88h(2)
x09h/ WREG Working Register 0000 0000 uuuu uuuu
x89h(2)
x0Ah/ PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
x8Ah(1),(2)
x0Bh/ INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
x8Bh(2)
x0Ch/ — Unimplemented — —
x8Ch
—
x1Fh/
x9Fh

PIC16(L)F1933
Value on all
Value on
POR, BOR
Resets
Bank 31
F80h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
F81h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
F82h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
F83h(2) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
F84h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
F85h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
F86h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
F87h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
F88h(2) BSR — — — BSR<4:0> ---0 0000 ---0 0000
F89h(2) WREG Working Register 0000 0000 uuuu uuuu
F8Ah(1),(2) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
F8Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
F8Ch — Unimplemented — —
—
FE3h
FE4h STATUS_ Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu
SHAD
FE5h WREG_ Working Register Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu
SHAD
FE6h BSR_ Bank Select Register Normal (Non-ICD) Shadow ---x xxxx ---u uuuu
SHAD
FE7h PCLATH_ Program Counter Latch High Register Normal (Non-ICD) Shadow -xxx xxxx uuuu uuuu
SHAD
FE8h FSR0L_ Indirect Data Memory Address 0 Low Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu
SHAD
FE9h FSR0H_ Indirect Data Memory Address 0 High Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu
SHAD
FEAh FSR1L_ Indirect Data Memory Address 1 Low Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu
SHAD
FEBh FSR1H_ Indirect Data Memory Address 1 High Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu
SHAD
FECh — Unimplemented — —
FEDh STKPTR — — — Current Stack pointer ---1 1111 ---1 1111
FEEh TOSL Top of Stack Low byte xxxx xxxx uuuu uuuu
FEFh TOSH — Top of Stack High byte -xxx xxxx -uuu uuuu

PIC16(L)F1933
3.4 PCL and PCLATH 3.4.3 COMPUTED FUNCTION CALLS
The Program Counter (PC) is 15 bits wide. The low byte A computed function CALL allows programs to maintain
comes from the PCL register, which is a readable and tables of functions and provide another way to execute
writable register. The high byte (PC<14:8>) is not directly state machines or look-up tables. When performing a
readable or writable and comes from PCLATH. On any table read using a computed function CALL, care
Reset, the PC is cleared. Figure 3-3 shows the five should be exercised if the table location crosses a PCL
situations for the loading of the PC. memory boundary (each 256-byte block).
If using the CALL instruction, the PCH<2:0> and PCL
FIGURE 3-3: LOADING OF PC IN registers are loaded with the operand of the CALL
DIFFERENT SITUATIONS instruction. PCH<6:3> is loaded with PCLATH<6:3>.
The CALLW instruction enables computed calls by com-
14 PCH PCL 0 Instruction with
PC PCL as bining PCLATH and W to form the destination address.
Destination
A computed CALLW is accomplished by loading the W
6 7 0 8 register with the desired address and executing CALLW.
PCLATH ALU Result The PCL register is loaded with the value of W and
PCH is loaded with PCLATH.
14 PCH PCL 0
PC GOTO, CALL 3.4.4 BRANCHING
The branching instructions add an offset to the PC.
6 4 0 11
This allows relocatable code and code that crosses
PCLATH OPCODE <10:0>
page boundaries. There are two forms of branching,
14 PCH PCL 0 BRW and BRA. The PC will have incremented to fetch
PC CALLW the next instruction in both cases. When using either
branching instruction, a PCL memory boundary may be
6 7 0 8
crossed.
PCLATH W
If using BRW, load the W register with the desired
14 PCH PCL 0 unsigned address and execute BRW. The entire PC will
PC BRW be loaded with the address PC + 1 + W.
If using BRA, the entire PC will be loaded with PC + 1 +,
15
PC + W the signed value of the operand of the BRA instruction.
14 PCH PCL 0
PC BRA
15
PC + OPCODE <8:0>
3.4.1 MODIFYING PCL

Executing any instruction with the PCL register as the
destination simultaneously causes the Program Counter
PC<14:8> bits (PCH) to be replaced by the contents of
the PCLATH register. This allows the entire contents of
the program counter to be changed by writing the
desired upper seven bits to the PCLATH register. When
the lower eight bits are written to the PCL register, all 15
bits of the program counter will change to the values
contained in the PCLATH register and those being
written to the PCL register.
3.4.2 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset to
the program counter (ADDWF PCL). When performing a
table read using a computed GOTO method, care should
be exercised if the table location crosses a PCL memory
boundary (each 256-byte block). Refer to Application
Note AN556, “Implementing a Table Read” (DS00556).

PIC16(L)F1933
3.5 Stack 3.5.1 ACCESSING THE STACK
All devices have a 16-level x 15-bit wide hardware The stack is available through the TOSH, TOSL and
stack (refer to Figures 3-4 through 3-7). The stack STKPTR registers. STKPTR is the current value of the
space is not part of either program or data space. The Stack Pointer. TOSH:TOSL register pair points to the
PC is PUSHed onto the stack when CALL or CALLW TOP of the stack. Both registers are read/writable. TOS
instructions are executed or an interrupt causes a is split into TOSH and TOSL due to the 15-bit size of the
branch. The stack is POPed in the event of a RETURN, PC. To access the stack, adjust the value of STKPTR,
RETLW or a RETFIE instruction execution. PCLATH is which will position TOSH:TOSL, then read/write to
not affected by a PUSH or POP operation. TOSH:TOSL. STKPTR is five bits to allow detection of
overflow and underflow.
The stack operates as a circular buffer if the STVREN
bit is programmed to ‘0‘ (Configuration Word 2). This Note: Care should be taken when modifying the
means that after the stack has been PUSHed sixteen STKPTR while interrupts are enabled.
times, the seventeenth PUSH overwrites the value that
During normal program operation, CALL, CALLW and
was stored from the first PUSH. The eighteenth PUSH
Interrupts will increment STKPTR while RETLW,
overwrites the second PUSH (and so on). The
RETURN, and RETFIE will decrement STKPTR. At any
STKOVF and STKUNF flag bits will be set on an Over-
time, STKPTR can be inspected to see how much
flow/Underflow, regardless of whether the Reset is
stack is left. The STKPTR always points at the currently
enabled.
used place on the stack. Therefore, a CALL or CALLW
Note 1: There are no instructions/mnemonics will increment the STKPTR and then write the PC, and
called PUSH or POP. These are actions a return will unload the PC and then decrement the
that occur from the execution of the STKPTR.
CALL, CALLW, RETURN, RETLW and Reference Figure 3-4 through Figure 3-7 for examples
RETFIE instructions or the vectoring to of accessing the stack.
an interrupt address.
FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1
Stack Reset Disabled

TOSH:TOSL 0x0F STKPTR = 0x1F
(STVREN = 0)
0x0E
0x0D
0x0C
0x0B
0x0A
Initial Stack Configuration:
0x09
After Reset, the stack is empty. The
0x08 empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
0x07
Overflow/Underflow Reset is enabled, the
0x06 TOSH/TOSL registers will return ‘0’. If
the Stack Overflow/Underflow Reset is
0x05 disabled, the TOSH/TOSL registers will
return the contents of stack address 0x0F.
0x04
0x03
0x02
0x01
0x00
Stack Reset Enabled
TOSH:TOSL 0x1F 0x0000 STKPTR = 0x1F
(STVREN = 1)

PIC16(L)F1933
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09 This figure shows the stack configuration
after the first CALL or a single interrupt.
0x08 If a RETURN instruction is executed, the
0x07 return address will be placed in the
Program Counter and the Stack Pointer
0x06 decremented to the empty state (0x1F).
0x05
0x04
0x03
0x02
0x01
TOSH:TOSL 0x00 Return Address STKPTR = 0x00
0x0F
0x0E
0x0D
0x0C
After seven CALLs or six CALLs and an
0x0B interrupt, the stack looks like the figure
on the left. A series of RETURN instructions
0x0A will repeatedly place the return addresses
into the Program Counter and pop the stack.
0x09
0x08
0x07
0x05 Return Address

0x04 Return Address
0x03 Return Address
0x02 Return Address
0x01 Return Address
0x00 Return Address

PIC16(L)F1933
0x0F Return Address

0x0E Return Address
0x0D Return Address
0x0C Return Address
0x0B Return Address
0x0A Return Address
When the stack is full, the next CALL or
0x09 Return Address an interrupt will set the Stack Pointer to
0x10. This is identical to address 0x00
0x08 Return Address so the stack will wrap and overwrite the
return address at 0x00. If the Stack
0x07 Return Address Overflow/Underflow Reset is enabled, a
Reset will occur and location 0x00 will
0x06 Return Address not be overwritten.
0x05 Return Address
0x04 Return Address
0x03 Return Address
0x02 Return Address
0x01 Return Address
3.5.2 OVERFLOW/UNDERFLOW RESET

If the STVREN bit in Configuration Word 2 is
programmed to ‘1’, the device will be reset if the stack
is PUSHed beyond the sixteenth level or POPed
beyond the first level, setting the appropriate bits
(STKOVF or STKUNF, respectively) in the PCON
register.
3.6 Indirect Addressing

The INDFn registers are not physical registers. Any
instruction that accesses an INDFn register actually
accesses the register at the address specified by the
File Select Registers (FSR). If the FSRn address
specifies one of the two INDFn registers, the read will
return ‘0’ and the write will not occur (though Status bits
may be affected). The FSRn register value is created
by the pair FSRnH and FSRnL.
The FSR registers form a 16-bit address that allows an
addressing space with 65536 locations. These locations
are divided into three memory regions:
• Traditional Data Memory
• Linear Data Memory
• Program Flash Memory

PIC16(L)F1933
FIGURE 3-8: INDIRECT ADDRESSING
0x0000 0x0000
Traditional
Data Memory
0x0FFF 0x0FFF
0x1000
Reserved
0x1FFF
0x2000
Linear
Data Memory
0x29AF
0x29B0
FSR Reserved
0x7FFF
Address
Range 0x8000 0x0000
Program
Flash Memory
0xFFFF 0x7FFF
Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.

PIC16(L)F1933
3.6.1 TRADITIONAL DATA MEMORY
The traditional data memory is a region from FSR
address 0x000 to FSR address 0xFFF. The addresses
correspond to the absolute addresses of all SFR, GPR
and common registers.
FIGURE 3-9: TRADITIONAL DATA MEMORY MAP
Direct Addressing Indirect Addressing
4 BSR 0 6 From Opcode 0 7 FSRxH 0 7 FSRxL 0

0 0 0 0
Bank Select Location Select Bank Select Location Select

0000 0001 0010 1111
0x00
0x7F
Bank 0 Bank 1 Bank 2 Bank 31

PIC16(L)F1933
3.6.2 LINEAR DATA MEMORY 3.6.3 PROGRAM FLASH MEMORY
The linear data memory is the region from FSR To make constant data access easier, the entire
address 0x2000 to FSR address 0x29AF. This region is program Flash memory is mapped to the upper half of
a virtual region that points back to the 80-byte blocks of the FSR address space. When the MSB of FSRnH is
GPR memory in all the banks. set, the lower 15 bits are the address in program
Unimplemented memory reads as 0x00. Use of the memory which will be accessed through INDF. Only the
linear data memory region allows buffers to be larger lower 8 bits of each memory location is accessible via
than 80 bytes because incrementing the FSR beyond INDF. Writing to the program Flash memory cannot be
one bank will go directly to the GPR memory of the next accomplished via the FSR/INDF interface. All
bank. instructions that access program Flash memory via the
FSR/INDF interface will require one additional
The 16 bytes of common memory are not included in instruction cycle to complete.
the linear data memory region.
FIGURE 3-11: PROGRAM FLASH
FIGURE 3-10: LINEAR DATA MEMORY MEMORY MAP
MAP
7 FSRnH 0 7 FSRnL 0
7 FSRnH 0 7 FSRnL 0 1
0 0 1
Location Select 0x8000 0x0000
Location Select 0x2000 0x020
Bank 0
0x06F
0x0A0
Bank 1
Program
0x0EF Flash
0x120 Memory
Bank 2 (low 8
bits)
0x16F
0xF20
Bank 30 0x7FFF
0xFFFF
0x29AF 0xF6F

PIC16(L)F1933
4.0 DEVICE CONFIGURATION
Device configuration consists of Configuration Words,
Code Protection and Device ID.
4.1 Configuration Words

There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word 1 at
8007h and Configuration Word 2 at 8008h.
Note: The DEBUG bit in Configuration Words is
managed automatically by device
development tools including debuggers
and programmers. For normal device
operation, this bit should be maintained as
a ‘1’.

PIC16(L)F1933
4.2 Register Definitions: Configuration Words
REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
FCMEN IESO CLKOUTEN BOREN<1:0> CPD
bit 13 bit 8
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase
bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit

1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
bit 12 IESO: Internal External Switchover bit
1 = Internal/External Switchover mode is enabled
0 = Internal/External Switchover mode is disabled
bit 11 CLKOUTEN: Clock Out Enable bit
1 = CLKOUT function is disabled. I/O or oscillator function on RA6/CLKOUT
0 = CLKOUT function is enabled on RA6/CLKOUT
bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits(1)
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the BORCON register
00 = BOR disabled
bit 8 CPD: Data Code Protection bit(2)
1 = Data memory code protection is disabled
0 = Data memory code protection is enabled
bit 7 CP: Code Protection bit(3)
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 6 MCLRE: MCLR/VPP Pin Function Select bit
If LVP bit = 1:
This bit is ignored.
If LVP bit = 0:
1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of
WPUE3 bit.
bit 5 PWRTE: Power-up Timer Enable bit(1)
1 = PWRT disabled
0 = PWRT enabled
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire data EEPROM will be erased when the code protection is turned off during
3: The entire program memory will be erased when the code protection is turned off.

PIC16(L)F1933
REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 (CONTINUED)
bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit
11 = WDT enabled
10 = WDT enabled while running and disabled in Sleep
01 = WDT controlled by the SWDTEN bit in the WDTCON register
00 = WDT disabled
bit 2-0 FOSC<2:0>: Oscillator Selection bits
111 = ECH: External Clock, High-Power mode (4-20 MHz): device clock supplied to CLKIN pin
110 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin
101 = ECL: External Clock, Low-Power mode (0-0.5 MHz): device clock supplied to CLKIN pin
100 = INTOSC oscillator: I/O function on CLKIN pin
011 = EXTRC oscillator: External RC circuit connected to CLKIN pin
010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins
001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins
000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire data EEPROM will be erased when the code protection is turned off during
3: The entire program memory will be erased when the code protection is turned off.

PIC16(L)F1933
REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2

R/P-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1
(1) (3)
LVP DEBUG — BORV STVREN PLLEN
bit 13 bit 8
U-1 U-1 R/P-1 R/P-1 U-1 U-1 R/P-1 R/P-1

(2)
— — VCAPEN<1:0> — — WRT<1:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase
bit 13 LVP: Low-Voltage Programming Enable bit(1)

1 = Low-voltage programming enabled
0 = High-voltage on MCLR must be used for programming
bit 12 DEBUG: In-Circuit Debugger Mode bit(3)
1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins
0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger
bit 11 Unimplemented: Read as ‘1’
bit 10 BORV: Brown-out Reset Voltage Selection bit(4)
1 = Brown-out Reset voltage (Vbor), low trip point selected.
0 = Brown-out Reset voltage (Vbor), high trip point selected.
bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit
1 = Stack Overflow or Underflow will cause a Reset
0 = Stack Overflow or Underflow will not cause a Reset
bit 8 PLLEN: PLL Enable bit
1 = 4xPLL enabled
0 = 4xPLL disabled
bit 4 VCAPEN: Voltage Regulator Capacitor Enable bits(2)
00 = VCAP functionality is enabled on RA0
11 = No capacitor on VCAP pin
bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits
11 = No capacitor on VCAP pin
Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
2: Reads as ‘11’ on PIC16LF193X only.
3: The DEBUG bit in Configuration Words is managed automatically by device development tools including
debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.
4: See Vbor parameter for specific trip point voltages.

PIC16(L)F1933
4.3 Code Protection
Code protection allows the device to be protected from
unauthorized access. Program memory protection and
data EEPROM protection are controlled independently.
Internal access to the program memory and data
EEPROM are unaffected by any code protection
setting.
4.3.1 PROGRAM MEMORY PROTECTION

The entire program memory space is protected from
external reads and writes by the CP bit in Configuration
Words. When CP = 0, external reads and writes of
program memory are inhibited and a read will return all
‘0’s. The CPU can continue to read program memory,
regardless of the protection bit settings. Writing the
program memory is dependent upon the write
protection setting. See Section 4.4 “Write
Protection” for more information.
4.3.2 DATA EEPROM PROTECTION

The entire data EEPROM is protected from external
reads and writes by the CPD bit. When CPD = 0,
external reads and writes of data EEPROM are
inhibited. The CPU can continue to read and write data
EEPROM regardless of the protection bit settings.
4.4 Write Protection

Write protection allows the device to be protected from
unintended self-writes. Applications, such as boot
loader software, can be protected while allowing other
regions of the program memory to be modified.
The WRT<1:0> bits in Configuration Words define the
size of the program memory block that is protected.
4.5 User ID
Four memory locations (8000h-8003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
readable and writable during normal execution. See
Section 4.6 “Device ID and Revision ID” for more
information on accessing these memory locations. For
more information on checksum calculation, see the
“PIC16F193X/LF193X/PIC16F194X/LF194X/PIC16LF
190X Memory Programming Specification” (DS41397).

PIC16(L)F1933
4.6 Device ID and Revision ID
The memory location 8006h is where the Device ID and
Revision ID are stored. The upper nine bits hold the
Device ID. The lower five bits hold the Revision ID. See
Section 11.5 “User ID, Device ID and Configuration
Word Access” for more information on accessing
these memory locations.
Development tools, such as device programmers and
debuggers, may be used to read the Device ID and
Revision ID.
4.7 Register Definitions: Device ID
REGISTER 4-3: DEVID: DEVICE ID REGISTER

R R R R R R
DEV<8:3>
bit 13 bit 8
R R R R R R R R
DEV<2:0> REV<4:0>
bit 7 bit 0
Legend:
R = Readable bit
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 13-5 DEV<8:0>: Device ID bits
DEVID<13:0> Values
Device
DEV<8:0> REV<4:0>
PIC16F1933 10 0011 001 x xxxx
PIC16LF1933 10 0100 001 x xxxx
bit 4-0 REV<4:0>: Revision ID bits

These bits are used to identify the revision (see Table under DEV<8:0> above).

PIC16(L)F1933
5.0 OSCILLATOR MODULE (WITH The oscillator module can be configured in one of eight
clock modes.
FAIL-SAFE CLOCK MONITOR)
1. ECL – External Clock Low-Power mode
5.1 Overview (0 MHz to 0.5 MHz)
2. ECM – External Clock Medium-Power mode
The oscillator module has a wide variety of clock (0.5 MHz to 4 MHz)
sources and selection features that allow it to be used 3. ECH – External Clock High-Power mode
in a wide range of applications while maximizing perfor- (4 MHz to 32 MHz)
mance and minimizing power consumption. Figure 5-1
4. LP – 32 kHz Low-Power Crystal mode.
illustrates a block diagram of the oscillator module.
5. XT – Medium Gain Crystal or Ceramic Resonator
Clock sources can be supplied from external oscillators, Oscillator mode (up to 4 MHz)
quartz crystal resonators, ceramic resonators and
6. HS – High Gain Crystal or Ceramic Resonator
Resistor-Capacitor (RC) circuits. In addition, the system
mode (4 MHz to 20 MHz)
clock source can be supplied from one of two internal
oscillators and PLL circuits, with a choice of speeds 7. RC – External Resistor-Capacitor (RC).
selectable via software. Additional clock features 8. INTOSC – Internal oscillator (31 kHz to 32 MHz).
include: Clock Source modes are selected by the FOSC<2:0>
• Selectable system clock source between external bits in the Configuration Words. The FOSC bits
or internal sources via software. determine the type of oscillator that will be used when
• Two-Speed Start-up mode, which minimizes the device is first powered.
latency between external oscillator start-up and The EC clock mode relies on an external logic level
code execution. signal as the device clock source. The LP, XT, and HS
• Fail-Safe Clock Monitor (FSCM) designed to clock modes require an external crystal or resonator to
detect a failure of the external clock source (LP, be connected to the device. Each mode is optimized for
XT, HS, EC or RC modes) and switch a different frequency range. The RC clock mode
automatically to the internal oscillator. requires an external resistor and capacitor to set the
• Oscillator Start-up Timer (OST) ensures stability oscillator frequency.
of crystal oscillator sources The INTOSC internal oscillator block produces low,
medium, and high-frequency clock sources,
designated LFINTOSC, MFINTOSC and HFINTOSC.
(see Internal Oscillator Block, Figure 5-1). A wide
selection of device clock frequencies may be derived
from these three clock sources.

PIC16(L)F1933
FIGURE 5-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
External
Oscillator LP, XT, HS, RC, EC
OSC2
Sleep
4x PLL Sleep
OSC1
Oscillator Timer1 FOSC<2:0> = 100 T1OSC CPU and
MUX
T1OSO Peripherals
T1OSCEN
Enable
T1OSI Oscillator IRCF<3:0>
Internal Oscillator
16 MHz
8 MHz
Internal
Oscillator 4 MHz
Block 2 MHz
Postscaler 1 MHz Clock
HFPLL Control
MUX
16 MHz 500 kHz
(HFINTOSC) 250 kHz
125 kHz FOSC<2:0> SCS<1:0>
500 kHz
Source 500 kHz 62.5 kHz
(MFINTOSC) 31.25 kHz Clock Source Option
31 kHz for other modules
31 kHz
Source
31 kHz (LFINTOSC) WDT, PWRT, Fail-Safe Clock Monitor

Two-Speed Start-up and other modules

PIC16(L)F1933
5.2 Clock Source Types The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
Clock sources can be classified as external or internal. operation after a Power-on Reset (POR) or wake-up
External clock sources rely on external circuitry for the from Sleep. Because the PIC® MCU design is fully
clock source to function. Examples are: oscillator static, stopping the external clock input will have the
modules (EC mode), quartz crystal resonators or effect of halting the device while leaving all data intact.
ceramic resonators (LP, XT and HS modes) and Upon restarting the external clock, the device will
Resistor-Capacitor (RC) mode circuits. resume operation as if no time had elapsed.
Internal clock sources are contained within the
oscillator module. The internal oscillator block has two FIGURE 5-2: EXTERNAL CLOCK (EC)
internal oscillators and a dedicated Phase-Lock Loop MODE OPERATION
(HFPLL) that are used to generate three internal
system clock sources: the 16 MHz High-Frequency OSC1/CLKIN
Clock from
Internal Oscillator (HFINTOSC), 500 kHz (MFINTOSC) Ext. System
and the 31 kHz Low-Frequency Internal Oscillator PIC® MCU
(LFINTOSC).
OSC2/CLKOUT
The system clock can be selected between external or FOSC/4 or I/O(1)
internal clock sources via the System Clock Select
(SCS) bits in the OSCCON register. See Section 5.3
Note 1: Output depends upon CLKOUTEN bit of the
“Clock Switching” for additional information. Configuration Words.
5.2.1 EXTERNAL CLOCK SOURCES

An external clock source can be used as the device 5.2.1.2 LP, XT, HS Modes
system clock by performing one of the following The LP, XT and HS modes support the use of quartz
actions: crystal resonators or ceramic resonators connected to
• Program the FOSC<2:0> bits in the Configuration OSC1 and OSC2 (Figure 5-3). The three modes select
Words to select an external clock source that will a low, medium or high gain setting of the internal
be used as the default system clock upon a inverter-amplifier to support various resonator types
device Reset. and speed.
• Write the SCS<1:0> bits in the OSCCON register LP Oscillator mode selects the lowest gain setting of the
to switch the system clock source to: internal inverter-amplifier. LP mode current consumption
- Timer1 oscillator during run-time, or is the least of the three modes. This mode is designed to
drive only 32.768 kHz tuning-fork type crystals (watch
- An external clock source determined by the
crystals).
value of the FOSC bits.
XT Oscillator mode selects the intermediate gain
See Section 5.3 “Clock Switching”for more
setting of the internal inverter-amplifier. XT mode
information.
current consumption is the medium of the three modes.
5.2.1.1 EC Mode This mode is best suited to drive resonators with a
medium drive level specification.
The External Clock (EC) mode allows an externally
generated logic level signal to be the system clock HS Oscillator mode selects the highest gain setting of the
source. When operating in this mode, an external clock internal inverter-amplifier. HS mode current consumption
source is connected to the OSC1 input. is the highest of the three modes. This mode is best
OSC2/CLKOUT is available for general purpose I/O or suited for resonators that require a high drive setting.
CLKOUT. Figure 5-2 shows the pin connections for EC Figure 5-3 and Figure 5-4 show typical circuits for
mode. quartz crystal and ceramic resonators, respectively.
EC mode has three power modes to select from through
Configuration Words:
• High power, 4-32 MHz (FOSC = 111)
• Medium power, 0.5-4 MHz (FOSC = 110)
• Low power, 0-0.5 MHz (FOSC = 101)

PIC16(L)F1933
FIGURE 5-3: QUARTZ CRYSTAL FIGURE 5-4: CERAMIC RESONATOR
OPERATION (LP, XT OR OPERATION
HS MODE) (XT OR HS MODE)
PIC® MCU PIC® MCU
OSC1/CLKIN OSC1/CLKIN
C1 To Internal C1 To Internal
Logic Logic
Quartz
RF(2) Sleep RP(3)
Crystal RF(2) Sleep
OSC2/CLKOUT
C2 RS(1) OSC2/CLKOUT
C2 Ceramic RS(1)
Resonator
Note 1: A series resistor (RS) may be required for
quartz crystals with low drive level. Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M. 2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
3: An additional parallel feedback resistor (RP)
Note 1: Quartz crystal characteristics vary may be required for proper ceramic resonator
according to type, package and operation.
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application. 5.2.1.3 Oscillator Start-up Timer (OST)
2: Always verify oscillator performance over If the oscillator module is configured for LP, XT or HS
the VDD and temperature range that is modes, the Oscillator Start-up Timer (OST) counts
expected for the application. 1024 oscillations from OSC1. This occurs following a
3: For oscillator design assistance, reference Power-on Reset (POR) and when the Power-up Timer
the following Microchip Applications Notes: (PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
• AN826, “Crystal Oscillator Basics and increment and program execution is suspended unless
Crystal Selection for rfPIC® and PIC® either FSCM or Two-Speed Start-Up are enabled. In
Devices” (DS00826) this case code will continue to execute at the selected
• AN849, “Basic PIC® Oscillator Design” INTOSC frequency while the OST is counting. The
(DS00849) OST ensures that the oscillator circuit, using a quartz
• AN943, “Practical PIC® Oscillator crystal resonator or ceramic resonator, has started and
Analysis and Design” (DS00943) is providing a stable system clock to the oscillator
• AN949, “Making Your Oscillator Work” module.
(DS00949) In order to minimize latency between external oscillator
start-up and code execution, the Two-Speed Clock
Start-up mode can be selected (see Section 5.4
“Two-Speed Clock Start-up Mode”).
5.2.1.4 4x PLL
The oscillator module contains a 4x PLL that can be
used with both external and internal clock sources to
provide a system clock source. The input frequency for
the 4x PLL must fall within specifications. See the PLL
Clock Timing specifications in Section 30.0
“Electrical Specifications”.

PIC16(L)F1933
The 4x PLL may be enabled for use by one of two
Note 1: Quartz crystal characteristics vary
methods:
according to type, package and
1. Program the PLLEN bit in Configuration Words manufacturer. The user should consult the
to a ‘1’. manufacturer data sheets for specifications
2. Write the SPLLEN bit in the OSCCON register to and recommended application.
a ‘1’. If the PLLEN bit in Configuration Words is 2: Always verify oscillator performance over
programmed to a ‘1’, then the value of SPLLEN the VDD and temperature range that is
is ignored. expected for the application.
5.2.1.5 TIMER1 Oscillator 3: For oscillator design assistance, reference
the following Microchip Applications Notes:
The Timer1 oscillator is a separate crystal oscillator
that is associated with the Timer1 peripheral. It is opti- • AN826, “Crystal Oscillator Basics and
mized for timekeeping operations with a 32.768 kHz Crystal Selection for rfPIC® and PIC®
crystal connected between the T1OSO and T1OSI Devices” (DS00826)
device pins. • AN849, “Basic PIC® Oscillator Design”
The Timer1 oscillator can be used as an alternate (DS00849)
system clock source and can be selected during • AN943, “Practical PIC® Oscillator
run-time using clock switching. Refer to Section 5.3 Analysis and Design” (DS00943)
“Clock Switching” for more information. • AN949, “Making Your Oscillator Work”
(DS00949)
FIGURE 5-5: QUARTZ CRYSTAL • TB097, “Interfacing a Micro Crystal
OPERATION (TIMER1 MS1V-T1K 32.768 kHz Tuning Fork
OSCILLATOR) Crystal to a PIC16F690/SS” (DS91097)
• AN1288, “Design Practices for
Low-Power External Oscillators”
PIC® MCU (DS01288)
T1OSI
C1 To Internal 5.2.1.6 External RC Mode

Logic
32.768 kHz The external Resistor-Capacitor (RC) modes support
Quartz the use of an external RC circuit. This allows the
Crystal
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
C2 T1OSO required.
The RC circuit connects to OSC1. OSC2/CLKOUT is
available for general purpose I/O or CLKOUT. The
function of the OSC2/CLKOUT pin is determined by the
CLKOUTEN bit in Configuration Words.
Figure 5-6 shows the external RC mode connections.

PIC16(L)F1933
FIGURE 5-6: EXTERNAL RC MODES
VDD
PIC® MCU
REXT
OSC1/CLKIN Internal
Clock
CEXT
VSS
OSC2/CLKOUT
FOSC/4 or I/O(1)
Recommended values: 10 k  REXT  100 k, <3V

3 k  REXT  100 k, 3-5V
CEXT > 20 pF, 2-5V
Note 1: Output depends upon CLKOUTEN bit of the

Configuration Words.
The RC oscillator frequency is a function of the supply

voltage, the resistor (REXT) and capacitor (CEXT) values
and the operating temperature. Other factors affecting
the oscillator frequency are:
• threshold voltage variation
• component tolerances
• packaging variations in capacitance
The user also needs to take into account variation due
to tolerance of external RC components used.

PIC16(L)F1933
5.2.2 INTERNAL CLOCK SOURCES 5.2.2.1 HFINTOSC
The device may be configured to use the internal The High-Frequency Internal Oscillator (HFINTOSC) is
oscillator block as the system clock by performing one a factory calibrated 16 MHz internal clock source. The
of the following actions: frequency of the HFINTOSC can be altered via
• Program the FOSC<2:0> bits in Configuration software using the OSCTUNE register (Register 5-3).
Words to select the INTOSC clock source, which The output of the HFINTOSC connects to a postscaler
will be used as the default system clock upon a and multiplexer (see Figure 5-1). One of multiple
device Reset. frequencies derived from the HFINTOSC can be
• Write the SCS<1:0> bits in the OSCCON register selected via software using the IRCF<3:0> bits of the
to switch the system clock source to the internal OSCCON register. See Section 5.2.2.7 “Internal
oscillator during run-time. See Section 5.3 Oscillator Clock Switch Timing” for more information.
“Clock Switching”for more information. The HFINTOSC is enabled by:
In INTOSC mode, OSC1/CLKIN is available for general • Configure the IRCF<3:0> bits of the OSCCON
purpose I/O. OSC2/CLKOUT is available for general register for the desired HF frequency, and
purpose I/O or CLKOUT. • FOSC<2:0> = 100, or
The function of the OSC2/CLKOUT pin is determined • Set the System Clock Source (SCS) bits of the
by the CLKOUTEN bit in Configuration Words. OSCCON register to ‘1x’.
The internal oscillator block has two independent A fast start-up oscillator allows internal circuits to
oscillators and a dedicated Phase-Lock Loop, HFPLL power-up and stabilize before switching to HFINTOSC.
that can produce one of three internal system clock
The High-Frequency Internal Oscillator Ready bit
sources.
(HFIOFR) of the OSCSTAT register indicates when the
1. The HFINTOSC (High-Frequency Internal HFINTOSC is running.
Oscillator) is factory calibrated and operates at
The High-Frequency Internal Oscillator Status Locked
16 MHz. The HFINTOSC source is generated
bit (HFIOFL) of the OSCSTAT register indicates when
from the 500 kHz MFINTOSC source and the
the HFINTOSC is running within 2% of its final value.
dedicated Phase-Lock Loop, HFPLL. The
frequency of the HFINTOSC can be The High-Frequency Internal Oscillator Stable bit
user-adjusted via software using the OSCTUNE (HFIOFS) of the OSCSTAT register indicates when the
register (Register 5-3). HFINTOSC is running within 0.5% of its final value.
2. The MFINTOSC (Medium-Frequency Internal
Oscillator) is factory calibrated and operates at 5.2.2.2 MFINTOSC
500 kHz. The frequency of the MFINTOSC can The Medium-Frequency Internal Oscillator
be user-adjusted via software using the (MFINTOSC) is a factory calibrated 500 kHz internal
OSCTUNE register (Register 5-3). clock source. The frequency of the MFINTOSC can be
3. The LFINTOSC (Low-Frequency Internal altered via software using the OSCTUNE register
Oscillator) is uncalibrated and operates at (Register 5-3).
31 kHz. The output of the MFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). One of nine
frequencies derived from the MFINTOSC can be
selected via software using the IRCF<3:0> bits of the
OSCCON register. See Section 5.2.2.7 “Internal
Oscillator Clock Switch Timing” for more information.
The MFINTOSC is enabled by:
• Configure the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and
• FOSC<2:0> = 100, or
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’
The Medium Frequency Internal Oscillator Ready bit
(MFIOFR) of the OSCSTAT register indicates when the
MFINTOSC is running.

PIC16(L)F1933
5.2.2.3 Internal Oscillator Frequency 5.2.2.5 Internal Oscillator Frequency
Adjustment Selection
The 500 kHz internal oscillator is factory calibrated. The system clock speed can be selected via software
This internal oscillator can be adjusted in software by using the Internal Oscillator Frequency Select bits
writing to the OSCTUNE register (Register 5-3). Since IRCF<3:0> of the OSCCON register.
the HFINTOSC and MFINTOSC clock sources are The output of the 16 MHz HFINTOSC and 31 kHz
derived from the 500 kHz internal oscillator a change in LFINTOSC connects to a postscaler and multiplexer
the OSCTUNE register value will apply to both. (see Figure 5-1). The Internal Oscillator Frequency
The default value of the OSCTUNE register is ‘0’. The Select bits IRCF<3:0> of the OSCCON register select
value is a 6-bit two’s complement number. A value of the frequency output of the internal oscillators. One of
1Fh will provide an adjustment to the maximum the following frequencies can be selected via software:
frequency. A value of 20h will provide an adjustment to - 32 MHz (requires 4x PLL)
the minimum frequency.
- 16 MHz
When the OSCTUNE register is modified, the oscillator - 8 MHz
frequency will begin shifting to the new frequency. Code
- 4 MHz
execution continues during this shift. There is no
indication that the shift has occurred. - 2 MHz
- 1 MHz
OSCTUNE does not affect the LFINTOSC frequency.
Operation of features that depend on the LFINTOSC - 500 kHz (default after Reset)
clock source frequency, such as the Power-up Timer - 250 kHz
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock - 125 kHz
Monitor (FSCM) and peripherals, are not affected by the - 62.5 kHz
change in frequency.
- 31.25 kHz
5.2.2.4 LFINTOSC - 31 kHz (LFINTOSC)
The Low-Frequency Internal Oscillator (LFINTOSC) is Note: Following any Reset, the IRCF<3:0> bits
an uncalibrated 31 kHz internal clock source. of the OSCCON register are set to ‘0111’
and the frequency selection is set to
The output of the LFINTOSC connects to a multiplexer 500 kHz. The user can modify the IRCF
(see Figure 5-1). Select 31 kHz, via software, using the bits to select a different frequency.
IRCF<3:0> bits of the OSCCON register. See
Section 5.2.2.7 “Internal Oscillator Clock Switch The IRCF<3:0> bits of the OSCCON register allow
Timing” for more information. The LFINTOSC is also duplicate selections for some frequencies. These
the frequency for the Power-up Timer (PWRT), duplicate choices can offer system design trade-offs.
Watchdog Timer (WDT) and Fail-Safe Clock Monitor Lower power consumption can be obtained when
(FSCM). changing oscillator sources for a given frequency.
Faster transition times can be obtained between
The LFINTOSC is enabled by selecting 31 kHz
frequency changes that use the same oscillator source.
(IRCF<3:0> bits of the OSCCON register = 000) as the
system clock source (SCS bits of the OSCCON
register = 1x), or when any of the following are
enabled:
• Configure the IRCF<3:0> bits of the OSCCON
register for the desired LF frequency, and
• FOSC<2:0> = 100, or
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’
Peripherals that use the LFINTOSC are:
• Power-up Timer (PWRT)
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor (FSCM)
The Low-Frequency Internal Oscillator Ready bit
(LFIOFR) of the OSCSTAT register indicates when the
LFINTOSC is running.

PIC16(L)F1933
5.2.2.6 32 MHz Internal Oscillator 5.2.2.7 Internal Oscillator Clock Switch
Frequency Selection Timing
The Internal Oscillator Block can be used with the 4x When switching between the HFINTOSC, MFINTOSC
PLL associated with the External Oscillator Block to and the LFINTOSC, the new oscillator may already be
produce a 32 MHz internal system clock source. The shut down to save power (see Figure 5-7). If this is the
following settings are required to use the 32 MHz case, there is a delay after the IRCF<3:0> bits of the
internal clock source: OSCCON register are modified before the frequency
• The FOSC bits in Configuration Words must be selection takes place. The OSCSTAT register will
set to use the INTOSC source as the device reflect the current active status of the HFINTOSC,
system clock (FOSC<2:0> = 100). MFINTOSC and LFINTOSC oscillators. The sequence
of a frequency selection is as follows:
• The SCS bits in the OSCCON register must be
cleared to use the clock determined by 1. IRCF<3:0> bits of the OSCCON register are
FOSC<2:0> in Configuration Words modified.
(SCS<1:0> = 00). 2. If the new clock is shut down, a clock start-up
• The IRCF bits in the OSCCON register must be delay is started.
set to the 8 MHz HFINTOSC set to use 3. Clock switch circuitry waits for a falling edge of
(IRCF<3:0> = 1110). the current clock.
• The SPLLEN bit in the OSCCON register must be 4. The current clock is held low and the clock
set to enable the 4x PLL, or the PLLEN bit of the switch circuitry waits for a rising edge in the new
Configuration Words must be programmed to a clock.
‘1’. 5. The new clock is now active.
Note: When using the PLLEN bit of the 6. The OSCSTAT register is updated as required.
Configuration Words, the 4x PLL cannot 7. Clock switch is complete.
be disabled by software and the 8 MHz
See Figure 5-7 for more details.
HFINTOSC option will no longer be
available. If the internal oscillator speed is switched between two
clocks of the same source, there is no start-up delay
The 4x PLL is not available for use with the internal before the new frequency is selected. Clock switching
oscillator when the SCS bits of the OSCCON register time delays are shown in Table 5-1.
are set to ‘1x’. The SCS bits must be set to ‘00’ to use
the 4x PLL with the internal oscillator. Start-up delay specifications are located in the
oscillator tables in Section 30.0 “Electrical
Specifications”.

PIC16(L)F1933
FIGURE 5-7: INTERNAL OSCILLATOR SWITCH TIMING
HFINTOSC/ LFINTOSC (FSCM and WDT disabled)

MFINTOSC
HFINTOSC/
MFINTOSC Start-up Time 2-cycle Sync Running
LFINTOSC
IRCF <3:0> 0 0
System Clock
HFINTOSC/ LFINTOSC (Either FSCM or WDT enabled)

MFINTOSC
HFINTOSC/
MFINTOSC
2-cycle Sync Running
LFINTOSC
IRCF <3:0> 0 0
System Clock
LFINTOSC HFINTOSC/MFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled
LFINTOSC
Start-up Time 2-cycle Sync Running
HFINTOSC/
MFINTOSC
IRCF <3:0> =0 0
System Clock

PIC16(L)F1933
5.3 Clock Switching 5.3.3 TIMER1 OSCILLATOR
The system clock source can be switched between The Timer1 oscillator is a separate crystal oscillator
external and internal clock sources via software using associated with the Timer1 peripheral. It is optimized
the System Clock Select (SCS) bits of the OSCCON for timekeeping operations with a 32.768 kHz crystal
register. The following clock sources can be selected connected between the T1OSO and T1OSI device
using the SCS bits: pins.
• Default system oscillator determined by FOSC The Timer1 oscillator is enabled using the T1OSCEN
bits in Configuration Words control bit in the T1CON register. See Section 21.0
“Timer1 Module with Gate Control” for more
• Timer1 32 kHz crystal oscillator
information about the Timer1 peripheral.
• Internal Oscillator Block (INTOSC)
5.3.4 TIMER1 OSCILLATOR READY
5.3.1 SYSTEM CLOCK SELECT (SCS)
(T1OSCR) BIT
BITS
The user must ensure that the Timer1 oscillator is
The System Clock Select (SCS) bits of the OSCCON
ready to be used before it is selected as a system clock
register selects the system clock source that is used for
source. The Timer1 Oscillator Ready (T1OSCR) bit of
the CPU and peripherals.
the OSCSTAT register indicates whether the Timer1
• When the SCS bits of the OSCCON register = 00, oscillator is ready to be used. After the T1OSCR bit is
the system clock source is determined by value of set, the SCS bits can be configured to select the Timer1
the FOSC<2:0> bits in the Configuration Words. oscillator.
• When the SCS bits of the OSCCON register = 01,
the system clock source is the Timer1 oscillator.
• When the SCS bits of the OSCCON register = 1x,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<3:0>
bits of the OSCCON register. After a Reset, the
SCS bits of the OSCCON register are always
cleared.
Note: Any automatic clock switch, which may
occur from Two-Speed Start-up or
Fail-Safe Clock Monitor, does not update
the SCS bits of the OSCCON register. The
user can monitor the OSTS bit of the
OSCSTAT register to determine the current
system clock source.
When switching between clock sources, a delay is
required to allow the new clock to stabilize. These
oscillator delays are shown in Table 5-1.
5.3.2 OSCILLATOR START-UP TIMER

STATUS (OSTS) BIT
The Oscillator Start-up Timer Status (OSTS) bit of the
OSCSTAT register indicates whether the system clock
is running from the external clock source, as defined by
the FOSC<2:0> bits in the Configuration Words, or
from the internal clock source. In particular, OSTS
indicates that the Oscillator Start-up Timer (OST) has
counted 1024 clock cycles for LP, XT or HS modes. The
OST does not reflect the status of the Timer1 oscillator.

PIC16(L)F1933
5.4 Two-Speed Clock Start-up Mode 5.4.1 TWO-SPEED START-UP MODE
CONFIGURATION
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external Two-Speed Start-up mode is configured by the
oscillator start-up and code execution. In applications following settings:
that make heavy use of the Sleep mode, Two-Speed • IESO (of the Configuration Words) = 1;
Start-up will remove the external oscillator start-up Internal/External Switchover bit (Two-Speed
time from the time spent awake and can reduce the Start-up mode enabled).
overall power consumption of the device. This mode • SCS (of the OSCCON register) = 00.
allows the application to wake-up from Sleep, perform
• FOSC<2:0> bits in the Configuration Words
a few instructions using the INTOSC internal oscillator
configured for LP, XT or HS mode.
block as the clock source and go back to Sleep without
waiting for the external oscillator to become stable. Two-Speed Start-up mode is entered after:
Two-Speed Start-up provides benefits when the • Power-on Reset (POR) and, if enabled, after
oscillator module is configured for LP, XT or HS Power-up Timer (PWRT) has expired, or
modes. The Oscillator Start-up Timer (OST) is enabled • Wake-up from Sleep.
for these modes and must count 1024 oscillations
before the oscillator can be used as the system clock
source. Note: When FSCM is enabled, Two-Speed
If the oscillator module is configured for any mode Start-Up will automatically be enabled.
other than LP, XT or HS mode, then Two-Speed
Start-up is disabled. This is because the external clock
oscillator does not require any stabilization time after
POR or an exit from Sleep.
If the OST count reaches 1024 before the device
enters Sleep mode, the OSTS bit of the OSCSTAT
register is set and program execution switches to the
external oscillator. However, the system may never
operate from the external oscillator if the time spent
awake is very short.
Note: Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit of the OSCSTAT register to
remain clear.
TABLE 5-1: OSCILLATOR SWITCHING DELAYS

Switch From Switch To Frequency Oscillator Delay
LFINTOSC(1) 31 kHz
Sleep/POR MFINTOSC(1) 31.25 kHz-500 kHz 2 cycles
HFINTOSC(1) 31.25 kHz-16 MHz
Sleep/POR EC, RC(1) DC – 32 MHz 2 cycles
LFINTOSC EC, RC(1) DC – 32 MHz 1 cycle of each
Timer1 Oscillator
Sleep/POR 32 kHz-20 MHz 1024 Clock Cycles (OST)
LP, XT, HS(1)
MFINTOSC(1) 31.25 kHz-500 kHz
Any clock source 2 s (approx.)
HFINTOSC(1) 31.25 kHz-16 MHz
Any clock source LFINTOSC(1) 31 kHz 1 cycle of each
Any clock source Timer1 Oscillator 32 kHz 1024 Clock Cycles (OST)
PLL inactive PLL active 16-32 MHz 2 ms (approx.)
Note 1: PLL inactive.

PIC16(L)F1933
5.4.2 TWO-SPEED START-UP 5.4.3 CHECKING TWO-SPEED CLOCK
SEQUENCE STATUS
1. Wake-up from Power-on Reset or Sleep. Checking the state of the OSTS bit of the OSCSTAT
2. Instructions begin execution by the internal register will confirm if the microcontroller is running
oscillator at the frequency set in the IRCF<3:0> from the external clock source, as defined by the
bits of the OSCCON register. FOSC<2:0> bits in the Configuration Words, or the
3. OST enabled to count 1024 clock cycles. internal oscillator.
4. OST timed out, wait for falling edge of the
internal oscillator.
5. OSTS is set.
6. System clock held low until the next falling edge
of new clock (LP, XT or HS mode).
7. System clock is switched to external clock
source.
FIGURE 5-8: TWO-SPEED START-UP
INTOSC
TOST
OSC1 0 1 1022 1023
OSC2
Program Counter PC - N PC PC + 1
System Clock

PIC16(L)F1933
5.5 Fail-Safe Clock Monitor 5.5.3 FAIL-SAFE CONDITION CLEARING
The Fail-Safe Clock Monitor (FSCM) allows the device The Fail-Safe condition is cleared after a Reset,
to continue operating should the external oscillator fail. executing a SLEEP instruction or changing the SCS bits
The FSCM can detect oscillator failure any time after of the OSCCON register. When the SCS bits are
the Oscillator Start-up Timer (OST) has expired. The changed, the OST is restarted. While the OST is
FSCM is enabled by setting the FCMEN bit in the running, the device continues to operate from the
Configuration Words. The FSCM is applicable to all INTOSC selected in OSCCON. When the OST times
external Oscillator modes (LP, XT, HS, EC, Timer1 out, the Fail-Safe condition is cleared after successfully
Oscillator and RC). switching to the external clock source. The OSFIF bit
should be cleared prior to switching to the external
clock source. If the Fail-Safe condition still exists, the
FIGURE 5-9: FSCM BLOCK DIAGRAM
OSFIF flag will again become set by hardware.
Clock Monitor
Latch 5.5.4 RESET OR WAKE-UP FROM SLEEP
External
S Q The FSCM is designed to detect an oscillator failure
Clock
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
LFINTOSC any type of Reset. The OST is not used with the EC or
÷ 64 R Q
Oscillator RC Clock modes so that the FSCM will be active as
soon as the Reset or wake-up has completed. When
31 kHz 488 Hz the FSCM is enabled, the Two-Speed Start-up is also
(~32 s) (~2 ms)
enabled. Therefore, the device will always be executing
Sample Clock code while the OST is operating.
Clock
Failure Note: Due to the wide range of oscillator start-up
Detected times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
5.5.1 FAIL-SAFE DETECTION amount of time, the user should check the
The FSCM module detects a failed oscillator by Status bits in the OSCSTAT register to
comparing the external oscillator to the FSCM sample verify the oscillator start-up and that the
clock. The sample clock is generated by dividing the system clock switchover has successfully
LFINTOSC by 64. See Figure 5-9. Inside the fail completed.
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire
half-cycle of the sample clock elapses before the
external clock goes low.
5.5.2 FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the
device clock to an internal clock source and sets the bit
flag OSFIF of the PIR2 register. Setting this flag will
generate an interrupt if the OSFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation.
The internal clock source chosen by the FSCM is
determined by the IRCF<3:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.

PIC16(L)F1933
FIGURE 5-10: FSCM TIMING DIAGRAM
Sample Clock
System Oscillator
Clock Failure
Output
Clock Monitor Output

(Q)
Failure
Detected
OSCFIF
Test Test Test
Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.

PIC16(L)F1933
5.6 Register Definitions: Oscillator Control
REGISTER 5-1: OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0
SPLLEN IRCF<3:0> — SCS<1:0>
bit 7 bit 0
Legend:
bit 7 SPLLEN: Software PLL Enable bit

If PLLEN in Configuration Words = 1:
SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements)
If PLLEN in Configuration Words = 0:
1 = 4x PLL Is enabled
0 = 4x PLL is disabled
bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits
1111 = 16 MHz HF
1110 = 8 MHz or 32 MHz HF(see Section 5.2.2.1 “HFINTOSC”)
1101 = 4 MHz HF
1100 = 2 MHz HF
1011 = 1 MHz HF
1010 = 500 kHz HF(1)
1001 = 250 kHz HF(1)
1000 = 125 kHz HF(1)
0111 = 500 kHz MF (default upon Reset)
0110 = 250 kHz MF
0101 = 125 kHz MF
0100 = 62.5 kHz MF
0011 = 31.25 kHz HF(1)
0010 = 31.25 kHz MF
000x = 31 kHz LF
bit 1-0 SCS<1:0>: System Clock Select bits
1x = Internal oscillator block
01 = Timer1 oscillator
00 = Clock determined by FOSC<2:0> in Configuration Words.
Note 1: Duplicate frequency derived from HFINTOSC.

PIC16(L)F1933
REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER

R-1/q R-0/q R-q/q R-0/q R-0/q R-q/q R-0/0 R-0/q
T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional
bit 7 T1OSCR: Timer1 Oscillator Ready bit

If T1OSCEN = 1:
1 = Timer1 oscillator is ready
0 = Timer1 oscillator is not ready
If T1OSCEN = 0:
1 = Timer1 clock source is always ready
bit 6 PLLR 4x PLL Ready bit
1 = 4x PLL is ready
0 = 4x PLL is not ready
bit 5 OSTS: Oscillator Start-up Timer Status bit
1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Words
0 = Running from an internal oscillator (FOSC<2:0> = 100)
bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit
1 = HFINTOSC is ready
0 = HFINTOSC is not ready
bit 3 HFIOFL: High-Frequency Internal Oscillator Locked bit
1 = HFINTOSC is at least 2% accurate
0 = HFINTOSC is not 2% accurate
bit 2 MFIOFR: Medium-Frequency Internal Oscillator Ready bit
1 = MFINTOSC is ready
0 = MFINTOSC is not ready
bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit
1 = LFINTOSC is ready
0 = LFINTOSC is not ready
bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit
1 = HFINTOSC is at least 0.5% accurate
0 = HFINTOSC is not 0.5% accurate

PIC16(L)F1933
REGISTER 5-3: OSCTUNE: OSCILLATOR TUNING REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — TUN<5:0>
bit 7 bit 0
Legend:

bit 5-0 TUN<5:0>: Frequency Tuning bits
100000 = Minimum frequency
•
•
•
111111 =
000000 = Oscillator module is running at the factory-calibrated frequency
000001 =
•
•
•
011110 =
011111 = Maximum frequency
TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
OSCCON SPLLEN IRCF<3:0> — SCS<1:0> 66

OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 67
OSCTUNE — — TUN<5:0> 68
PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE 84
PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF — CCP2IF 87
T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 183
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
TABLE 5-3: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES

Register
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
on Page
13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> CPD

CONFIG1 46
7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
13:8 — — LVP DEBUG — BORV STVREN PLLEN
CONFIG2 48
7:0 — — VCAPEN<1:0>(1) — — WRT<1:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
Note 1: PIC16F1933 only.

PIC16(L)F1933
6.0 RESETS
There are multiple ways to reset this device:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• MCLR Reset
• WDT Reset
• RESET instruction
• Stack Overflow
• Stack Underflow
• Programming mode exit
To allow VDD to stabilize, an optional power-up timer
can be enabled to extend the Reset time after a BOR
or POR event.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 6-1.
FIGURE 6-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Programming Mode Exit

RESET Instruction
Stack Stack Overflow/Underflow Reset

Pointer
External Reset
MCLRE
MCLR
Sleep
WDT
Time-out
Device
Power-on Reset
Reset
VDD
Brown-out
Reset
BOR
Enable
PWRT
Zero
64 ms
LFINTOSC
PWRTEN

PIC16(L)F1933
6.1 Power-On Reset (POR) 6.2 Brown-Out Reset (BOR)
The POR circuit holds the device in Reset until VDD has The BOR circuit holds the device in Reset when VDD
reached an acceptable level for minimum operation. reaches a selectable minimum level. Between the
Slow rising VDD, fast operating speeds or analog POR and BOR, complete voltage range coverage for
performance may require greater than minimum VDD. execution protection can be implemented.
The PWRT, BOR or MCLR features can be used to The Brown-out Reset module has four operating
extend the start-up period until all device operation modes controlled by the BOREN<1:0> bits in Configu-
conditions have been met. ration Words. The four operating modes are:
6.1.1 POWER-UP TIMER (PWRT) • BOR is always on
The Power-up Timer provides a nominal 64 ms time- • BOR is off when in Sleep
out on POR or Brown-out Reset. • BOR is controlled by software
The device is held in Reset as long as PWRT is active. • BOR is always off
The PWRT delay allows additional time for the VDD to Refer to Table 6-3 for more information.
rise to an acceptable level. The Power-up Timer is The Brown-out Reset voltage level is selectable by
enabled by clearing the PWRTE bit in Configuration configuring the BORV bit in Configuration Words.
Words.
A VDD noise rejection filter prevents the BOR from
The Power-up Timer starts after the release of the POR triggering on small events. If VDD falls below VBOR for
and BOR. a duration greater than parameter TBORDC, the device
For additional information, refer to Application Note will reset. See Figure 6-2 for more information.
AN607, “Power-up Trouble Shooting” (DS00607).
TABLE 6-1: BOR OPERATING MODES

Instruction Execution upon:
BOREN<1:0> SBOREN Device Mode BOR Mode
Release of POR or Wake-up from Sleep
11 X X Active Waits for BOR ready(1) (BORRDY = 1)

Awake Active
10 X Waits for BOR ready (BORRDY = 1)
Sleep Disabled
1 X Active Waits for BOR ready(1) (BORRDY = 1)
01
0 X Disabled
Begins immediately (BORRDY = x)
00 X X Disabled
Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR
ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR
circuit is forced on by the BOREN<1:0> bits.
6.2.1 BOR IS ALWAYS ON 6.2.3 BOR CONTROLLED BY SOFTWARE

When the BOREN bits of Configuration Words are When the BOREN bits of Configuration Words are
programmed to ‘11’, the BOR is always on. The device programmed to ‘01’, the BOR is controlled by the
start-up will be delayed until the BOR is ready and VDD SBOREN bit of the BORCON register. The device start-
is higher than the BOR threshold. up is not delayed by the BOR ready condition or the
BOR protection is active during Sleep. The BOR does VDD level.
not delay wake-up from Sleep. BOR protection begins as soon as the BOR circuit is
ready. The status of the BOR circuit is reflected in the
6.2.2 BOR IS OFF IN SLEEP BORRDY bit of the BORCON register.
When the BOREN bits of Configuration Words are BOR protection is unchanged by Sleep.
programmed to ‘10’, the BOR is on, except in Sleep.
The device start-up will be delayed until the BOR is
ready and VDD is higher than the BOR threshold.
BOR protection is not active during Sleep. The device
wake-up will be delayed until the BOR is ready.

PIC16(L)F1933
FIGURE 6-2: BROWN-OUT SITUATIONS
VDD
VBOR
Internal
Reset TPWRT(1)
VDD
VBOR
Internal < TPWRT

Reset TPWRT(1)
VDD
VBOR
Internal
Reset TPWRT(1)
Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.
6.3 Register Definitions: BOR Control
REGISTER 6-1: BORCON: BROWN-OUT RESET CONTROL REGISTER

R/W-1/u U-0 U-0 U-0 U-0 U-0 U-0 R-q/u
SBOREN — — — — — — BORRDY
bit 7 bit 0
Legend:
bit 7 SBOREN: Software Brown-out Reset Enable bit

If BOREN <1:0> in Configuration Words  01:
SBOREN is read/write, but has no effect on the BOR.
If BOREN <1:0> in Configuration Words = 01:
1 = BOR Enabled
0 = BOR Disabled
bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit
1 = The Brown-out Reset circuit is active
0 = The Brown-out Reset circuit is inactive

PIC16(L)F1933
6.4 MCLR 6.9 Power-up Timer
The MCLR is an optional external input that can reset The Power-up Timer optionally delays device execution
the device. The MCLR function is controlled by the after a BOR or POR event. This timer is typically used to
MCLRE bit of Configuration Words and the LVP bit of allow VDD to stabilize before allowing the device to start
Configuration Words (Table 6-2). running.
The Power-up Timer is controlled by the PWRTE bit of
TABLE 6-2: MCLR CONFIGURATION Configuration Words.
MCLRE LVP MCLR

6.10 Start-up Sequence
0 0 Disabled
Upon the release of a POR or BOR, the following must
1 0 Enabled occur before the device will begin executing:
x 1 Enabled
1. Power-up Timer runs to completion (if enabled).
6.4.1 MCLR ENABLED 2. Oscillator start-up timer runs to completion (if
required for oscillator source).
When MCLR is enabled and the pin is held low, the
3. MCLR must be released (if enabled).
device is held in Reset. The MCLR pin is connected to
VDD through an internal weak pull-up. The total time-out will vary based on oscillator configu-
ration and Power-up Timer configuration. See
The device has a noise filter in the MCLR Reset path.
Section 5.0 “Oscillator Module (with Fail-Safe
The filter will detect and ignore small pulses.
Clock Monitor)” for more information.
Note: A Reset does not drive the MCLR pin low. The Power-up Timer and oscillator start-up timer run
independently of MCLR Reset. If MCLR is kept low long
6.4.2 MCLR DISABLED enough, the Power-up Timer and oscillator start-up
When MCLR is disabled, the pin functions as a general timer will expire. Upon bringing MCLR high, the device
purpose input and the internal weak pull-up is under will begin execution immediately (see Figure 6-3). This
software control. See Section 12.6 “PORTE is useful for testing purposes or to synchronize more
Registers” for more information. than one device operating in parallel.
6.5 Watchdog Timer (WDT) Reset

The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDT instruction within the time-out
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See Section 10.0
“Watchdog Timer (WDT)” for more information.
6.6 RESET Instruction

A RESET instruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘0’. See Table 6-4
for default conditions after a RESET instruction has
occurred.
6.7 Stack Overflow/Underflow Reset

The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in Configuration
Words. See Section 3.5.2 “Overflow/Underflow
Reset” for more information.
6.8 Programming Mode Exit

Upon exit of Programming mode, the device will
behave as if a POR had just occurred.

PIC16(L)F1933
FIGURE 6-3: RESET START-UP SEQUENCE
VDD
Internal POR
TPWRT
Power-Up Timer
MCLR
TMCLR
Internal RESET
Oscillator Modes
External Crystal
TOST
Oscillator Start-Up Timer
Oscillator
FOSC
Internal Oscillator
Oscillator
FOSC
External Clock (EC)
CLKIN
FOSC

PIC16(L)F1933
6.11 Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON register are updated to indicate the cause of the
Reset. Table 6-3 and Table 6-4 show the Reset
conditions of these registers.
TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE

STKOVF STKUNF RMCLR RI POR BOR TO PD Condition
0 0 1 1 0 x 1 1 Power-on Reset
0 0 1 1 0 x 0 x Illegal, TO is set on POR
0 0 1 1 0 x x 0 Illegal, PD is set on POR
0 0 1 1 u 0 1 1 Brown-out Reset
u u u u u u 0 u WDT Reset
u u u u u u 0 0 WDT Wake-up from Sleep
u u u u u u 1 0 Interrupt Wake-up from Sleep
u u 0 u u u u u MCLR Reset during normal operation
u u 0 u u u 1 0 MCLR Reset during Sleep
u u u 0 u u u u RESET Instruction Executed
1 u u u u u u u Stack Overflow Reset (STVREN = 1)
u 1 u u u u u u Stack Underflow Reset (STVREN = 1)
TABLE 6-4: RESET CONDITION FOR SPECIAL REGISTERS(2)

Program STATUS PCON
Condition
Counter Register Register
Power-on Reset 0000h ---1 1000 00-- 110x
MCLR Reset during normal operation 0000h ---u uuuu uu-- 0uuu
MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu
WDT Reset 0000h ---0 uuuu uu-- uuuu
WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu
Brown-out Reset 0000h ---1 1uuu 00-- 11u0
(1)
Interrupt Wake-up from Sleep PC + 1 ---1 0uuu uu-- uuuu
RESET Instruction Executed 0000h ---u uuuu uu-- u0uu
Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu
Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on
the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
2: If a Status bit is not implemented, that bit will be read as ‘0’.

PIC16(L)F1933
6.12 Power Control (PCON) Register
The Power Control (PCON) register contains flag bits
to differentiate between a:
• Reset Instruction Reset (RI)
• Stack Overflow Reset (STKOVF)
• Stack Underflow Reset (STKUNF)
• MCLR Reset (RMCLR)
The PCON register bits are shown in Register 6-2.
6.13 Register Definitions: Power Control
REGISTER 6-2: PCON: POWER CONTROL REGISTER

R/W/HS-0/q R/W/HS-0/q U-0 U-0 R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u
STKOVF STKUNF — — RMCLR RI POR BOR
bit 7 bit 0
Legend:
HC = Bit is cleared by hardware HS = Bit is set by hardware
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets
bit 7 STKOVF: Stack Overflow Flag bit

1 = A Stack Overflow occurred
0 = A Stack Overflow has not occurred or set to ‘0’ by firmware
bit 6 STKUNF: Stack Underflow Flag bit
1 = A Stack Underflow occurred
0 = A Stack Underflow has not occurred or set to ‘0’ by firmware
bit 3 RMCLR: MCLR Reset Flag bit
1 = A MCLR Reset has not occurred or set to ‘1’ by firmware
0 = A MCLR Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs)
bit 2 RI: RESET Instruction Flag bit
1 = A RESET instruction has not been executed or set to ‘1’ by firmware
0 = A RESET instruction has been executed (set to ‘0’ in hardware upon executing a RESET instruction)
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset
occurs)

PIC16(L)F1933
TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Register
on Page
BORCON SBOREN — — — — — — BORRDY 71
PCON STKOVF STKUNF — — RMCLR RI POR BOR 75
STATUS — — — TO PD Z DC C 18
WDTCON — — WDTPS<4:0> SWDTEN 97
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

PIC16(L)F1933
7.0 INTERRUPTS
The interrupt feature allows certain events to preempt
normal program flow. Firmware is used to determine
the source of the interrupt and act accordingly. Some
interrupts can be configured to wake the MCU from
Sleep mode.
This chapter contains the following information for
Interrupts:
• Operation
• Interrupt Latency
• Interrupts During Sleep
• INT Pin
• Automatic Context Saving
Many peripherals produce interrupts. Refer to the
corresponding chapters for details.
A block diagram of the interrupt logic is shown in
Figure 7-1.
FIGURE 7-1: INTERRUPT LOGIC
TMR0IF Wake-up
TMR0IE (If in Sleep mode)
INTF
Peripheral Interrupts INTE
(TMR1IF) PIR1<0>
IOCIF Interrupt
(TMR1IF) PIR1<0> IOCIE to CPU
PEIE
PIRn<7>
PIEn<7> GIE

PIC16(L)F1933
7.1 Operation 7.2 Interrupt Latency
Interrupts are disabled upon any device Reset. They Interrupt latency is defined as the time from when the
are enabled by setting the following bits: interrupt event occurs to the time code execution at the
• GIE bit of the INTCON register interrupt vector begins. The latency for synchronous
interrupts is three or four instruction cycles. For
• Interrupt Enable bit(s) for the specific interrupt
asynchronous interrupts, the latency is three to five
event(s)
instruction cycles, depending on when the interrupt
• PEIE bit of the INTCON register (if the Interrupt occurs. See Figure 7-2 and Figure 7-3 for more details.
Enable bit of the interrupt event is contained in the
PIE1, PIE2 and PIE3 registers)
The INTCON, PIR1, PIR2 and PIR3 registers record
individual interrupts via interrupt flag bits. Interrupt flag
bits will be set, regardless of the status of the GIE, PEIE
and individual interrupt enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Counter (PC) is pushed onto the
stack
• Critical registers are automatically saved to the
shadow registers (See Section 7.5 “Automatic
Context Saving”)
• PC is loaded with the interrupt vector 0004h
The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.

PIC16(L)F1933
FIGURE 7-2: INTERRUPT LATENCY
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKOUT Interrupt Sampled

during Q1
Interrupt
GIE
PC PC-1 PC PC+1 0004h 0005h
Execute 1 Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h)
Interrupt
GIE
PC+1/FSR New PC/

PC PC-1 PC 0004h 0005h
ADDR PC+1
Execute 2 Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h)
Interrupt
GIE
PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h
Execute 3 Cycle Instruction at PC INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h)
Interrupt
GIE
PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h
Execute 3 Cycle Instruction at PC INST(PC) NOP NOP NOP NOP Inst(0004h)

PIC16(L)F1933
FIGURE 7-3: INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF (5) Interrupt Latency (2)
GIE
INSTRUCTION FLOW
PC PC PC + 1 PC + 1 0004h 0005h
Instruction
Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h)
Instruction Dummy Cycle Inst (0004h)

Inst (PC – 1) Inst (PC) Dummy Cycle
Executed
Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT not available in all Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 30.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.

PIC16(L)F1933
7.3 Interrupts During Sleep
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to the Section 9.0 “Power-
Down Mode (Sleep)” for more details.
7.4 INT Pin

The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the INTCON register. The
INTEDG bit of the OPTION_REG register determines on
which edge the interrupt will occur. When the INTEDG
bit is set, the rising edge will cause the interrupt. When
the INTEDG bit is clear, the falling edge will cause the
interrupt. The INTF bit of the INTCON register will be set
when a valid edge appears on the INT pin. If the GIE and
INTE bits are also set, the processor will redirect
program execution to the interrupt vector.
7.5 Automatic Context Saving

Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the Shadow registers:
• W register
• STATUS register (except for TO and PD)
• BSR register
• FSR registers
• PCLATH register
Upon exiting the Interrupt Service Routine (ISR), these
registers are automatically restored. Any modifications
to these registers during the ISR will be lost. If
modifications to any of these registers are desired, the
corresponding Shadow register should be modified
and the value will be restored when exiting the ISR.
The Shadow registers are available in Bank 31 and are
readable and writable. Depending on the user’s
application, other registers may also need to be saved.

PIC16(L)F1933
7.6 Register Definitions: Interrupt Control
REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0
GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF
bit 7 bit 0
Legend:
bit 7 GIE: Global Interrupt Enable bit

1 = Enables all active interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all active peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4 INTE: INT External Interrupt Enable bit
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
bit 3 IOCIE: Interrupt-on-Change Enable bit
1 = Enables the interrupt-on-change
0 = Disables the interrupt-on-change
bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed
0 = TMR0 register did not overflow
bit 1 INTF: INT External Interrupt Flag bit
1 = The INT external interrupt occurred
0 = The INT external interrupt did not occur
bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit
1 = When at least one of the interrupt-on-change pins changed state
0 = None of the interrupt-on-change pins have changed state
Note 1: The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCBF register
have been cleared by software.
Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.

PIC16(L)F1933
7.6.1 PIE1 REGISTER
REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
Legend:
bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit

1 = Enables the Timer1 Gate Acquisition interrupt
0 = Disables the Timer1 Gate Acquisition interrupt
bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5 RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4 TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3 SSPIE: Synchronous Serial Port (MSSP) Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt
bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt
Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

PIC16(L)F1933
7.6.2 PIE2 REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0
OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE
bit 7 bit 0
Legend:
bit 7 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables the Oscillator Fail interrupt
0 = Disables the Oscillator Fail interrupt
bit 6 C2IE: Comparator C2 Interrupt Enable bit
1 = Enables the Comparator C2 interrupt
0 = Disables the Comparator C2 interrupt
bit 5 C1IE: Comparator C1 Interrupt Enable bit
1 = Enables the Comparator C1 interrupt
0 = Disables the Comparator C1 interrupt
bit 4 EEIE: EEPROM Write Completion Interrupt Enable bit
1 = Enables the EEPROM Write Completion interrupt
0 = Disables the EEPROM Write Completion interrupt
bit 3 BCLIE: MSSP Bus Collision Interrupt Enable bit
1 = Enables the MSSP Bus Collision Interrupt
0 = Disables the MSSP Bus Collision Interrupt
bit 2 LCDIE: LCD Module Interrupt Enable bit
1 = Enables the LCD module interrupt
0 = Disables the LCD module interrupt


PIC16(L)F1933
7.6.3 PIE3 REGISTER

U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 U-0
— CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE —
bit 7 bit 0
Legend:

1 = Enables the TMR6 to PR6 match interrupt
0 = Disables the TMR6 to PR6 match interrupt
1 = Enables the TMR4 to PR4 match interrupt
0 = Disables the TMR4 to PR4 match interrupt


PIC16(L)F1933
7.6.4 PIR1 REGISTER
REGISTER 7-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
Legend:
bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending
bit 6 ADIF: A/D Converter Interrupt Flag bit
bit 5 RCIF: USART Receive Interrupt Flag bit
bit 4 TXIF: USART Transmit Interrupt Flag bit
bit 3 SSPIF: Synchronous Serial Port (MSSP) Interrupt Flag bit
bit 2 CCP1IF: CCP1 Interrupt Flag bit
bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit
bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit

User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.

PIC16(L)F1933
7.6.5 PIR2 REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0
OSFIF C2IF C1IF EEIF BCLIF LCDIF — CCP2IF
bit 7 bit 0
Legend:
bit 7 OSFIF: Oscillator Fail Interrupt Flag bit

bit 6 C2IF: Comparator C2 Interrupt Flag bit
bit 5 C1IF: Comparator C1 Interrupt Flag bit
bit 4 EEIF: EEPROM Write Completion Interrupt Flag bit
bit 3 BCLIF: MSSP Bus Collision Interrupt Flag bit
bit 2 LCDIF: LCD Module Interrupt Flag bit


PIC16(L)F1933
7.6.6 PIR3 REGISTER

— CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF —
bit 7 bit 0
Legend:

bit 3 TMR6IF: TMR6 to PR6 Match Interrupt Flag bit
bit 1 TMR4IF: TMR4 to PR4 Match Interrupt Flag bit


PIC16(L)F1933
TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Register
on Page
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 82
OPTION_REG WPUEN INTEDG TMROCS TMROSE PSA PS<2:0> 173
PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 83
PIE3 — CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE — 85
PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 86
PIR3 — CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF — 88
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupts.

PIC16(L)F1933
NOTES:

PIC16(L)F1933
8.0 LOW DROPOUT (LDO) On power-up, the external capacitor will load the LDO
voltage regulator. To prevent erroneous operation, the
VOLTAGE REGULATOR
device is held in Reset while a constant current source
The PIC16F193X has an internal Low Dropout charges the external capacitor. After the cap is fully
Regulator (LDO) which provides operation above 3.6V. charged, the device is released from Reset. For more
The LDO regulates a voltage for the internal device information on the constant current rate, refer to the
logic while permitting the VDD and I/O pins to operate LDO Regulator Characteristics Table in Section 30.0
at a higher voltage. There is no user enable/disable “Electrical Specifications”.
control available for the LDO, it is always active. The
PIC16LF193X operates at a maximum VDD of 3.6V and
does not incorporate an LDO.
A device I/O pin may be configured as the LDO voltage
output, identified as the VCAP pin. Although not
required, an external low-ESR capacitor may be
connected to the VCAP pin for additional regulator
stability.
The VCAPEN<1:0> bits of Configuration Words
determines which pin is assigned as the VCAP pin.
Refer to Table 8-1.
TABLE 8-1: VCAPEN<1:0> SELECT BITS

VCAPEN<1:0> Pin
00 RA0
01 RA5
10 RA6
11 No VCAP
TABLE 8-2: SUMMARY OF CONFIGURATION WORD WITH LDO

Register
on Page

CONFIG2 48
7:0 — — VCAPEN<1:0>(1) — — WRT1 WRT0
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by LDO.

PIC16(L)F1933
NOTES:

PIC16(L)F1933
9.0 POWER-DOWN MODE (SLEEP) 9.1 Wake-up from Sleep
The Power-Down mode is entered by executing a The device can wake-up from Sleep through one of the
SLEEP instruction. following events:
Upon entering Sleep mode, the following conditions 1. External Reset input on MCLR pin, if enabled
exist: 2. BOR Reset, if enabled
1. WDT will be cleared but keeps running, if 3. POR Reset
enabled for operation during Sleep. 4. Watchdog Timer, if enabled
2. PD bit of the STATUS register is cleared. 5. Any external interrupt
3. TO bit of the STATUS register is set. 6. Interrupts by peripherals capable of running
4. CPU clock is disabled. during Sleep (see individual peripheral for more
5. 31 kHz LFINTOSC is unaffected and peripherals information)
that operate from it may continue operation in The first three events will cause a device Reset. The
Sleep. last three events are considered a continuation of
6. Timer1 and peripherals that operate from program execution. To determine whether a device
Timer1 continue operation in Sleep when the Reset or wake-up event occurred, refer to Section 6.11
Timer1 clock source selected is: “Determining the Cause of a Reset”.
• LFINTOSC When the SLEEP instruction is being executed, the next
• T1CKI instruction (PC + 1) is prefetched. For the device to
• Timer1 oscillator wake-up through an interrupt event, the corresponding
interrupt enable bit must be enabled. Wake-up will
• CapSense oscillator
occur regardless of the state of the GIE bit. If the GIE
7. ADC is unaffected, if the dedicated FRC clock is bit is disabled, the device continues execution at the
selected. instruction after the SLEEP instruction. If the GIE bit is
8. Capacitive Sensing oscillator is unaffected. enabled, the device executes the instruction after the
9. I/O ports maintain the status they had before SLEEP instruction, the device will then call the Interrupt
SLEEP was executed (driving high, low or high- Service Routine. In cases where the execution of the
impedance). instruction following SLEEP is not desirable, the user
10. Resets other than WDT are not affected by should have a NOP after the SLEEP instruction.
Sleep mode. The WDT is cleared when the device wakes up from
Refer to individual chapters for more details on Sleep, regardless of the source of wake-up.
peripheral operation during Sleep.
To minimize current consumption, the following
conditions should be considered:
• I/O pins should not be floating
• External circuitry sinking current from I/O pins
• Internal circuitry sourcing current from I/O pins
• Current draw from pins with internal weak pull-ups
• Modules using 31 kHz LFINTOSC
• Modules using Timer1 oscillator
I/O pins that are high-impedance inputs should be
pulled to VDD or VSS externally to avoid switching
currents caused by floating inputs.
Examples of internal circuitry that might be sourcing
current include modules such as the DAC and FVR
modules. See Section 17.0 “Digital-to-Analog
Converter (DAC) Module” and Section 14.0 “Fixed
Voltage Reference (FVR)” for more information on
these modules.

PIC16(L)F1933
9.1.1 WAKE-UP USING INTERRUPTS • If the interrupt occurs during or after the execution
of a SLEEP instruction
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit - SLEEP instruction will be completely
and interrupt flag bit set, one of the following will occur: executed
- Device will immediately wake-up from Sleep
• If the interrupt occurs before the execution of a
SLEEP instruction - WDT and WDT prescaler will be cleared
- SLEEP instruction will execute as a NOP. - TO bit of the STATUS register will be set
- WDT and WDT prescaler will not be cleared - PD bit of the STATUS register will be cleared.
- TO bit of the STATUS register will not be set Even if the flag bits were checked before executing a
- PD bit of the STATUS register will not be SLEEP instruction, it may be possible for flag bits to
cleared. become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
FIGURE 9-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1(1)
CLKOUT(2) TOST(3)
Interrupt flag Interrupt Latency (4)
GIE bit
(INTCON reg.) Processor in
Sleep
Instruction Flow
PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h
Instruction Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
Fetched Inst(PC) = Sleep
Instruction Sleep Inst(PC + 1) Forced NOP Forced NOP
Executed Inst(PC - 1) Inst(0004h)
Note 1: XT, HS or LP Oscillator mode assumed.

2: CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference.
3: TOST = 1024 TOSC (drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes.
4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Register on
Page

IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 131
IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 131
IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 131
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in Power-Down mode.

PIC16(L)F1933
10.0 WATCHDOG TIMER (WDT)
The Watchdog Timer is a system timer that generates
a Reset if the firmware does not issue a CLRWDT
instruction within the time-out period. The Watchdog
Timer is typically used to recover the system from
unexpected events.
The WDT has the following features:
• Independent clock source
• Multiple operating modes
- WDT is always on
- WDT is off when in Sleep
- WDT is controlled by software
- WDT is always off
• Configurable time-out period is from 1 ms to 256
seconds (nominal)
• Multiple Reset conditions
• Operation during Sleep
FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM
WDTE<1:0> = 01
SWDTEN
WDTE<1:0> = 11 23-bit Programmable

LFINTOSC WDT Time-out
Prescaler WDT
WDTE<1:0> = 10
Sleep
WDTPS<4:0>

PIC16(L)F1933
10.1 Independent Clock Source 10.3 Time-Out Period
The WDT derives its time base from the 31 kHz The WDTPS bits of the WDTCON register set the
LFINTOSC internal oscillator. Time intervals in this time-out period from 1 ms to 256 seconds (nominal).
chapter are based on a nominal interval of 1 ms. See After a Reset, the default time-out period is two
the Electrical Specifications Chapters for the seconds.
LFINTOSC tolerances.
10.4 Clearing the WDT
10.2 WDT Operating Modes
The WDT is cleared when any of the following
The Watchdog Timer module has four operating modes conditions occur:
controlled by the WDTE<1:0> bits in Configuration • Any Reset
Words. See Table 10-1.
• CLRWDT instruction is executed
10.2.1 WDT IS ALWAYS ON • Device enters Sleep
When the WDTE bits of Configuration Words are set to • Device wakes up from Sleep
‘11’, the WDT is always on. • Oscillator fail
WDT protection is active during Sleep. • WDT is disabled
• Oscillator Start-up TImer (OST) is running
10.2.2 WDT IS OFF IN SLEEP See Table 10-2 for more information.
When the WDTE bits of Configuration Words are set to
‘10’, the WDT is on, except in Sleep. 10.5 Operation During Sleep
WDT protection is not active during Sleep. When the device enters Sleep, the WDT is cleared. If
the WDT is enabled during Sleep, the WDT resumes
10.2.3 WDT CONTROLLED BY SOFTWARE
counting.
When the WDTE bits of Configuration Words are set to
When the device exits Sleep, the WDT is cleared
‘01’, the WDT is controlled by the SWDTEN bit of the
again. The WDT remains clear until the OST, if
WDTCON register.
enabled, completes. See Section 5.0 “Oscillator
WDT protection is unchanged by Sleep. See Module (with Fail-Safe Clock Monitor)” for more
Table 10-1 for more details. information on the OST.
TABLE 10-1: WDT OPERATING MODES When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device wakes
Device WDT up and resumes operation. The TO and PD bits in the
WDTE<1:0> SWDTEN
Mode Mode STATUS register are changed to indicate the event. See
Section 3.0 “Memory Organization” and STATUS
11 X X Active register (Register 3-1) for more information.
Awake Active
10 X
Sleep Disabled
1 X Active
01
0 X Disabled
00 X X Disabled
TABLE 10-2: WDT CLEARING CONDITIONS

Conditions WDT
WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
Cleared
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST
Change INTOSC divider (IRCF bits) Unaffected

PIC16(L)F1933
10.6 Register Definitions: Watchdog Control
REGISTER 10-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER

U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0
— — WDTPS<4:0> SWDTEN
bit 7 bit 0
Legend:
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets

bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits
Bit Value = Prescale Rate
11111 = Reserved. Results in minimum interval (1:32)
•
•
•
10011 = Reserved. Results in minimum interval (1:32)
10010 = 1:8388608 (223) (Interval 256s nominal)

01011 = 1:65536 (Interval 2s nominal) (Reset value)
01010 = 1:32768 (Interval 1s nominal)
01001 = 1:16384 (Interval 512 ms nominal)
bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit
If WDTE<1:0> = 00:
If WDTE<1:0> = 01:
1 = WDT is turned on
0 = WDT is turned off
If WDTE<1:0> = 1x:

PIC16(L)F1933
TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Register
on Page
OSCCON SPLLEN IRCF<3:0> — SCS<1:0> 66
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.
TABLE 10-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER

Register
on Page

CONFIG1 46
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.

PIC16(L)F1933
11.0 DATA EEPROM AND FLASH 11.1 EEADRL and EEADRH Registers
PROGRAM MEMORY The EEADRH:EEADRL register pair can address up to
CONTROL a maximum of 256 bytes of data EEPROM or up to a
maximum of 32K words of program memory.
The Data EEPROM and Flash program memory are
readable and writable during normal operation (full VDD When selecting a program address value, the MSB of
range). These memories are not directly mapped in the the address is written to the EEADRH register and the
register file space. Instead, they are indirectly LSB is written to the EEADRL register. When selecting
addressed through the Special Function Registers a EEPROM address value, only the LSB of the address
(SFRs). There are six SFRs used to access these is written to the EEADRL register.
memories:
11.1.1 EECON1 AND EECON2 REGISTERS
• EECON1
EECON1 is the control register for EE memory
• EECON2
accesses.
• EEDATL
Control bit EEPGD determines if the access will be a
• EEDATH
program or data memory access. When clear, any
• EEADRL subsequent operations will operate on the EEPROM
• EEADRH memory. When set, any subsequent operations will
When interfacing the data memory block, EEDATL operate on the program memory. On Reset, EEPROM is
holds the 8-bit data for read/write, and EEADRL holds selected by default.
the address of the EEDATL location being accessed. Control bits RD and WR initiate read and write,
These devices have 256 bytes of data EEPROM with respectively. These bits cannot be cleared, only set, in
an address range from 0h to 0FFh. software. They are cleared in hardware at completion
When accessing the program memory block, the of the read or write operation. The inability to clear the
EEDATH:EEDATL register pair forms a 2-byte word WR bit in software prevents the accidental, premature
that holds the 14-bit data for read/write, and the termination of a write operation.
EEADRL and EEADRH registers form a 2-byte word The WREN bit, when set, will allow a write operation to
that holds the 15-bit address of the program memory occur. On power-up, the WREN bit is clear. The
location being read. WRERR bit is set when a write operation is interrupted
The EEPROM data memory allows byte read and write. by a Reset during normal operation. In these situations,
An EEPROM byte write automatically erases the following Reset, the user can check the WRERR bit
location and writes the new data (erase before write). and execute the appropriate error handling routine.
The write time is controlled by an on-chip timer. The Interrupt flag bit EEIF of the PIR2 register is set when
write/erase voltages are generated by an on-chip write is complete. It must be cleared in the software.
charge pump rated to operate over the voltage range of Reading EECON2 will read all ‘0’s. The EECON2
the device for byte or word operations. register is used exclusively in the data EEPROM write
Depending on the setting of the Flash Program sequence. To enable writes, a specific pattern must be
Memory Self Write Enable bits WRT<1:0> of the written to EECON2.
Configuration Words, the device may or may not be
able to write certain blocks of the program memory.
However, reads from the program memory are always
allowed.
When the device is code-protected, the device
programmer can no longer access data or program
memory. When code-protected, the CPU may continue
to read and write the data EEPROM memory and Flash
program memory.

PIC16(L)F1933
11.2 Using the Data EEPROM 11.2.2 WRITING TO THE DATA EEPROM
MEMORY
The data EEPROM is a high-endurance, byte
addressable array that has been optimized for the To write an EEPROM data location, the user must first
storage of frequently changing information (e.g., write the address to the EEADRL register and the data
program variables or other data that are updated to the EEDATL register. Then the user must follow a
often). When variables in one section change specific sequence to initiate the write for each byte.
frequently, while variables in another section do not The write will not initiate if the above sequence is not
change, it is possible to exceed the total number of followed exactly (write 55h to EECON2, write AAh to
write cycles to the EEPROM without exceeding the EECON2, then set the WR bit) for each byte. Interrupts
total number of write cycles to a single byte. Refer to should be disabled during this code segment.
Section 30.0 “Electrical Specifications”. If this is the
Additionally, the WREN bit in EECON1 must be set to
case, then a refresh of the array must be performed.
enable write. This mechanism prevents accidental
For this reason, variables that change infrequently
writes to data EEPROM due to errant (unexpected)
(such as constants, IDs, calibration, etc.) should be
code execution (i.e., lost programs). The user should
stored in Flash program memory.
keep the WREN bit clear at all times, except when
11.2.1 READING THE DATA EEPROM updating EEPROM. The WREN bit is not cleared
by hardware.
MEMORY
After a write sequence has been initiated, clearing the
To read a data memory location, the user must write the
WREN bit will not affect this write cycle. The WR bit will
address to the EEADRL register, clear the EEPGD and
be inhibited from being set unless the WREN bit is set.
CFGS control bits of the EECON1 register, and then
set control bit RD. The data is available at the very next At the completion of the write cycle, the WR bit is
cycle, in the EEDATL register; therefore, it can be read cleared in hardware and the EE Write Complete
in the next instruction. EEDATL will hold this value until Interrupt Flag bit (EEIF) is set. The user can either
another read or until it is written to by the user (during enable this interrupt or poll this bit. EEIF must be
a write operation). cleared by software.
EXAMPLE 11-1: DATA EEPROM READ 11.2.3 PROTECTION AGAINST SPURIOUS

WRITE
BANKSEL EEADRL ;
MOVLW DATA_EE_ADDR ; There are conditions when the user may not want to
MOVWF EEADRL ;Data Memory write to the data EEPROM memory. To protect against
;Address to read spurious EEPROM writes, various mechanisms have
BCF EECON1, CFGS ;Deselect Config space been built-in. On power-up, WREN is cleared. Also, the
BCF EECON1, EEPGD;Point to DATA memory Power-up Timer (64 ms duration) prevents EEPROM
BSF EECON1, RD ;EE Read
write.
MOVF EEDATL, W ;W = EEDATL
The write initiate sequence and the WREN bit together
help prevent an accidental write during:
• Brown-out
Note: Data EEPROM can be read regardless of
the setting of the CPD bit. • Power Glitch
• Software Malfunction
11.2.4 DATA EEPROM OPERATION

DURING CODE-PROTECT
Data memory can be code-protected by programming
the CPD bit in the Configuration Words to ‘0’.
When the data memory is code-protected, only the
CPU is able to read and write data to the data
EEPROM. It is recommended to code-protect the
program memory when code-protecting data memory.
This prevents anyone from replacing your program with
a program that will access the contents of the data
EEPROM.

PIC16(L)F1933
EXAMPLE 11-2: DATA EEPROM WRITE
BANKSEL EEADRL ;
MOVLW DATA_EE_ADDR ;
MOVWF EEADRL ;Data Memory Address to write
MOVLW DATA_EE_DATA ;
MOVWF EEDATL ;Data Memory Value to write
BCF EECON1, CFGS ;Deselect Configuration space
BCF EECON1, EEPGD ;Point to DATA memory
BSF EECON1, WREN ;Enable writes
BCF INTCON, GIE ;Disable INTs.

MOVLW 55h ;
MOVWF EECON2 ;Write 55h
Sequence
Required
MOVLW 0AAh ;
MOVWF EECON2 ;Write AAh
BSF EECON1, WR ;Set WR bit to begin write
BSF INTCON, GIE ;Enable Interrupts
BCF EECON1, WREN ;Disable writes
BTFSC EECON1, WR ;Wait for write to complete
GOTO $-2 ;Done
FIGURE 11-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Flash ADDR PC PC + 1 EEADRH,EEADRL PC +3

PC+3 PC + 4 PC + 5
Flash Data INSTR (PC) INSTR (PC + 1) EEDATH,EEDATL INSTR (PC + 3) INSTR (PC + 4)
INSTR(PC - 1) BSF EECON1,RD INSTR(PC + 1) Forced NOP INSTR(PC + 3) INSTR(PC + 4)

executed here executed here executed here executed here executed here executed here
RD bit
EEDATH
EEDATL
Register

PIC16(L)F1933
11.3 Flash Program Memory Overview The size of a program memory row and the number of
program memory write latches may vary by device.
It is important to understand the Flash program See Table 11-1 for details.
memory structure for erase and programming
operations. Flash Program memory is arranged in 11.3.1 READING THE FLASH PROGRAM
rows. A row consists of a fixed number of 14-bit MEMORY
program memory words. A row is the minimum block
size that can be erased by user software. To read a program memory location, the user must:
Flash program memory may only be written or erased 1. Write the Least and Most Significant address
if the destination address is in a segment of memory bits to the EEADRH:EEADRL register pair.
that is not write-protected, as defined in bits WRT<1:0> 2. Clear the CFGS bit of the EECON1 register.
of Configuration Words. 3. Set the EEPGD control bit of the EECON1
After a row has been erased, the user can reprogram register.
all or a portion of this row. Data to be written into the 4. Then, set control bit RD of the EECON1 register.
program memory row is written to 14-bit wide data write Once the read control bit is set, the program memory
latches. These write latches are not directly accessible Flash controller will use the second instruction cycle to
to the user, but may be loaded via sequential writes to read the data. This causes the second instruction
the EEDATH:EEDATL register pair. immediately following the “BSF EECON1,RD” instruction
Note: If the user wants to modify only a portion to be ignored. The data is available in the very next cycle,
of a previously programmed row, then the in the EEDATH:EEDATL register pair; therefore, it can
contents of the entire row must be read be read as two bytes in the following instructions.
and saved in RAM prior to the erase. EEDATH:EEDATL register pair will hold this value until
another read or until it is written to by the user.
The number of data write latches may not be equivalent
to the number of row locations. During programming, Note 1: The two instructions following a program
user software may need to fill the set of write latches memory read are required to be NOPs.
and initiate a programming operation multiple times in This prevents the user from executing a
order to fully reprogram an erased row. For example, a two-cycle instruction on the next
device with a row size of 32 words and eight write instruction after the RD bit is set.
latches will need to load the write latches with data and 2: Flash program memory can be read
initiate a programming operation four times. regardless of the setting of the CP bit.
TABLE 11-1: FLASH MEMORY ORGANIZATION BY DEVICE

Device Erase Block (Row) Size/Boundary Number of Write Latches/Boundary
PIC16(L)F1933 32 words, EEADRL<4:0> = 00000 8 words, EEADRL<2:0> = 000

PIC16(L)F1933
EXAMPLE 11-3: FLASH PROGRAM MEMORY READ
* This code block will read 1 word of program
* memory at the memory address:
PROG_ADDR_HI: PROG_ADDR_LO
* data will be returned in the variables;
* PROG_DATA_HI, PROG_DATA_LO
BANKSEL EEADRL ; Select Bank for EEPROM registers

MOVLW PROG_ADDR_LO ;
MOVWF EEADRL ; Store LSB of address
MOVLW PROG_ADDR_HI ;
MOVWL EEADRH ; Store MSB of address
BCF EECON1,CFGS ; Do not select Configuration Space

BSF EECON1,EEPGD ; Select Program Memory
BCF INTCON,GIE ; Disable interrupts
BSF EECON1,RD ; Initiate read
NOP ; Executed (Figure 11-1)
NOP ; Ignored (Figure 11-1)
BSF INTCON,GIE ; Restore interrupts
MOVF EEDATL,W ; Get LSB of word

MOVWF PROG_DATA_LO ; Store in user location
MOVF EEDATH,W ; Get MSB of word
MOVWF PROG_DATA_HI ; Store in user location

PIC16(L)F1933
11.3.2 ERASING FLASH PROGRAM The following steps should be completed to load the
MEMORY write latches and program a block of program memory.
These steps are divided into two parts. First, all write
While executing code, program memory can only be
latches are loaded with data except for the last program
erased by rows. To erase a row:
memory location. Then, the last write latch is loaded
1. Load the EEADRH:EEADRL register pair with and the programming sequence is initiated. A special
the address of new row to be erased. unlock sequence is required to load a write latch with
2. Clear the CFGS bit of the EECON1 register. data or initiate a Flash programming operation. This
3. Set the EEPGD, FREE and WREN bits of the unlock sequence should not be interrupted.
EECON1 register. 1. Set the EEPGD and WREN bits of the EECON1
4. Write 55h, then AAh, to EECON2 (Flash register.
programming unlock sequence). 2. Clear the CFGS bit of the EECON1 register.
5. Set control bit WR of the EECON1 register to 3. Set the LWLO bit of the EECON1 register. When
begin the erase operation. the LWLO bit of the EECON1 register is ‘1’, the
6. Poll the FREE bit in the EECON1 register to write sequence will only load the write latches
determine when the row erase has completed. and will not initiate the write to Flash program
memory.
See Example 11-4.
4. Load the EEADRH:EEADRL register pair with
After the “BSF EECON1,WR” instruction, the processor the address of the location to be written.
requires two cycles to set up the erase operation. The
5. Load the EEDATH:EEDATL register pair with
user must place two NOP instructions after the WR bit is
the program memory data to be written.
set. The processor will halt internal operations for the
typical 2 ms erase time. This is not Sleep mode as the 6. Write 55h, then AAh, to EECON2, then set the
clocks and peripherals will continue to run. After the WR bit of the EECON1 register (Flash
erase cycle, the processor will resume operation with programming unlock sequence). The write latch
the third instruction after the EECON1 write instruction. is now loaded.
7. Increment the EEADRH:EEADRL register pair
11.3.3 WRITING TO FLASH PROGRAM to point to the next location.
MEMORY 8. Repeat steps 5 through 7 until all but the last
Program memory is programmed using the following write latch has been loaded.
steps: 9. Clear the LWLO bit of the EECON1 register.
When the LWLO bit of the EECON1 register is
1. Load the starting address of the word(s) to be
‘0’, the write sequence will initiate the write to
programmed.
Flash program memory.
2. Load the write latches with data.
10. Load the EEDATH:EEDATL register pair with
3. Initiate a programming operation. the program memory data to be written.
4. Repeat steps 1 through 3 until all data is written. 11. Write 55h, then AAh, to EECON2, then set the
Before writing to program memory, the word(s) to be WR bit of the EECON1 register (Flash
written must be erased or previously unwritten. programming unlock sequence). The entire
Program memory can only be erased one row at a time. latch block is now written to Flash program
No automatic erase occurs upon the initiation of the memory.
write. It is not necessary to load the entire write latch block
Program memory can be written one or more words at with user program data. However, the entire write latch
a time. The maximum number of words written at one block will be written to program memory.
time is equal to the number of write latches. See An example of the complete write sequence for eight
Figure 11-2 (block writes to program memory with eight words is shown in Example 11-5. The initial address is
write latches) for more details. The write latches are loaded into the EEADRH:EEADRL register pair; the
aligned to the address boundary defined by EEADRL eight words of data are loaded using indirect
as shown in Table 11-1. Write operations do not cross addressing.
these boundaries. At the completion of a program
memory write operation, the write latches are reset to
contain 0x3FFF. Note: The code sequence provided in
Example 11-5 must be repeated multiple
times to fully program an erased program
memory row.

PIC16(L)F1933
After the “BSF EECON1,WR” instruction, the processor continue to run. The processor does not stall when
requires two cycles to set up the write operation. The LWLO = 1, loading the write latches. After the write
user must place two NOP instructions after the WR bit is cycle, the processor will resume operation with the third
set. The processor will halt internal operations for the instruction after the EECON1 write instruction.
typical 2 ms, only during the cycle in which the write
takes place (i.e., the last word of the block write). This
is not Sleep mode as the clocks and peripherals will
FIGURE 11-2: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 8 WRITE LATCHES
7 5 0 7 0
EEDATH EEDATA
6 8
First word of block Last word of block

to be written to be written
14 14 14 14
EEADRL<2:0> = 000 EEADRL<2:0> = 001 EEADRL<2:0> = 010 EEADRL<2:0> = 111
Buffer Register Buffer Register Buffer Register Buffer Register
Program Memory

PIC16(L)F1933
EXAMPLE 11-4: ERASING ONE ROW OF PROGRAM MEMORY
; This row erase routine assumes the following:
; 1. A valid address within the erase block is loaded in ADDRH:ADDRL
; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
BCF INTCON,GIE ; Disable ints so required sequences will execute properly

BANKSEL EEADRL
MOVF ADDRL,W ; Load lower 8 bits of erase address boundary
MOVWF EEADRL
MOVF ADDRH,W ; Load upper 6 bits of erase address boundary
MOVWF EEADRH
BSF EECON1,EEPGD ; Point to program memory
BCF EECON1,CFGS ; Not configuration space
BSF EECON1,FREE ; Specify an erase operation
BSF EECON1,WREN ; Enable writes
MOVLW 55h ; Start of required sequence to initiate erase

MOVWF EECON2 ; Write 55h
MOVLW 0AAh ;
Sequence
Required
MOVWF EECON2 ; Write AAh

BSF EECON1,WR ; Set WR bit to begin erase
NOP ; Any instructions here are ignored as processor
; halts to begin erase sequence
NOP ; Processor will stop here and wait for erase complete.
; after erase processor continues with 3rd instruction
BCF EECON1,WREN ; Disable writes

BSF INTCON,GIE ; Enable interrupts

PIC16(L)F1933
EXAMPLE 11-5: WRITING TO FLASH PROGRAM MEMORY
; This write routine assumes the following:
; 1. The 16 bytes of data are loaded, starting at the address in DATA_ADDR
; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,
; stored in little endian format
; 3. A valid starting address (the least significant bits = 000) is loaded in ADDRH:ADDRL
; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
;
BCF INTCON,GIE ; Disable ints so required sequences will execute properly
BANKSEL EEADRH ; Bank 3
MOVF ADDRH,W ; Load initial address
MOVWF EEADRH ;
MOVF ADDRL,W ;
MOVWF EEADRL ;
MOVLW LOW DATA_ADDR ; Load initial data address
MOVWF FSR0L ;
MOVLW HIGH DATA_ADDR ; Load initial data address
MOVWF FSR0H ;
BSF EECON1,EEPGD ; Point to program memory
BCF EECON1,CFGS ; Not configuration space
BSF EECON1,WREN ; Enable writes
BSF EECON1,LWLO ; Only Load Write Latches
LOOP
MOVIW FSR0++ ; Load first data byte into lower
MOVWF EEDATL ;
MOVIW FSR0++ ; Load second data byte into upper
MOVWF EEDATH ;
MOVF EEADRL,W ; Check if lower bits of address are '000'

XORLW 0x07 ; Check if we're on the last of 8 addresses
ANDLW 0x07 ;
BTFSC STATUS,Z ; Exit if last of eight words,
GOTO START_WRITE ;
MOVLW 55h ; Start of required write sequence:

MOVLW 0AAh ;
Sequence
Required

BSF EECON1,WR ; Set WR bit to begin write
; halts to begin write sequence
NOP ; Processor will stop here and wait for write to complete.
; After write processor continues with 3rd instruction.
INCF EEADRL,F ; Still loading latches Increment address

GOTO LOOP ; Write next latches
START_WRITE
BCF EECON1,LWLO ; No more loading latches - Actually start Flash program
; memory write
MOVLW 55h ; Start of required write sequence:

Sequence
MOVLW 0AAh ;
Required

BSF EECON1,WR ; Set WR bit to begin write
; halts to begin write sequence
NOP ; Processor will stop here and wait for write complete.
; after write processor continues with 3rd instruction

BCF EECON1,WREN ; Disable writes
BSF INTCON,GIE ; Enable interrupts

PIC16(L)F1933
11.4 Modifying Flash Program Memory 11.5 User ID, Device ID and
When modifying existing data in a program memory
Configuration Word Access
row, and data within that row must be preserved, it must Instead of accessing program memory or EEPROM
first be read and saved in a RAM image. Program data memory, the User ID’s, Device ID/Revision ID and
memory is modified using the following steps: Configuration Words can be accessed when CFGS = 1
1. Load the starting address of the row to be in the EECON1 register. This is the region that would
modified. be pointed to by PC<15> = 1, but not all addresses are
2. Read the existing data from the row into a RAM accessible. Different access may exist for reads and
image. writes. Refer to Table 11-2.
3. Modify the RAM image to contain the new data When read access is initiated on an address outside the
to be written into program memory. parameters listed in Table 11-2, the EEDATH:EEDATL
4. Load the starting address of the row to be rewrit- register pair is cleared.
ten.
5. Erase the program memory row.
6. Load the write latches with data from the RAM
image.
7. Initiate a programming operation.
8. Repeat steps 6 and 7 as many times as required
to reprogram the erased row.
TABLE 11-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)
Address Function Read Access Write Access
8000h-8003h User IDs Yes Yes
8006h Device ID/Revision ID Yes No
8007h-8008h Configuration Words 1 and 2 Yes No
EXAMPLE 11-3: CONFIGURATION WORD AND DEVICE ID ACCESS

* This code block will read 1 word of program memory at the memory address:
* PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;
* PROG_DATA_HI, PROG_DATA_LO
BANKSEL EEADRL ; Select correct Bank

MOVLW PROG_ADDR_LO ;
MOVWF EEADRL ; Store LSB of address
CLRF EEADRH ; Clear MSB of address
BSF EECON1,CFGS ; Select Configuration Space

BCF INTCON,GIE ; Disable interrupts
BSF EECON1,RD ; Initiate read
NOP ; Executed (See Figure 11-1)
NOP ; Ignored (See Figure 11-1)
BSF INTCON,GIE ; Restore interrupts
MOVF EEDATL,W ; Get LSB of word

MOVWF PROG_DATA_LO ; Store in user location
MOVF EEDATH,W ; Get MSB of word
MOVWF PROG_DATA_HI ; Store in user location

PIC16(L)F1933
11.6 Write Verify
Depending on the application, good programming
practice may dictate that the value written to the data
EEPROM or program memory should be verified (see
Example 11-6) to the desired value to be written.
Example 11-6 shows how to verify a write to EEPROM.
EXAMPLE 11-6: EEPROM WRITE VERIFY

BANKSEL EEDATL ;
MOVF EEDATL, W ;EEDATL not changed
;from previous write
BSF EECON1, RD ;YES, Read the
;value written
XORWF EEDATL, W ;
BTFSS STATUS, Z ;Is data the same
GOTO WRITE_ERR ;No, handle error
: ;Yes, continue

PIC16(L)F1933
11.7 Register Definitions: Data EEPROM Control
REGISTER 11-1: EEDATL: EEPROM DATA LOW BYTE REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
EEDAT<7:0>
bit 7 bit 0
Legend:
bit 7-0 EEDAT<7:0>: Read/Write Value for EEPROM Data Byte or Least Significant bits of Program Memory
REGISTER 11-2: EEDATH: EEPROM DATA HIGH BYTE REGISTER

U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — EEDAT<13:8>
bit 7 bit 0
Legend:

bit 5-0 EEDAT<13:8>: Read/Write Value for Most Significant bits of Program Memory
REGISTER 11-3: EEADRL: EEPROM ADDRESS LOW BYTE REGISTER

EEADR<7:0>
bit 7 bit 0
Legend:
bit 7-0 EEADR<7:0>: Specifies the Least Significant bits for Program Memory Address or EEPROM Address
REGISTER 11-4: EEADRH: EEPROM ADDRESS HIGH BYTE REGISTER

U-1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
—(1) EEADR<14:8>
bit 7 bit 0
Legend:

bit 6-0 EEADR<14:8>: Specifies the Most Significant bits for Program Memory Address or EEPROM Address
Note 1: Unimplemented, read as ‘1’.

PIC16(L)F1933
REGISTER 11-5: EECON1: EEPROM CONTROL 1 REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W-x/q R/W-0/0 R/S/HC-0/0 R/S/HC-0/0
EEPGD CFGS LWLO FREE WRERR WREN WR RD
bit 7 bit 0
Legend:
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware
bit 7 EEPGD: Flash Program/Data EEPROM Memory Select bit

1 = Accesses program space Flash memory
0 = Accesses data EEPROM memory
bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Accesses Configuration, User ID and Device ID Registers
0 = Accesses Flash Program or data EEPROM Memory
bit 5 LWLO: Load Write Latches Only bit
If CFGS = 1 (Configuration space) OR CFGS = 0 and EEPGD = 1 (program Flash):
1 = The next WR command does not initiate a write; only the program memory latches are
updated.
0 = The next WR command writes a value from EEDATH:EEDATL into program memory latches
and initiates a write of all the data stored in the program memory latches.
If CFGS = 0 and EEPGD = 0: (Accessing data EEPROM)

LWLO is ignored. The next WR command initiates a write to the data EEPROM.
bit 4 FREE: Program Flash Erase Enable bit
If CFGS = 1 (Configuration space) OR CFGS = 0 and EEPGD = 1 (program Flash):
1 = Performs an erase operation on the next WR command (cleared by hardware after
completion of erase).
0 = Performs a write operation on the next WR command.
If EEPGD = 0 and CFGS = 0: (Accessing data EEPROM)

FREE is ignored. The next WR command will initiate both a erase cycle and a write cycle.
bit 3 WRERR: EEPROM Error Flag bit
1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set
automatically on any set attempt (write ‘1’) of the WR bit).
0 = The program or erase operation completed normally.
bit 2 WREN: Program/Erase Enable bit
1 = Allows program/erase cycles
0 = Inhibits programming/erasing of program Flash and data EEPROM
bit 1 WR: Write Control bit
1 = Initiates a program Flash or data EEPROM program/erase operation.
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
0 = Program/erase operation to the Flash or data EEPROM is complete and inactive.
bit 0 RD: Read Control bit
1 = Initiates an program Flash or data EEPROM read. Read takes one cycle. RD is cleared in
hardware. The RD bit can only be set (not cleared) in software.
0 = Does not initiate a program Flash or data EEPROM data read.

PIC16(L)F1933
REGISTER 11-6: EECON2: EEPROM CONTROL 2 REGISTER

W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0
EEPROM Control Register 2
bit 7 bit 0
Legend:
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
bit 7-0 Data EEPROM Unlock Pattern bits

To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the
EECON1 register. The value written to this register is used to unlock the writes. There are specific
timing requirements on these writes. Refer to Section 11.2.2 “Writing to the Data EEPROM
Memory” for more information.
TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM

Register
on Page
EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 111
EECON2 EEPROM Control Register 2 (not a physical register) 99*
EEADRL EEADRL<7:0> 110
EEADRH —(1) EEADRH<6:0 110
EEDATL EEDATL<7:0> 110
EEDATH — — EEDATH<5:0> 110
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Data EEPROM module.
* Page provides register information.

PIC16(L)F1933
12.0 I/O PORTS FIGURE 12-1: GENERIC I/O PORT
OPERATION
Each port has three standard registers for its operation.
These registers are:
• TRISx registers (data direction)
• PORTx registers (reads the levels on the pins of Read LATx
TRISx
the device)
• LATx registers (output latch) D Q
Some ports may have one or more of the following Write LATx
Write PORTx
additional registers. These registers are: CK VDD
• ANSELx (analog select) Data Register
• WPUx (weak pull-up)
Data Bus
In general, when a peripheral is enabled on a port pin,
I/O pin
that pin cannot be used as a general purpose output. Read PORTx
However, the pin can still be read.
To peripherals
VSS
ANSELx
TABLE 12-1: PORT AVAILABILITY PER
DEVICE
EXAMPLE 12-1: INITIALIZING PORTA
PORTB
PORTA
PORTC
PORTE
Device ; This code example illustrates

; initializing the PORTA register. The
; other ports are initialized in the same
PIC16(L)F1933 ● ● ● ● ; manner.
The Data Latch (LATx registers) is useful for
BANKSEL PORTA ;
read-modify-write operations on the value that the I/O
CLRF PORTA ;Init PORTA
pins are driving. BANKSEL LATA ;Data Latch
A write operation to the LATx register has the same CLRF LATA ;
effect as a write to the corresponding PORTx register. BANKSEL ANSELA ;
A read of the LATx register reads of the values held in CLRF ANSELA ;digital I/O
the I/O PORT latches, while a read of the PORTx BANKSEL TRISA ;
MOVLW B'00111000' ;Set RA<5:3> as inputs
register reads the actual I/O pin value.
MOVWF TRISA ;and set RA<2:0> as
Ports that support analog inputs have an associated ;outputs
ANSELx register. When an ANSEL bit is set, the digital
input buffer associated with that bit is disabled.
Disabling the input buffer prevents analog signal levels
on the pin between a logic high and low from causing
excessive current in the logic input circuitry. A
simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 12-1.

PIC16(L)F1933
12.1 Alternate Pin Function These bits have no effect on the values of any TRIS
register. PORT and TRIS overrides will be routed to the
The Alternate Pin Function Control (APFCON) register correct pin. The unselected pin will be unaffected.
is used to steer specific peripheral input and output
functions between different pins. The APFCON register
is shown in Register 12-1. For this device family, the
following functions can be moved between different
pins.
• SS (Slave Select)
• P2B output
• CCP2/P2A output
• CCP3/P3A output
• Timer1 gate
• SR Latch SRNQ output
• Comparator C2 output
12.2 Register Definitions: Alternate Pin Function Control
REGISTER 12-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER

— CCP3SEL T1GSEL P2BSEL SRNQSEL C2OUTSEL SSSEL CCP2SEL
bit 7 bit 0
Legend:
u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
bit 7 Unimplemented: Read as ‘0’.

bit 6 CCP3SEL: CCP3 Input/Output Pin Selection bit
0 = CCP3/P3A function is on RC6/TX/CK/CCP3/P3A/SEG9
1 = CCP3/P3A function is on RB5/AN13/CPS5/CCP3/P3A/T1G/COM1
bit 5 T1GSEL: Timer1 Gate Input Pin Selection bit
0 = T1G function is on RB5/AN13/CPS5/CCP3/P3A/T1G/COM1
1 = T1G function is on RC4/SDI/SDA/T1G/SEG11
bit 4 P2BSEL: CCP2 PWM B Output Pin Selection bit
0 = P2B function is on RC0/T1OSO/T1CKI/P2B
1 = P2B function is on RB5/AN13/P2B/CPS5/T1G/COM1
bit 3 SRNQSEL: SR Latch nQ Output Pin Selection bit
0 = SRnQ function is on RA5/AN4/C2OUT/SRnQ/SS/CPS7/SEG5/VCAP
1 = SRnQ function is on RA0/AN0/C12IN0-/C2OUT/SRnQ/SS/SEG12/VCAP
bit 2 C2OUTSEL: Comparator C2 Output Pin Selection bit
0 = C2OUT function is on RA5/AN4/C2OUT/SRnQ/SS/CPS7/SEG5/VCAP
1 = C2OUT function is on RA0/AN0/C12IN0-/C2OUT/SRnQ/SS/SEG12/VCAP
bit 1 SSSEL: SS Input Pin Selection bit
0 = SS function is on RA5/AN4/C2OUT/SRNQ/SS/CPS7/SEG5/VCAP
1 = SS function is on RA0/AN0/C12IN0-/C2OUT/SRNQ/SS/SEG12/VCAP
bit 0 CCP2SEL: CCP2 Input/Output Pin Selection bit
0 = CCP2/P2A function is on RC1/T1OSI/CCP2/P2A
1 = CCP2/P2A function is on RB3/AN9/C12IN2-/CPS3/CCP2/P2A/VLCD3

PIC16(L)F1933
12.3 PORTA Registers 12.3.4 PORTA FUNCTIONS AND OUTPUT
PRIORITIES
12.3.1 DATA REGISTER
Each PORTA pin is multiplexed with other functions. The
PORTA is an 8-bit wide, bidirectional port. The pins, their combined functions and their output priorities
corresponding data direction register is TRISA are shown in Table 12-2.
(Register 12-3). Setting a TRISA bit (= 1) will make the
When multiple outputs are enabled, the actual pin
corresponding PORTA pin an input (i.e., disable the
control goes to the peripheral with the highest priority.
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables Analog input functions, such as ADC, comparator and
output driver and puts the contents of the output latch CapSense inputs, are not shown in the priority lists.
on the selected pin). Example 12-1 shows how to These inputs are active when the I/O pin is set for
initialize PORTA. Analog mode using the ANSELx registers. Digital
output functions may control the pin when it is in Analog
Reading the PORTA register (Register 12-2) reads the
mode with the priority shown in the priority list.
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the TABLE 12-2: PORTA OUTPUT PRIORITY
port pins are read, this value is modified and then
Pin Name Function Priority(1)
written to the PORT data latch (LATA).
RA0 VCAP
12.3.2 DIRECTION CONTROL SEG12 (LCD)
The TRISA register (Register 12-3) controls the SRNQ (SR Latch)
PORTA pin output drivers, even when they are being C2OUT (Comparator)
used as analog inputs. The user should ensure the bits RA0
in the TRISA register are maintained set when using RA1 SEG7 (LCD)
them as analog inputs. I/O pins configured as analog RA1
input always read ‘0’. RA2 COM2 (LCD)
AN2 (DAC)
12.3.3 ANALOG CONTROL RA2
The ANSELA register (Register 12-5) is used to RA3 COM3 (LCD)
configure the Input mode of an I/O pin to analog. SEG15
Setting the appropriate ANSELA bit high will cause all RA3
digital reads on the pin to be read as ‘0’ and allow
RA4 SEG4 (LCD)
analog functions on the pin to operate correctly.
SRQ (SR Latch)
The state of the ANSELA bits has no effect on digital C1OUT (Comparator)
output functions. A pin with TRIS clear and ANSEL set CCP5
will still operate as a digital output, but the Input mode RA4
will be analog. This can cause unexpected behavior
RA5 VCAP (enabled by Config. Word)
when executing read-modify-write instructions on the
SEG5 (LCD)
affected port.
SRNQ (SR Latch)
Note: The ANSELA bits default to the Analog C2OUT (Comparator)
mode after Reset. To use any pins as RA5
digital general purpose or peripheral RA6 VCAP (enabled by Config. Word)
inputs, the corresponding ANSEL bits OSC2 (enabled by Config. Word)
must be initialized to ‘0’ by user software. CLKOUT (enabled by Config. Word)
SEG1 (LCD)
RA6
RA7 OSC1/CLKIN (enabled by Config. Word)
SEG2 (LCD)
RA7
Note 1: Priority listed from highest to lowest.

PIC16(L)F1933
REGISTER 12-2: PORTA: PORTA REGISTER

RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
bit 7 bit 0
Legend:
bit 7-0 RA<7:0>: PORTA I/O Value bits(1)

1 = Port pin is > VIH
0 = Port pin is < VIL
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
REGISTER 12-3: TRISA: PORTA TRI-STATE REGISTER

TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
bit 7 bit 0
Legend:
bit 7-0 TRISA<7:0>: PORTA Tri-State Control bits

1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
REGISTER 12-4: LATA: PORTA DATA LATCH REGISTER

LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0
bit 7 bit 0
Legend:
bit 7-0 LATA<7:0>: PORTA Output Latch Value bits(1)
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.

PIC16(L)F1933
REGISTER 12-5: ANSELA: PORTA ANALOG SELECT REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
— — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0
bit 7 bit 0
Legend:

bit 5-0 ANSA<5:0>: Analog Select between Analog or Digital Function on pins RA<5:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.

PIC16(L)F1933
TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Register
on Page
ADCON0 — CHS<4:0> GO/DONE ADON 143
ADCON1 ADFM ADCS<2:0> — ADNREF ADPREF<1:0> 144
ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 117
APFCON — CCP3SEL T1GSEL P2BSEL SRNQSEL C2OUTSEL SSSEL CCP2SEL 114
CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 163
CM1CON1 C1NTP C1INTN C1PCH<1:0> — — C1NCH<1:0> 164
CPSCON0 CPSON CPSRM — — CPSRNG<1:0> CPSOUT T0XCS 311
CPSCON1 — — — — — CPSCH<2:0> 312
DACCON0 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS 156
LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 116
LCDCON LCDEN SLPEN WERR — CS<1:0> LMUX<1:0> 315
LCDSE0 SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 319
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 173
PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 116
SRCON0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR 169
SSPCON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 268
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 116
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
TABLE 12-4: SUMMARY OF CONFIGURATION WORD WITH PORTA

Register
on Page

CONFIG1 46
CONFIG2 48
7:0 — — VCAPEN<1:0>(1) — — WRT<1:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.

PIC16(L)F1933
12.4 PORTB Registers will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
12.4.1 DATA REGISTER affected port.
PORTB is an 8-bit wide, bidirectional port. The Note: The ANSELB bits default to the Analog
corresponding data direction register is TRISB mode after Reset. To use any pins as
(Register 12-7). Setting a TRISB bit (= 1) will make the digital general purpose or peripheral
corresponding PORTB pin an input (i.e., put the inputs, the corresponding ANSEL bits
corresponding output driver in a High-Impedance mode). must be initialized to ‘0’ by user software.
Clearing a TRISB bit (= 0) will make the corresponding
PORTB pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 12-1 shows how to initialize an I/O port.
Reading the PORTB register (Register 12-6) reads the
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATB).
12.4.2 DIRECTION CONTROL

The TRISB register (Register 12-7) controls the PORTB
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISB register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.
12.4.3 WEAK PULL-UPS

Each of the PORTB pins has an individually configurable
internal weak pull-up. Control bits WPUB<7:0> enable or
disable each pull-up (see Register 12-10). Each weak
pull-up is automatically turned off when the port pin is
configured as an output. All pull-ups are disabled on a
Power-on Reset by the WPUEN bit of the OPTION_REG
register.
12.4.4 INTERRUPT-ON-CHANGE
All of the PORTB pins are individually configurable as an
interrupt-on-change pin. Control bits IOCB<7:0> enable
or disable the interrupt function for each pin. The
interrupt-on-change feature is disabled on a Power-on
Reset. Reference Section 13.0
“Interrupt-on-Change” for more information.
12.4.5 ANALOG CONTROL

The ANSELB register (Register 12-9) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELB bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELB bits has no effect on digital
output functions. A pin with TRIS clear and ANSELB set
will still operate as a digital output, but the Input mode

PIC16(L)F1933
12.4.6 PORTB FUNCTIONS AND OUTPUT
PRIORITIES
Each PORTB pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in Table 12-5.
control goes to the peripheral with the highest priority.
Analog input and some digital input functions are not
included in the list below. These input functions can
remain active when the pin is configured as an output.
Certain digital input functions override other port
functions and are included in the priority list.
TABLE 12-5: PORTB OUTPUT PRIORITY

RB0 SEG0 (LCD)
CCP4
RB0
RB1 P1C (ECCP1)
RB1
RB2 P1B (ECCP1)
RB2
RB3 CCP2/P2A
RB3
RB4 COM0
P1D
RB4
RB5 COM1
P2B
CCP3/P3A
RB5
RB6 ICSPCLK (Programming)
ICDCLK (enabled by Config. Word)
SEG14 (LCD)
RB6
RB7 ICSPDAT (Programming)
ICDDAT (enabled by Config. Word)
SEG13 (LCD)
RB7

PIC16(L)F1933
REGISTER 12-6: PORTB: PORTB REGISTER

RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
bit 7 bit 0
Legend:
bit 7-0 RB<7:0>: PORTB I/O Pin bits

REGISTER 12-7: TRISB: PORTB TRI-STATE REGISTER

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
bit 7 bit 0
Legend:
bit 7-0 TRISB<7:0>: PORTB Tri-State Control bits

1 = PORTB pin configured as an input (tri-stated)
0 = PORTB pin configured as an output
REGISTER 12-8: LATB: PORTB DATA LATCH REGISTER

LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0
bit 7 bit 0
Legend:
bit 7-0 LATB<7:0>: PORTB Output Latch Value bits(1)
Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.

PIC16(L)F1933
REGISTER 12-9: ANSELB: PORTB ANALOG SELECT REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
— — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0
bit 7 bit 0
Legend:

bit 5-0 ANSB<5:0>: Analog Select between Analog or Digital Function on Pins RB<5:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
REGISTER 12-10: WPUB: WEAK PULL-UP PORTB REGISTER

WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0
bit 7 bit 0
Legend:
bit 7-0 WPUB<7:0>: Weak Pull-up Register bits

1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is configured as an output.

PIC16(L)F1933
TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Register
on Page

ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 122
CCPxCON PxM<1:0> DCxB<1:0> CCPxM<3:0> 214
CPSCON1 — — — — — CPSCH<2:0> 312
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 121
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 121
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 184
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 121
WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 122
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.

PIC16(L)F1933
12.5 PORTC Registers 12.5.3 PORTC FUNCTIONS AND OUTPUT
PRIORITIES
Each PORTC pin is multiplexed with other functions. The
PORTC is a 8-bit wide, bidirectional port. The pins, their combined functions and their output priorities
corresponding data direction register is TRISC are shown in Table 12-7.
(Register 12-12). Setting a TRISC bit (= 1) will make the
corresponding PORTC pin an input (i.e., put the
control goes to the peripheral with the lowest number in
corresponding output driver in a High-Impedance mode).
the following lists.
Clearing a TRISC bit (= 0) will make the corresponding
PORTC pin an output (i.e., enable the output driver and Analog input and some digital input functions are not
put the contents of the output latch on the selected pin). included in the list below. These input functions can
Example 12-1 shows how to initialize an I/O port. remain active when the pin is configured as an output.
Certain digital input functions override other port
Reading the PORTC register (Register 12-11) reads the
functions and are included in the priority list.
operations. Therefore, a write to a port implies that the TABLE 12-7: PORTC OUTPUT PRIORITY
port pins are read, this value is modified and then written
to the PORT data latch (LATC).
RC0 T1OSO (Timer1 Oscillator)
12.5.2 DIRECTION CONTROL CCP2/P2B
The TRISC register (Register 12-12) controls the RC0
PORTC pin output drivers, even when they are being RC1 T1OSI (Timer1 Oscillator)
used as analog inputs. The user should ensure the bits in CCP2/P2A
the TRISC register are maintained set when using them RC1
as analog inputs. I/O pins configured as analog input RC2 SEG3 (LCD)
always read ‘0’. CCP1/P1A
RC2
RC3 SEG6 (LCD)
SCL (MSSP)
SCK (MSSP)
RC3
RC4 SEG11 (LCD)
SDA (MSSP)
RC4
RC5 SEG10 (LCD)
SDO (MSSP)
RC5
RC6 ISEG9 (LCD)
TX (EUSART)
CK (EUSART)
CCP3/P3A
RC6
RC7 SEG8 (LCD)
DT (EUSART)
CCP3/P3B
RC7

PIC16(L)F1933
REGISTER 12-11: PORTC: PORTC REGISTER

RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
bit 7 bit 0
Legend:
bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bits

REGISTER 12-12: TRISC: PORTC TRI-STATE REGISTER

TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
bit 7 bit 0
Legend:
bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits

1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output
REGISTER 12-13: LATC: PORTC DATA LATCH REGISTER

LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0
bit 7 bit 0
Legend:
bit 7-0 LATC<7:0>: PORTC Output Latch Value bits(1)
Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
return of actual I/O pin values.

PIC16(L)F1933
TABLE 12-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Register
on Page

LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 125
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 125
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 286
SSPSTAT SMP CKE D/A P S R/W UA BF 267
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 285
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 125
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.

PIC16(L)F1933
12.6 PORTE Registers 12.6.2 PORTE FUNCTIONS AND OUTPUT
PRIORITIES
No output priorities, RE3 is an input only pin.
RE3 is input only, and also functions as MCLR. The
MCLR feature can be disabled via a configuration fuse.
RE3 also supplies the programming voltage. The TRIS bit
for RE3 (TRISE3) always reads ‘1’.
REGISTER 12-14: PORTE: PORTE REGISTER

U-0 U-0 U-0 U-0 R-x/u U-0 U-0 U-0
— — — — RE3 — — —
bit 7 bit 0
Legend:

bit 3 RE3: PORTE Input Pin bit
REGISTER 12-15: TRISE: PORTE TRI-STATE REGISTER

U-0 U-0 U-0 U-0 U-1(1) U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets


PIC16(L)F1933
REGISTER 12-16: WPUE: WEAK PULL-UP PORTE REGISTER

U-0 U-0 U-0 U-0 R/W-1/1 U-0 U-0 U-0
— — — — WPUE3 — — —
bit 7 bit 0
Legend:

bit 3 WPUE3: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is configured as an output.
TABLE 12-9: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Register
on Page

PORTE — — — — RE3 — — — 127
TRISE — — — — —(3) — — — 127
WPUE — — — — WPUE3 — — — 128
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTE.

PIC16(L)F193X
13.0 INTERRUPT-ON-CHANGE 13.3 Interrupt Flags
The PORTB pins can be configured to operate as The IOCBFx bits located in the IOCBF register are
Interrupt-On-Change (IOC) pins. An interrupt can be status flags that correspond to the Interrupt-on-change
generated by detecting a signal that has either a rising pins of PORTB. If an expected edge is detected on an
edge or a falling edge. Any individual PORT IOC pin, or appropriately enabled pin, then the status flag for that pin
combination of PORT IOC pins, can be configured to will be set, and an interrupt will be generated if the IOCIE
generate an interrupt. The interrupt-on-change module bit is set. The IOCIF bit of the INTCON register reflects
has the following features: the status of all IOCBFx bits.
• Interrupt-on-Change enable (Master Switch)
• Individual pin configuration
13.4 Clearing Interrupt Flags
• Rising and falling edge detection The individual status flags, (IOCBFx bits), can be
• Individual pin interrupt flags cleared by resetting them to zero. If another edge is
detected during this clearing operation, the associated
Figure 13-1 is a block diagram of the IOC module.
status flag will be set at the end of the sequence,
regardless of the value actually being written.
13.1 Enabling the Module
In order to ensure that no detected edge is lost while
To allow individual PORTB pins to generate an interrupt, clearing flags, only AND operations masking out known
the IOCIE bit of the INTCON register must be set. If the changed bits should be performed. The following
IOCIE bit is disabled, the edge detection on the pin will sequence is an example of what should be performed.
still occur, but an interrupt will not be generated.
EXAMPLE 13-1: CLEARING INTERRUPT
13.2 Individual Pin Configuration FLAGS (PORTA
EXAMPLE)
For each PORTB pin, a rising edge detector and a falling
edge detector are present. To enable a pin to detect a MOVLW 0xff
rising edge, the associated IOCBPx bit of the IOCBP XORWF IOCBF, W
register is set. To enable a pin to detect a falling edge, ANDWF IOCBF, F
the associated IOCBNx bit of the IOCBN register is set.
A pin can be configured to detect rising and falling 13.5 Operation in Sleep
edges simultaneously by setting both the IOCBPx bit
and the IOCBNx bit of the IOCBP and IOCBN registers, The interrupt-on-change interrupt sequence will wake
respectively. the device from Sleep mode, if the IOCIE bit is set.
If an edge is detected while in Sleep mode, the IOCBF
register will be updated prior to the first instruction
executed out of Sleep.

PIC16(L)F193X
FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM
IOCBNx D Q4Q1
Q
CK edge
detect
R
RBx
data bus = S to data bus

IOCBPx D Q 0 or 1 D Q IOCBFx
CK write IOCBFx CK
IOCIE
R
Q2
from all other
IOCBFx individual IOC interrupt
pin detectors to CPU core
Q1 Q1 Q1
Q2 Q2 Q2
Q3 Q3 Q3
Q4 Q4 Q4 Q4
Q4Q1 Q4Q1 Q4Q1 Q4Q1

PIC16(L)F193X
13.6 Register Definitions: Interrupt-on-Change Control
REGISTER 13-1: IOCBP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER

IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0
bit 7 bit 0
Legend:
bit 7-0 IOCBP<7:0>: Interrupt-on-Change Positive Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCBFx bit and IOCIF flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
REGISTER 13-2: IOCBN: INTERRUPT-ON-CHANGE NEGATIVE EDGE REGISTER

IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0
bit 7 bit 0
Legend:
bit 7-0 IOCBN<7:0>: Interrupt-on-Change Negative Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCBFx bit and IOCIF flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
REGISTER 13-3: IOCBF: INTERRUPT-ON-CHANGE FLAG REGISTER

R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware
bit 7-0 IOCBF<7:0>: Interrupt-on-Change Flag bits

1 = An enabled change was detected on the associated pin.
Set when IOCBPx = 1 and a rising edge was detected on RBx, or when IOCBNx = 1 and a falling
edge was detected on RBx.
0 = No change was detected, or the user cleared the detected change.

PIC16(L)F193X
TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
Register
on Page
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change.

PIC16(L)F1933
14.0 FIXED VOLTAGE REFERENCE
(FVR)
The Fixed Voltage Reference, or FVR, is a stable
voltage reference, independent of VDD, with 1.024V,
2.048V or 4.096V selectable output levels. The output
of the FVR can be configured to supply a reference
voltage to the following:
• ADC input channel
• ADC positive reference
• Comparator positive input
• Digital-to-Analog Converter (DAC)
• Capacitive Sensing (CPS) module
• LCD bias generator
The FVR can be enabled by setting the FVREN bit of
the FVRCON register.
14.1 Independent Gain Amplifiers

The output of the FVR supplied to the ADC,
Comparators, DAC and CPS is routed through two
independent programmable gain amplifiers. Each
amplifier can be programmed for a gain of 1x, 2x or 4x,
to produce the three possible voltage levels.
The ADFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
for the reference supplied to the ADC module. Refer-
ence Section 15.0 “Analog-to-Digital Converter
(ADC) Module” for additional information.
The CDAFVR<1:0> bits of the FVRCON register are used
to enable and configure the gain amplifier settings for the
reference supplied to the DAC, CPS and Comparator
module. Reference Section 17.0 “Digital-to-Analog
Converter (DAC) Module”, Section 18.0 “Comparator
Module” and Section 26.0 “Capacitive Sensing (CPS)
Module” for additional information.
14.2 FVR Stabilization Period

When the Fixed Voltage Reference module is enabled, it
requires time for the reference and amplifier circuits to
stabilize. Once the circuits stabilize and are ready for use,
the FVRRDY bit of the FVRCON register will be set. See
in Section 30.0 “Electrical Specifications” for the
minimum delay requirement.

PIC16(L)F1933
FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM
ADFVR<1:0>
2
X1
X2 FVR BUFFER1
X4 (To ADC Module)
CDAFVR<1:0> 2
X1
X2 FVR BUFFER2
X4 (To Comparators, DAC)
FVR VREF
1.024V Fixed (To LCD Bias Generator)
Reference
+
FVREN
_ FVRRDY
Any peripheral requiring the

Fixed Reference
(See Table 14-1)

PIC16(L)F1933
14.3 Register Definitions: FVR Control
REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER

R/W-0/0 R-q/q R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
FVREN FVRRDY(1) TSEN TSRNG CDAFVR<1:0> ADFVR<1:0>
bit 7 bit 0
Legend:
bit 7 FVREN: Fixed Voltage Reference Enable bit

1 = Fixed Voltage Reference is enabled
0 = Fixed Voltage Reference is disabled
bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1)
1 = Fixed Voltage Reference output is ready for use
0 = Fixed Voltage Reference output is not ready or not enabled
bit 5 TSEN: Temperature Indicator Enable bit(3)
1 = Temperature Indicator is enabled
0 = Temperature Indicator is disabled
bit 4 TSRNG: Temperature Indicator Range Selection bit(3)
1 = VOUT = VDD - 4VT (High Range)
0 = VOUT = VDD - 2VT (Low Range)
bit 3-2 CDAFVR<1:0>: Comparator and DAC Fixed Voltage Reference Selection bit
11 = Comparator and DAC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2)
10 = Comparator and DAC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)
01 = Comparator and DAC Fixed Voltage Reference Peripheral output is 1x (1.024V)
00 = Comparator and DAC Fixed Voltage Reference Peripheral output is off
bit 1-0 ADFVR<1:0>: ADC Fixed Voltage Reference Selection bit
11 = ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2)
10 = ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)
01 = ADC Fixed Voltage Reference Peripheral output is 1x (1.024V)
00 = ADC Fixed Voltage Reference Peripheral output is off
Note 1: FVRRDY is always ‘1’ on devices with PIC16F1933 only.

2: Fixed Voltage Reference output cannot exceed VDD.
3: See Section 16.0 “Temperature Indicator Module” for additional information.
TABLE 14-1: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE

Register
on page
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 135
Legend: Shaded cells are not used with Fixed Voltage Reference.

PIC16(L)F1933
NOTES:

PIC16(L)F1933
15.0 ANALOG-TO-DIGITAL The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
CONVERTER (ADC) MODULE
device from Sleep.
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESH:ADRESL register pair).
Figure 15-1 shows the block diagram of the ADC.
The ADC voltage reference is software selectable to be
either internally generated or externally supplied.
FIGURE 15-1: ADC BLOCK DIAGRAM
VREF- ADNREF = 1
ADNREF = 0
VSS
VDD
ADPREF = 00
ADPREF = 11
VREF+ ADPREF = 10
AN0 00000
AN1 00001
AN2 00010
AN3 00011
AN4 00100
Reserved 00101
Reserved 00110
ref+ ref-
Reserved 00111
AN8 01000 ADC
AN9 01001 10
GO/DONE
AN10 01010
AN11 01011 0 = Left Justify
ADFM
1 = Right Justify
AN12 01100
ADON(1) 16
AN13 01101
VSS ADRESH ADRESL
Temp Indicator 11101

DAC_output 11110
FVR Buffer1 11111
CHS<4:0>
Note 1: When ADON = 0, all multiplexer inputs are disconnected.

PIC16(L)F1933
15.1 ADC Configuration 15.1.4 CONVERSION CLOCK
When configuring and using the ADC the following The source of the conversion clock is software selectable
functions must be considered: via the ADCS bits of the ADCON1 register. There are
seven possible clock options:
• Port configuration
• FOSC/2
• Channel selection
• FOSC/4
• ADC voltage reference selection
• FOSC/8
• ADC conversion clock source
• FOSC/16
• Interrupt control
• FOSC/32
• Result formatting
• FOSC/64
15.1.1 PORT CONFIGURATION • FRC (dedicated internal oscillator)
The ADC can be used to convert both analog and The time to complete one bit conversion is defined as
digital signals. When converting analog signals, the I/O TAD. One full 10-bit conversion requires 11.5 TAD
pin should be configured for analog by setting the periods as shown in Figure 15-2.
associated TRIS and ANSEL bits. Refer to For correct conversion, the appropriate TAD specification
Section 12.0 “I/O Ports” for more information. must be met. Refer to the A/D conversion requirements
Note: Analog voltages on any pin that is defined in Section 30.0 “Electrical Specifications” for more
as a digital input may cause the input information. Table 15-1 gives examples of appropriate
buffer to conduct excess current. ADC clock selections.
Note: Unless using the FRC, any changes in the
15.1.2 CHANNEL SELECTION system clock frequency will change the
There are 14 channel selections available: ADC clock frequency, which may
adversely affect the ADC result.
• AN<13:8, 4:0> pins
• Temperature Indicator
• DAC_output
• FVR (Fixed Voltage Reference) Output
Refer to Section 16.0 “Temperature Indicator
Module”, Section 17.0 “Digital-to-Analog Converter
(DAC) Module” and Section 14.0 “Fixed Voltage
Reference (FVR)” for more information on these
channel selections.
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 15.2
“ADC Operation” for more information.
15.1.3 ADC VOLTAGE REFERENCE

The ADPREF bits of the ADCON1 register provides
control of the positive voltage reference. The positive
voltage reference can be:
• VREF+ pin
• VDD
The ADNREF bits of the ADCON1 register provides
control of the negative voltage reference. The negative
voltage reference can be:
• VREF- pin
• VSS
See Section 14.0 “Fixed Voltage Reference (FVR)”
for more details on the fixed voltage reference.

PIC16(L)F1933
TABLE 15-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
Device Frequency (FOSC)
ADC Clock Period (TAD)
Device Frequency (FOSC)
ADC
ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz
Clock Source
Fosc/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s
(2) (2) (2) (2)
Fosc/4 100 125 ns 200 ns 250 ns 500 ns 1.0 s 4.0 s
Fosc/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) 1.0 s 2.0 s 8.0 s(3)
Fosc/16 101 800 ns 800 ns 1.0 s 2.0 s 4.0 s 16.0 s(3)
Fosc/32 010 1.0 s 1.6 s 2.0 s 4.0 s 8.0 s(3) 32.0 s(3)
Fosc/64 110 2.0 s 3.2 s 4.0 s 8.0 s(3) 16.0 s(3) 64.0 s(3)
(1,4) (1,4) (1,4) (1,4) (1,4)
FRC x11 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 1.6 s for VDD.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the
system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the
device in Sleep mode.
FIGURE 15-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.

PIC16(L)F1933
15.1.5 INTERRUPTS 15.1.6 RESULT FORMATTING
The ADC module allows for the ability to generate an The 10-bit A/D conversion result can be supplied in two
interrupt upon completion of an Analog-to-Digital formats, left justified or right justified. The ADFM bit of
conversion. The ADC Interrupt Flag is the ADIF bit in the ADCON1 register controls the output format.
the PIR1 register. The ADC Interrupt Enable is the Figure 15-3 shows the two output formats.
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
Note 1: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the FRC oscillator is selected.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code execu-
tion, the GIE and PEIE bits of the INTCON register
must be disabled. If the GIE and PEIE bits of the
INTCON register are enabled, execution will switch to
the Interrupt Service Routine.
FIGURE 15-3: 10-BIT A/D CONVERSION RESULT FORMAT
ADRESH ADRESL
(ADFM = 0) MSB LSB
bit 7 bit 0 bit 7 bit 0
10-bit A/D Result Unimplemented: Read as ‘0’
(ADFM = 1) MSB LSB

bit 7 bit 0 bit 7 bit 0
Unimplemented: Read as ‘0’ 10-bit A/D Result

PIC16(L)F1933
15.2 ADC Operation 15.2.4 ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
15.2.1 STARTING A CONVERSION requires the ADC clock source to be set to the FRC
To enable the ADC module, the ADON bit of the option. When the FRC clock source is selected, the
ADCON0 register must be set to a ‘1’. Setting the GO/ ADC waits one additional instruction before starting the
DONE bit of the ADCON0 register to a ‘1’ will start the conversion. This allows the SLEEP instruction to be
Analog-to-Digital conversion. executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
Note: The GO/DONE bit should not be set in the
will wake-up from Sleep when the conversion
same instruction that turns on the ADC.
completes. If the ADC interrupt is disabled, the ADC
Refer to Section 15.2.6 “A/D Conver-
module is turned off after the conversion completes,
sion Procedure”.
although the ADON bit remains set.
15.2.2 COMPLETION OF A CONVERSION When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conversion
When the conversion is complete, the ADC module will: to be aborted and the ADC module is turned off,
• Clear the GO/DONE bit although the ADON bit remains set.
• Set the ADIF Interrupt Flag bit
15.2.5 SPECIAL EVENT TRIGGER
• Update the ADRESH and ADRESL registers with
new conversion result The Special Event Trigger of the CCPx/ECCPX module
allows periodic ADC measurements without software
15.2.3 TERMINATING A CONVERSION intervention. When this trigger occurs, the GO/DONE
If a conversion must be terminated before completion, bit is set by hardware and the Timer1 counter resets to
the GO/DONE bit can be cleared in software. The zero.
ADRESH and ADRESL registers will be updated with TABLE 15-2: SPECIAL EVENT TRIGGER
the partially complete Analog-to-Digital conversion Device CCPx/ECCPx
sample. Incomplete bits will match the last bit
converted. PIC16(L)F1933 CCP5
Note: A device Reset forces all registers to their Using the Special Event Trigger does not assure proper
Reset state. Thus, the ADC module is ADC timing. It is the user’s responsibility to ensure that
turned off and any pending conversion is the ADC timing requirements are met.
terminated. Refer to Section 23.0 “Capture/Compare/PWM
Modules” for more information.

PIC16(L)F1933
15.2.6 A/D CONVERSION PROCEDURE EXAMPLE 15-1: A/D CONVERSION
This is an example procedure for using the ADC to ;This code block configures the ADC
perform an Analog-to-Digital conversion: ;for polling, Vdd and Vss references, Frc
;clock and AN0 input.
1. Configure Port:
;
• Disable pin output driver (Refer to the TRIS ;Conversion start & polling for completion
register) ; are included.
• Configure pin as analog (Refer to the ANSEL ;
register) BANKSEL ADCON1 ;
MOVLW B’11110000’ ;Right justify, Frc
2. Configure the ADC module: ;clock
• Select ADC conversion clock MOVWF ADCON1 ;Vdd and Vss Vref
• Configure voltage reference BANKSEL TRISA ;
BSF TRISA,0 ;Set RA0 to input
• Select ADC input channel
BANKSEL ANSEL ;
• Turn on ADC module BSF ANSEL,0 ;Set RA0 to analog
3. Configure ADC interrupt (optional): BANKSEL ADCON0 ;
• Clear ADC interrupt flag MOVLW B’00000001’ ;Select channel AN0
MOVWF ADCON0 ;Turn ADC On
• Enable ADC interrupt CALL SampleTime ;Acquisiton delay
• Enable peripheral interrupt BSF ADCON0,ADGO ;Start conversion
• Enable global interrupt(1) BTFSC ADCON0,ADGO ;Is conversion done?
GOTO $-1 ;No, test again
4. Wait the required acquisition time(2). BANKSEL ADRESH ;
5. Start conversion by setting the GO/DONE bit. MOVF ADRESH,W ;Read upper 2 bits
6. Wait for ADC conversion to complete by one of MOVWF RESULTHI ;store in GPR space
the following: BANKSEL ADRESL ;
MOVF ADRESL,W ;Read lower 8 bits
• Polling the GO/DONE bit MOVWF RESULTLO ;Store in GPR space
• Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result.
8. Clear the ADC interrupt flag (required if interrupt
is enabled).
Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer to Section 15.4 “A/D Acquisition
Requirements”.

PIC16(L)F1933
15.3 Register Definitions: ADC Control
REGISTER 15-1: ADCON0: A/D CONTROL REGISTER 0

— CHS<4:0> GO/DONE ADON
bit 7 bit 0
Legend:

bit 6-2 CHS<4:0>: Analog Channel Select bits
11111 = FVR (Fixed Voltage Reference) Buffer 1 Output(2)
11110 = DAC_output(1)
11101 = Temperature Indicator(3)
11100 = Reserved. No channel connected.
•
•
•
01101 = AN13
01100 = AN12
01011 = AN11
01010 = AN10
01001 = AN9
01000 = AN8
00100 = AN4
00011 = AN3
00010 = AN2
00001 = AN1
00000 = AN0
bit 1 GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0 ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
Note 1: See Section 17.0 “Digital-to-Analog Converter (DAC) Module” for more information.
2: See Section 14.0 “Fixed Voltage Reference (FVR)” for more information.
3: See Section 16.0 “Temperature Indicator Module” for more information.

PIC16(L)F1933
REGISTER 15-2: ADCON1: A/D CONTROL REGISTER 1
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
ADFM ADCS<2:0> — ADNREF ADPREF<1:0>
bit 7 bit 0
Legend:
bit 7 ADFM: A/D Result Format Select bit

1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is
loaded.
0 = Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is
loaded.
bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits
111 = FRC (clock supplied from a dedicated RC oscillator)
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC (clock supplied from a dedicated RC oscillator)
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2
bit 2 ADNREF: A/D Negative Voltage Reference Configuration bit
1 = VREF- is connected to external VREF- pin(1)
0 = VREF- is connected to VSS
bit 1-0 ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits
11 = VREF+ is connected to internal Fixed Voltage Reference (FVR) module(1)
10 = VREF+ is connected to external VREF+ pin(1)
01 = Reserved
00 = VREF+ is connected to VDD
Note 1: When selecting the FVR or the VREF+ pin as the source of the positive reference, be aware that a
minimum voltage specification exists. See Section 30.0 “Electrical Specifications” for details.

PIC16(L)F1933
REGISTER 15-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0

ADRES<9:2>
bit 7 bit 0
Legend:
bit 7-0 ADRES<9:2>: ADC Result Register bits

Upper eight bits of 10-bit conversion result
REGISTER 15-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0

ADRES<1:0> — — — — — —
bit 7 bit 0
Legend:

Lower two bits of 10-bit conversion result
bit 5-0 Reserved: Do not use.

PIC16(L)F1933
REGISTER 15-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1

— — — — — — ADRES<9:8>
bit 7 bit 0
Legend:
bit 7-2 Reserved: Do not use.

Upper two bits of 10-bit conversion result
REGISTER 15-6: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1

ADRES<7:0>
bit 7 bit 0
Legend:

Lower eight bits of 10-bit conversion result

PIC16(L)F1933
15.4 A/D Acquisition Requirements source impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
For the ADC to meet its specified accuracy, the charge selected (or changed), an A/D acquisition must be
holding capacitor (CHOLD) must be allowed to fully done before the conversion can be started. To calculate
charge to the input channel voltage level. The Analog the minimum acquisition time, Equation 15-1 may be
Input model is shown in Figure 15-4. The source used. This equation assumes that 1/2 LSb error is used
impedance (RS) and the internal sampling switch (RSS) (1,024 steps for the ADC). The 1/2 LSb error is the
impedance directly affect the time required to charge maximum error allowed for the ADC to meet its
the capacitor CHOLD. The sampling switch (RSS) specified resolution.
impedance varies over the device voltage (VDD), refer
to Figure 15-4. The maximum recommended
impedance for analog sources is 10 k. As the
EQUATION 15-1: ACQUISITION TIME EXAMPLE
Assumptions: Temperature = 50°C and external impedance of 10k  5.0V V DD
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2µs + T C +   Temperature - 25°C   0.05µs/°C  
The value for TC can be approximated with the following equations:
1
V AP P LI ED  1 – -------------------------- = V CHOLD ;[1] VCHOLD charged to within 1/2 lsb
 n+1 
2 –1
–TC
 ----------
RC
V AP P LI ED  1 – e  = V CHOLD ;[2] VCHOLD charge response to VAPPLIED
 
– Tc
 ---------
1
V AP P LI ED  1 – e  = V A PP LIE D  1 – -------------------------- ;combining [1] and [2]
RC
  n+1 
2 –1
Note: Where n = number of bits of the ADC.
Solving for TC:
T C = – C HOLD  R IC + R SS + R S  ln(1/2047)
= – 13.5pF  1k  + 7k  + 10k   ln(0.0004885)
= 1.20 µs
Therefore:
T A CQ = 5µs + 1.20µs +   50°C- 25°C   0.05 µs/°C  
= 7.45µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.

PIC16(L)F1933
FIGURE 15-4: ANALOG INPUT MODEL
VDD
Analog Sampling
Input Switch
VT  0.6V
Rs pin RIC  1k SS Rss
VA CPIN I LEAKAGE(1)
VT  0.6V CHOLD = 10 pF
5 pF
Ref-
6V
5V RSS
Legend: CHOLD = Sample/Hold Capacitance VDD 4V
3V
CPIN = Input Capacitance 2V
I LEAKAGE = Leakage current at the pin due to
various junctions
5 6 7 8 9 10 11
RIC = Interconnect Resistance
Sampling Switch
RSS = Resistance of Sampling Switch (k)
SS = Sampling Switch
VT = Threshold Voltage
Note 1: Refer to in Section 30.0 “Electrical Specifications”.
FIGURE 15-5: ADC TRANSFER FUNCTION
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
ADC Output Code
3FBh
03h
02h
01h
00h
Analog Input Voltage
0.5 LSB 1.5 LSB
Ref- Zero-Scale
Transition Full-Scale
Transition Ref+

PIC16(L)F1933
TABLE 15-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page
ADCON1 ADFM ADCS<2:0> — ADNREF ADPREF<1:0> 144
ADRESH A/D Result Register High 145
ADRESL A/D Result Register Low 145
CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 214
DACCON1 — — — DACR<4:0> 156
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not
used for ADC module.

PIC16(L)F1933
NOTES:

PIC16(L)F1933
16.0 TEMPERATURE INDICATOR FIGURE 16-1: TEMPERATURE CIRCUIT
MODULE DIAGRAM
This family of devices is equipped with a temperature

circuit designed to measure the operating temperature VDD
of the silicon die. The circuit’s range of operating
TSEN
temperature falls between -40°C and +85°C. The
output is a voltage that is proportional to the device
temperature. The output of the temperature indicator is
internally connected to the device ADC. TSRNG
The circuit may be used as a temperature threshold

detector or a more accurate temperature indicator,
depending on the level of calibration performed. A one-
point calibration allows the circuit to indicate a
VOUT
temperature closely surrounding that point. A two-point To ADC
calibration allows the circuit to sense the entire range
of temperature more accurately. Reference Application
Note AN1333, “Use and Calibration of the Internal
Temperature Indicator” (DS01333) for more details
regarding the calibration process.
16.1 Circuit Operation 16.2 Minimum Operating VDD

Figure 16-1 shows a simplified block diagram of the When the temperature circuit is operated in low range,
temperature circuit. The proportional voltage output is the device may be operated at any operating voltage
achieved by measuring the forward voltage drop across that is within specifications.
multiple silicon junctions.
When the temperature circuit is operated in high range,
Equation 16-1 describes the output characteristics of the device operating voltage, VDD, must be high
the temperature indicator. enough to ensure that the temperature circuit is
correctly biased.
EQUATION 16-1: VOUT RANGES Table 16-1 shows the recommended minimum VDD vs.
range setting.
High Range: VOUT = VDD - 4VT
TABLE 16-1: RECOMMENDED VDD VS.
Low Range: VOUT = VDD - 2VT RANGE
Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0
The temperature sense circuit is integrated with the 3.6V 1.8V
Fixed Voltage Reference (FVR) module. See
Section 14.0 “Fixed Voltage Reference (FVR)” for 16.3 Temperature Output
more information.
The circuit is enabled by setting the TSEN bit of the The output of the circuit is measured using the internal
FVRCON register. When disabled, the circuit draws no Analog-to-Digital Converter. A channel is reserved for
current. the temperature circuit output. Refer to Section 15.0
“Analog-to-Digital Converter (ADC) Module” for
The circuit operates in either high or low range. The high detailed information.
range, selected by setting the TSRNG bit of the
FVRCON register, provides a wider output voltage. This
16.4 ADC Acquisition Time
provides more resolution over the temperature range,
but may be less consistent from part to part. This range To ensure accurate temperature measurements, the
requires a higher bias voltage to operate and thus, a user must wait at least 200 s after the ADC input
higher VDD is needed. multiplexer is connected to the temperature indicator
The low range is selected by clearing the TSRNG bit of output before the conversion is performed. In addition,
the FVRCON register. The low range generates a lower the user must wait 200 s between sequential
voltage drop and thus, a lower bias voltage is needed to conversions of the temperature indicator output.
operate the circuit. The low range is provided for low
voltage operation.

PIC16(L)F1933
TABLE 16-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR
Register
on page
Legend: Shaded cells are unused by the temperature indicator module.

PIC16(L)F1933
17.0 DIGITAL-TO-ANALOG 17.1 Output Voltage Selection
CONVERTER (DAC) MODULE The DAC has 32 voltage level ranges. The 32 levels
The Digital-to-Analog Converter supplies a variable are set with the DACR<4:0> bits of the DACCON1
voltage reference, ratiometric with the input source, register.
with 32 selectable output levels. The DAC output voltage is determined by the following
The input of the DAC can be connected to: equations:
• External VREF pins

• VDD supply voltage
• FVR (Fixed Voltage Reference)
The output of the DAC can be configured to supply a
reference voltage to the following:
• Comparator positive input
• ADC input channel
• DACOUT pin
• Capacitive Sensing module (CPS)
The Digital-to-Analog Converter (DAC) can be enabled
by setting the DACEN bit of the DACCON0 register.
EQUATION 17-1: DAC OUTPUT VOLTAGE

IF DACEN = 1
DACR  4:0 
VOUT =   VSOURCE+ – VSOURCE-   ----------------------------- + VSOURCE-
 5 
2
IF DACEN = 0 and DACLPS = 1 and DACR[4:0] = 11111
V OUT = V SOURCE +
IF DACEN = 0 and DACLPS = 0 and DACR[4:0] = 00000
V OUT = V SOURCE –
VSOURCE+ = VDD, VREF+, or FVR BUFFER 2

VSOURCE- = VSS or VREF-
17.2 Ratiometric Output Level 17.3 DAC Voltage Reference Output

The DAC output value is derived using a resistor ladder The DAC can be output to the DACOUT pin by setting
with each end of the ladder tied to a positive and the DACOE bit of the DACCON0 register to ‘1’.
negative voltage reference input source. If the voltage Selecting the DAC reference voltage for output on the
of either input source fluctuates, a similar fluctuation will DACOUT pin automatically overrides the digital output
result in the DAC output value. buffer and digital input threshold detector functions of
The value of the individual resistors within the ladder that pin. Reading the DACOUT pin when it has been
can be found in Section 30.0 “Electrical configured for DAC reference voltage output will
Specifications”. always return a ‘0’.
Due to the limited current drive capability, a buffer must
be used on the DAC voltage reference output for
external connections to DACOUT. Figure 17-2 shows
an example buffering technique.

PIC16(L)F1933
FIGURE 17-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM
Digital-to-Analog Converter (DAC)
FVR BUFFER2
VDD
VSOURCE+
DACR<4:0>
5
VREF+
R
R
DACPSS<1:0>
2
R
DACEN
DACLPS R
32-to-1 MUX
32 DAC_OUTPUT
Steps (To Comparator,
CPS and ADC
Modules)
R
R
DACOUT
R
DACOE
DACNSS
VREF- VSOURCE-
VSS
FIGURE 17-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC® MCU
DAC
R
Module
+
Voltage DACOUT Buffered DAC Output
–
Reference
Output
Impedance

PIC16(L)F1933
17.4 Low-Power Voltage State This is also the method used to output the voltage level
from the FVR to an output pin. See Section 17.5
In order for the DAC module to consume the least “Operation During Sleep” for more information.
amount of power, one of the two voltage reference input
sources to the resistor ladder must be disconnected. Reference Figure 17-3 for output clamping examples.
Either the positive voltage source, (VSOURCE+), or the
17.4.2 OUTPUT CLAMPED TO NEGATIVE
negative voltage source, (VSOURCE-) can be disabled.
VOLTAGE SOURCE
The negative voltage source is disabled by setting the
DACLPS bit in the DACCON0 register. Clearing the The DAC output voltage can be set to VSOURCE- with
DACLPS bit in the DACCON0 register disables the the least amount of power consumption by performing
positive voltage source. the following:
• Clearing the DACEN bit in the DACCON0 register.
17.4.1 OUTPUT CLAMPED TO POSITIVE • Clearing the DACLPS bit in the DACCON0 register.
VOLTAGE SOURCE • Configuring the DACNSS bits to the proper
The DAC output voltage can be set to VSOURCE+ with negative source.
the least amount of power consumption by performing • Configuring the DACR<4:0> bits to ‘00000’ in the
the following: DACCON1 register.
• Clearing the DACEN bit in the DACCON0 register. This allows the comparator to detect a zero-crossing
• Setting the DACLPS bit in the DACCON0 register. while not consuming additional current through the DAC
• Configuring the DACPSS bits to the proper module.
positive source. Reference Figure 17-3 for output clamping examples.
• Configuring the DACR<4:0> bits to ‘11111’ in the
DACCON1 register.
FIGURE 17-3: OUTPUT VOLTAGE CLAMPING EXAMPLES
Output Clamped to Positive Voltage Source Output Clamped to Negative Voltage Source
VSOURCE+ VSOURCE+
R R
DACR<4:0> = 11111
R R
DACEN = 0 DACEN = 0
DACLPS = 1 DAC Voltage Ladder DACLPS = 0 DAC Voltage Ladder
(see Figure 17-1) (see Figure 17-1)
R R
DACR<4:0> = 00000
VSOURCE- VSOURCE-
17.5 Operation During Sleep

When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the DACCON0 register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
17.6 Effects of a Reset

A device Reset affects the following:
• DAC is disabled.
• DAC output voltage is removed from the
DACOUT pin.
• The DACR<4:0> range select bits are cleared.

PIC16(L)F1933
17.7 Register Definitions: DAC Control
REGISTER 17-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0

R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0
DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS
bit 7 bit 0
Legend:
bit 7 DACEN: DAC Enable bit

1 = DAC is enabled
0 = DAC is disabled
bit 6 DACLPS: DAC Low-Power Voltage State Select bit
1 = DAC Positive reference source selected
0 = DAC Negative reference source selected
bit 5 DACOE: DAC Voltage Output Enable bit
1 = DAC voltage level is also an output on the DACOUT pin
0 = DAC voltage level is disconnected from the DACOUT pin
bit 3-2 DACPSS<1:0>: DAC Positive Source Select bits
11 = Reserved, do not use
10 = FVR Buffer2 output
01 = VREF+ pin
00 = VDD
bit 0 DACNSS: DAC Negative Source Select bits
1 = VREF-
0 = VSS
REGISTER 17-2: DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1

U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — DACR<4:0>
bit 7 bit 0
Legend:

bit 4-0 DACR<4:0>: DAC Voltage Output Select bits
TABLE 17-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE

Register
on page
DACCON1 — — — DACR<4:0> 156
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC module.

PIC16(L)F1933
18.0 COMPARATOR MODULE FIGURE 18-1: SINGLE COMPARATOR
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and VIN+ +
providing a digital indication of their relative magnitudes. Output
Comparators are very useful mixed signal building VIN- –
blocks because they provide analog functionality
independent of program execution. The analog
comparator module includes the following features:
• Independent comparator control VIN-
• Programmable input selection VIN+
• Comparator output is available internally/externally
• Programmable output polarity
• Interrupt-on-change
• Wake-up from Sleep Output
• Programmable Speed/Power optimization
• PWM shutdown
Note: The black areas of the output of the
• Programmable and fixed voltage reference
comparator represents the uncertainty
18.1 Comparator Overview due to input offsets and response time.
A single comparator is shown in Figure 18-1 along with

the relationship between the analog input levels and
the digital output. When the analog voltage at VIN+ is
less than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the output of the comparator is a digital high level.
The comparators available for this device are located in
Table 18-1.
TABLE 18-1: COMPARATOR AVAILABILITY

PER DEVICE
Device C1 C2
PIC16(L)F1933 ● ●

PIC16(L)F1933
FIGURE 18-2: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM
CxNCH<1:0>
CxON(1)
2 Interrupt CxINTP
det
C12IN0- 0 Set CxIF
C12IN1- 1
MUX Interrupt CxINTN
C12IN2- 2 (1) det
CXPOL
C12IN3- 3 CxVN
-
CXOUT To Data Bus
D Q
Cx(2) MCXOUT
+
CxVP
Q1 EN
CXIN+ 0
MUX CxHYS
DAC_OUTPUT 1 (1) CxSP async_CxOUT
To ECCP PWM Logic
FVR Buffer2 2
3
CXSYNC
VSS CxON CXOE
TRIS bit
CXOUT
CXPCH<1:0> 0
2
D Q 1
(from Timer1)
T1CLK To Timer1 or
sync_CXOUT
SR Latch
Note 1: When CxON = 0, all multiplexer inputs are disconnected and the Comparator will product a ‘0’ at the output.
2: Output of comparator can be frozen during debugging.

PIC16(L)F1933
18.2 Comparator Control 18.2.3 COMPARATOR OUTPUT POLARITY
Each comparator has two control registers: CMxCON0 Inverting the output of the comparator is functionally
and CMxCON1. equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
The CMxCON0 registers (see Register 18-1) contain setting the CxPOL bit of the CMxCON0 register.
Control and Status bits for the following: Clearing the CxPOL bit results in a non-inverted output.
• Enable Table 18-2 shows the output state versus input
• Output selection conditions, including polarity control.
• Output polarity TABLE 18-2: COMPARATOR OUTPUT
• Speed/Power selection STATE VS. INPUT
• Hysteresis enable CONDITIONS
• Output synchronization Input Condition CxPOL CxOUT
The CMxCON1 registers (see Register 18-2) contain
CxVN > CxVP 0 0
Control bits for the following:
CxVN < CxVP 0 1
• Interrupt enable
CxVN > CxVP 1 1
• Interrupt edge polarity
CxVN < CxVP 1 0
• Positive input channel selection
• Negative input channel selection 18.2.4 COMPARATOR SPEED/POWER
18.2.1 COMPARATOR ENABLE SELECTION
The trade-off between speed or power can be
Setting the CxON bit of the CMxCON0 register enables
optimized during program execution with the CxSP
the comparator for operation. Clearing the CxON bit
control bit. The default state for this bit is ‘1’ which
disables the comparator resulting in minimum current
selects the normal speed mode. Device power
consumption.
consumption can be optimized at the cost of slower
18.2.2 COMPARATOR OUTPUT comparator propagation delay by clearing the CxSP bit
to ‘0’.
SELECTION
The output of the comparator can be monitored by
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CMOUT register. In order to
make the output available for an external connection,
the following conditions must be true:
• CxOE bit of the CMxCON0 register must be set
• Corresponding TRIS bit must be cleared
• CxON bit of the CMxCON0 register must be set
Note 1: The CxOE bit of the CMxCON0 register

overrides the PORT data latch. Setting
the CxON bit of the CMxCON0 register
has no impact on the port override.
2: The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external
outputs are not latched.

PIC16(L)F1933
18.3 Comparator Hysteresis 18.5 Comparator Interrupt
A selectable amount of separation voltage can be An interrupt can be generated upon a change in the
added to the input pins of each comparator to provide a output value of the comparator for each comparator, a
hysteresis function to the overall operation. Hysteresis rising edge detector and a Falling edge detector are
is enabled by setting the CxHYS bit of the CMxCON0 present.
register. When either edge detector is triggered and its associ-
See Section 30.0 “Electrical Specifications” for ated enable bit is set (CxINTP and/or CxINTN bits of
more information. the CMxCON1 register), the Corresponding Interrupt
Flag bit (CxIF bit of the PIR2 register) will be set.
18.4 Timer1 Gate Operation To enable the interrupt, you must set the following bits:
The output resulting from a comparator operation can • CxON, CxPOL and CxSP bits of the CMxCON0
be used as a source for gate control of Timer1. See register
Section 21.6 “Timer1 Gate” for more information. • CxIE bit of the PIE2 register
This feature is useful for timing the duration or interval • CxINTP bit of the CMxCON1 register (for a rising
of an analog event. edge detection)
It is recommended that the comparator output be • CxINTN bit of the CMxCON1 register (for a falling
synchronized to Timer1. This ensures that Timer1 does edge detection)
not increment while a change in the comparator is • PEIE and GIE bits of the INTCON register
occurring.
The associated interrupt flag bit, CxIF bit of the PIR2
18.4.1 COMPARATOR OUTPUT register, must be cleared in software. If another edge is
SYNCHRONIZATION detected while this flag is being cleared, the flag will still
be set at the end of the sequence.
The output from either comparator, C1 or C2, can be
synchronized with Timer1 by setting the CxSYNC bit of Note: Although a comparator is disabled, an
the CMxCON0 register. interrupt can be generated by changing
the output polarity with the CxPOL bit of
Once enabled, the comparator output is latched on the
the CMxCON0 register, or by switching
falling edge of the Timer1 source clock. If a prescaler is
the comparator on or off with the CxON bit
used with Timer1, the comparator output is latched after
of the CMxCON0 register.
the prescaling function. To prevent a race condition, the
comparator output is latched on the falling edge of the
Timer1 clock source and Timer1 increments on the 18.6 Comparator Positive Input
rising edge of its clock source. See the Comparator Selection
Block Diagram (Figure 18-2) and the Timer1 Block
Diagram (Figure 22-1) for more information. Configuring the CxPCH<1:0> bits of the CMxCON1
register directs an internal voltage reference or an
analog pin to the non-inverting input of the comparator:
• CxIN+ analog pin
• DAC_output
• DAC FVR Buffer2
• VSS (Ground)
See Section 14.0 “Fixed Voltage Reference (FVR)”
for more information on the Fixed Voltage Reference
module.
See Section 17.0 “Digital-to-Analog Converter
(DAC) Module” for more information on the DAC input
signal.
Any time the comparator is disabled (CxON = 0), all
comparator inputs are disabled.

PIC16(L)F1933
18.7 Comparator Negative Input 18.10 Analog Input Connection
Selection Considerations
The CxNCH<1:0> bits of the CMxCON0 register direct A simplified circuit for an analog input is shown in
one of four analog pins to the comparator inverting Figure 18-3. Since the analog input pins share their
input. connection with a digital input, they have reverse
biased ESD protection diodes to VDD and VSS. The
Note: To use CxIN+ and CxINx- pins as analog
analog input, therefore, must be between VSS and VDD.
input, the appropriate bits must be set in
If the input voltage deviates from this range by more
the ANSEL register and the correspond-
than 0.6V in either direction, one of the diodes is
ing TRIS bits must also be set to disable
forward biased and a latch-up may occur.
the output drivers.
A maximum source impedance of 10 k is recommended
for the analog sources. Also, any external component
18.8 Comparator Response Time connected to an analog input pin, such as a capacitor or
The comparator output is indeterminate for a period of a Zener diode, should have very little leakage current to
time after the change of an input source or the selection minimize inaccuracies introduced.
of a new reference voltage. This period is referred to as
the response time. The response time of the comparator
differs from the settling time of the voltage reference. Note 1: When reading a PORT register, all pins
Therefore, both of these times must be considered when configured as analog inputs will read as a
determining the total response time to a comparator ‘0’. Pins configured as digital inputs will
input change. See the Comparator and Voltage convert as an analog input, according to
Reference specifications in Section 30.0 “Electrical the input specification.
Specifications” for more details. 2: Analog levels on any pin defined as a
digital input, may cause the input buffer to
18.9 Interaction with ECCP Logic consume more current than is specified.
The C1 and C2 comparators can be used as general

purpose comparators. Their outputs can be brought
out to the C1OUT and C2OUT pins. When the ECCP
auto-shutdown is active it can use one or both
comparator signals. If auto-restart is also enabled, the
comparators can be configured as a closed loop
analog feedback to the ECCP, thereby, creating an
analog controlled PWM.
Note: When the comparator module is first
initialized the output state is unknown.
Upon initialization, the user should verify
the output state of the comparator prior to
relying on the result, primarily when using
the result in connection with other
peripheral features, such as the ECCP
Auto-Shutdown mode.

PIC16(L)F1933
FIGURE 18-3: ANALOG INPUT MODEL
VDD
Analog
Input
pin VT  0.6V RIC
Rs < 10K
To Comparator
CPIN ILEAKAGE(1)
VA VT  0.6V
5 pF
Vss
Legend: CPIN = Input Capacitance

ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS = Source Impedance
VA = Analog Voltage
VT = Threshold Voltage
Note 1: See Section 30.0 “Electrical Specifications”.

PIC16(L)F1933
18.11 Register Definitions: Comparator Control
REGISTER 18-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0

R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 U-0 R/W-1/1 R/W-0/0 R/W-0/0
CxON CxOUT CxOE CxPOL — CxSP CxHYS CxSYNC
bit 7 bit 0
Legend:
bit 7 CxON: Comparator Enable bit

1 = Comparator is enabled and consumes no active power
0 = Comparator is disabled
bit 6 CxOUT: Comparator Output bit
If CxPOL = 1 (inverted polarity):
1 = CxVP < CxVN
0 = CxVP > CxVN
If CxPOL = 0 (non-inverted polarity):
1 = CxVP > CxVN
0 = CxVP < CxVN
bit 5 CxOE: Comparator Output Enable bit
1 = CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually
drive the pin. Not affected by CxON.
0 = CxOUT is internal only
bit 4 CxPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 2 CxSP: Comparator Speed/Power Select bit
1 = Comparator operates in normal power, higher speed mode
0 = Comparator operates in low-power, low-speed mode
bit 1 CxHYS: Comparator Hysteresis Enable bit
1 = Comparator hysteresis enabled
0 = Comparator hysteresis disabled
bit 0 CxSYNC: Comparator Output Synchronous Mode bit
1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source.
Output updated on the falling edge of Timer1 clock source.
0 = Comparator output to Timer1 and I/O pin is asynchronous

PIC16(L)F1933
REGISTER 18-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
CxINTP CxINTN CxPCH<1:0> — — CxNCH<1:0>
bit 7 bit 0
Legend:
bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits

1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit
0 = No interrupt flag will be set on a positive going edge of the CxOUT bit
bit 6 CxINTN: Comparator Interrupt on Negative Going Edge Enable bits
1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit
0 = No interrupt flag will be set on a negative going edge of the CxOUT bit
bit 5-4 CxPCH<1:0>: Comparator Positive Input Channel Select bits
11 = CxVP connects to VSS
10 = CxVP connects to FVR Voltage Reference
01 = CxVP connects to DAC Voltage Reference
00 = CxVP connects to CxIN+ pin
bit 1-0 CxNCH<1:0>: Comparator Negative Input Channel Select bits
11 = CxVN connects to C12IN3- pin
REGISTER 18-3: CMOUT: COMPARATOR OUTPUT REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R-0/0 R-0/0
— — — — — — MC2OUT MC1OUT
bit 7 bit 0
Legend:

bit 1 MC2OUT: Mirror Copy of C2OUT bit
bit 0 MC1OUT: Mirror Copy of C1OUT bit

PIC16(L)F1933
TABLE 18-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Register
on Page
CM1CON0 C1ON C1OUT C1OE C1POL --- C1SP C1HYS C1SYNC 163
CMOUT — — — — — — MC2OUT MC1OUT 164
DACCON1 — — — DACR<4:0> 156
Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.

PIC16(L)F1933
NOTES:

PIC16(L)F1933
19.0 SR LATCH 19.2 Latch Output
The module consists of a single SR latch with multiple The SRQEN and SRNQEN bits of the SRCON0
Set and Reset inputs as well as separate latch outputs. register control the Q and Q latch outputs. Both of the
The SR latch module includes the following features: SR latch outputs may be directly output to an I/O pin at
the same time. The Q latch output pin function can be
• Programmable input selection
moved to an alternate pin using the SRNQSEL bit of
• SR latch output is available externally the APFCON register.
• Separate Q and Q outputs
The applicable TRIS bit of the corresponding port must
• Firmware Set and Reset be cleared to enable the port pin output driver.
The SR latch can be used in a variety of analog appli-
cations, including oscillator circuits, one-shot circuit, 19.3 Effects of a Reset
hysteretic controllers, and analog timing applications.
Upon any device Reset, the SR latch output is not
19.1 Latch Operation initialized to a known state. The user’s firmware is
responsible for initializing the latch output before
The latch is a Set-Reset Latch that does not depend on enabling the output pins.
a clock source. Each of the Set and Reset inputs are
active-high. The latch can be set or reset by:
• Software control (SRPS and SRPR bits)
• Comparator C1 output (sync_C1OUT)
• Comparator C2 output (sync_C2OUT)
• SRI pin
• Programmable clock (SRCLK)
The SRPS and the SRPR bits of the SRCON0 register
may be used to set or reset the SR latch, respectively.
The latch is Reset-dominant. Therefore, if both Set and
Reset inputs are high, the latch will go to the Reset
state. Both the SRPS and SRPR bits are self resetting
which means that a single write to either of the bits is all
that is necessary to complete a latch Set or Reset oper-
ation.
The output from Comparator C1 or C2 can be used as
the Set or Reset inputs of the SR latch. The output of
either comparator can be synchronized to the Timer1
clock source. See Section 18.0 “Comparator
Module” and Section 21.0 “Timer1 Module with
Gate Control” for more information.
An external source on the SRI pin can be used as the
Set or Reset inputs of the SR latch.
An internal clock source is available that can periodically
set or reset the SR latch. The SRCLK<2:0> bits in the
SRCON0 register are used to select the clock source
period. The SRSCKE and SRRCKE bits of the SRCON1
register enable the clock source to set or reset the SR
latch, respectively.

PIC16(L)F1933
FIGURE 19-1: SR LATCH SIMPLIFIED BLOCK DIAGRAM
SRLEN
SRPS Pulse SRQEN
Gen(2)
SRI
SRSPE S Q
SRCLK
SRQ
SRSCKE
sync_C2OUT(3)
SRSC2E
sync_C1OUT(3)
SR
SRSC1E
Latch(1)
SRPR Pulse
Gen(2)
SRI
SRRPE R Q
SRCLK SRNQ
SRRCKE SRLEN
sync_C2OUT(3) SRNQEN
SRRC2E
sync_C1OUT(3)
SRRC1E
Note 1: If R = 1 and S = 1 simultaneously, Q = 0, Q = 1

2: Pulse generator causes a 1 Q-state pulse width.
3: Name denotes the connection point at the comparator output.
TABLE 19-1: SRCLK FREQUENCY TABLE

SRCLK Divider FOSC = 32 MHz FOSC = 20 MHz FOSC = 16 MHz FOSC = 4 MHz FOSC = 1 MHz
111 512 62.5 kHz 39.0 kHz 31.3 kHz 7.81 kHz 1.95 kHz
110 256 125 kHz 78.1 kHz 62.5 kHz 15.6 kHz 3.90 kHz
101 128 250 kHz 156 kHz 125 kHz 31.25 kHz 7.81 kHz
100 64 500 kHz 313 kHz 250 kHz 62.5 kHz 15.6 kHz
011 32 1 MHz 625 kHz 500 kHz 125 kHz 31.3 kHz
010 16 2 MHz 1.25 MHz 1 MHz 250 kHz 62.5 kHz
001 8 4 MHz 2.5 MHz 2 MHz 500 kHz 125 kHz
000 4 8 MHz 5 MHz 4 MHz 1 MHz 250 kHz

PIC16(L)F1933
19.4 Register Definitions: SR Latch Control
REGISTER 19-1: SRCON0: SR LATCH CONTROL 0 REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/S-0/0 R/S-0/0
SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared S = Bit is set only
bit 7 SRLEN: SR Latch Enable bit

1 = SR latch is enabled
0 = SR latch is disabled
bit 6-4 SRCLK<2:0>: SR Latch Clock Divider bits
111 = Generates a 1 FOSC wide pulse every 512th FOSC cycle clock
011 = Generates a 1 FOSC wide pulse every 32nd FOSC cycle clock
bit 3 SRQEN: SR Latch Q Output Enable bit
If SRLEN = 1:
1 = Q is present on the SRQ pin
0 = External Q output is disabled
If SRLEN = 0:
SR latch is disabled
bit 2 SRNQEN: SR Latch Q Output Enable bit
If SRLEN = 1:
1 = Q is present on the SRnQ pin
0 = External Q output is disabled
If SRLEN = 0:
SR latch is disabled
bit 1 SRPS: Pulse Set Input of the SR Latch bit(1)
1 = Pulse set input for 1 Q-clock period
0 = No effect on set input.
bit 0 SRPR: Pulse Reset Input of the SR Latch bit(1)
1 = Pulse reset input for 1 Q-clock period
0 = No effect on reset input.
Note 1: Set only, always reads back ‘0’.
REGISTER 19-2: SRCON1: SR LATCH CONTROL 1 REGISTER

SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E
bit 7 bit 0
Legend:

PIC16(L)F1933
REGISTER 19-2: SRCON1: SR LATCH CONTROL 1 REGISTER (CONTINUED)
bit 7 SRSPE: SR Latch Peripheral Set Enable bit

1 = SR latch is set when the SRI pin is high.
0 = SRI pin has no effect on the set input of the SR latch
bit 6 SRSCKE: SR Latch Set Clock Enable bit
1 = Set input of SR latch is pulsed with SRCLK
0 = SRCLK has no effect on the set input of the SR latch
bit 5 SRSC2E: SR Latch C2 Set Enable bit
1 = SR latch is set when the C2 Comparator output is high
0 = C2 Comparator output has no effect on the set input of the SR latch
bit 4 SRSC1E: SR Latch C1 Set Enable bit
1 = SR latch is set when the C1 Comparator output is high
0 = C1 Comparator output has no effect on the set input of the SR latch
bit 3 SRRPE: SR Latch Peripheral Reset Enable bit
1 = SR latch is reset when the SRI pin is high.
0 = SRI pin has no effect on the reset input of the SR latch
bit 2 SRRCKE: SR Latch Reset Clock Enable bit
1 = Reset input of SR latch is pulsed with SRCLK
0 = SRCLK has no effect on the reset input of the SR latch
bit 1 SRRC2E: SR Latch C2 Reset Enable bit
1 = SR latch is reset when the C2 Comparator output is high
0 = C2 Comparator output has no effect on the reset input of the SR latch
bit 0 SRRC1E: SR Latch C1 Reset Enable bit
1 = SR latch is reset when the C1 Comparator output is high
0 = C1 Comparator output has no effect on the reset input of the SR latch
TABLE 19-2: SUMMARY OF REGISTERS ASSOCIATED WITH SR LATCH MODULE

Register
on Page
SRCON0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR 169
SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 169
Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the SR latch module.

PIC16(L)F1933
20.0 TIMER0 MODULE 20.1.2 8-BIT COUNTER MODE
The Timer0 module is an 8-bit timer/counter with the In 8-Bit Counter mode, the Timer0 module will increment
following features: on every rising or falling edge of the T0CKI pin or the
Capacitive Sensing Oscillator (CPSCLK) signal.
• 8-bit timer/counter register (TMR0)
8-Bit Counter mode using the T0CKI pin is selected by
• 8-bit prescaler (independent of Watchdog Timer)
setting the TMR0CS bit in the OPTION_REG register to
• Programmable internal or external clock source ‘1’ and resetting the T0XCS bit in the CPSCON0 register
• Programmable external clock edge selection to ‘0’.
• Interrupt on overflow 8-Bit Counter mode using the Capacitive Sensing
• TMR0 can be used to gate Timer1 Oscillator (CPSCLK) signal is selected by setting the
Figure 20-1 is a block diagram of the Timer0 module. TMR0CS bit in the OPTION_REG register to ‘1’ and
setting the T0XCS bit in the CPSCON0 register to ‘1’.
20.1 Timer0 Operation The rising or falling transition of the incrementing edge
for either input source is determined by the TMR0SE bit
The Timer0 module can be used as either an 8-bit timer in the OPTION_REG register.
or an 8-bit counter.
20.1.1 8-BIT TIMER MODE

The Timer0 module will increment every instruction
cycle, if used without a prescaler. 8-bit Timer mode is
selected by clearing the TMR0CS bit of the
OPTION_REG register.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
Note: The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
FIGURE 20-1: BLOCK DIAGRAM OF THE TIMER0
FOSC/4
Data Bus
0
8
T0CKI 1
0 Sync
1 2 TCY TMR0
0
From CPSCLK
1 TMR0SE Set Flag bit TMR0IF
TMR0CS 8-bit on Overflow
Prescaler PSA
T0XCS
Overflow to Timer1
PS<2:0>

PIC16(L)F1933
20.1.3 SOFTWARE PROGRAMMABLE
PRESCALER
A software programmable prescaler is available for
exclusive use with Timer0. The prescaler is enabled by
clearing the PSA bit of the OPTION_REG register.
Note: The Watchdog Timer (WDT) uses its own
independent prescaler.
There are eight prescaler options for the Timer0 mod-
ule ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION_REG
register. In order to have a 1:1 prescaler value for the
Timer0 module, the prescaler must be disabled by
setting the PSA bit of the OPTION_REG register.
The prescaler is not readable or writable. All instructions
writing to the TMR0 register will clear the prescaler.
20.1.4 TIMER0 INTERRUPT

Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The TMR0IF
interrupt flag bit of the INTCON register is set every
time the TMR0 register overflows, regardless of
whether or not the Timer0 interrupt is enabled. The
TMR0IF bit can only be cleared in software. The Timer0
interrupt enable is the TMR0IE bit of the INTCON
register.
Note: The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
20.1.5 8-BIT COUNTER MODE

SYNCHRONIZATION
When in 8-Bit Counter mode, the incrementing edge on
the T0CKI pin must be synchronized to the instruction
clock. Synchronization can be accomplished by
sampling the prescaler output on the Q2 and Q4 cycles
of the instruction clock. The high and low periods of the
external clocking source must meet the timing
requirements as shown in Section 30.0 “Electrical
Specifications”.
20.1.6 OPERATION DURING SLEEP

Timer0 cannot operate while the processor is in Sleep
mode. The contents of the TMR0 register will remain
unchanged while the processor is in Sleep mode.

PIC16(L)F1933
20.2 Register Definitions: Option Register
REGISTER 20-1: OPTION_REG: OPTION REGISTER

WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0>
bit 7 bit 0
Legend:
bit 7 WPUEN: Weak Pull-Up Enable bit

1 = All weak pull-ups are disabled (except MCLR, if it is enabled)
0 = Weak pull-ups are enabled by individual WPUx latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5 TMR0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4 TMR0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is not assigned to the Timer0 module
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Bit Value Timer0 Rate
000 1:2
001 1:4
010 1:8
011 1 : 16
100 1 : 32
101 1 : 64
110 1 : 128
111 1 : 256
TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Register
on Page
TMR0 Timer0 Module Register 171*
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.

PIC16(L)F1933
NOTES:

PIC16(L)F1933
21.0 TIMER1 MODULE WITH GATE • Gate Toggle mode
CONTROL • Gate Single-pulse mode
• Gate Value Status
The Timer1 module is a 16-bit timer/counter with the
• Gate Event Interrupt
following features:
Figure 21-1 is a block diagram of the Timer1 module.
• 16-bit timer/counter register pair (TMR1H:TMR1L)
• Programmable internal or external clock source
• 2-bit prescaler
• Dedicated 32 kHz oscillator circuit
• Optionally synchronized comparator out
• Multiple Timer1 gate (count enable) sources
• Interrupt on overflow
• Wake-up on overflow (external clock,
Asynchronous mode only)
• Time base for the Capture/Compare function
• Special Event Trigger (with CCP/ECCP)
• Selectable Gate Source Polarity
FIGURE 21-1: TIMER1 BLOCK DIAGRAM
T1GSS<1:0>
T1G 00 T1GSPM
From Timer0 01 t1g_in 0

Overflow T1GVAL Data Bus
0 D Q
Comparator 1 10 Single Pulse RD
sync_C1OUT 1 T1GCON
Acq. Control Q1 EN
D Q 1
Comparator 2 11 Interrupt
sync_C2OUT Q T1GGO/DONE Set
TMR1ON CK
det TMR1GIF
R
T1GPOL T1GTM
TMR1GE
Set flag bit TMR1ON
TMR1IF on To Comparator Module
Overflow TMR1(2)
EN Synchronized
To ADC Auto-Conversion 0 clock input
TMR1H TMR1L T1CLK
Q D
1
TMR1CS<1:0>
T1SYNC
T1OSO OUT
Cap. Sensing
11
T1OSC Oscillator Prescaler Synchronize(3)
1 1, 2, 4, 8 det
T1OSI 10
EN
2
0
FOSC T1CKPS<1:0>
Internal 01
Clock FOSC/2
T1OSCEN Sleep input
Internal
FOSC/4 Clock
Internal 00
(1) Clock
T1CKI
To LCD and Clock Switching Modules
Note 1: ST Buffer is high speed type when using T1CKI.

2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.

PIC16(L)F1933
21.1 Timer1 Operation 21.2 Clock Source Selection
The Timer1 module is a 16-bit incrementing counter The TMR1CS<1:0> and T1OSCEN bits of the T1CON
which is accessed through the TMR1H:TMR1L register register are used to select the clock source for Timer1.
pair. Writes to TMR1H or TMR1L directly update the Table 21-2 displays the clock source selections.
counter.
21.2.1 INTERNAL CLOCK SOURCE
When used with an internal clock source, the module is
a timer and increments on every instruction cycle. When the internal clock source is selected, the
When used with an external clock source, the module TMR1H:TMR1L register pair will increment on multiples
can be used as either a timer or counter and of FOSC as determined by the Timer1 prescaler.
increments on every selected edge of the external When the FOSC internal clock source is selected, the
source. Timer1 register value will increment by four counts every
Timer1 is enabled by configuring the TMR1ON and instruction clock cycle. Due to this condition, a 2 LSB
TMR1GE bits in the T1CON and T1GCON registers, error in resolution will occur when reading the Timer1
respectively. Table 21-1 displays the Timer1 enable value. To utilize the full resolution of Timer1, an
selections. asynchronous input signal must be used to gate the
Timer1 clock input.
TABLE 21-1: TIMER1 ENABLE The following asynchronous sources may be used:
SELECTIONS • Asynchronous event on the T1G pin to Timer1
gate
Timer1
TMR1ON TMR1GE • C1 or C2 comparator input to Timer1 gate
Operation
0 0 Off 21.2.2 EXTERNAL CLOCK SOURCE
0 1 Off When the external clock source is selected, the Timer1
1 0 Always On module may work as a timer or a counter.
1 1 Count Enabled When enabled to count, Timer1 is incremented on the
rising edge of the external clock input T1CKI or the
capacitive sensing oscillator signal. Either of these
external clock sources can be synchronized to the
microcontroller system clock or they can run
asynchronously.
When used as a timer with a clock oscillator, an
external 32.768 kHz crystal can be used in conjunction
with the dedicated internal oscillator circuit.
Note: In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions:
• Timer1 enabled after POR
• Write to TMR1H or TMR1L
• Timer1 is disabled
• Timer1 is disabled (TMR1ON = 0)
when T1CKI is high then Timer1 is
enabled (TMR1ON=1) when T1CKI is
low.
TABLE 21-2: CLOCK SOURCE SELECTIONS

TMR1CS<1:0> T1OSCEN Clock Source
11 x Capacitive Sensing Oscillator
10 0 External Clocking on T1CKI Pin
01 x System Clock (FOSC)
00 x Instruction Clock (FOSC/4)

PIC16(L)F1933
21.3 Timer1 Prescaler 21.5.1 READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
Timer1 has four prescaler options allowing 1, 2, 4 or 8
MODE
divisions of the clock input. The T1CKPS bits of the
T1CON register control the prescale counter. The Reading TMR1H or TMR1L while the timer is running
prescale counter is not directly readable or writable; from an external asynchronous clock will ensure a valid
however, the prescaler counter is cleared upon a write to read (taken care of in hardware). However, the user
TMR1H or TMR1L. should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
21.4 Timer1 Oscillator timer may overflow between the reads.
For writes, it is recommended that the user simply stop
A dedicated low-power 32.768 kHz oscillator circuit is
the timer and write the desired values. A write
built-in between pins T1OSI (input) and T1OSO
contention may occur by writing to the timer registers,
(amplifier output). This internal circuit is to be used in
while the register is incrementing. This may produce an
conjunction with an external 32.768 kHz crystal.
unpredictable value in the TMR1H:TMR1L register pair.
The oscillator circuit is enabled by setting the
T1OSCEN bit of the T1CON register. The oscillator will 21.6 Timer1 Gate
continue to run during Sleep.
Timer1 can be configured to count freely or the count
Note: The oscillator requires a start-up and can be enabled and disabled using Timer1 gate
stabilization time before use. Thus, circuitry. This is also referred to as Timer1 Gate Enable.
T1OSCEN should be set and a suitable
delay observed prior to using Timer1. A Timer1 gate can also be driven by multiple selectable
suitable delay similar to the OST delay sources.
can be implemented in software by
clearing the TMR1IF bit then presetting 21.6.1 TIMER1 GATE ENABLE
the TMR1H:TMR1L register pair to The Timer1 Gate Enable mode is enabled by setting
FC00h. The TMR1IF flag will be set when the TMR1GE bit of the T1GCON register. The polarity
1024 clock cycles have elapsed, thereby of the Timer1 Gate Enable mode is configured using
indicating that the oscillator is running and the T1GPOL bit of the T1GCON register.
reasonably stable. When Timer1 Gate Enable mode is enabled, Timer1
will increment on the rising edge of the Timer1 clock
21.5 Timer1 Operation in source. When Timer1 Gate Enable mode is disabled,
Asynchronous Counter Mode no incrementing will occur and Timer1 will hold the
current count. See Figure 21-3 for timing details.
If the control bit T1SYNC of the T1CON register is set,
the external clock input is not synchronized. The timer
increments asynchronously to the internal phase TABLE 21-3: TIMER1 GATE ENABLE
clocks. If the external clock source is selected then the SELECTIONS
timer will continue to run during Sleep and can T1CLK T1GPOL T1G Timer1 Operation
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in  0 0 Counts
software are needed to read/write the timer (see  0 1 Holds Count
Section 21.5.1 “Reading and Writing Timer1 in  1 0 Holds Count
Asynchronous Counter Mode”).
 1 1 Counts
Note: When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.

PIC16(L)F1933
21.6.2 TIMER1 GATE SOURCE Timer1 Gate Toggle mode is enabled by setting the
SELECTION T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
The Timer1 gate source can be selected from one of
is necessary in order to control which edge is
four different sources. Source selection is controlled by
measured.
the T1GSS bits of the T1GCON register. The polarity
for each available source is also selectable. Polarity Note: Enabling Toggle mode at the same time
selection is controlled by the T1GPOL bit of the as changing the gate polarity may result in
T1GCON register. indeterminate operation.
TABLE 21-4: TIMER1 GATE SOURCES 21.6.4 TIMER1 GATE SINGLE-PULSE

T1GSS Timer1 Gate Source MODE
When Timer1 Gate Single-Pulse mode is enabled, it is
00 Timer1 Gate Pin
possible to capture a single-pulse gate event. Timer1
01 Overflow of Timer0 Gate Single-Pulse mode is first enabled by setting the
(TMR0 increments from FFh to 00h) T1GSPM bit in the T1GCON register. Next, the
10 Comparator 1 Output sync_C1OUT T1GGO/DONE bit in the T1GCON register must be set.
(optionally Timer1 synchronized output) The Timer1 will be fully enabled on the next
Comparator 2 Output sync_C2OUT incrementing edge. On the next trailing edge of the
11
(optionally Timer1 synchronized output) pulse, the T1GGO/DONE bit will automatically be
cleared. No other gate events will be allowed to
increment Timer1 until the T1GGO/DONE bit is once
21.6.2.1 T1G Pin Gate Operation
again set in software. See Figure 21-5 for timing details.
The T1G pin is one source for Timer1 gate control. It
If the Single-Pulse Gate mode is disabled by clearing the
can be used to supply an external source to the Timer1
T1GSPM bit in the T1GCON register, the T1GGO/DONE
gate circuitry.
bit should also be cleared.
21.6.2.2 Timer0 Overflow Gate Operation Enabling the Toggle mode and the Single-Pulse mode
When Timer0 increments from FFh to 00h, a simultaneously will permit both sections to work
low-to-high pulse will automatically be generated and together. This allows the cycle times on the Timer1 gate
internally supplied to the Timer1 gate circuitry. source to be measured. See Figure 21-6 for timing
details.
21.6.2.3 Comparator C1 Gate Operation
21.6.5 TIMER1 GATE VALUE STATUS
The output resulting from a Comparator 1 operation can
be selected as a source for Timer1 gate control. The When Timer1 Gate Value Status is utilized, it is possible
Comparator 1 output (sync_C1OUT) can be to read the most current level of the gate control value.
synchronized to the Timer1 clock or left asynchronous. The value is stored in the T1GVAL bit in the T1GCON
For more information see Section 18.4.1 “Comparator register. The T1GVAL bit is valid even when the Timer1
Output Synchronization”. gate is not enabled (TMR1GE bit is cleared).
21.6.2.4 Comparator C2 Gate Operation 21.6.6 TIMER1 GATE EVENT INTERRUPT

The output resulting from a Comparator 2 operation When Timer1 Gate Event Interrupt is enabled, it is
can be selected as a source for Timer1 gate control. possible to generate an interrupt upon the completion
The Comparator 2 output (sync_C2OUT) can be of a gate event. When the falling edge of T1GVAL
synchronized to the Timer1 clock or left asynchronous. occurs, the TMR1GIF flag bit in the PIR1 register will be
For more information see Section 18.4.1 “Comparator set. If the TMR1GIE bit in the PIE1 register is set, then
Output Synchronization”. an interrupt will be recognized.
The TMR1GIF flag bit operates even when the Timer1
21.6.3 TIMER1 GATE TOGGLE MODE gate is not enabled (TMR1GE bit is cleared).
When Timer1 Gate Toggle mode is enabled, it is possi-
ble to measure the full-cycle length of a Timer1 gate
signal, as opposed to the duration of a single level
pulse.
The Timer1 gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. See Figure 21-4 for timing details.

PIC16(L)F1933
21.7 Timer1 Interrupt 21.9 ECCP/CCP Capture/Compare Time
The Timer1 register pair (TMR1H:TMR1L) increments
Base
to FFFFh and rolls over to 0000h. When Timer1 rolls The CCP modules use the TMR1H:TMR1L register
over, the Timer1 interrupt flag bit of the PIR1 register is pair as the time base when operating in Capture or
set. To enable the interrupt on rollover, you must set Compare mode.
these bits:
In Capture mode, the value in the TMR1H:TMR1L
• TMR1ON bit of the T1CON register register pair is copied into the CCPR1H:CCPR1L
• TMR1IE bit of the PIE1 register register pair on a configured event.
• PEIE bit of the INTCON register In Compare mode, an event is triggered when the value
• GIE bit of the INTCON register CCPR1H:CCPR1L register pair matches the value in
The interrupt is cleared by clearing the TMR1IF bit in the TMR1H:TMR1L register pair. This event can be a
the Interrupt Service Routine. Special Event Trigger.
For more information, see Section 12.0 “I/O Ports”.
Note: The TMR1H:TMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts. 21.10 ECCP/CCP Special Event Trigger
When any of the CCP’s are configured to trigger a spe-
21.8 Timer1 Operation During Sleep cial event, the trigger will clear the TMR1H:TMR1L reg-
ister pair. This special event does not cause a Timer1
Timer1 can only operate during Sleep when setup in interrupt. The CCP module may still be configured to
Asynchronous Counter mode. In this mode, an external generate a CCP interrupt.
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device: In this mode of operation, the CCPR1H:CCPR1L
register pair becomes the period register for Timer1.
• TMR1ON bit of the T1CON register must be set
Timer1 should be synchronized and FOSC/4 should be
• TMR1IE bit of the PIE1 register must be set
selected as the clock source in order to utilize the
• PEIE bit of the INTCON register must be set Special Event Trigger. Asynchronous operation of
• T1SYNC bit of the T1CON register must be set Timer1 can cause a Special Event Trigger to be
• TMR1CS bits of the T1CON register must be missed.
configured In the event that a write to TMR1H or TMR1L coincides
• T1OSCEN bit of the T1CON register must be with a Special Event Trigger from the CCP, the write will
configured take precedence.
The device will wake-up on an overflow and execute For more information, see Section 15.2.5 “Special
the next instructions. If the GIE bit of the INTCON Event Trigger”.
register is set, the device will call the Interrupt Service
Routine.
Timer1 oscillator will continue to operate in Sleep
regardless of the T1SYNC bit setting.
FIGURE 21-2: TIMER1 INCREMENTING EDGE
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.

PIC16(L)F1933
FIGURE 21-3: TIMER1 GATE ENABLE MODE
TMR1GE
T1GPOL
t1g_in
T1CKI
T1GVAL
TIMER1 N N+1 N+2 N+3 N+4
FIGURE 21-4: TIMER1 GATE TOGGLE MODE
TMR1GE
T1GPOL
T1GTM
t1g_in
T1CKI
T1GVAL
TIMER1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8

PIC16(L)F1933
FIGURE 21-5: TIMER1 GATE SINGLE-PULSE MODE
TMR1GE
T1GPOL
T1GSPM
Cleared by hardware on
T1GGO/ Set by software falling edge of T1GVAL
DONE
Counting enabled on
rising edge of T1G
t1g_in
T1CKI
T1GVAL
TIMER1 N N+1 N+2
Cleared by
TMR1GIF Cleared by software Set by hardware on software
falling edge of T1GVAL

PIC16(L)F1933
FIGURE 21-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
TMR1GE
T1GPOL
T1GSPM
T1GTM
Cleared by hardware on
T1GGO/ Set by software falling edge of T1GVAL
DONE Counting enabled on
rising edge of T1G
t1g_in
T1CKI
T1GVAL
TIMER1 N N+1 N+2 N+3 N+4
Set by hardware on Cleared by

TMR1GIF Cleared by software falling edge of T1GVAL software

PIC16(L)F1933
21.11 Register Definitions: Timer1 Control
REGISTER 21-1: T1CON: TIMER1 CONTROL REGISTER

R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u U-0 R/W-0/u
TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON
bit 7 bit 0
Legend:
bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits

11 = Timer1 clock source is Capacitive Sensing Oscillator (CAPOSC)
10 = Timer1 clock source is pin or oscillator:
If T1OSCEN = 0:
External clock from T1CKI pin (on the rising edge)
If T1OSCEN = 1:
Crystal oscillator on T1OSI/T1OSO pins
01 = Timer1 clock source is system clock (FOSC)
00 = Timer1 clock source is instruction clock (FOSC/4)
bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
bit 3 T1OSCEN: LP Oscillator Enable Control bit
1 = Dedicated Timer1 oscillator circuit enabled
0 = Dedicated Timer1 oscillator circuit disabled
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS<1:0> = 1X
1 = Do not synchronize external clock input
0 = Synchronize external clock input with system clock (FOSC)
TMR1CS<1:0> = 0X
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1 and clears Timer1 gate flip-flop

PIC16(L)F1933
REGISTER 21-2: T1GCON: TIMER1 GATE CONTROL REGISTER

R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x R/W-0/u R/W-0/u
TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0>
DONE
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware
bit 7 TMR1GE: Timer1 Gate Enable bit

If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1 = Timer1 counting is controlled by the Timer1 gate function
0 = Timer1 counts regardless of Timer1 gate function
bit 6 T1GPOL: Timer1 Gate Polarity bit
1 = Timer1 gate is active-high (Timer1 counts when gate is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 5 T1GTM: Timer1 Gate Toggle Mode bit
1 = Timer1 Gate Toggle mode is enabled
0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4 T1GSPM: Timer1 Gate Single-Pulse Mode bit
1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate
0 = Timer1 Gate Single-Pulse mode is disabled
bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit
1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge
0 = Timer1 gate single-pulse acquisition has completed or has not been started
bit 2 T1GVAL: Timer1 Gate Current State bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.
Unaffected by Timer1 Gate Enable (TMR1GE).
bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits
11 = Comparator 2 optionally synchronized output (sync_C2OUT)
10 = Comparator 1 optionally synchronized output (sync_C1OUT)
01 = Timer0 overflow output
00 = Timer1 gate pin

PIC16(L)F1933
TABLE 21-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Register
on Page
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 179*
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 179*
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 184
DONE
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module.

PIC16(L)F1933
NOTES:

PIC16(L)F1933
22.0 TIMER2/4/6 MODULES
There are up to three identical Timer2-type modules
available. To maintain pre-existing naming conventions,
the Timers are called Timer2, Timer4 and Timer6 (also
Timer2/4/6).
Note: The ‘x’ variable used in this section is
used to designate Timer2, Timer4, or
Timer6. For example, TxCON references
T2CON, T4CON, or T6CON. PRx refer-
ences PR2, PR4, or PR6.
The Timer2/4/6 modules incorporate the following
features:
• 8-bit Timer and Period registers (TMRx and PRx,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16,
and 1:64)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMRx match with PRx, respectively
• Optional use as the shift clock for the MSSP
module (Timer2 only)
See Figure 22-1 for a block diagram of Timer2/4/6.
FIGURE 22-1: TIMER2/4/6 BLOCK DIAGRAM
Sets Flag
TMRx
bit TMRxIF
Output
Prescaler Reset
FOSC/4 TMRx
1:1, 1:4, 1:16, 1:64
2 Postscaler
Comparator
EQ 1:1 to 1:16
TxCKPS<1:0>
PRx 4
TxOUTPS<3:0>

PIC16(L)F1933
22.1 Timer2/4/6 Operation 22.3 Timer2/4/6 Output
The clock input to the Timer2/4/6 modules is the The unscaled output of TMRx is available primarily to
system instruction clock (FOSC/4). the CCP modules, where it is used as a time base for
TMRx increments from 00h on each clock edge. operations in PWM mode.
A 4-bit counter/prescaler on the clock input allows direct Timer2 can be optionally used as the shift clock source
input, divide-by-4 and divide-by-16 prescale options. for the MSSP module operating in SPI mode.
These options are selected by the prescaler control bits, Additional information is provided in Section 24.0
TxCKPS<1:0> of the TxCON register. The value of “Master Synchronous Serial Port Module”
TMRx is compared to that of the Period register, PRx, on
each clock cycle. When the two values match, the 22.4 Timer2/4/6 Operation During Sleep
comparator generates a match signal as the timer
The Timer2/4/6 timers cannot be operated while the
output. This signal also resets the value of TMRx to 00h
processor is in Sleep mode. The contents of the TMRx
on the next cycle and drives the output
and PRx registers will remain unchanged while the
counter/postscaler (see Section 22.2 “Timer2/4/6
processor is in Sleep mode.
Interrupt”).
The TMRx and PRx registers are both directly readable
and writable. The TMRx register is cleared on any
device Reset, whereas the PRx register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
• a write to the TMRx register
• a write to the TxCON register
• MCLR Reset
• Watchdog Timer (WDT) Reset
• Stack Overflow Reset
• Stack Underflow Reset
• RESET Instruction
Note: TMRx is not cleared when TxCON is
written.
22.2 Timer2/4/6 Interrupt

Timer2/4/6 can also generate an optional device
interrupt. The Timer2/4/6 output signal (TMRx-to-PRx
match) provides the input for the 4-bit
counter/postscaler. This counter generates the TMRx
match interrupt flag which is latched in TMRxIF of the
PIRx register. The interrupt is enabled by setting the
TMRx Match Interrupt Enable bit, TMRxIE, of the PIEx
register.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, TxOUTPS<3:0>, of the TxCON register.

PIC16(L)F1933
22.5 Register Definitions: Timer2/4/6 Control
REGISTER 22-1: TXCON: TIMER2/TIMER4/TIMER6 CONTROL REGISTER

— TxOUTPS<3:0> TMRxON TxCKPS<1:0>
bit 7 bit 0
Legend:

bit 6-3 TxOUTPS<3:0>: Timer Output Postscaler Select bits
1111 = 1:16 Postscaler
bit 2 TMRxON: Timerx On bit
1 = Timerx is on
0 = Timerx is off
bit 1-0 TxCKPS<1:0>: Timer2-type Clock Prescale Select bits
11 = Prescaler is 64
10 = Prescaler is 16
01 = Prescaler is 4
00 = Prescaler is 1

PIC16(L)F1933
TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2/4/6
Register
on Page
PR2 Timer2 Module Period Register 187*
T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 189
TMR2 Holding Register for the 8-bit TMR2 Register 187*
TMR4 Holding Register for the 8-bit TMR4 Register(1) 187*
TMR6 Holding Register for the 8-bit TMR6 Register(1) 187*
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module.

PIC16(L)F1933
23.0 CAPTURE/COMPARE/PWM
MODULES Note 1: In devices with more than one CCP
The Capture/Compare/PWM module is a peripheral module, it is very important to pay close
which allows the user to time and control different attention to the register names used. A
events, and to generate Pulse-Width Modulation number placed after the module acronym
(PWM) signals. In Capture mode, the peripheral allows is used to distinguish between separate
the timing of the duration of an event. The Compare modules. For example, the CCP1CON
mode allows the user to trigger an external event when and CCP2CON control the same
a predetermined amount of time has expired. The operational aspects of two completely
PWM mode can generate Pulse-Width Modulated different CCP modules.
signals of varying frequency and duty cycle. 2: Throughout this section, generic
This family of devices contains three Enhanced references to a CCP module in any of its
Capture/Compare/PWM modules (ECCP1, ECCP2, operating modes may be interpreted as
and ECCP3) and two standard Capture/Compare/PWM being equally applicable to ECCP1,
modules (CCP4 and CCP5). ECCP2, ECCP3, CCP4 and CCP5.
Register names, module signals, I/O pins,
The Capture and Compare functions are identical for all
and bit names may use the generic
five CCP modules (ECCP1, ECCP2, ECCP3, CCP4,
designator ‘x’ to indicate the use of a
and CCP5). The only differences between CCP
numeral to distinguish a particular module,
modules are in the Pulse-Width Modulation (PWM)
when required.
function. The standard PWM function is identical in
modules CCP4 and CCP5. In CCP modules ECCP1,
ECCP2 and ECCP3, the Enhanced PWM function has
slight variations from one another. Full-Bridge ECCP
modules have four available I/O pins while Half-Bridge
ECCP modules only have two available I/O pins. See
Table 23-1 for more information.
TABLE 23-1: PWM RESOURCES

Device Name ECCP1 ECCP2 ECCP3 CCP4 CCP5
Enhanced PWM Enhanced PWM Enhanced PWM
PIC16(L)F1933 Standard PWM Standard PWM
Full-Bridge Half-Bridge Half-Bridge

PIC16(L)F1933
23.1 Capture Mode 23.1.2 TIMER1 MODE RESOURCE
The Capture mode function described in this section is Timer1 must be running in Timer mode or Synchronized
available and identical for CCP modules ECCP1, Counter mode for the CCP module to use the capture
ECCP2, ECCP3, CCP4 and CCP5. feature. In Asynchronous Counter mode, the capture
operation may not work.
Capture mode makes use of the 16-bit Timer1
resource. When an event occurs on the CCPx pin, the See Section 21.0 “Timer1 Module with Gate Control”
16-bit CCPRxH:CCPRxL register pair captures and for more information on configuring Timer1.
stores the 16-bit value of the TMR1H:TMR1L register 23.1.3 SOFTWARE INTERRUPT MODE
pair, respectively. An event is defined as one of the
following and is configured by the CCPxM<3:0> bits of When the Capture mode is changed, a false capture
the CCPxCON register: interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit of the PIEx register clear to
• Every falling edge avoid false interrupts. Additionally, the user should
• Every rising edge clear the CCPxIF interrupt flag bit of the PIRx register
• Every 4th rising edge following any change in Operating mode.
• Every 16th rising edge
23.1.4 CCP PRESCALER
When a capture is made, the Interrupt Request Flag bit
There are four prescaler settings specified by the
CCPxIF of the PIRx register is set. The interrupt flag
CCPxM<3:0> bits of the CCPxCON register. Whenever
must be cleared in software. If another capture occurs
the CCP module is turned off, or the CCP module is not
before the value in the CCPRxH, CCPRxL register pair
in Capture mode, the prescaler counter is cleared. Any
is read, the old captured value is overwritten by the new
Reset will clear the prescaler counter.
captured value.
Switching from one capture prescaler to another does
Figure 23-1 shows a simplified diagram of the Capture
not clear the prescaler and may generate a false
operation.
interrupt. To avoid this unexpected operation, turn the
module off by clearing the CCPxCON register before
23.1.1 CCP PIN CONFIGURATION
changing the prescaler. Example 23-1 demonstrates
In Capture mode, the CCPx pin should be configured the code to perform this function.
as an input by setting the associated TRIS control bit.
Also, the CCPx pin function can be moved to EXAMPLE 23-1: CHANGING BETWEEN
alternative pins using the APFCON register. Refer to CAPTURE PRESCALERS
Section 12.1 “Alternate Pin Function” for more BANKSEL CCPxCON ;Set Bank bits to point
details. ;to CCPxCON
CLRF CCPxCON ;Turn CCP module off
Note: If the CCPx pin is configured as an output, MOVLW NEW_CAPT_PS ;Load the W reg with
a write to the port can cause a capture ;the new prescaler
condition. ;move value and CCP ON
MOVWF CCPxCON ;Load CCPxCON with this
FIGURE 23-1: CAPTURE MODE ;value
OPERATION BLOCK
DIAGRAM 23.1.5 CAPTURE DURING SLEEP
Set Flag bit CCPxIF Capture mode depends upon the Timer1 module for
Prescaler
(PIRx register) proper operation. There are two options for driving the
 1, 4, 16 Timer1 module in Capture mode. It can be driven by the
CCPx CCPRxH CCPRxL
instruction clock (FOSC/4), or by an external clock source.
pin
When Timer1 is clocked by FOSC/4, Timer1 will not
and Capture increment during Sleep. When the device wakes from
Edge Detect Enable
Sleep, Timer1 will continue from its previous state.
TMR1H TMR1L Capture mode will operate during Sleep when Timer1
CCPxM<3:0> is clocked by an external clock source.
System Clock (FOSC)

PIC16(L)F1933
23.1.6 ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see Section 12.1 “Alternate Pin Function” for
more information.
TABLE 23-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE

Register
on Page
CCPxCON PxM<1:0>(1) DCxB<1:0> CCPxM<3:0> 214
CCPRxL Capture/Compare/PWM Register x Low Byte (LSB) 192
CCPRxH Capture/Compare/PWM Register x High Byte (MSB) 192
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 179
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 179
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Capture mode.
Note 1: Applies to ECCP modules only.

PIC16(L)F1933
23.2 Compare Mode 23.2.2 TIMER1 MODE RESOURCE
The Compare mode function described in this section In Compare mode, Timer1 must be running in either
is available and identical for CCP modules ECCP1, Timer mode or Synchronized Counter mode. The
ECCP2, ECCP3, CCP4 and CCP5. compare operation may not work in Asynchronous
Counter mode.
Compare mode makes use of the 16-bit Timer1
resource. The 16-bit value of the CCPRxH:CCPRxL See Section 21.0 “Timer1 Module with Gate Control”
register pair is constantly compared against the 16-bit for more information on configuring Timer1.
value of the TMR1H:TMR1L register pair. When a Note: Clocking Timer1 from the system clock
match occurs, one of the following events can occur: (FOSC) should not be used in Compare
• Toggle the CCPx output mode. In order for Compare mode to
• Set the CCPx output recognize the trigger event on the CCPx
pin, TImer1 must be clocked from the
• Clear the CCPx output
instruction clock (FOSC/4) or from an
• Generate a Special Event Trigger external clock source.
• Generate a Software Interrupt
The action on the pin is based on the value of the 23.2.3 SOFTWARE INTERRUPT MODE
CCPxM<3:0> control bits of the CCPxCON register. At When Generate Software Interrupt mode is chosen
the same time, the interrupt flag CCPxIF bit is set. (CCPxM<3:0> = 1010), the CCPx module does not
All Compare modes can generate an interrupt. assert control of the CCPx pin (see the CCPxCON
register).
Figure 23-2 shows a simplified diagram of the
Compare operation.
23.2.4 SPECIAL EVENT TRIGGER
FIGURE 23-2: COMPARE MODE When Special Event Trigger mode is chosen
(CCPxM<3:0> = 1011), the CCPx module does the
OPERATION BLOCK
following:
DIAGRAM
• Resets Timer1
CCPxM<3:0>
Mode Select • Starts an ADC conversion if ADC is enabled
The CCPx module does not assert control of the CCPx
Set CCPxIF Interrupt Flag pin in this mode.
(PIRx)
CCPx 4
CCPRxH CCPRxL The Special Event Trigger output of the CCP occurs
Pin
immediately upon a match between the TMR1H,
Q S TMR1L register pair and the CCPRxH, CCPRxL
Output Comparator
R Logic Match register pair. The TMR1H, TMR1L register pair is not
TMR1H TMR1L
reset until the next rising edge of the Timer1 clock. The
TRIS Special Event Trigger output starts an A/D conversion
Output Enable
(if the A/D module is enabled). This allows the
Special Event Trigger CCPRxH, CCPRxL register pair to effectively provide a
16-bit programmable period register for Timer1.
23.2.1 CCP PIN CONFIGURATION TABLE 23-3: SPECIAL EVENT TRIGGER
The user must configure the CCPx pin as an output by Device CCPx/ECCPx
clearing the associated TRIS bit. PIC16(L)F1933 CCP5
Also, the CCPx pin function can be moved to Refer to Section 15.2.5 “Special Event Trigger”for
alternative pins using the APFCON register. Refer to more information.
Section 12.1 “Alternate Pin Function” for more
details. Note 1: The Special Event Trigger from the CCP
module does not set interrupt flag bit
Note: Clearing the CCPxCON register will force TMR1IF of the PIR1 register.
the CCPx compare output latch to the
default low level. This is not the PORT I/O 2: Removing the match condition by
data latch. changing the contents of the CCPRxH
and CCPRxL register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates the Timer1 Reset, will
preclude the Reset from occurring.

PIC16(L)F1933
23.2.5 COMPARE DURING SLEEP 23.2.6 ALTERNATE PIN LOCATIONS
The Compare mode is dependent upon the system This module incorporates I/O pins that can be moved to
clock (FOSC) for proper operation. Since FOSC is shut other locations with the use of the alternate pin function
down during Sleep mode, the Compare mode will not register, APFCON. To determine which pins can be
function properly during Sleep. moved and what their default locations are upon a
Reset, see Section 12.1 “Alternate Pin Function” for
more information.
TABLE 23-4: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE

Register
on Page
CCPRxL Capture/Compare/PWM Register x Low Byte (LSB) 192
CCPRxH Capture/Compare/PWM Register x High Byte (MSB) 192
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 179
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 179
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode.

PIC16(L)F1933
23.3 PWM Overview FIGURE 23-3: CCP PWM OUTPUT SIGNAL
Pulse-Width Modulation (PWM) is a scheme that Period
provides power to a load by switching quickly between
fully on and fully off states. The PWM signal resembles Pulse Width
TMRx = PRx
a square wave where the high portion of the signal is
considered the on state and the low portion of the signal TMRx = CCPRxH:CCPxCON<5:4>
is considered the off state. The high portion, also known
TMRx = 0
as the pulse width, can vary in time and is defined in
steps. A larger number of steps applied, which
lengthens the pulse width, also supplies more power to
the load. Lowering the number of steps applied, which
FIGURE 23-4: SIMPLIFIED PWM BLOCK
shortens the pulse width, supplies less power. The DIAGRAM
PWM period is defined as the duration of one complete CCPxCON<5:4>
cycle or the total amount of on and off time combined. Duty Cycle Registers
PWM resolution defines the maximum number of steps CCPRxL

that can be present in a single PWM period. A higher
resolution allows for more precise control of the pulse
width time and in turn the power that is applied to the
load. CCPRxH(2) (Slave)
CCPx
The term duty cycle describes the proportion of the on
time to the off time and is expressed in percentages, Comparator R Q
where 0% is fully off and 100% is fully on. A lower duty
cycle corresponds to less power applied and a higher (1) S
TMRx
duty cycle corresponds to more power applied. TRIS
Figure 23-3 shows a typical waveform of the PWM
signal. Comparator
Clear Timer,
toggle CCPx pin and
23.3.1 STANDARD PWM OPERATION PRx
latch duty cycle
The standard PWM function described in this section is

Note 1: The 8-bit timer TMRx register is concatenated
available and identical for CCP modules ECCP1,
with the 2-bit internal system clock (FOSC), or
ECCP2, ECCP3, CCP4 and CCP5. 2 bits of the prescaler, to create the 10-bit time
The standard PWM mode generates a Pulse-Width base.
Modulation (PWM) signal on the CCPx pin with up to 10 2: In PWM mode, CCPRxH is a read-only register.
bits of resolution. The period, duty cycle, and resolution
are controlled by the following registers:
• PRx registers
• TxCON registers
• CCPRxL registers
• CCPxCON registers
Figure 23-4 shows a simplified block diagram of PWM
operation.
Note 1: The corresponding TRIS bit must be

cleared to enable the PWM output on the
CCPx pin.
2: Clearing the CCPxCON register will
relinquish control of the CCPx pin.

PIC16(L)F1933
23.3.2 SETUP FOR PWM OPERATION When TMRx is equal to PRx, the following three events
occur on the next increment cycle:
The following steps should be taken when configuring
the CCP module for standard PWM operation: • TMRx is cleared
1. Disable the CCPx pin output driver by setting the • The CCPx pin is set. (Exception: If the PWM duty
associated TRIS bit. cycle = 0%, the pin will not be set.)
2. Load the PRx register with the PWM period • The PWM duty cycle is latched from CCPRxL into
value. CCPRxH.
3. Configure the CCP module for the PWM mode
by loading the CCPxCON register with the Note: The Timer postscaler (see Section 22.1
appropriate values. “Timer2/4/6 Operation”) is not used in the
determination of the PWM frequency.
4. Load the CCPRxL register and the DCxBx bits
of the CCPxCON register, with the PWM duty
23.3.5 PWM DUTY CYCLE
cycle value.
5. Configure and start Timer2/4/6: The PWM duty cycle is specified by writing a 10-bit
value to multiple registers: CCPRxL register and
• Select the Timer2/4/6 resource to be used
DCxB<1:0> bits of the CCPxCON register. The
for PWM generation by setting the
CCPRxL contains the eight MSbs and the DCxB<1:0>
CxTSEL<1:0> bits in the CCPTMRSx
bits of the CCPxCON register contain the two LSbs.
register.
CCPRxL and DCxB<1:0> bits of the CCPxCON
• Clear the TMRxIF interrupt flag bit of the register can be written to at any time. The duty cycle
PIRx register. See Note below. value is not latched into CCPRxH until after the period
• Configure the TxCKPS bits of the TxCON completes (i.e., a match between PRx and TMRx
register with the Timer prescale value. registers occurs). While using the PWM, the CCPRxH
• Enable the Timer by setting the TMRxON register is read-only.
bit of the TxCON register. Equation 23-2 is used to calculate the PWM pulse
6. Enable PWM output pin: width.
• Wait until the Timer overflows and the Equation 23-3 is used to calculate the PWM duty cycle
TMRxIF bit of the PIRx register is set. See ratio.
Note below.
• Enable the CCPx pin output driver by EQUATION 23-2: PULSE WIDTH
clearing the associated TRIS bit.
Note: In order to send a complete duty cycle and Pulse Width =  CCPRxL:CCPxCON<5:4>  
period on the first PWM output, the above
steps must be included in the setup T OSC  (TMRx Prescale Value)
sequence. If it is not critical to start with a
complete PWM signal on the first output,
then step 6 may be ignored. EQUATION 23-3: DUTY CYCLE RATIO
23.3.3 TIMER2/4/6 TIMER RESOURCE  CCPRxL:CCPxCON<5:4> 

Duty Cycle Ratio = -----------------------------------------------------------------------
The PWM standard mode makes use of one of the 8-bit 4  PRx + 1 
Timer2/4/6 timer resources to specify the PWM period.
Configuring the CxTSEL<1:0> bits in the CCPTMRSx The CCPRxH register and a 2-bit internal latch are
register selects which Timer2/4/6 timer is used. used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
23.3.4 PWM PERIOD The 8-bit timer TMRx register is concatenated with either
The PWM period is specified by the PRx register of the 2-bit internal system clock (FOSC), or 2 bits of the
Timer2/4/6. The PWM period can be calculated using prescaler, to create the 10-bit time base. The system
the formula of Equation 23-1. clock is used if the Timer2/4/6 prescaler is set to 1:1.
When the 10-bit time base matches the CCPRxH and
EQUATION 23-1: PWM PERIOD 2-bit latch, then the CCPx pin is cleared (see
Figure 23-4).
PWM Period =   PRx  + 1   4  T OSC 
(TMRx Prescale Value)
Note 1: TOSC = 1/FOSC

PIC16(L)F1933
23.3.6 PWM RESOLUTION EQUATION 23-4: PWM RESOLUTION
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolution log  4  PRx + 1  
Resolution = ------------------------------------------ bits
will result in 1024 discrete duty cycles, whereas an 8-bit log  2 
resolution will result in 256 discrete duty cycles.
The maximum PWM resolution is 10 bits when PRx is
255. The resolution is a function of the PRx register Note: If the pulse width value is greater than the
value as shown by Equation 23-4. period the assigned PWM pin(s) will
remain unchanged.
TABLE 23-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 32 MHz)

PWM Frequency 1.95 kHz 7.81 kHz 31.25 kHz 125 kHz 250 kHz 333.3 kHz
Timer Prescale 16 4 1 1 1 1
PRx Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 6.6

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
PRx Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 6.6

PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz
PRx Value 0x65 0x65 0x65 0x19 0x0C 0x09
Maximum Resolution (bits) 8 8 8 6 5 5

PIC16(L)F1933
23.3.7 OPERATION IN SLEEP MODE 23.3.10 ALTERNATE PIN LOCATIONS
In Sleep mode, the TMRx register will not increment This module incorporates I/O pins that can be moved to
and the state of the module will not change. If the CCPx other locations with the use of the alternate pin function
pin is driving a value, it will continue to drive that value. register, APFCON. To determine which pins can be
When the device wakes up, TMRx will continue from its moved and what their default locations are upon a
previous state. Reset, see Section 12.1 “Alternate Pin Function” for
more information.
23.3.8 CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 5.0 “Oscillator Module (with Fail-Safe
Clock Monitor)” for additional details.
23.3.9 EFFECTS OF RESET

Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
TABLE 23-8: SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM

Register
on Page
CCPTMRS0 C4TSEL<1:0> C3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> 215
CCPTMRS1 — — — — — — C5TSEL<1:0> 215
PRx Timer2/4/6 Period Register 187*
TxCON — TxOUTPS<3:0> TMRxON TxCKPS<:0>1 189
TMRx Timer2/4/6 Module Register 187
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.

PIC16(L)F1933
23.4 PWM (Enhanced Mode) To select an Enhanced PWM Output mode, the PxM bits
of the CCPxCON register must be configured
The enhanced PWM function described in this section is appropriately.
available for CCP modules ECCP1, ECCP2 and
ECCP3, with any differences between modules noted. The PWM outputs are multiplexed with I/O pins and are
designated PxA, PxB, PxC and PxD. The polarity of the
The enhanced PWM mode generates a Pulse-Width PWM pins is configurable and is selected by setting the
Modulation (PWM) signal on up to four different output CCPxM bits in the CCPxCON register appropriately.
pins with up to 10 bits of resolution. The period, duty
cycle, and resolution are controlled by the following Figure 23-5 shows an example of a simplified block
registers: diagram of the Enhanced PWM module.
• PRx registers Table 23-9 shows the pin assignments for various
Enhanced PWM modes.
• TxCON registers
• CCPRxL registers Note 1: The corresponding TRIS bit must be
• CCPxCON registers cleared to enable the PWM output on the
CCPx pin.
The ECCP modules have the following additional PWM
registers which control Auto-shutdown, Auto-restart, 2: Clearing the CCPxCON register will
Dead-band Delay and PWM Steering modes: relinquish control of the CCPx pin.
• CCPxAS registers 3: Any pin not used in the enhanced PWM

mode is available for alternate pin
• PSTRxCON registers
functions, if applicable.
• PWMxCON registers
4: To prevent the generation of an
The enhanced PWM module can generate the following incomplete waveform when the PWM is
five PWM Output modes: first enabled, the ECCP module waits
• Single PWM until the start of a new PWM period
• Half-Bridge PWM before generating a PWM signal.
• Full-Bridge PWM, Forward mode
• Full-Bridge PWM, Reverse mode
• Single PWM with PWM Steering mode
FIGURE 23-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE
DCxB<1:0> PxM<1:0> CCPxM<3:0>
Duty Cycle Registers
2 4
CCPRxL
CCPx/PxA CCPx/PxA
TRISx
CCPRxH (Slave)
PxB PxB
Output TRISx
Comparator R Q
Controller
PxC PxC
TMRx (1)
S TRISx
PxD PxD
Comparator
Clear Timer, TRISx
toggle PWM pin and
latch duty cycle
PRx PWMxCON
Note 1: The 8-bit timer TMRx register is concatenated with the 2-bit internal Q clock, or two bits of the prescaler to create the 10-bit time
base.

PIC16(L)F1933
TABLE 23-9: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES
ECCP Mode PxM<1:0> CCPx/PxA PxB PxC PxD
Single 00 Yes(1) Yes(1) Yes(1) Yes(1)
Half-Bridge 10 Yes Yes No No
Full-Bridge, Forward 01 Yes Yes Yes Yes
Full-Bridge, Reverse 11 Yes Yes Yes Yes
Note 1: PWM Steering enables outputs in Single mode.
FIGURE 23-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH

STATE)
Pulse PRX+1
PxM<1:0> Signal 0
Width
Period
00 (Single Output) PxA Modulated

Delay Delay
PxA Modulated
10 (Half-Bridge) PxB Modulated
PxA Active
(Full-Bridge, PxB Inactive

01 Forward)
PxC Inactive
PxD Modulated
PxA Inactive
(Full-Bridge, PxB Modulated

11
Reverse)
PxC Active
PxD Inactive
Relationships:
• Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)
• Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)
• Delay = 4 * TOSC * (PWMxCON<6:0>)

PIC16(L)F1933
FIGURE 23-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
Pulse PRx+1
PxM<1:0> Signal 0
Width
Period
00 (Single Output) PxA Modulated
PxA Modulated
Delay Delay
10 (Half-Bridge) PxB Modulated
PxA Active
(Full-Bridge, PxB Inactive

01 Forward)
PxC Inactive
PxD Modulated
PxA Inactive
(Full-Bridge, PxB Modulated

11
Reverse)
PxC Active
PxD Inactive
Relationships:
• Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)
• Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)
• Delay = 4 * TOSC * (PWMxCON<6:0>)

PIC16(L)F1933
23.4.1 HALF-BRIDGE MODE Since the PxA and PxB outputs are multiplexed with the
PORT data latches, the associated TRIS bits must be
In Half-Bridge mode, two pins are used as outputs to
cleared to configure PxA and PxB as outputs.
drive push-pull loads. The PWM output signal is output
on the CCPx/PxA pin, while the complementary PWM
output signal is output on the PxB pin (see FIGURE 23-8: EXAMPLE OF
Figure 23-9). This mode can be used for Half-Bridge HALF-BRIDGE PWM
applications, as shown in Figure 23-9, or for Full-Bridge OUTPUT
applications, where four power switches are being Period Period
modulated with two PWM signals.
Pulse Width
In Half-Bridge mode, the programmable dead-band delay
can be used to prevent shoot-through current in PxA(2)
Half-Bridge power devices. The value of the PDC<6:0> td
bits of the PWMxCON register sets the number of td
instruction cycles before the output is driven active. If the PxB(2)
value is greater than the duty cycle, the corresponding
output remains inactive during the entire cycle. See (1) (1) (1)
Section 23.4.5 “Programmable Dead-Band Delay
Mode” for more details of the dead-band delay td = Dead-Band Delay
operations. Note 1: At this time, the TMRx register is equal to the
PRx register.
2: Output signals are shown as active-high.
FIGURE 23-9: EXAMPLE OF HALF-BRIDGE APPLICATIONS
Standard Half-Bridge Circuit (“Push-Pull”)
FET
Driver +
PxA
-
Load
FET
Driver
+
PxB
-
Half-Bridge Output Driving a Full-Bridge Circuit
V+
FET FET
Driver Driver
PxA
Load
FET FET
Driver Driver
PxB

PIC16(L)F1933
23.4.2 FULL-BRIDGE MODE
In Full-Bridge mode, all four pins are used as outputs.
An example of Full-Bridge application is shown in
Figure 23-10.
In the Forward mode, pin CCPx/PxA is driven to its active
state, pin PxD is modulated, while PxB and PxC will be
driven to their inactive state as shown in Figure 23-11.
In the Reverse mode, PxC is driven to its active state, pin
PxB is modulated, while PxA and PxD will be driven to
their inactive state as shown Figure 23-11.
PxA, PxB, PxC and PxD outputs are multiplexed with
the PORT data latches. The associated TRIS bits must
be cleared to configure the PxA, PxB, PxC and PxD
pins as outputs.
FIGURE 23-10: EXAMPLE OF FULL-BRIDGE APPLICATION

V+
FET QA QC FET
Driver Driver
PxA
Load
PxB
FET FET
Driver Driver
PxC
QB QD
V-
PxD

PIC16(L)F1933
FIGURE 23-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT
Forward Mode
Period
(2)
PxA
Pulse Width
PxB(2)
PxC(2)
PxD(2)
(1) (1)
Reverse Mode
Period
Pulse Width
PxA(2)
PxB(2)
PxC(2)
PxD(2)
(1) (1)
Note 1: At this time, the TMRx register is equal to the PRx register.
2: Output signal is shown as active-high.

PIC16(L)F1933
23.4.2.1 Direction Change in Full-Bridge The Full-Bridge mode does not provide dead-band
Mode delay. As one output is modulated at a time, dead-band
delay is generally not required. There is a situation
In the Full-Bridge mode, the PxM1 bit in the CCPxCON
where dead-band delay is required. This situation
register allows users to control the forward/reverse
occurs when both of the following conditions are true:
direction. When the application firmware changes this
direction control bit, the module will change to the new 1. The direction of the PWM output changes when
direction on the next PWM cycle. the duty cycle of the output is at or near 100%.
A direction change is initiated in software by changing 2. The turn off time of the power switch, including
the PxM1 bit of the CCPxCON register. The following the power device and driver circuit, is greater
sequence occurs four Timer cycles prior to the end of than the turn on time.
the current PWM period: Figure 23-13 shows an example of the PWM direction
• The modulated outputs (PxB and PxD) are placed changing from forward to reverse, at a near 100% duty
in their inactive state. cycle. In this example, at time t1, the output PxA and
PxD become inactive, while output PxC becomes
• The associated unmodulated outputs (PxA and
active. Since the turn-off time of the power devices is
PxC) are switched to drive in the opposite
longer than the turn-on time, a shoot-through current
direction.
will flow through power devices QC and QD (see
• PWM modulation resumes at the beginning of the Figure 23-10) for the duration of ‘t’. The same
next period. phenomenon will occur to power devices QA and QB
See Figure 23-12 for an illustration of this sequence. for PWM direction change from reverse to forward.
If changing PWM direction at high duty cycle is required
for an application, two possible solutions for eliminating
the shoot-through current are:
1. Reduce PWM duty cycle for one PWM period
before changing directions.
2. Use switch drivers that can drive the switches off
faster than they can drive them on.
Other options to prevent shoot-through current may
exist.
FIGURE 23-12: EXAMPLE OF PWM DIRECTION CHANGE
Signal Period(1) Period
PxA (Active-High)
PxB (Active-High)
Pulse Width
PxC (Active-High)
(2)
PxD (Active-High)
Pulse Width
Note 1: The direction bit PxM1 of the CCPxCON register is written any time during the PWM cycle.
2: When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The
modulated PxB and PxD signals are inactive at this time. The length of this time is four Timer counts.

PIC16(L)F1933
FIGURE 23-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
Forward Period t1 Reverse Period
PxA
PxB
PW
PxC
PxD PW
TON
External Switch C
TOFF
External Switch D
Potential T = TOFF – TON

Shoot-Through Current
Note 1: All signals are shown as active-high.

2: TON is the turn-on delay of power switch QC and its driver.
3: TOFF is the turn-off delay of power switch QD and its driver.

PIC16(L)F1933
23.4.3 ENHANCED PWM
AUTO-SHUTDOWN MODE Note 1: The auto-shutdown condition is a
The PWM mode supports an Auto-Shutdown mode that level-based signal, not an edge-based
will disable the PWM outputs when an external signal. As long as the level is present, the
shutdown event occurs. Auto-Shutdown mode places auto-shutdown will persist.
the PWM output pins into a predetermined state. This 2: Writing to the CCPxASE bit is disabled
mode is used to help prevent the PWM from damaging while an auto-shutdown condition
the application. persists.
The auto-shutdown sources are selected using the 3: Once the auto-shutdown condition has
CCPxAS<2:0> bits of the CCPxAS register. A shutdown been removed and the PWM restarted
event may be generated by: (either through firmware or auto-restart)
• A logic ‘0’ on the INT pin the PWM signal will always restart at the
• A logic ‘1’ on a Comparator (Cx) output beginning of the next PWM period.
A shutdown condition is indicated by the CCPxASE 4: Prior to an auto-shutdown event caused
(Auto-Shutdown Event Status) bit of the CCPxAS by a comparator output or INT pin event,
register. If the bit is a ‘0’, the PWM pins are operating a software shutdown can be triggered in
normally. If the bit is a ‘1’, the PWM outputs are in the firmware by setting the CCPxASE bit of
shutdown state. the CCPxAS register to ‘1’. The
Auto-Restart feature tracks the active
When a shutdown event occurs, two things happen:
status of a shutdown caused by a
The CCPxASE bit is set to ‘1’. The CCPxASE will comparator output or INT pin event only.
remain set until cleared in firmware or an auto-restart If it is enabled at this time, it will immedi-
occurs (see Section 23.4.4 “Auto-Restart Mode”). ately clear this bit and restart the ECCP
The enabled PWM pins are asynchronously placed in module at the beginning of the next PWM
their shutdown states. The PWM output pins are period.
grouped into pairs [PxA/PxC] and [PxB/PxD]. The state
of each pin pair is determined by the PSSxAC and
PSSxBD bits of the CCPxAS register. Each pin pair may
be placed into one of three states:
• Drive logic ‘1’
• Drive logic ‘0’
• Tri-state (high-impedance)
FIGURE 23-14: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PXRSEN = 0)
Missing Pulse Missing Pulse

(Auto-Shutdown) (CCPxASE not clear)
Timer Timer Timer Timer Timer
Overflow Overflow Overflow Overflow Overflow
PWM Period
PWM Activity
Start of
PWM Period
Shutdown Event
CCPxASE bit
PWM
Shutdown Shutdown Resumes
Event Occurs Event Clears CCPxASE
Cleared by
Firmware

PIC16(L)F1933
23.4.4 AUTO-RESTART MODE
The Enhanced PWM can be configured to automati-
cally restart the PWM signal once the auto-shutdown
condition has been removed. Auto-restart is enabled by
setting the PxRSEN bit in the PWMxCON register.
If auto-restart is enabled, the CCPxASE bit will remain
set as long as the auto-shutdown condition is active.
When the auto-shutdown condition is removed, the
CCPxASE bit will be cleared via hardware and normal
operation will resume.
FIGURE 23-15: PWM AUTO-SHUTDOWN WITH AUTO-RESTART (PXRSEN = 1)

Missing Pulse Missing Pulse
(Auto-Shutdown) (CCPxASE not clear)
Timer Timer Timer Timer Timer
Overflow Overflow Overflow Overflow Overflow
PWM Period
PWM Activity
Start of
PWM Period
Shutdown Event
CCPxASE bit
PWM
Shutdown Resumes
Event Occurs
Shutdown CCPxASE
Event Clears Cleared by
Hardware

PIC16(L)F1933
23.4.5 PROGRAMMABLE DEAD-BAND FIGURE 23-16: EXAMPLE OF
DELAY MODE HALF-BRIDGE PWM
In half-bridge applications where all power switches are OUTPUT
modulated at the PWM frequency, the power switches Period Period
normally require more time to turn off than to turn on. If
both the upper and lower power switches are switched Pulse Width
at the same time (one turned on, and the other turned PxA(2)
off), both switches may be on for a short period of time td
until one switch completely turns off. During this brief
td
interval, a very high current (shoot-through current) will PxB(2)
flow through both power switches, shorting the bridge
supply. To avoid this potentially destructive (1) (1) (1)
shoot-through current from flowing during switching,
turning on either of the power switches is normally td = Dead-Band Delay
delayed to allow the other switch to completely turn off.
In Half-Bridge mode, a digitally programmable Note 1: At this time, the TMRx register is equal to the
dead-band delay is available to avoid shoot-through PRx register.
current from destroying the bridge power switches. The 2: Output signals are shown as active-high.
delay occurs at the signal transition from the non-active
state to the active state. See Figure 23-16 for
illustration. The lower seven bits of the associated
PWMxCON register (Register 23-5) sets the delay
period in terms of microcontroller instruction cycles
(TCY or 4 TOSC).
FIGURE 23-17: EXAMPLE OF HALF-BRIDGE APPLICATIONS

V+
Standard Half-Bridge Circuit (“Push-Pull”)
FET
Driver +
PxA V
-
Load
FET
Driver
+
PxB V
-
V-

PIC16(L)F1933
23.4.6 PWM STEERING MODE
In Single Output mode, PWM steering allows any of the
PWM pins to be the modulated signal. Additionally, the
same PWM signal can be simultaneously available on
multiple pins.
Once the Single Output mode is selected
(CCPxM<3:2> = 11 and PxM<1:0> = 00 of the
CCPxCON register), the user firmware can bring out
the same PWM signal to one, two, three or four output
pins by setting the appropriate STRx<D:A> bits of the
PSTRxCON register, as shown in Table 23-9.
Note: The associated TRIS bits must be set to

output (‘0’) to enable the pin output driver
in order to see the PWM signal on the pin.
While the PWM Steering mode is active, CCPxM<1:0>
bits of the CCPxCON register select the PWM output
polarity for the Px<D:A> pins.
The PWM auto-shutdown operation also applies to
PWM Steering mode as described in Section 23.4.3
“Enhanced PWM Auto-Shutdown mode”. An
auto-shutdown event will only affect pins that have
PWM outputs enabled.
FIGURE 23-18: SIMPLIFIED STEERING

BLOCK DIAGRAM
STRxA
PxA Signal PxA pin

CCPxM1 1
PORT Data
0
TRIS
STRxB
CCPxM0 1 PxB pin
PORT Data 0
TRIS
STRxC
1 PxC pin
CCPxM1
PORT Data 0
TRIS
STRxD
CCPxM0 1 PxD pin
PORT Data 0
TRIS
Note 1: Port outputs are configured as shown when

the CCPxCON register bits PxM<1:0> = 00
and CCPxM<3:2> = 11.
2: Single PWM output requires setting at least
one of the STRx bits.

PIC16(L)F1933
23.4.6.1 Steering Synchronization drivers are enabled. Changing the polarity
configuration while the PWM pin output drivers are
The STRxSYNC bit of the PSTRxCON register gives
enable is not recommended since it may result in
the user two selections of when the steering event will
damage to the application circuits.
happen. When the STRxSYNC bit is ‘0’, the steering
event will happen at the end of the instruction that The PxA, PxB, PxC and PxD output latches may not be
writes to the PSTRxCON register. In this case, the in the proper states when the PWM module is
output signal at the Px<D:A> pins may be an initialized. Enabling the PWM pin output drivers at the
incomplete PWM waveform. This operation is useful same time as the Enhanced PWM modes may cause
when the user firmware needs to immediately remove damage to the application circuit. The Enhanced PWM
a PWM signal from the pin. modes must be enabled in the proper Output mode and
complete a full PWM cycle before enabling the PWM
When the STRxSYNC bit is ‘1’, the effective steering
pin output drivers. The completion of a full PWM cycle
update will happen at the beginning of the next PWM
is indicated by the TMRxIF bit of the PIRx register
period. In this case, steering on/off the PWM output will
being set as the second PWM period begins.
always produce a complete PWM waveform.
Figures 23-19 and 23-20 illustrate the timing diagrams Note: When the microcontroller is released from
of the PWM steering depending on the STRxSYNC Reset, all of the I/O pins are in the
setting. high-impedance state. The external cir-
cuits must keep the power switch devices
23.4.7 START-UP CONSIDERATIONS in the Off state until the microcontroller
drives the I/O pins with the proper signal
When any PWM mode is used, the application
levels or activates the PWM output(s).
hardware must use the proper external pull-up and/or
pull-down resistors on the PWM output pins.
The CCPxM<1:0> bits of the CCPxCON register allow
the user to choose whether the PWM output signals are
active-high or active-low for each pair of PWM output
pins (PxA/PxC and PxB/PxD). The PWM output
polarities must be selected before the PWM pin output
FIGURE 23-19: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRxSYNC = 0)
PWM Period
PWM
STRx
P1<D:A> PORT Data PORT Data
P1n = PWM
FIGURE 23-20: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION

(STRxSYNC = 1)
PWM
STRx
P1<D:A> PORT Data PORT Data
P1n = PWM

PIC16(L)F1933
TABLE 23-10: SUMMARY OF REGISTERS ASSOCIATED WITH ENHANCED PWM
Register
on Page
CCPxAS CCPxASE CCPxAS<2:0> PSSxAC<1:0> PSSxBD<1:0> 216
CCPTMRS0 C4TSEL<1:0> C3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> 215
CCPTMRS1 — — — — — — C5TSEL<1:0> 215
PRx Timer2/4/6 Period Register 187*
PSTRxCON — — — STRxSYNC STRxD STRxC STRxB STRxA 218
PWMxCON PxRSEN PxDC<6:0> 217
TxCON — TxOUTPS<3:0> TMRxON TxCKPS<:0>1 189
TMRx Timer2/4/6 Module Register 187
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.

PIC16(L)F1933
23.5 CCP Control Register
REGISTER 23-1: CCPxCON: CCPx CONTROL REGISTER
R/W-00 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
(1)
PxM<1:0> DCxB<1:0> CCPxM<3:0>
bit 7 bit 0
Legend:
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset
bit 7-6 PxM<1:0>: Enhanced PWM Output Configuration bits(1)

Capture mode:
Unused
Compare mode:
Unused
If CCPxM<3:2> = 00, 01, 10:
xx = PxA assigned as Capture/Compare input; PxB, PxC, PxD assigned as port pins
If CCPxM<3:2> = 11:
11 = Full-Bridge output reverse; PxB modulated; PxC active; PxA, PxD inactive
10 = Half-Bridge output; PxA, PxB modulated with dead-band control; PxC, PxD assigned as port pins
01 = Full-Bridge output forward; PxD modulated; PxA active; PxB, PxC inactive
00 = Single output; PxA modulated; PxB, PxC, PxD assigned as port pins
bit 5-4 DCxB<1:0>: PWM Duty Cycle Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0 CCPxM<3:0>: ECCPx Mode Select bits
1011 = Compare mode: Special Event Trigger (ECCPx resets Timer, sets CCPxIF bit starts A/D conversion if A/D
module is enabled)(1)
1010 = Compare mode: generate software interrupt only; ECCPx pin reverts to I/O state
1001 = Compare mode: initialize ECCPx pin high; clear output on compare match (set CCPxIF)
1000 = Compare mode: initialize ECCPx pin low; set output on compare match (set CCPxIF)
0111 = Capture mode: every 16th rising edge

0110 = Capture mode: every 4th rising edge
0101 = Capture mode: every rising edge
0100 = Capture mode: every falling edge
0011 = Reserved
0010 = Compare mode: toggle output on match
0001 = Reserved
0000 = Capture/Compare/PWM off (resets ECCPx module)
CCP4/CCP5 only:
11xx = PWM mode
ECCP1/ECCP2/ECCP3 only:
1111 = PWM mode: PxA, PxC active-low; PxB, PxD active-low
1110 = PWM mode: PxA, PxC active-low; PxB, PxD active-high
1101 = PWM mode: PxA, PxC active-high; PxB, PxD active-low
1100 = PWM mode: PxA, PxC active-high; PxB, PxD active-high
Note 1: This function is available on the CCP module(s) listed in Table 23-3.

PIC16(L)F1933
REGISTER 23-2: CCPTMRS0: PWM TIMER SELECTION CONTROL REGISTER 0

C4TSEL<1:0> C3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0>
bit 7 bit 0
Legend:
bit 7-6 C4TSEL<1:0>: CCP4 Timer Selection

11 = Reserved
10 = CCP4 is based off Timer6 in PWM mode
11 = Reserved
11 = Reserved
11 = Reserved
REGISTER 23-3: CCPTMRS1: PWM TIMER SELECTION CONTROL REGISTER 1

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0
— — — — — — C5TSEL<1:0>
bit 7 bit 0
Legend:

bit 1-0 C5TSEL<1:0>: CCP5 Timer Selection bits
11 = Reserved

PIC16(L)F1933
REGISTER 23-4: CCPxAS: CCPX AUTO-SHUTDOWN CONTROL REGISTER

CCPxASE CCPxAS<2:0> PSSxAC<1:0> PSSxBD<1:0>
bit 7 bit 0
Legend:
bit 7 CCPxASE: CCPx Auto-Shutdown Event Status bit

1 = A shutdown event has occurred; CCPx outputs are in shutdown state
0 = CCPx outputs are operating
bit 6-4 CCxPAS<2:0>: CCPx Auto-Shutdown Source Select bits
111 = VIL on INT pin or Comparator C1 or Comparator C2 high(1)
110 = VIL on INT pin or Comparator C2 high(1)
101 = VIL on INT pin or Comparator C1 high(1)
100 = VIL on INT pin
011 = Either Comparator C1 or C2 high(1)
010 = Comparator C2 output high(1)
001 = Comparator C1 output high(1)
000 = Auto-shutdown is disabled
bit 3-2 PSSxAC<1:0>: Pins PxA and PxC Shutdown State Control bits
1x = Pins PxA and PxC tri-state
01 = Drive pins PxA and PxC to ‘1’
00 = Drive pins PxA and PxC to ‘0’
bit 1-0 PSSxBD<1:0>: Pins PxB and PxD Shutdown State Control bits
1x = Pins PxB and PxD tri-state
01 = Drive pins PxB and PxD to ‘1’
00 = Drive pins PxB and PxD to ‘0’
Note 1: If CxSYNC is enabled, the shutdown will be delayed by Timer1.

PIC16(L)F1933
REGISTER 23-5: PWMxCON: ENHANCED PWM CONTROL REGISTER

PxRSEN PxDC<6:0>
bit 7 bit 0
Legend:
bit 7 PxRSEN: PWM Restart Enable bit

1 = Upon auto-shutdown, the CCPxASE bit clears automatically once the shutdown event goes away;
the PWM restarts automatically
0 = Upon auto-shutdown, CCPxASE must be cleared in software to restart the PWM
bit 6-0 PxDC<6:0>: PWM Delay Count bits
PxDCx = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal
should transition active and the actual time it transitions active
Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe
mode is enabled.

PIC16(L)F1933
REGISTER 23-6: PSTRxCON: PWM STEERING CONTROL REGISTER(1)

U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1
— — — STRxSYNC STRxD STRxC STRxB STRxA
bit 7 bit 0
Legend:

bit 4 STRxSYNC: Steering Sync bit
1 = Output steering update occurs on next PWM period
0 = Output steering update occurs at the beginning of the instruction cycle boundary
bit 3 STRxD: Steering Enable bit D
1 = PxD pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxD pin is assigned to port pin
bit 2 STRxC: Steering Enable bit C
1 = PxC pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxC pin is assigned to port pin
bit 1 STRxB: Steering Enable bit B
1 = PxB pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxB pin is assigned to port pin
bit 0 STRxA: Steering Enable bit A
1 = PxA pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxA pin is assigned to port pin
Note 1: The PWM Steering mode is available only when the CCPxCON register bits CCPxM<3:2> = 11 and
PxM<1:0> = 00.

PIC16(L)F1933
24.0 MASTER SYNCHRONOUS
SERIAL PORT MODULE
24.1 Master SSP (MSSP) Module

Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C™)
The SPI interface supports the following modes and
features:
• Master mode
• Slave mode
• Clock Parity
• Slave Select Synchronization (Slave mode only)
• Daisy-chain connection of slave devices
Figure 24-1 is a block diagram of the SPI Interface
module.
FIGURE 24-1: MSSP BLOCK DIAGRAM (SPI MODE)
Data Bus
Read Write
SSPBUF Reg
SDI
SSPSR Reg
SDO bit 0 Shift
Clock
SS SS Control 2 (CKP, CKE)

Enable Clock Select
Edge
Select
SSPM<3:0>
4
( TMR22Output )
SCK
Edge Prescaler TOSC
Select 4, 16, 64
Baud Rate
Generator
TRIS bit (SSPADD)

PIC16(L)F1933
The I2C interface supports the following modes and
features:
• Master mode
• Slave mode
• Byte NACKing (Slave mode)
• Limited Multi-master support
• 7-bit and 10-bit addressing
• Start and Stop interrupts
• Interrupt masking
• Clock stretching
• Bus collision detection
• General call address matching
• Address masking
• Address Hold and Data Hold modes
• Selectable SDA hold times
Figure 24-2 is a block diagram of the I2C Interface
module in Master mode. Figure 24-3 is a diagram of the
I2C Interface module in Slave mode.
FIGURE 24-2: MSSP BLOCK DIAGRAM (I2C™ MASTER MODE)
Internal
Data Bus [SSPM 3:0]
Read Write
SSPBUF Baud Rate

Generator
(SSPADD)
SDA Shift
SDA in Clock
Clock arbitrate/BCOL detect

SSPSR
Clock Cntl
(Hold off clock source)

MSb LSb
Receive Enable (RCEN)
Start bit, Stop bit,

Acknowledge
Generate (SSPCON2)
SCL
Start bit detect,

Stop bit detect
SCL in Write collision detect Set/Reset: S, P, SSPSTAT, WCOL, SSPOV
Clock arbitration Reset SEN, PEN (SSPCON2)
Bus Collision State counter for Set SSPIF, BCLIF
end of XMIT/RCV
Address Match detect

PIC16(L)F1933
FIGURE 24-3: MSSP BLOCK DIAGRAM (I2C™ SLAVE MODE)
Internal
Data Bus
Read Write
SCL SSPBUF Reg
Shift
Clock
SSPSR Reg
SDA MSb LSb
SSPMSK Reg
Match Detect Addr Match
SSPADD Reg
Start and Set, Reset

Stop bit Detect S, P bits
(SSPSTAT Reg)

PIC16(L)F1933
24.2 SPI Mode Overview During each SPI clock cycle, a full-duplex data
transmission occurs. This means that while the master
The Serial Peripheral Interface (SPI) bus is a device is sending out the MSb from its shift register (on
synchronous serial data communication bus that its SDO pin) and the slave device is reading this bit and
operates in Full-Duplex mode. Devices communicate saving it as the LSb of its shift register, that the slave
in a master/slave environment where the master device device is also sending out the MSb from its shift register
initiates the communication. A slave device is (on its SDO pin) and the master device is reading this
controlled through a Chip Select known as Slave bit and saving it as the LSb of its shift register.
Select.
After eight bits have been shifted out, the master and
The SPI bus specifies four signal connections: slave have exchanged register values.
• Serial Clock (SCK) If there is more data to exchange, the shift registers are
• Serial Data Out (SDO) loaded with new data and the process repeats itself.
• Serial Data In (SDI) Whether the data is meaningful or not (dummy data),
• Slave Select (SS) depends on the application software. This leads to
Figure 24-1 shows the block diagram of the MSSP three scenarios for data transmission:
module when operating in SPI Mode. • Master sends useful data and slave sends dummy
The SPI bus operates with a single master device and data.
one or more slave devices. When multiple slave • Master sends useful data and slave sends useful
devices are used, an independent Slave Select data.
connection is required from the master device to each • Master sends dummy data and slave sends useful
slave device. data.
Figure 24-4 shows a typical connection between a Transmissions may involve any number of clock
master device and multiple slave devices. cycles. When there is no more data to be transmitted,
The master selects only one slave at a time. Most slave the master stops sending the clock signal and it
devices have tri-state outputs so their output signal deselects the slave.
appears disconnected from the bus when they are not Every slave device connected to the bus that has not
selected. been selected through its slave select line must
Transmissions involve two shift registers, eight bits in disregard the clock and transmission signals and must
size, one in the master and one in the slave. With either not transmit out any data of its own.
the master or the slave device, data is always shifted
out one bit at a time, with the Most Significant bit (MSb)
shifted out first. At the same time, a new Least
Significant bit (LSb) is shifted into the same register.
Figure 24-5 shows a typical connection between two
processors configured as master and slave devices.
Data is shifted out of both shift registers on the
programmed clock edge and latched on the opposite
edge of the clock.
The master device transmits information out on its SDO
output pin which is connected to, and received by, the
slave’s SDI input pin. The slave device transmits
information out on its SDO output pin, which is
connected to, and received by, the master’s SDI input
pin.
To begin communication, the master device first sends
out the clock signal. Both the master and the slave
devices should be configured for the same clock
polarity.
The master device starts a transmission by sending out
the MSb from its shift register. The slave device reads
this bit from that same line and saves it into the LSb
position of its shift register.

PIC16(L)F1933
FIGURE 24-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION
SCK SCK
SPI Master
SDO SDI SPI Slave
SDI SDO #1
General I/O SS
General I/O
General I/O SCK
SDI SPI Slave
SDO #2
SS
SCK
SDI SPI Slave
SDO #3
SS
24.2.1 SPI MODE REGISTERS

The MSSP module has five registers for SPI mode
operation. These are:
• MSSP STATUS register (SSPSTAT)
• MSSP Control register 1 (SSPCON1)
• MSSP Control register 3 (SSPCON3)
• MSSP Data Buffer register (SSPBUF)
• MSSP Address register (SSPADD)
• MSSP Shift register (SSPSR)
(Not directly accessible)
SSPCON1 and SSPSTAT are the control and STATUS
registers in SPI mode operation. The SSPCON1 regis-
ter is readable and writable. The lower six bits of the
SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
In one SPI master mode, SSPADD can be loaded with
a value used in the Baud Rate Generator. More
information on the Baud Rate Generator is available in
Section 24.7 “Baud Rate Generator”.
SSPSR is the shift register used for shifting data in and
out. SSPBUF provides indirect access to the SSPSR
register. SSPBUF is the buffer register to which data
bytes are written, and from which data bytes are read.
In receive operations, SSPSR and SSPBUF together
create a buffered receiver. When SSPSR receives a
complete byte, it is transferred to SSPBUF and the
SSPIF interrupt is set.
During transmission, the SSPBUF is not buffered. A
write to SSPBUF will write to both SSPBUF and
SSPSR.

PIC16(L)F1933
24.2.2 SPI MODE OPERATION The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
When initializing the SPI, several options need to be
shifts the data in and out of the device, MSb first. The
specified. This is done by programming the appropriate
SSPBUF holds the data that was written to the SSPSR
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
until the received data is ready. Once the eight bits of
These control bits allow the following to be specified:
data have been received, that byte is moved to the
• Master mode (SCK is the clock output) SSPBUF register. Then, the Buffer Full Detect bit, BF
• Slave mode (SCK is the clock input) of the SSPSTAT register, and the interrupt flag bit,
• Clock Polarity (Idle state of SCK) SSPIF, are set. This double-buffering of the received
• Data Input Sample Phase (middle or end of data data (SSPBUF) allows the next byte to start reception
output time) before reading the data that was just received. Any
write to the SSPBUF register during
• Clock Edge (output data on rising/falling edge of
transmission/reception of data will be ignored and the
SCK)
write collision detect bit WCOL of the SSPCON1
• Clock Rate (Master mode only) register, will be set. User software must clear the
• Slave Select mode (Slave mode only) WCOL bit to allow the following write(s) to the SSPBUF
To enable the serial port, SSP Enable bit, SSPEN of the register to complete successfully.
SSPCON1 register, must be set. To reset or reconfig- When the application software is expecting to receive
ure SPI mode, clear the SSPEN bit, re-initialize the valid data, the SSPBUF should be read before the next
SSPCONx registers and then set the SSPEN bit. This byte of data to transfer is written to the SSPBUF. The
configures the SDI, SDO, SCK and SS pins as serial Buffer Full bit, BF of the SSPSTAT register, indicates
port pins. For the pins to behave as the serial port when SSPBUF has been loaded with the received data
function, some must have their data direction bits (in (transmission is complete). When the SSPBUF is read,
the TRIS register) appropriately programmed as the BF bit is cleared. This data may be irrelevant if the
follows: SPI is only a transmitter. Generally, the MSSP interrupt
• SDI must have corresponding TRIS bit set is used to determine when the transmission/reception
has completed. If the interrupt method is not going to
• SDO must have corresponding TRIS bit cleared
be used, then software polling can be done to ensure
• SCK (Master mode) must have corresponding that a write collision does not occur.
TRIS bit cleared
The SSPSR is not directly readable or writable and can
• SCK (Slave mode) must have corresponding
only be accessed by addressing the SSPBUF register.
TRIS bit set
Additionally, the SSPSTAT register indicates the
• SS must have corresponding TRIS bit set various Status conditions.
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
FIGURE 24-5: SPI MASTER/SLAVE CONNECTION
SPI Master SSPM<3:0> = 00xx SPI Slave SSPM<3:0> = 010x

= 1010 SDO SDI
Serial Input Buffer Serial Input Buffer

(BUF) (SSPBUF)
Shift Register SDI SDO Shift Register

(SSPSR) (SSPSR)
MSb LSb MSb LSb
Serial Clock
SCK SCK
Slave Select
General I/O SS
Processor 1 (optional) Processor 2

PIC16(L)F1933
24.2.3 SPI MASTER MODE The clock polarity is selected by appropriately
programming the CKP bit of the SSPCON1 register
The master can initiate the data transfer at any time
and the CKE bit of the SSPSTAT register. This then,
because it controls the SCK line. The master
would give waveforms for SPI communication as
determines when the slave (Processor 2, Figure 24-5)
shown in Figure 24-6, Figure 24-8, Figure 24-9 and
is to broadcast data by the software protocol.
Figure 24-10, where the MSB is transmitted first. In
In Master mode, the data is transmitted/received as Master mode, the SPI clock rate (bit rate) is user
soon as the SSPBUF register is written to. If the SPI is programmable to be one of the following:
only going to receive, the SDO output could be
• FOSC/4 (or TCY)
disabled (programmed as an input). The SSPSR
register will continue to shift in the signal present on the • FOSC/16 (or 4 * TCY)
SDI pin at the programmed clock rate. As each byte is • FOSC/64 (or 16 * TCY)
received, it will be loaded into the SSPBUF register as • Timer2 output/2
if a normal received byte (interrupts and Status bits • Fosc/(4 * (SSPADD + 1))
appropriately set).
Figure 24-6 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
FIGURE 24-6: SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
SCK Modes
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 0)

(CKE = 1)
SDI
(SMP = 0) bit 7 bit 0
Input
Sample
(SMP = 0)
SDI
(SMP = 1) bit 0
bit 7
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF

PIC16(L)F1933
24.2.4 SPI SLAVE MODE 24.2.5 SLAVE SELECT
In Slave mode, the data is transmitted and received as SYNCHRONIZATION
external clock pulses appear on SCK. When the last The Slave Select can also be used to synchronize com-
bit is latched, the SSPIF interrupt flag bit is set. munication. The Slave Select line is held high until the
Before enabling the module in SPI Slave mode, the clock master device is ready to communicate. When the
line must match the proper Idle state. The clock line can Slave Select line is pulled low, the slave knows that a
be observed by reading the SCK pin. The Idle state is new transmission is starting.
determined by the CKP bit of the SSPCON1 register. If the slave fails to receive the communication properly,
While in Slave mode, the external clock is supplied by it will be reset at the end of the transmission, when the
the external clock source on the SCK pin. This external Slave Select line returns to a high state. The slave is
clock must meet the minimum high and low times as then ready to receive a new transmission when the
specified in the Electrical Specifications. Slave Select line is pulled low again. If the Slave Select
line is not used, there is a risk that the slave will
While in Sleep mode, the slave can transmit/receive eventually become out of sync with the master. If the
data. The shift register is clocked from the SCK pin slave misses a bit, it will always be one bit off in future
input and when a byte is received, the device will transmissions. Use of the Slave Select line allows the
generate an interrupt. If enabled, the device will slave and master to align themselves at the beginning
wake-up from Sleep. of each transmission.
24.2.4.1 Daisy-Chain Configuration The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
The SPI bus can sometimes be connected in a
(SSPCON1<3:0> = 0100).
daisy-chain configuration. The first slave output is
connected to the second slave input, the second slave When the SS pin is low, transmission and reception are
output is connected to the third slave input, and so on. enabled and the SDO pin is driven.
The final slave output is connected to the master input. When the SS pin goes high, the SDO pin is no longer
Each slave sends out, during a second group of clock driven, even if in the middle of a transmitted byte and
pulses, an exact copy of what was received during the becomes a floating output. External pull-up/pull-down
first group of clock pulses. The whole chain acts as one resistors may be desirable depending on the
large communication shift register. The daisy-chain application.
feature only requires a single Slave Select line from the
master device. Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON1<3:0> =
Figure 24-7 shows the block diagram of a typical 0100), the SPI module will reset if the SS
daisy-chain connection when operating in SPI mode. pin is set to VDD.
In a daisy-chain configuration, only the most recent 2: When the SPI is used in Slave mode with
byte on the bus is required by the slave. Setting the CKE set; the user must enable SS pin
BOEN bit of the SSPCON3 register will enable writes control.
to the SSPBUF register, even if the previous byte has
not been read. This allows the software to ignore data 3: While operated in SPI Slave mode the
that may not apply to it. SMP bit of the SSPSTAT register must
remain clear.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.

PIC16(L)F1933
FIGURE 24-7: SPI DAISY-CHAIN CONNECTION
SCK SCK
SPI Master
SDO SDI SPI Slave
SDI SDO #1
General I/O SS
SCK
SDI SPI Slave
SDO #2
SS
SCK
SDI SPI Slave
SDO #3
SS
FIGURE 24-8: SLAVE SELECT SYNCHRONOUS WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
Shift register SSPSR
and bit count are reset
SSPBUF to
SSPSR
SDO bit 7 bit 6 bit 7 bit 6 bit 0
SDI bit 0
bit 7 bit 7
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF

PIC16(L)F1933
FIGURE 24-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
Valid
SDI
bit 7 bit 0
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
Write Collision
detection active
FIGURE 24-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
Valid
SDI
bit 7 bit 0
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
Write Collision
detection active

PIC16(L)F1933
24.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmission/recep-
In SPI Master mode, module clocks may be operating
tion will remain in that state until the device wakes. After
at a different speed than when in Full-Power mode; in
the device returns to Run mode, the module will resume
the case of the Sleep mode, all clocks are halted.
transmitting and receiving data.
Special care must be taken by the user when the MSSP
In SPI Slave mode, the SPI Transmit/Receive Shift
clock is much faster than the system clock.
register operates asynchronously to the device. This
In Slave mode, when MSSP interrupts are enabled, allows the device to be placed in Sleep mode and data
after the master completes sending data, an MSSP to be shifted into the SPI Transmit/Receive Shift
interrupt will wake the controller from Sleep. register. When all eight bits have been received, the
If an exit from Sleep mode is not desired, MSSP MSSP interrupt flag bit will be set and if enabled, will
interrupts should be disabled. wake the device.
TABLE 24-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION

Register
on Page
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 83
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 86
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register 223*
SSPCON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 271
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISB2 TRISC1 TRISC0 125
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.

PIC16(L)F1933
24.3 I2C Mode Overview FIGURE 24-11: I2C MASTER/SLAVE
CONNECTION
The Inter-Integrated Circuit Bus (I2C) is a multi-master
serial data communication bus. Devices communicate
in a master/slave environment where the master VDD
devices initiate the communication. A slave device is
controlled through addressing.
SCL SCL
The I2C bus specifies two signal connections:
VDD
• Serial Clock (SCL) Master Slave
• Serial Data (SDA)
Figure 24-2 and Figure 24-3 show the block diagram of SDA SDA
the MSSP module when operating in I2C mode.
Both the SCL and SDA connections are bidirectional
open-drain lines, each requiring pull-up resistors for the The Acknowledge bit (ACK) is an active-low signal,
supply voltage. Pulling the line to ground is considered
which holds the SDA line low to indicate to the transmit-
a logical zero and letting the line float is considered a ter that the slave device has received the transmitted
logical one. data and is ready to receive more.
Figure 24-11 shows a typical connection between two The transition of a data bit is always performed while
processors configured as master and slave devices.
the SCL line is held low. Transitions that occur while the
The I2C bus can operate with one or more master SCL line is held high are used to indicate Start and Stop
devices and one or more slave devices. bits.
There are four potential modes of operation for a given If the master intends to write to the slave, then it repeat-
device: edly sends out a byte of data, with the slave responding
• Master Transmit mode after each byte with an ACK bit. In this example, the
(master is transmitting data to a slave) master device is in Master Transmit mode and the
slave is in Slave Receive mode.
• Master Receive mode
(master is receiving data from a slave) If the master intends to read from the slave, then it
• Slave Transmit mode repeatedly receives a byte of data from the slave, and
(slave is transmitting data to a master) responds after each byte with an ACK bit. In this
example, the master device is in Master Receive mode
• Slave Receive mode
and the slave is Slave Transmit mode.
(slave is receiving data from the master)
On the last byte of data communicated, the master
To begin communication, a master device starts out in
device may end the transmission by sending a Stop bit.
Master Transmit mode. The master device sends out a
If the master device is in Receive mode, it sends the
Start bit followed by the address byte of the slave it
Stop bit in place of the last ACK bit. A Stop bit is
intends to communicate with. This is followed by a
indicated by a low-to-high transition of the SDA line
single Read/Write bit, which determines whether the
while the SCL line is held high.
master intends to transmit to or receive data from the
slave device. In some cases, the master may want to maintain
control of the bus and re-initiate another transmission.
If the requested slave exists on the bus, it will respond
If so, the master device may send another Start bit in
with an Acknowledge bit, otherwise known as an ACK.
place of the Stop bit or last ACK bit when it is in receive
The master then continues in either Transmit mode or
mode.
Receive mode and the slave continues in the
complement, either in Receive mode or Transmit The I2C bus specifies three message protocols;
mode, respectively. • Single message where a master writes data to a
A Start bit is indicated by a high-to-low transition of the slave.
SDA line while the SCL line is held high. Address and • Single message where a master reads data from
data bytes are sent out, Most Significant bit (MSb) first. a slave.
The Read/Write bit is sent out as a logical one when the • Combined message where a master initiates a
master intends to read data from the slave, and is sent minimum of two writes, or two reads, or a
out as a logical zero when it intends to write data to the combination of writes and reads, to one or more
slave. slaves.

PIC16(L)F1933
When one device is transmitting a logical one, or letting Slave Transmit mode can also be arbitrated, when a
the line float, and a second device is transmitting a master addresses multiple slaves, but this is less
logical zero, or holding the line low, the first device can common.
detect that the line is not a logical one. This detection, If two master devices are sending a message to two
when used on the SCL line, is called clock stretching. different slave devices at the address stage, the master
Clock stretching gives slave devices a mechanism to sending the lower slave address always wins arbitra-
control the flow of data. When this detection is used on tion. When two master devices send messages to the
the SDA line, it is called arbitration. Arbitration ensures same slave address, and addresses can sometimes
that there is only one master device communicating at refer to multiple slaves, the arbitration process must
any single time. continue into the data stage.
24.3.1 CLOCK STRETCHING Arbitration usually occurs very rarely, but it is a
necessary process for proper multi-master support.
When a slave device has not completed processing
data, it can delay the transfer of more data through the
process of clock stretching. An addressed slave device 24.4 I2C™ Mode Operation
may hold the SCL clock line low after receiving or send- All MSSP I2C communication is byte oriented and
ing a bit, indicating that it is not yet ready to continue. shifted out MSb first. Six SFR registers and two
The master that is communicating with the slave will interrupt flags interface the module with the PIC®
attempt to raise the SCL line in order to transfer the microcontroller and user software. Two pins, SDA and
next bit, but will detect that the clock line has not yet SCL, are exercised by the module to communicate
been released. Because the SCL connection is with other external I2C devices.
open-drain, the slave has the ability to hold that line low
until it is ready to continue communicating. 24.4.1 BYTE FORMAT
Clock stretching allows receivers that cannot keep up All communication in I2C is done in 9-bit segments. A
with a transmitter to control the flow of incoming data. byte is sent from a master to a slave or vice-versa,
followed by an Acknowledge bit sent back. After the
24.3.2 ARBITRATION 8th falling edge of the SCL line, the device outputting
Each master device must monitor the bus for Start and data on the SDA changes that pin to an input and
Stop bits. If the device detects that the bus is busy, it reads in an acknowledge value on the next clock
cannot begin a new message until the bus returns to an pulse.
Idle state. The clock signal, SCL, is provided by the master. Data
However, two master devices may try to initiate a is valid to change while the SCL signal is low, and
transmission on or about the same time. When this sampled on the rising edge of the clock. Changes on
occurs, the process of arbitration begins. Each the SDA line while the SCL line is high define special
transmitter checks the level of the SDA data line and conditions on the bus, explained below.
compares it to the level that it expects to find. The first
transmitter to observe that the two levels do not match, 24.4.2 DEFINITION OF I2C TERMINOLOGY
loses arbitration, and must stop transmitting on the There is language and terminology in the description of
SDA line. I2C communication that have definitions specific to I2C.
For example, if one transmitter holds the SDA line to a That word usage is defined below and may be used in
logical one (lets it float) and a second transmitter holds the rest of this document without explanation. This
it to a logical zero (pulls it low), the result is that the table was adapted from the Philips I2C specification.
SDA line will be low. The first transmitter then observes
that the level of the line is different than expected and 24.4.3 SDA AND SCL PINS
concludes that another transmitter is communicating. Selection of any I2C mode with the SSPEN bit set,
The first transmitter to notice this difference is the one forces the SCL and SDA pins to be open-drain. These
that loses arbitration and must stop driving the SDA pins should be set by the user to inputs by setting the
line. If this transmitter is also a master device, it also appropriate TRIS bits.
must stop driving the SCL line. It then can monitor the Note: Data is tied to output zero when an I2C
lines for a Stop condition before trying to reissue its mode is enabled.
transmission. In the meantime, the other device that
has not noticed any difference between the expected 24.4.4 SDA HOLD TIME
and actual levels on the SDA line continues with its
original transmission. It can do so without any compli- The hold time of the SDA pin is selected by the SDAHT
cations, because so far, the transmission appears bit of the SSPCON3 register. Hold time is the time SDA
exactly as expected with no other transmitter disturbing is held valid after the falling edge of SCL. Setting the
the message. SDAHT bit selects a longer 300 ns minimum hold time
and may help on buses with large capacitance.

PIC16(L)F1933
TABLE 24-2: I2C BUS TERMS 24.4.5 START CONDITION
2
TERM Description The I C specification defines a Start condition as a
Transmitter The device which shifts data out transition of SDA from a high to a low state while SCL
onto the bus. line is high. A Start condition is always generated by
the master and signifies the transition of the bus from
Receiver The device which shifts data in
an Idle to an Active state. Figure 24-12 shows wave
from the bus.
forms for Start and Stop conditions.
Master The device that initiates a transfer,
generates clock signals and A bus collision can occur on a Start condition if the
terminates a transfer. module samples the SDA line low before asserting it
low. This does not conform to the I2C specification that
Slave The device addressed by the
states no bus collision can occur on a Start.
master.
Multi-master A bus with more than one device 24.4.6 STOP CONDITION
that can initiate data transfers.
A Stop condition is a transition of the SDA line from
Arbitration Procedure to ensure that only one low-to-high state while the SCL line is high.
master at a time controls the bus.
Winning arbitration ensures that Note: At least one SCL low time must appear
the message is not corrupted. before a Stop is valid, therefore, if the SDA
Synchronization Procedure to synchronize the line goes low then high again while the SCL
clocks of two or more devices on line stays high, only the Start condition is
the bus. detected.
Idle No master is controlling the bus,
and both SDA and SCL lines are 24.4.7 RESTART CONDITION
high. A Restart is valid any time that a Stop would be valid.
Active Any time one or more master A master can issue a Restart if it wishes to hold the
devices are controlling the bus. bus after terminating the current transfer. A Restart
Addressed Slave device that has received a has the same effect on the slave that a Start would,
Slave matching address and is actively resetting all slave logic and preparing it to clock in an
being clocked by a master. address. The master may want to address the same or
another slave. Figure 24-13 shows the wave form for a
Matching Address byte that is clocked into a
Restart condition.
Address slave that matches the value
stored in SSPADD. In 10-bit Addressing Slave mode a Restart is required
Write Request Slave receives a matching for the master to clock data out of the addressed
address with R/W bit clear, and is slave. Once a slave has been fully addressed, match-
ready to clock in data. ing both high and low address bytes, the master can
issue a Restart and the high address byte with the
Read Request Master sends an address byte with
R/W bit set. The slave logic will then hold the clock
the R/W bit set, indicating that it
and prepare to clock out data.
wishes to clock data out of the
Slave. This data is the next and all After a full match with R/W clear in 10-bit mode, a prior
following bytes until a Restart or match flag is set and maintained. Until a Stop
Stop. condition, a high address with R/W clear, or high
Clock Stretching When a device on the bus hold address match fails.
SCL low to stall communication.
24.4.8 START/STOP CONDITION
Bus Collision Any time the SDA line is sampled
INTERRUPT MASKING
low by the module while it is
outputting and expected high The SCIE and PCIE bits of the SSPCON3 register can
state. enable the generation of an interrupt in Slave modes
that do not typically support this function. Slave modes
where interrupt on Start and Stop detect are already
enabled, these bits will have no effect.

PIC16(L)F1933
FIGURE 24-12: I2C START AND STOP CONDITIONS
SDA
SCL
S P
Change of Change of
Data Allowed Data Allowed
Start Stop
Condition Condition
FIGURE 24-13: I2C RESTART CONDITION
Sr
Change of Change of
Data Allowed Data Allowed
Restart
Condition

PIC16(L)F1933
24.4.9 ACKNOWLEDGE SEQUENCE 24.5 I2C Slave Mode Operation
The 9th SCL pulse for any transferred byte in I2C is The MSSP Slave mode operates in one of four modes
dedicated as an Acknowledge. It allows receiving selected in the SSPM bits of SSPCON1 register. The
devices to respond back to the transmitter by pulling modes can be divided into 7-bit and 10-bit Addressing
the SDA line low. The transmitter must release control mode. 10-bit Addressing modes operate the same as
of the line during this time to shift in the response. The 7-bit with some additional overhead for handling the
Acknowledge (ACK) is an active-low signal, pulling the larger addresses.
SDA line low indicated to the transmitter that the
device has received the transmitted data and is ready Modes with Start and Stop bit interrupts operated the
to receive more. same as the other modes with SSPIF additionally
getting set upon detection of a Start, Restart, or Stop
The result of an ACK is placed in the ACKSTAT bit of condition.
the SSPCON2 register.
Slave software, when the AHEN and DHEN bits are 24.5.1 SLAVE MODE ADDRESSES
set, allow the user to set the ACK value sent back to The SSPADD register (Register 24-6) contains the
the transmitter. The ACKDT bit of the SSPCON2 Slave mode address. The first byte received after a
register is set/cleared to determine the response. Start or Restart condition is compared against the
Slave hardware will generate an ACK response if the value stored in this register. If the byte matches, the
AHEN and DHEN bits of the SSPCON3 register are value is loaded into the SSPBUF register and an
clear. interrupt is generated. If the value does not match, the
module goes Idle and no indication is given to the
There are certain conditions where an ACK will not be
software that anything happened.
sent by the slave. If the BF bit of the SSPSTAT register
or the SSPOV bit of the SSPCON1 register are set The SSP Mask register (Register 24-5) affects the
when a byte is received. address matching process. See Section 24.5.9 “SSP
Mask Register” for more information.
When the module is addressed, after the 8th falling
edge of SCL on the bus, the ACKTIM bit of the 24.5.1.1 I2C Slave 7-bit Addressing Mode
SSPCON3 register is set. The ACKTIM bit indicates
the acknowledge time of the active bus. The ACKTIM In 7-bit Addressing mode, the LSb of the received data
Status bit is only active when the AHEN bit or DHEN byte is ignored when determining if there is an address
bit is enabled. match.
24.5.1.2 I2C Slave 10-bit Addressing Mode

In 10-bit Addressing mode, the first received byte is
compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9
and A8 are the two MSb of the 10-bit address and
stored in bits 2 and 1 of the SSPADD register.
After the acknowledge of the high byte the UA bit is set
and SCL is held low until the user updates SSPADD
with the low address. The low address byte is clocked
in and all eight bits are compared to the low address
value in SSPADD. Even if there is not an address
match; SSPIF and UA are set, and SCL is held low
until SSPADD is updated to receive a high byte again.
When SSPADD is updated the UA bit is cleared. This
ensures the module is ready to receive the high
address byte on the next communication.
A high and low address match as a write request is
required at the start of all 10-bit addressing communi-
cation. A transmission can be initiated by issuing a
Restart once the slave is addressed, and clocking in
the high address with the R/W bit set. The slave hard-
ware will then acknowledge the read request and pre-
pare to clock out data. This is only valid for a slave
after it has received a complete high and low address
byte match.

PIC16(L)F1933
24.5.2 SLAVE RECEPTION 24.5.2.2 7-bit Reception with AHEN and
When the R/W bit of a matching received address byte DHEN
is clear, the R/W bit of the SSPSTAT register is cleared. Slave device reception with AHEN and DHEN set
The received address is loaded into the SSPBUF operate the same as without these options with extra
register and acknowledged. interrupts and clock stretching added after the 8th
When the overflow condition exists for a received falling edge of SCL. These additional interrupts allow
address, then not Acknowledge is given. An overflow the slave software to decide whether it wants to ACK
condition is defined as either bit BF bit of the SSPSTAT the receive address or data byte, rather than the
register is set, or bit SSPOV bit of the SSPCON1 hardware. This functionality adds support for PMBus™
register is set. The BOEN bit of the SSPCON3 register that was not present on previous versions of this
modifies this operation. For more information see module.
Register 24-4. This list describes the steps that need to be taken by
An MSSP interrupt is generated for each transferred slave software to use these options for I2C communi-
data byte. Flag bit, SSPIF, must be cleared by software. cation. Figure 24-16 displays a module using both
address and data holding. Figure 24-17 includes the
When the SEN bit of the SSPCON2 register is set, SCL operation with the SEN bit of the SSPCON2 register
will be held low (clock stretch) following each received set.
byte. The clock must be released by setting the CKP
bit of the SSPCON1 register, except sometimes in 1. S bit of SSPSTAT is set; SSPIF is set if interrupt
10-bit mode. See Section 24.2.3 “SPI Master Mode” on Start detect is enabled.
for more detail. 2. Matching address with R/W bit clear is clocked
in. SSPIF is set and CKP cleared after the 8th
24.5.2.1 7-bit Addressing Reception falling edge of SCL.
This section describes a standard sequence of events 3. Slave clears the SSPIF.
for the MSSP module configured as an I2C Slave in 4. Slave can look at the ACKTIM bit of the
7-bit Addressing mode. All decisions made by hard- SSPCON3 register to determine if the SSPIF
ware or software and their effect on reception. was after or before the ACK.
Figure 24-14 and Figure 24-15 is used as a visual 5. Slave reads the address value from SSPBUF,
reference for this description. clearing the BF flag.
This is a step by step process of what typically must 6. Slave sets ACK value clocked out to the master
be done to accomplish I2C communication. by setting ACKDT.
1. Start bit detected. 7. Slave releases the clock by setting CKP.
2. S bit of SSPSTAT is set; SSPIF is set if interrupt 8. SSPIF is set after an ACK, not after a NACK.
on Start detect is enabled. 9. If SEN = 1 the slave hardware will stretch the
3. Matching address with R/W bit clear is received. clock after the ACK.
4. The slave pulls SDA low sending an ACK to the 10. Slave clears SSPIF.
master, and sets SSPIF bit. Note: SSPIF is still set after the 9th falling edge of
5. Software clears the SSPIF bit. SCL even if there is no clock stretching and
6. Software reads received address from SSPBUF BF has been cleared. Only if NACK is sent
clearing the BF flag. to master is SSPIF not set
7. If SEN = 1; Slave software sets CKP bit to 11. SSPIF set and CKP cleared after 8th falling
release the SCL line. edge of SCL for a received data byte.
8. The master clocks out a data byte. 12. Slave looks at ACKTIM bit of SSPCON3 to
9. Slave drives SDA low sending an ACK to the determine the source of the interrupt.
master, and sets SSPIF bit. 13. Slave reads the received data from SSPBUF
10. Software clears SSPIF. clearing BF.
11. Software reads the received byte from SSPBUF 14. Steps 7-14 are the same for each received data
clearing BF. byte.
12. Steps 8-12 are repeated for all received bytes 15. Communication is ended by either the slave
from the Master. sending an ACK = 1, or the master sending a
13. Master sends Stop condition, setting P bit of Stop condition. If a Stop is sent and
SSPSTAT, and the bus goes Idle. Interrupt-on-Stop Detect is disabled, the slave
will only know by polling the P bit of the
SSTSTAT register.

FIGURE 24-14:
DS41575C-page 236
Bus Master sends
Stop condition
From Slave to Master
Receiving Address Receiving Data Receiving Data ACK = 1

PIC16(L)F1933
SDA
A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPIF
SSPIF set on 9th
Cleared by software Cleared by software falling edge of
SCL
BF
First byte
SSPBUF is read of data is
available
in SSPBUF
SSPOV
SSPOV set because

SSPBUF is still full.
ACK is not sent.
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)

FIGURE 24-15:
Bus Master sends

Stop condition
Receive Address Receive Data Receive Data ACK

SDA A7 A6 A5 A4 A3 A2 A1 R/W=0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCL S 1 2 3 4 5 6 7 8 9 SEN 1 2 3 4 5 6 7 8 9 SEN 1 2 3 4 5 6 7 8 9 P
Clock is held low until CKP is set to ‘1’
SSPIF
SSPIF set on 9th

Cleared by software Cleared by software falling edge of SCL
BF
First byte
of data is
SSPBUF is read available
in SSPBUF
SSPOV
SSPOV set because

SSPBUF is still full.
ACK is not sent.
CKP
SCL is not held

CKP is written to ‘1’ in software, CKP is written to 1 in software,
low because
releasing SCL releasing SCL
ACK= 1
PIC16(L)F1933
DS41575C-page 237
Master Releases SDA Master sends
to slave for ACK sequence Stop condition
FIGURE 24-16:
SDA Receiving Address Receiving Data ACK Received Data ACK=1
DS41575C-page 238
A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCL
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SSPIF
PIC16(L)F1933
If AHEN = 1: SSPIF is set on

SSPIF is set 9th falling edge of Cleared by software No interrupt
SCL, after ACK after not ACK
BF from Slave
Address is
read from Data is read from SSPBUF
ACKDT SSBUF
Slave software
clears ACKDT to Slave software
ACK the received sets ACKDT to
CKP byte not ACK
When AHEN=1:
When DHEN=1: CKP set by software,
CKP is cleared by hardware
CKP is cleared by SCL is released
and SCL is stretched hardware on 8th falling
edge of SCL
ACKTIM
ACKTIM set by hardware ACKTIM cleared by ACKTIM set by hardware

on 8th falling edge of SCL hardware in 9th on 8th falling edge of SCL
rising edge of SCL
P

Master sends
FIGURE 24-17:
Stop condition
Master releases
R/W = 0 SDA to slave for ACK sequence
Receiving Address Receive Data Receive Data ACK
SDA ACK
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P

S
SSPIF
Cleared by software No interrupt after
if not ACK
from Slave
BF
Received
address is loaded into Received data is SSPBUF can be
SSPBUF available on SSPBUF read any time before
next byte is loaded
ACKDT
Slave software clears

Slave sends
ACKDT to ACK not ACK
the received byte
CKP
When AHEN = 1; When DHEN = 1; CKP is not cleared
on the 8th falling edge on the 8th falling edge Set by software, if not ACK
of SCL of an address of SCL of a received release SCL
byte, CKP is cleared data byte, CKP is cleared
ACKTIM
ACKTIM is set by hardware ACKTIM is cleared by hardware

on 8th falling edge of SCL on 9th rising edge of SCL
P
PIC16(L)F1933
DS41575C-page 239
PIC16(L)F1933
24.5.3 SLAVE TRANSMISSION 24.5.3.2 7-bit Transmission
When the R/W bit of the incoming address byte is set A master device can transmit a read request to a
and an address match occurs, the R/W bit of the slave, and then clock data out of the slave. The list
SSPSTAT register is set. The received address is below outlines what software for a slave will need to
loaded into the SSPBUF register, and an ACK pulse is do to accomplish a standard transmission.
sent by the slave on the ninth bit. Figure 24-18 can be used as a reference to this list.
Following the ACK, slave hardware clears the CKP bit 1. Master sends a Start condition on SDA and
and the SCL pin is held low (see Section 24.5.6 SCL.
“Clock Stretching” for more detail). By stretching the 2. S bit of SSPSTAT is set; SSPIF is set if interrupt
clock, the master will be unable to assert another clock on Start detect is enabled.
pulse until the slave is done preparing the transmit 3. Matching address with R/W bit set is received by
data. the Slave setting SSPIF bit.
The transmit data must be loaded into the SSPBUF 4. Slave hardware generates an ACK and sets
register which also loads the SSPSR register. Then the SSPIF.
SCL pin should be released by setting the CKP bit of 5. SSPIF bit is cleared by user.
the SSPCON1 register. The eight data bits are shifted
6. Software reads the received address from
out on the falling edge of the SCL input. This ensures
SSPBUF, clearing BF.
that the SDA signal is valid during the SCL high time.
7. R/W is set so CKP was automatically cleared
The ACK pulse from the master-receiver is latched on after the ACK.
the rising edge of the ninth SCL input pulse. This ACK
8. The slave software loads the transmit data into
value is copied to the ACKSTAT bit of the SSPCON2
SSPBUF.
register. If ACKSTAT is set (not ACK), then the data
transfer is complete. In this case, when the not ACK is 9. CKP bit is set releasing SCL, allowing the
latched by the slave, the slave goes Idle and waits for master to clock the data out of the slave.
another occurrence of the Start bit. If the SDA line was 10. SSPIF is set after the ACK response from the
low (ACK), the next transmit data must be loaded into master is loaded into the ACKSTAT register.
the SSPBUF register. Again, the SCL pin must be 11. SSPIF bit is cleared.
released by setting bit CKP. 12. The slave software checks the ACKSTAT bit to
An MSSP interrupt is generated for each data transfer see if the master wants to clock out more data.
byte. The SSPIF bit must be cleared by software and Note 1: If the master ACKs the clock will be
the SSPSTAT register is used to determine the status stretched.
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse. 2: ACKSTAT is the only bit updated on the
rising edge of SCL (9th) rather than the
24.5.3.1 Slave Mode Bus Collision falling.
A slave receives a Read request and begins shifting 13. Steps 9-13 are repeated for each transmitted
data out on the SDA line. If a bus collision is detected byte.
and the SBCDE bit of the SSPCON3 register is set, the 14. If the master sends a not ACK; the clock is not
BCLIF bit of the PIR register is set. Once a bus collision held, but SSPIF is still set.
is detected, the slave goes Idle and waits to be 15. The master sends a Restart condition or a Stop.
addressed again. User software can use the BCLIF bit
16. The slave is no longer addressed.
to handle a slave bus collision.

Master sends
Stop condition
FIGURE 24-18:
Receiving Address Transmitting Data Automatic Transmitting Data ACK

R/W = 1 Automatic
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPIF

Cleared by software
BF
BF is automatically
Received address Data to transmit is cleared after 8th falling
is read from SSPBUF loaded into SSPBUF edge of SCL
CKP
When R/W is set CKP is not
SCL is always held for not
held low after 9th SCL Set by software ACK
falling edge
ACKSTAT
Masters not ACK

is copied to
ACKSTAT
R/W
R/W is copied from the
matching address byte
D/A
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)
Indicates an address
has been received
P
PIC16(L)F1933
DS41575C-page 241
PIC16(L)F1933
24.5.3.3 7-bit Transmission with Address
Hold Enabled
Setting the AHEN bit of the SSPCON3 register
enables additional clock stretching and interrupt
generation after the 8th falling edge of a received
matching address. Once a matching address has
been clocked in, CKP is cleared and the SSPIF
interrupt is set.
Figure 24-19 displays a standard waveform of a 7-bit
Address Slave Transmission with AHEN enabled.
1. Bus starts Idle.
2. Master sends Start condition; the S bit of
SSPSTAT is set; SSPIF is set if interrupt on Start
detect is enabled.
3. Master sends matching address with R/W bit
set. After the 8th falling edge of the SCL line the
CKP bit is cleared and SSPIF interrupt is
generated.
4. Slave software clears SSPIF.
5. Slave software reads ACKTIM bit of SSPCON3
register, and R/W and D/A of the SSPSTAT
register to determine the source of the interrupt.
6. Slave reads the address value from the
SSPBUF register clearing the BF bit.
7. Slave software decides from this information if it
wishes to ACK or not ACK and sets ACKDT bit
of the SSPCON2 register accordingly.
8. Slave sets the CKP bit releasing SCL.
9. Master clocks in the ACK value from the slave.
10. Slave hardware automatically clears the CKP bit
and sets SSPIF after the ACK if the R/W bit is
set.
11. Slave software clears SSPIF.
12. Slave loads value to transmit to the master into
SSPBUF setting the BF bit.
Note: SSPBUF cannot be loaded until after the
ACK.
13. Slave sets CKP bit releasing the clock.
14. Master clocks out the data from the slave and
sends an ACK value on the 9th SCL pulse.
15. Slave hardware copies the ACK value into the
ACKSTAT bit of the SSPCON2 register.
16. Steps 10-15 are repeated for each byte transmit-
ted to the master from the slave.
17. If the master sends a not ACK the slave
releases the bus allowing the master to send a
Stop and end the communication.
Note: Master must send a not ACK on the last byte
to ensure that the slave releases the SCL
line to receive a Stop.

Master sends
Master releases SDA Stop condition
FIGURE 24-19:
to slave for ACK sequence
Receiving Address R/W = 1 Automatic Transmitting Data Automatic Transmitting Data ACK
SDA ACK
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
P

SSPIF
Cleared by software
BF BF is automatically
Received address Data to transmit is cleared after 8th falling
is read from SSPBUF loaded into SSPBUF edge of SCL
ACKDT
Slave clears
ACKDT to ACK
address
ACKSTAT
Master’s ACK
response is copied
to SSPSTAT
CKP
When AHEN = 1; CKP not cleared
CKP is cleared by hardware When R/W = 1; Set by software, after not ACK
after receiving matching CKP is always releases SCL
address. cleared after ACK
ACKTIM
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)
ACKTIM is set on 8th falling ACKTIM is cleared

edge of SCL on 9th rising edge of SCL
R/W
D/A
PIC16(L)F1933
DS41575C-page 243
PIC16(L)F1933
24.5.4 SLAVE MODE 10-BIT ADDRESS 24.5.5 10-BIT ADDRESSING WITH
RECEPTION ADDRESS OR DATA HOLD
This section describes a standard sequence of events Reception using 10-bit addressing with AHEN or
for the MSSP module configured as an I2C Slave in DHEN set is the same as with 7-bit modes. The only
10-bit Addressing mode. difference is the need to update the SSPADD register
Figure 24-20 is used as a visual reference for this using the UA bit. All functionality, specifically when the
description. CKP bit is cleared and SCL line is held low are the
same. Figure 24-21 can be used as a reference of a
This is a step by step process of what must be done by slave in 10-bit addressing with AHEN set.
slave software to accomplish I2C communication.
Figure 24-22 shows a standard waveform for a slave
1. Bus starts Idle. transmitter in 10-bit Addressing mode.
2. Master sends Start condition; S bit of SSPSTAT
is set; SSPIF is set if interrupt on Start detect is
enabled.
3. Master sends matching high address with R/W
bit clear; UA bit of the SSPSTAT register is set.
4. Slave sends ACK and SSPIF is set.
5. Software clears the SSPIF bit.
6. Software reads received address from SSPBUF
clearing the BF flag.
7. Slave loads low address into SSPADD,
releasing SCL.
8. Master sends matching low address byte to the
Slave; UA bit is set.
Note: Updates to the SSPADD register are not
allowed until after the ACK sequence.
9. Slave sends ACK and SSPIF is set.

Note: If the low address does not match, SSPIF
and UA are still set so that the slave soft-
ware can set SSPADD back to the high
address. BF is not set because there is no
match. CKP is unaffected.
10. Slave clears SSPIF.
11. Slave reads the received matching address
from SSPBUF clearing BF.
12. Slave loads high address into SSPADD.
13. Master clocks a data byte to the slave and
clocks out the slaves ACK on the 9th SCL pulse;
SSPIF is set.
14. If SEN bit of SSPCON2 is set, CKP is cleared by
hardware and the clock is stretched.
15. Slave clears SSPIF.
16. Slave reads the received byte from SSPBUF
clearing BF.
17. If SEN is set the slave sets CKP to release the
SCL.
18. Steps 13-17 repeat for each received byte.
19. Master sends Stop to end the transmission.

FIGURE 24-20:
Master sends
Stop condition
Receive First Address Byte Receive Second Address Byte Receive Data Receive Data
SDA
1 1 1 1
0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
SCL is held low
while CKP = 0
SSPIF
Set by hardware Cleared by software
on 9th falling edge
BF
If address matches Receive address is Data is read
SSPADD it is loaded into read from SSPBUF from SSPBUF
SSPBUF
UA
When UA = 1; Software updates SSPADD
SCL is held low and releases SCL
CKP
When SEN = 1; Set by software,

CKP is cleared after releasing SCL
9th falling edge of received byte
PIC16(L)F1933
DS41575C-page 245
Receive First Address Byte R/W = 0 Receive Second Address Byte Receive Data Receive Data
FIGURE 24-21:
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5
DS41575C-page 246
SCL S 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 1 2
PIC16(L)F1933
SSPIF
Set by hardware Cleared by software Cleared by software
on 9th falling edge
BF
SSPBUF can be Received data

read anytime before is read from
the next received byte SSPBUF
ACKDT
Slave software clears
ACKDT to ACK
the received byte
UA
Update to SSPADD is Update of SSPADD,

not allowed until 9th
falling edge of SCL clears UA and releases
SCL
CKP If when AHEN = 1;

on the 8th falling edge Set CKP with software
of SCL of an address releases SCL
byte, CKP is cleared
ACKTIM
ACKTIM is set by hardware
on 8th falling edge of SCL

FIGURE 24-22:
Master sends
Master sends Stop condition
Restart event Master sends
not ACK
Receiving Address R/W = 0 Receiving Second Address Byte Receive First Address Byte Transmitting Data Byte ACK = 1
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
Sr
SSPIF
Set by hardware Cleared by software Set by hardware
BF
SSPBUF loaded Received address is Data to transmit is

with received address read from SSPBUF loaded into SSPBUF
UA
High address is loaded
UA indicates SSPADD After SSPADD is back into SSPADD
must be updated updated, UA is cleared
CKP and SCL is released
When R/W = 1; Set by software

ACKSTAT CKP is cleared on releases SCL
9th falling edge of SCL
Masters not ACK

is copied
R/W
R/W is copied from the
matching address byte
D/A
Indicates an address
has been received
I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)
PIC16(L)F1933
DS41575C-page 247
PIC16(L)F1933
24.5.6 CLOCK STRETCHING 24.5.6.2 10-bit Addressing Mode
Clock stretching occurs when a device on the bus In 10-bit Addressing mode, when the UA bit is set, the
holds the SCL line low effectively pausing communica- clock is always stretched. This is the only time the SCL
tion. The slave may stretch the clock to allow more is stretched without CKP being cleared. SCL is
time to handle data or prepare a response for the released immediately after a write to SSPADD.
master device. A master device is not concerned with
Note: Previous versions of the module did not
stretching as anytime it is active on the bus and not
stretch the clock if the second address byte
transferring data it is stretching. Any stretching done
did not match.
by a slave is invisible to the master software and
handled by the hardware that generates SCL.
24.5.6.3 Byte NACKing
The CKP bit of the SSPCON1 register is used to
control stretching in software. Any time the CKP bit is When the AHEN bit of SSPCON3 is set; CKP is
cleared, the module will wait for the SCL line to go low cleared by hardware after the 8th falling edge of SCL
and then hold it. Setting CKP will release SCL and for a received matching address byte. When the
allow more communication. DHEN bit of SSPCON3 is set; CKP is cleared after the
8th falling edge of SCL for received data.
24.5.6.1 Normal Clock Stretching Stretching after the 8th falling edge of SCL allows the
Following an ACK if the R/W bit of SSPSTAT is set, a slave to look at the received address or data and
read request, the slave hardware will clear CKP. This decide if it wants to ACK the received data.
allows the slave time to update SSPBUF with data to
transfer to the master. If the SEN bit of SSPCON2 is 24.5.7 CLOCK SYNCHRONIZATION AND
set, the slave hardware will always stretch the clock THE CKP BIT
after the ACK sequence. Once the slave is ready; CKP Any time the CKP bit is cleared, the module will wait
is set by software and communication resumes. for the SCL line to go low and then hold it. However,
clearing the CKP bit will not assert the SCL output low
Note 1: The BF bit has no effect on if the clock will
until the SCL output is already sampled low. There-
be stretched or not. This is different than
fore, the CKP bit will not assert the SCL line until an
previous versions of the module that
external I2C master device has already asserted the
would not stretch the clock, clear CKP, if
SCL line. The SCL output will remain low until the CKP
SSPBUF was read before the 9th falling
bit is set and all other devices on the I2C bus have
edge of SCL.
released SCL. This ensures that a write to the CKP bit
2: Previous versions of the module did not will not violate the minimum high time requirement for
stretch the clock for a transmission if SCL (see Figure 24-23).
SSPBUF was loaded before the 9th falling
edge of SCL. It is now always cleared for
read requests.
FIGURE 24-23: CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA DX DX ‚ – 1
SCL
Master device
CKP asserts clock
Master device
releases clock
WR
SSPCON1

PIC16(L)F1933
24.5.8 GENERAL CALL ADDRESS In 10-bit Address mode, the UA bit will not be set on
SUPPORT the reception of the general call address. The slave
will prepare to receive the second byte as data, just as
The addressing procedure for the I2C bus is such that
it would in 7-bit mode.
the first byte after the Start condition usually deter-
mines which device will be the slave addressed by the If the AHEN bit of the SSPCON3 register is set, just as
master device. The exception is the general call with any other address reception, the slave hardware
address which can address all devices. When this will stretch the clock after the 8th falling edge of SCL.
address is used, all devices should, in theory, respond The slave must then set its ACKDT value and release
with an Acknowledge. the clock with communication progressing as it would
normally.
The general call address is a reserved address in the
I2C protocol, defined as address 0x00. When the
GCEN bit of the SSPCON2 register is set, the slave
module will automatically ACK the reception of this
address regardless of the value stored in SSPADD.
After the slave clocks in an address of all zeros with
the R/W bit clear, an interrupt is generated and slave
software can read SSPBUF and respond.
Figure 24-24 shows a general call reception
sequence.
FIGURE 24-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

Address is compared to General Call Address
after ACK, set interrupt
R/W = 0 Receiving Data ACK

SDA General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
SSPIF
BF (SSPSTAT<0>)
Cleared by software
SSPBUF is read
GCEN (SSPCON2<7>)
’1’
24.5.9 SSP MASK REGISTER

An SSP Mask (SSPMSK) register (Register 24-5) is
available in I2C Slave mode as a mask for the value
held in the SSPSR register during an address
comparison operation. A zero (‘0’) bit in the SSPMSK
register has the effect of making the corresponding bit
of the received address a “don’t care”.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
The SSP Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
• 10-bit Address mode: address compare of A<7:0>
only. The SSP mask has no effect during the
reception of the first (high) byte of the address.

PIC16(L)F1933
24.6 I2C Master Mode 24.6.1 I2C MASTER MODE OPERATION
Master mode is enabled by setting and clearing the The master device generates all of the serial clock
appropriate SSPM bits in the SSPCON1 register and pulses and the Start and Stop conditions. A transfer is
by setting the SSPEN bit. In Master mode, the SDA and ended with a Stop condition or with a Repeated Start
SCK pins must be configured as inputs. The MSSP condition. Since the Repeated Start condition is also
peripheral hardware will override the output driver TRIS the beginning of the next serial transfer, the I2C bus will
controls when necessary to drive the pins low. not be released.
Master mode of operation is supported by interrupt In Master Transmitter mode, serial data is output
generation on the detection of the Start and Stop con- through SDA, while SCL outputs the serial clock. The
ditions. The Stop (P) and Start (S) bits are cleared from first byte transmitted contains the slave address of the
a Reset or when the MSSP module is disabled. Control receiving device (7 bits) and the Read/Write (R/W) bit.
of the I 2C bus may be taken when the P bit is set, or the In this case, the R/W bit will be logic ‘0’. Serial data is
bus is Idle. transmitted eight bits at a time. After each byte is trans-
mitted, an Acknowledge bit is received. Start and Stop
In Firmware Controlled Master mode, user code conditions are output to indicate the beginning and the
conducts all I 2C bus operations based on Start and end of a serial transfer.
Stop bit condition detection. Start and Stop condition
detection is the only active circuitry in this mode. All In Master Receive mode, the first byte transmitted
other communication is done by the user software contains the slave address of the transmitting device
directly manipulating the SDA and SCL lines. (7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
The following events will cause the SSP Interrupt Flag address followed by a ‘1’ to indicate the receive bit.
bit, SSPIF, to be set (SSP interrupt, if enabled): Serial data is received via SDA, while SCL outputs the
• Start condition detected serial clock. Serial data is received eight bits at a time.
After each byte is received, an Acknowledge bit is
• Stop condition detected
transmitted. Start and Stop conditions indicate the
• Data transfer byte transmitted/received beginning and end of transmission.
• Acknowledge transmitted/received
A Baud Rate Generator (BRG) is used to set the clock
• Repeated Start generated frequency output on SCL. See Section 24.7 “Baud
Note 1: The MSSP module, when configured in Rate Generator” for more detail.
I2C Master mode, does not allow queue-
ing of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start con-
dition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a
write to the SSPBUF did not occur
2: When in Master mode, Start/Stop detec-
tion is masked and an interrupt is gener-
ated when the SEN/PEN bit is cleared and
the generation is complete.

PIC16(L)F1933
24.6.2 CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
releases the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the Baud Rate
Generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPADD<7:0> and begins
counting. This ensures that the SCL high time will
always be at least one BRG rollover count in the event
that the clock is held low by an external device
(Figure 24-25).
FIGURE 24-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA DX DX ‚ – 1
SCL deasserted but slave holds SCL allowed to transition high

SCL low (clock arbitration)
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
03h 02h 01h 00h (hold off) 03h 02h
Value
SCL is sampled high, reload takes

place and BRG starts its count
BRG
Reload
24.6.3 WCOL STATUS FLAG

If the user writes the SSPBUF when a Start, Restart,
Stop, Receive or Transmit sequence is in progress, the
WCOL is set and the contents of the buffer are
unchanged (the write does not occur). Any time the
WCOL bit is set it indicates that an action on SSPBUF
was attempted while the module was not idle.
Note: Because queueing of events is not
allowed, writing to the lower five bits of
SSPCON2 is disabled until the Start
condition is complete.

PIC16(L)F1933
24.6.4 I2C MASTER MODE START hardware; the Baud Rate Generator is suspended,
CONDITION TIMING leaving the SDA line held low and the Start condition is
complete.
To initiate a Start condition (Figure 24-26), the user
sets the Start Enable bit, SEN bit of the SSPCON2 Note 1: If at the beginning of the Start condition,
register. If the SDA and SCL pins are sampled high, the SDA and SCL pins are already
the Baud Rate Generator is reloaded with the contents sampled low, or if during the Start
of SSPADD<7:0> and starts its count. If SCL and SDA condition, the SCL line is sampled low
are both sampled high when the Baud Rate Generator before the SDA line is driven low, a bus
times out (TBRG), the SDA pin is driven low. The action collision occurs, the Bus Collision
of the SDA being driven low while SCL is high is the Interrupt Flag, BCLIF, is set, the Start
Start condition and causes the S bit of the SSPSTAT1 condition is aborted and the I2C module is
register to be set. Following this, the Baud Rate reset into its Idle state.
Generator is reloaded with the contents of 2: The Philips I2C specification states that a
SSPADD<7:0> and resumes its count. When the Baud bus collision cannot occur on a Start.
Rate Generator times out (TBRG), the SEN bit of the
SSPCON2 register will be automatically cleared by
FIGURE 24-26: FIRST START BIT TIMING
Write to SEN bit occurs here Set S bit (SSPSTAT<3>)
At completion of Start bit,

SDA = 1,
SCL = 1 hardware clears SEN bit
and sets SSPIF bit
TBRG TBRG Write to SSPBUF occurs here
SDA 1st bit 2nd bit
TBRG
SCL
S
TBRG

PIC16(L)F1933
24.6.5 I2C MASTER MODE REPEATED SSPCON2 register will be automatically cleared and
START CONDITION TIMING the Baud Rate Generator will not be reloaded, leaving
the SDA pin held low. As soon as a Start condition is
A Repeated Start condition (Figure 24-27) occurs when
detected on the SDA and SCL pins, the S bit of the
the RSEN bit of the SSPCON2 register is programmed
SSPSTAT register will be set. The SSPIF bit will not be
high and the master state machine is no longer active.
set until the Baud Rate Generator has timed out.
When the RSEN bit is set, the SCL pin is asserted low.
When the SCL pin is sampled low, the Baud Rate Note 1: If RSEN is programmed while any other
Generator is loaded and begins counting. The SDA pin event is in progress, it will not take effect.
is released (brought high) for one Baud Rate Generator 2: A bus collision during the Repeated Start
count (TBRG). When the Baud Rate Generator times condition occurs if:
out, if SDA is sampled high, the SCL pin will be
deasserted (brought high). When SCL is sampled high, • SDA is sampled low when SCL
the Baud Rate Generator is reloaded and begins count- goes from low-to-high.
ing. SDA and SCL must be sampled high for one TBRG. • SCL goes low before SDA is
This action is then followed by assertion of the SDA pin asserted low. This may indicate
(SDA = 0) for one TBRG while SCL is high. SCL is that another master is attempting to
asserted low. Following this, the RSEN bit of the transmit a data ‘1’.
FIGURE 24-27: REPEAT START CONDITION WAVEFORM
S bit set by hardware

Write to SSPCON2
occurs here At completion of Start bit,
SDA = 1, SDA = 1,
hardware clears RSEN bit
SCL (no change) SCL = 1 and sets SSPIF
TBRG TBRG TBRG
SDA 1st bit
Write to SSPBUF occurs here

TBRG
SCL
Sr TBRG
Repeated Start

PIC16(L)F1933
24.6.6 I2C MASTER MODE 24.6.6.3 ACKSTAT Status Flag
TRANSMISSION In Transmit mode, the ACKSTAT bit of the SSPCON2
Transmission of a data byte, a 7-bit address or the register is cleared when the slave has sent an
other half of a 10-bit address is accomplished by simply Acknowledge (ACK = 0) and is set when the slave
writing a value to the SSPBUF register. This action will does not Acknowledge (ACK = 1). A slave sends an
set the Buffer Full flag bit, BF, and allow the Baud Rate Acknowledge when it has recognized its address
Generator to begin counting and start the next (including a general call), or when the slave has
transmission. Each bit of address/data will be shifted properly received its data.
out onto the SDA pin after the falling edge of SCL is
asserted. SCL is held low for one Baud Rate Generator 24.6.6.4 Typical Transmit Sequence:
rollover count (TBRG). Data should be valid before SCL 1. The user generates a Start condition by setting
is released high. When the SCL pin is released high, it the SEN bit of the SSPCON2 register.
is held that way for TBRG. The data on the SDA pin 2. SSPIF is set by hardware on completion of the
must remain stable for that duration and some hold Start.
time after the next falling edge of SCL. After the eighth
3. SSPIF is cleared by software.
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA. 4. The MSSP module will wait the required start
This allows the slave device being addressed to time before any other operation takes place.
respond with an ACK bit during the ninth bit time if an 5. The user loads the SSPBUF with the slave
address match occurred, or if data was received address to transmit.
properly. The status of ACK is written into the 6. Address is shifted out the SDA pin until all eight
ACKSTAT bit on the rising edge of the ninth clock. If the bits are transmitted. Transmission begins as
master receives an Acknowledge, the Acknowledge soon as SSPBUF is written to.
Status bit, ACKSTAT, is cleared. If not, the bit is set. 7. The MSSP module shifts in the ACK bit from the
After the ninth clock, the SSPIF bit is set and the master slave device and writes its value into the
clock (Baud Rate Generator) is suspended until the ACKSTAT bit of the SSPCON2 register.
next data byte is loaded into the SSPBUF, leaving SCL
8. The MSSP module generates an interrupt at the
low and SDA unchanged (Figure 24-28).
end of the ninth clock cycle by setting the SSPIF
After the write to the SSPBUF, each bit of the address bit.
will be shifted out on the falling edge of SCL until all 9. The user loads the SSPBUF with eight bits of
seven address bits and the R/W bit are completed. On data.
the falling edge of the eighth clock, the master will
10. Data is shifted out the SDA pin until all eight bits
release the SDA pin, allowing the slave to respond with
are transmitted.
an Acknowledge. On the falling edge of the ninth clock,
the master will sample the SDA pin to see if the address 11. The MSSP module shifts in the ACK bit from the
was recognized by a slave. The status of the ACK bit is slave device and writes its value into the
loaded into the ACKSTAT Status bit of the SSPCON2 ACKSTAT bit of the SSPCON2 register.
register. Following the falling edge of the ninth clock 12. Steps 8-11 are repeated for all transmitted data
transmission of the address, the SSPIF is set, the BF bytes.
flag is cleared and the Baud Rate Generator is turned 13. The user generates a Stop or Restart condition
off until another write to the SSPBUF takes place, by setting the PEN or RSEN bits of the
holding SCL low and allowing SDA to float. SSPCON2 register. Interrupt is generated once
the Stop/Restart condition is complete.
24.6.6.1 BF Status Flag
In Transmit mode, the BF bit of the SSPSTAT register
is set when the CPU writes to SSPBUF and is cleared
when all 8 bits are shifted out.
24.6.6.2 WCOL Status Flag

If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write does not occur).
WCOL must be cleared by software before the next
transmission.

Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
Write to SSPCON2<0> (SEN = 1),
FIGURE 24-28:
begin Start condition ACK from Master Set ACKEN, start Acknowledge sequence
Master configured as a receiver SDA = ACKDT = 0 SDA = ACKDT = 1
SEN = 0 by programming SSPCON2<3> (RCEN = 1)
PEN bit = 1
Write to SSPBUF occurs here, RCEN cleared RCEN = 1, start RCEN cleared
ACK from Slave next receive automatically written here
start XMIT automatically
Transmit Address to Slave Receiving Data from Slave Receiving Data from Slave
SDA A7 A6 A5 A4 A3 A2 A1 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

Bus master
ACK is not sent terminates
transfer
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL S P
Data shifted in on falling edge of CLK Set SSPIF at end
of receive Set SSPIF interrupt
Set SSPIF interrupt at end of Acknow-
Set SSPIF interrupt ledge sequence
at end of receive at end of Acknowledge
SSPIF sequence
Set P bit
Cleared by software Cleared by software Cleared by software Cleared by software (SSPSTAT<4>)
SDA = 0, SCL = 1 Cleared in
while CPU software and SSPIF
responds to SSPIF
BF
(SSPSTAT<0>) Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
SSPOV
SSPOV is set because

SSPBUF is still full
ACKEN
I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
RCEN
Master configured as a receiver RCEN cleared ACK from Master RCEN cleared
by programming SSPCON2<3> (RCEN = 1) automatically SDA = ACKDT = 0 automatically
PIC16(L)F1933
DS41575C-page 255
PIC16(L)F1933
24.6.7 I2C MASTER MODE RECEPTION 24.6.7.4 Typical Receive Sequence:
Master mode reception (Figure 24-29) is enabled by 1. The user generates a Start condition by setting
programming the Receive Enable bit, RCEN bit of the the SEN bit of the SSPCON2 register.
SSPCON2 register. 2. SSPIF is set by hardware on completion of the
Note: The MSSP module must be in an Idle Start.
state before the RCEN bit is set or the 3. SSPIF is cleared by software.
RCEN bit will be disregarded. 4. User writes SSPBUF with the slave address to
transmit and the R/W bit set.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes 5. Address is shifted out the SDA pin until all eight
(high-to-low/low-to-high) and data is shifted into the bits are transmitted. Transmission begins as
SSPSR. After the falling edge of the eighth clock, the soon as SSPBUF is written to.
receive enable flag is automatically cleared, the 6. The MSSP module shifts in the ACK bit from the
contents of the SSPSR are loaded into the SSPBUF, slave device and writes its value into the
the BF flag bit is set, the SSPIF flag bit is set and the ACKSTAT bit of the SSPCON2 register.
Baud Rate Generator is suspended from counting, 7. The MSSP module generates an interrupt at the
holding SCL low. The MSSP is now in Idle state end of the ninth clock cycle by setting the SSPIF
awaiting the next command. When the buffer is read by bit.
the CPU, the BF flag bit is automatically cleared. The 8. User sets the RCEN bit of the SSPCON2 register
user can then send an Acknowledge bit at the end of and the master clocks in a byte from the slave.
reception by setting the Acknowledge Sequence 9. After the 8th falling edge of SCL, SSPIF and BF
Enable, ACKEN bit of the SSPCON2 register. are set.
24.6.7.1 BF Status Flag 10. Master clears SSPIF and reads the received
byte from SSPBUF, clears BF.
In receive operation, the BF bit is set when an address
11. Master sets ACK value sent to slave in ACKDT
or data byte is loaded into SSPBUF from SSPSR. It is
bit of the SSPCON2 register and initiates the
cleared when the SSPBUF register is read.
ACK by setting the ACKEN bit.
24.6.7.2 SSPOV Status Flag 12. Masters ACK is clocked out to the Slave and
SSPIF is set.
In receive operation, the SSPOV bit is set when eight
13. User clears SSPIF.
bits are received into the SSPSR and the BF flag bit is
already set from a previous reception. 14. Steps 8-13 are repeated for each received byte
from the slave.
24.6.7.3 WCOL Status Flag 15. Master sends a not ACK or Stop to end
If the user writes the SSPBUF when a receive is communication.
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write does not occur).

Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
Write to SSPCON2<0> (SEN = 1),
FIGURE 24-29:
begin Start condition ACK from Master Set ACKEN, start Acknowledge sequence
Master configured as a receiver SDA = ACKDT = 0 SDA = ACKDT = 1
SEN = 0 by programming SSPCON2<3> (RCEN = 1)
PEN bit = 1
Write to SSPBUF occurs here, RCEN cleared RCEN = 1, start RCEN cleared
ACK from Slave next receive automatically written here
start XMIT automatically
Transmit Address to Slave Receiving Data from Slave Receiving Data from Slave
SDA A7 A6 A5 A4 A3 A2 A1 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

Bus master
ACK is not sent terminates
transfer
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL S P
Data shifted in on falling edge of CLK Set SSPIF at end
of receive Set SSPIF interrupt
Set SSPIF interrupt at end of Acknow-
Set SSPIF interrupt ledge sequence
at end of receive at end of Acknowledge
SSPIF sequence
Set P bit
Cleared by software Cleared by software Cleared by software Cleared by software (SSPSTAT<4>)
SDA = 0, SCL = 1 Cleared in
while CPU software and SSPIF
responds to SSPIF
BF
(SSPSTAT<0>) Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
SSPOV
SSPOV is set because

SSPBUF is still full
ACKEN
I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
RCEN
Master configured as a receiver RCEN cleared ACK from Master RCEN cleared
by programming SSPCON2<3> (RCEN = 1) automatically SDA = ACKDT = 0 automatically
PIC16(L)F1933
DS41575C-page 257
PIC16(L)F1933
24.6.8 ACKNOWLEDGE SEQUENCE 24.6.9 STOP CONDITION TIMING
TIMING A Stop bit is asserted on the SDA pin at the end of a
An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable
Acknowledge Sequence Enable bit, ACKEN bit of the bit, PEN bit of the SSPCON2 register. At the end of a
SSPCON2 register. When this bit is set, the SCL pin is receive/transmit, the SCL line is held low after the
pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set,
are presented on the SDA pin. If the user wishes to the master will assert the SDA line low. When the SDA
generate an Acknowledge, then the ACKDT bit should line is sampled low, the Baud Rate Generator is
be cleared. If not, the user should set the ACKDT bit reloaded and counts down to ‘0’. When the Baud Rate
before starting an Acknowledge sequence. The Baud Generator times out, the SCL pin will be brought high
Rate Generator then counts for one rollover period and one TBRG (Baud Rate Generator rollover count)
(TBRG) and the SCL pin is deasserted (pulled high). later, the SDA pin will be deasserted. When the SDA
When the SCL pin is sampled high (clock arbitration), pin is sampled high while SCL is high, the P bit of the
the Baud Rate Generator counts for TBRG. The SCL pin SSPSTAT register is set. A TBRG later, the PEN bit is
is then pulled low. Following this, the ACKEN bit is cleared and the SSPIF bit is set (Figure 24-31).
automatically cleared, the Baud Rate Generator is
turned off and the MSSP module then goes into Idle 24.6.9.1 WCOL Status Flag
mode (Figure 24-30). If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
24.6.8.1 WCOL Status Flag contents of the buffer are unchanged (the write does
If the user writes the SSPBUF when an Acknowledge not occur).
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write does
not occur).
FIGURE 24-30: ACKNOWLEDGE SEQUENCE WAVEFORM

Acknowledge sequence starts here, ACKEN automatically cleared
write to SSPCON2
ACKEN = 1, ACKDT = 0
TBRG TBRG
SDA D0 ACK
SCL 8 9
SSPIF
Cleared in
SSPIF set at software
the end of receive Cleared in
software SSPIF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.

PIC16(L)F1933
FIGURE 24-31: STOP CONDITION RECEIVE OR TRANSMIT MODE
Write to SSPCON2, SCL = 1 for TBRG, followed by SDA = 1 for TBRG
set PEN after SDA sampled high. P bit (SSPSTAT<4>) is set.
Falling edge of PEN bit (SSPCON2<2>) is cleared by

9th clock hardware and the SSPIF bit is set
TBRG
SCL
SDA ACK
P
TBRG TBRG TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
24.6.10 SLEEP OPERATION 24.6.13 MULTI -MASTER COMMUNICATION,

While in Sleep mode, the I2C slave
module can receive BUS COLLISION AND BUS
addresses or data and when an address match or ARBITRATION
complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra-
from Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
24.6.11 EFFECTS OF A RESET outputs a ‘1’ on SDA, by letting SDA float high and
A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCL pin floats
current transfer. high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’,
24.6.12 MULTI-MASTER MODE then a bus collision has taken place. The master will set
In Multi-Master mode, the interrupt generation on the the Bus Collision Interrupt Flag, BCLIF, and reset the
detection of the Start and Stop conditions allows the I2C port to its Idle state (Figure 24-32).
determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision
Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is
MSSP module is disabled. Control of the I 2C bus may cleared, the SDA and SCL lines are deasserted and the
be taken when the P bit of the SSPSTAT register is set, SSPBUF can be written to. When the user services the
or the bus is Idle, with both the S and P bits clear. When bus collision Interrupt Service Routine and if the I2C
the bus is busy, enabling the SSP interrupt will bus is free, the user can resume communication by
generate the interrupt when the Stop condition occurs. asserting a Start condition.
In multi-master operation, the SDA line must be If a Start, Repeated Start, Stop or Acknowledge condition
monitored for arbitration to see if the signal level is the was in progress when the bus collision occurred, the con-
expected output level. This check is performed by dition is aborted, the SDA and SCL lines are deasserted
hardware with the result placed in the BCLIF bit. and the respective control bits in the SSPCON2 register
The states where arbitration can be lost are: are cleared. When the user services the bus collision
Interrupt Service Routine and if the I2C bus is free, the
• Address Transfer user can resume communication by asserting a Start
• Data Transfer condition.
• A Start Condition The master will continue to monitor the SDA and SCL
• A Repeated Start Condition pins. If a Stop condition occurs, the SSPIF bit will be set.
• An Acknowledge Condition A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the I2C
bus can be taken when the P bit is set in the SSPSTAT
register, or the bus is Idle and the S and P bits are
cleared.

PIC16(L)F1933
FIGURE 24-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDA. While SCL is high,
Data changes SDA line pulled low data does not match what is driven
while SCL = 0 by another source by the master.
Bus collision has occurred.
SDA released
by master
SDA
SCL Set bus collision

interrupt (BCLIF)
BCLIF
24.6.13.1 Bus Collision During a Start If the SDA pin is sampled low during this count, the
Condition BRG is reset and the SDA line is asserted early
(Figure 24-35). If, however, a ‘1’ is sampled on the SDA
During a Start condition, a bus collision occurs if:
pin, the SDA pin is asserted low at the end of the BRG
a) SDA or SCL are sampled low at the beginning of count. The Baud Rate Generator is then reloaded and
the Start condition (Figure 24-33). counts down to zero; if the SCL pin is sampled as ‘0’
b) SCL is sampled low before SDA is asserted low during this time, a bus collision does not occur. At the
(Figure 24-34). end of the BRG count, the SCL pin is asserted low.
During a Start condition, both the SDA and the SCL Note: The reason that bus collision is not a
pins are monitored. factor during a Start condition is that no
If the SDA pin is already low, or the SCL pin is already two bus masters can assert a Start
low, then all of the following occur: condition at the exact same time. There-
fore, one master will always assert SDA
• the Start condition is aborted,
before the other. This condition does not
• the BCLIF flag is set and cause a bus collision because the two
• the MSSP module is reset to its Idle state masters must be allowed to arbitrate the
(Figure 24-33). first address following the Start condition.
The Start condition begins with the SDA and SCL pins If the address is the same, arbitration
deasserted. When the SDA pin is sampled high, the must be allowed to continue into the data
Baud Rate Generator is loaded and counts down. If the portion, Repeated Start or Stop
SCL pin is sampled low while SDA is high, a bus conditions.
collision occurs because it is assumed that another
master is attempting to drive a data ‘1’ during the Start
condition.

PIC16(L)F1933
FIGURE 24-33: BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
Set SEN, enable Start SEN cleared automatically because of bus collision.
condition if SDA = 1, SCL = 1 SSP module reset into Idle state.
SEN
SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
BCLIF SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared by software
SSPIF
SSPIF and BCLIF are

cleared by software
FIGURE 24-34: BUS COLLISION DURING START CONDITION (SCL = 0)

SDA = 0, SCL = 1
TBRG TBRG
SDA
SCL Set SEN, enable Start

sequence if SDA = 1, SCL = 1
SCL = 0 before SDA = 0,
bus collision occurs. Set BCLIF.
SEN
SCL = 0 before BRG time-out,
bus collision occurs. Set BCLIF.
BCLIF
Interrupt cleared
by software
S ’0’ ’0’
SSPIF ’0’ ’0’

PIC16(L)F1933
FIGURE 24-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S Set SSPIF
Less than TBRG
TBRG
SDA SDA pulled low by other master.

Reset BRG and assert SDA.
SCL S
SCL pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
BCLIF ’0’
SSPIF
SDA = 0, SCL = 1, Interrupts cleared
set SSPIF by software

PIC16(L)F1933
24.6.13.2 Bus Collision During a Repeated If SDA is low, a bus collision has occurred (i.e., another
Start Condition master is attempting to transmit a data ‘0’, Figure 24-36).
If SDA is sampled high, the BRG is reloaded and begins
During a Repeated Start condition, a bus collision
counting. If SDA goes from high-to-low before the BRG
occurs if:
times out, no bus collision occurs because no two
a) A low level is sampled on SDA when SCL goes masters can assert SDA at exactly the same time.
from a low level to a high level.
If SCL goes from high-to-low before the BRG times out
b) SCL goes low before SDA is asserted low, and SDA has not already been asserted, a bus collision
indicating that another master is attempting to occurs. In this case, another master is attempting to
transmit a data ‘1’. transmit a data ‘1’ during the Repeated Start condition,
When the user releases SDA and the pin is allowed to see Figure 24-37.
float high, the BRG is loaded with SSPADD and counts If, at the end of the BRG time-out, both SCL and SDA
down to zero. The SCL pin is then deasserted and are still high, the SDA pin is driven low and the BRG is
when sampled high, the SDA pin is sampled. reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
FIGURE 24-36: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.

If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared by software
S ’0’
SSPIF ’0’
FIGURE 24-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG TBRG
SDA
SCL
SCL goes low before SDA,

BCLIF set BCLIF. Release SDA and SCL.
Interrupt cleared
by software
RSEN
S ’0’
SSPIF

PIC16(L)F1933
24.6.13.3 Bus Collision During a Stop The Stop condition begins with SDA asserted low.
Condition When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
Bus collision occurs during a Stop condition if:
the Baud Rate Generator is loaded with SSPADD and
a) After the SDA pin has been deasserted and counts down to zero. After the BRG times out, SDA is
allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has
the BRG has timed out. occurred. This is due to another master attempting to
b) After the SCL pin is deasserted, SCL is sampled drive a data ‘0’ (Figure 24-38). If the SCL pin is sampled
low before SDA goes high. low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 24-39).
FIGURE 24-38: BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG TBRG TBRG SDA sampled

low after TBRG,
set BCLIF
SDA
SDA asserted low

SCL
PEN
BCLIF
P ’0’
SSPIF ’0’
FIGURE 24-39: BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG TBRG TBRG
SDA
Assert SDA SCL goes low before SDA goes high,

set BCLIF
SCL
PEN
BCLIF
P ’0’
SSPIF ’0’

PIC16(L)F1933
TABLE 24-3: SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ OPERATION
Reset
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on
Page:

SSPADD ADD<7:0> 272
SSPBUF MSSP Receive Buffer/Transmit Register 223*
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 270
SSPCON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 271
SSPMSK MSK<7:0> 272
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I2C™ mode.

PIC16(L)F1933
24.7 Baud Rate Generator clock line. The logic dictating when the reload signal is
asserted depends on the mode the MSSP is being
The MSSP module has a Baud Rate Generator avail- operated in.
able for clock generation in both I2C and SPI Master
modes. The Baud Rate Generator (BRG) reload value Table 24-4 demonstrates clock rates based on
is placed in the SSPADD register (Register 24-6). instruction cycles and the BRG value loaded into
When a write occurs to SSPBUF, the Baud Rate SSPADD.
Generator will automatically begin counting down.
EQUATION 24-1:
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
FOSC
remain in its last state. FCLOCK = -------------------------------------------------
 SSPxADD + 1   4 
An internal signal “Reload” in Figure 24-40 triggers the
value from SSPADD to be loaded into the BRG counter.
This occurs twice for each oscillation of the module
FIGURE 24-40: BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0> SSPADD<7:0>
SSPM<3:0> Reload Reload

SCL Control
SSPCLK BRG Down Counter FOSC/2
Note: Values of 0x00, 0x01 and 0x02 are not valid

for SSPADD when used as a Baud Rate
Generator for I2C. This is an implementation
limitation.
TABLE 24-4: MSSP CLOCK RATE W/BRG

FCLOCK
FOSC FCY BRG Value
(2 Rollovers of BRG)
32 MHz 8 MHz 13h 400 kHz(1)
32 MHz 8 MHz 19h 308 kHz
32 MHz 8 MHz 4Fh 100 kHz
16 MHz 4 MHz 09h 400 kHz(1)
16 MHz 4 MHz 0Ch 308 kHz
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.

PIC16(L)F1933
REGISTER 24-1: SSPSTAT: SSP STATUS REGISTER

R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0
SMP CKE D/A P S R/W UA BF
bit 7 bit 0
Legend:
bit 7 SMP: SPI Data Input Sample bit

SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
In I2 C Master or Slave mode:
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high speed mode (400 kHz)
bit 6 CKE: SPI Clock Edge Select bit (SPI mode only)
In SPI Master or Slave mode:
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
In I2 C™ mode only:
1 = Enable input logic so that thresholds are compliant with SMBus specification
0 = Disable SMBus specific inputs
bit 5 D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0 = Stop bit was not detected last
bit 3 S: Start bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
bit 2 R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match
to the next Start bit, Stop bit, or not ACK bit.
In I2 C Slave mode:
1 = Read
0 = Write
In I2 C Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode.
bit 1 UA: Update Address bit (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
Receive (SPI and I2 C modes):
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2 C mode only):
1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full
0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty

PIC16(L)F1933
REGISTER 24-2: SSPCON1: SSP CONTROL REGISTER 1

R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
WCOL SSPOV SSPEN CKP SSPM<3:0>
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared
bit 7 WCOL: Write Collision Detect bit

Master mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be
started
0 = No collision
Slave mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit(1)
In SPI mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in
SSPSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPBUF, even if
only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new recep-
tion (and transmission) is initiated by writing to the SSPBUF register (must be cleared in software).
0 = No overflow
In I2 C mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in
Transmit mode (must be cleared in software).
0 = No overflow
bit 5 SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
In SPI mode:
1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2)
0 = Disables serial port and configures these pins as I/O port pins
In I2 C mode:
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3)
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2 C Slave mode:
SCL release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2 C Master mode:
Unused in this mode

PIC16(L)F1933
REGISTER 24-2: SSPCON1: SSP CONTROL REGISTER 1 (CONTINUED)
bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1101 = Reserved
1100 = Reserved
1011 = I2C firmware controlled Master mode (slave idle)
1010 = SPI Master mode, clock = FOSC/(4 * (SSPADD+1))(5)
1001 = Reserved
1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1))(4)
0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = FOSC/64
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the
SSPBUF register.
2: When enabled, these pins must be properly configured as input or output.
3: When enabled, the SDA and SCL pins must be configured as inputs.
4: SSPADD values of 0, 1 or 2 are not supported for I2C mode.
5: SSPADD value of ‘0’ is not supported. Use SSPM = 0000 instead.

PIC16(L)F1933

R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set
bit 7 GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only)
1 = Acknowledge was not received
0 = Acknowledge was received
bit 5 ACKDT: Acknowledge Data bit (in I2C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3 RCEN: Receive Enable bit (in I2C Master mode only)
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only)
SCKMSSP Release Control:
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enable/Stretch Enable bit
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).

PIC16(L)F1933

R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN
bit 7 bit 0
Legend:
bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3)

1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCL clock
0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCL clock
bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only)
1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled(2)
bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only)
1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled(2)
bit 4 BOEN: Buffer Overwrite Enable bit
In SPI Slave mode:(1)
1 = SSPBUF updates every time that a new data byte is shifted in ignoring the BF bit
0 = If new byte is received with BF bit of the SSPSTAT register already set, SSPOV bit of the
SSPCON1 register is set, and the buffer is not updated
In I2C Master and SPI Master mode:
In I2C Slave mode:
1 = SSPBUF is updated and ACK is generated for a received address/data byte, ignoring the state
of the SSPOV bit only if the BF bit = 0.
0 = SSPBUF is only updated when SSPOV is clear
bit 3 SDAHT: SDA Hold Time Selection bit (I2C mode only)
1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL
0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL
bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCLIF
bit of the PIR2 register is set, and bus goes idle
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only)
1 = Following the 8th falling edge of SCL for a matching received address byte; CKP bit of the
SSPCON1 register will be cleared and the SCL will be held low.
0 = Address holding is disabled
bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only)
1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit
of the SSPCON1 register and SCL is held low.
0 = Data holding is disabled
Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPBUF.
2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.

PIC16(L)F1933
REGISTER 24-5: SSPMSK: SSP MASK REGISTER

MSK<7:0>
bit 7 bit 0
Legend:
bit 7-1 MSK<7:1>: Mask bits

1 = The received address bit n is compared to SSPADD<n> to detect I2C address match
0 = The received address bit n is not used to detect I2C address match
bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address
I2C Slave mode, 10-bit address (SSPM<3:0> = 0111 or 1111):
1 = The received address bit 0 is compared to SSPADD<0> to detect I2C address match
0 = The received address bit 0 is not used to detect I2C address match
I2C Slave mode, 7-bit address, the bit is ignored
REGISTER 24-6: SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE)
ADD<7:0>
bit 7 bit 0
Legend:
Master mode:
bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits

SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC
10-Bit Slave mode — Most Significant Address Byte:
bit 7-3 Not used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care”. Bit
pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits
are compared by hardware and are not affected by the value in this register.
bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address
bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.
10-Bit Slave mode — Least Significant Address Byte:
bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address

7-Bit Slave mode:
bit 7-1 ADD<7:1>: 7-bit address

bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.

PIC16(L)F1933
NOTES:

PIC16(L)F1933

PIC16(L)F1933
25.0 ENHANCED UNIVERSAL The EUSART module includes the following capabilities:
SYNCHRONOUS • Full-duplex asynchronous transmit and receive
ASYNCHRONOUS RECEIVER • Two-character input buffer
TRANSMITTER (EUSART) • One-character output buffer
• Programmable 8-bit or 9-bit character length
The Enhanced Universal Synchronous Asynchronous
• Address detection in 9-bit mode
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock • Input buffer overrun error detection
generators, shift registers and data buffers necessary • Received character framing error detection
to perform an input or output serial data transfer • Half-duplex synchronous master
independent of device program execution. The • Half-duplex synchronous slave
EUSART, also known as a Serial Communications • Programmable clock polarity in synchronous
Interface (SCI), can be configured as a full-duplex modes
asynchronous system or half-duplex synchronous
• Sleep operation
system. Full-Duplex mode is useful for
communications with peripheral systems, such as CRT The EUSART module implements the following
terminals and personal computers. Half-Duplex additional features, making it ideally suited for use in
Synchronous mode is intended for communications Local Interconnect Network (LIN) bus systems:
with peripheral devices, such as A/D or D/A integrated • Automatic detection and calibration of the baud rate
circuits, serial EEPROMs or other microcontrollers.
• Wake-up on Break reception
These devices typically do not have internal clocks for
baud rate generation and require the external clock • 13-bit Break character transmit
signal provided by a master synchronous device. Block diagrams of the EUSART transmitter and
receiver are shown in Figure 25-1 and Figure 25-2.
FIGURE 25-1: EUSART TRANSMIT BLOCK DIAGRAM

Data Bus
TXIE
Interrupt
TXREG Register TXIF
8
MSb LSb TX/CK pin
(8) 0 Pin Buffer
• • • and Control
Transmit Shift Register (TSR)
TXEN
TRMT SPEN
Baud Rate Generator FOSC
÷n
TX9
BRG16 n
+1 Multiplier x4 x16 x64
TX9D
SYNC 1 X 0 0 0
SPBRGH SPBRGL BRGH X 1 1 0 0
BRG16 X 1 0 1 0

PIC16(L)F1933
FIGURE 25-2: EUSART RECEIVE BLOCK DIAGRAM
SPEN CREN OERR RCIDL
RX/DT pin MSb RSR Register LSb

Pin Buffer Data
and Control Recovery
Stop (8) 7 ••• 1 0 START
Baud Rate Generator FOSC RX9

÷n
BRG16
+1 n
Multiplier x4 x16 x64
SYNC 1 X 0 0 0
SPBRGH SPBRGL BRGH X 1 1 0 0 FIFO
FERR RX9D RCREG Register
BRG16 X 1 0 1 0
8
Data Bus
RCIF Interrupt
RCIE
The operation of the EUSART module is controlled

through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCON)
These registers are detailed in Register 25-1,
Register 25-2 and Register 25-3, respectively.
When the receiver or transmitter section is not enabled
then the corresponding RX or TX pin may be used for
general purpose input and output.

PIC16(L)F1933
25.1 EUSART Asynchronous Mode 25.1.1.2 Transmitting Data
The EUSART transmits and receives data using the A transmission is initiated by writing a character to the
standard non-return-to-zero (NRZ) format. NRZ is TXREG register. If this is the first character, or the
implemented with two levels: a VOH mark state which previous character has been completely flushed from
represents a ‘1’ data bit, and a VOL space state which the TSR, the data in the TXREG is immediately
represents a ‘0’ data bit. NRZ refers to the fact that transferred to the TSR register. If the TSR still contains
consecutively transmitted data bits of the same value all or part of a previous character, the new character
stay at the output level of that bit without returning to a data is held in the TXREG until the Stop bit of the
neutral level between each bit transmission. An NRZ previous character has been transmitted. The pending
transmission port idles in the mark state. Each character character in the TXREG is then transferred to the TSR
transmission consists of one Start bit followed by eight in one TCY immediately following the Stop bit
or nine data bits and is always terminated by one or transmission. The transmission of the Start bit, data bits
more Stop bits. The Start bit is always a space and the and Stop bit sequence commences immediately
Stop bits are always marks. The most common data following the transfer of the data to the TSR from the
format is eight bits. Each transmitted bit persists for a TXREG.
period of 1/(Baud Rate). An on-chip dedicated
8-bit/16-bit Baud Rate Generator is used to derive 25.1.1.3 Transmit Data Polarity
standard baud rate frequencies from the system The polarity of the transmit data can be controlled with
oscillator. See Table 25-5 for examples of baud rate the SCKP bit of the BAUDCON register. The default
configurations. state of this bit is ‘0’ which selects high true transmit idle
The EUSART transmits and receives the LSb first. The and data bits. Setting the SCKP bit to ‘1’ will invert the
EUSART’s transmitter and receiver are functionally transmit data resulting in low true idle and data bits. The
independent, but share the same data format and baud SCKP bit controls transmit data polarity in
rate. Parity is not supported by the hardware, but can Asynchronous mode only. In Synchronous mode, the
be implemented in software and stored as the ninth SCKP bit has a different function. See Section 25.5.1.2
data bit. “Clock Polarity”.
25.1.1 EUSART ASYNCHRONOUS 25.1.1.4 Transmit Interrupt Flag

TRANSMITTER The TXIF interrupt flag bit of the PIR1 register is set
whenever the EUSART transmitter is enabled and no
The EUSART transmitter block diagram is shown in
character is being held for transmission in the TXREG.
Figure 25-1. The heart of the transmitter is the serial
In other words, the TXIF bit is only clear when the TSR
Transmit Shift Register (TSR), which is not directly
is busy with a character and a new character has been
accessible by software. The TSR obtains its data from
queued for transmission in the TXREG. The TXIF flag bit
the transmit buffer, which is the TXREG register.
is not cleared immediately upon writing TXREG. TXIF
25.1.1.1 Enabling the Transmitter becomes valid in the second instruction cycle following
the write execution. Polling TXIF immediately following
The EUSART transmitter is enabled for asynchronous the TXREG write will return invalid results. The TXIF bit
operations by configuring the following three control is read-only, it cannot be set or cleared by software.
bits:
The TXIF interrupt can be enabled by setting the TXIE
• TXEN = 1 interrupt enable bit of the PIE1 register. However, the
• SYNC = 0 TXIF flag bit will be set whenever the TXREG is empty,
• SPEN = 1 regardless of the state of TXIE enable bit.
All other EUSART control bits are assumed to be in To use interrupts when transmitting data, set the TXIE
their default state. bit only when there is more data to send. Clear the
TXIE interrupt enable bit upon writing the last character
Setting the TXEN bit of the TXSTA register enables the
of the transmission to the TXREG.
transmitter circuitry of the EUSART. Clearing the SYNC
bit of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART and automatically
configures the TX/CK I/O pin as an output. If the TX/CK
pin is shared with an analog peripheral, the analog I/O
function must be disabled by clearing the corresponding
ANSEL bit.
Note 1: The TXIF Transmitter Interrupt flag is set
when the TXEN enable bit is set.

PIC16(L)F1933
25.1.1.5 TSR Status 25.1.1.7 Asynchronous Transmission Set-up:
The TRMT bit of the TXSTA register indicates the 1. Initialize the SPBRGH, SPBRGL register pair and
status of the TSR register. This is a read-only bit. The the BRGH and BRG16 bits to achieve the desired
TRMT bit is set when the TSR register is empty and is baud rate (see Section 25.4 “EUSART Baud
cleared when a character is transferred to the TSR Rate Generator (BRG)”).
register from the TXREG. The TRMT bit remains clear 2. Enable the asynchronous serial port by clearing
until all bits have been shifted out of the TSR register. the SYNC bit and setting the SPEN bit.
No interrupt logic is tied to this bit, so the user has to 3. If 9-bit transmission is desired, set the TX9
poll this bit to determine the TSR status. control bit. A set ninth data bit will indicate that
Note: The TSR register is not mapped in data the eight Least Significant data bits are an
memory, so it is not available to the user. address when the receiver is set for address
detection.
25.1.1.6 Transmitting 9-Bit Characters 4. Set SCKP bit if inverted transmit is desired.
The EUSART supports 9-bit character transmissions. 5. Enable the transmission by setting the TXEN
When the TX9 bit of the TXSTA register is set, the control bit. This will cause the TXIF interrupt bit
EUSART will shift nine bits out for each character to be set.
transmitted. The TX9D bit of the TXSTA register is the 6. If interrupts are desired, set the TXIE interrupt
ninth, and Most Significant, data bit. When transmitting enable bit of the PIE1 register. An interrupt will
9-bit data, the TX9D data bit must be written before occur immediately provided that the GIE and
writing the eight Least Significant bits into the TXREG. PEIE bits of the INTCON register are also set.
All nine bits of data will be transferred to the TSR shift 7. If 9-bit transmission is selected, the ninth bit
register immediately after the TXREG is written. should be loaded into the TX9D data bit.
A special 9-bit Address mode is available for use with 8. Load 8-bit data into the TXREG register. This
multiple receivers. See Section 25.1.2.7 “Address will start the transmission.
Detection” for more information on the address mode.
FIGURE 25-3: ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXIF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)
TRMT bit Word 1

Transmit Shift Reg.
(Transmit Shift
Reg. Empty Flag)

PIC16(L)F1933
FIGURE 25-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXREG
Word 1 Word 2
BRG Output
(Shift Clock)
TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0
TXIF bit 1 TCY Word 1 Word 2
(Transmit Buffer
Reg. Empty Flag) 1 TCY
TRMT bit Word 1 Word 2

(Transmit Shift Transmit Shift Reg. Transmit Shift Reg.
Reg. Empty Flag)
Note: This timing diagram shows two consecutive transmissions.
TABLE 25-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Register
on Page
BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 287
SPBRGL BRG<7:0> 288*
SPBRGH BRG<15:8> 288*
TXREG EUSART Transmit Data Register 277*
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous transmission.

PIC16(L)F1933
25.1.2 EUSART ASYNCHRONOUS 25.1.2.2 Receiving Data
RECEIVER The receiver data recovery circuit initiates character
The Asynchronous mode is typically used in RS-232 reception on the falling edge of the first bit. The first bit,
systems. The receiver block diagram is shown in also known as the Start bit, is always a zero. The data
Figure 25-2. The data is received on the RX/DT pin and recovery circuit counts one-half bit time to the center of
drives the data recovery block. The data recovery block the Start bit and verifies that the bit is still a zero. If it is
is actually a high-speed shifter operating at 16 times not a zero then the data recovery circuit aborts
the baud rate, whereas the serial Receive Shift character reception, without generating an error, and
Register (RSR) operates at the bit rate. When all eight resumes looking for the falling edge of the Start bit. If
or nine bits of the character have been shifted in, they the Start bit zero verification succeeds then the data
are immediately transferred to a two character recovery circuit counts a full bit time to the center of the
First-In-First-Out (FIFO) memory. The FIFO buffering next bit. The bit is then sampled by a majority detect
allows reception of two complete characters and the circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.
start of a third character before software must start This repeats until all data bits have been sampled and
servicing the EUSART receiver. The FIFO and RSR shifted into the RSR. One final bit time is measured and
registers are not directly accessible by software. the level sampled. This is the Stop bit, which is always
Access to the received data is via the RCREG register. a ‘1’. If the data recovery circuit samples a ‘0’ in the
Stop bit position then a framing error is set for this
25.1.2.1 Enabling the Receiver character, otherwise the framing error is cleared for this
The EUSART receiver is enabled for asynchronous character. See Section 25.1.2.4 “Receive Framing
operation by configuring the following three control bits: Error” for more information on framing errors.
• CREN = 1 Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
• SYNC = 0
to the EUSART receive FIFO and the RCIF interrupt
• SPEN = 1 flag bit of the PIR1 register is set. The top character in
All other EUSART control bits are assumed to be in the FIFO is transferred out of the FIFO by reading the
their default state. RCREG register.
Setting the CREN bit of the RCSTA register enables the Note: If the receive FIFO is overrun, no additional
receiver circuitry of the EUSART. Clearing the SYNC bit characters will be received until the overrun
of the TXSTA register configures the EUSART for condition is cleared. See Section 25.1.2.5
asynchronous operation. Setting the SPEN bit of the “Receive Overrun Error” for more
RCSTA register enables the EUSART. The programmer information on overrun errors.
must set the corresponding TRIS bit to configure the
RX/DT I/O pin as an input. 25.1.2.3 Receive Interrupts
Note 1: If the RX/DT function is on an analog pin, The RCIF interrupt flag bit of the PIR1 register is set
the corresponding ANSEL bit must be whenever the EUSART receiver is enabled and there is
cleared for the receiver to function. an unread character in the receive FIFO. The RCIF
interrupt flag bit is read-only, it cannot be set or cleared
by software.
RCIF interrupts are enabled by setting all of the
following bits:
• RCIE, Interrupt Enable bit of the PIE1 register
• PEIE, Peripheral Interrupt Enable bit of the
INTCON register
• GIE, Global Interrupt Enable bit of the INTCON
register
The RCIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.

PIC16(L)F1933
25.1.2.4 Receive Framing Error 25.1.2.7 Address Detection
Each character in the receive FIFO buffer has a A special Address Detection mode is available for use
corresponding framing error Status bit. A framing error when multiple receivers share the same transmission
indicates that a Stop bit was not seen at the expected line, such as in RS-485 systems. Address detection is
time. The framing error status is accessed via the enabled by setting the ADDEN bit of the RCSTA
FERR bit of the RCSTA register. The FERR bit register.
represents the status of the top unread character in the Address detection requires 9-bit character reception.
receive FIFO. Therefore, the FERR bit must be read When address detection is enabled, only characters
before reading the RCREG. with the ninth data bit set will be transferred to the
The FERR bit is read-only and only applies to the top receive FIFO buffer, thereby setting the RCIF interrupt
unread character in the receive FIFO. A framing error bit. All other characters will be ignored.
(FERR = 1) does not preclude reception of additional Upon receiving an address character, user software
characters. It is not necessary to clear the FERR bit. determines if the address matches its own. Upon
Reading the next character from the FIFO buffer will address match, user software must disable address
advance the FIFO to the next character and the next detection by clearing the ADDEN bit before the next
corresponding framing error. Stop bit occurs. When user software detects the end of
The FERR bit can be forced clear by clearing the SPEN the message, determined by the message protocol
bit of the RCSTA register which resets the EUSART. used, software places the receiver back into the
Clearing the CREN bit of the RCSTA register does not Address Detection mode by setting the ADDEN bit.
affect the FERR bit. A framing error by itself does not
generate an interrupt.
Note: If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RCREG will not clear the FERR bit.
25.1.2.5 Receive Overrun Error

The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RCSTA register is set.
The characters already in the FIFO buffer can be read
but no additional characters will be received until the
error is cleared. The error must be cleared by either
clearing the CREN bit of the RCSTA register or by
resetting the EUSART by clearing the SPEN bit of the
RCSTA register.
25.1.2.6 Receiving 9-bit Characters

The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set the EUSART
will shift nine bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth and Most Significant data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the eight Least Significant bits
from the RCREG.

PIC16(L)F1933
25.1.2.8 Asynchronous Reception Set-up: 25.1.2.9 9-bit Address Detection Mode Set-up
1. Initialize the SPBRGH, SPBRGL register pair This mode would typically be used in RS-485 systems.
and the BRGH and BRG16 bits to achieve the To set up an Asynchronous Reception with Address
desired baud rate (see Section 25.4 “EUSART Detect Enable:
Baud Rate Generator (BRG)”). 1. Initialize the SPBRGH, SPBRGL register pair
2. Clear the ANSEL bit for the RX pin (if applicable). and the BRGH and BRG16 bits to achieve the
3. Enable the serial port by setting the SPEN bit. desired baud rate (see Section 25.4 “EUSART
The SYNC bit must be clear for asynchronous Baud Rate Generator (BRG)”).
operation. 2. Clear the ANSEL bit for the RX pin (if applicable).
4. If interrupts are desired, set the RCIE bit of the 3. Enable the serial port by setting the SPEN bit.
PIE1 register and the GIE and PEIE bits of the The SYNC bit must be clear for asynchronous
INTCON register. operation.
5. If 9-bit reception is desired, set the RX9 bit. 4. If interrupts are desired, set the RCIE bit of the
6. Enable reception by setting the CREN bit. PIE1 register and the GIE and PEIE bits of the
7. The RCIF interrupt flag bit will be set when a INTCON register.
character is transferred from the RSR to the 5. Enable 9-bit reception by setting the RX9 bit.
receive buffer. An interrupt will be generated if 6. Enable address detection by setting the ADDEN
the RCIE interrupt enable bit was also set. bit.
8. Read the RCSTA register to get the error flags 7. Enable reception by setting the CREN bit.
and, if 9-bit data reception is enabled, the ninth 8. The RCIF interrupt flag bit will be set when a
data bit. character with the ninth bit set is transferred
9. Get the received eight Least Significant data bits from the RSR to the receive buffer. An interrupt
from the receive buffer by reading the RCREG will be generated if the RCIE interrupt enable bit
register. was also set.
10. If an overrun occurred, clear the OERR flag by 9. Read the RCSTA register to get the error flags.
clearing the CREN receiver enable bit. The ninth data bit will always be set.
10. Get the received eight Least Significant data bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
11. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
12. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
FIGURE 25-5: ASYNCHRONOUS RECEPTION

Start Start Start
RX/DT pin bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop
bit bit bit
Rcv Shift
Reg
Rcv Buffer Reg.
Word 1 Word 2
RCREG RCREG
RCIDL
Read Rcv
Buffer Reg.
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.

PIC16(L)F1933
TABLE 25-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Register
on Page
RCREG EUSART Receive Data Register 280*
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for asynchronous reception.

PIC16(L)F1933
25.2 Clock Accuracy with
Asynchronous Operation
The factory calibrates the internal oscillator block
output (INTOSC). However, the INTOSC frequency
may drift as VDD or temperature changes, and this
directly affects the asynchronous baud rate. Two
methods may be used to adjust the baud rate clock, but
both require a reference clock source of some kind.
The first (preferred) method uses the OSCTUNE
register to adjust the INTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
changes to the system clock source. See Section 5.2.2
“Internal Clock Sources” for more information.
The other method adjusts the value in the Baud Rate
Generator. This can be done automatically with the
Auto-Baud Detect feature (see Section 25.4.1
“Auto-Baud Detect”). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.

PIC16(L)F1933
25.3 Register Definitions: EUSART Control
REGISTER 25-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0
(1)
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
bit 7 bit 0
Legend:
bit 7 CSRC: Clock Source Select bit

Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.

PIC16(L)F1933
REGISTER 25-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1)

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-x/x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
Legend:
bit 7 SPEN: Serial Port Enable bit

1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave
Don’t care
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.

PIC16(L)F1933
REGISTER 25-3: BAUDCON: BAUD RATE CONTROL REGISTER

R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN
bit 7 bit 0
Legend:
bit 7 ABDOVF: Auto-Baud Detect Overflow bit

Asynchronous mode:
1 = Auto-baud timer overflowed
0 = Auto-baud timer did not overflow
Synchronous mode:
Don’t care
bit 6 RCIDL: Receive Idle Flag bit
Asynchronous mode:
1 = Receiver is Idle
0 = Start bit has been received and the receiver is receiving
Synchronous mode:
Don’t care
bit 4 SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
1 = Transmit inverted data to the TX/CK pin
0 = Transmit non-inverted data to the TX/CK pin
Synchronous mode:
1 = Data is clocked on rising edge of the clock
0 = Data is clocked on falling edge of the clock
bit 3 BRG16: 16-bit Baud Rate Generator bit
1 = 16-bit Baud Rate Generator is used
0 = 8-bit Baud Rate Generator is used
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE
will automatically clear after RCIF is set.
0 = Receiver is operating normally
Synchronous mode:
Don’t care
bit 0 ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete)
0 = Auto-Baud Detect mode is disabled
Synchronous mode:
Don’t care

PIC16(L)F1933
25.4 EUSART Baud Rate Generator EXAMPLE 25-1: CALCULATING BAUD
(BRG) RATE ERROR
The Baud Rate Generator (BRG) is an 8-bit or 16-bit For a device with FOSC of 16 MHz, desired baud rate
timer that is dedicated to the support of both the of 9600, Asynchronous mode, 8-bit BRG:
asynchronous and synchronous EUSART operation. F OS C
Desired Baud Rate = ---------------------------------------------------------------------
By default, the BRG operates in 8-bit mode. Setting the 64  [SPBRGH:SPBRG] + 1 
BRG16 bit of the BAUDCON register selects 16-bit Solving for SPBRGH:SPBRGL:
mode.
FOSC
The SPBRGH, SPBRGL register pair determines the ---------------------------------------------
Desired Baud Rate
period of the free running baud rate timer. In X = --------------------------------------------- – 1
64
Asynchronous mode the multiplier of the baud rate
16000000
period is determined by both the BRGH bit of the TXSTA ------------------------
9600
register and the BRG16 bit of the BAUDCON register. In = ------------------------ – 1
64
Synchronous mode, the BRGH bit is ignored.
=  25.042  = 25
Table 25-3 contains the formulas for determining the
baud rate. Example 25-1 provides a sample calculation 16000000
Calculated Baud Rate = ---------------------------
for determining the baud rate and baud rate error. 64  25 + 1 
Typical baud rates and error values for various = 9615

asynchronous modes have been computed for your
convenience and are shown in Table 25-3. It may be Calc. Baud Rate – Desired Baud Rate
Error = --------------------------------------------------------------------------------------------
advantageous to use the high baud rate (BRGH = 1), Desired Baud Rate
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
 9615 – 9600 
error. The 16-bit BRG mode is used to achieve slow = ---------------------------------- = 0.16%
9600
baud rates for fast oscillator frequencies.
Writing a new value to the SPBRGH, SPBRGL register
pair causes the BRG timer to be reset (or cleared). This
ensures that the BRG does not wait for a timer overflow
before outputting the new baud rate.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is Idle before
changing the system clock.

PIC16(L)F1933
TABLE 25-3: BAUD RATE FORMULAS
Configuration Bits
BRG/EUSART Mode Baud Rate Formula
SYNC BRG16 BRGH
0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)]

0 0 1 8-bit/Asynchronous
FOSC/[16 (n+1)]
1 0 x 8-bit/Synchronous FOSC/[4 (n+1)]
1 1 x 16-bit/Synchronous
Legend: x = Don’t care, n = value of SPBRGH, SPBRGL register pair
TABLE 25-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Register
on Page
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for the Baud Rate Generator.

PIC16(L)F1933
TABLE 25-5: BAUD RATES FOR ASYNCHRONOUS MODES

SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
BAUD
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — — — —
1200 — — — 1221 1.73 255 1200 0.00 239 1200 0.00 143
2400 2404 0.16 207 2404 0.16 129 2400 0.00 119 2400 0.00 71
9600 9615 0.16 51 9470 -1.36 32 9600 0.00 29 9600 0.00 17
10417 10417 0.00 47 10417 0.00 29 10286 -1.26 27 10165 -2.42 16
19.2k 19.23k 0.16 25 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8
57.6k 55.55k -3.55 3 — — — 57.60k 0.00 7 57.60k 0.00 2
115.2k — — — — — — — — — — — —
SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
BAUD
300 — — — 300 0.16 207 300 0.00 191 300 0.16 51
1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12
2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — —
9600 9615 0.16 12 — — — 9600 0.00 5 — — —
10417 10417 0.00 11 10417 0.00 5 — — — — — —
19.2k — — — — — — 19.20k 0.00 2 — — —
57.6k — — — — — — 57.60k 0.00 0 — — —
115.2k — — — — — — — — — — — —
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
300 — — — — — — — — — — — —
1200 — — — — — — — — — — — —
2400 — — — — — — — — — — — —
9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71
10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65
19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35
57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11
115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5

PIC16(L)F1933
TABLE 25-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 0
300 — — — — — — — — — 300 0.16 207
1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
SYNC = 0, BRGH = 0, BRG16 = 1
300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303
1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575
2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287
9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71
10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65
19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35
57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11
115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5
SYNC = 0, BRGH = 0, BRG16 = 1
300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207
1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —

PIC16(L)F1933
TABLE 25-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
300 300.0 0.00 26666 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215
1200 1200 0.00 6666 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303
2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151
9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287
10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264
19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143
57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47
115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832
1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207
2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103
9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25
10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23
19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12
57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — —
115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —

PIC16(L)F1933
25.4.1 AUTO-BAUD DETECT and SPBRGL registers are clocked at 1/8th the BRG
base clock rate. The resulting byte measurement is the
The EUSART module supports automatic detection
average bit time when clocked at full speed.
and calibration of the baud rate.
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the Note 1: If the WUE bit is set with the ABDEN bit,
incoming RX signal, the RX signal is timing the BRG. auto-baud detection will occur on the byte
The Baud Rate Generator is used to time the period of following the Break character (see
a received 55h (ASCII “U”) which is the Sync character Section 25.4.3 “Auto-Wake-up on
for the LIN bus. The unique feature of this character is Break”).
that it has five rising edges including the Stop bit edge. 2: It is up to the user to determine that the
Setting the ABDEN bit of the BAUDCON register starts incoming character baud rate is within the
the auto-baud calibration sequence (Figure 25-6). range of the selected BRG clock source.
While the ABD sequence takes place, the EUSART Some combinations of oscillator frequency
state machine is held in Idle. On the first rising edge of and EUSART baud rates are not possible.
the receive line, after the Start bit, the SPBRG begins 3: During the auto-baud process, the
counting up using the BRG counter clock as shown in auto-baud counter starts counting at 1.
Table 25-6. The fifth rising edge will occur on the RX pin Upon completion of the auto-baud
at the end of the eighth bit period. At that time, an sequence, to achieve maximum accuracy,
accumulated value totaling the proper BRG period is subtract 1 from the SPBRGH:SPBRGL
left in the SPBRGH, SPBRGL register pair, the ABDEN register pair.
bit is automatically cleared and the RCIF interrupt flag
is set. The value in the RCREG needs to be read to TABLE 25-6: BRG COUNTER CLOCK RATES
clear the RCIF interrupt. RCREG content should be
discarded. When calibrating for modes that do not use BRG Base BRG ABD
BRG16 BRGH
the SPBRGH register the user can verify that the Clock Clock
SPBRGL register did not overflow by checking for 00h 0 0 FOSC/64 FOSC/512
in the SPBRGH register.
0 1 FOSC/16 FOSC/128
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in Table 25-6. During ABD, 1 0 FOSC/16 FOSC/128
both the SPBRGH and SPBRGL registers are used as 1 1 FOSC/4 FOSC/32
a 16-bit counter, independent of the BRG16 bit setting.
Note: During the ABD sequence, SPBRGL and
While calibrating the baud rate period, the SPBRGH
SPBRGH registers are both used as a 16-bit
counter, independent of BRG16 setting.
FIGURE 25-6: AUTOMATIC BAUD RATE CALIBRATION
BRG Value XXXXh 0000h 001Ch

Edge #1 Edge #2 Edge #3 Edge #4 Edge #5
RX pin Start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit
BRG Clock
Set by User Auto Cleared

ABDEN bit
RCIDL
RCIF bit
(Interrupt)
Read
RCREG
SPBRGL XXh 1Ch
SPBRGH XXh 00h
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.

PIC16(L)F1933
25.4.2 AUTO-BAUD OVERFLOW 25.4.3.1 Special Considerations
During the course of automatic baud detection, the Break Character
ABDOVF bit of the BAUDCON register will be set if the To avoid character errors or character fragments during
baud rate counter overflows before the fifth rising edge a wake-up event, the wake-up character must be all
is detected on the RX pin. The ABDOVF bit indicates zeros.
that the counter has exceeded the maximum count that
can fit in the 16 bits of the SPBRGH:SPBRGL register When the wake-up is enabled the function works
pair. After the ABDOVF bit has been set, the counter independent of the low time on the data stream. If the
continues to count until the fifth rising edge is detected WUE bit is set and a valid non-zero character is
on the RX pin. Upon detecting the fifth RX edge, the received, the low time from the Start bit to the first rising
hardware will set the RCIF interrupt flag and clear the edge will be interpreted as the wake-up event. The
ABDEN bit of the BAUDCON register. The RCIF flag remaining bits in the character will be received as a
can be subsequently cleared by reading the RCREG fragmented character and subsequent characters can
register. The ABDOVF flag of the BAUDCON register result in framing or overrun errors.
can be cleared by software directly. Therefore, the initial character in the transmission must
To terminate the auto-baud process before the RCIF be all ‘0’s. This must be ten or more bit times, 13-bit
flag is set, clear the ABDEN bit then clear the ABDOVF times recommended for LIN bus, or any number of bit
bit of the BAUDCON register. The ABDOVF bit will times for standard RS-232 devices.
remain set if the ABDEN bit is not cleared first. Oscillator Start-up Time
Oscillator start-up time must be considered, especially
25.4.3 AUTO-WAKE-UP ON BREAK
in applications using oscillators with longer start-up
During Sleep mode, all clocks to the EUSART are intervals (i.e., LP, XT or HS/PLL mode). The Sync
suspended. Because of this, the Baud Rate Generator Break (or wake-up signal) character must be of
is inactive and a proper character reception cannot be sufficient length, and be followed by a sufficient
performed. The Auto-Wake-up feature allows the interval, to allow enough time for the selected oscillator
controller to wake-up due to activity on the RX/DT line. to start and provide proper initialization of the EUSART.
This feature is available only in Asynchronous mode.
WUE Bit
The Auto-Wake-up feature is enabled by setting the
The wake-up event causes a receive interrupt by
WUE bit of the BAUDCON register. Once set, the normal
setting the RCIF bit. The WUE bit is cleared in
receive sequence on RX/DT is disabled, and the
hardware by a rising edge on RX/DT. The interrupt
EUSART remains in an Idle state, monitoring for a
condition is then cleared in software by reading the
wake-up event independent of the CPU mode. A
RCREG register and discarding its contents.
wake-up event consists of a high-to-low transition on the
RX/DT line. (This coincides with the start of a Sync Break To ensure that no actual data is lost, check the RCIDL
or a wake-up signal character for the LIN protocol.) bit to verify that a receive operation is not in process
before setting the WUE bit. If a receive operation is not
The EUSART module generates an RCIF interrupt
occurring, the WUE bit may then be set just prior to
coincident with the wake-up event. The interrupt is
entering the Sleep mode.
generated synchronously to the Q clocks in normal CPU
operating modes (Figure 25-7), and asynchronously if
the device is in Sleep mode (Figure 25-8). The interrupt
condition is cleared by reading the RCREG register.
The WUE bit is automatically cleared by the low-to-high
transition on the RX line at the end of the Break. This
signals to the user that the Break event is over. At this
point, the EUSART module is in Idle mode waiting to
receive the next character.

PIC16(L)F1933
FIGURE 25-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Bit set by user Auto Cleared
WUE bit
RX/DT Line
RCIF
Cleared due to User Read of RCREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
FIGURE 25-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4

OSC1
Bit Set by User Auto Cleared
WUE bit
RX/DT Line Note 1
RCIF
Cleared due to User Read of RCREG
Sleep Command Executed Sleep Ends
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.

PIC16(L)F1933
25.4.4 BREAK CHARACTER SEQUENCE 25.4.5 RECEIVING A BREAK CHARACTER
The EUSART module has the capability of sending the The Enhanced EUSART module can receive a Break
special Break character sequences that are required by character in two ways.
the LIN bus standard. A Break character consists of a The first method to detect a Break character uses the
Start bit, followed by 12 ‘0’ bits and a Stop bit. FERR bit of the RCSTA register and the Received data
To send a Break character, set the SENDB and TXEN as indicated by RCREG. The Baud Rate Generator is
bits of the TXSTA register. The Break character assumed to have been initialized to the expected baud
transmission is then initiated by a write to the TXREG. rate.
The value of data written to TXREG will be ignored and A Break character has been received when;
all ‘0’s will be transmitted.
• RCIF bit is set
The SENDB bit is automatically reset by hardware after
• FERR bit is set
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte • RCREG = 00h
following the Break character (typically, the Sync The second method uses the Auto-Wake-up feature
character in the LIN specification). described in Section 25.4.3 “Auto-Wake-up on
The TRMT bit of the TXSTA register indicates when the Break”. By enabling this feature, the EUSART will
transmit operation is active or Idle, just as it does during sample the next two transitions on RX/DT, cause an
normal transmission. See Figure 25-9 for the timing of RCIF interrupt, and receive the next data byte followed
the Break character sequence. by another interrupt.
Note that following a Break character, the user will
25.4.4.1 Break and Sync Transmit Sequence typically want to enable the Auto-Baud Detect feature.
The following sequence will start a message frame For both methods, the user can set the ABDEN bit of
header made up of a Break, followed by an auto-baud the BAUDCON register before placing the EUSART in
Sync byte. This sequence is typical of a LIN bus Sleep mode.
master.
1. Configure the EUSART for the desired mode.
2. Set the TXEN and SENDB bits to enable the
Break sequence.
3. Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXREG to load the Sync character
into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware and the Sync character is
then transmitted.
When the TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.
FIGURE 25-9: SEND BREAK CHARACTER SEQUENCE
Write to TXREG
Dummy Write
BRG Output
(Shift Clock)
TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit

Break
TXIF bit
(Transmit
Interrupt Flag)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB Sampled Here Auto Cleared
SENDB
(send Break
control bit)

PIC16(L)F1933
25.5 EUSART Synchronous Mode Clearing the SCKP bit sets the Idle state as low. When
the SCKP bit is cleared, the data changes on the rising
Synchronous serial communications are typically used edge of each clock.
in systems with a single master and one or more
slaves. The master device contains the necessary 25.5.1.3 Synchronous Master Transmission
circuitry for baud rate generation and supplies the clock
Data is transferred out of the device on the RX/DT pin.
for all devices in the system. Slave devices can take
The RX/DT and TX/CK pin output drivers are automat-
advantage of the master clock by eliminating the
ically enabled when the EUSART is configured for
internal clock generation circuitry.
synchronous master transmit operation.
There are two signal lines in Synchronous mode: a
A transmission is initiated by writing a character to the
bidirectional data line and a clock line. Slaves use the
TXREG register. If the TSR still contains all or part of a
external clock supplied by the master to shift the serial
previous character the new character data is held in the
data into and out of their respective receive and
TXREG until the last bit of the previous character has
transmit shift registers. Since the data line is
been transmitted. If this is the first character, or the
bidirectional, synchronous operation is half-duplex
previous character has been completely flushed from
only. Half-duplex refers to the fact that master and
the TSR, the data in the TXREG is immediately
slave devices can receive and transmit data, but not
transferred to the TSR. The transmission of the
both simultaneously. The EUSART can operate as
character commences immediately following the
either a master or slave device.
transfer of the data to the TSR from the TXREG.
Start and Stop bits are not used in synchronous
Each data bit changes on the leading edge of the
transmissions.
master clock and remains valid until the subsequent
leading clock edge.
25.5.1 SYNCHRONOUS MASTER MODE
The following bits are used to configure the EUSART Note: The TSR register is not mapped in data
for synchronous master operation: memory, so it is not available to the user.
• SYNC = 1 25.5.1.4 Synchronous Master Transmission
• CSRC = 1 Set-up:
• SREN = 0 (for transmit); SREN = 1 (for receive)
1. Initialize the SPBRGH, SPBRGL register pair
• CREN = 0 (for transmit); CREN = 1 (for receive) and the BRGH and BRG16 bits to achieve the
• SPEN = 1 desired baud rate (see Section 25.4 “EUSART
Setting the SYNC bit of the TXSTA register configures Baud Rate Generator (BRG)”).
the device for synchronous operation. Setting the CSRC 2. Enable the synchronous master serial port by
bit of the TXSTA register configures the device as a setting bits SYNC, SPEN and CSRC.
master. Clearing the SREN and CREN bits of the RCSTA 3. Disable Receive mode by clearing bits SREN
register ensures that the device is in the Transmit mode, and CREN.
otherwise the device will be configured to receive. Setting 4. Enable Transmit mode by setting the TXEN bit.
the SPEN bit of the RCSTA register enables the
5. If 9-bit transmission is desired, set the TX9 bit.
EUSART.
6. If interrupts are desired, set the TXIE bit of the
25.5.1.1 Master Clock PIE1 register and the GIE and PEIE bits of the
INTCON register.
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device config- 7. If 9-bit transmission is selected, the ninth bit
ured as a master transmits the clock on the TX/CK line. should be loaded in the TX9D bit.
The TX/CK pin output driver is automatically enabled 8. Start transmission by loading data to the TXREG
when the EUSART is configured for synchronous register.
transmit or receive operation. Serial data bits change
on the leading edge to ensure they are valid at the
trailing edge of each clock. One clock cycle is
generated for each data bit. Only as many clock cycles
are generated as there are data bits.
25.5.1.2 Clock Polarity

A clock polarity option is provided for Microwire
compatibility. Clock polarity is selected with the SCKP
bit of the BAUDCON register. Setting the SCKP bit sets
the clock Idle state as high. When the SCKP bit is set,
the data changes on the falling edge of each clock.

PIC16(L)F1933
FIGURE 25-10: SYNCHRONOUS TRANSMISSION
RX/DT
pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7
Word 1 Word 2
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
TXREG Reg Write Word 1 Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
‘1’ ‘1’
TXEN bit
Note: Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.
FIGURE 25-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit

PIC16(L)F1933
TABLE 25-7: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
TRANSMISSION
Register
on Page
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.

PIC16(L)F1933
25.5.1.5 Synchronous Master Reception set then the error condition is cleared by either clearing
the CREN bit of the RCSTA register or by clearing the
Data is received at the RX/DT pin. The RX/DT pin
SPEN bit which resets the EUSART.
output driver is automatically disabled when the
EUSART is configured for synchronous master receive
25.5.1.8 Receiving 9-bit Characters
operation.
The EUSART supports 9-bit character reception. When
In Synchronous mode, reception is enabled by setting
the RX9 bit of the RCSTA register is set the EUSART
either the Single Receive Enable bit (SREN of the
will shift 9-bits into the RSR for each character
RCSTA register) or the Continuous Receive Enable bit
received. The RX9D bit of the RCSTA register is the
(CREN of the RCSTA register).
ninth, and Most Significant, data bit of the top unread
When SREN is set and CREN is clear, only as many character in the receive FIFO. When reading 9-bit data
clock cycles are generated as there are data bits in a from the receive FIFO buffer, the RX9D data bit must
single character. The SREN bit is automatically cleared be read before reading the eight Least Significant bits
at the completion of one character. When CREN is set, from the RCREG.
clocks are continuously generated until CREN is
cleared. If CREN is cleared in the middle of a character 25.5.1.9 Synchronous Master Reception
the CK clock stops immediately and the partial character Set-up:
is discarded. If SREN and CREN are both set, then
1. Initialize the SPBRGH, SPBRGL register pair for
SREN is cleared at the completion of the first character
the appropriate baud rate. Set or clear the
and CREN takes precedence.
BRGH and BRG16 bits, as required, to achieve
To initiate reception, set either SREN or CREN. Data is the desired baud rate.
sampled at the RX/DT pin on the trailing edge of the 2. Clear the ANSEL bit for the RX pin (if applicable).
TX/CK clock pin and is shifted into the Receive Shift
3. Enable the synchronous master serial port by
Register (RSR). When a complete character is
setting bits SYNC, SPEN and CSRC.
received into the RSR, the RCIF bit is set and the
character is automatically transferred to the two 4. Ensure bits CREN and SREN are clear.
character receive FIFO. The Least Significant eight bits 5. If interrupts are desired, set the RCIE bit of the
of the top character in the receive FIFO are available in PIE1 register and the GIE and PEIE bits of the
RCREG. The RCIF bit remains set as long as there are INTCON register.
unread characters in the receive FIFO. 6. If 9-bit reception is desired, set bit RX9.
7. Start reception by setting the SREN bit or for
25.5.1.6 Slave Clock continuous reception, set the CREN bit.
Synchronous data transfers use a separate clock line, 8. Interrupt flag bit RCIF will be set when reception
which is synchronous with the data. A device configured of a character is complete. An interrupt will be
as a slave receives the clock on the TX/CK line. The generated if the enable bit RCIE was set.
TX/CK pin output driver is automatically disabled when 9. Read the RCSTA register to get the ninth bit (if
the device is configured for synchronous slave transmit enabled) and determine if any error occurred
or receive operation. Serial data bits change on the during reception.
leading edge to ensure they are valid at the trailing edge
10. Read the 8-bit received data by reading the
of each clock. One data bit is transferred for each clock
RCREG register.
cycle. Only as many clock cycles should be received as
there are data bits. 11. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
25.5.1.7 Receive Overrun Error register or by clearing the SPEN bit which resets
the EUSART.
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before RCREG is read to access
the FIFO. When this happens, the OERR bit of the
RCSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
buffer can be read, however, no additional characters
will be received until the error is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear then the error is cleared by reading
RCREG. If the overrun occurred when the CREN bit is

PIC16(L)F1933
FIGURE 25-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RX/DT
pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit ‘0’ ‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 25-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER

RECEPTION
Register
on Page
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.

PIC16(L)F1933
25.5.2 SYNCHRONOUS SLAVE MODE If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
The following bits are used to configure the EUSART
for synchronous slave operation: 1. The first character will immediately transfer to
the TSR register and transmit.
• SYNC = 1
2. The second word will remain in TXREG register.
• CSRC = 0
3. The TXIF bit will not be set.
• SREN = 0 (for transmit); SREN = 1 (for receive)
4. After the first character has been shifted out of
• CREN = 0 (for transmit); CREN = 1 (for receive)
TSR, the TXREG register will transfer the second
• SPEN = 1 character to the TSR and the TXIF bit will now be
Setting the SYNC bit of the TXSTA register configures the set.
device for synchronous operation. Clearing the CSRC bit 5. If the PEIE and TXIE bits are set, the interrupt
of the TXSTA register configures the device as a slave. will wake the device from Sleep and execute the
Clearing the SREN and CREN bits of the RCSTA register next instruction. If the GIE bit is also set, the
ensures that the device is in the Transmit mode, program will call the Interrupt Service Routine.
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the 25.5.2.2 Synchronous Slave Transmission
EUSART. Set-up:
25.5.2.1 EUSART Synchronous Slave 1. Set the SYNC and SPEN bits and clear the
CSRC bit.
Transmit
2. Clear the ANSEL bit for the CK pin (if applicable).
The operation of the Synchronous Master and Slave
3. Clear the CREN and SREN bits.
modes are identical (see Section 25.5.1.3
“Synchronous Master Transmission”), except in the 4. If interrupts are desired, set the TXIE bit of the
case of the Sleep mode. PIE1 register and the GIE and PEIE bits of the
INTCON register.
5. If 9-bit transmission is desired, set the TX9 bit.
6. Enable transmission by setting the TXEN bit.
7. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
8. Start transmission by writing the Least
Significant eight bits to the TXREG register.
TABLE 25-9: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE

TRANSMISSION
Register
on Page
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.

PIC16(L)F1933
25.5.2.3 EUSART Synchronous Slave 25.5.2.4 Synchronous Slave Reception
Reception Set-up:
The operation of the Synchronous Master and Slave 1. Set the SYNC and SPEN bits and clear the
modes is identical (Section 25.5.1.5 “Synchronous CSRC bit.
Master Reception”), with the following exceptions: 2. Clear the ANSEL bit for both the CK and DT pins
• Sleep (if applicable).
• CREN bit is always set, therefore the receiver is 3. If interrupts are desired, set the RCIE bit of the
never Idle PIE1 register and the GIE and PEIE bits of the
• SREN bit, which is a “don’t care” in Slave mode INTCON register.
4. If 9-bit reception is desired, set the RX9 bit.
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the 5. Set the CREN bit to enable reception.
word is received, the RSR register will transfer the data 6. The RCIF bit will be set when reception is
to the RCREG register. If the RCIE enable bit is set, the complete. An interrupt will be generated if the
interrupt generated will wake the device from Sleep RCIE bit was set.
and execute the next instruction. If the GIE bit is also 7. If 9-bit mode is enabled, retrieve the Most
set, the program will branch to the interrupt vector. Significant bit from the RX9D bit of the RCSTA
register.
8. Retrieve the eight Least Significant bits from the
receive FIFO by reading the RCREG register.
9. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
TABLE 25-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE

RECEPTION
Register
on Page
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.

PIC16(L)F1933
25.6 EUSART Operation During Sleep 25.6.2 SYNCHRONOUS TRANSMIT
DURING SLEEP
The EUSART will remain active during Sleep only in the
Synchronous Slave mode. All other modes require the To transmit during Sleep, all the following conditions
system clock and therefore cannot generate the must be met before entering Sleep mode:
necessary signals to run the Transmit or Receive Shift • RCSTA and TXSTA Control registers must be
registers during Sleep. configured for Synchronous Slave Transmission
Synchronous Slave mode uses an externally generated (see Section 25.5.2.2 “Synchronous Slave
clock to run the Transmit and Receive Shift registers. Transmission Set-up:”).
• The TXIF interrupt flag must be cleared by writing
25.6.1 SYNCHRONOUS RECEIVE DURING the output data to the TXREG, thereby filling the
SLEEP TSR and transmit buffer.
To receive during Sleep, all the following conditions • If interrupts are desired, set the TXIE bit of the
must be met before entering Sleep mode: PIE1 register and the PEIE bit of the INTCON
register.
• RCSTA and TXSTA Control registers must be
configured for Synchronous Slave Reception (see • Interrupt enable bits TXIE of the PIE1 register and
Section 25.5.2.4 “Synchronous Slave PEIE of the INTCON register must set.
Reception Set-up:”). Upon entering Sleep mode, the device will be ready to
• If interrupts are desired, set the RCIE bit of the accept clocks on TX/CK pin and transmit data on the
PIE1 register and the GIE and PEIE bits of the RX/DT pin. When the data word in the TSR has been
INTCON register. completely clocked out by the external device, the
• The RCIF interrupt flag must be cleared by pending byte in the TXREG will transfer to the TSR and
reading RCREG to unload any pending the TXIF flag will be set. Thereby, waking the processor
characters in the receive buffer. from Sleep. At this point, the TXREG is available to
accept another character for transmission, which will
Upon entering Sleep mode, the device will be ready to clear the TXIF flag.
accept data and clocks on the RX/DT and TX/CK pins,
respectively. When the data word has been completely Upon waking from Sleep, the instruction following the
clocked in by the external device, the RCIF interrupt SLEEP instruction will be executed. If the Global
flag bit of the PIR1 register will be set. Thereby, waking Interrupt Enable (GIE) bit is also set then the Interrupt
the processor from Sleep. Service Routine at address 0004h will be called.
Upon waking from Sleep, the instruction following the

SLEEP instruction will be executed. If the Global
Interrupt Enable (GIE) bit of the INTCON register is
also set, then the Interrupt Service Routine at address
004h will be called.

PIC16(L)F1933
26.0 CAPACITIVE SENSING (CPS)
MODULE
The Capacitive Sensing (CPS) module allows for an
interaction with an end user without a mechanical
interface. In a typical application, the CPS module is
attached to a pad on a Printed Circuit Board (PCB),
which is electrically isolated from the end user. When the
end user places their finger over the PCB pad, a
capacitive load is added, causing a frequency shift in the
CPS module. The CPS module requires software and at
least one timer resource to determine the change in
frequency. Key features of this module include:
• Analog MUX for monitoring multiple inputs
• Capacitive sensing oscillator
• Multiple current ranges
• Multiple voltage reference modes
• Multiple timer resources
• Software control
• Operation during Sleep
FIGURE 26-1: CAPACITIVE SENSING BLOCK DIAGRAM
Timer0 Module
Set
TMR0CS TMR0IF
T0XCS
FOSC/4 0
Overflow
T0CKI 0 TMR0
CPSCH<2:0>
1
CPSON(1) 1
CPSRNG<1:0>
CPS0 CPSON
CPS1
CPS2 Capacitive
CPS3 Sensing Timer1 Module
Oscillator
CPS4 T1CS<1:0>
CPS5 CPSOSC
FOSC
CPS6 FOSC/4
Int. CPSCLK
CPS7 0
Ref. T1OSC/ TMR1H:TMR1L
Ref- EN
1 T1CKI
DAC
Output 0 T1GSEL<1:0>
Ref+
T1G
1 FVR
Timer1 Gate
sync_C1OUT Control Logic
CPSOUT sync_C2OUT
CPSRM
Note 1: If CPSON = 0, disabling capacitive sensing, no channel is selected.

PIC16(L)F1933
FIGURE 26-2: CAPACITIVE SENSING OSCILLATOR BLOCK DIAGRAM
Oscillator Module
VDD
(1)
(2)
+
-
S Q CPSCLK
CPSx
Analog Pin (1) (2) R

-
+
Internal
References
0 0
Ref- Ref+
1 DAC 1 FVR
CPSRM
Note 1: Module enable, voltage reference mode, and current range selections are not shown.
2: Comparators remain active in Noise Detection mode.

PIC16(L)F1933
26.1 Analog MUX 26.3 Voltage Reference Modes
The CPS module can monitor up to 16 inputs. The The capacitive sensing oscillator uses voltage refer-
capacitive sensing inputs are defined as CPS<15:0>. ences to provide two voltage thresholds for oscillation.
To determine if a frequency change has occurred the The upper voltage threshold is referred to as Ref+ and
user must: the lower voltage threshold is referred to as Ref-.
• Select the appropriate CPS pin by setting the The user can elect to use Fixed Voltage References,
CPSCH<2:0> bits of the CPSCON1 register. which are internal to the capacitive sensing oscillator,
• Set the corresponding ANSEL bit. or variable voltage references, which are supplied by
• Set the corresponding TRIS bit. the Fixed Voltage Reference (FVR) module and the
Digital-to-Analog Converter (DAC) module.
• Run the software algorithm.
When the Fixed Voltage References are used, the VSS
Selection of the CPSx pin while the module is enabled
voltage determines the lower threshold level (Ref-) and
will cause the capacitive sensing oscillator to be on the
the VDD voltage determines the upper threshold level
CPSx pin. Failure to set the corresponding ANSEL and
(Ref+).
TRIS bits can cause the capacitive sensing oscillator to
stop, leading to false frequency readings. When the variable voltage references are used, the
DAC voltage determines the lower threshold level
26.2 Capacitive Sensing Oscillator (Ref-) and the FVR voltage determines the upper
threshold level (Ref+). An advantage of using these
The capacitive sensing oscillator consists of a constant reference sources is that oscillation frequency remains
current source and a constant current sink, to produce constant with changes in VDD.
a triangle waveform. The CPSOUT bit of the Different oscillation frequencies can be obtained
CPSCON0 register shows the status of the capacitive through the use of these variable voltage references.
sensing oscillator, whether it is a sinking or sourcing The more the upper voltage reference level is lowered
current. The oscillator is designed to drive a capacitive and the more the lower voltage reference level is
load (single PCB pad) and at the same time, be a clock raised, the higher the capacitive sensing oscillator
source to either Timer0 or Timer1. The oscillator has frequency becomes.
several different current settings as defined by
CPSRNG<1:0> of the CPSCON0 register. The different Selection between the voltage references is controlled
current settings for the oscillator serve two purposes: by the CPSRM bit of the CPSCON0 register. Setting
this bit selects the variable voltage references and
• Maximize the number of counts in a timer for a clearing this bit selects the fixed voltage references.
fixed time base.
Please see Section 14.0 “Fixed Voltage Reference
• Maximize the count differential in the timer during
(FVR)” and Section 17.0 “Digital-to-Analog Converter
a change in frequency.
(DAC) Module” for more information on configuring the
variable voltage levels.

PIC16(L)F1933
26.4 Current Ranges The Noise Detection mode is unique in that it disables
the constant current source associated with the selected
The capacitive sensing oscillator can operate within input pin, but leaves the rest of the oscillator circuitry and
different current ranges, depending on the voltage pin structure active. This eliminates the oscillation
reference mode and current range selections. frequency on the analog pin and greatly reduces the
Within each of the two voltage reference modes, there current consumed by the oscillator module. When noise
are four current ranges. Selection between the voltage is introduced onto the pin, the oscillator is driven at the
reference modes is controlled by the CPSRM bit of the frequency determined by the noise. This produces a
CPSCON0 register. Clearing this bit selects the fixed detectable signal at the comparator stage, indicating the
voltage references provided by the capacitive sensing presence of activity on the pin.
oscillator module. Setting this bit selects the variable Figure 26-2 shows a more detailed drawing of the
voltage references supplied by the Fixed Voltage constant current sources and comparators associated
Reference (FVR) module and the Digital-to-Analog with the oscillator and input pin.
Converter (DAC) module. See Section Section 26.3
“Voltage Reference Modes” for more information on
configuring the voltage references.
Selecting the current range within the voltage reference
mode is controlled by configuring the CPSRNG<1:0>
bits in the CPSCON0 register. See Table 26-1 for proper
current mode selection.
TABLE 26-1: CURRENT RANGE MODE SELECTION

CPSRM Voltage Reference Mode CPSRNG<1:0> Current Range(1)
00 Noise Detection
01 Low
1 Variable
10 Medium
11 High
00 Off
01 Low
0 Fixed
10 Medium
11 High
Note 1: See Power-Down Currents (IPD) in Section 30.0 “Electrical Specifications” for more information.

PIC16(L)F1933
26.5 Timer Resources 26.7 Software Control
To measure the change in frequency of the capacitive The software portion of the capacitive sensing module
sensing oscillator, a fixed time base is required. For the is required to determine the change in frequency of the
period of the fixed time base, the capacitive sensing capacitive sensing oscillator. This is accomplished by
oscillator is used to clock either Timer0 or Timer1. The the following:
frequency of the capacitive sensing oscillator is equal • Setting a fixed time base to acquire counts on
to the number of counts in the timer divided by the Timer0 or Timer1.
period of the fixed time base.
• Establishing the nominal frequency for the
capacitive sensing oscillator.
26.6 Fixed Time Base
• Establishing the reduced frequency for the
To measure the frequency of the capacitive sensing capacitive sensing oscillator due to an additional
oscillator, a fixed time base is required. Any timer capacitive load.
resource or software loop can be used to establish the • Set the frequency threshold.
fixed time base. It is up to the end user to determine the
method in which the fixed time base is generated. 26.7.1 NOMINAL FREQUENCY
(NO CAPACITIVE LOAD)
Note: The fixed time base can not be generated
by the timer resource that the capacitive To determine the nominal frequency of the capacitive
sensing oscillator is clocking. sensing oscillator:
• Remove any extra capacitive load on the selected
26.6.1 TIMER0 CPSx pin.
To select Timer0 as the timer resource for the capacitive • At the start of the fixed time base, clear the timer
sensing module: resource.
• Set the T0XCS bit of the CPSCON0 register. • At the end of the fixed time base save the value in
• Clear the TMR0CS bit of the OPTION_REG the timer resource.
register. The value of the timer resource is the number of
When Timer0 is chosen as the timer resource, the oscillations of the capacitive sensing oscillator for the
capacitive sensing oscillator will be the clock source for given time base. The frequency of the capacitive
Timer0. Refer to Section 20.0 “Timer0 Module” for sensing oscillator is equal to the number of counts on
additional information. in the timer divided by the period of the fixed time base.
26.6.2 TIMER1 26.7.2 REDUCED FREQUENCY

(ADDITIONAL CAPACITIVE LOAD)
To select Timer1 as the timer resource for the
Capacitive Sensing module, set the TMR1CS<1:0> of The extra capacitive load will cause the frequency of the
the T1CON register to ‘11’. When Timer1 is chosen as capacitive sensing oscillator to decrease. To determine
the timer resource, the capacitive sensing oscillator will the reduced frequency of the capacitive sensing
be the clock source for Timer1. Because the Timer1 oscillator:
module has a gate control, developing a time base for • Add a typical capacitive load on the selected
the frequency measurement can be simplified by using CPSx pin.
the Timer0 overflow flag. • Use the same fixed time base as the nominal
It is recommend that the Timer0 overflow flag, in con- frequency measurement.
junction with the Toggle mode of the Timer1 gate, be • At the start of the fixed time base, clear the timer
used to develop the fixed time base required by the resource.
software portion of the Capacitive Sensing module. • At the end of the fixed time base save the value in
Refer to Section 21.11 “Register Definitions: Timer1 the timer resource.
Control” for additional information.
The value of the timer resource is the number of oscil-
lations of the capacitive sensing oscillator with an addi-
TABLE 26-2: TIMER1 ENABLE FUNCTION
tional capacitive load. The frequency of the capacitive
TMR1ON TMR1GE Timer1 Operation sensing oscillator is equal to the number of counts on
0 0 Off in the timer divided by the period of the fixed time base.
This frequency should be less than the value obtained
0 1 Off during the nominal frequency measurement.
1 0 On
1 1 Count Enabled by input

PIC16(L)F1933
26.7.3 FREQUENCY THRESHOLD
The frequency threshold should be placed midway
between the value of nominal frequency and the
reduced frequency of the capacitive sensing oscillator.
Refer to Application Note AN1103, “Software Handling
for Capacitive Sensing” (DS01103) for more detailed
information on the software required for the capacitive
sensing module.
Note: For more information on general capacitive
sensing refer to Application Notes:
• AN1101, “Introduction to Capacitive
Sensing” (DS01101)
• AN1102, “Layout and Physical
Design Guidelines for Capacitive
Sensing” (DS01102)
26.8 Operation during Sleep

The capacitive sensing oscillator will continue to run as
long as the module is enabled, independent of the part
being in Sleep. In order for the software to determine if
a frequency change has occurred, the part must be
awake. However, the part does not have to be awake
when the timer resource is acquiring counts.
Note: Timer0 does not operate when in Sleep,
and therefore cannot be used for
capacitive sense measurements in Sleep.

PIC16(L)F1933
26.9 Register Definitions: CPS Control
REGISTER 26-1: CPSCON0: CAPACITIVE SENSING CONTROL REGISTER 0

R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R-0/0 R/W-0/0
CPSON CPSRM — — CPSRNG<1:0> CPSOUT T0XCS
bit 7 bit 0
Legend:
bit 7 CPSON: CPS Module Enable bit

1 = CPS module is enabled
0 = CPS module is disabled
bit 6 CPSRM: Capacitive Sensing Reference Mode bit
1 = Capacitive sensing module is in Variable Voltage Reference mode
0 = Capacitive sensing module is in Fixed Voltage Reference mode
bit 3-2 CPSRNG<1:0>: Capacitive Sensing Current Range
If CPSRM = 1 (Variable Voltage Reference mode):

11 = Oscillator is in high-current range
10 = Oscillator is in medium-current range
01 = Oscillator is in low-current range
00 = Oscillator is on. Noise Detection mode
If CPSRM = 0 (Fixed Voltage Reference mode):

11 = Oscillator is in high-current range
10 = Oscillator is in medium-current range
01 = Oscillator is in low-current range
00 = Oscillator is off
bit 1 CPSOUT: Capacitive Sensing Oscillator Status bit
1 = Oscillator is sourcing current (Current flowing out of the pin)
0 = Oscillator is sinking current (Current flowing into the pin)
bit 0 T0XCS: Timer0 External Clock Source Select bit
If TMR0CS = 1:
The T0XCS bit controls which clock external to the core/Timer0 module supplies Timer0:
1 = Timer0 clock source is the capacitive sensing oscillator, CPSLK
0 = Timer0 clock source is the T0CKI pin
If TMR0CS = 0:
Timer0 clock source is controlled by the core/Timer0 module and is FOSC/4

PIC16(L)F1933
REGISTER 26-2: CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1

U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — — CPSCH<2:0>
bit 7 bit 0
Legend:

bit 2-0 CPSCH<2:0>: Capacitive Sensing Channel Select bits
If CPSON = 0:
These bits are ignored. No channel is selected.
If CPSON = 1:
000 = channel 0, (CPS0)
TABLE 26-3: SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
CPSCON1 — — — — — CPSCH<2:0> 312
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 173
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the CPS module.

PIC16(L)F1933
27.0 LIQUID CRYSTAL DISPLAY
(LCD) DRIVER MODULE Note: COM3 and SEG15 share the same physical
pin on the PIC16(L)F1933, therefore
The Liquid Crystal Display (LCD) driver module
SEG15 is not available when using 1/4
generates the timing control to drive a static or
multiplex displays.
multiplexed LCD panel. In the PIC16(L)F1933 device,
the module drives the panels of up to four commons
and up to 24 segments. The LCD module also provides
control of the LCD pixel data.
The LCD driver module supports:
• Direct driving of LCD panel
• Three LCD clock sources with selectable prescaler
• Up to four common pins:
- Static (1 common)
- 1/2 multiplex (2 commons)
• Segment pins up to:
- 16 (PIC16(L)F1933)
• Static, 1/2 or 1/3 LCD Bias
FIGURE 27-1: LCD DRIVER MODULE BLOCK DIAGRAM
LCDDATAx SEG<15:0>(1, 2)
Data Bus
MUX To I/O Pads(1)
Registers
Timing Control
LCDCON
COM<3:0>(2)
LCDPS To I/O Pads(1)
LCDSEn
FOSC/256
Clock Source
T1OSC
Select and
Prescaler
LFINTOSC
Note 1: These are not directly connected to the I/O pads, but may be tri-stated, depending on the configuration of
the LCD module.
2: COM3 and SEG15 share the same physical pin on the PIC16(L)F1933, therefore SEG15 is not available
when using 1/4 multiplex displays.

PIC16(L)F1933
27.1 LCD Registers TABLE 27-1: LCD SEGMENT AND DATA
REGISTERS
The module contains the following registers:
# of LCD Registers
• LCD Control register (LCDCON)
Device Segment
• LCD Phase register (LCDPS) Data
• LCD Reference Ladder register (LCDRL) Enable
• LCD Contrast Control register (LCDCST) PIC16(L)F1933 2 8
• LCD Reference Voltage Control register The LCDCON register (Register 27-1) controls the
(LCDREF) operation of the LCD driver module. The LCDPS
• Up to 3 LCD Segment Enable registers (LCDSEn) register (Register 27-2) configures the LCD clock
• Up to 12 LCD data registers (LCDDATAn) source prescaler and the type of waveform; Type-A or
Type-B. The LCDSEn registers (Register 27-5)
configure the functions of the port pins.
The following LCDSEn registers are available:
• LCDSE0 SE<7:0>
• LCDSE1 SE<15:8>
Once the module is initialized for the LCD panel, the
individual bits of the LCDDATAn registers are
cleared/set to represent a clear/dark pixel, respectively:
• LCDDATA0 SEG<7:0>COM0
As an example, LCDDATAn is detailed in
Register 27-6.
Once the module is configured, the LCDEN bit of the
LCDCON register is used to enable or disable the LCD
module. The LCD panel can also operate during Sleep
by clearing the SLPEN bit of the LCDCON register.

PIC16(L)F1933
27.2 Register Definitions: Liquid Crystal Display (LCD) Control
REGISTER 27-1: LCDCON: LIQUID CRYSTAL DISPLAY (LCD) CONTROL REGISTER
R/W-0/0 R/W-0/0 R/C-0/0 U-0 R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1
LCDEN SLPEN WERR — CS<1:0> LMUX<1:0>
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared C = Only clearable bit
bit 7 LCDEN: LCD Driver Enable bit

1 = LCD driver module is enabled
0 = LCD driver module is disabled
bit 6 SLPEN: LCD Driver Enable in Sleep Mode bit
1 = LCD driver module is disabled in Sleep mode
0 = LCD driver module is enabled in Sleep mode
bit 5 WERR: LCD Write Failed Error bit
1 = LCDDATAn register written while the WA bit of the LCDPS register = 0 (must be cleared in
software)
0 = No LCD write error
bit 3-2 CS<1:0>: Clock Source Select bits
00 = FOSC/256
01 = T1OSC (Timer1)
1x = LFINTOSC (31 kHz)
bit 1-0 LMUX<1:0>: Commons Select bits
Maximum Number of Pixels

LMUX<1:0> Multiplex Bias
PIC16(L)F1933
00 Static (COM0) 16 Static
01 1/2 (COM<1:0>) 32 1/2 or 1/3
10 1/3 (COM<2:0>) 48 1/2 or 1/3
(1)
11 1/4 (COM<3:0>) 60 1/3
Note 1: On these devices, COM3 and SEG15 are shared on one pin, limiting the device from driving 64 pixels.

PIC16(L)F1933
REGISTER 27-2: LCDPS: LCD PHASE REGISTER

R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1
WFT BIASMD LCDA WA LP<3:0>
bit 7 bit 0
Legend:
bit 7 WFT: Waveform Type bit

1 = Type-B phase changes on each frame boundary
0 = Type-A phase changes within each common type
bit 6 BIASMD: Bias Mode Select bit
When LMUX<1:0> = 00:
0 = Static Bias mode (do not set this bit to ‘1’)
1 = 1/2 Bias mode
0 = 1/3 Bias mode
1 = 1/2 Bias mode
0 = 1/3 Bias mode
0 = 1/3 Bias mode (do not set this bit to ‘1’)
bit 5 LCDA: LCD Active Status bit
1 = LCD driver module is active
0 = LCD driver module is inactive
bit 4 WA: LCD Write Allow Status bit
1 = Writing to the LCDDATAn registers is allowed
0 = Writing to the LCDDATAn registers is not allowed
bit 3-0 LP<3:0>: LCD Prescaler Selection bits
1111 = 1:16
1110 = 1:15
1101 = 1:14
1100 = 1:13
1011 = 1:12
1010 = 1:11
1001 = 1:10
1000 = 1:9
0111 = 1:8
0110 = 1:7
0101 = 1:6
0100 = 1:5
0011 = 1:4
0010 = 1:3
0001 = 1:2
0000 = 1:1

PIC16(L)F1933
REGISTER 27-3: LCDREF: LCD REFERENCE VOLTAGE CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0
LCDIRE LCDIRS LCDIRI — VLCD3PE VLCD2PE VLCD1PE —
bit 7 bit 0
Legend:
bit 7 LCDIRE: LCD Internal Reference Enable bit

1 = Internal LCD Reference is enabled and connected to the Internal Contrast Control circuit
0 = Internal LCD Reference is disabled
bit 6 LCDIRS: LCD Internal Reference Source bit
If LCDIRE = 1:
0 = Internal LCD Contrast Control is powered by VDD
1 = Internal LCD Contrast Control is powered by a 3.072V output of the FVR
If LCDIRE = 0:
Internal LCD Contrast Control is unconnected. LCD bandgap buffer is disabled.
bit 5 LCDIRI: LCD Internal Reference Ladder Idle Enable bit
Allows the Internal FVR buffer to shut down when the LCD Reference Ladder is in power mode ‘B’
1 = When the LCD Reference Ladder is in power mode ‘B’, the LCD Internal FVR buffer is disabled
0 = The LCD Internal FVR Buffer ignores the LCD Reference Ladder power mode
bit 3 VLCD3PE: VLCD3 Pin Enable bit
1 = The VLCD3 pin is connected to the internal bias voltage LCDBIAS3(1)
0 = The VLCD3 pin is not connected
Note 1: Normal pin controls of TRISx and ANSELx are unaffected.

PIC16(L)F1933
REGISTER 27-4: LCDCST: LCD CONTRAST CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — — LCDCST<2:0>
bit 7 bit 0
Legend:

bit 2-0 LCDCST<2:0>: LCD Contrast Control bits
Selects the resistance of the LCD contrast control resistor ladder
Bit Value = Resistor ladder
000 = Minimum Resistance (Maximum contrast). Resistor ladder is shorted.
001 = Resistor ladder is at 1/7th of maximum resistance
111 = Resistor ladder is at maximum resistance (Minimum contrast)

PIC16(L)F1933
REGISTER 27-5: LCDSEn: LCD SEGMENT ENABLE REGISTERS

SEn SEn SEn SEn SEn SEn SEn SEn
bit 7 bit 0
Legend:
bit 7-0 SEn: Segment Enable bits

1 = Segment function of the pin is enabled
0 = I/O function of the pin is enabled
REGISTER 27-6: LCDDATAn: LCD DATA REGISTERS

SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy
bit 7 bit 0
Legend:
bit 7-0 SEGx-COMy: Pixel On bits

1 = Pixel on (dark)
0 = Pixel off (clear)

PIC16(L)F1933
27.3 LCD Clock Source Selection Using bits CS<1:0> of the LCDCON register can select
any of these clock sources.
The LCD module has three possible clock sources:
• FOSC/256 27.3.1 LCD PRESCALER
• T1OSC A 4-bit counter is available as a prescaler for the LCD
• LFINTOSC clock. The prescaler is not directly readable or writable;
its value is set by the LP<3:0> bits of the LCDPS register,
The first clock source is the system clock divided by
which determine the prescaler assignment and prescale
256 (FOSC/256). This divider ratio is chosen to provide
ratio.
about 1 kHz output when the system clock is 8 MHz.
The divider is not programmable. Instead, the LCD The prescale values are selectable from 1:1 through
prescaler bits LP<3:0> of the LCDPS register are used 1:16.
to set the LCD frame clock rate.
The second clock source is the T1OSC. This also gives
about 1 kHz when a 32.768 kHz crystal is used with the
Timer1 oscillator. To use the Timer1 oscillator as a
clock source, the T1OSCEN bit of the T1CON register
should be set.
The third clock source is the 31 kHz LFINTOSC, which
provides approximately 1 kHz output.
The second and third clock sources may be used to
continue running the LCD while the processor is in
Sleep.
FIGURE 27-2: LCD CLOCK GENERATION
COM0
COM1
COM2
COM3
FOSC ÷256 To Ladder
Power Control
÷4 Static
T1OSC 32 kHz
Crystal Osc. 4-bit Prog Segment ÷1, 2, 3, 4
÷2 1/2 ÷ 32
Prescaler Counter Clock Ring Counter
1/3,
LFINTOSC 1/4
Nominal = 31 kHz
LP<3:0>
CS<1:0>
LMUX<1:0>

PIC16(L)F1933
27.4 LCD Bias Voltage Generation TABLE 27-2: LCD BIAS VOLTAGES
The LCD module can be configured for one of three Static Bias 1/2 Bias 1/3 Bias
bias types: LCD Bias 0 VSS VSS VSS
• Static Bias (two voltage levels: VSS and VLCD) LCD Bias 1 — 1/2 VDD 1/3 VDD
• 1/2 Bias (three voltage levels: VSS, 1/2 VLCD and LCD Bias 2 — 1/2 VDD 2/3 VDD
VLCD) LCD Bias 3 VLCD3 VLCD3 VLCD3
• 1/3 Bias (four voltage levels: VSS, 1/3 VLCD, So that the user is not forced to place external compo-
2/3 VLCD and VLCD) nents and use up to three pins for bias voltage generation,
internal contrast control and an internal reference ladder
are provided internally to the PIC16(L)F1933. Both of
these features may be used in conjunction with the
external VLCD<3:1> pins, to provide maximum flexibility.
Refer to Figure 27-3.
FIGURE 27-3: LCD BIAS VOLTAGE GENERATION BLOCK DIAGRAM
VDD LCDIRE
LCDIRS
LCDA
1.024V from
FVR 3.072V
x3
LCDIRE LCDRLP1
LCDIRS LCDRLP0
LCDA
LCDCST<2:0>
VLCD3PE LCDA
VLCD3
lcdbias3
VLCD2PE
VLCD2
lcdbias2
BIASMD
VLCD1PE
VLCD1
lcdbias1
lcdbias0

PIC16(L)F1933
27.5 LCD Bias Internal Reference 27.5.2 POWER MODES
Ladder The internal reference ladder may be operated in one of
three power modes. This allows the user to trade off LCD
The internal reference ladder can be used to divide the
contrast for power in the specific application. The larger
LCD bias voltage two or three equally spaced voltages
the LCD glass, the more capacitance is present on a
that will be supplied to the LCD segment pins. To create
physical LCD segment, requiring more current to
this, the reference ladder consists of three matched
maintain the same contrast level.
resistors. Refer to Figure 27-3.
Three different power modes are available, LP, MP and
27.5.1 BIAS MODE INTERACTION HP. The internal reference ladder can also be turned off
When in 1/2 bias mode (BIASMD = 1), then the middle for applications that wish to provide an external ladder
resistor of the ladder is shorted out so that only two or to minimize power consumption. Disabling the
voltages are generated. The current consumption of the internal reference ladder results in all of the ladders
ladder is higher in this mode, with the one resistor being disconnected, allowing external voltages to be
removed. supplied.
Whenever the LCD module is inactive (LCDA = 0), the
TABLE 27-3: LCD INTERNAL LADDER internal reference ladder will be turned off.
POWER MODES (1/3 BIAS)
Power Nominal Resistance of Nominal
Mode Entire Ladder IDD
Low 3 Mohm 1 µA
Medium 300 kohm 10 µA
High 30 kohm 100 µA

PIC16(L)F1933
27.5.3 AUTOMATIC POWER MODE The LCDRL register allows switching between two
SWITCHING power modes, designated ‘A’ and ‘B’. ‘A’ power mode
is active for a programmable time, beginning at the
As an LCD segment is electrically only a capacitor,
time when the LCD segments transition. ‘B’ power
current is drawn only during the interval where the
mode is the remaining time before the segments or
voltage is switching. To minimize total device current,
commons change again. The LRLAT<2:0> bits select
the LCD internal reference ladder can be operated in a
how long, if any, that the ‘A’ power mode is active.
different power mode for the transition portion of the
Refer to Figure 27-4.
duration. This is controlled by the LCDRL Register
(Register 27-7). To implement this, the 5-bit prescaler used to divide
the 32 kHz clock down to the LCD controller’s 1 kHz
base rate is used to select the power mode.
FIGURE 27-4: LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM –
TYPE A
Single Segment Time
32 kHz Clock
Ladder Power
Control ‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07 ‘H0E ‘H0F ‘H00 ‘H01
Segment Clock
LRLAT<2:0> ‘H3
Segment Data
LRLAT<2:0>
Power Mode Power Mode A Power Mode B Mode A
COM0
V1
V0
V1
SEG0 V0
V1
COM0-SEG0 V0
-V1

DS41575C-page 324
PIC16(L)F1933
TYPE A WAVEFORM (1/2 MUX, 1/2 BIAS DRIVE)
Single Segment Time Single Segment Time
32 kHz Clock
Ladder Power
Control ‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07 ‘H0E ‘H0F ‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07 ‘H0E ‘H0F
Segment Clock
Segment Data
Power Mode Power Mode A Power Mode B Power Mode A Power Mode B
LRLAT<2:0> = 011 LRLAT<2:0> = 011

V2
V1
COM0-SEG0 V0
-V1
-V2
TYPE B WAVEFORM (1/2 MUX, 1/2 BIAS DRIVE)
Single Segment Time Single Segment Time Single Segment Time Single Segment Time
32 kHz Clock
Ladder Power
Control ‘H00 ‘H01 ‘H02 ‘H03 ‘H0E ‘H0F ‘H10 ‘H11 ‘H12 ‘H13 ‘H1E ‘H1F ‘H00 ‘H01 ‘H02 ‘H03 ‘H0E ‘H0F ‘H10 ‘H11 ‘H12 ‘H13 ‘H1E ‘H1F
Segment Clock
Segment Data
Power Mode Power Mode A Power Mode B Power Mode A Power Mode B Power Mode A Power Mode B Power Mode A Power Mode B
LRLAT<2:0> = 011 LRLAT<2:0> = 011 LRLAT<2:0> = 011 LRLAT<2:0> = 011
V2
V1
COM0-SEG0 V0
-V1
PIC16(L)F1933
-V2
DS41575C-page 325
PIC16(L)F1933
REGISTER 27-7: LCDRL: LCD REFERENCE LADDER CONTROL REGISTERS

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
LRLAP<1:0> LRLBP<1:0> — LRLAT<2:0>
bit 7 bit 0
Legend:
bit 7-6 LRLAP<1:0>: LCD Reference Ladder A Time Power Control bits
During Time interval A (Refer to Figure 27-4):
00 = Internal LCD Reference Ladder is powered down and unconnected
01 = Internal LCD Reference Ladder is powered in Low-Power mode
10 = Internal LCD Reference Ladder is powered in Medium-Power mode
11 = Internal LCD Reference Ladder is powered in High-Power mode
bit 5-4 LRLBP<1:0>: LCD Reference Ladder B Time Power Control bits
During Time interval B (Refer to Figure 27-4):
00 = Internal LCD Reference Ladder is powered down and unconnected
01 = Internal LCD Reference Ladder is powered in Low-Power mode
10 = Internal LCD Reference Ladder is powered in Medium-Power mode
11 = Internal LCD Reference Ladder is powered in High-Power mode
bit 2-0 LRLAT<2:0>: LCD Reference Ladder A Time Interval Control bits
Sets the number of 32 kHz clocks that the A Time Interval power mode is active
For type A waveforms (WFT = 0):
000 = Internal LCD Reference Ladder is always in ‘B’ Power mode

001 = Internal LCD Reference Ladder is in ‘A’ power mode for 1 clock and ‘B’ power mode for 15 clocks
010 = Internal LCD Reference Ladder is in ‘A’ power mode for 2 clocks and ‘B’ power mode for 14 clocks
For type B waveforms (WFT = 1):
000 = Internal LCD Reference Ladder is always in ‘B’ power mode.

001 = Internal LCD Reference Ladder is in ‘A’ power mode for 1 clock and ‘B’ power mode for 31 clocks

PIC16(L)F1933
27.5.4 CONTRAST CONTROL The contrast control circuit is used to decrease the
output voltage of the signal source by a total of
The LCD contrast control circuit consists of a
approximately 10%, when LCDCST = 111.
seven-tap resistor ladder, controlled by the LCDCST
bits. Refer to Figure 27-7. Whenever the LCD module is inactive (LCDA = 0), the
contrast control ladder will be turned off (open).
FIGURE 27-7: INTERNAL REFERENCE AND CONTRAST CONTROL BLOCK DIAGRAM
VDDIO 7 Stages
R R R R
3.072V
From FVR Analog

Buffer MUX
7
To top of
Reference Ladder
0
LCDCST<2:0>
3
Internal Reference Contrast Control
27.5.5 INTERNAL REFERENCE 27.5.6 VLCD<3:1> PINS

Under firmware control, an internal reference for the The VLCD<3:1> pins provide the ability for an external
LCD bias voltages can be enabled. When enabled, the LCD bias network to be used instead of the internal
source of this voltage can be either VDDIO or a voltage ladder. Use of the VLCD<3:1> pins does not prevent
3 times the main fixed voltage reference (3.072V). use of the internal ladder. Each VLCD pin has an
When no internal reference is selected, the LCD independent control in the LCDREF register
contrast control circuit is disabled and LCD bias must (Register 27-3), allowing access to any or all of the
be provided externally. LCD Bias signals. This architecture allows for
Whenever the LCD module is inactive (LCDA = 0), the maximum flexibility in different applications
internal reference will be turned off. For example, the VLCD<3:1> pins may be used to add
When the internal reference is enabled and the Fixed capacitors to the internal reference ladder, increasing
Voltage Reference is selected, the LCDIRI bit can be the drive capacity.
used to minimize power consumption by tieing into the For applications where the internal contrast control is
LCD Reference Ladder Automatic power mode insufficient, the firmware can choose to only enable the
switching. When LCDIRI = 1 and the LCD reference VLCD3 pin, allowing an external contrast control circuit
ladder is in power mode ‘B’, the LCD internal FVR to use the internal reference divider.
buffer is disabled.
.
Note: The LCD module automatically turns on the
Fixed Voltage Reference when needed.

PIC16(L)F1933
27.6 LCD Multiplex Types TABLE 27-5: FRAME FREQUENCY
FORMULAS
The LCD driver module can be configured into one of
four multiplex types: Multiplex Frame Frequency =
• Static (only COM0 is used) Static Clock source/(4 x 1 x (LCD Prescaler) x 32))
• 1/2 multiplex (COM<1:0> are used) 1/2 Clock source/(2 x 2 x (LCD Prescaler) x 32))
The LMUX<1:0> bit setting of the LCDCON register Note: Clock source is FOSC/256, T1OSC or
decides which of the LCD common pins are used (see LFINTOSC.
Table 27-4 for details).
If the pin is a digital I/O, the corresponding TRIS bit TABLE 27-6: APPROXIMATE FRAME
controls the data direction. If the pin is a COM drive, FREQUENCY (IN Hz) USING
then the TRIS setting of that pin is overridden. FOSC @ 8 MHz, TIMER1 @
32.768 kHz OR LFINTOSC
TABLE 27-4: COMMON PIN USAGE
LP<3:0> Static 1/2 1/3 1/4
LMUX
Multiplex COM3 COM2 COM1 2 122 122 162 122
<1:0>
Static 00 Unused Unused Unused 3 81 81 108 81
1/2 01 Unused Unused Active 4 61 61 81 61
1/3 10 Unused Active Active 5 49 49 65 49
1/4 11 Active Active Active 6 41 41 54 41
7 35 35 47 35
27.7 Segment Enables
The LCDSEn registers are used to select the pin
function for each segment pin. The selection allows
each pin to operate as either an LCD segment driver or
as one of the pin’s alternate functions. To configure the
pin as a segment pin, the corresponding bits in the
LCDSEn registers must be set to ‘1’.
If the pin is a digital I/O, the corresponding TRIS bit
controls the data direction. Any bit set in the LCDSEn
registers overrides any bit settings in the corresponding
TRIS register.
Note: On a Power-on Reset, these pins are
configured as normal I/O, not LCD pins.
27.8 Pixel Control

The LCDDATAx registers contain bits which define the
state of each pixel. Each bit defines one unique pixel.
Register 27-6 shows the correlation of each bit in the
LCDDATAx registers to the respective common and
segment signals.
Any LCD pixel location not being used for display can
be used as general purpose RAM.
27.9 LCD Frame Frequency

The rate at which the COM and SEG outputs change is
called the LCD frame frequency.

PIC16(L)F1933
TABLE 27-7: LCD SEGMENT MAPPING WORKSHEET
LCD COM0 COM1 COM2 COM3

Function
LCDDATAx LCD LCDDATAx LCD LCDDATAx LCD LCDDATAx LCD
Address Segment Address Segment Address Segment Address Segment
SEG0 LCDDATA0, 0 LCDDATA3, 0 LCDDATA6, 0 LCDDATA9, 0

PIC16(L)F1933
27.10 LCD Waveform Generation The LCDs can be driven by two types of waveform:
Type-A and Type-B. In Type-A waveform, the phase
LCD waveforms are generated so that the net AC changes within each common type, whereas in Type-B
voltage across the dark pixel should be maximized and waveform, the phase changes on each frame
the net AC voltage across the clear pixel should be boundary. Thus, Type-A waveform maintains 0 VDC
minimized. The net DC voltage across any pixel should over a single frame, whereas Type-B waveform takes
be zero. two frames.
The COM signal represents the time slice for each
Note 1: If Sleep has to be executed with LCD
common, while the SEG contains the pixel data.
Sleep disabled (LCDCON<SLPEN> is
The pixel signal (COM-SEG) will have no DC ‘1’), then care must be taken to execute
component and it can take only one of the two RMS Sleep only when VDC on all the pixels is
values. The higher RMS value will create a dark pixel ‘0’.
and a lower RMS value will create a clear pixel.
2: When the LCD clock source is FOSC/256,
As the number of commons increases, the delta if Sleep is executed, irrespective of the
between the two RMS values decreases. The delta LCDCON<SLPEN> setting, the LCD
represents the maximum contrast that the display can immediately goes into Sleep. Thus, take
have. care to see that VDC on all pixels is ‘0’
when Sleep is executed.
Figure 27-8 through Figure 27-18 provide waveforms
for static, half-multiplex, 1/3-multiplex and 1/4-multiplex
drives for Type-A and Type-B waveforms.
FIGURE 27-8: TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE
V1
COM0 pin
V0
COM0
V1
SEG0 pin
V0
V1
SEG1 pin
V0
V1
COM0-SEG0 V0
segment voltage
(active) -V1
COM0-SEG1 V0
segment voltage
1 Frame
(inactive)
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0

PIC16(L)F1933
FIGURE 27-9: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE
V2
COM0 pin V1
COM1
V0
V2
COM1 pin V1
COM0
V0
V2
SEG0 pin V1
V0
V2
SEG1 pin V1
V0
SEG3
SEG2
SEG1
V2
SEG0
V1
COM0-SEG0 V0
segment voltage
(active) -V1
-V2
V2
V1
COM0-SEG1 V0
segment voltage
(inactive) -V1
-V2
1 Frame
1 Segment Time
Note: 1 Frame = 2 single segment times.

PIC16(L)F1933
FIGURE 27-10: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE
V2
COM1
COM0 pin V1
V0
COM0
V2
COM1 pin V1
V0
V2
SEG0 pin
V1
V0
V2
SEG1 pin
SEG1
SEG0
SEG2
SEG3
V1
V0
V2
V1
COM0-SEG0 V0
segment voltage
(active) -V1
-V2
V2
V1
COM0-SEG1 V0
segment voltage
(inactive) -V1
-V2
2 Frames
1 Segment Time

PIC16(L)F1933
V3
V2
COM1 COM0 pin
V1
V0
V3
COM0
V2
COM1 pin
V1
V0
V3
V2
SEG0 pin
V1
V0
V3
V2
SEG1 pin
SEG1
SEG0
SEG3
SEG2
V1
V0
V3
V2
V1
COM0-SEG0 V0
segment voltage
(active) -V1
-V2
-V3
V3
V2
V1
COM0-SEG1 V0
segment voltage
(inactive) -V1
-V2
1 Frame
-V3
1 Segment Time

PIC16(L)F1933
V3
V2
COM1 COM0 pin
V1
V0
V3
COM0
V2
COM1 pin
V1
V0
V3
V2
SEG0 pin
V1
V0
V3
V2
SEG1 pin
SEG1
SEG0
SEG3
SEG2
V1
V0
V3
V2
V1
COM0-SEG0 V0
segment voltage
(active) -V1
-V2
-V3
V3
V2
V1
COM0-SEG1 V0
segment voltage
(inactive) -V1
2 Frames -V2
-V3
1 Segment Time

PIC16(L)F1933
V2
COM0 pin
V1
V0
V2
COM2 COM1 pin V1
V0
COM1 V2
COM0 COM2 pin V1
V0
V2
SEG0 and
SEG2 pins V1
V0
V2
SEG1 pin V1
V0
SEG2
SEG1
SEG0
V2
V1
COM0-SEG0 V0
segment voltage
(inactive) -V1
-V2
V2
V1
COM0-SEG1 V0
segment voltage
(active) -V1
-V2
1 Frame
1 Segment Time

PIC16(L)F1933
V2
COM0 pin
V1
V0
COM2
V2
COM1 pin
V1
COM1
V0
COM0
V2
COM2 pin
V1
V0
V2
SEG0 pin
V1
V0
SEG2
SEG1
SEG0
V2
SEG1 pin
V1
V0
V2
V1
COM0-SEG0 V0
segment voltage
(inactive) -V1
-V2
V2
V1
COM0-SEG1 V0
segment voltage
(active) -V1
-V2
2 Frames
1 Segment Time

PIC16(L)F1933
V3
V2
COM0 pin
V1
V0
COM2 V3
V2
COM1 pin
V1
COM1
V0
COM0
V3
V2
COM2 pin
V1
V0
V3
V2
SEG0 and
SEG2 pins V1
V0
SEG2
SEG1
SEG0
V3
V2
SEG1 pin
V1
V0
V3
V2
V1
COM0-SEG0 V0
segment voltage
(inactive) -V1
-V2
-V3
V3
V2
V1
COM0-SEG1 V0
segment voltage
(active) -V1
-V2
-V3
1 Frame
1 Segment Time

PIC16(L)F1933
V3
V2
COM0 pin
V1
V0
COM2 V3
V2
COM1 pin
V1
COM1
V0
COM0
V3
V2
COM2 pin
V1
V0
V3
V2
SEG0 pin
V1
V0
SEG2
SEG1
SEG0
V3
V2
SEG1 pin
V1
V0
V3
V2
V1
COM0-SEG0 V0
segment voltage
(inactive) -V1
-V2
-V3
V3
V2
V1
COM0-SEG1 V0
segment voltage
(active) -V1
-V2
-V3
2 Frames
1 Segment Time

PIC16(L)F1933
COM3 V3
V2
COM0 pin V1
COM2 V0
V3
V2
COM1 pin V1
COM1
V0
COM0
V3
V2
COM2 pin V1
V0
V3
V2
COM3 pin V1
V0
V3
V2
SEG0 pin V1
V0
V3
SEG1
SEG0
V2
SEG1 pin V1
V0
V3
V2
V1
COM0-SEG0 V0
segment voltage -V1
-V2
(active) -V3
V3
V2
V1
COM0-SEG1 V0
segment voltage -V1
-V2
(inactive) -V3
1 Frame
1 Segment Time

PIC16(L)F1933
COM3 V3
V2
COM0 pin V1
COM2 V0
V3
V2
COM1 pin V1
COM1
V0
COM0
V3
V2
COM2 pin V1
V0
V3
V2
COM3 pin V1
V0
V3
V2
SEG0 pin V1
V0
V3
SEG1
SEG0
V2
SEG1 pin V1
V0
V3
V2
V1
COM0-SEG0 V0
segment voltage -V1
-V2
(active) -V3
V3
V2
V1
COM0-SEG1 V0
segment voltage -V1
-V2
(inactive) -V3
2 Frames
1 Segment Time

PIC16(L)F1933
27.11 LCD Interrupts
The LCD module provides an interrupt in two cases. An
interrupt when the LCD controller goes from active to
inactive controller. An interrupt also provides unframe
boundaries for Type B waveform. The LCD timing
generation provides an interrupt that defines the LCD
frame timing.
27.11.1 LCD INTERRUPT ON MODULE

SHUTDOWN
An LCD interrupt is generated when the module
completes shutting down (LCDA goes from ‘1’ to ‘0’).
27.11.2 LCD FRAME INTERRUPTS

A new frame is defined to begin at the leading edge of
the COM0 common signal. The interrupt will be set
immediately after the LCD controller completes access-
ing all pixel data required for a frame. This will occur at
a fixed interval before the frame boundary (TFINT), as
shown in Figure 27-19. The LCD controller will begin to
access data for the next frame within the interval from
the interrupt to when the controller begins to access
data after the interrupt (TFWR). New data must be
written within TFWR, as this is when the LCD controller
will begin to access the data for the next frame.
When the LCD driver is running with Type-B waveforms
and the LMUX<1:0> bits are not equal to ‘00’ (static
drive), there are some additional issues that must be
addressed. Since the DC voltage on the pixel takes two
frames to maintain zero volts, the pixel data must not
change between subsequent frames. If the pixel data
were allowed to change, the waveform for the odd
frames would not necessarily be the complement of the
waveform generated in the even frames and a DC
component would be introduced into the panel.
Therefore, when using Type-B waveforms, the user
must synchronize the LCD pixel updates to occur within
a subframe after the frame interrupt.
To correctly sequence writing while in Type-B, the
interrupt will only occur on complete phase intervals. If
the user attempts to write when the write is disabled,
the WERR bit of the LCDCON register is set and the
write does not occur.
Note: The LCD frame interrupt is not generated
when the Type-A waveform is selected
and when the Type-B with no multiplex
(static) is selected.

PIC16(L)F1933
FIGURE 27-19: WAVEFORMS AND INTERRUPT TIMING IN QUARTER-DUTY CYCLE DRIVE
(EXAMPLE – TYPE-B, NON-STATIC)
LCD Controller Accesses
Interrupt Next Frame Data
Occurs
V3
V2
COM0 V1
V0
V3
V2
COM1 V1
V0
V3
V2
COM2 V1
V0
COM3 V3
V2
V1
V0
2 Frames
TFINT
TFWR Frame
Frame Frame
Boundary Boundary Boundary
TFWR = TFRAME/2*(LMUX<1:0> + 1) + TCY/2

TFINT = (TFWR/2 – (2 TCY + 40 ns))  minimum = 1.5(TFRAME/4) – (2 TCY + 40 ns)
(TFWR/2 – (1 TCY + 40 ns))  maximum = 1.5(TFRAME/4) – (1 TCY + 40 ns)

PIC16(L)F1933
27.12 Operation During Sleep Table 27-8 shows the status of the LCD module during
a Sleep while using each of the three available clock
The LCD module can operate during Sleep. The sources.
selection is controlled by bit SLPEN of the LCDCON
register. Setting the SLPEN bit allows the LCD module Note: When the LCDEN bit is cleared, the LCD
to go to Sleep. Clearing the SLPEN bit allows the module will be disabled at the completion
module to continue to operate during Sleep. of frame. At this time, the port pins will
revert to digital functionality. To minimize
If a SLEEP instruction is executed and SLPEN = 1, the
power consumption due to floating digital
LCD module will cease all functions and go into a very
inputs, the LCD pins should be driven low
low-current consumption mode. The module will stop
using the PORT and TRIS registers.
operation immediately and drive the minimum LCD
voltage on both segment and common lines. If a SLEEP instruction is executed and SLPEN = 0, the
Figure 27-20 shows this operation. module will continue to display the current contents of
The LCD module can be configured to operate during the LCDDATA registers. To allow the module to
Sleep. The selection is controlled by bit SLPEN of the continue operation while in Sleep, the clock source
LCDCON register. Clearing SLPEN and correctly must be either the LFINTOSC or T1OSC external
configuring the LCD module clock will allow the LCD oscillator. While in Sleep, the LCD data cannot be
module to operate during Sleep. Setting SLPEN and changed. The LCD module current consumption will
correctly executing the LCD module shutdown will not decrease in this mode; however, the overall
disable the LCD module during Sleep and save power. consumption of the device will be lower due to shut
down of the core and other peripheral functions.
If a SLEEP instruction is executed and SLPEN = 1, the
LCD module will immediately cease all functions, drive Table 27-8 shows the status of the LCD module during
the outputs to Vss and go into a very low-current mode. Sleep while using each of the three available clock
The SLEEP instruction should only be executed after sources:
the LCD module has been disabled and the current
cycle completed, thus ensuring that there are no DC TABLE 27-8: LCD MODULE STATUS
voltages on the glass. To disable the LCD module, DURING SLEEP
clear the LCDEN bit. The LCD module will complete the Operational
disabling process after the current frame, clear the Clock Source SLPEN
During Sleep
LCDA bit and optionally cause an interrupt.
0 Yes
The steps required to properly enter Sleep with the T1OSC
LCD disabled are: 1 No
• Clear LCDEN 0 Yes

LFINTOSC
• Wait for LCDA = 0 either by polling or by interrupt 1 No
• Execute SLEEP 0 No
FOSC/4
If SLPEN = 0 and SLEEP is executed while the LCD 1 No
module clock source is FOSC/4, then the LCD module
will halt with the pin driving the last LCD voltage
pattern. Prolonged exposure to a fixed LCD voltage Note: The LFINTOSC or external T1OSC
pattern will cause damage to the LCD glass. To prevent oscillator must be used to operate the
LCD glass damage, either perform the proper LCD LCD module during Sleep.
module shutdown prior to Sleep, or change the LCD If LCD interrupts are being generated (Type-B wave-
module clock to allow the LCD module to continue form with a multiplex mode not static) and LCDIE = 1,
operation during Sleep. the device will awaken from Sleep on the next frame
If a SLEEP instruction is executed and SLPEN = 0 and boundary.
the LCD module clock is either T1OSC or LFINTOSC,
the module will continue to display the current contents
of the LCDDATA registers. While in Sleep, the LCD
data cannot be changed. If the LCDIE bit is set, the
device will wake from Sleep on the next LCD frame
boundary. The LCD module current consumption will
not decrease in this mode; however, the overall device
power consumption will be lower due to the shutdown
of the CPU and other peripherals.

PIC16(L)F1933
FIGURE 27-20: SLEEP ENTRY/EXIT WHEN SLPEN = 1
V3
V2
V1
COM0 V0
V3
V2
V1
COM1 V0
V3
V2
V1
COM2 V0
V3
V2
V1
SEG0 V0
2 Frames
SLEEP Instruction Execution Wake-up

PIC16(L)F1933
27.13 Configuring the LCD Module 27.15 LCD Current Consumption
The following is the sequence of steps to configure the When using the LCD module the current consumption
LCD module. consists of the following three factors:
1. Select the frame clock prescale using bits • Oscillator Selection
LP<3:0> of the LCDPS register. • LCD Bias Source
2. Configure the appropriate pins to function as • Capacitance of the LCD segments
segment drivers using the LCDSEn registers.
The current consumption of just the LCD module can
3. Configure the LCD module for the following be considered negligible compared to these other
using the LCDCON register: factors.
- Multiplex and bias mode, bits LMUX<1:0>
- Timing source, bits CS<1:0> 27.15.1 OSCILLATOR SELECTION
- Sleep mode, bit SLPEN The current consumed by the clock source selected
4. Write initial values to pixel data registers, must be considered when using the LCD module. See
LCDDATA0 through LCDDATA11. Section 30.0 “Electrical Specifications” for oscillator
5. Clear LCD Interrupt Flag, LCDIF bit of the PIR2 current consumption information.
register and if desired, enable the interrupt by
setting bit LCDIE of the PIE2 register. 27.15.2 LCD BIAS SOURCE
6. Configure bias voltages by setting the LCDRL, The LCD bias source, internal or external, can
LCDREF and the associated ANSELx contribute significantly to the current consumption. Use
registers as needed. the highest possible resistor values while maintaining
7. Enable the LCD module by setting bit LCDEN of contrast to minimize current.
the LCDCON register.
27.15.3 CAPACITANCE OF THE LCD
SEGMENTS
27.14 Disabling the LCD Module
The LCD segments which can be modeled as
To disable the LCD module, write all ‘0’s to the capacitors which must be both charged and discharged
LCDCON register. every frame. The size of the LCD segment and its
technology determines the segment’s capacitance.

PIC16(L)F1933
TABLE 27-9: SUMMARY OF REGISTERS ASSOCIATED WITH LCD OPERATION

Register
on Page

LCDCST — — — — — LCDCST<2:0> 318
LCDDATA0 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 319
LCDPS WFT BIASMD LCDA WA LP<3:0> 316
LCDREF LCDIRE LCDIRS LCDIRI — VLCD3PE VLCD2PE VLCD1PE — 317
LCDRL LRLAP<1:0> LRLBP<1:0> — LRLAT<2:0> 326
LCDSE0 SE<7:0> 319
LCDSE1 SE<15:8> 319
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the LCD module.

PIC16(L)F1933
28.0 IN-CIRCUIT SERIAL
PROGRAMMING™ (ICSP™)
ICSP™ programming allows customers to manufacture
circuit boards with unprogrammed devices. Programming
can be done after the assembly process, allowing the
device to be programmed with the most recent firmware
or a custom firmware. Five pins are needed for ICSP™
programming:
• ICSPCLK
• ICSPDAT
• MCLR/VPP
• VDD
• VSS
In Program/Verify mode the program memory, user IDs
and the Configuration Words are programmed through
serial communications. The ICSPDAT pin is a
bidirectional I/O used for transferring the serial data and
the ICSPCLK pin is the clock input. For more information
on ICSP™ refer to the “PIC16193X/PIC16LF193X
Memory Programming Specification” (DS41360A).
28.1 High-Voltage Programming Entry

Mode
The device is placed into High-Voltage Programming
Entry mode by holding the ICSPCLK and ICSPDAT
pins low then raising the voltage on MCLR/VPP to VIHH.
Some programmers produce VPP greater than VIHH
(9.0V), an external circuit is required to limit the VPP
voltage. See Figure 28-1 for example circuit.
FIGURE 28-1: VPP LIMITER EXAMPLE CIRCUIT

RJ11-6PIN
1 6
VPP
2 5
VDD
3 4
VSS
4 3
ICSP_DATA
5 2
ICSP_CLOCK
6 1
NC
RJ11-6PIN
® R1
To MPLAB ICD 2 To Target Board
270 Ohm
LM431BCMX
2 A 1
K
3 A U1
6 A NC 4
7 A NC 5
VREF
8
R2 R3
10k 1% 24k 1%
Note: The MPLAB® ICD 2 produces a VPP

voltage greater than the maximum VPP
specification of the PIC16(L)F1933.

PIC16(L)F1933
28.2 Low-Voltage Programming Entry FIGURE 28-2: ICD RJ-11 STYLE
Mode CONNECTOR INTERFACE
The Low-Voltage Programming Entry mode allows the
PIC® Flash MCUs to be programmed using VDD only,
without high voltage. When the LVP bit of Configuration
Words is set to ‘1’, the low-voltage ICSP programming
entry is enabled. To disable the Low-Voltage ICSP ICSPDAT
mode, the LVP bit must be programmed to ‘0’. 2 4 6 NC
VDD
ICSPCLK
Entry into the Low-Voltage Programming Entry mode 1 3 5
Target
requires the following steps:
VPP/MCLR VSS PC Board
1. MCLR is brought to VIL. Bottom Side
2. A 32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
Pin Description*
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be 1 = VPP/MCLR
maintained. 2 = VDD Target
3 = VSS (ground)
If low-voltage programming is enabled (LVP = 1), the
MCLR Reset function is automatically enabled and 4 = ICSPDAT
cannot be disabled. See Section 6.4 “MCLR” for more 5 = ICSPCLK

information. 6 = No Connect
The LVP bit can only be reprogrammed to ‘0’ by using

the High-Voltage Programming mode.
Another connector often found in use with the PICkit™
28.3 Common Programming Interfaces programmers is a standard 6-pin header with 0.1 inch
Connection to a target device is typically done through spacing. Refer to Figure 28-3.
an ICSP™ header. A commonly found connector on
development tools is the RJ-11 in the 6P6C (6 pin, 6
connector) configuration. See Figure 28-2.
FIGURE 28-3: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE
Pin 1 Indicator
Pin Description*
1 1 = VPP/MCLR
2
2 = VDD Target
3
4 3 = VSS (ground)
5
6 4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
* The 6-pin header (0.100" spacing) accepts 0.025" square pins.

PIC16(L)F1933
For additional interface recommendations, refer to your
specific device programmer manual prior to PCB
design.
It is recommended that isolation devices be used to
separate the programming pins from other circuitry.
The type of isolation is highly dependent on the specific
application and may include devices such as resistors,
diodes, or even jumpers. See Figure 28-4 for more
information.
FIGURE 28-4: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING
External
Programming VDD Device to be
Signals Programmed
VDD VDD
VPP MCLR/VPP
VSS VSS
Data ICSPDAT
Clock ICSPCLK
* * *
To Normal Connections
* Isolation devices (as required).

PIC16(L)F1933
NOTES:

PIC16(L)F1933
29.0 INSTRUCTION SET SUMMARY 29.1 Read-Modify-Write Operations
Each instruction is a 14-bit word containing the Any instruction that specifies a file register as part of
operation code (opcode) and all required operands. the instruction performs a Read-Modify-Write (R-M-W)
The opcodes are broken into three broad categories. operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
• Byte Oriented
tion, or the destination designator ‘d’. A read operation
• Bit Oriented is performed on a register even if the instruction writes
• Literal and Control to that register.
The literal and control category contains the most
varied instruction word format. TABLE 29-1: OPCODE FIELD
Table 29-3 lists the instructions recognized by the DESCRIPTIONS
MPASMTM assembler. Field Description
All instructions are executed within a single instruction f Register file address (0x00 to 0x7F)
cycle, with the following exceptions, which may take
W Working register (accumulator)
two or three cycles:
b Bit address within an 8-bit file register
• Subroutine takes two cycles (CALL, CALLW)
• Returns from interrupts or subroutines take two k Literal field, constant data or label
cycles (RETURN, RETLW, RETFIE) x Don’t care location (= 0 or 1).
• Program branching takes two cycles (GOTO, BRA, The assembler will generate code with x = 0.
BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) It is the recommended form of use for
• One additional instruction cycle will be used when compatibility with all Microchip software tools.
any instruction references an indirect file register d Destination select; d = 0: store result in W,
and the file select register is pointing to program d = 1: store result in file register f.
memory. Default is d = 1.
One instruction cycle consists of 4 oscillator cycles; for n FSR or INDF number. (0-1)
an oscillator frequency of 4 MHz, this gives a nominal mm Pre-post increment-decrement mode
instruction execution rate of 1 MHz.
selection
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a TABLE 29-2: ABBREVIATION
hexadecimal digit.
DESCRIPTIONS
Field Description
PC Program Counter
TO Time-out bit
C Carry bit
DC Digit carry bit
Z Zero bit
PD Power-down bit

PIC16(L)F1933
FIGURE 29-1: GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13 8 7 6 0
OPCODE d f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations

13 10 9 7 6 0
OPCODE b (BIT #) f (FILE #)
b = 3-bit bit address

f = 7-bit file register address
Literal and control operations

General
13 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
CALL and GOTO instructions only

13 11 10 0
OPCODE k (literal)
MOVLP instruction only

13 7 6 0
OPCODE k (literal)
MOVLB instruction only

13 5 4 0
OPCODE k (literal)
BRA instruction only

13 9 8 0
OPCODE k (literal)
FSR Offset instructions

13 7 6 5 0
OPCODE n k (literal)
n = appropriate FSR
FSR Increment instructions

13 3 2 1 0
OPCODE n m (mode)
n = appropriate FSR
m = 2-bit mode value
OPCODE only
13 0
OPCODE

PIC16(L)F1933
TABLE 29-3: PIC16(L)F1933 INSTRUCTION SET

Mnemonic, 14-Bit Opcode Status
Description Cycles Notes
Operands MSb LSb Affected
BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 2
ADDWFC f, d Add with Carry W and f 1 11 1101 dfff ffff C, DC, Z 2
ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 2
ASRF f, d Arithmetic Right Shift 1 11 0111 dfff ffff C, Z 2
LSLF f, d Logical Left Shift 1 11 0101 dfff ffff C, Z 2
LSRF f, d Logical Right Shift 1 11 0110 dfff ffff C, Z 2
CLRF f Clear f 1 00 0001 lfff ffff Z 2
CLRW – Clear W 1 00 0001 0000 00xx Z
COMF f, d Complement f 1 00 1001 dfff ffff Z 2
DECF f, d Decrement f 1 00 0011 dfff ffff Z 2
INCF f, d Increment f 1 00 1010 dfff ffff Z 2
IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 2
MOVF f, d Move f 1 00 1000 dfff ffff Z 2
MOVWF f Move W to f 1 00 0000 1fff ffff 2
RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 2
RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 2
SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 2
SUBWFB f, d Subtract with Borrow W from f 1 11 1011 dfff ffff C, DC, Z 2
SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 2
XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 2
BYTE ORIENTED SKIP OPERATIONS
DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2

INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF f, b Bit Clear f 1 01 00bb bfff ffff 2

BSF f, b Bit Set f 1 01 01bb bfff ffff 2
BIT-ORIENTED SKIP OPERATIONS

BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 1, 2
BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 1, 2
LITERAL OPERATIONS
ADDLW k Add literal and W 1 11 1110 kkkk kkkk C, DC, Z
ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z
IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z
MOVLB k Move literal to BSR 1 00 0000 001k kkkk
MOVLP k Move literal to PCLATH 1 11 0001 1kkk kkkk
MOVLW k Move literal to W 1 11 0000 kkkk kkkk
SUBLW k Subtract W from literal 1 11 1100 kkkk kkkk C, DC, Z
XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z
Note 1:If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one
additional instruction cycle.

PIC16(L)F1933
TABLE 29-3: PIC16(L)F1933 INSTRUCTION SET (CONTINUED)
Mnemonic, 14-Bit Opcode Status
Description Cycles Notes
Operands MSb LSb Affected
CONTROL OPERATIONS
BRA k Relative Branch 2 11 001k kkkk kkkk
BRW – Relative Branch with W 2 00 0000 0000 1011
CALL k Call Subroutine 2 10 0kkk kkkk kkkk
CALLW – Call Subroutine with W 2 00 0000 0000 1010
GOTO k Go to address 2 10 1kkk kkkk kkkk
RETFIE k Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 0100 kkkk kkkk
RETURN – Return from Subroutine 2 00 0000 0000 1000
INHERENT OPERATIONS
CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD
NOP – No Operation 1 00 0000 0000 0000
OPTION – Load OPTION_REG register with W 1 00 0000 0110 0010
RESET – Software device Reset 1 00 0000 0000 0001
SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD
TRIS f Load TRIS register with W 1 00 0000 0110 0fff
C-COMPILER OPTIMIZED
ADDFSR n, k Add Literal k to FSRn 1 11 0001 0nkk kkkk
MOVIW n mm Move Indirect FSRn to W with pre/post inc/dec 1 00 0000 0001 0nmm Z 2, 3
modifier, mm
k[n] Move INDFn to W, Indexed Indirect. 1 11 1111 0nkk kkkk Z 2
MOVWI n mm Move W to Indirect FSRn with pre/post inc/dec 1 00 0000 0001 1nmm 2, 3
modifier, mm
k[n] Move W to INDFn, Indexed Indirect. 1 11 1111 1nkk kkkk 2
Note 1:If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Table in the MOVIW and MOVWI instruction descriptions.

PIC16(L)F1933
29.2 Instruction Descriptions
ADDFSR Add Literal to FSRn ANDLW AND literal with W

Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW k
Operands: -32  k  31 Operands: 0  k  255
n  [ 0, 1]
Operation: (W) .AND. (k)  (W)
Operation: FSR(n) + k  FSR(n)
Status Affected: Z
Status Affected: None Description: The contents of W register are
Description: The signed 6-bit literal ‘k’ is added to AND’ed with the eight-bit literal ‘k’.
the contents of the FSRnH:FSRnL The result is placed in the W register.
register pair.
FSRn is limited to the range 0000h -

FFFFh. Moving beyond these bounds
will cause the FSR to wrap-around.
ADDLW Add literal and W ANDWF AND W with f

Syntax: [ label ] ADDLW k Syntax: [ label ] ANDWF f,d
Operands: 0  k  255 Operands: 0  f  127
d 0,1
Operation: (W) + k  (W)
Operation: (W) .AND. (f)  (destination)
Status Affected: C, DC, Z
Status Affected: Z
Description: The contents of the W register are
added to the eight-bit literal ‘k’ and the Description: AND the W register with register ‘f’. If
result is placed in the W register. ‘d’ is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
ADDWF Add W and f ASRF Arithmetic Right Shift

Syntax: [ label ] ADDWF f,d Syntax: [ label ] ASRF f {,d}
Operands: 0  f  127 Operands: 0  f  127
d 0,1 d [0,1]
Operation: (W) + (f)  (destination) Operation: (f<7>) dest<7>
(f<7:1>)  dest<6:0>,
(f<0>)  C,
Description: Add the contents of the W register
Status Affected: C, Z
with register ‘f’. If ‘d’ is ‘0’, the result is
stored in the W register. If ‘d’ is ‘1’, the Description: The contents of register ‘f’ are shifted
result is stored back in register ‘f’. one bit to the right through the Carry
flag. The MSb remains unchanged. If
‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in reg-
ister ‘f’.
ADDWFC ADD W and CARRY bit to f register f C
Syntax: [ label ] ADDWFC f {,d}
Operands: 0  f  127
d [0,1]
Operation: (W) + (f) + (C)  dest
Description: Add W, the Carry flag and data mem-
ory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.

PIC16(L)F1933
BCF Bit Clear f BTFSC Bit Test f, Skip if Clear
Syntax: [ label ] BCF f,b Syntax: [ label ] BTFSC f,b

0b7 0b7
Operation: 0  (f<b>) Operation: skip if (f<b>) = 0
Status Affected: None Status Affected: None
Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOP is
executed instead, making this a
2-cycle instruction.
BRA Relative Branch BTFSS Bit Test f, Skip if Set

Syntax: [ label ] BRA label Syntax: [ label ] BTFSS f,b
[ label ] BRA $+k Operands: 0  f  127
Operands: -256  label - PC + 1  255 0b<7
-256  k  255 Operation: skip if (f<b>) = 1
Operation: (PC) + 1 + k  PC Status Affected: None
Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next
Description: Add the signed 9-bit literal ‘k’ to the instruction is executed.
PC. Since the PC will have incre- If bit ‘b’ is ‘1’, then the next
mented to fetch the next instruction, instruction is discarded and a NOP is
the new address will be PC + 1 + k. executed instead, making this a
This instruction is a two-cycle instruc- 2-cycle instruction.
tion. This branch has a limited range.
BRW Relative Branch with W

Syntax: [ label ] BRW
Operands: None
Operation: (PC) + (W)  PC
Status Affected: None
Description: Add the contents of W (unsigned) to
the PC. Since the PC will have incre-
mented to fetch the next instruction,
the new address will be PC + 1 + (W).
This instruction is a two-cycle instruc-
tion.
BSF Bit Set f

Syntax: [ label ] BSF f,b
0b7
Operation: 1  (f<b>)
Description: Bit ‘b’ in register ‘f’ is set.

PIC16(L)F1933
CALL Call Subroutine CLRWDT Clear Watchdog Timer

Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT
Operands: 0  k  2047 Operands: None
Operation: (PC)+ 1 TOS, Operation: 00h  WDT
k  PC<10:0>, 0  WDT prescaler,
(PCLATH<6:3>)  PC<14:11> 1  TO
Status Affected: None 1  PD
Description: Call Subroutine. First, return address Status Affected: TO, PD
(PC + 1) is pushed onto the stack. Description: CLRWDT instruction resets the Watch-
The eleven-bit immediate address is dog Timer. It also resets the prescaler
loaded into PC bits <10:0>. The upper of the WDT.
bits of the PC are loaded from Status bits TO and PD are set.
PCLATH. CALL is a two-cycle instruc-
tion.
CALLW Subroutine Call With W COMF Complement f
Syntax: [ label ] CALLW Syntax: [ label ] COMF f,d
Operands: None Operands: 0  f  127

d  [0,1]
Operation: (PC) +1  TOS,
(W)  PC<7:0>, Operation: (f)  (destination)
(PCLATH<6:0>) PC<14:8> Status Affected: Z
Description: The contents of register ‘f’ are com-
Status Affected: None plemented. If ‘d’ is ‘0’, the result is
Description: Subroutine call with W. First, the stored in W. If ‘d’ is ‘1’, the result is
return address (PC + 1) is pushed stored back in register ‘f’.
onto the return stack. Then, the con-
tents of W is loaded into PC<7:0>,
and the contents of PCLATH into
PC<14:8>. CALLW is a two-cycle
instruction.
CLRF Clear f DECF Decrement f

Syntax: [ label ] CLRF f Syntax: [ label ] DECF f,d
d  [0,1]
Operation: 00h  (f)
1Z Operation: (f) - 1  (destination)
Status Affected: Z Status Affected: Z
Description: The contents of register ‘f’ are cleared Description: Decrement register ‘f’. If ‘d’ is ‘0’, the
and the Z bit is set. result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h  (W)
1Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z) is
set.

PIC16(L)F1933
DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0

Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d
d  [0,1] d  [0,1]
Operation: (f) - 1  (destination); Operation: (f) + 1  (destination),
skip if result = 0 skip if result = 0
Status Affected: None Status Affected: None
Description: The contents of register ‘f’ are decre- Description: The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘0’, the result is placed mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’. is placed back in register ‘f’.
If the result is ‘1’, the next instruction is If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, then a executed. If the result is ‘0’, a NOP is
NOP is executed instead, making it a executed instead, making it a 2-cycle
2-cycle instruction. instruction.
GOTO Unconditional Branch IORLW Inclusive OR literal with W

Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k
Operands: 0  k  2047 Operands: 0  k  255
Operation: k  PC<10:0> Operation: (W) .OR. k  (W)
PCLATH<6:3>  PC<14:11>
Status Affected: Z
Status Affected: None Description: The contents of the W register are
Description: GOTO is an unconditional branch. The OR’ed with the eight-bit literal ‘k’. The
eleven-bit immediate value is loaded result is placed in the W register.
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTO is a two-cycle instruction.
INCF Increment f IORWF Inclusive OR W with f

Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d
d  [0,1] d  [0,1]
Operation: (f) + 1  (destination) Operation: (W) .OR. (f)  (destination)
Status Affected: Z Status Affected: Z
Description: The contents of register ‘f’ are incre- Description: Inclusive OR the W register with regis-
mented. If ‘d’ is ‘0’, the result is placed ter ‘f’. If ‘d’ is ‘0’, the result is placed in
in the W register. If ‘d’ is ‘1’, the result the W register. If ‘d’ is ‘1’, the result is
is placed back in register ‘f’. placed back in register ‘f’.

PIC16(L)F1933
LSLF Logical Left Shift MOVF Move f

Syntax: [ label ] LSLF f {,d} Syntax: [ label ] MOVF f,d
d [0,1] d  [0,1]
Operation: (f<7>)  C Operation: (f)  (dest)
(f<6:0>)  dest<7:1>
Status Affected: Z
0  dest<0>
Description: The contents of register f is moved to
a destination dependent upon the
Description: The contents of register ‘f’ are shifted status of d. If d = 0,
one bit to the left through the Carry flag. destination is W register. If d = 1, the
A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, destination is file register f itself. d = 1
the result is placed in W. If ‘d’ is ‘1’, the is useful to test a file register since
result is stored back in register ‘f’. status flag Z is affected.
C register f 0 Words: 1
Cycles: 1
Example: MOVF FSR, 0
After Instruction
LSRF Logical Right Shift
W = value in FSR register
Syntax: [ label ] LSRF f {,d} Z = 1
d [0,1]
Operation: 0  dest<7>
(f<7:1>)  dest<6:0>,
(f<0>)  C,
Description: The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. A ‘0’ is shifted into the MSb. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
0 register f C

PIC16(L)F1933
MOVIW Move INDFn to W MOVLP Move literal to PCLATH

Syntax: [ label ] MOVIW ++FSRn Syntax: [ label ] MOVLP k
[ label ] MOVIW --FSRn
Operands: 0  k  127
[ label ] MOVIW FSRn++
[ label ] MOVIW FSRn-- Operation: k  PCLATH
[ label ] MOVIW k[FSRn] Status Affected: None
Operands: n  [0,1] Description: The seven-bit literal ‘k’ is loaded into the
mm  [00,01, 10, 11] PCLATH register.
-32  k  31
Operation: INDFn  W
Effective address is determined by MOVLW Move literal to W
• FSR + 1 (preincrement)
Syntax: [ label ] MOVLW k
• FSR - 1 (predecrement)
• FSR + k (relative offset) Operands: 0  k  255
After the Move, the FSR value will be
Operation: k  (W)
either:
• FSR + 1 (all increments) Status Affected: None
• FSR - 1 (all decrements) Description: The eight-bit literal ‘k’ is loaded into W
• Unchanged register. The “don’t cares” will assem-
Status Affected: Z ble as ‘0’s.
Words: 1
Mode Syntax mm Cycles: 1
Preincrement ++FSRn 00 Example: MOVLW 0x5A
Predecrement --FSRn 01 After Instruction

W = 0x5A
Postincrement FSRn++ 10
Postdecrement FSRn-- 11
MOVWF Move W to f
Syntax: [ label ] MOVWF f
Description: This instruction is used to move data
between W and one of the indirect Operands: 0  f  127
registers (INDFn). Before/after this Operation: (W)  (f)
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Description: Move data from W register to register
Note: The INDFn registers are not ‘f’.
physical registers. Any instruction that Words: 1
accesses an INDFn register actually
accesses the register at the address Cycles: 1
specified by the FSRn. Example: MOVWF OPTION_REG
Before Instruction
OPTION_REG = 0xFF
FFFFh. Incrementing/decrementing it
W = 0x4F
beyond these bounds will cause it to
After Instruction
wrap-around.
OPTION_REG = 0x4F
W = 0x4F
MOVLB Move literal to BSR
Syntax: [ label ] MOVLB k
Operands: 0  k  15
Operation: k  BSR
Description: The five-bit literal ‘k’ is loaded into the
Bank Select Register (BSR).

PIC16(L)F1933
MOVWI Move W to INDFn NOP No Operation
Syntax: [ label ] MOVWI ++FSRn Syntax: [ label ] NOP

[ label ] MOVWI --FSRn Operands: None
[ label ] MOVWI FSRn++
Operation: No operation
[ label ] MOVWI FSRn--
[ label ] MOVWI k[FSRn] Status Affected: None
Operands: n  [0,1] Description: No operation.

mm  [00,01, 10, 11] Words: 1
-32  k  31
Cycles: 1
Operation: W  INDFn
Example: NOP
Effective address is determined by
• FSR + 1 (preincrement)
• FSR - 1 (predecrement)
• FSR + k (relative offset)
After the Move, the FSR value will be
either:
Load OPTION_REG Register
OPTION
• FSR + 1 (all increments) with W
• FSR - 1 (all decrements) Syntax: [ label ] OPTION
Unchanged
Operands: None
Operation: (W)  OPTION_REG
Mode Syntax mm
Description: Move data from W register to
Preincrement ++FSRn 00 OPTION_REG register.
Predecrement --FSRn 01
Postincrement FSRn++ 10 Words: 1
Postdecrement FSRn-- 11 Cycles: 1
Example: OPTION
Description: This instruction is used to move data Before Instruction
between W and one of the indirect OPTION_REG = 0xFF
registers (INDFn). Before/after this W = 0x4F
move, the pointer (FSRn) is updated by After Instruction
pre/post incrementing/decrementing it. OPTION_REG = 0x4F
W = 0x4F
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
RESET Software Reset
accesses the register at the address
specified by the FSRn. Syntax: [ label ] RESET
Operands: None
FFFFh. Incrementing/decrementing it Operation: Execute a device Reset. Resets the
beyond these bounds will cause it to RI flag of the PCON register.
wrap-around. Status Affected: None
The increment/decrement operation on Description: This instruction provides a way to

FSRn WILL NOT affect any Status bits. execute a hardware Reset by soft-
ware.

PIC16(L)F1933
RETFIE Return from Interrupt RETURN Return from Subroutine

Syntax: [ label ] RETFIE Syntax: [ label ] RETURN
Operands: None Operands: None
Operation: TOS  PC, Operation: TOS  PC
1  GIE Status Affected: None
Status Affected: None Description: Return from subroutine. The stack is
Description: Return from Interrupt. Stack is POPed POPed and the top of the stack (TOS)
and Top-of-Stack (TOS) is loaded in is loaded into the program counter.
the PC. Interrupts are enabled by This is a two-cycle instruction.
setting Global
Interrupt Enable bit, GIE
(INTCON<7>). This is a two-cycle
instruction.
Words: 1
Cycles: 2
Example: RETFIE
After Interrupt
PC = TOS
GIE = 1
RETLW Return with literal in W RLF Rotate Left f through Carry

Syntax: [ label ] RETLW k Syntax: [ label ] RLF f,d
Operands: 0  k  255 Operands: 0  f  127

d  [0,1]
Operation: k  (W);
TOS  PC Operation: See description below
Status Affected: None Status Affected: C
Description: The W register is loaded with the eight Description: The contents of register ‘f’ are rotated
bit literal ‘k’. The program counter is one bit to the left through the Carry
loaded from the top of the stack (the flag. If ‘d’ is ‘0’, the result is placed in
return address). This is a two-cycle the W register. If ‘d’ is ‘1’, the result is
instruction. stored back in register ‘f’.
Words: 1 C Register f
Cycles: 2
Words: 1
Example: CALL TABLE;W contains table
;offset value Cycles: 1
• ;W now has table value Example: RLF REG1,0
TABLE •
Before Instruction
•
REG1 = 1110 0110
ADDWF PC ;W = offset
C = 0
RETLW k1 ;Begin table
After Instruction
RETLW k2 ;
REG1 = 1110 0110
•
W = 1100 1100
•
C = 1
•
RETLW kn ; End of table
Before Instruction
W = 0x07
After Instruction
W = value of k8

PIC16(L)F1933
SUBLW Subtract W from literal

RRF Rotate Right f through Carry
Syntax: [ label ] SUBLW k
Syntax: [ label ] RRF f,d
Operands: 0 k 255
d  [0,1] Operation: k - (W) W)
Operation: See description below Status Affected: C, DC, Z
Status Affected: C Description: The W register is subtracted (2’s com-

plement method) from the eight-bit
Description: The contents of register ‘f’ are rotated literal ‘k’. The result is placed in the W
one bit to the right through the Carry register.
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is C=0 Wk
placed back in register ‘f’.
C=1 Wk
C Register f
DC = 0 W<3:0>  k<3:0>
DC = 1 W<3:0>  k<3:0>
SLEEP Enter Sleep mode SUBWF Subtract W from f

Syntax: [ label ] SLEEP Syntax: [ label ] SUBWF f,d
Operands: None Operands: 0 f 127
d  [0,1]
Operation: 00h  WDT,
0  WDT prescaler, Operation: (f) - (W) destination)
1  TO, Status Affected: C, DC, Z
0  PD
Description: Subtract (2’s complement method) W
Status Affected: TO, PD register from register ‘f’. If ‘d’ is ‘0’, the
Description: The power-down Status bit, PD is result is stored in the W
cleared. Time-out Status bit, TO is register. If ‘d’ is ‘1’, the result is stored
set. Watchdog Timer and its pres- back in register ‘f.
caler are cleared.
The processor is put into Sleep mode C=0 Wf
with the oscillator stopped. C=1 Wf
DC = 0 W<3:0>  f<3:0>
DC = 1 W<3:0>  f<3:0>
SUBWFB Subtract W from f with Borrow

Syntax: SUBWFB f {,d}
d  [0,1]
Operation: (f) – (W) – (B) dest
Description: Subtract W and the BORROW flag
(CARRY) from register ‘f’ (2’s comple-
ment method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.

PIC16(L)F1933
SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W

Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORLW k
Operands: 0  f  127 Operands: 0 k 255
d  [0,1]
Operation: (W) .XOR. k W)
Operation: (f<3:0>)  (destination<7:4>),
Status Affected: Z
(f<7:4>)  (destination<3:0>)
Description: The contents of the W register are
XOR’ed with the eight-bit
Description: The upper and lower nibbles of regis- literal ‘k’. The result is placed in the
ter ‘f’ are exchanged. If ‘d’ is ‘0’, the W register.
result is placed in the W register. If ‘d’
is ‘1’, the result is placed in register ‘f’.
TRIS Load TRIS Register with W XORWF Exclusive OR W with f

Syntax: [ label ] TRIS f Syntax: [ label ] XORWF f,d
Operands: 5f7 Operands: 0  f  127
d  [0,1]
Operation: (W)  TRIS register ‘f’
Operation: (W) .XOR. (f) destination)
Status Affected: Z
Description: Move data from W register to TRIS
register. Description: Exclusive OR the contents of the W
When ‘f’ = 5, TRISA is loaded. register with register ‘f’. If ‘d’ is ‘0’, the
When ‘f’ = 6, TRISB is loaded. result is stored in the W register. If ‘d’
When ‘f’ = 7, TRISC is loaded. is ‘1’, the result is stored back in regis-
ter ‘f’.

PIC16(L)F1933
30.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings(†)

Ambient temperature under bias....................................................................................................... -40°C to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on VDD with respect to VSS, PIC16F1933 ............................................................................. -0.3V to +6.5V
Voltage on VCAP pin with respect to VSS, PIC16F1933 ....................................................................... -0.3V to +4.0V
Voltage on VDD with respect to VSS, PIC16LF1933 ........................................................................... -0.3V to +4.0V
Voltage on MCLR with respect to Vss ................................................................................................. -0.3V to +9.0V
Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation(1) ............................................................................................................................... 800 mW
Maximum current out of VSS pin, -40°C  TA  +85°C for industrial............................................................... 255 mA
Maximum current out of VSS pin, -40°C  TA  +125°C for extended ............................................................ 105 mA
Maximum current into VDD pin, -40°C  TA  +85°C for industrial.................................................................. 170 mA
Maximum current into VDD pin, -40°C  TA  +125°C for extended ................................................................. 70 mA
Clamp current, IK (VPIN < 0 or VPIN > VDD) 20 mA
Maximum output current sunk by any I/O pin.................................................................................................... 25 mA
Maximum output current sourced by any I/O pin .............................................................................................. 25 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOl x IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure above maximum rating condi-
tions for extended periods may affect device reliability.

PIC16(L)F1933
FIGURE 30-1: PIC16F1933 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C
Vdd (V) 5.5
2.5
1.8
0 4 10 16 32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 30-1 for each Oscillator mode’s supported frequencies.
FIGURE 30-2: PIC16LF1933 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C

Vdd (V)
3.6
2.5
1.8
0 4 10 16 32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 30-1 for each Oscillator mode’s supported frequencies.

PIC16(L)F1933
FIGURE 30-3: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
125
± 5%
85
± 3%
Temperature (°C)
60
± 2%
25
0
-20
± 5%
-40
1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC16(L)F1933
30.1 DC Characteristics: Supply Voltage

Standard Operating Conditions (unless otherwise stated)
PIC16LF1933 Operating temperature -40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
PIC16F1933 Operating temperature -40°C  TA  +85°C for industrial
Param. Sym. Characteristic Min. Typ† Max. Units Conditions
No.
D001 VDD Supply Voltage (VDDMIN, VDDMAX)
PIC16LF1933 1.8 — 3.6 V FOSC  16 MHz:
2.5 — 3.6 V FOSC  32 MHz (Note 2)
D001 PIC16F1933 1.8 — 5.5 V FOSC  16 MHz:
2.5 — 5.5 V FOSC  32 MHz (Note 2)
D002* VDR RAM Data Retention Voltage(1)
PIC16LF1933 1.5 — — V Device in Sleep mode
D002* PIC16F1933 1.7 — — V Device in Sleep mode
D002A* VPOR* Power-on Reset Release Voltage — 1.6 — V
D002B* VPORR* Power-on Reset Rearm Voltage
PIC16LF1933 — 0.8 — V
D002B* PIC16F1933 — 1.42 — V
D003 VADFVR Fixed Voltage Reference Voltage -8 — 6 % 1.024V, VDD  2.5V
for ADC 2.048V, VDD  2.5V
4.096V, VDD  4.75V
D003A VCDAFVR Fixed Voltage Reference Voltage -11 — 7 % 1.024V, VDD  2.5V
for Comparator and DAC 2.048V, VDD  2.5V
4.096V, VDD  4.75V
D003B VLCDFVR Fixed Voltage Reference Voltage -11 — 10 % 3.072V, VDD  3.6V
for LCD Bias
D004* SVDD VDD Rise Rate to ensure internal 0.05 — — V/ms See Section 6.1 “Power-On Reset
Power-on Reset signal (POR)” for details.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: PLL required for 32 MHz operation.

PIC16(L)F1933
FIGURE 30-4: POR AND POR REARM WITH SLOW RISING VDD
VDD
VPOR
VPORR
VSS
NPOR
POR REARM
VSS
TVLOW(2) TPOR(3)
Note 1: When NPOR is low, the device is held in Reset.

2: TPOR 1 s typical.
3: TVLOW 2.7 s typical.

PIC16(L)F1933
30.2 DC Characteristics: Supply Currents (IDD)

Param Device Conditions

Min. Typ† Max. Units
No. Characteristics VDD Note
(1, 2)
Supply Current (IDD)
D009 LDO Regulator — 350 — A — HS, EC OR INTOSC/INTOSCIO (8-16 MHZ)
Clock modes with all VCAP pins disabled
— 50 — A — All VCAP pins disabled
— 30 — A — VCAP enabled
— 5 — A — LP Clock mode and Sleep
(requires FVR and BOR to be disabled)
D010 — 8 14 A 1.8 FOSC = 32 kHz
— 12 18 A 3.0 LP Oscillator mode (Note 4),
-40°C  TA  +85°C
D010 — 23 63 A 1.8 FOSC = 32 kHz
— 28 74 A 3.0 LP Oscillator mode (Note 4, Note 5),
-40°C  TA  +85°C
— 33 79 A 5.0
D010A — 10 18 A 1.8 FOSC = 32 kHz
— 15 20 A 3.0 LP Oscillator mode (Note 4)
-40°C  TA  +125°C
D010A — 24 79 A 1.8 FOSC = 32 kHz
— 30 93 A 3.0 LP Oscillator mode (Note 4, Note 5)
-40°C  TA  +125°C
— 35 99 A 5.0
D011 — 120 160 A 1.8 FOSC = 1 MHz
— 200 255 A 3.0 XT Oscillator mode
D011 — 160 195 A 1.8 FOSC = 1 MHz

— 230 275 A 3.0 XT Oscillator mode (Note 5)
— 280 410 A 5.0

D012 — 325 370 A 1.8 FOSC = 4 MHz
— 600 710 A 3.0 XT Oscillator mode
D012 — 350 410 A 1.8 FOSC = 4 MHz

— 625 765 A 3.0 XT Oscillator mode (Note 5)
— 700 850 A 5.0

Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k
4: FVR and BOR are disabled.
5: 0.1 F capacitor on VCAP.
6: 8 MHz crystal oscillator with 4x PLL enabled.

PIC16(L)F1933
30.2 DC Characteristics: Supply Currents (IDD) (Continued)

Supply Current (IDD)(1, 2)

D013 — 60 90 A 1.8 FOSC = 500 kHz
— 85 135 A 3.0 EC Oscillator Low-Power mode
D013 — 60 137 A 1.8 FOSC = 500 kHz

— 85 194 A 3.0 EC Oscillator Low-Power mode (Note 5)
— 95 230 A 5.0
D014 — 300 340 A 1.8 FOSC = 4 MHz
— 400 650 A 3.0 EC Oscillator mode
Medium-Power mode
D014 — 350 375 A 1.8 FOSC = 4 MHz
— 550 700 A 3.0 EC Oscillator mode (Note 5)
Medium-Power mode
— 600 900 A 5.0
D015 — 3.7 4.2 mA 3.0 FOSC = 32 MHz
— 4.2 5.2 mA 3.6 EC Oscillator High-Power mode
D015 — 3.7 4.2 mA 3.0 FOSC = 32 MHz

— 3.9 4.7 mA 5.0 EC Oscillator High-Power mode (Note 5)
D016 — 4 10 A 1.8 FOSC = 32 kHz

— 7 13 A 3.0 LFINTOSC mode, 85°C
D016 — 27 61 A 1.8 FOSC = 32 kHz

— 33 74 A 3.0 LFINTOSC mode, 85°C (Note 5)
— 34 76 A 5.0
consumption.

PIC16(L)F1933
30.2 DC Characteristics: Supply Currents (IDD) (Continued)

Supply Current (IDD)(1, 2)

D017
— 130 175 A 1.8 FOSC = 500 kHz
— 165 210 A 3.0 MFINTOSC mode
D017 — 150 200 A 1.8 FOSC = 500 kHz

— 210 240 A 3.0 MFINTOSC mode (Note 5)
— 270 330 A 5.0

D018 — 0.8 1.1 mA 1.8 FOSC = 8 MHz
— 1.3 1.7 mA 3.0 HFINTOSC mode
D018 — 0.9 1.1 mA 1.8 FOSC = 8 MHz

— 1.4 1.7 mA 3.0 HFINTOSC mode (Note 5)
— 1.6 1.8 mA 5.0

D019 — 1.3 1.7 mA 1.8 FOSC = 16 MHz
D019 — 1.4 1.6 mA 1.8 FOSC = 16 MHz

— 2.2 2.6 mA 3.0 HFINTOSC mode (Note 5)
— 2.4 3.0 mA 5.0

D020 — 3.9 4.5 mA 3.0 FOSC = 32 MHz
D020 — 3.9 4.5 mA 3.0 FOSC = 32 MHz

D021 — 300 350 A 1.8 FOSC = 4 MHz

— 500 675 A 3.0 EXTRC mode (Note 3)
D021 — 350 390 A 1.8 FOSC = 4 MHz

— 550 720 A 3.0 EXTRC mode (Note 3, Note 5)
— 620 790 A 5.0

D022 — 2.7 4.4 mA 3.0 FOSC = 32 MHz
— 2.9 5.7 mA 3.6 HS Oscillator mode (Note 6)
D022 — 3.6 4.4 mA 3.0 FOSC = 32 MHz

— 3.9 4.7 mA 5.0 HS Oscillator mode (Note 5, Note 6)
consumption.

PIC16(L)F1933
30.3 DC Characteristics: Power-Down Currents (IPD)

Param Max. Max. Conditions

Device Characteristics Min. Typ† Units
No. +85°C +125°C VDD Note
Power-down Base Current (IPD)(2)
D023 — 0.06 1 7 A 1.8 WDT, BOR, FVR, and T1OSC
— 0.08 2 8 A 3.0 disabled, all Peripherals Inactive
D023 — 20 55 69 A 1.8 WDT, BOR, FVR, and T1OSC

— 24 58 72 A 3.0 disabled, all Peripherals Inactive
— 26 60 75 A 5.0
D024 — 0.5 6 8 A 1.8 LPWDT Current (Note 1)
— 0.8 7 9 A 3.0
D024 — 20 56 70 A 1.8 LPWDT Current (Note 1)
— 25 59 73 A 3.0
— 26 61 76 A 5.0
D025 — 9 20 20 A 1.8 FVR current
— 9 23 23 A 3.0
D025 — 36 96 120 A 1.8 FVR current (Note 4)
— 43 110 140 A 3.0
— 75 140 170 A 5.0
D026 — 8 17 17 A 3.0 BOR Current (Note 1)
D026 — 28 96 120 A 3.0 BOR Current (Note 1, Note 4)
— 30 130 170 A 5.0
D027 — 0.6 5 5 A 1.8 T1OSC Current (Note 1)
— 3.9 9 9.5 A 3.0
D027 — 22 57 71 A 1.8 T1OSC Current (Note 1)
— 28 62 78 A 3.0
— 33 66 83 A 5.0
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: A/D oscillator source is FRC.

PIC16(L)F1933
30.3 DC Characteristics: Power-Down Currents (IPD) (Continued)
Param Max. Max. Conditions

Device Characteristics Min. Typ† Units
No. +85°C +125°C VDD Note
(2)
Power-down Base Current (IPD)
D028 — 0.1 1 7 A 1.8 A/D Current (Note 1, Note 3),
— 0.1 2 8 A 3.0 no conversion in progress
D028 — 16 56 70 A 1.8 A/D Current (Note 1, Note 3),

— 21 58 78 A 3.0 no conversion in progress
— 25 61 88 A 5.0
D028A — 250 — — A 1.8 A/D Current (Note 1, Note 3),
— 250 — — A 3.0 conversion in progress
D028A — 280 — — A 1.8 A/D Current (Note 1, Note 3,

— 280 — — A 3.0 Note 4), conversion in progress
— 280 — — A 5.0
D029 — 1.9 6 6 A 1.8 Cap Sense, Low-Power mode
— 3.6 9 9 A 3.0 CPSRM = 0, cpsrng = 01
(Note 1)
D029 — 20 61 76 A 1.8 Cap Sense, Low-Power mode
— 24 64 79 A 3.0 CPSRM = 0, cpsrng = 01
(Note 1)
— 26 66 83 A 5.0
D030 — 1 — — A 3.0 LCD Bias Ladder, Low-power
— 10 — — A 3.0 LCD Bias Ladder, Medium-power
— 75 — — A 3.0 LCD Bias Ladder, High-power
D030 — 1 — — A 5.0 LCD Bias Ladder, Low-power
— 10 — — A 5.0 LCD Bias Ladder, Medium-power
— 75 — — A 5.0 LCD Bias Ladder, High-power
D031 — 16 18 18 A 1.8 Comparator, Low-Power mode
— 18 20 20 A 3.0
D031 — 27 65 81 A 1.8 Comparator, Low-Power mode
— 30 75 94 A 3.0
— 32 76 95 A 5.0
not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: A/D oscillator source is FRC.

PIC16(L)F1933
30.4 DC Characteristics: I/O Ports

DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial
Param
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
VIL Input Low Voltage
I/O PORT:
D032 with TTL buffer — — 0.8 V 4.5V  VDD  5.5V
D032A — — 0.15 VDD V 1.8V  VDD  4.5V
D033 with Schmitt Trigger buffer — — 0.2 VDD V 2.0V  VDD  5.5V
with I2C™ levels — — 0.3 VDD V
with SMBus levels — — 0.8 V 2.7V  VDD  5.5V
D034 MCLR, OSC1 (RC mode) — — 0.2 VDD V (Note 1)
D034A OSC1 (HS mode) — — 0.3 VDD V
VIH Input High Voltage
I/O PORT:
D040 with TTL buffer 2.0 — — V 4.5V  VDD 5.5V
D040A 0.25 VDD + — — V 1.8V  VDD  4.5V
0.8
D041 with Schmitt Trigger buffer 0.8 VDD — — V 2.0V  VDD  5.5V
with I2C™ levels 0.7 VDD — — V
with SMBus levels 2.1 — — V 2.7V  VDD  5.5V
D042 MCLR 0.8 VDD — — V
D043A OSC1 (HS mode) 0.7 VDD — — V
D043B OSC1 (RC mode) 0.9 VDD — — V VDD > 2.0V (Note 1)
IIL Input Leakage Current(2)
D060 I/O ports — ±5 ± 125 nA VSS  VPIN  VDD, Pin at high-
impedance @ 85°C
±5 ± 1000 nA 125°C
D061 MCLR(3) — ± 50 ± 200 nA VSS  VPIN  VDD @ 85°C
IPUR Weak Pull-up Current
D070* 25 100 200 VDD = 3.3V, VPIN = VSS
25 140 300 A VDD = 5.0V, VPIN = VSS
VOL Output Low Voltage(4)
D080 I/O ports IOL = 8mA, VDD = 5V
— — 0.6 V IOL = 6mA, VDD = 3.3V
IOL = 1.8mA, VDD = 1.8V
VOH Output High Voltage(4)
D090 I/O ports IOH = 3.5mA, VDD = 5V
VDD - 0.7 — — V IOH = 3mA, VDD = 3.3V
IOH = 1mA, VDD = 1.8V
not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: Including OSC2 in CLKOUT mode.

PIC16(L)F1933
30.4 DC Characteristics: I/O Ports (Continued)
DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial
Param
No.
Capacitive Loading Specs on Output Pins
D101* COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when
external clock is used to drive
OSC1
D101A* CIO All I/O pins — — 50 pF
VCAP Capacitor Charging
D102 Charging current — 200 — A
D102A Source/sink capability when — 0.0 — mA
charging complete
not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: Including OSC2 in CLKOUT mode.

PIC16(L)F1933
30.5 Memory Programming Requirements

DC CHARACTERISTICS
Operating temperature -40°C  TA  +125°C
Param
No.
Program Memory
Programming Specifications
D110 VIHH Voltage on MCLR/VPP/RE3 pin 8.0 — 9.0 V (Note 3, Note 4)
D111 IDDP Supply Current during — — 10 mA
Programming
D112 VDD for Bulk Erase 2.7 — VDDMAX V
D113 VPEW VDD for Write or Row Erase VDDMIN — VDDMAX V
D114 IPPPGM Current on MCLR/VPP during — — 1.0 mA
Erase/Write
D115 IDDPGM Current on VDD during Erase/ — — 5.0 mA
Write
Data EEPROM Memory
D116 ED Byte Endurance 100K — — E/W -40C to +85C
D117 VDRW VDD for Read/Write VDDMIN — VDDMAX V
D118 TDEW Erase/Write Cycle Time — 4.0 5.0 ms
D119 TRETD Characteristic Retention — 40 — Year Provided no other
specifications are violated
D120 TREF Number of Total Erase/Write 1M 10M — E/W -40°C to +85°C
Cycles before Refresh(2)
Program Flash Memory
D121 EP Cell Endurance 10K — — E/W -40C to +85C (Note 1)
D122 VPRW VDD for Read/Write VDDMIN — VDDMAX V
D123 TIW Self-timed Write Cycle Time — 2 2.5 ms
D124 TRETD Characteristic Retention — 40 — Year Provided no other
specifications are violated
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Self-write and Block Erase.
2: Refer to Section 11.2 “Using the Data EEPROM” for a more detailed discussion on data EEPROM
endurance.
3: Required only if single-supply programming is disabled.
4: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the ICD 2 VPP voltage must be
placed between the ICD 2 and target system when programming or debugging with the ICD 2.

PIC16(L)F1933
30.6 Thermal Considerations
Param
Sym. Characteristic Typ. Units Conditions
No.
TH01 JA Thermal Resistance Junction to Ambient 60.0 C/W 28-pin SPDIP package
69.7 C/W 28-pin SOIC package
71.0 C/W 28-pin SSOP package
27.5 C/W 28-pin UQFN 4x4mm package
31.1 C/W 28-pin QFN 6x6mm package
TH02 JC Thermal Resistance Junction to Case 29.0 C/W 28-pin SPDIP package
18.9 C/W 28-pin SOIC package
24.0 C/W 28-pin SSOP package
24.0 C/W 28-pin UQFN 4x4mm package
5.0 C/W 28-pin QFN 6x6mm package
TH03 TJMAX Maximum Junction Temperature 150 C
TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O
TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1)
TH06 PI/O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH))
TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2)
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature
3: TJ = Junction Temperature

PIC16(L)F1933
30.7 Timing Parameter Symbology
The timing parameter symbols have been created with
one of the following formats:
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O PORT t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (High-impedance) V Valid
L Low Z High-impedance
FIGURE 30-5: LOAD CONDITIONS

Load Condition
Pin Cl
Vss
Legend: CL = 50 pF for all pins, 15 pF for

OSC2 output

PIC16(L)F1933
30.8 AC Characteristics: PIC16(L)F1933-I/E
FIGURE 30-6: CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1/CLKIN
OS02
OS04 OS04
OS03
OSC2/CLKOUT
(LP,XT,HS Modes)
OSC2/CLKOUT
(CLKOUT Mode)
TABLE 30-1: CLOCK OSCILLATOR TIMING REQUIREMENTS

Param
No.
OS01 FOSC External CLKIN Frequency(1) DC — 0.5 MHz EC Oscillator mode (low)
DC — 4 MHz EC Oscillator mode (medium)
DC — 20 MHz EC Oscillator mode (high)
Oscillator Frequency(1) — 32.768 — kHz LP Oscillator mode
0.1 — 4 MHz XT Oscillator mode
1 — 4 MHz HS Oscillator mode
1 — 20 MHz HS Oscillator mode, VDD > 2.7V
DC — 4 MHz RC Oscillator mode, VDD > 2.0V
OS02 TOSC External CLKIN Period(1) 27 —  s LP Oscillator mode
250 —  ns XT Oscillator mode
50 —  ns HS Oscillator mode
50 —  ns EC Oscillator mode
Oscillator Period(1) — 30.5 — s LP Oscillator mode
250 — 10,000 ns XT Oscillator mode
50 — 1,000 ns HS Oscillator mode
250 — — ns RC Oscillator mode
OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC
OS04* TosH, External CLKIN High, 2 — — s LP oscillator
TosL External CLKIN Low 100 — — ns XT oscillator
20 — — ns HS oscillator
OS05* TosR, External CLKIN Rise, 0 —  ns LP oscillator
TosF External CLKIN Fall 0 —  ns XT oscillator
0 —  ns HS oscillator
†Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external
clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

PIC16(L)F1933
TABLE 30-2: OSCILLATOR PARAMETERS
Operating Temperature -40°C TA +125°C
Param Freq.
No. Tolerance
OS08 HFOSC Internal Calibrated HFINTOSC ±2% — 16.0 — MHz 0°C  TA  +60°C, VDD 2.5V
Frequency(1) ±3% — 16.0 — MHz 60°C TA 85°C, VDD 2.5V
±5% — 16.0 — MHz -40°C  TA  +125°C
OS08A MFOSC Internal Calibrated MFINTOSC ±2% — 500 — kHz 0°C  TA  +60°C, VDD 2.5V
Frequency(1) ±3% — 500 — kHz 60°C TA 85°C, VDD 2.5V
±5% — 500 — kHz -40°C  TA  +125°C
OS09 LFOSC Internal LFINTOSC Frequency ±25% — 31 — kHz -40°C  TA  +125°C
OS10* TIOSC ST HFINTOSC — — 3.2 8 s
Wake-up from Sleep Start-up Time
MFINTOSC — — 24 35 s
Wake-up from Sleep Start-up Time
*These parameters are characterized but not tested.
tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
TABLE 30-3: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.7V TO 5.5V)

Param
No.
F10 FOSC Oscillator Frequency Range (Note 1) 4 — 8 MHz
F11 FSYS On-Chip VCO System Frequency 16 — 32 MHz
F12 TRC PLL Start-up Time (Lock Time) — — 2 ms
F13* CLK CLKOUT Stability (Jitter) -0.25% — +0.25% %
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
Note 1: The min. and max. frequency specifications are the oscillator nominal frequencies. Oscillators may have
frequency tolerances of up to ±5%.

PIC16(L)F1933
FIGURE 30-7: CLKOUT AND I/O TIMING
Cycle Write Fetch Read Execute

Q4 Q1 Q2 Q3
FOSC
OS11 OS12
OS20
CLKOUT OS21
OS19 OS16 OS18
OS13 OS17
I/O pin
(Input)
OS15 OS14
I/O pin Old Value New Value
(Output)
OS18, OS19
TABLE 30-4: CLKOUT AND I/O TIMING PARAMETERS

Param
No.
OS11 TosH2ckL FOSC to CLKOUT (1) — — 70 ns VDD = 3.3-5.0V
(1)
OS12 TosH2ckH FOSC to CLKOUT — — 72 ns VDD = 3.3-5.0V
OS13 TckL2ioV CLKOUT to Port out valid(1) — — 20 ns
OS14 TioV2ckH Port input valid before CLKOUT(1) TOSC + 200 ns — — ns
OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid — 50 70* ns VDD = 3.3-5.0V
OS16 TosH2ioI Fosc (Q2 cycle) to Port input invalid 50 — — ns VDD = 3.3-5.0V
(I/O in hold time)
OS17 TioV2osH Port input valid to Fosc(Q2 cycle) 20 — — ns
(I/O in setup time)
OS18 TioR Port output rise time — 40 72 ns VDD = 1.8V
— 15 32 VDD = 3.3-5.0V
OS19 TioF Port output fall time — 28 55 ns VDD = 1.8V
— 15 30 VDD = 3.3-5.0V
OS20* Tinp INT pin input high or low time 25 — — ns
OS21* Tioc Interrupt-on-change new input level 25 — — ns
time
† Data in “Typ” column is at 3.0V, 25C unless otherwise stated.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.

PIC16(L)F1933
FIGURE 30-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out 32
OSC
Start-Up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
31
34
34
I/O pins
Note 1: Asserted low.
FIGURE 30-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
VBOR and VHYST
VBOR
(Device in Brown-out Reset) (Device not in Brown-out Reset)
37
Reset
33(1)
(due to BOR)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Words register is programmed to ‘0’.
2 ms delay if PWRTE = 0 and VREGEN = 1.

PIC16(L)F1933
TABLE 30-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Param
No.
30 TMCL MCLR Pulse Width (low) 2 — — s
31 TWDTLP Low-Power Watchdog Timer 10 16 27 ms VDD = 3.3V-5V
Time-out Period 1:16 Prescaler used
32 TOST Oscillator Start-up Timer Period(1) — 1024 — Tosc
33* TPWRT Power-up Timer Period, PWRTE = 0 40 65 140 ms
34* TIOZ I/O high-impedance from MCLR Low — — 2.0 s
or Watchdog Timer Reset
35 VBOR Brown-out Reset Voltage(2) 2.38 2.5 2.73 V BORV = 0
1.80 1.9 2.11 V BORV = 1
36* VHYST Brown-out Reset Hysteresis 0 25 60 mV -40°C to +85°C
37* TBORDC Brown-out Reset DC Response 1 3 35 s VDD  VBOR
Time
Note 1: By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency.
2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
FIGURE 30-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40 41
42
T1CKI
45 46
47 49
TMR0 or
TMR1

PIC16(L)F1933
TABLE 30-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns
42* TT0P T0CKI Period Greater of: — — ns N = prescale value
20 or TCY + 40 (2, 4, ..., 256)
N
45* TT1H T1CKI High Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Time Synchronous, 15 — — ns
with Prescaler
Asynchronous 30 — — ns
46* TT1L T1CKI Low Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Time Synchronous, with Prescaler 15 — — ns
47* TT1P T1CKI Input Synchronous Greater of: — — ns N = prescale value
Period 30 or TCY + 40 (1, 2, 4, 8)
N
48 FT1 Timer1 Oscillator Input Frequency Range 32.4 32.768 33.1 kHz
(oscillator enabled by setting bit T1OSCEN)
49* TCKEZTMR1 Delay from External Clock Edge to Timer 2 TOSC — 7 TOSC — Timers in Sync
Increment mode
tested.
FIGURE 30-11: CAPTURE/COMPARE/PWM TIMINGS (CCP)

CCPx
(Capture mode)
CC01 CC02
CC03
Note: Refer to Figure 30.5 for load conditions.
TABLE 30-7: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)

Operating Temperature -40°C  TA  +125°C
Param
No.
CC01* TccL CCPx Input Low Time No Prescaler 0.5TCY + 20 — — ns
CC02* TccH CCPx Input High Time No Prescaler 0.5TCY + 20 — — ns
CC03* TccP CCPx Input Period 3TCY + 40 — — ns N = prescale value
N
tested.

PIC16(L)F1933
TABLE 30-8: PIC16(L)F1933 A/D CONVERTER (ADC) CHARACTERISTICS:(1,2,3)
Operating temperature Tested at25°C
Param
No.
AD01 NR Resolution — — 10 bit
AD02 EIL Integral Error — — ±1.7 LSb VREF = 3.0V
AD03 EDL Differential Error — — ±1 LSb No missing codes
VREF = 3.0V
AD04 EOFF Offset Error — — ±2.5 LSb VREF = 3.0V
AD05 EGN Gain Error — — ±2.0 LSb VREF = 3.0V
AD06 VREF Reference Voltage(4) 1.8 — VDD V VREF = (VREF+ minus VREF-)
AD07 VAIN Full-Scale Range VSS — VREF V
AD08 ZAIN Recommended Impedance of — — 10 k Can go higher if external 0.01F capacitor is
Analog Voltage Source present on input pin.
tested.
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
3: ADC VREF is from external VREF, VDD pin or FVR, whichever is selected as reference input.
4: ADC Reference Voltage (Ref+) is the selected reference input, VREF+ pin, VDD pin or the FVR Buffer1. When the FVR is
selected as the reference input, the FVR Buffer1 output selection must be 2.048V or 4.096V, (ADFVR<1:0> = 1x).
TABLE 30-9: PIC16(L)F1933 A/D CONVERSION REQUIREMENTS

Param
No.
AD130* TAD A/D Clock Period 1.0 — 9.0 s TOSC-based
A/D Internal RC Oscillator 1.0 2.5 6.0 s ADCS<1:0> = 11 (ADRC mode)
Period
AD131 TCNV Conversion Time (not including — 11 — TAD Set GO/DONE bit to conversion
Acquisition Time)(1) complete
AD132* TACQ Acquisition Time — 5.0 — s
*These parameters are characterized but not tested.
tested.
Note 1: The ADRES register may be read on the following TCY cycle.

PIC16(L)F1933
FIGURE 30-12: PIC16(L)F1933 A/D CONVERSION TIMING (NORMAL MODE)
BSF ADCON0, GO
1 Tcy
AD134 (TOSC/2(1))
AD131
Q4
AD130
A/D CLK
A/D Data 7 6 5 4 3 2 1 0
ADRES OLD_DATA NEW_DATA
ADIF 1 Tcy
GO DONE
AD132 Sampling Stopped

Sample
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
FIGURE 30-13: PIC16(L)F1933 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO
AD134 (TOSC/2 + TCY(1)) 1 Tcy
AD131
Q4
AD130
A/D CLK
A/D Data 7 6 5 4 3 2 1 0
ADRES OLD_DATA NEW_DATA
ADIF 1 Tcy
GO DONE
AD132 Sampling Stopped

Sample
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.

PIC16(L)F1933
TABLE 30-10: COMPARATOR SPECIFICATIONS
Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated).
Param
Sym. Characteristics Min. Typ. Max. Units Comments
No.
CM01 VIOFF Input Offset Voltage(1) — ±7.5 ±60 mV High-Power mode
VICM = VDD/2
CM02 VICM Input Common Mode Voltage 0 — VDD V
CM03 CMRR Common Mode Rejection Ratio — 50 — dB
CM04A Response Time Rising Edge — 400 800 ns High-Power mode
CM04B Response Time Falling Edge — 200 400 ns High-Power mode
TRESP
CM04C Response Time Rising Edge — 1200 — ns Low-Power mode
CM04D Response Time Falling Edge — 550 — ns Low-Power mode
CM05 TMC2OV Comparator Mode Change to — — 10 s
Output Valid*
CM06 CHYSTER Comparator Hysteresis(2) — 45 — mV CxHYS = 1
Note 1: High-Power mode only.
2: Comparator Hysteresis is available when the CxHYS bit of the CMxCON0 register is enabled.
TABLE 30-11: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS

Operating Conditions: 2.5V < VDD < 5.5V, -40°C < Ta < +125°C (unless otherwise stated).
Param
Sym. Characteristics Min. Typ. Max. Units Comments
No.
DAC01* CLSB Step Size(2) — VDD/32 — V
DAC02* CACC Absolute Accuracy — —  1/2 LSb
DAC03* CR Unit Resistor Value (R) — 5000 — 
DAC04* CST Settling Time(1) — — 10 s
Note 1: Settling time measured while DACR<4:0> transitions from ‘0000’ to ‘1111’.
FIGURE 30-14: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
CK
US121 US121
DT
US120 US122
Note: Refer to Figure 30-5 for load conditions.

PIC16(L)F1933
TABLE 30-12: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param.
Symbol Characteristic Min. Max. Units Conditions
No.
US120 TCKH2DTV SYNC XMIT (Master and Slave) 3.0-5.5V — 80 ns
Clock high to data-out valid 1.8-5.5V — 100 ns
US121 TCKRF Clock out rise time and fall time 3.0-5.5V — 45 ns
(Master mode) 1.8-5.5V — 50 ns
US122 TDTRF Data-out rise time and fall time 3.0-5.5V — 45 ns
1.8-5.5V — 50 ns
FIGURE 30-15: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
CK
US125
DT
US126
TABLE 30-13: USART SYNCHRONOUS RECEIVE REQUIREMENTS

Param.
No.
US125 TDTV2CKL SYNC RCV (Master and Slave)
Data-hold before CK  (DT hold time) 10 — ns
US126 TCKL2DTL Data-hold after CK  (DT hold time) 15 — ns

PIC16(L)F1933
FIGURE 30-16: SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
SS
SP70
SCK
(CKP = 0)
SP71 SP72
SP78 SP79
SCK
(CKP = 1)
SP79 SP78
SP80
SDO MSb bit 6 - - - - - -1 LSb
SP75, SP76
SDI MSb In bit 6 - - - -1 LSb In
SP74
SP73
FIGURE 30-17: SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SS
SP81
SCK
(CKP = 0)
SP71 SP72
SP79
SP73
SCK
(CKP = 1)
SP80
SP78
SP75, SP76
SP74

PIC16(L)F1933
FIGURE 30-18: SPI SLAVE MODE TIMING (CKE = 0)
SS
SP70
SCK SP83
(CKP = 0)
SP71 SP72
SP78 SP79
SCK
(CKP = 1)
SP79 SP78
SP80
SP75, SP76 SP77
SP74
SP73
FIGURE 30-19: SPI SLAVE MODE TIMING (CKE = 1)
SP82
SS
SP70
SCK SP83
(CKP = 0)
SP71 SP72
SCK
(CKP = 1)
SP80
SP77
SP75, SP76
SDI
MSb In bit 6 - - - -1 LSb In
SP74

PIC16(L)F1933
TABLE 30-14: SPI MODE REQUIREMENTS
Param
Symbol Characteristic Min. Typ† Max. Units Conditions
No.
SP70* TSSL2SCH, SS to SCK or SCK input TCY — — ns

TSSL2SCL
SP71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns
SP72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns
SP73* TDIV2SCH, Setup time of SDI data input to SCK edge 100 — — ns
TDIV2SCL
SP74* TSCH2DIL, Hold time of SDI data input to SCK edge 100 — — ns
TSCL2DIL
SP75* TDOR SDO data output rise time 3.0-5.5V — 10 25 ns
1.8-5.5V — 25 50 ns
SP76* TDOF SDO data output fall time — 10 25 ns
SP77* TSSH2DOZ SS to SDO output high-impedance 10 — 50 ns
SP78* TSCR SCK output rise time 3.0-5.5V — 10 25 ns
(Master mode) 1.8-5.5V — 25 50 ns
SP79* TSCF SCK output fall time (Master mode) — 10 25 ns
SP80* TSCH2DOV, SDO data output valid after 3.0-5.5V — — 50 ns
TSCL2DOV SCK edge 1.8-5.5V — — 145 ns
SP81* TDOV2SCH, SDO data output setup to SCK edge Tcy — — ns
TDOV2SCL
SP82* TSSL2DOV SDO data output valid after SS edge — — 50 ns
SP83* TSCH2SSH, SS after SCK edge 1.5TCY + 40 — — ns
TSCL2SSH
FIGURE 30-20: I2C™ BUS START/STOP BITS TIMING
SCL
SP91 SP93
SP90 SP92
SDA
Start Stop
Condition Condition

PIC16(L)F1933
TABLE 30-15: I2C™ BUS START/STOP BITS REQUIREMENTS
Param
Symbol Characteristic Min. Typ Max. Units Conditions
No.
SP90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated
Setup time 400 kHz mode 600 — — Start condition
SP91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first
Hold time 400 kHz mode 600 — — clock pulse is generated
SP92* TSU:STO Stop condition 100 kHz mode 4700 — — ns
Setup time 400 kHz mode 600 — —
SP93 THD:STO Stop condition 100 kHz mode 4000 — — ns
Hold time 400 kHz mode 600 — —
FIGURE 30-21: I2C™ BUS DATA TIMING
SP103 SP100 SP102

SP101
SCL
SP90
SP106
SP107
SP91 SP92
SDA
In
SP110
SP109
SP109
SDA
Out

PIC16(L)F1933
TABLE 30-16: I2C™ BUS DATA REQUIREMENTS
Param.
No.
SP100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — s Device must operate at a
minimum of 10 MHz
SSP module 1.5TCY —
SP101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 — s Device must operate at a
minimum of 10 MHz
SSP module 1.5TCY —
SP102* TR SDA and SCL rise 100 kHz mode — 1000 ns
time 400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from
10-400 pF
SP103* TF SDA and SCL fall 100 kHz mode — 250 ns
time 400 kHz mode 20 + 0.1CB 250 ns CB is specified to be from
10-400 pF
SP106* THD:DAT Data input hold time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 s
SP107* TSU:DAT Data input setup 100 kHz mode 250 — ns (Note 2)
time 400 kHz mode 100 — ns
SP109* TAA Output valid from 100 kHz mode — 3500 ns (Note 1)
clock 400 kHz mode — — ns
SP110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free
400 kHz mode 1.3 — s before a new transmission
can start
SP111 CB Bus capacitive loading — 400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but
the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does
not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal,
it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to
the Standard mode I2C bus specification), before the SCL line is released.

PIC16(L)F1933
TABLE 30-17: CAP SENSE OSCILLATOR SPECIFICATIONS
Param.
Symbol Characteristic Min. Typ† Max. Units Conditions
No.
CS01* ISRC Current Source High — -8 — A
Medium — -1.5 — A
Low — -0.3 — A
CS02* ISNK Current Sink High — 7.5 — A
Medium — 1.5 — A
Low — 0.25 — A
CS03* VCTH Cap Threshold — 0.8 — mV
CS04* VCTL Cap Threshold — 0.4 — mV
CS05* VCHYST Cap Hysteresis High — 525 — mV
(VCTH-VCTL) Medium — 375 — mV
Low — 300 — mV
FIGURE 30-22: CAP SENSE OSCILLATOR
VCTH
VCTL
ISRC ISNK
Enabled Enabled

PIC16(L)F1933
NOTES:

PIC16(L)F1933
31.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25C. “MAXIMUM”, “Max.”, “MINIMUM” or “Min.”
represents (mean + 3) or (mean - 3) respectively, where  is a standard deviation, over each
temperature range.

PIC16(L)F1933
FIGURE 31-1: IDD, LP OSCILLATOR MODE, FOSC = 32 kHz, PIC16LF1933 ONLY
14
Max: 85°C + 3 Max.
12 Typical: 25°C
10
Typical
8
IDD (μA)
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 31-2: IDD, LP OSCILLATOR MODE, FOSC = 32 kHz, PIC16F1933 ONLY
60
Max: 85°C + 3
Typical: 25°C
50 Max.
40 Typical
IDD (μA)
30
20
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1933
FIGURE 31-3: IDD TYPICAL, XT AND EXTRC OSCILLATOR MODE, PIC16LF1933 ONLY
600
4 MHz XT
Typical: 25°C
500
4 MHz EXTRC
400
IDD (μA)
300
1 MHz XT
200
100
1 MHz EXTRC
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 31-4: IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16LF1933 ONLY
700
Max: 85°C + 3
600
4 MHz XT
500
4 MHz EXTRC
400
IDD (μA)
300
1 MHz XT
200
100
1 MHz EXTRC
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)

PIC16(L)F1933
FIGURE 31-5: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC16F1933 ONLY
700
Typical: 25°C 4 MHz XT
600
4 MHz EXTRC
500
400
IDD (μA)
300
1 MHz XT
200
100 1 MHz EXTRC
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
FIGURE 31-6: IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16F1933 ONLY
800
4 MHz XT
700 Max: 85°C + 3
600
4 MHz EXTRC
500
IDD (μA)
400
300 1 MHz XT
200
100 1 MHz EXTRC
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1933
FIGURE 31-7: IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 500 kHz, PIC16LF1933 ONLY
120
Max: 85°C + 3
100 Typical: 25°C
Max.
80
IDD (μA)
60 Typical
40
20
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 31-8: IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 500 kHz, PIC16F1933 ONLY
120
Max: 85°C + 3 Max.

100 Typical: 25°C
80 Typical
IDD (μA)
60
40
20
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC16(L)F1933
FIGURE 31-9: IDD TYPICAL, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16LF1933 ONLY
400
350 Typical: 25°C 4 MHz
300
250
IDD (μA)
200
150
100
50 1 MHz
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 31-10: IDD MAXIMUM, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16LF1933 ONLY
450
400
4 MHz
350
300 Max: 85°C + 3

IDD (μA)
250
200
150
100
50 1 MHz
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)

PIC16(L)F1933
FIGURE 31-11: IDD TYPICAL, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16F1933 ONLY
700
Typical: 25°C 4 MHz

600
500
IDD (μA)
400
300
200 1 MHz
100
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
FIGURE 31-12: IDD MAXIMUM, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16F1933 ONLY
700
4 MHz
600 Max: 85°C + 3
500
IDD (μA)
400
300
200 1 MHz
100
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1933
FIGURE 31-13: IDD TYPICAL, EC OSCILLATOR, HIGH-POWER MODE, PIC16LF1933 ONLY
4.5
4.0 Typical: 25°C 32 MHz (PLL)
3.5
3.0
IDD (mA)
2.5
2.0
16 MHz
1.5
1.0
8 MHz
0.5
0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 31-14: IDD MAXIMUM, EC OSCILLATOR, HIGH-POWER MODE, PIC16LF1933 ONLY
5.0
4.5 Max: 85°C + 3 32 MHz (PLL)

4.0
3.5
3.0
IDD (mA)
2.5
2.0
16 MHz
1.5
1.0
8 MHz
0.5
0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)

PIC16(L)F1933
FIGURE 31-15: IDD TYPICAL, EC OSCILLATOR, HIGH-POWER MODE, PIC16F1933 ONLY
4.0
3.0
2.5
IDD (mA)
2.0
16 MHz
1.5
1.0 8 MHz
0.5
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
FIGURE 31-16: IDD MAXIMUM, EC OSCILLATOR, HIGH-POWER MODE, PIC16F1933 ONLY
4.5
4.0 Max: 85°C + 3

32 MHz (PLL)
3.5
3.0
IDD (mA)
2.5
2.0 16 MHz
1.5
1.0 8 MHz
0.5
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1933
FIGURE 31-17: IDD, LFINTOSC MODE, FOSC = 31 kHz, PIC16LF1933 ONLY
12
Max: 85°C + 3
10 Typical: 25°C
Max.
8
IDD (μA)
6 Typical
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 31-18: IDD, LFINTOSC MODE, FOSC = 31 kHz, PIC16F1933 ONLY
45
40 Max.
35
30 Typical
IDD (μA)
25
20
15
10
Max: 85°C + 3
5 Typical: 25°C
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC16(L)F1933
FIGURE 31-19: IDD, MFINTOSC MODE, FOSC = 500 kHz, PIC16LF1933 ONLY
200
Max.
190 Max: 85°C + 3
Typical: 25°C
180
170 Typical
160
IDD (μA)
150
140
130
120
110
100
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 31-20: IDD, MFINTOSC MODE, FOSC = 500 kHz, PIC16F1933 ONLY
300
Max.
280
Max: 85°C + 3
260 Typical: 25°C
240 Typical
220
IDD (μA)
200
180
160
140
120
100
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC16(L)F1933
FIGURE 31-21: IDD TYPICAL, HFINTOSC MODE, PIC16LF1933 ONLY
5.0

4.0
3.5
3.0
IDD (mA)
2.5 16 MHz
2.0
8 MHz
1.5
1.0 4 MHz
0.5
0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 31-22: IDD MAXIMUM, HFINTOSC MODE, PIC16LF1933 ONLY
6.0
Max: 85°C + 3
5.0 32 MHz (PLL)
4.0
IDD (mA)
3.0
16 MHz
2.0
8 MHz
1.0 4 MHz
0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)

PIC16(L)F1933
FIGURE 31-23: IDD TYPICAL, HFINTOSC MODE, PIC16F1933 ONLY
4.5
4.0 Typical: 25°C

32 MHz (PLL)
3.5
3.0
2.5 16 MHz
IDD (mA)
2.0
8 MHz
1.5
1.0 4 MHz
0.5
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
FIGURE 31-24: IDD MAXIMUM, HFINTOSC MODE, PIC16F1933 ONLY
4.5
4.0 Max: 85°C + 3 32 MHz (PLL)
3.5
3.0
16 MHz
IDD (mA)
2.5
2.0
8 MHz
1.5
1.0 4 MHz
0.5
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1933
FIGURE 31-25: IDD TYPICAL, HS OSCILLATOR, PIC16LF1933 ONLY
3.5
3 Typical: 25°C 32 MHz (PLL)
2.5
2 20 MHz
IDD (mA)
1.5
1 8 MHz
0.5
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 31-26: IDD MAXIMUM, HS OSCILLATOR, PIC16LF1933 ONLY
3.5
3.0 Max: 85°C + 3 32 MHz (PLL)
2.5
20 MHz
2.0
IDD (mA)
1.5
1.0 8 MHz
0.5
0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)

PIC16(L)F1933
FIGURE 31-27: IDD TYPICAL, HS OSCILLATOR, PIC16F1933 ONLY
4.5
32 MHz (PLL)
4 Typical: 25°C
3.5
2.5
20 MHz
IDD (mA)
1.5
8 MHz
1
0.5
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
FIGURE 31-28: IDD MAXIMUM, HS OSCILLATOR, PIC16F1933 ONLY
4.5
4.0
Max: 85°C + 3 32 MHz (PLL)
3.5
3.0
2.5 20 MHz
IDD (mA)
2.0
1.5
8 MHz
1.0
0.5
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1933
FIGURE 31-29: IPD BASE, LOW-POWER SLEEP MODE, PIC16LF1933 ONLY
1,200
Max: 85°C + 3 Max.

1,000
Typical: 25°C
800
D (nA)
600
IPD
400
200
Typical
yp
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 31-30: IPD BASE, LOW-POWER SLEEP MODE, PIC16F1933 ONLY
50
45 Max: 85°C + 3
M 3
Typical: 25°C
Max.
40
35
30
IPD (μA)
Typical
25
20
15
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1933
FIGURE 31-31: IPD, WATCHDOG TIMER (WDT), PIC16LF1933 ONLY
2500
2000 Max: 85°C + 3

Typical: 25°C
Max.
1500
(μA)
IPD (μA
1000
Typical
500
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 31-32: IPD, WATCHDOG TIMER (WDT), PIC16F1933 ONLY
45
Max: 85°C + 3
M 3 Max.
40
Typical: 25°C
35
30
Typical
A)
IPD (μA
25
20
15
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1933
FIGURE 31-33: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16LF1933 ONLY
14
Max.
12
10 Typical
8
A)
IPD (μA
2 Max: 85°C + 3
yp
Typical: 25°C
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 31-34: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16F1933 ONLY
120
Max: 85°C + 3 Max.

100
Typical: 25°C
Typical
80
IPD (μA)
60
40
20
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1933
FIGURE 31-35: IPD, BROWN-OUT RESET (BOR), PIC16LF1933 ONLY
12
Max: 85°C + 3 Max.
11 Typical: 25°C
10
9
Typical
IPD (μA)
4
1 8
1.8 2 0
2.0 2 2
2.2 2 4
2.4 2 6
2.6 2 8
2.8 3 0
3.0 3 2
3.2 3 4
3.4 3 6
3.6 3 8
3.8
VDD (V)
FIGURE 31-36: IPD, BROWN-OUT RESET (BOR), PIC16F1933 ONLY
50
Max: 85°C + 3 Max
Max.
45
Typical: 25°C
40
35
Typical
30
IPD (μA)
25
20
15
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1933
FIGURE 31-37: IPD, TIMER1 OSCILLATOR, FOSC = 32 kHz, PIC16LF1933 ONLY
Max: 85°C + 3
M 3
5 Typical: 25°C
Max.
4
A)
IPD (μA
Typical
2
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 31-38: IPD, TIMER1 OSCILLATOR, FOSC = 32 kHz, PIC16F1933 ONLY
60
50 Max.
40
Typical
IPD (μA)
30
20
10 Max: 85°C + 3
Typical: 25°C
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1933
FIGURE 31-39: IPD, CAPACITIVE SENSING (CPS) MODULE, LOW-CURRENT RANGE,
CPSRM = 0, CPSRNG = 01, PIC16LF1933 ONLY
8
Max.
Max: 85°C + 3
M 3
7
Typical: 25°C
5
A)
IPD (μA
4 Typical
0
16
1.6 1 8
1.8 2 0
2.0 2 2
2.2 2 4
2.4 2 6
2.6 2 8
2.8 3 0
3.0 3 2
3.2 3 4
3.4 3 6
3.6 3 8
3.8
VDD (V)
FIGURE 31-40: IPD, CAPACITIVE SENSING (CPS) MODULE, LOW-CURRENT RANGE,

CPSRM = 0, CPSRNG = 01, PIC16F1933 ONLY
45
40 Max: 85°C + 3 Max.

Typical: 25°C
35
30
Typical
A)
25
IPD (μA
20
15
10
0
1 5
1.5 2 0
2.0 2 5
2.5 3 0
3.0 3 5
3.5 4 0
4.0 4 5
4.5 5 0
5.0 5 5
5.5 6 0
6.0
VDD (V)

PIC16(L)F1933
FIGURE 31-41: IPD, CAPACITIVE SENSING (CPS) MODULE, MEDIUM-CURRENT RANGE,
14
Max: 85°C + 3
12 Max.
Typical: 25°C
10
8
D (μA)
IPD
6
Typical
4
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 31-42: IPD, CAPACITIVE SENSING (CPS) MODULE, MEDIUM-CURRENT RANGE,

60
50 Max.
40
Typical
A)
IPD (μA
30
20
10 Max: 85°C + 3
yp
Typical: 25°C
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1933
FIGURE 31-43: IPD, CAPACITIVE SENSING (CPS) MODULE, HIGH-CURRENT RANGE,
70
Max: 85°C + 3
M 3
60 Typical: 25°C
Max.
50
40
A)
IPD (μA
30
20
Typical
10
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 31-44: IPD, CAPACITIVE SENSING (CPS) MODULE, HIGH-CURRENT RANGE,

140
Max: 85°C + 3 Max

Max.
120 Typical: 25°C
100
80
A)
IPD (μA
Typical
60
40
20
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1933
FIGURE 31-45: IPD, COMPARATOR, LOW-POWER MODE, CxSP = 0, PIC16LF1933 ONLY
30
Max
Max.
25
20
Typical
IPD (μA)
15
10
5 Max: 85°C + 3
Typical: 25°C
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 31-46: IPD, COMPARATOR, LOW-POWER MODE, CxSP = 0, PIC16F1933 ONLY
60
50 Max.
40
Typical
IPD (μA)
30
20
10 Max: 85°C + 3
Typical: 25°C
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1933
FIGURE 31-47: IPD, COMPARATOR, NORMAL-POWER MODE, CxSP = 1, PIC16LF1933 ONLY
50
45
Max.
40
35
Typical
30
A)
IPD (μA
25
20
15
Max: 85°C + 3
10
Typical: 25°C
5
0
16
1.6 1
1.8
8 2
2.0
0 2
2.2
2 2
2.4
4 2
2.6
6 2
2.8
8 3
3.0
0 3
3.2
2 3
3.4
4 3
3.6
6 3
3.8
8
VDD (V)
FIGURE 31-48: IPD, COMPARATOR, NORMAL-POWER MODE, CxSP = 1, PIC16F1933 ONLY
80
70 M
Max.
60
50 Typical
A)
IPD (μA
40
30
20
10 Max: 85°C + 3
yp
Typical: 25°C
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1933
FIGURE 31-49: VOH vs. IOH, OVER TEMPERATURE, VDD = 5.0V, PIC16F1933 ONLY
Graph represents
5
3 Limits
4
VOH (V)
-40°C
3
125°C
2 Typical
0
-30 -25 -20 -15 -10 -5 0
IOH (mA)
FIGURE 31-50: VOL vs. IOL, OVER TEMPERATURE, VDD = 5.0V, PIC16F1933 ONLY
Graph represents
4 3 Limits
3
VOL (V)
-40°C
2 Typical
125°C
0
0 10 20 30 40 50 60 70 80
IOL (mA)

PIC16(L)F1933
FIGURE 31-51: VOH vs. IOH, OVER TEMPERATURE, VDD = 3.0V
3.5
3.0 Graph represents

3 Limits
2.5
VOH (V)
2.0
1.5 125°C
Typical
1.0
-40°C
0.5
0.0
-14 -12 -10 -8 -6 -4 -2 0
IOH (mA)
FIGURE 31-52: VOL vs. IOL, OVER TEMPERATURE, VDD = 3.0V
3.0
Graph represents
2.5
3 Limits
2.0
VOL (V)
-40°C
1.5 Typical
125°C
1.0
0.5
0.0
0 5 10 15 20 25 30
IOL (mA)

PIC16(L)F1933
FIGURE 31-53: VOH vs. IOH, OVER TEMPERATURE, VDD = 1.8V
2.0

3 Limits
1.6
1.4
1.2
VOH (V)
1.0 125°C
0.8
Typical
0.6 -40°C
0.4
0.2
0.0
-4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0
IOH (mA)
FIGURE 31-54: VOL vs. IOL, OVER TEMPERATURE, VDD = 1.8V
1.8

3 Limits
1.4
1.2
VOL (V)
1.0
125°C Typical
0.8
-40°C
0.6
0.4
0.2
0.0
0 1 2 3 4 5 6 7 8 9 10
IOL (mA)

PIC16(L)F1933
FIGURE 31-55: POR RELEASE VOLTAGE
1.70
1.68
Max.
1.66
1.64 Typical
1.62
Voltage (V)
Min.
1.60
1.58
1.56
1.54 Max: Typical + 3

Typical: 25°C
1.52 Min: Typical - 3
1.50
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
FIGURE 31-56: POR REARM VOLTAGE, PIC16F1933 ONLY
1.54

Typical: 25°C
1.50 Min: Typical - 3
Max.
1.48
1.46
Voltage (V)
1.44
Typical
1.42
1.40
1.38 Min.
1.36
1.34
-40 -20 0 20 40 60 80 100 120
Temperature (°C)

PIC16(L)F1933
FIGURE 31-57: BROWN-OUT RESET VOLTAGE, BORV = 1
2.10

Min: Typical - 3
2.00
1.95 Max.
Voltage (V)
1.90
1.85
Min.
1.80
1.75
1.70
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
FIGURE 31-58: BROWN-OUT RESET HYSTERESIS, BORV = 1
70
60 Max.
50
Typical
Voltage (mV)
40
30
Min.
20
Max: Typical + 3
10 Typical: 25°C
Min: Typical - 3
0
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)

PIC16(L)F1933
FIGURE 31-59: BROWN-OUT RESET VOLTAGE, BORV = 0
2.65
2.60
Max.
2.55
Voltage (V)
2.50
2.45 Min.

Min: Typical - 3
2.35
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
FIGURE 31-60: BROWN-OUT RESET HYSTERESIS, BORV = 0
90
80
Max.
70
60
Voltage (mV)
50
Typical
40
30
20 Max: Typical Min.

+ 3
Min. Typical: 25°C
10 Min: Typical - 3
0
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)

PIC16(L)F1933
FIGURE 31-61: WDT TIME-OUT PERIOD
24
22
Max.
20
Time (mS)
18 Typical
16
14 Min.
Max: Typical + 3 (-40°C to +125°C)

12 Typical: statistical mean @ 25°C
Min: Typical - 3 (-40°C to +125°C)
10
1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Voltage (V)
FIGURE 31-62: PWRT PERIOD
110
100
Max.
90
Time (mS)
80 Typical
70
Min.
60
Max: Typical + 3 (-40°C to +125°C)

50 Typical: statistical mean @ 25°C
Min: Typical - 3 (-40°C to +125°C)
40
1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Voltage (V)

PIC16(L)F1933
FIGURE 31-63: COMPARATOR HYSTERESIS, NORMAL-POWER MODE, CxSP = 1, CxHYS = 1
100
90
80 Max.
70
Hysteresis (mV)
60 Typical
50
40 Max: Typical + 3
Typical: 25°C
30 Min: Typical - 3 Min.
20
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
FIGURE 31-64: COMPARATOR HYSTERESIS, LOW-POWER MODE, CxSP = 0, CxHYS = 1
25
Max: Typical + 3
20 Typical: 25°C
Min: Typical - 3
Hysteresis (mV)
15
Max.
Typical
10
Min.
5
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1933
FIGURE 31-65: COMPARATOR RESPONSE TIME, NORMAL-POWER MODE, CxSP = 1
390
Max: Typical + 3
340 Typical: 25°C
290
Time (nS)
240
Max.
190
Typical
140
90
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
FIGURE 31-66: COMPARATOR RESPONSE TIME OVER TEMPERATURE, NORMAL-POWER MODE,

CxSP = 1
260
Graph represents
240 3 Limits
220
Time (nS)
200
180
125°C
160
Typical
-40°C
140
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1933
FIGURE 31-67: COMPARATOR INPUT OFFSET AT 25°C, NORMAL-POWER MODE, CxSP = 1,
PIC16F1933 ONLY
60
40
Max.
20
Offset Voltage (mV)
Typical
0
Min.
-20
Max: Typical + 3
-40 Typical: 25°C
Min: Typical - 3
-60
0.0 1.0 2.0 3.0 4.0 5.0
Common Mode Voltage (V)

PIC16(L)F1933
NOTES:

PIC16(L)F1933
32.0 DEVELOPMENT SUPPORT 32.1 MPLAB Integrated Development
Environment Software
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software The MPLAB IDE software brings an ease of software
and hardware development tools: development previously unseen in the 8/16/32-bit
• Integrated Development Environment microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
- MPLAB® IDE Software
• Compilers/Assemblers/Linkers • A single graphical interface to all debugging tools
- MPLAB C Compiler for Various Device - Simulator
Families - Programmer (sold separately)
- HI-TECH C® for Various Device Families - In-Circuit Emulator (sold separately)
- MPASMTM Assembler - In-Circuit Debugger (sold separately)
- MPLINKTM Object Linker/ • A full-featured editor with color-coded context
MPLIBTM Object Librarian • A multiple project manager
- MPLAB Assembler/Linker/Librarian for • Customizable data windows with direct edit of
Various Device Families contents
• Simulators • High-level source code debugging
- MPLAB SIM Software Simulator • Mouse over variable inspection
• Emulators • Drag and drop variables from source to watch
- MPLAB REAL ICE™ In-Circuit Emulator windows
• In-Circuit Debuggers • Extensive on-line help
- MPLAB ICD 3 • Integration of select third party tools, such as
- PICkit™ 3 Debug Express IAR C Compilers
• Device Programmers The MPLAB IDE allows you to:
- PICkit™ 2 Programmer • Edit your source files (either C or assembly)
- MPLAB PM3 Device Programmer • One-touch compile or assemble, and download to
• Low-Cost Demonstration/Development Boards, emulator and simulator tools (automatically
Evaluation Kits, and Starter Kits updates all project information)
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.

PIC16(L)F1933
32.2 MPLAB C Compilers for Various 32.5 MPLINK Object Linker/
Device Families MPLIB Object Librarian
The MPLAB C Compiler code development systems The MPLINK Object Linker combines relocatable
are complete ANSI C compilers for Microchip’s PIC18, objects created by the MPASM Assembler and the
PIC24 and PIC32 families of microcontrollers and the MPLAB C18 C Compiler. It can link relocatable objects
dsPIC30 and dsPIC33 families of digital signal control- from precompiled libraries, using directives from a
lers. These compilers provide powerful integration linker script.
capabilities, superior code optimization and ease of The MPLIB Object Librarian manages the creation and
use. modification of library files of precompiled code. When
For easy source level debugging, the compilers provide a routine from a library is called from a source file, only
symbol information that is optimized to the MPLAB IDE the modules that contain that routine will be linked in
debugger. with the application. This allows large libraries to be
used efficiently in many different applications.
32.3 HI-TECH C for Various Device The object linker/library features include:
Families • Efficient linking of single libraries instead of many
The HI-TECH C Compiler code development systems smaller files
are complete ANSI C compilers for Microchip’s PIC • Enhanced code maintainability by grouping
family of microcontrollers and the dsPIC family of digital related modules together
signal controllers. These compilers provide powerful • Flexible creation of libraries with easy module
integration capabilities, omniscient code generation listing, replacement, deletion and extraction
and ease of use.
For easy source level debugging, the compilers provide 32.6 MPLAB Assembler, Linker and
symbol information that is optimized to the MPLAB IDE Librarian for Various Device
debugger. Families
The compilers include a macro assembler, linker, pre-
MPLAB Assembler produces relocatable machine
processor, and one-step driver, and can run on multiple
code from symbolic assembly language for PIC24,
platforms.
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
32.4 MPASM Assembler generates relocatable object files that can then be
The MPASM Assembler is a full-featured, universal archived or linked with other relocatable object files and
macro assembler for PIC10/12/16/18 MCUs. archives to create an executable file. Notable features
of the assembler include:
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX • Support for the entire device instruction set
files, MAP files to detail memory usage and symbol • Support for fixed-point and floating-point data
reference, absolute LST files that contain source lines • Command line interface
and generated machine code and COFF files for • Rich directive set
debugging.
• Flexible macro language
The MPASM Assembler features include: • MPLAB IDE compatibility
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process

PIC16(L)F1933
32.7 MPLAB SIM Software Simulator 32.9 MPLAB ICD 3 In-Circuit Debugger
The MPLAB SIM Software Simulator allows code
System
development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro-
ing the PIC MCUs and dsPIC® DSCs on an instruction chip's most cost effective high-speed hardware
level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig-
examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU)
a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon-
logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet easy-
buffer and logic analyzer display extend the power of to-use graphical user interface of MPLAB Integrated
the simulator to record and track program execution, Development Environment (IDE).
actions on I/O, most peripherals and internal registers.
The MPLAB ICD 3 In-Circuit Debugger probe is con-
The MPLAB SIM Software Simulator fully supports nected to the design engineer's PC using a high-speed
symbolic debugging using the MPLAB C Compilers, USB 2.0 interface and is connected to the target with a
and the MPASM and MPLAB Assemblers. The soft- connector compatible with the MPLAB ICD 2 or MPLAB
ware simulator offers the flexibility to develop and REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
debug code outside of the hardware laboratory envi- MPLAB ICD 2 headers.
ronment, making it an excellent, economical software
development tool. 32.10 PICkit 3 In-Circuit Debugger/
Programmer and
32.8 MPLAB REAL ICE In-Circuit
PICkit 3 Debug Express
Emulator System
The MPLAB PICkit 3 allows debugging and program-
MPLAB REAL ICE In-Circuit Emulator System is ming of PIC® and dsPIC® Flash microcontrollers at a
Microchip’s next generation high-speed emulator for most affordable price point using the powerful graphical
Microchip Flash DSC and MCU devices. It debugs and user interface of the MPLAB Integrated Development
programs PIC® Flash MCUs and dsPIC® Flash DSCs Environment (IDE). The MPLAB PICkit 3 is connected
with the easy-to-use, powerful graphical user interface of to the design engineer's PC using a full speed USB
the MPLAB Integrated Development Environment (IDE), interface and can be connected to the target via an
included with each kit. Microchip debug (RJ-11) connector (compatible with
The emulator is connected to the design engineer’s PC MPLAB ICD 3 and MPLAB REAL ICE). The connector
using a high-speed USB 2.0 interface and is connected uses two device I/O pins and the reset line to imple-
to the target with either a connector compatible with in- ment in-circuit debugging and In-Circuit Serial Pro-
circuit debugger systems (RJ11) or with the new high- gramming™.
speed, noise tolerant, Low-Voltage Differential Signal The PICkit 3 Debug Express include the PICkit 3, demo
(LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM
The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and
downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software.
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.

PIC16(L)F1933
32.11 PICkit 2 Development 32.13 Demonstration/Development
Programmer/Debugger and Boards, Evaluation Kits, and
PICkit 2 Debug Express Starter Kits
The PICkit™ 2 Development Programmer/Debugger is A wide variety of demonstration, development and
a low-cost development tool with an easy to use inter- evaluation boards for various PIC MCUs and dsPIC
face for programming and debugging Microchip’s Flash DSCs allows quick application development on fully func-
families of microcontrollers. The full featured tional systems. Most boards include prototyping areas for
Windows® programming interface supports baseline adding custom circuitry and provide application firmware
(PIC10F, PIC12F5xx, PIC16F5xx), midrange and source code for examination and modification.
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, The boards support a variety of features, including LEDs,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit temperature sensors, switches, speakers, RS-232
microcontrollers, and many Microchip Serial EEPROM interfaces, LCD displays, potentiometers and additional
products. With Microchip’s powerful MPLAB Integrated EEPROM memory.
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC® microcon- The demonstration and development boards can be
trollers. In-Circuit-Debugging runs, halts and single used in teaching environments, for prototyping custom
steps the program while the PIC microcontroller is circuits and for learning about various microcontroller
embedded in the application. When halted at a break- applications.
point, the file registers can be examined and modified. In addition to the PICDEM™ and dsPICDEM™ demon-
The PICkit 2 Debug Express include the PICkit 2, demo stration/development board series of circuits, Microchip
board and microcontroller, hookup cables and CDROM has a line of evaluation kits and demonstration software
with user’s guide, lessons, tutorial, compiler and for analog filter design, KEELOQ® security ICs, CAN,
MPLAB IDE software. IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
32.12 MPLAB PM3 Device Programmer
Also available are starter kits that contain everything
The MPLAB PM3 Device Programmer is a universal, needed to experience the specified device. This usually
CE compliant device programmer with programmable includes a single application and debug capability, all
voltage verification at VDDMIN and VDDMAX for on one board.
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu- Check the Microchip web page (www.microchip.com)
lar, detachable socket assembly to support various for the complete list of demonstration, development
package types. The ICSP™ cable assembly is included and evaluation kits.
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.

PIC16(L)F1933
33.0 PACKAGING INFORMATION
33.1 Package Marking Information
28-Lead SPDIP (.300”) Example
PIC16F1933
-E/SP e3
1210017
28-Lead SOIC (7.50 mm) Example
XXXXXXXXXXXXXXXXXXXX PIC16F1933
XXXXXXXXXXXXXXXXXXXX -E/SO e3
XXXXXXXXXXXXXXXXXXXX
1210017
YYWWNNN
28-Lead SSOP (5.30 mm) Example
PIC16F1933
-E/SS e3
1210017
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
* Standard PICmicro® device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.

PIC16(L)F1933
Package Marking Information (Continued)
28-Lead QFN (6x6 mm) Example
PIN 1 PIN 1
XXXXXXXX 16LF1933
XXXXXXXX -I/ML e3
YYWWNNN 1210017
28-Lead UQFN (4x4x0.5 mm) Example
PIN 1 PIN 1 PIC16

F1933
E/MV e3
210017
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
* Standard PICmicro® device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.

PIC16(L)F1933
33.2 Package Details
The following sections give the technical details of the packages.
/HDG6NLQQ\3ODVWLF'XDO,Q/LQH 63 ±PLO%RG\>63',3@
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
NOTE 1
E1
1 2 3
A A2
L c
A1 b1
b e eB
8QLWV ,1&+(6
'LPHQVLRQ/LPLWV 0,1 120 0$;
1XPEHURI3LQV 1
3LWFK H %6&
7RSWR6HDWLQJ3ODQH $ ± ±
0ROGHG3DFNDJH7KLFNQHVV $
%DVHWR6HDWLQJ3ODQH $ ± ±
6KRXOGHUWR6KRXOGHU:LGWK (
0ROGHG3DFNDJH:LGWK (
2YHUDOO/HQJWK '
7LSWR6HDWLQJ3ODQH /
/HDG7KLFNQHVV F
8SSHU/HDG:LGWK E
/RZHU/HDG:LGWK E
2YHUDOO5RZ6SDFLQJ H% ± ±
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
6LJQLILFDQW&KDUDFWHULVWLF
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGSHUVLGH
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

PIC16(L)F1933
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

PIC16(L)F1933

PIC16(L)F1933

PIC16(L)F1933
/HDG3ODVWLF6KULQN6PDOO2XWOLQH 66 ±PP%RG\>6623@
D
N
E
E1
1 2
b
NOTE 1
e
c
A A2
φ
A1
L1 L
8QLWV 0,//,0(7(56
1XPEHURI3LQV 1
3LWFK H %6&
2YHUDOO+HLJKW $ ± ±
0ROGHG3DFNDJH7KLFNQHVV $
6WDQGRII $ ± ±
2YHUDOO:LGWK (
0ROGHG3DFNDJH:LGWK (
2YHUDOO/HQJWK '
)RRW/HQJWK /
)RRWSULQW / 5()
/HDG7KLFNQHVV F ±
)RRW$QJOH
/HDG:LGWK E ±
1RWHV
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH
5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\

PIC16(L)F1933

PIC16(L)F1933
/HDG3ODVWLF4XDG)ODW1R/HDG3DFNDJH 0/ ±[PP%RG\>4)1@
ZLWKPP&RQWDFW/HQJWK
D D2
EXPOSED
PAD
E
b
E2
2 2
1 1 K
N N
NOTE 1 L
TOP VIEW BOTTOM VIEW
A3 A1
8QLWV 0,//,0(7(56
1XPEHURI3LQV 1
3LWFK H %6&
2YHUDOO+HLJKW $
6WDQGRII $
&RQWDFW7KLFNQHVV $ 5()
2YHUDOO:LGWK ( %6&
([SRVHG3DG:LGWK (
2YHUDOO/HQJWK ' %6&
([SRVHG3DG/HQJWK '
&RQWDFW:LGWK E
&RQWDFW/HQJWK /
&RQWDFWWR([SRVHG3DG . ± ±
1RWHV
3DFNDJHLVVDZVLQJXODWHG
5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\

PIC16(L)F1933
/HDG3ODVWLF4XDG)ODW1R/HDG3DFNDJH 0/ ±[PP%RG\>4)1@
ZLWKPP&RQWDFW/HQJWK

PIC16(L)F1933

PIC16(L)F1933

PIC16(L)F1933
APPENDIX A: DATA SHEET APPENDIX B: MIGRATING FROM
REVISION HISTORY OTHER PIC®
DEVICES
Revision A (05/2011)
This discusses some of the issues in migrating from
Initial release. other PIC® devices to the PIC16(L)F1933 family of
devices.
Revision B (06/2012)
B.1 PIC16F917 to PIC16(L)F1933
Update to Electrical Specifications.
TABLE B-1: FEATURE COMPARISON
Revision C (09/2012) Feature PIC16F917 PIC16F1933
Updated Note 1 in Register 23-1; Updated Table 26-1; Max. Operating Speed 20 MHz 32 MHz
Updated the Electrical Specifications section; Updated Max. Program 8K 8K
Figure 31-37; Other minor corrections. Memory (Words)
Max. SRAM (Bytes) 368 512
A/D Resolution 10-bit 10-bit
Timers (8/16-bit) 2/1 4/1
Oscillator Modes 4 8
Brown-out Reset Y Y
Internal Pull-ups RB<7:0> RB<7:0>
Interrupt-on-change RB<7:4> RB<7:0>
Comparator 2 2
AUSART/EUSART 1/0 0/1
Extended WDT Y Y
Software Control N Y
Option of WDT/BOR
INTOSC Frequencies 30 kHz - 500 kHz -
8 MHz 32 MHz
Clock Switching Y Y
Capacitive Sensing N Y
CCP/ECCP 2/0 2/3
Enhanced PIC16 CPU N Y
MSSP/SSP 0/1 1/0
LCD Y Y

PIC16(L)F1933
NOTES:

PIC16(L)F1933
INDEX
A EUSART Transmit .................................................... 275
External RC Mode ...................................................... 56
A/D
Specifications............................................................ 386 Fail-Safe Clock Monitor (FSCM)................................. 64
Absolute Maximum Ratings (PIC16F/LF1933) ................. 365 Generic I/O Port........................................................ 113
Interrupt Logic............................................................. 77
AC Characteristics
Industrial and Extended (PIC16F/LF1933) ............... 380 LCD Bias Voltage Generation .................................. 321
Load Conditions ........................................................ 379 LCD Clock Generation.............................................. 320
On-Chip Reset Circuit................................................. 69
ACKSTAT ......................................................................... 254
ACKSTAT Status Flag ...................................................... 254 PIC16F193X/LF193X ............................................. 8, 14
ADC .................................................................................. 137 PWM (Enhanced) ..................................................... 200
Resonator Operation .................................................. 54
Acquisition Requirements ......................................... 147
Associated registers.................................................. 149 Timer0 ...................................................................... 171
Block Diagram........................................................... 137 Timer1 ...................................................................... 175
Timer1 Gate.............................................. 180, 181, 182
Calculating Acquisition Time..................................... 147
Channel Selection..................................................... 138 Timer2/4/6 ................................................................ 187
Configuration............................................................. 138 Voltage Reference.................................................... 134
Voltage Reference Output Buffer Example .............. 154
Configuring Interrupt ................................................. 142
Conversion Clock...................................................... 138 BORCON Register.............................................................. 71
Conversion Procedure .............................................. 142 BRA .................................................................................. 356
Break Character (12-bit) Transmit and Receive ............... 296
Internal Sampling Switch (RSS) Impedance.............. 147
Interrupts................................................................... 140 Brown-out Reset (BOR)...................................................... 71
Operation .................................................................. 141 Specifications ........................................................... 384
Timing and Characteristics ....................................... 383
Operation During Sleep ............................................ 141
Port Configuration ..................................................... 138 C
Reference Voltage (VREF)......................................... 138
C Compilers
Source Impedance.................................................... 147
MPLAB C18.............................................................. 434
Special Event Trigger................................................ 141
CALL................................................................................. 357
Starting an A/D Conversion ...................................... 140
CALLW ............................................................................. 357
ADCON0 Register....................................................... 26, 143
Capacitive Sensing ........................................................... 305
ADCON1 Register....................................................... 26, 144
Associated registers w/ Capacitive Sensing............. 312
ADDFSR ........................................................................... 355
Specifications ........................................................... 395
ADDWFC .......................................................................... 355
Capture Module. See Enhanced Capture/Compare/PWM
ADRESH Register............................................................... 26
(ECCP)
ADRESH Register (ADFM = 0) ......................................... 145
Capture/Compare/PWM ................................................... 191
ADRESH Register (ADFM = 1) ......................................... 146
Capture/Compare/PWM (CCP)
ADRESL Register (ADFM = 0).......................................... 145
Associated Registers w/ Capture ............................. 193
ADRESL Register (ADFM = 1).......................................... 146
Associated Registers w/ Compare ........................... 195
Alternate Pin Function....................................................... 114
Associated Registers w/ PWM ......................... 199, 213
Analog-to-Digital Converter. See ADC
Capture Mode........................................................... 192
ANSELA Register ............................................................. 117
CCPx Pin Configuration............................................ 192
ANSELB Register ............................................................. 122
Compare Mode......................................................... 194
APFCON Register............................................................. 114
CCPx Pin Configuration.................................... 194
Assembler
Software Interrupt Mode ........................... 192, 194
MPASM Assembler................................................... 434
Special Event Trigger ....................................... 194
B Timer1 Mode Resource ............................ 192, 194
BAUDCON Register.......................................................... 287 Prescaler .................................................................. 192
PWM Mode
BF ............................................................................. 254, 256
BF Status Flag .......................................................... 254, 256 Duty Cycle ........................................................ 197
Block Diagram Effects of Reset ................................................ 199
Example PWM Frequencies and
Capacitive Sensing ........................................... 305, 306
Block Diagrams Resolutions, 20 MHZ ................................ 198
Example PWM Frequencies and
(CCP) Capture Mode Operation ............................... 192
ADC .......................................................................... 137 Resolutions, 32 MHZ ................................ 198
ADC Transfer Function ............................................. 148 Example PWM Frequencies and
Resolutions, 8 MHz .................................. 198
Analog Input Model ........................................... 148, 162
CCP PWM................................................................. 196 Operation in Sleep Mode.................................. 199
Clock Source............................................................... 52 Resolution ........................................................ 198
System Clock Frequency Changes .................. 199
Comparator ............................................................... 158
Compare ................................................................... 194 PWM Operation ........................................................ 196
Crystal Operation .................................................. 54, 55 PWM Overview......................................................... 196
PWM Period ............................................................. 197
Digital-to-Analog Converter (DAC)............................ 154
EUSART Receive ..................................................... 276 PWM Setup .............................................................. 197
CCP1CON Register...................................................... 30, 31

PIC16(L)F1933
CCPR1H Register ......................................................... 30, 31 Device Configuration .......................................................... 45
CCPR1L Register.......................................................... 30, 31 Code Protection .......................................................... 49
CCPTMRS0 Register ........................................................ 215 Configuration Word..................................................... 45
CCPTMRS1 Register ........................................................ 215 User ID ................................................................. 49, 50
CCPxAS Register.............................................................. 216 Device ID Register.............................................................. 50
CCPxCON (ECCPx) Register ........................................... 214 Device Overview............................................................. 7, 95
Clock Accuracy with Asynchronous Operation ................. 284 Digital-to-Analog Converter (DAC) ................................... 153
Clock Sources Effects of a Reset ..................................................... 154
External Modes ........................................................... 53 Specifications ........................................................... 388
EC ....................................................................... 53
HS ....................................................................... 53 E
LP........................................................................ 53 ECCP/CCP. See Enhanced Capture/Compare/PWM
OST..................................................................... 54 EEADR Registers ............................................................... 99
RC....................................................................... 55 EEADRH Registers............................................................. 99
XT ....................................................................... 53 EEADRL Register ............................................................. 110
Internal Modes ............................................................ 57 EEADRL Registers ............................................................. 99
HFINTOSC.......................................................... 57 EECON1 Register....................................................... 99, 111
Internal Oscillator Clock Switch Timing............... 59 EECON2 Register....................................................... 99, 112
LFINTOSC .......................................................... 58 EEDATH Register............................................................. 110
MFINTOSC ......................................................... 57 EEDATL Register ............................................................. 110
Clock Switching................................................................... 61 EEPROM Data Memory
CMOUT Register............................................................... 164 Avoiding Spurious Write ........................................... 100
CMxCON0 Register .......................................................... 163 Write Verify ............................................................... 109
CMxCON1 Register .......................................................... 164 Effects of Reset
Code Examples PWM mode ............................................................... 199
A/D Conversion ......................................................... 142 Electrical Specifications (PIC16F/LF1933) ....................... 365
Changing Between Capture Prescalers .................... 192 Enhanced Capture/Compare/PWM (ECCP)
Initializing PORTA ..................................................... 113 Enhanced PWM Mode.............................................. 200
Write Verify ............................................................... 109 Auto-Restart ..................................................... 209
Writing to Flash Program Memory ............................ 107 Auto-shutdown.................................................. 208
Comparator Direction Change in Full-Bridge Output Mode.. 206
Associated Registers ........................................ 165, 166 Full-Bridge Application...................................... 204
Operation .................................................................. 157 Full-Bridge Mode .............................................. 204
Comparator Module .......................................................... 157 Half-Bridge Application ..................................... 203
Cx Output State Versus Input Conditions ................. 159 Half-Bridge Application Examples .................... 210
Comparator Specifications ................................................ 388 Half-Bridge Mode.............................................. 203
Comparators Output Relationships (Active-High and
C2OUT as T1 Gate ................................................... 177 Active-Low)............................................... 201
Compare Module. See Enhanced Capture/Compare/ Output Relationships Diagram.......................... 202
PWM (ECCP) Programmable Dead Band Delay..................... 210
CONFIG1 Register.............................................................. 46 Shoot-through Current ...................................... 210
CONFIG2 Register.............................................................. 48 Start-up Considerations .................................... 212
Core Registers .................................................................... 25 Specifications ........................................................... 385
CPSCON0 Register .......................................................... 311 Enhanced Mid-range CPU.................................................. 13
CPSCON1 Register .......................................................... 312 Enhanced Universal Synchronous Asynchronous
Customer Change Notification Service ............................. 459 Receiver Transmitter (EUSART) .............................. 275
Customer Notification Service........................................... 459 Errata .................................................................................... 6
Customer Support ............................................................. 459 EUSART ........................................................................... 275
Associated Registers
D Baud Rate Generator ....................................... 289
DACCON0 (Digital-to-Analog Converter Control 0) Asynchronous Mode ................................................. 277
Register..................................................................... 156 12-bit Break Transmit and Receive .................. 296
DACCON1 (Digital-to-Analog Converter Control 1) Associated Registers
Register..................................................................... 156 Receive .................................................... 283
Data EEPROM Memory ...................................................... 99 Transmit.................................................... 279
Associated Registers ................................................ 112 Auto-Wake-up on Break ................................... 294
Code Protection ........................................................ 100 Baud Rate Generator (BRG) ............................ 288
Reading..................................................................... 100 Clock Accuracy................................................. 284
Writing ....................................................................... 100 Receiver ........................................................... 280
Data Memory................................................................. 17, 20 Setting up 9-bit Mode with Address Detect ...... 282
DC and AC Characteristics ............................................... 397 Transmitter ....................................................... 277
Graphs and Tables ................................................... 397 Baud Rate Generator (BRG)
DC Characteristics Auto Baud Rate Detect..................................... 293
Extended and Industrial (PIC16F/LF1933) ............... 375 Baud Rate Error, Calculating............................ 288
Industrial and Extended (PIC16F/LF1933) ............... 368 Baud Rates, Asynchronous Modes .................. 290
Development Support ....................................................... 433 Formulas........................................................... 289

PIC16(L)F1933
High Baud Rate Select (BRGH Bit) .................. 288 LSRF ........................................................................ 359
Synchronous Master Mode ............................... 297, 302 MOVF ....................................................................... 359
Associated Registers MOVIW ..................................................................... 360
Receive..................................................... 301 MOVLB ..................................................................... 360
Transmit.................................................... 299 MOVWI ..................................................................... 361
Reception.......................................................... 300 OPTION.................................................................... 361
Transmission .................................................... 297 RESET...................................................................... 361
Synchronous Slave Mode SUBWFB .................................................................. 363
Associated Registers TRIS ......................................................................... 364
Receive..................................................... 303 BCF .......................................................................... 356
Transmit.................................................... 302 BSF........................................................................... 356
Reception.......................................................... 303 BTFSC...................................................................... 356
Transmission .................................................... 302 BTFSS ...................................................................... 356
Extended Instruction Set CALL......................................................................... 357
ADDFSR ................................................................... 355 CLRF ........................................................................ 357
CLRW ....................................................................... 357
F CLRWDT .................................................................. 357
Fail-Safe Clock Monitor....................................................... 64 COMF ....................................................................... 357
Fail-Safe Condition Clearing ....................................... 64 DECF........................................................................ 357
Fail-Safe Detection ..................................................... 64 DECFSZ ................................................................... 358
Fail-Safe Operation..................................................... 64 GOTO ....................................................................... 358
Reset or Wake-up from Sleep..................................... 64 INCF ......................................................................... 358
Firmware Instructions........................................................ 351 INCFSZ..................................................................... 358
Fixed Voltage Reference (FVR) IORLW ...................................................................... 358
Associated Registers ................................................ 135 IORWF...................................................................... 358
Flash Program Memory ...................................................... 99 MOVLW .................................................................... 360
Erasing...................................................................... 104 MOVWF.................................................................... 360
Modifying................................................................... 108 NOP.......................................................................... 361
Writing....................................................................... 104 RETFIE..................................................................... 362
FSR Register25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 RETLW ..................................................................... 362
FVRCON (Fixed Voltage Reference Control) Register ..... 135 RETURN................................................................... 362
RLF........................................................................... 362
I RRF .......................................................................... 363
I2C Mode (MSSP) SLEEP ...................................................................... 363
Acknowledge Sequence Timing................................ 258 SUBLW..................................................................... 363
Bus Collision SUBWF..................................................................... 363
During a Repeated Start Condition ................... 263 SWAPF..................................................................... 364
During a Stop Condition.................................... 264 XORLW .................................................................... 364
Effects of a Reset...................................................... 259 XORWF .................................................................... 364
I2C Clock Rate w/BRG.............................................. 267 INTCON Register................................................................ 82
Master Mode Internal Oscillator Block
Operation .......................................................... 250 INTOSC
Reception.......................................................... 256 Specifications ................................................... 381
Start Condition Timing .............................. 252, 253 Internal Sampling Switch (RSS) Impedance ..................... 147
Transmission .................................................... 254 Internet Address ............................................................... 459
Multi-Master Communication, Bus Collision and Interrupt-On-Change......................................................... 129
Arbitration ......................................................... 259 Associated Registers................................................ 132
Multi-Master Mode .................................................... 259 Interrupts ............................................................................ 77
Read/Write Bit Information (R/W Bit) ........................ 235 ADC .......................................................................... 142
Slave Mode Associated registers w/ Interrupts .............................. 89
Transmission .................................................... 240 Configuration Word w/ Clock Sources........................ 68
Sleep Operation ........................................................ 259 Configuration Word w/ LDO........................................ 91
Stop Condition Timing............................................... 258 TMR1........................................................................ 179
INDF Register25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 INTOSC Specifications ..................................................... 381
Indirect Addressing ............................................................. 41 IOCBF Register ................................................................ 131
Instruction Format ............................................................. 352 IOCBN Register ................................................................ 131
Instruction Set ................................................................... 351 IOCBP Register ................................................................ 131
ADDLW ..................................................................... 355
ADDWF..................................................................... 355 L
ADDWFC .................................................................. 355 LATA Register .......................................................... 116, 125
ANDLW ..................................................................... 355 LATB Register .................................................................. 121
ANDWF..................................................................... 355 LCD
BRA........................................................................... 356 Associated Registers................................................ 346
CALL ......................................................................... 357 Bias Voltage Generation................................... 321, 322
CALLW...................................................................... 357 Clock Source Selection ............................................ 320
LSLF ......................................................................... 359 Configuring the Module ............................................ 345

PIC16(L)F1933
Disabling the Module ................................................ 345 Oscillator Switching
Frame Frequency...................................................... 328 Fail-Safe Clock Monitor .............................................. 64
Interrupts ................................................................... 341 Two-Speed Clock Start-up.......................................... 62
LCDCON Register .................................................... 314 OSCSTAT Register ............................................................ 67
LCDPS Register........................................................ 314 OSCTUNE Register............................................................ 68
Multiplex Types ......................................................... 328
Operation During Sleep ............................................ 343 P
Pixel Control.............................................................. 328 P1A/P1B/P1C/P1D.See Enhanced Capture/Compare/
Prescaler ................................................................... 320 PWM (ECCP)............................................................ 200
Segment Enables...................................................... 328 Packaging ......................................................................... 437
Waveform Generation ............................................... 330 Marking ............................................................. 437, 438
LCDCON Register..................................................... 314, 315 PDIP Details ............................................................. 439
LCDCST Register ............................................................. 318 PCL and PCLATH............................................................... 14
LCDDATAx Registers ............................................... 319, 326 PCL Register25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37
LCDPS Register........................................................ 314, 316 PCLATH Register25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
LP Bits....................................................................... 320 37
LCDREF Register ............................................................. 317 PCON Register ............................................................. 26, 75
LCDRL Register ................................................................ 326 PIE1 Register................................................................ 26, 83
LCDSEn Registers ............................................................ 319 PIE2 Register................................................................ 26, 84
Liquid Crystal Display (LCD) Driver .................................. 313 PIE3 Register...................................................................... 85
Load Conditions ................................................................ 379 Pin Diagram
LSLF.................................................................................. 359 PIC16F1933, PIC16LF1933, 28-pin QFN..................... 3
LSRF ................................................................................. 359 PIC16F1933, PICLF1933, 28-pin PDIP/SOIC/SSOP ... 3
Pinout Descriptions
M PIC16F193X/PIC16LF193X.......................................... 9
Master Synchronous Serial Port. See MSSP PIR1 Register ............................................................... 25, 86
MCLR .................................................................................. 72 PIR2 Register ............................................................... 25, 87
Internal ........................................................................ 72 PIR3 Register ..................................................................... 88
Memory Organization PORTA ............................................................................. 115
Data ...................................................................... 17, 20 Associated Registers ................................................ 118
Program ...................................................................... 15 Configuration Word w/ PORTA................................. 118
Microchip Internet Web Site .............................................. 459 PORTA Register ................................................... 25, 27
Migrating from other PIC Microcontroller Devices............. 449 Specifications ........................................................... 382
MOVIW.............................................................................. 360 PORTA Register ............................................................... 116
MOVLB.............................................................................. 360 PORTB ............................................................................. 119
MOVWI.............................................................................. 361 Additional Pin Functions
MPLAB ASM30 Assembler, Linker, Librarian ................... 434 Weak Pull-up .................................................... 120
MPLAB Integrated Development Environment Software .. 433 Associated Registers ................................................ 123
MPLAB PM3 Device Programmer..................................... 436 Interrupt-on-Change ................................................. 119
MPLAB REAL ICE In-Circuit Emulator System................. 435 P1B/P1C/P1D.See Enhanced Capture/Compare/
MPLINK Object Linker/MPLIB Object Librarian ................ 434 PWM+ (ECCP+) ............................................... 119
MSSP ................................................................................ 219 Pin Descriptions and Diagrams ................................ 120
SPI Mode .................................................................. 222 PORTB Register ................................................... 25, 27
SSPBUF Register ..................................................... 225 PORTB Register ............................................................... 121
SSPSR Register ....................................................... 225 PORTC ............................................................................. 124
Associated Registers ................................................ 126
O P1A.See Enhanced Capture/Compare/PWM+
OPCODE Field Descriptions ............................................. 351 (ECCP+) ........................................................... 124
OPTION ............................................................................ 361 Pin Descriptions and Diagrams ................................ 124
OPTION Register .............................................................. 173 PORTC Register................................................... 25, 27
OSCCON Register .............................................................. 66 Specifications ........................................................... 382
Oscillator PORTC Register............................................................... 125
Associated Registers .................................................. 68 PORTE ............................................................................. 127
Oscillator Module ................................................................ 51 Associated Registers ................................................ 128
ECH ............................................................................ 51 Pin Descriptions and Diagrams ................................ 127
ECL ............................................................................. 51 PORTE Register ......................................................... 25
ECM ............................................................................ 51 PORTE Register ............................................................... 127
HS ............................................................................... 51 Power-Down Mode (Sleep)................................................. 93
INTOSC ...................................................................... 51 Associated Registers .................................................. 94
LP................................................................................ 51 Power-on Reset .................................................................. 70
RC ............................................................................... 51 Power-up Timer (PWRT) .................................................... 70
XT ............................................................................... 51 Specifications ........................................................... 384
Oscillator Parameters........................................................ 381 PR2 Register ................................................................ 25, 33
Oscillator Specifications .................................................... 380 Precision Internal Oscillator Parameters .......................... 381
Oscillator Start-up Timer (OST)
Specifications ............................................................ 384

PIC16(L)F1933
Program Memory ................................................................ 15 LCDDATAx (LCD Data) .................................... 319, 326
Map and Stack (PIC16F1933/LF1933, LCDPS (LCD Phase)................................................ 316
PIC16F1934/LF1934) ................................... 15, 20 LCDREF (LCD Reference Voltage Control) ............. 317
Map and Stack (PIC16F1936/LF1936, LCDRL (LCD Reference Voltage Control)................ 326
PIC16F1937/LF1937) ................................... 16, 20 LCDSEn (LCD Segment Enable) ............................. 319
Map and Stack (PIC16F1938/LF1938, OPTION_REG (OPTION)......................................... 173
PIC16F1939/LF1939) ......................................... 20 OSCCON (Oscillator Control)..................................... 66
Programming Mode Exit ..................................................... 72 OSCSTAT (Oscillator Status) ..................................... 67
Programming, Device Instructions .................................... 351 OSCTUNE (Oscillator Tuning).................................... 68
PSTRxCON Register ........................................................ 218 PCON (Power Control Register)................................. 75
PWM (ECCP Module) PCON (Power Control) ............................................... 75
PWM Steering........................................................... 211 PIE1 (Peripheral Interrupt Enable 1) .......................... 83
Steering Synchronization .......................................... 212 PIE2 (Peripheral Interrupt Enable 2) .......................... 84
PWM Mode. See Enhanced Capture/Compare/PWM ...... 200 PIE3 (Peripheral Interrupt Enable 3) .......................... 85
PWM Steering ................................................................... 211 PIR1 (Peripheral Interrupt Register 1) ........................ 86
PWMxCON Register ......................................................... 217 PIR2 (Peripheral Interrupt Request 2) ........................ 87
PIR3 (Peripheral Interrupt Request 3) ........................ 88
R PORTA ..................................................................... 116
RCREG ............................................................................. 282 PORTB ..................................................................... 121
RCREG Register................................................................. 28 PORTC ..................................................................... 125
RCSTA Register ......................................................... 28, 286 PORTE ..................................................................... 127
Reader Response ............................................................. 460 PSTRxCON (PWM Steering Control) ....................... 218
Read-Modify-Write Operations ......................................... 351 PWMxCON (Enhanced PWM Control) ..................... 217
Register RCSTA (Receive Status and Control) ...................... 286
RCREG Register....................................................... 293 Special Function, Summary........................................ 25
Registers SRCON0 (SR Latch Control 0)................................. 169
ADCON0 (ADC Control 0) ........................................ 143 SRCON1 (SR Latch Control 1)................................. 169
ADCON1 (ADC Control 1) ........................................ 144 SSPADD (MSSP Address and Baud Rate,
ADRESH (ADC Result High) with ADFM = 0)........... 145 I2C Mode) ......................................................... 273
ADRESH (ADC Result High) with ADFM = 1)........... 146 SSPCON1 (MSSP Control 1) ................................... 269
ADRESL (ADC Result Low) with ADFM = 0) ............ 145 SSPCON2 (SSP Control 2) ...................................... 271
ADRESL (ADC Result Low) with ADFM = 1) ............ 146 SSPCON3 (SSP Control 3) ...................................... 272
ANSELA (PORTA Analog Select)............................. 117 SSPMSK (SSP Mask) .............................................. 273
ANSELB (PORTB Analog Select)............................. 122 SSPSTAT (SSP Status) ........................................... 268
APFCON (Alternate Pin Function Control)................ 114 STATUS ..................................................................... 18
BAUDCON (Baud Rate Control) ............................... 287 T1CON (Timer1 Control) .......................................... 183
BORCON Brown-out Reset Control)........................... 71 T1GCON (Timer1 Gate Control)............................... 184
CCPTMRS0 (PWM Timer Selection Control 0) ........ 215 TRISA (Tri-State PORTA) ........................................ 116
CCPTMRS1 (PWM Timer Selection Control 1) ........ 215 TRISB (Tri-State PORTB) ........................................ 121
CCPxAS (CCPx Auto-Shutdown Control)................. 216 TRISC (Tri-State PORTC) ........................................ 125
CCPxCON (ECCPx Control)..................................... 214 TRISE (Tri-State PORTE) ........................................ 127
CMOUT (Comparator Output)................................... 164 TXCON ..................................................................... 189
CMxCON0 (Cx Control) ............................................ 163 TXSTA (Transmit Status and Control)...................... 285
CMxCON1 (Cx Control 1) ......................................... 164 WDTCON (Watchdog Timer Control) ......................... 97
Configuration Word 1 .................................................. 46 WPUB (Weak Pull-up PORTB)................................. 122
Configuration Word 2 .................................................. 48 RESET.............................................................................. 361
CPSCON0 (Capacitive Sensing Control Register 0) 311 Reset .................................................................................. 69
CPSCON1 (Capacitive Sensing Control Register 1) 312 Reset Instruction................................................................. 72
DACCON0 ................................................................ 156 Resets ................................................................................ 69
DACCON1 ................................................................ 156 Associated Registers.................................................. 76
Device ID .................................................................... 50 Revision History................................................................ 449
EEADRL (EEPROM Address) .................................. 110
EECON1 (EEPROM Control 1)................................. 111 S
EECON2 (EEPROM Control 2)................................. 112 Shoot-through Current ...................................................... 210
EEDATH (EEPROM Data)........................................ 110 Software Simulator (MPLAB SIM) .................................... 435
EEDATL (EEPROM Data) ........................................ 110 SPBRG Register........................................................... 27, 28
FVRCON................................................................... 135 SPBRGH .......................................................................... 288
INTCON (Interrupt Control)......................................... 82 SPBRGL ........................................................................... 288
IOCBF (Interrupt-on-Change Flag) ........................... 131 Special Event Trigger ....................................................... 141
IOCBN (Interrupt-on-Change Negative Edge) .......... 131 Special Function Registers (SFRs)..................................... 25
IOCBP (Interrupt-on-Change Positive Edge) ............ 131 SPI Mode (MSSP)
LATA (Data Latch PORTA)....................................... 116 Associated Registers................................................ 229
LATB (Data Latch PORTB)....................................... 121 SPI Clock.................................................................. 225
LATC (Data Latch PORTC) ...................................... 125 SR Latch ........................................................................... 167
LCDCON (LCD Control)............................................ 315 Associated registers w/ SR Latch............................. 170
LCDCST (LCD Contrast Control).............................. 318 SRCON0 Register ............................................................ 169

PIC16(L)F1933
SRCON1 Register............................................................. 169 Baud Rate Generator with Clock Arbitration............. 251
SSPADD Register ....................................................... 29, 273 BRG Reset Due to SDA Arbitration During Start
SSPBUF Register ............................................................... 29 Condition .......................................................... 262
SSPCON Register............................................................... 29 Brown-out Reset (BOR)............................................ 383
SSPCON1 Register........................................................... 269 Brown-out Reset Situations ........................................ 71
SSPCON2 Register........................................................... 271 Bus Collision During a Repeated Start Condition
SSPCON3 Register........................................................... 272 (Case 1)............................................................ 263
SSPMSK Register............................................................. 273 Bus Collision During a Repeated Start Condition
SSPOV.............................................................................. 256 (Case 2)............................................................ 264
SSPOV Status Flag........................................................... 256 Bus Collision During a Start Condition (SCL = 0) ..... 261
SSPSTAT Register ..................................................... 29, 268 Bus Collision During a Stop Condition (Case 1) ....... 264
R/W Bit ...................................................................... 235 Bus Collision During a Stop Condition (Case 2) ....... 265
Stack ................................................................................... 39 Bus Collision During Start Condition (SDA only) ...... 261
Accessing.................................................................... 39 Bus Collision for Transmit and Acknowledge ........... 260
Reset........................................................................... 41 CLKOUT and I/O ...................................................... 382
Stack Overflow/Underflow................................................... 72 Clock Synchronization .............................................. 248
STATUS Register................................................................ 18 Clock Timing ............................................................. 380
SUBWFB........................................................................... 363 Comparator Output ................................................... 157
Enhanced Capture/Compare/PWM (ECCP)............. 385
T Fail-Safe Clock Monitor (FSCM)................................. 65
T1CON Register.......................................................... 25, 183 First Start Bit Timing ................................................. 252
T1GCON Register............................................................. 184 Full-Bridge PWM Output........................................... 205
T2CON Register............................................................ 25, 33 Half-Bridge PWM Output .................................. 203, 210
Temperature Indicator I2C Bus Data............................................................. 393
Associated Registers ................................................ 152 I2C Bus Start/Stop Bits ............................................. 392
Temperature Indicator Module .......................................... 151 I2C Master Mode (7-Bit Reception)................... 255, 257
Thermal Considerations (PIC16F/LF1933) ....................... 378 I2C Stop Condition Receive or Transmit Mode......... 259
Timer0 ............................................................................... 171 INT Pin Interrupt ......................................................... 80
Associated Registers ................................................ 173 Internal Oscillator Switch Timing ................................ 60
Operation .................................................................. 171 LCD Interrupt Timing in Quarter-Duty Cycle Drive ... 342
Specifications ............................................................ 385 LCD Sleep Entry/Exit when SLPEN = 1 or CS = 00 . 344
Timer1 ............................................................................... 175 PWM Auto-shutdown ................................................ 209
Associated registers.................................................. 185 Firmware Restart .............................................. 208
Asynchronous Counter Mode ................................... 177 PWM Direction Change ............................................ 206
Reading and Writing ......................................... 177 PWM Direction Change at Near 100% Duty Cycle... 207
Clock Source Selection ............................................. 176 PWM Output (Active-High) ....................................... 201
Interrupt..................................................................... 179 PWM Output (Active-Low) ........................................ 202
Operation .................................................................. 176 Repeat Start Condition ............................................. 253
Operation During Sleep ............................................ 179 Reset Start-up Sequence ........................................... 73
Oscillator ................................................................... 177 Reset, WDT, OST and Power-up Timer ................... 383
Prescaler ................................................................... 177 Send Break Character Sequence ............................. 296
Specifications ............................................................ 385 SPI Master Mode (CKE = 1, SMP = 1) ..................... 390
Timer1 Gate SPI Mode (Master Mode).......................................... 225
Selecting Source............................................... 177 SPI Slave Mode (CKE = 0) ....................................... 391
TMR1H Register ....................................................... 175 SPI Slave Mode (CKE = 1) ....................................... 391
TMR1L Register ........................................................ 175 Synchronous Reception (Master Mode, SREN) ....... 301
Timer2 Synchronous Transmission ...................................... 298
Associated registers.................................................. 190 Synchronous Transmission (Through TXEN) ........... 298
Timer2/4/6 ......................................................................... 187 Timer0 and Timer1 External Clock ........................... 384
Associated registers.................................................. 190 Timer1 Incrementing Edge ....................................... 179
Timers Two Speed Start-up.................................................... 63
Timer1 Type-A in 1/2 MUX, 1/2 Bias Drive ........................... 331
T1CON.............................................................. 183 Type-A in 1/2 MUX, 1/3 Bias Drive ........................... 333
T1GCON ........................................................... 184 Type-A in 1/3 MUX, 1/2 Bias Drive ........................... 335
Timer2/4/6 Type-A in 1/3 MUX, 1/3 Bias Drive ........................... 337
TXCON ............................................................. 189 Type-A in 1/4 MUX, 1/3 Bias Drive ........................... 339
Timing Diagrams Type-A/Type-B in Static Drive .................................. 330
A/D Conversion ......................................................... 387 Type-B in 1/2 MUX, 1/2 Bias Drive ........................... 332
A/D Conversion (Sleep Mode) .................................. 387 Type-B in 1/2 MUX, 1/3 Bias Drive ........................... 334
Acknowledge Sequence ........................................... 258 Type-B in 1/3 MUX, 1/2 Bias Drive ........................... 336
Asynchronous Reception .......................................... 282 Type-B in 1/3 MUX, 1/3 Bias Drive ........................... 338
Asynchronous Transmission ..................................... 278 Type-B in 1/4 MUX, 1/3 Bias Drive ........................... 340
Asynchronous Transmission (Back to Back) ............ 279 USART Synchronous Receive (Master/Slave) ......... 389
Auto Wake-up Bit (WUE) During Normal Operation . 295 USART Synchronous Transmission (Master/Slave). 388
Auto Wake-up Bit (WUE) During Sleep .................... 295 Wake-up from Interrupt............................................... 94
Automatic Baud Rate Calibration .............................. 293

PIC16(L)F1933
Timing Diagrams and Specifications
PLL Clock.................................................................. 381
Timing Parameter Symbology........................................... 379
Timing Requirements
I2C Bus Data ............................................................. 394
I2C Bus Start/Stop Bits ............................................. 393
SPI Mode .................................................................. 392
TMR0 Register .................................................................... 25
TMR1H Register ................................................................. 25
TMR1L Register .................................................................. 25
TMR2 Register .............................................................. 25, 33
TRIS .................................................................................. 364
TRISA Register ........................................................... 26, 116
TRISB ............................................................................... 119
TRISB Register ........................................................... 26, 121
TRISC ............................................................................... 124
TRISC Register ........................................................... 26, 125
TRISE ............................................................................... 127
TRISE Register ........................................................... 26, 127
Two-Speed Clock Start-up Mode ........................................ 62
TXCON (Timer2/4/6) Register .......................................... 189
TXREG.............................................................................. 277
TXREG Register ................................................................. 28
TXSTA Register .......................................................... 28, 285
BRGH Bit .................................................................. 288
U
USART
Synchronous Master Mode
Requirements, Synchronous Receive .............. 389
Requirements, Synchronous Transmission ...... 389
Timing Diagram, Synchronous Receive ........... 389
Timing Diagram, Synchronous Transmission ... 388
V
VREF. SEE ADC Reference Voltage
W
Wake-up on Break ............................................................ 294
Wake-up Using Interrupts ................................................... 94
Watchdog Timer (WDT) ...................................................... 72
Associated Registers .................................................. 98
Configuration Word w/ Watchdog Timer ..................... 98
Modes ......................................................................... 96
Specifications............................................................ 384
WCOL ....................................................... 251, 254, 256, 258
WCOL Status Flag .................................... 251, 254, 256, 258
WDTCON Register ............................................................. 97
WPUB Register ................................................................. 122
Write Protection .................................................................. 49
WWW Address.................................................................. 459
WWW, On-Line Support ........................................... 2, 6, 461

PIC16(L)F1933
NOTES:

PIC16(L)F1933
THE MICROCHIP WEB SITE CUSTOMER SUPPORT
Microchip provides online support via our WWW site at Users of Microchip products can receive assistance
www.microchip.com. This web site is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
customers. Accessible by using your favorite Internet
• Local Sales Office
browser, the web site contains the following
information: • Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design • Development Systems Information Line
resources, user’s guides and hardware support Customers should contact their distributor,
documents, latest software releases and archived representative or field application engineer (FAE) for
software support. Local sales offices are also available to help
• General Technical Support – Frequently Asked customers. A listing of sales offices and locations is
Questions (FAQ), technical support requests, included in the back of this document.
online discussion groups, Microchip consultant Technical support is available through the web site
program member listing at: http://microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.

PIC16(L)F1933
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO: Technical Publications Manager Total Pages Sent ________

RE: Reader Response
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________ FAX: (______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: PIC16(L)F1933 Literature Number: DS41575C
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?

PIC16(L)F1933
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. [X](1) - X /XX XXX Examples:
Device Tape and Reel Temperature Package Pattern a) PIC16LF1933 - I/P = Industrial temp., Plastic
DIP package
Option Range b) PIC16F1933 - E/ML = Extended temp., QFN
package
Device: PIC16F1933, PIC16LF1933
Tape and Reel Blank = Standard packaging (tube or tray)

Option: T = Tape and Reel(1)
Temperature I = -40C to +85C

Range: E = -40C to +125C
Package:(2) ML = Micro Lead Frame (QFN)

MV = Micro Lead Frame (UQFN)
SO = SOIC Note 1: Tape and Reel identifier only appears in the
SP = Skinny Plastic DIP catalog part number description. This
SS = SSOP identifier is used for ordering purposes and is
not printed on the device package. Check
with your Microchip Sales Office for package
Pattern: 3-Digit Pattern Code for QTP (blank otherwise) availability with the Tape and Reel option.
2: Small-form factor packaging options may be
available. Please check
http://www.microchip.com/packaging for
small-form factor package availability, or
contact your local Sales Office.

PIC16(L)F1933
NOTES:

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
ensure that your application meets with your specifications.
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
Incorporated in the U.S.A. and other countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions
QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology
FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of
devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries.
the buyer’s risk, and the buyer agrees to defend, indemnify and
Analog-for-the-Digital Age, Application Maestro, BodyCom,
hold harmless Microchip from any and all damages, claims,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
suits, or expenses resulting from such use. No licenses are
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
conveyed, implicitly or otherwise, under any Microchip
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
intellectual property rights.
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2011-2012, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620765746
QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
== ISO/TS 16949 == devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

Worldwide Sales and Service
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
Corporate Office Asia Pacific Office India - Bangalore Austria - Wels
2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-3090-4444 Tel: 43-7242-2244-39
Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-3090-4123 Fax: 43-7242-2244-393
Tel: 480-792-7200 Harbour City, Kowloon Denmark - Copenhagen
India - New Delhi
Fax: 480-792-7277 Hong Kong Tel: 45-4450-2828
Tel: 91-11-4160-8631
Technical Support: Tel: 852-2401-1200 Fax: 45-4485-2829
Fax: 91-11-4160-8632
http://www.microchip.com/ Fax: 852-2401-3431
India - Pune France - Paris
support
Australia - Sydney Tel: 91-20-2566-1512 Tel: 33-1-69-53-63-20
Web Address:
Tel: 61-2-9868-6733 Fax: 91-20-2566-1513 Fax: 33-1-69-30-90-79
www.microchip.com
Fax: 61-2-9868-6755 Germany - Munich
Atlanta Japan - Osaka
China - Beijing Tel: 49-89-627-144-0
Duluth, GA Tel: 81-66-152-7160
Tel: 86-10-8569-7000 Fax: 49-89-627-144-44
Tel: 678-957-9614 Fax: 81-66-152-9310
Fax: 86-10-8528-2104 Italy - Milan
Fax: 678-957-1455 Japan - Yokohama
China - Chengdu Tel: 39-0331-742611
Boston Tel: 81-45-471- 6166
Tel: 86-28-8665-5511 Fax: 39-0331-466781
Westborough, MA Fax: 81-45-471-6122
Fax: 86-28-8665-7889 Netherlands - Drunen
Tel: 774-760-0087 Korea - Daegu
Fax: 774-760-0088 China - Chongqing Tel: 82-53-744-4301 Tel: 31-416-690399
Tel: 86-23-8980-9588 Fax: 82-53-744-4302 Fax: 31-416-690340
Chicago
Itasca, IL Fax: 86-23-8980-9500 Spain - Madrid
Korea - Seoul
Tel: 630-285-0071 China - Hangzhou Tel: 34-91-708-08-90
Tel: 82-2-554-7200
Fax: 630-285-0075 Tel: 86-571-2819-3187 Fax: 82-2-558-5932 or Fax: 34-91-708-08-91
Cleveland Fax: 86-571-2819-3189 82-2-558-5934 UK - Wokingham
Independence, OH China - Hong Kong SAR Tel: 44-118-921-5869
Malaysia - Kuala Lumpur
Tel: 216-447-0464 Tel: 852-2401-1200 Fax: 44-118-921-5820
Tel: 60-3-6201-9857
Fax: 216-447-0643 Fax: 852-2401-3431 Fax: 60-3-6201-9859
Dallas China - Nanjing Malaysia - Penang
Addison, TX Tel: 86-25-8473-2460 Tel: 60-4-227-8870
Tel: 972-818-7423 Fax: 86-25-8473-2470 Fax: 60-4-227-4068
Fax: 972-818-2924
China - Qingdao Philippines - Manila
Detroit Tel: 86-532-8502-7355 Tel: 63-2-634-9065
Farmington Hills, MI
Fax: 86-532-8502-7205 Fax: 63-2-634-9069
Tel: 248-538-2250
Fax: 248-538-2260 China - Shanghai Singapore
Tel: 86-21-5407-5533 Tel: 65-6334-8870
Indianapolis Fax: 86-21-5407-5066 Fax: 65-6334-8850
Noblesville, IN
Tel: 317-773-8323 China - Shenyang Taiwan - Hsin Chu
Fax: 317-773-5453 Tel: 86-24-2334-2829 Tel: 886-3-5778-366
Fax: 86-24-2334-2393 Fax: 886-3-5770-955
Los Angeles
Mission Viejo, CA China - Shenzhen Taiwan - Kaohsiung
Tel: 949-462-9523 Tel: 86-755-8203-2660 Tel: 886-7-536-4818
Fax: 949-462-9608 Fax: 86-755-8203-1760 Fax: 886-7-330-9305
Santa Clara China - Wuhan Taiwan - Taipei
Santa Clara, CA Tel: 86-27-5980-5300 Tel: 886-2-2500-6610
Tel: 408-961-6444 Fax: 86-27-5980-5118 Fax: 886-2-2508-0102
Fax: 408-961-6445 China - Xian Thailand - Bangkok
Toronto Tel: 86-29-8833-7252 Tel: 66-2-694-1351
Mississauga, Ontario, Fax: 86-29-8833-7256 Fax: 66-2-694-1350
Canada China - Xiamen
Tel: 905-673-0699 Tel: 86-592-2388138
Fax: 905-673-6509 Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
11/29/11
Fax: 86-756-3210049

Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Microchip:
PIC16F1933-E/MV PIC16F1933-I/MV PIC16F1933T-I/MV PIC16LF1933-E/MV PIC16LF1933-I/MV PIC16LF1933T-
I/MV PIC16F1933-E/ML PIC16F1933-E/SO PIC16F1933-E/SP PIC16F1933-E/SS PIC16F1933-I/ML PIC16F1933-
I/SO PIC16F1933-I/SP PIC16F1933-I/SS PIC16F1933T-I/ML PIC16F1933T-I/SO PIC16F1933T-I/SS PIC16LF1933-
E/ML PIC16LF1933-E/SO PIC16LF1933-E/SP PIC16LF1933-E/SS PIC16LF1933-I/ML PIC16LF1933-I/SO
PIC16LF1933-I/SP PIC16LF1933-I/SS PIC16LF1933T-I/ML PIC16LF1933T-I/SO PIC16LF1933T-I/SS

PIC16 (L) F1933 Datasheet

Uploaded by

Copyright:

Available Formats

PIC16 (L) F1933 Datasheet

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

PIC16 (L) F1933 Datasheet

Uploaded by

Copyright:

Available Formats

PIC16(L)F1933

28-Pin Flash-Based, 8-Bit CMOS Microcontrollers with

 2011-2012 Microchip Technology Inc. DS41575C-page 1

PIC16(L)F1933 (1) 4096 256 256 25 11 8 2 4/1 1 1 3 2 4/16/60(3) I/H Y

DS41575C-page 2  2011-2012 Microchip Technology Inc.

28-pin SPDIP, SOIC, SSOP

Pin Diagram – 28-Pin QFN/UQFN (PIC16F1933, PIC16LF1933)

 2011-2012 Microchip Technology Inc. DS41575C-page 3

RA0 2 27 Y AN0 — C12IN0-/ — — — SEG12 — — VCAP(2)

DS41575C-page 4  2011-2012 Microchip Technology Inc.

 2011-2012 Microchip Technology Inc. DS41575C-page 5

TO OUR VALUED CUSTOMERS

Most Current Data Sheet

Customer Notification System

DS41575C-page 6  2011-2012 Microchip Technology Inc.

TABLE 1-1: DEVICE PERIPHERAL

 2011-2012 Microchip Technology Inc. DS41575C-page 7

OSC1/CLKIN CPU PORTB

LCD ECCP1 ECCP2 ECCP3 CCP4 CCP5 MSSP EUSART

Note 1: See applicable chapters for more information on peripherals.

DS41575C-page 8  2011-2012 Microchip Technology Inc.

TABLE 1-2: PIC16(L)F1933 PINOUT DESCRIPTION

RA0/AN0/C12IN0-/C2OUT(1)/ RA0 TTL CMOS General purpose I/O.

 2011-2012 Microchip Technology Inc. DS41575C-page 9

DS41575C-page 10  2011-2012 Microchip Technology Inc.

 2011-2012 Microchip Technology Inc. DS41575C-page 11

DS41575C-page 12  2011-2012 Microchip Technology Inc.

2.1 Automatic Interrupt Context

2.2 16-level Stack with Overflow and

2.3 File Select Registers

2.4 Instruction Set

 2011-2012 Microchip Technology Inc. DS41575C-page 13

DS41575C-page 14  2011-2012 Microchip Technology Inc.

Note 1: The Data EEPROM Memory and the

TABLE 3-1: DEVICE SIZES AND ADDRESSES

 2011-2012 Microchip Technology Inc. DS41575C-page 15

Stack Level 15 EXAMPLE 3-1: RETLW INSTRUCTION

The BRW instruction makes this type of table very

DS41575C-page 16  2011-2012 Microchip Technology Inc.

3.2 Data Memory Organization

 2011-2012 Microchip Technology Inc. DS41575C-page 17

bit 7-5 Unimplemented: Read as ‘0’

DS41575C-page 18  2011-2012 Microchip Technology Inc.

3.3.3 COMMON RAM General Purpose RAM

3.3.4 DEVICE MEMORY MAPS

TABLE 3-2: MEMORY MAP TABLES

 2011-2012 Microchip Technology Inc. DS41575C-page 19

06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh

Legend: = Unimplemented data memory locations, read as ‘0’.

41Fh — 49Fh — 51Fh — 59Fh — 61Fh — 69Fh — 71Fh — 79Fh

Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented

46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh

Legend: = Unimplemented data memory locations, read as ‘0’.

81Fh — 89Fh — 91Fh — 99Fh — A1Fh — A9Fh — B1Fh — B9Fh —

Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented

86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh

Legend: = Unimplemented data memory locations, read as ‘0’.

C1Fh — C9Fh — D1Fh — D9Fh — E1Fh — E9Fh — F1Fh — F9Fh

Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented