Chip Data Sheet (Signal Generator)

PIC24FJ64GA004 FAMILY
28/44-Pin General Purpose, 16-Bit Flash Microcontrollers
High-Performance CPU Analog Features

• Modified Harvard Architecture • 10-Bit, up to 13-Channel Analog-to-Digital Converter:
• Up to 16 MIPS Operation @ 32 MHz - 500 ksps conversion rate
• 8 MHz Internal Oscillator with 4x PLL Option and - Conversion available during Sleep and Idle
Multiple Divide Options • Dual Analog Comparators with Programmable
• 17-Bit by 17-Bit Single-Cycle Hardware Multiplier Input/Output Configuration
• 32-Bit by 16-Bit Hardware Divider
• 16-Bit x 16-Bit Working Register Array
Peripheral Features
• C Compiler Optimized Instruction Set Architecture: • Peripheral Pin Select (PPS):
- 76 base instructions - Allows independent I/O mapping of many peripherals
- Flexible addressing modes - Up to 26 available pins (44-pin devices)
• Two Address Generation Units (AGUs) for Separate - Continuous hardware integrity checking and safety
Read and Write Addressing of Data Memory interlocks prevent unintentional configuration changes
• 8-Bit Parallel Master/Slave Port (PMP/PSP):
Special Microcontroller Features - Up to 16-bit multiplexed addressing, with up to
• Operating Voltage Range of 2.0V to 3.6V 11 dedicated address pins on 44-pin devices
• 5.5V Tolerant Input (digital pins only) - Programmable polarity on control lines
• High-Current Sink/Source (18 mA/18 mA) on All I/O Pins • Hardware Real-Time Clock/Calendar (RTCC):
• Flash Program Memory: - Provides clock, calendar and alarm functions
- 10,000 erase/write • Programmable Cyclic Redundancy Check (CRC)
- 20-year data retention minimum • Two 3-Wire/4-Wire SPI modules (support 4 Frame
• Power Management modes: modes) with 8-Level FIFO Buffer
- Sleep, Idle, Doze and Alternate Clock modes • Two I2C™ modules Support Multi-Master/Slave
- Operating current: 650 A/MIPS, typical at 2.0V mode and 7-Bit/10-Bit Addressing
- Sleep current: 150 nA, typical at 2.0V • Two UART modules:
• Fail-Safe Clock Monitor (FSCM) Operation: - Supports RS-485, RS-232, and LIN/J2602
- Detects clock failure and switches to on-chip, - On-chip hardware encoder/decoder for IrDA®
low-power RC oscillator - Auto-wake-up on Start bit
• On-Chip, 2.5V Regulator with Tracking mode - Auto-Baud Detect
• Power-on Reset (POR), Power-up Timer (PWRT) - 4-level deep FIFO buffer
and Oscillator Start-up Timer (OST) • Five 16-Bit Timers/Counters with Programmable Prescaler
• Flexible Watchdog Timer (WDT) with On-Chip, • Five 16-Bit Capture Inputs
Low-Power RC Oscillator for Reliable Operation • Five 16-Bit Compare/PWM Outputs
• In-Circuit Serial Programming™ (ICSP™) and • Configurable Open-Drain Outputs on Digital I/O Pins
In-Circuit Debug (ICD) via 2 Pins • Up to 3 External Interrupt Sources
• JTAG Boundary Scan Support
Remappable Peripherals
Comparators
10-Bit A/D
PMP/PSP
Program
Memory
Remappable
(bytes)
(bytes)
SRAM
JTAG
Compare/
I2C™
Pins
UART w/
(ch)
Capture
Output
Timers
16-Bit
Device
IrDA®
Input
PWM
Pins
SPI
PIC24FJ16GA002 28 16K 4K 16 5 5 5 2 2 2 10 2 Y Y
PIC24FJ32GA002 28 32K 8K 16 5 5 5 2 2 2 10 2 Y Y
PIC24FJ48GA002 28 48K 8K 16 5 5 5 2 2 2 10 2 Y Y
PIC24FJ64GA002 28 64K 8K 16 5 5 5 2 2 2 10 2 Y Y
PIC24FJ16GA004 44 16K 4K 26 5 5 5 2 2 2 13 2 Y Y
PIC24FJ32GA004 44 32K 8K 26 5 5 5 2 2 2 13 2 Y Y
PIC24FJ48GA004 44 48K 8K 26 5 5 5 2 2 2 13 2 Y Y
PIC24FJ64GA004 44 64K 8K 26 5 5 5 2 2 2 13 2 Y Y
 2010-2013 Microchip Technology Inc. DS39881E-page 1

Pin Diagrams
28-Pin SPDIP, SSOP, SOIC
MCLR 1 28 VDD
AN0/VREF+/CN2/RA0 2 27 VSS
AN1/VREF-/CN3/RA1 3 26 AN9/RP15/CN11/PMCS1/RB15
PIC24FJXXGA002
PGED1/AN2/C2IN-/RP0/CN4/RB0 4 25 AN10/CVREF/RTCC/RP14/CN12/PMWR/RB14
PGEC1/AN3/C2IN+/RP1/CN5/RB1 5 24 AN11/RP13/CN13/PMRD/RB13
AN4/C1IN-/SDA2/RP2/CN6/RB2 6 23 AN12/RP12/CN14/PMD0/RB12
AN5/C1IN+/SCL2/RP3/CN7/RB3 7 22 PGEC2/TMS/RP11/CN15/PMD1/RB11
VSS 8 21 PGED2/TDI/RP10/CN16/PMD2/RB10
OSCI/CLKI/CN30/RA2 9 20 VCAP/VDDCORE
OSCO/CLKO/CN29/PMA0/RA3 10 19 DISVREG
SOSCI/RP4/PMBE/CN1/RB4 11 18 TDO/SDA1/RP9/CN21/PMD3/RB9
SOSCO/T1CK/CN0/PMA1/RA4 12 17 TCK/SCL1/RP8/CN22/PMD4/RB8
VDD 13 16 RP7/INT0/CN23/PMD5/RB7
PGED3/ASDA1/RP5/CN27/PMD7/RB5 14 15 PGEC3/ASCL1/RP6/CN24/PMD6/RB6
28-Pin QFN(1)
AN10/CVREF/RTCC/RP14/CN12/PMWR/RB14
AN9/RP15/CN11/PMCS1/RB15
AN0/VREF+/CN2/RA0
AN1/VREF-/CN3/RA1
MCLR
VDD
VSS
28 27 26 25 24 23 22
PGED1/AN2/C2IN-/RP0/CN4/RB0 1 21 AN11/RP13/CN13/PMRD/RB13
PGEC1/AN3/C2IN+/RP1/CN5/RB1 2 20 AN12/RP12/CN14/PMD0/RB12
AN4/C1IN-/SDA2/RP2/CN6/RB2 3 19 PGEC2/TMS/RP11/CN15/PMD1/RB11
AN5/C1IN+/SCL2/RP3/CN7/RB3 4 PIC24FJXXGA002 18 PGED2/TDI/RP10/CN16/PMD2/RB10
VSS 5 17 VCAP/VDDCORE
OSCI/CLKI/CN30/RA2 6 16 DISVREG
OSCO/CLKO/CN29/PMA0/RA3 7 15 TDO/SDA1/RP9/CN21/PMD3/RB9
8 9 10 11 12 13 14
RP7/INT0/CN23/PMD5/RB7
PGED3/ASDA1/RP5/CN27/PMD7/RB5
SOSCO/T1CK/CN0/PMA1/RA4
SOSCI/RP4/PMBE/CN1/RB4
VDD
TCK/SCL1/RP8/CN22/PMD4/RB8
PGEC3/ASCL1/RP6/CN24/PMD6/RB6
Legend: RPn represents remappable peripheral pins. Gray shading indicates 5.5V tolerant input pins.
Note 1: Back pad on QFN devices should be connected to Vss.
DS39881E-page 2  2010-2013 Microchip Technology Inc.

Pin Diagrams (Continued)
44-Pin QFN(1)
PGED3/ASDA1/RP5/CN27/PMD7/RB5
PGEC3/ASCL1/RP6/CN24/PMD6/RB6
SCL1/RP8/CN22/PMD4/RB8
SOSCO/T1CK/CN0/RA4
RP19/CN28/PMBE/RC3
RP21/CN26/PMA3/RC5
RP20/CN25/PMA4/RC4
TDI/PMA9/RA9
VDD
VSS
44
43
42
41
40
39
38
37
36
35
34
SDA1/RP9/CN21/PMD3/RB9 1 33 SOSCI/RP4/CN1/RB4
RP22/CN18/PMA1/RC6 2 32 TDO/PMA8/RA8
RP23/CN17/PMA0/RC7 3 31 OSCO/CLKO/CN29/RA3
RP24/CN20/PMA5/RC8 4 30 OSCI/CLKI/CN30/RA2
RP25/CN19/PMA6/RC9 5 29 VSS
DISVREG 6 PIC24FJXXGA004 28 VDD
VCAP/VDDCORE 7 27 AN8/RP18/CN10/PMA2/RC2
PGED2/RP10/CN16/PMD2/RB10 8 26 AN7/RP17/CN9/RC1
PGEC2/RP11/CN15/PMD1/RB11 9 25 AN6/RP16/CN8/RC0
AN12/RP12/CN14/PMD0/RB12 10 24 AN5/C1IN+/SCL2/RP3/CN7/RB3
AN11/RP13/CN13/PMRD/RB13 11 23 AN4/C1IN-/SDA2/RP2/CN6/RB2
12
13
14
15
16
17
18
19
20
21
22
MCLR
AVSS
AN0/VREF+/CN2/RA0
TMS/PMA10/RA10
AN1/VREF-/CN3/RA1
PGED1/AN2/C2IN-/RP0/CN4/RB0
PGEC1/AN3/C2IN+/RP1/CN5/RB1
TCK/PMA7/RA7
AVDD
Note 1: Back pad on QFN devices should be connected to Vss.

Pin Diagrams (Continued)
44-Pin TQFP
PGED3/RP5/ASDA1/CN27/PMD7/RB5
PGEC3/RP6/ASCL1/CN24/PMD6/RB6
SCL1/RP8/CN22/PMD4/RB8
SOSCO/T1CK/CN0/RA4
RP19/CN28/PMBE/RC3
RP21/CN26/PMA3/RC5
RP20/CN25/PMA4/RC4
TDI/PMA9/RA9
VDD
VSS
38
44
43
42
41
40
39
37
36
35
34
SDA1/RP9/CN21/PMD3/RB9 1 33 SOSCI/RP4/CN1/RB4
RP22/CN18/PMA1/RC6 2 32 TDO/PMA8/RA8
RP23/CN17/PMA0/RC7 3 31 OSCO/CLKO/CN29/RA3
RP24/CN20/PMA5/RC8 4 30 OSCI/CLKI/CN30/RA2
RP25/CN19/PMA6/RC9 5 29 VSS
DISVREG 6 PIC24FJXXGA004 28 VDD
VCAP/VDDCORE 7 27 AN8/RP18/CN10/PMA2/RC2
PGED2/RP10/CN16/PMD2/RB10 8 26 AN7/RP17/CN9/RC1
PGEC2/RP11/CN15/PMD1/RB11 9 25 AN6/RP16/CN8/RC0
AN12/RP12/CN14/PMD0/RB12 10 24 AN5/C1IN+/SCL2/RP3/CN7/RB3
AN11/RP13/CN13/PMRD/RB13 11 23 AN4/C1IN-/SDA2/RP2/CN6/RB2
12
13
14
15
16
17
18
19
20
21
22
MCLR
AVSS
AN0/VREF+/CN2/RA0
TMS/PMA10/RA10
TCK/PMA7/RA7
AN1/VREF-/CN3/RA1
PGED1/AN2/C2IN-/RP0/CN4/RB0
PGEC1/AN3/C2IN+/RP1/CN5/RB1
AVDD

Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................ 17
3.0 CPU ........................................................................................................................................................................................... 23
4.0 Memory Organization ................................................................................................................................................................. 29
5.0 Flash Program Memory.............................................................................................................................................................. 47
6.0 Resets ........................................................................................................................................................................................ 53
7.0 Interrupt Controller ..................................................................................................................................................................... 59
8.0 Oscillator Configuration .............................................................................................................................................................. 95
9.0 Power-Saving Features............................................................................................................................................................ 103
10.0 I/O Ports ................................................................................................................................................................................... 105
11.0 Timer1 ..................................................................................................................................................................................... 125
12.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 127
13.0 Input Capture............................................................................................................................................................................ 133
14.0 Output Compare....................................................................................................................................................................... 135
15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 141
16.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................. 151
17.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 159
18.0 Parallel Master Port (PMP)....................................................................................................................................................... 167
19.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 177
20.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 189
21.0 10-Bit High-Speed A/D Converter ............................................................................................................................................ 193
22.0 Comparator Module.................................................................................................................................................................. 203
23.0 Comparator Voltage Reference................................................................................................................................................ 207
24.0 Special Features ...................................................................................................................................................................... 209
25.0 Development Support............................................................................................................................................................... 219
26.0 Instruction Set Summary .......................................................................................................................................................... 223
27.0 Electrical Characteristics .......................................................................................................................................................... 231
28.0 Packaging Information.............................................................................................................................................................. 251
Appendix A: Revision History............................................................................................................................................................. 267
Appendix B: Additional Guidance for PIC24FJ64GA004 Family Applications ................................................................................... 268
Index ................................................................................................................................................................................................. 269
The Microchip Web Site ..................................................................................................................................................................... 273
Customer Change Notification Service .............................................................................................................................................. 273
Customer Support .............................................................................................................................................................................. 273
Reader Response .............................................................................................................................................................................. 274
Product Identification System ............................................................................................................................................................ 275

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1.0 DEVICE OVERVIEW 1.1.2 POWER-SAVING TECHNOLOGY
This document contains device-specific information for All of the devices in the PIC24FJ64GA004 family
the following devices: incorporate a range of features that can significantly
reduce power consumption during operation. Key
• PIC24FJ16GA002 items include:
• PIC24FJ32GA002
• On-the-Fly Clock Switching: The device clock
• PIC24FJ48GA002 can be changed under software control to the
• PIC24FJ64GA002 Timer1 source or the internal, low-power RC
• PIC24FJ16GA004 oscillator during operation, allowing the user to
• PIC24FJ32GA004 incorporate power-saving ideas into their software
designs.
• PIC24FJ48GA004
• Doze Mode Operation: When timing-sensitive
• PIC24FJ64GA004
applications, such as serial communications,
This family introduces a new line of Microchip devices: require the uninterrupted operation of peripherals,
a 16-bit microcontroller family with a broad peripheral the CPU clock speed can be selectively reduced,
feature set and enhanced computational performance. allowing incremental power savings without
The PIC24FJ64GA004 family offers a new migration missing a beat.
option for those high-performance applications which • Instruction-Based Power-Saving Modes: The
may be outgrowing their 8-bit platforms, but don’t microcontroller can suspend all operations, or
require the numerical processing power of a digital selectively shut down its core while leaving its
signal processor. peripherals active, with a single instruction in
software.
1.1 Core Features
1.1.3 OSCILLATOR OPTIONS AND
1.1.1 16-BIT ARCHITECTURE FEATURES
Central to all PIC24F devices is the 16-bit modified All of the devices in the PIC24FJ64GA004 family offer
Harvard architecture, first introduced with Microchip’s five different oscillator options, allowing users a range
dsPIC® Digital Signal Controllers (DSCs). The PIC24F of choices in developing application hardware. These
CPU core offers a wide range of enhancements, such as: include:
• 16-bit data and 24-bit address paths with the • Two Crystal modes using crystals or ceramic
ability to move information between data and resonators.
memory spaces • Two External Clock modes offering the option of a
• Linear addressing of up to 12 Mbytes (program divide-by-2 clock output.
space) and 64 Kbytes (data) • A Fast Internal Oscillator (FRC) with a nominal
• A 16-element working register array with built-in 8 MHz output, which can also be divided under
software stack support software control to provide clock speeds as low as
• A 17 x 17 hardware multiplier with support for 31 kHz.
integer math • A Phase Lock Loop (PLL) frequency multiplier,
• Hardware support for 32 by 16-bit division available to the External Oscillator modes and the
• An instruction set that supports multiple FRC oscillator, which allows clock speeds of up to
addressing modes and is optimized for high-level 32 MHz.
languages such as ‘C’ • A separate internal RC oscillator (LPRC) with a
• Operational performance up to 16 MIPS fixed 31 kHz output, which provides a low-power
option for timing-insensitive applications.
The internal oscillator block also provides a stable
reference source for the Fail-Safe Clock Monitor. This
option constantly monitors the main clock source
against a reference signal provided by the internal
oscillator and enables the controller to switch to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.

1.1.4 EASY MIGRATION 1.3 Details on Individual Family
Regardless of the memory size, all devices share the Members
same rich set of peripherals, allowing for a smooth
Devices in the PIC24FJ64GA004 family are available
migration path as applications grow and evolve.
in 28-pin and 44-pin packages. The general block
The consistent pinout scheme used throughout the diagram for all devices is shown in Figure 1-1.
entire family also aids in migrating to the next larger
The devices are differentiated from each other in two
device. This is true when moving between devices with
ways:
the same pin count, or even jumping from 28-pin to
44-pin devices. 1. Flash program memory (64 Kbytes for
PIC24FJ64GA devices, 48 Kbytes for
The PIC24F family is pin-compatible with devices in the
PIC24FJ48GA devices, 32 Kbytes for
dsPIC33 family, and shares some compatibility with the
PIC24FJ32GA devices and 16 Kbytes for
pinout schema for PIC18 and dsPIC30. This extends
PIC24FJ16GA devices).
the ability of applications to grow from the relatively
simple, to the powerful and complex, yet still selecting 2. Internal SRAM memory (4k for PIC24FJ16GA
a Microchip device. devices, 8k for all other devices in the family).
3. Available I/O pins and ports (21 pins on 2 ports
1.2 Other Special Features for 28-pin devices and 35 pins on 3 ports for
44-pin devices).
• Communications: The PIC24FJ64GA004 family All other features for devices in this family are identical.
incorporates a range of serial communication These are summarized in Table 1-1.
peripherals to handle a range of application
requirements. There are two independent I2C A list of the pin features that are available on the
modules that support both Master and Slave PIC24FJ64GA004 family devices, sorted by function, is
modes of operation. Devices also have, through shown in Table 1-2. Note that this table shows the pin
the Peripheral Pin Select (PPS) feature, two location of individual peripheral features and not how
independent UARTs with built-in IrDA they are multiplexed on the same pin. This information
encoder/decoders and two SPI modules. is provided in the pinout diagrams in the beginning of
the data sheet. Multiplexed features are sorted by the
• Peripheral Pin Select (PPS): The Peripheral Pin
priority given to a feature, with the highest priority
Select feature allows most digital peripherals to
peripheral being listed first.
be mapped over a fixed set of digital I/O pins.
Users may independently map the input and/or
output of any one of the many digital peripherals
to any one of the I/O pins.
• Parallel Master/Enhanced Parallel Slave Port:
One of the general purpose I/O ports can be
reconfigured for enhanced parallel data communi-
cations. In this mode, the port can be configured
for both master and slave operations, and
supports 8-bit and 16-bit data transfers with up to
16 external address lines in Master modes.
• Real-Time Clock/Calendar (RTCC): This module
implements a full-featured clock and calendar with
alarm functions in hardware, freeing up timer
resources and program memory space for use of
the core application.
• 10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period, as
well as faster sampling speeds.

TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ64GA004 FAMILY
16GA002
32GA002
48GA002
64GA002
16GA004
32GA004
48GA004
64GA004
Features
Operating Frequency DC – 32 MHz

Program Memory (bytes) 16K 32K 48K 64K 16K 32K 48K 64K
Program Memory (instructions) 5,504 11,008 16,512 22,016 5,504 11,008 16,512 22,016
Data Memory (bytes) 4096 8192 4096 8192
Interrupt Sources 43
(soft vectors/NMI traps) (39/4)
I/O Ports Ports A, B Ports A, B, C
Total I/O Pins 21 35
Timers:
Total Number (16-bit) 5(1)
32-Bit (from paired 16-bit timers) 2
Input Capture Channels 5(1)
Output Compare/PWM Channels 5(1)
Input Change Notification Interrupt 21 30
Serial Communications:
UART 2(1)
SPI (3-wire/4-wire) 2(1)
I2C™ 2
Parallel Communications (PMP/PSP) Yes
JTAG Boundary Scan Yes
10-Bit Analog-to-Digital Module 10 13
(input channels)
Analog Comparators 2
Remappable Pins 16 26
Resets (and delays) POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode,
REPEAT Instruction, Hardware Traps, Configuration Word Mismatch
(PWRT, OST, PLL Lock)
Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations
Packages 28-Pin SPDIP/SSOP/SOIC/QFN 44-Pin QFN/TQFP
Note 1: Peripherals are accessible through remappable pins.

FIGURE 1-1: PIC24FJ64GA004 FAMILY GENERAL BLOCK DIAGRAM
Interrupt Data Bus

Controller
16
8 16 16
PSV & Table Data Latch

Data Access
Control Block PCH PCL Data RAM
23
Program Counter Address
Stack Repeat Latch PORTA(1)
Control Control
Logic Logic RA<9:0>
16
23
16
Address Latch Read AGU

Write AGU
PORTB
Program Memory
RB<15:0>
Data Latch
EA MUX 16
Address Bus
Literal Data
24 16 16 PORTC(1)
RC<9:0>
Inst Latch
Inst Register
Instruction RP(1)
Decode &
Control RP<25:0>
Divide
Control Signals Support 16 x 16
17x17 W Reg Array
Timing Power-up Multiplier
OSCO/CLKO
OSCI/CLKI Generation Timer
Oscillator
FRC/LPRC Start-up Timer
Oscillators 16-Bit ALU
Power-on
Reset
16
Precision
Band Gap Watchdog
Reference Timer
DISVREG BOR and
Voltage
Regulator LVD(2)
VDDCORE/VCAP VDD, VSS MCLR
10-Bit
Timer1 Timer2/3(3) Timer4/5(3) RTCC A/D Comparators(3)
PMP/PSP
PWM/
IC1-5(3) CN1-22(1) SPI1/2(3) I2C1/2 UART1/2(3)
OC1-5(3)
Note 1: Not all pins or features are implemented on all device pinout configurations. See Table 1-2 for I/O port pin descriptions.
2: BOR and LVD functionality is provided when the on-board voltage regulator is enabled.
3: Peripheral I/Os are accessible through remappable pins.

TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS
Pin Number
28-Pin Input
Function 28-Pin 44-Pin I/O Description
SPDIP/ Buffer
QFN QFN/TQFP
SSOP/SOIC
AN0 2 27 19 I ANA A/D Analog Inputs.

AN1 3 28 20 I ANA
AN2 4 1 21 I ANA
AN3 5 2 22 I ANA
AN4 6 3 23 I ANA
AN5 7 4 24 I ANA
AN6 — — 25 I ANA
AN7 — — 26 I ANA
AN8 — — 27 I ANA
AN9 26 23 15 I ANA
AN10 25 22 14 I ANA
AN11 24 21 11 I ANA
AN12 23 20 10 I ANA
ASCL1 15 12 42 I/O I2C Alternate I2C1 Synchronous Serial Clock Input/Output.(1)
2
ASDA1 14 11 41 I/O I C Alternate I2C2 Synchronous Serial Clock Input/Output. (1)
AVDD — — 17 P — Positive Supply for Analog Modules.
AVSS — — 16 P — Ground Reference for Analog Modules.
C1IN- 6 3 23 I ANA Comparator 1 Negative Input.
C1IN+ 7 4 24 I ANA Comparator 1 Positive Input.
C2IN- 4 1 21 I ANA Comparator 2 Negative Input.
C2IN+ 5 2 22 I ANA Comparator 2 Positive Input.
CLKI 9 6 30 I ANA Main Clock Input Connection.
CLKO 10 7 31 O — System Clock Output.
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I2C™ = I2C/SMBus input buffer
Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.

TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
28-Pin Input
SPDIP/ Buffer
QFN QFN/TQFP
SSOP/SOIC
CN0 12 9 34 I ST Interrupt-on-Change Inputs.

CN1 11 8 33 I ST
CN2 2 27 19 I ST
CN3 3 28 20 I ST
CN4 4 1 21 I ST
CN5 5 2 22 I ST
CN6 6 3 23 I ST
CN7 7 4 24 I ST
CN8 — — 25 I ST
CN9 — — 26 I ST
CN10 — — 27 I ST
CN11 26 23 15 I ST
CN12 25 22 14 I ST
CN13 24 21 11 I ST
CN14 23 20 10 I ST
CN15 22 19 9 I ST
CN16 21 18 8 I ST
CN17 — — 3 I ST
CN18 — — 2 I ST
CN19 — — 5 I ST
CN20 — — 4 I ST
CN21 18 15 1 I ST
CN22 17 14 44 I ST
CN23 16 13 43 I ST
CN24 15 12 42 I ST
CN25 — — 37 I ST
CN26 — — 38 I ST
CN27 14 11 41 I ST
CN28 — — 36 I ST
CN29 10 7 31 I ST
CN30 9 6 30 I ST
CVREF 25 22 14 O ANA Comparator Voltage Reference Output.
DISVREG 19 16 6 I ST Voltage Regulator Disable.
INT0 16 13 43 I ST External Interrupt Input.
MCLR 1 26 18 I ST Master Clear (device Reset) Input. This line is brought low
to cause a Reset.

Pin Number
28-Pin Input
SPDIP/ Buffer
QFN QFN/TQFP
SSOP/SOIC
OSCI 9 6 30 I ANA Main Oscillator Input Connection.

OSCO 10 7 31 O ANA Main Oscillator Output Connection.
PGEC1 5 2 22 I/O ST In-Circuit Debugger/Emulator and ICSP™ Programming
PGEC2 22 19 9 I/O ST Clock.
PGEC3 14 12 42 I/O ST
PGED1 4 1 21 I/O ST In-Circuit Debugger/Emulator and ICSP Programming
PGED2 21 18 8 I/O ST Data.
PGED3 15 11 41 I/O ST
PMA0 10 7 3 I/O ST/TTL Parallel Master Port Address Bit 0 Input (Buffered Slave
modes) and Output (Master modes).
PMA1 12 9 2 I/O ST/TTL Parallel Master Port Address Bit 1 Input (Buffered Slave
modes) and Output (Master modes).
PMA2 — — 27 O — Parallel Master Port Address (Demultiplexed Master
PMA3 — — 38 O — modes).
PMA4 — — 37 O —
PMA5 — — 4 O —
PMA6 — — 5 O —
PMA7 — — 13 O —
PMA8 — — 32 O —
PMA9 — — 35 O —
PMA10 — — 12 O —
PMA11 — — — O —
PMA12 — — — O —
PMA13 — — — O —
PMBE 11 8 36 O — Parallel Master Port Byte Enable Strobe.
PMCS1 26 23 15 O — Parallel Master Port Chip Select 1 Strobe/Address Bit 14.
PMD0 23 20 10 I/O ST/TTL Parallel Master Port Data (Demultiplexed Master mode) or
PMD1 22 19 9 I/O ST/TTL Address/Data (Multiplexed Master modes).
PMD2 21 18 8 I/O ST/TTL

PMRD 24 21 11 O — Parallel Master Port Read Strobe.
PMWR 25 22 14 O — Parallel Master Port Write Strobe.

Pin Number
28-Pin Input
SPDIP/ Buffer
QFN QFN/TQFP
SSOP/SOIC
RA0 2 27 19 I/O ST PORTA Digital I/O.

RA1 3 28 20 I/O ST
RA2 9 6 30 I/O ST
RA3 10 7 31 I/O ST
RA4 12 9 34 I/O ST
RA7 — — 13 I/O ST
RA8 — — 32 I/O ST
RA9 — — 35 I/O ST
RA10 — — 12 I/O ST
RB0 4 1 21 I/O ST PORTB Digital I/O.
RB1 5 2 22 I/O ST
RB2 6 3 23 I/O ST
RB3 7 4 24 I/O ST
RB4 11 8 33 I/O ST
RB5 14 11 41 I/O ST
RB6 15 12 42 I/O ST
RB7 16 13 43 I/O ST
RB8 17 14 44 I/O ST
RB9 18 15 1 I/O ST
RB10 21 18 8 I/O ST
RB11 22 19 9 I/O ST
RB12 23 20 10 I/O ST
RB13 24 21 11 I/O ST
RB14 25 22 14 I/O ST
RB15 26 23 15 I/O ST
RC0 — — 25 I/O ST PORTC Digital I/O.
RC1 — — 26 I/O ST
RC2 — — 27 I/O ST
RC3 — — 36 I/O ST
RC4 — — 37 I/O ST
RC5 — — 38 I/O ST
RC6 — — 2 I/O ST
RC7 — — 3 I/O ST
RC8 — — 4 I/O ST
RC9 — — 5 I/O ST

Pin Number
28-Pin Input
SPDIP/ Buffer
QFN QFN/TQFP
SSOP/SOIC
RP0 4 1 21 I/O ST Remappable Peripheral.

RP1 5 2 22 I/O ST
RP2 6 3 23 I/O ST
RP3 7 4 24 I/O ST
RP4 11 8 33 I/O ST
RP5 14 11 41 I/O ST
RP6 15 12 42 I/O ST
RP7 16 13 43 I/O ST
RP8 17 14 44 I/O ST
RP9 18 15 1 I/O ST
RP10 21 18 8 I/O ST
RP11 22 19 9 I/O ST
RP12 23 20 10 I/O ST
RP13 24 21 11 I/O ST
RP14 25 22 14 I/O ST
RP15 26 23 15 I/O ST
RP16 — — 25 I/O ST
RP17 — — 26 I/O ST
RP18 — — 27 I/O ST
RP19 — — 36 I/O ST
RP20 — — 37 I/O ST
RP21 — — 38 I/O ST
RP22 — — 2 I/O ST
RP23 — — 3 I/O ST
RP24 — — 4 I/O ST
RP25 — — 5 I/O ST
RTCC 25 22 14 O — Real-Time Clock Alarm Output.
SCL1 17 14 44 I/O I2C I2C1 Synchronous Serial Clock Input/Output.
SCL2 7 4 24 I/O I2C I2C2 Synchronous Serial Clock Input/Output.
SDA1 18 15 1 I/O I2C I2C1 Data Input/Output.
SDA2 6 3 23 I/O I2C I2C2 Data Input/Output.
SOSCI 11 8 33 I ANA Secondary Oscillator/Timer1 Clock Input.
SOSCO 12 9 34 O ANA Secondary Oscillator/Timer1 Clock Output.

Pin Number
28-Pin Input
SPDIP/ Buffer
QFN QFN/TQFP
SSOP/SOIC
T1CK 12 9 34 I ST Timer1 Clock.

TCK 17 14 13 I ST JTAG Test Clock Input.
TDI 21 18 35 I ST JTAG Test Data Input.
TDO 18 15 32 O — JTAG Test Data Output.
TMS 22 19 12 I ST JTAG Test Mode Select Input.
VDD 13, 28 10, 25 28, 40 P — Positive Supply for Peripheral Digital Logic and I/O Pins.
VDDCAP 20 17 7 P — External Filter Capacitor Connection (regulator enabled).
VDDCORE 20 17 7 P — Positive Supply for Microcontroller Core Logic (regulator
disabled).
VREF- 3 28 20 I ANA A/D and Comparator Reference Voltage (low) Input.
VREF+ 2 27 19 I ANA A/D and Comparator Reference Voltage (high) Input.
VSS 8, 27 5, 24 29, 39 P — Ground Reference for Logic and I/O Pins.

2.0 GUIDELINES FOR GETTING FIGURE 2-1: RECOMMENDED
STARTED WITH 16-BIT MINIMUM CONNECTIONS
MICROCONTROLLERS
C2(2)
2.1 Basic Connection Requirements VDD
Getting started with the PIC24FJ64GA004 family of
VDD
VSS
R1 (1) (1)
16-bit microcontrollers requires attention to a minimal R2 (EN/DIS)VREG
set of device pin connections before proceeding with MCLR
development. VCAP/VDDCORE
C1
The following pins must always be connected: C7
PIC24FJXXXX
• All VDD and VSS pins
(see Section 2.2 “Power Supply Pins”) VSS VDD
C6(2) C3(2)
• All AVDD and AVSS pins, regardless of whether or
VDD VSS
not the analog device features are used
AVDD
AVSS
VDD
VSS
(see Section 2.2 “Power Supply Pins”)
• MCLR pin
(see Section 2.3 “Master Clear (MCLR) Pin”)
C5(2) C4(2)
• ENVREG/DISVREG and VCAP/VDDCORE pins
(PIC24F J devices only)
(see Section 2.4 “Voltage Regulator Pins
Key (all values are recommendations):
(ENVREG/DISVREG and VCAP/VDDCORE)”)
C1 through C6: 0.1 F, 20V ceramic
These pins must also be connected if they are being
C7: 10 F, 6.3V or greater, tantalum or ceramic
used in the end application:
R1: 10 kΩ
• PGECx/PGEDx pins used for In-Circuit Serial
R2: 100Ω to 470Ω
Programming™ (ICSP™) and debugging purposes
Note 1: See Section 2.4 “Voltage Regulator Pins
(see Section 2.5 “ICSP Pins”)
(ENVREG/DISVREG and VCAP/VDDCORE)”
• OSCI and OSCO pins when an external oscillator for an explanation of the ENVREG/DISVREG
source is used pin connections.
(see Section 2.6 “External Oscillator Pins”) 2: The example shown is for a PIC24F device
Additionally, the following pins may be required: with five VDD/VSS and AVDD/AVSS pairs.
Other devices may have more or less pairs;
• VREF+/VREF- pins used when external voltage adjust the number of decoupling capacitors
reference for analog modules is implemented appropriately.
Note: The AVDD and AVSS pins must always be
connected, regardless of whether any of
the analog modules are being used.
The minimum mandatory connections are shown in
Figure 2-1.

2.2 Power Supply Pins 2.3 Master Clear (MCLR) Pin
2.2.1 DECOUPLING CAPACITORS The MCLR pin provides two specific device functions:
device Reset, and device programming and debug-
The use of decoupling capacitors on every pair of ging. If programming and debugging are not required
power supply pins, such as VDD, VSS, AVDD and in the end application, a direct connection to VDD may
AVSS is required. be all that is required. The addition of other com-
Consider the following criteria when using decoupling ponents, to help increase the application’s resistance
capacitors: to spurious Resets from voltage sags, may be
beneficial. A typical configuration is shown in
• Value and type of capacitor: A 0.1 F (100 nF),
Figure 2-1. Other circuit designs may be implemented,
10-20V capacitor is recommended. The capacitor
depending on the application’s requirements.
should be a low-ESR device with a resonance
frequency in the range of 200 MHz and higher. During programming and debugging, the resistance
Ceramic capacitors are recommended. and capacitance that can be added to the pin must
• Placement on the printed circuit board: The be considered. Device programmers and debuggers
decoupling capacitors should be placed as close drive the MCLR pin. Consequently, specific voltage
to the pins as possible. It is recommended to levels (VIH and VIL) and fast signal transitions must
place the capacitors on the same side of the not be adversely affected. Therefore, specific values
board as the device. If space is constricted, the of R1 and C1 will need to be adjusted based on the
capacitor can be placed on another layer on the application and PCB requirements. For example, it is
PCB using a via; however, ensure that the trace recommended that the capacitor, C1, be isolated
length from the pin to the capacitor is no greater from the MCLR pin during programming and debug-
than 0.25 inch (6 mm). ging operations by using a jumper (Figure 2-2). The
jumper is replaced for normal run-time operations.
• Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of Any components associated with the MCLR pin
tens of MHz), add a second ceramic type capaci- should be placed within 0.25 inch (6 mm) of the pin.
tor in parallel to the above described decoupling
capacitor. The value of the second capacitor can FIGURE 2-2: EXAMPLE OF MCLR PIN
be in the range of 0.01 F to 0.001 F. Place this CONNECTIONS
second capacitor next to each primary decoupling
capacitor. In high-speed circuit designs, consider VDD
implementing a decade pair of capacitances as
close to the power and ground pins as possible R1
(e.g., 0.1 F in parallel with 0.001 F). R2
• Maximizing performance: On the board layout MCLR
from the power supply circuit, run the power and PIC24FXXXX
JP
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the C1
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace Note 1: R1  10 k is recommended. A suggested
inductance. starting value is 10 k. Ensure that the MCLR
pin VIH and VIL specifications are met.
2.2.2 TANK CAPACITORS 2: R2  470 will limit any current flowing into
MCLR from the external capacitor, C, in the
On boards with power traces running longer than six
event of MCLR pin breakdown, due to Electro-
inches in length, it is suggested to use a tank capacitor
static Discharge (ESD) or Electrical
for integrated circuits including microcontrollers to Overstress (EOS). Ensure that the MCLR pin
supply a local power source. The value of the tank VIH and VIL specifications are met.
capacitor should be determined based on the trace
resistance that connects the power supply source to
the device, and the maximum current drawn by the
device in the application. In other words, select the tank
capacitor so that it meets the acceptable voltage sag at
the device. Typical values range from 4.7 F to 47 F.

2.4 Voltage Regulator Pins Designers may use Figure 2-3 to evaluate ESR
(ENVREG/DISVREG and equivalence of candidate devices.
VCAP/VDDCORE) The placement of this capacitor should be close to
VCAP/VDDCORE. It is recommended that the trace
Note: This section applies only to PIC24F J length not exceed 0.25 inch (6 mm). Refer to
devices with an on-chip voltage regulator. Section 27.0 “Electrical Characteristics” for
additional information.
The on-chip voltage regulator enable/disable pin
(ENVREG or DISVREG, depending on the device When the regulator is disabled, the VCAP/VDDCORE pin
family) must always be connected directly to either a must be tied to a voltage supply at the VDDCORE level.
supply voltage or to ground. The particular connection Refer to Section 27.0 “Electrical Characteristics” for
is determined by whether or not the regulator is to be information on VDD and VDDCORE.
used:
FIGURE 2-3: FREQUENCY vs. ESR
• For ENVREG, tie to VDD to enable the regulator,
or to ground to disable the regulator PERFORMANCE FOR
SUGGESTED VCAP
• For DISVREG, tie to ground to enable the
regulator or to VDD to disable the regulator 10
Refer to Section 24.2 “On-Chip Voltage Regulator”

for details on connecting and using the on-chip 1
regulator.
ESR ()
When the regulator is enabled, a low-ESR (< 5Ω) 0.1
capacitor is required on the VCAP/VDDCORE pin to
stabilize the voltage regulator output voltage. The
VCAP/VDDCORE pin must not be connected to VDD and 0.01
must use a capacitor of 10 µF connected to ground. The
type can be ceramic or tantalum. Suitable examples of 0.001
capacitors are shown in Table 2-1. Capacitors with 0.01 0.1 1 10 100 1000 10,000
equivalent specification can be used. Frequency (MHz)
Note: Typical data measurement at 25°C, 0V DC bias.
.
TABLE 2-1: SUITABLE CAPACITOR EQUIVALENTS
Nominal
Make Part # Base Tolerance Rated Voltage Temp. Range
Capacitance
TDK C3216X7R1C106K 10 µF ±10% 16V -55 to +125ºC
TDK C3216X5R1C106K 10 µF ±10% 16V -55 to +85ºC
Panasonic ECJ-3YX1C106K 10 µF ±10% 16V -55 to +125ºC
Panasonic ECJ-4YB1C106K 10 µF ±10% 16V -55 to +85ºC
Murata GRM32DR71C106KA01L 10 µF ±10% 16V -55 to +125ºC
Murata GRM31CR61C106KC31L 10 µF ±10% 16V -55 to +85ºC

2.4.1 CONSIDERATIONS FOR CERAMIC FIGURE 2-4: DC BIAS VOLTAGE vs.
CAPACITORS CAPACITANCE
In recent years, large value, low-voltage, surface-mount CHARACTERISTICS
ceramic capacitors have become very cost effective in
sizes up to a few tens of microfarad. The low-ESR, small
Capacitance Change (%)

10
physical size and other properties make ceramic 0
capacitors very attractive in many types of applications. -10

16V Capacitor
-20
Ceramic capacitors are suitable for use with the inter- -30
-40
nal voltage regulator of this microcontroller. However, -50
10V Capacitor
some care is needed in selecting the capacitor to -60
-70
6.3V Capacitor
ensure that it maintains sufficient capacitance over the -80
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
intended operating range of the application.
DC Bias Voltage (VDC)
Typical low-cost, 10 F ceramic capacitors are available
in X5R, X7R and Y5V dielectric ratings (other types are
also available, but are less common). The initial toler- When selecting a ceramic capacitor to be used with the
ance specifications for these types of capacitors are internal voltage regulator, it is suggested to select a
often specified as ±10% to ±20% (X5R and X7R), or high-voltage rating, so that the operating voltage is a
-20%/+80% (Y5V). However, the effective capacitance small percentage of the maximum rated capacitor volt-
that these capacitors provide in an application circuit will age. For example, choose a ceramic capacitor rated at
also vary based on additional factors, such as the 16V for the 2.5V or 1.8V core voltage. Suggested
applied DC bias voltage and the temperature. The total capacitors are shown in Table 2-1.
in-circuit tolerance is, therefore, much wider than the
initial tolerance specification. 2.5 ICSP Pins
The X5R and X7R capacitors typically exhibit satisfac- The PGECx and PGEDx pins are used for In-Circuit
tory temperature stability (ex: ±15% over a wide Serial Programming (ICSP) and debugging purposes.
temperature range, but consult the manufacturer’s data It is recommended to keep the trace length between
sheets for exact specifications). However, Y5V capaci- the ICSP connector and the ICSP pins on the device as
tors typically have extreme temperature tolerance short as possible. If the ICSP connector is expected to
specifications of +22%/-82%. Due to the extreme tem- experience an ESD event, a series resistor is recom-
perature tolerance, a 10 F nominal rated Y5V type mended, with the value in the range of a few tens of
capacitor may not deliver enough total capacitance to ohms, not to exceed 100Ω.
meet minimum internal voltage regulator stability and
transient response requirements. Therefore, Y5V Pull-up resistors, series diodes and capacitors on the
capacitors are not recommended for use with the PGECx and PGEDx pins are not recommended as they
internal regulator if the application must operate over a will interfere with the programmer/debugger communi-
wide temperature range. cations to the device. If such discrete components are
an application requirement, they should be removed
In addition to temperature tolerance, the effective from the circuit during programming and debugging.
capacitance of large value ceramic capacitors can vary Alternatively, refer to the AC/DC characteristics and
substantially, based on the amount of DC voltage timing requirements information in the respective
applied to the capacitor. This effect can be very signifi- device Flash programming specification for information
cant, but is often overlooked or is not always on capacitive loading limits and pin input voltage high
documented. (VIH) and input low (VIL) requirements.
Typical DC bias voltage vs. capacitance graph for X7R For device emulation, ensure that the “Communication
type capacitors is shown in Figure 2-4. Channel Select” (i.e., PGECx/PGEDx pins),
programmed into the device, matches the physical
connections for the ICSP to the Microchip
debugger/emulator tool.
For more information on available Microchip
development tools connection requirements, refer to
Section 25.0 “Development Support”.

2.6 External Oscillator Pins FIGURE 2-5: SUGGESTED
PLACEMENT OF THE
Many microcontrollers have options for at least two
OSCILLATOR CIRCUIT
oscillators: a high-frequency primary oscillator and a
low-frequency secondary oscillator (refer to Single-Sided and In-line Layouts:
Section 8.0 “Oscillator Configuration” for details).
Copper Pour Primary Oscillator
The oscillator circuit should be placed on the same (tied to ground) Crystal
side of the board as the device. Place the oscillator
DEVICE PINS
circuit close to the respective oscillator pins with no
more than 0.5 inch (12 mm) between the circuit
components and the pins. The load capacitors should
be placed next to the oscillator itself, on the same side Primary OSCI
Oscillator
of the board.
C1 ` OSCO
Use a grounded copper pour around the oscillator
circuit to isolate it from surrounding circuits. The C2 GND
grounded copper pour should be routed directly to the `
MCU ground. Do not run any signal traces or power SOSCO
traces inside the ground pour. Also, if using a two-sided
SOSC I
board, avoid any traces on the other side of the board Secondary
where the crystal is placed. Oscillator
Crystal `
Layout suggestions are shown in Figure 2-5. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With Sec Oscillator: C1 Sec Oscillator: C2
fine-pitch packages, it is not always possible to com-
pletely surround the pins and components. A suitable
solution is to tie the broken guard sections to a mirrored Fine-Pitch (Dual-Sided) Layouts:
ground layer. In all cases, the guard trace(s) must be
returned to ground. Top Layer Copper Pour
(tied to ground)
In planning the application’s routing and I/O assign-
ments, ensure that adjacent port pins, and other
Bottom Layer
signals in close proximity to the oscillator, are benign Copper Pour
(i.e., free of high frequencies, short rise and fall times (tied to ground)
and other similar noise).
OSCO
For additional information and design guidance on
oscillator circuits, please refer to these Microchip
C2
Application Notes, available at the corporate web site
Oscillator
(www.microchip.com): GND Crystal
• AN826, “Crystal Oscillator Basics and Crystal C1
Selection for rfPIC™ and PICmicro® Devices”
• AN849, “Basic PICmicro® Oscillator Design” OSCI
• AN943, “Practical PICmicro® Oscillator Analysis
and Design”
• AN949, “Making Your Oscillator Work”
DEVICE PINS

2.7 Configuration of Analog and If your application needs to use certain A/D pins as
Digital Pins During ICSP analog input pins during the debug session, the user
application must modify the appropriate bits during
Operations
initialization of the A/D module, as follows:
If an ICSP compliant emulator is selected as a debug- • For devices with an ADnPCFG register, clear the
ger, it automatically initializes all of the A/D input pins bits corresponding to the pin(s) to be configured
(ANx) as “digital” pins. Depending on the particular as analog. Do not change any other bits, particu-
device, this is done by setting all bits in the ADnPCFG larly those corresponding to the PGECx/PGEDx
register(s), or clearing all bit in the ANSx registers. pair, at any time.
All PIC24F devices will have either one or more • For devices with ANSx registers, set the bits
ADnPCFG registers or several ANSx registers (one for corresponding to the pin(s) to be configured as
each port); no device will have both. Refer to analog. Do not change any other bits, particularly
Section 21.0 “10-Bit High-Speed A/D Converter” for those corresponding to the PGECx/PGEDx pair,
more specific information. at any time.
The bits in these registers that correspond to the A/D When a Microchip debugger/emulator is used as a
pins that initialized the emulator must not be changed programmer, the user application firmware must
by the user application firmware; otherwise, correctly configure the ADnPCFG or ANSx registers.
communication errors will result between the debugger Automatic initialization of this register is only done
and the device. during debugger operation. Failure to correctly
configure the register(s) will result in all A/D pins being
recognized as analog input pins, resulting in the port
value being read as a logic ‘0’, which may affect user
application functionality.
2.8 Unused I/Os

Unused I/O pins should be configured as outputs and
driven to a logic low state. Alternatively, connect a 1 kΩ
to 10 kΩ resistor to VSS on unused pins and drive the
output to logic low.

3.0 CPU For most instructions, the core is capable of executing
a data (or program data) memory read, a working reg-
Note: This data sheet summarizes the features of ister (data) read, a data memory write and a program
this group of PIC24F devices. It is not (instruction) memory read per instruction cycle. As a
intended to be a comprehensive reference result, three parameter instructions can be supported,
source. For more information, refer to the allowing trinary operations (that is, A + B = C) to be
“PIC24F Family Reference Manual”, executed in a single cycle.
“CPU” (DS39703). A high-speed, 17-bit by 17-bit multiplier has been
The PIC24F CPU has a 16-bit (data) modified Harvard included to significantly enhance the core arithmetic
architecture with an enhanced instruction set and a capability and throughput. The multiplier supports
24-bit instruction word with a variable length opcode Signed, Unsigned and Mixed mode, 16-bit by 16-bit or
field. The Program Counter (PC) is 23 bits wide and 8-bit by 8-bit, integer multiplication. All multiply
addresses up to 4M instructions of user program instructions execute in a single cycle.
memory space. A single-cycle instruction prefetch The 16-bit ALU has been enhanced with integer divide
mechanism is used to help maintain throughput and pro- assist hardware that supports an iterative non-restoring
vides predictable execution. All instructions execute in a divide algorithm. It operates in conjunction with the
single cycle, with the exception of instructions that REPEAT instruction looping mechanism and a selection
change the program flow, the double-word move of iterative divide instructions to support 32-bit (or
(MOV.D) instruction and the table instructions. Over- 16-bit), divided by 16-bit, integer signed and unsigned
head-free program loop constructs are supported using division. All divide operations require 19 cycles to
the REPEAT instructions, which are interruptible at any complete, but are interruptible at any cycle boundary.
point. The PIC24F has a vectored exception scheme with up
PIC24F devices have sixteen, 16-bit working registers to 8 sources of non-maskable traps and up to 118 inter-
in the programmer’s model. Each of the working rupt sources. Each interrupt source can be assigned to
registers can act as a data, address or address offset one of seven priority levels.
register. The 16th working register (W15) operates as A “block diagram of the CPU is shown in Figure 3-1.
a Software Stack Pointer for interrupts and calls.
The upper 32 Kbytes of the data space memory map 3.1 Programmer’s Model
can optionally be mapped into program space at any
16K word boundary defined by the 8-bit Program Space The programmer’s model for the PIC24F is shown in
Visibility Page Address (PSVPAG) register. The program Figure 3-2. All registers in the programmer’s model are
to data space mapping feature lets any instruction memory mapped and can be manipulated directly by
access program space as if it were data space. instructions. A description of each register is provided
in Table 3-1. All registers associated with the
The Instruction Set Architecture (ISA) has been
programmer’s model are memory mapped.
significantly enhanced beyond that of the PIC18, but
maintains an acceptable level of backward compatibil-
ity. All PIC18 instructions and addressing modes are
supported, either directly, or through simple macros.
Many of the ISA enhancements have been driven by
compiler efficiency needs.
The core supports Inherent (no operand), Relative,
Literal, Memory Direct and three groups of addressing
modes. All modes support Register Direct and various
Register Indirect modes. Each group offers up to seven
addressing modes. Instructions are associated with
predefined addressing modes depending upon their
functional requirements.

FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM
PSV & Table

Data Access
Control Block
Data Bus
Interrupt
Controller
16
8 16 16
Data Latch
23
PCH PCL Data RAM 16
23
Program Counter
Stack Loop Address
Control Control Latch
Logic Logic
23 16
RAGU
Address Latch WAGU
Program Memory
Address Bus EA MUX
Data Latch ROM Latch

24 16 16
Instruction Literal Data

Decode &
Control Instruction Reg
Control Signals
to Various Blocks Hardware
Multiplier 16 x 16
Divide W Register Array
Support 16
16-Bit ALU
16
To Peripheral Modules

TABLE 3-1: CPU CORE REGISTERS
Register(s) Name Description
W0 through W15 Working Register Array
PC 23-Bit Program Counter
SR ALU STATUS Register
SPLIM Stack Pointer Limit Value Register
TBLPAG Table Memory Page Address Register
PSVPAG Program Space Visibility Page Address Register
RCOUNT Repeat Loop Counter Register
CORCON CPU Control Register
FIGURE 3-2: PROGRAMMER’S MODEL

15 0
W0 (WREG)
Divider Working Registers
W1
W2
Multiplier Registers
W3
W4
W5
W6
W7 Working/Address
W8 Registers
W9
W10
W11
W12
W13
W14 Frame Pointer
W15 Stack Pointer 0
Stack Pointer Limit

SPLIM 0
Value Register
22 0
PC 0 Program Counter
7 0
TBLPAG Table Memory Page
Address Register
7 0
Program Space Visibility
PSVPAG Page Address Register
15 0
Repeat Loop Counter
RCOUNT Register
15 SRH SRL 0
IPL
— — — — — — — DC
2 1 0
RA N OV Z C ALU STATUS Register (SR)
15 0
— — — — — — — — — — — — IPL3 PSV — — CPU Control Register (CORCON)
Registers or bits shadowed for PUSH.S and POP.S instructions.

3.2 CPU Control Registers
REGISTER 3-1: SR: ALU STATUS REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — DC
bit 15 bit 8
R/W-0(1) R/W-0(1) R/W-0(1) R-0 R/W-0 R/W-0 R/W-0 R/W-0

(2) (2)
IPL2 IPL1 IPL0(2) RA N OV Z C
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-9 Unimplemented: Read as ‘0’

bit 8 DC: ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th or 8th low-order bit of the result has occurred
bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(1,2)
111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110 = CPU Interrupt Priority Level is 6 (14)
bit 4 RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
bit 3 N: ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2 OV: ALU Overflow bit
1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation
0 = No overflow has occurred
bit 1 Z: ALU Zero bit
1 = An operation which effects the Z bit has set it at some time in the past
0 = The most recent operation which effects the Z bit has cleared it (i.e., a non-zero result)
bit 0 C: ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
2: The IPL Status bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority
Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.

REGISTER 3-2: CORCON: CPU CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0

— — — — IPL3(1) PSV — —
bit 7 bit 0
Legend: C = Clearable bit


bit 3 IPL3: CPU Interrupt Priority Level Status bit(1)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
bit 2 PSV: Program Space Visibility in Data Space Enable bit
1 = Program space is visible in data space
0 = Program space is not visible in data space
Note 1: User interrupts are disabled when IPL3 = 1.
3.3 Arithmetic Logic Unit (ALU) The PIC24F CPU incorporates hardware support for
both multiplication and division. This includes a
The PIC24F ALU is 16 bits wide, and is capable of addi- dedicated hardware multiplier and support hardware
tion, subtraction, bit shifts and logic operations. Unless for 16-bit divisor division.
otherwise mentioned, arithmetic operations are 2’s
complement in nature. Depending on the operation, the 3.3.1 MULTIPLIER
ALU may affect the values of the Carry (C), Zero (Z),
The ALU contains a high-speed, 17-bit x 17-bit
Negative (N), Overflow (OV) and Digit Carry (DC)
multiplier. It supports unsigned, signed or mixed sign
Status bits in the SR register. The C and DC Status bits
operation in several multiplication modes:
operate as Borrow and Digit Borrow bits, respectively,
for subtraction operations. 1. 16-bit x 16-bit signed
The ALU can perform 8-bit or 16-bit operations, 2. 16-bit x 16-bit unsigned
depending on the mode of the instruction that is used. 3. 16-bit signed x 5-bit (literal) unsigned
Data for the ALU operation can come from the W 4. 16-bit unsigned x 16-bit unsigned
register array, or data memory, depending on the 5. 16-bit unsigned x 5-bit (literal) unsigned
addressing mode of the instruction. Likewise, output
6. 16-bit unsigned x 16-bit signed
data from the ALU can be written to the W register array
or a data memory location. 7. 8-bit unsigned x 8-bit unsigned

3.3.2 DIVIDER 3.3.3 MULTI-BIT SHIFT SUPPORT
The divide block supports 32-bit/16-bit and 16-bit/16-bit The PIC24F ALU supports both single bit and
signed and unsigned integer divide operations with the single-cycle, multi-bit arithmetic and logic shifts.
following data sizes: Multi-bit shifts are implemented using a shifter block,
1. 32-bit signed/16-bit signed divide capable of performing up to a 15-bit arithmetic right
shift, or up to a 15-bit left shift, in a single cycle. All
2. 32-bit unsigned/16-bit unsigned divide
multi-bit shift instructions only support Register Direct
3. 16-bit signed/16-bit signed divide Addressing for both the operand source and result
4. 16-bit unsigned/16-bit unsigned divide destination.
The quotient for all divide instructions ends up in W0 A full summary of instructions that use the shift
and the remainder in W1. Sixteen-bit signed and operation is provided below in Table 3-2.
unsigned DIV instructions can specify any W register
for both the 16-bit divisor (Wn), and any W register
(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.
The divide algorithm takes one cycle per bit of divisor,
so both 32-bit/16-bit and 16-bit/16-bit instructions take
the same number of cycles to execute.
TABLE 3-2: INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION
Instruction Description
ASR Arithmetic shift right source register by one or more bits.
SL Shift left source register by one or more bits.
LSR Logical shift right source register by one or more bits.

4.0 MEMORY ORGANIZATION from either the 23-bit Program Counter (PC) during pro-
gram execution, or from table operation or data space
As Harvard architecture devices, PIC24F micro- remapping, as described in Section 4.3 “Interfacing
controllers feature separate program and data memory Program and Data Memory Spaces”.
spaces and buses. This architecture also allows the
User access to the program memory space is restricted
direct access of program memory from the data space
to the lower half of the address range (000000h to
during code execution.
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations which use TBLPAG<7> to permit access to
4.1 Program Address Space the Configuration bits and Device ID sections of the
The program address memory space of the configuration memory space.
PIC24FJ64GA004 family devices is 4M instructions. Memory maps for the PIC24FJ64GA004 family of
The space is addressable by a 24-bit value derived devices are shown in Figure 4-1.
FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ64GA004 FAMILY DEVICES
PIC24FJ16GA PIC24FJ32GA PIC24FJ48GA PIC24FJ64GA

GOTO Instruction GOTO Instruction GOTO Instruction GOTO Instruction 000000h
Reset Address Reset Address Reset Address Reset Address 000002h
000004h
Interrupt Vector Table Interrupt Vector Table Interrupt Vector Table Interrupt Vector Table
0000FEh
Reserved Reserved Reserved Reserved 000100h
Alternate Vector Table Alternate Vector Table 000104h
Alternate Vector Table Alternate Vector Table
0001FEh
User Flash 000200h
Program Memory
(5.5K instructions)
Flash Config Words 002BFEh
User Flash
Program Memory 002C00h
User Memory Space
(11K instructions) User Flash

Program Memory
(16K instructions) User Flash
Program Memory
(22K instructions)
Flash Config Words 0057FEh

005800h
Flash Config Words 0083FEh
008400h
Flash Config Words 00ABFEh

Unimplemented Unimplemented 00AC00h
Read ‘0’ Read ‘0’ Unimplemented
Read ‘0’ Unimplemented
Read ‘0’
7FFFFFh
800000h
Reserved Reserved Reserved Reserved

Configuration Memory Space
F7FFFEh
F80000h
Device Config Registers Device Config Registers Device Config Registers Device Config Registers
F8000Eh
F80010h
Reserved Reserved Reserved Reserved
FEFFFEh
DEVID (2) FF0000h
DEVID (2) DEVID (2) DEVID (2)
FFFFFFh
Note: Memory areas are not shown to scale.

4.1.1 PROGRAM MEMORY 4.1.3 FLASH CONFIGURATION WORDS
ORGANIZATION In PIC24FJ64GA004 family devices, the top two words
The program memory space is organized in of on-chip program memory are reserved for configura-
word-addressable blocks. Although it is treated as tion information. On device Reset, the configuration
24 bits wide, it is more appropriate to think of each information is copied into the appropriate Configuration
address of the program memory as a lower and upper registers. The addresses of the Flash Configuration
word, with the upper byte of the upper word being Word for devices in the PIC24FJ64GA004 family are
unimplemented. The lower word always has an even shown in Table 4-1. Their location in the memory map
address, while the upper word has an odd address is shown with the other memory vectors in Figure 4-1.
(Figure 4-2). The Configuration Words in program memory are a
Program memory addresses are always word-aligned compact format. The actual Configuration bits are
on the lower word, and addresses are incremented or mapped in several different registers in the configuration
decremented by two during code execution. This memory space. Their order in the Flash Configuration
arrangement also provides compatibility with data Words does not reflect a corresponding arrangement in
memory space addressing and makes it possible to the configuration space. Additional details on the device
access data in the program memory space. Configuration Words are provided in Section 24.1
“Configuration Bits”.
4.1.2 HARD MEMORY VECTORS
All PIC24F devices reserve the addresses between TABLE 4-1: FLASH CONFIGURATION
00000h and 000200h for hard-coded program execu- WORDS FOR PIC24FJ64GA004
tion vectors. A hardware Reset vector is provided to FAMILY DEVICES
redirect code execution from the default value of the
Program Configuration
PC on device Reset to the actual start of code. A GOTO
Device Memory Word
instruction is programmed by the user at 000000h with
(K words) Addresses
the actual address for the start of code at 000002h.
PIC24F devices also have two Interrupt Vector Tables 002BFCh:
PIC24FJ16GA 5.5
(IVT), located from 000004h to 0000FFh and 000100h 002BFEh
to 0001FFh. These vector tables allow each of the 0057FCh:
PIC24FJ32GA 11
many device interrupt sources to be handled by sepa- 0057FEh
rate ISRs. A more detailed discussion of the Interrupt 0083FCh:
Vector Tables is provided in Section 7.1 “Interrupt PIC24FJ48GA 16
0083FEh
Vector Table”.
00ABFCh:
PIC24FJ64GA 22
00ABFEh
FIGURE 4-2: PROGRAM MEMORY ORGANIZATION
msw most significant word least significant word PC Address

Address (lsw Address)
23 16 8 0
000001h 00000000 000000h
000003h 00000000 000002h
000005h 00000000 000004h
000007h 00000000 000006h
Program Memory Instruction Width

‘Phantom’ Byte
(read as ‘0’)

4.2 Data Address Space PIC24FJ64GA004 family devices implement a total of
8 Kbytes of data memory. Should an EA point to a
The PIC24F core has a separate, 16-bit wide data mem- location outside of this area, an all zero word or byte will
ory space, addressable as a single linear range. The be returned.
data space is accessed using two Address Generation
Units (AGUs), one each for read and write operations. 4.2.1 DATA SPACE WIDTH
The data space memory map is shown in Figure 4-3.
The data memory space is organized in
All Effective Addresses (EAs) in the data memory space byte-addressable, 16-bit wide blocks. Data is aligned
are 16 bits wide and point to bytes within the data space. in data memory and registers as 16-bit words, but all
This gives a data space address range of 64 Kbytes or data space EAs resolve to bytes. The Least Significant
32K words. The lower half of the data memory space Bytes (LSBs) of each word have even addresses, while
(that is, when EA<15> = 0) is used for implemented the Most Significant Bytes (MSBs) have odd
memory addresses, while the upper half (EA<15> = 1) is addresses.
reserved for the Program Space Visibility (PSV) area
(see Section 4.3.3 “Reading Data From Program
Memory Using Program Space Visibility”).
FIGURE 4-3: DATA SPACE MEMORY MAP FOR PIC24FJ64GA004 FAMILY DEVICES(1)
MSB LSB
Address MSB LSB Address
0001h 0000h SFR
SFR Space
07FFh 07FEh Space
0801h 0800h
Near
Data Space
Data RAM
Implemented
Data RAM
1FFFh 1FFEh
2001h 2000h
27FFh(2) 27FEh(2)
2801h 2800h
Unimplemented
Read as ‘0’
7FFFh 7FFFh
8001h 8000h
Program Space
Visibility Area
FFFFh FFFEh
Note 1: Data memory areas are not shown to scale.

2: Upper memory limit for PIC24FJ16GAXXX devices is 17FFh.

4.2.2 DATA MEMORY ORGANIZATION A Sign-Extend (SE) instruction is provided to allow
AND ALIGNMENT users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
To maintain backward compatibility with PIC® devices
can clear the MSB of any W register by executing a
and improve data space memory usage efficiency, the
Zero-Extend (ZE) instruction on the appropriate
PIC24F instruction set supports both word and byte
address.
operations. As a consequence of byte accessibility, all
Effective Address (EA) calculations are internally scaled Although most instructions are capable of operating on
to step through word-aligned memory. For example, the word or byte data sizes, it should be noted that some
core recognizes that Post-Modified Register Indirect instructions operate only on words.
Addressing mode [Ws++] will result in a value of Ws + 1
for byte operations and Ws + 2 for word operations. 4.2.3 NEAR DATA SPACE
Data byte reads will read the complete word which con- The 8-Kbyte area between 0000h and 1FFFh is
tains the byte, using the LSb of any EA to determine referred to as the Near Data Space. Locations in this
which byte to select. The selected byte is placed onto space are directly addressable via a 13-bit absolute
the LSB of the data path. That is, data memory and reg- address field within all memory direct instructions. The
isters are organized as two parallel, byte-wide entities remainder of the data space is addressable indirectly.
with shared (word) address decode but separate write Additionally, the whole data space is addressable using
lines. Data byte writes only write to the corresponding MOV instructions, which support Memory Direct
side of the array or register which matches the byte Addressing with a 16-bit address field.
address.
4.2.4 SFR SPACE
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so The first 2 Kbytes of the Near Data Space, from 0000h
care must be taken when mixing byte and word opera- to 07FFh, are primarily occupied with Special Function
tions, or translating from 8-bit MCU code. If a Registers (SFRs). These are used by the PIC24F core
misaligned read or write is attempted, an address error and peripheral modules for controlling the operation of
trap will be generated. If the error occurred on a read, the device.
the instruction underway is completed; if it occurred on SFRs are distributed among the modules that they
a write, the instruction will be executed but the write will control and are generally grouped together by module.
not occur. In either case, a trap is then executed, allow- Much of the SFR space contains unused addresses;
ing the system and/or user to examine the machine these are read as ‘0’. A diagram of the SFR space,
state prior to execution of the address Fault. showing where SFRs are actually implemented, is
All byte loads into any W register are loaded into the shown in Table 4-2. Each implemented area indicates
Least Significant Byte. The Most Significant Byte is not a 32-byte region where at least one address is imple-
modified. mented as an SFR. A complete listing of implemented
SFRs, including their addresses, is shown in Tables 4-3
through 4-24.
TABLE 4-2: IMPLEMENTED REGIONS OF SFR DATA SPACE

SFR Space Address
xx00 xx20 xx40 xx60 xx80 xxA0 xxC0 xxE0

000h Core ICN Interrupts —
100h Timers Capture — Compare — — —
200h I2C™ UART SPI — — I/O
300h A/D — — — — — —
400h — — — — — — — —
500h — — — — — — — —
600h PMP RTC/Comp CRC — PPS
700h — — System NVM/PMD — — — —
Legend: — = No implemented SFRs in this block

 2010-2013 Microchip Technology Inc.
TABLE 4-3: CPU CORE REGISTERS MAP

File All
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Resets
WREG0 0000 Working Register 0 0000

WREG5 000A Working Register 5 0000
WREG6 000C Working Register 6 0000
WREG7 000E Working Register 7 0000
WREG13 001A Working Register 13 0000
WREG14 001C Working Register 14 0000
WREG15 001E Working Register 15 0800
SPLIM 0020 Stack Pointer Limit Value Register xxxx
PCL 002E Program Counter Low Byte Register 0000
PCH 0030 — — — — — — — — Program Counter Register High Byte 0000
TBLPAG 0032 — — — — — — — — Table Memory Page Address Register 0000
PSVPAG 0034 — — — — — — — — Program Space Visibility Page Address Register 0000
RCOUNT 0036 Repeat Loop Counter Register xxxx
SR 0042 — — — — — — — DC IPL2 IPL1 IPL0 RA N OV Z C 0000
CORCON 0044 — — — — — — — — — — — — IPL3 PSV — — 0000
DISICNT 0052 — — Disable Interrupts Counter Register xxxx
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-4: ICN REGISTER MAP

File All
Name Resets
DS39881E-page 33
CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE(1) CN9IE(1) CN8IE(1) CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000
(1) (1) (1)
CNEN2 0062 — CN30IE CN29IE CN28IE CN27IE CN26IE CN25IE CN24IE CN23IE CN22IE CN21IE CN20IE(1) CN19IE(1) CN18IE(1) CN17IE(1) CN16IE 0000
CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE(1) CN9PUE(1) CN8PUE(1) CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000
CNPU2 006A — CN30PUE CN29PUE CN28PUE(1) CN27PUE CN26PUE(1) CN25PUE(1) CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE(1) CN19PUE(1) CN18PUE(1) CN17PUE(1) CN16PUE 0000
Note 1: These bits are not available on 28-pin devices; read as ‘0’.
DS39881E-page 34
TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP
File All
Name Resets
INTCON1 0080 NSTDIS — — — — — — — — — — MATHERR ADDRERR STKERR OSCFAIL — 0000

INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000
IFS0 0084 — — AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000
IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF — — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000
IFS2 0088 — — PMPIF — — — OC5IF — IC5IF IC4IF IC3IF — — — SPI2IF SPF2IF 0000
IFS3 008A — RTCIF — — — — — — — — — — — MI2C2IF SI2C2IF — 0000
IFS4 008C — — — — — — — LVDIF — — — — CRCIF U2ERIF U1ERIF — 0000
IEC0 0094 — — AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000
IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE — — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000
IEC2 0098 — — PMPIE — — — OC5IE — IC5IE IC4IE IC3IE — — — SPI2IE SPF2IE 0000
IEC3 009A — RTCIE — — — — — — — — — — — MI2C2IE SI2C2IE — 0000
IEC4 009C — — — — — — — LVDIE — — — — CRCIE U2ERIE U1ERIE — 0000
IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 4444
IPC1 00A6 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — — — — 4444
IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0 4444
IPC3 00AA — — — — — — — — — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 4444
IPC4 00AC — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 — MI2C1P2 MI2C1P1 MI2C1P0 — SI2C1P2 SI2C1P1 SI2C1P0 4444
IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0 4444
IPC6 00B0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 — OC3IP2 OC3IP1 OC3IP0 — — — — 4444
IPC7 00B2 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 4444
IPC8 00B4 — — — — — — — — — SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0 4444
IPC9 00B6 — IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0 — IC3IP2 IC3IP1 IC3IP0 — — — — 4444
IPC10 00B8 — — — — — — — — — OC5IP2 OC5IP1 OC5IP0 — — — — 4444
IPC11 00BA — — — — — — — — — PMPIP2 PMPIP1 PMPIP0 — — — — 4444
IPC12 00BC — — — — — MI2C2P2 MI2C2P1 MI2C2P0 — SI2C2P2 SI2C2P1 SI2C2P0 — — — — 4444

IPC15 00C2 — — — — — RTCIP2 RTCIP1 RTCIP0 — — — — — — — — 4444
IPC16 00C4 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — 4444
IPC18 00C8 — — — — — — — — — — — — — LVDIP2 LVDIP1 LVDIP0 4444
INTTREG 00E0 CPUIRQ — VHOLD — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000
TABLE 4-6: TIMER REGISTER MAP

All
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Resets
TMR1 0100 Timer1 Register 0000

PR1 0102 Timer1 Period Register FFFF
T1CON 0104 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000
TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) 0000
TMR3 010A Timer3 Register 0000
PR2 010C Timer2 Period Register FFFF
PR3 010E Timer3 Period Register FFFF
T2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000
T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000
TMR5HLD 0116 Timer5 Holding Register (for 32-bit operations only) 0000
PR4 011A Timer4 Period Register FFFF
PR5 011C Timer5 Period Register FFFF
T4CON 011E TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000
T5CON 0120 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000
TABLE 4-7: INPUT CAPTURE REGISTER MAP

File All
Name Resets
IC1BUF 0140 Input Capture 1 Register FFFF

IC1CON 0142 — — ICSIDL — — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000
IC3CON 014A — — ICSIDL — — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000
IC4BUF 014C Input Capture 4 Register FFFF
DS39881E-page 35
IC4CON 014E — — ICSIDL — — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000
DS39881E-page 36
TABLE 4-8: OUTPUT COMPARE REGISTER MAP
File All
Name Resets
OC1RS 0180 Output Compare 1 Secondary Register FFFF

OC1R 0182 Output Compare 1 Register FFFF
OC1CON 0184 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000
OC2CON 018A — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000
OC3RS 018C Output Compare 3 Secondary Register FFFF
OC3R 018E Output Compare 3 Register FFFF
OC5R 019A Output Compare 5 Register FFFF
OC5CON 019C — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000
TABLE 4-9: I2C™ REGISTER MAP

File All
Name Resets
I2C1RCV 0200 — — — — — — — — I2C1 Receive Register 0000

I2C1TRN 0202 — — — — — — — — I2C1 Transmit Register 00FF
I2C1BRG 0204 — — — — — — — Baud Rate Generator Register 1 0000
I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000
I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000
I2C1ADD 020A — — — — — — I2C1 Address Register 0000
I2C1MSK 020C — — — — — — AMSK9 AMSK8 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 0000
I2C2RCV 0210 — — — — — — — — I2C2 Receive Register 0000
I2C2TRN 0212 — — — — — — — — I2C2 Transmit Register 00FF
I2C2BRG 0214 — — — — — — — Baud Rate Generator Register 2 0000
I2C2CON 0216 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000
I2C2STAT 0218 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000
I2C2ADD 021A — — — — — — I2C2 Address Register 0000
I2C2MSK 021C — — — — — — AMSK9 AMSK8 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 0000
TABLE 4-10: UART REGISTER MAP

File All
Name Resets
U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000
U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110
U1TXREG 0224 — — — — — — — UTX8 UTX7 UTX6 UTX5 UTX4 UTX3 UTX2 UTX1 UTX0 0000
U1RXREG 0226 — — — — — — — URX8 URX7 URX6 URX5 URX4 URX3 URX2 URX1 URX0 0000
U1BRG 0228 Baud Rate Generator Prescaler Register 0000
U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000
U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110
U2TXREG 0234 — — — — — — — UTX8 UTX7 UTX6 UTX5 UTX4 UTX3 UTX2 UTX1 UTX0 0000
U2RXREG 0236 — — — — — — — URX8 URX7 URX6 URX5 URX4 URX3 URX2 URX1 URX0 0000
U2BRG 0238 Baud Rate Generator Prescaler 0000
TABLE 4-11: SPI REGISTER MAP
File All
Name Resets
SPI1STAT 0240 SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000
SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000
SPI1CON2 0244 FRMEN SPIFSD SPIFPOL — — — — — — — — — — — SPIFE SPIBEN 0000
SPI1BUF 0248 SPI1 Transmit/Receive Buffer 0000
SPI2STAT 0260 SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000
SPI2CON1 0262 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000
SPI2CON2 0264 FRMEN SPIFSD SPIFPOL — — — — — — — — — — — SPIFE SPIBEN 0000
SPI2BUF 0268 SPI2 Transmit/Receive Buffer 0000
DS39881E-page 37
DS39881E-page 38
TABLE 4-12: PORTA REGISTER MAP
File All
Name Resets
TRISA 02C0 — — — — — TRISA10(1) TRISA9(1) TRISA8(1) TRISA7(1) — — TRISA4 TRISA3(2) TRISA2(3) TRISA1 TRISA0 079F
PORTA 02C2 — — — — — RA10(1) RA9(1) RA8(1) RA7(1) — — RA4 RA3(2) RA2(3) RA1 RA0 0000
LATA 02C4 — — — — — LATA10(1) LATA9(1) LATA8(1) LATA7(1) — — LATA4 LATA3(2) LATA2(3) LATA1 LATA0 0000
ODCA 02C6 — — — — — ODA10(1) ODA9(1) ODA8(1) ODA7(1) — — ODA4 ODA3(2) ODA2(3) ODA1 ODA0 0000
2: These bits are only available when the primary oscillator is disabled (POSCMD<1:0> = 00); otherwise, read as ‘0’.
3: These bits are only available when the primary oscillator is disabled or EC mode is selected (POSCMD<1:0> = 00 or 11) and CLKO is disabled (OSCIOFNC = 0); otherwise, read as ‘0’.
TABLE 4-13: PORTB REGISTER MAP

File All
Name Resets
TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF
PORTB 02CA RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 0000
LATB 02CC LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0000
ODCB 02CE ODB15 ODB14 ODB13 ODB12 ODB11 ODB10 ODB9 ODB8 ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 0000
TABLE 4-14: PORTC REGISTER MAP

File All
Name Resets
TRISC(1) 02D0 — — — — — — TRISC9 TRISC8 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 03FF
PORTC(1) 02D2 — — — — — — RC9 RC8 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 0000
LATC(1) 02D4 — — — — — — LATC9 LATC8 LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 0000
ODCC(1) 02D6 — — — — — — ODC9 OSC8 ODC7 ODC6 ODC5 ODC4 ODC3 ODC2 ODC1 ODC0
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.Bits are not available on 28-pin devices; read as ‘0’.
TABLE 4-15: PAD CONFIGURATION REGISTER MAP

File All
Name Resets
PADCFG1 02FC — — — — — — — — — — — — — — RTSECSEL PMPTTL 0000

TABLE 4-16: A/D REGISTER MAP

File All
Name Resets
ADC1BUF0 0300 A/D Data Buffer 0 xxxx

ADC1BUF5 030A A/D Data Buffer 5 xxxx
ADC1BUF6 030C A/D Data Buffer 6 xxxx
ADC1BUF7 030E A/D Data Buffer 7 xxxx
ADC1BUFA 0314 A/D Data Buffer 10 xxxx
ADC1BUFB 0316 A/D Data Buffer 11 xxxx
ADC1BUFC 0318 A/D Data Buffer 12 xxxx
ADC1BUFD 031A A/D Data Buffer 13 xxxx
ADC1BUFE 031C A/D Data Buffer 14 xxxx
ADC1BUFF 031E A/D Data Buffer 15 xxxx
AD1CON1 0320 ADON — ADSIDL — — — FORM1 FORM0 SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE 0000
AD1CON2 0322 VCFG2 VCFG1 VCFG0 — — CSCNA — — BUFS — SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS 0000
AD1CON3 0324 ADRC — — SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 0000
AD1CHS 0328 CH0NB — — — CH0SB3 CH0SB2 CH0SB1 CH0SB0 CH0NA — — — CH0SA3 CH0SA2 CH0SA1 CH0SA0 0000
AD1PCFG 032C PCFG15 — — PCFG12 PCFG11 PCFG10 PCFG9 PCFG8(1) PCFG7(1) PCFG6(1) PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000
AD1CSSL 0330 CSSL15 — — CSSL12 CSSL11 CSSL10 CSSL9 CSSL8(1) CSSL7(1) CSSL6(1) CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000
DS39881E-page 39
TABLE 4-17: PARALLEL MASTER/SLAVE PORT REGISTER MAP
DS39881E-page 40
File All
Name Resets
PMCON 0600 PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN CSF1 CSF0 ALP — CS1P BEP WRSP RDSP 0000
PMMODE 0602 BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0 WAITE1 WAITE0 0000
PMADDR 0604 — CS1 — — — ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 0000
PMDOUT1 Parallel Port Data Out Register 1 (Buffers 0 and 1) 0000
PMDOUT2 0606 Parallel Port Data Out Register 2 (Buffers 2 and 3) 0000
PMDIN1 0608 Parallel Port Data In Register 1 (Buffers 0 and 1) 0000
PMDIN2 060A Parallel Port Data In Register 2 (Buffers 2 and 3) 0000
PMAEN 060C — PTEN14 — — — PTEN10 PTEN9 PTEN8 PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 0000
PMSTAT 060E IBF IBOV — — IB3F IB2F IB1F IB0F OBE OBUF — — OB3E OB2E OB1E OB0E 0000
TABLE 4-18: REAL-TIME CLOCK AND CALENDAR REGISTER MAP

File All
Name Resets
ALRMVAL 0620 Alarm Value Register Window Based on ALRMPTR<1:0> xxxx

ALCFGRPT 0622 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000
RTCVAL 0624 RTCC Value Register Window Based on RTCPTR<1:0> xxxx
RCFGCAL 0626 RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 0000
TABLE 4-19: DUAL COMPARATOR REGISTER MAP

File All
Name Resets
CMCON 0630 CMIDL — C2EVT C1EVT C2EN C1EN C2OUTEN C1OUTEN C2OUT C1OUT C2INV C1INV C2NEG C2POS C1NEG C1POS 0000
CVRCON 0632 — — — — — — — — CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000
TABLE 4-20: CRC REGISTER MAP

File All
Name Resets
CRCCON 0640 — — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT — CRCGO PLEN3 PLEN2 PLEN1 PLEN0 0040
CRCXOR 0642 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 — 0000
CRCDAT 0644 CRC Data Input Register 0000
CRCWDAT 0646 CRC Result Register 0000
TABLE 4-21: PERIPHERAL PIN SELECT REGISTER MAP (PPS)

File All
Name Resets
RPINR0 0680 — — — INT1R4 INT1R3 INT1R2 INT1R1 INT1R0 — — — — — — — — 1F00

RPINR1 0682 — — — — — — — — — — — INT2R4 INT2R3 INT2R2 INT2R1 INT2R0 001F
RPINR3 0686 — — — T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0 — — — T2CKR4 T2CKR3 T2CKR2 T2CKR1 T2CKR0 1F1F
RPINR4 0688 — — — T5CKR4 T5CKR3 T5CKR2 T5CKR1 T5CKR0 — — — T4CKR4 T4CKR3 T4CKR2 T4CKR1 T4CKR0 1F1F
RPINR7 068E — — — IC2R4 IC2R3 IC2R2 IC2R1 IC2R0 — — — IC1R4 IC1R3 IC1R2 IC1R1 IC1R0 1F1F
RPINR8 0690 — — — IC4R4 IC4R3 IC4R2 IC4R1 IC4R0 — — — IC3R4 IC3R3 IC3R2 IC3R1 IC3R0 1F1F
RPINR9 0692 — — — — — — — — — — — IC5R4 IC5R3 IC5R2 IC5R1 IC5R0 001F
RPINR11 0696 — — — OCFBR4 OCFBR3 OCFBR2 OCFBR1 OCFBR0 — — — OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0 1F1F
RPINR18 06A4 — — — U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 — — — U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0 1F1F
RPINR19 06A6 — — — U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0 — — — U2RXR4 U2RXR3 U2RXR2 U2RXR1 U2RXR0 1F1F
RPINR20 06A8 — — — SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 — — — SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0 1F1F
RPINR21 06AA — — — — — — — — — — — SS1R4 SS1R3 SS1R2 SS1R1 SS1R0 001F
RPINR22 06AC — — — SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 — — — SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0 1F1F
RPINR23 06AE — — — — — — — — — — — SS2R4 SS2R3 SS2R2 SS2R1 SS2R0 001F
RPOR0 06C0 — — — RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 — — — RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 0000
RPOR5 06CA — — — RP11R4 RP11R3 RP11R2 RP11R1 RP11R0 — — — RP10R4 RP10R3 RP10R2 RP10R1 RP10R0 0000
RPOR6 06CC — — — RP13R4 RP13R3 RP13R2 RP13R1 RP13R0 — — — RP12R4 RP12R3 RP12R2 RP12R1 RP12R0 0000
RPOR7 06CE — — — RP15R4 RP15R3 RP15R2 RP15R1 RP15R0 — — — RP14R4 RP14R3 RP14R2 RP14R1 RP14R0 0000
RPOR8 06D0 — — — RP17R4(1) RP17R3(1) RP17R2(1) RP17R1(1) RP17R0(1) — — — RP16R4(1) RP16R3(1) RP16R2(1) RP16R1(1) RP16R0(1) 0000
Note 1: These bits are only available on 44-pin devices; otherwise, they read as ‘0’.
DS39881E-page 41
DS39881E-page 42
TABLE 4-22: CLOCK CONTROL REGISTER MAP
File All
Name Resets
RCON 0740 TRAPR IOPUWR — — — — CM PMSLP EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR (Note 1)
OSCCON 0742 — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK IOLOCK LOCK — CF — SOSCEN OSWEN (Note 2)
CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0 — — — — — — — — 3140
OSCTUN 0748 — — — — — — — — — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000
Note 1: RCON register Reset values are dependent on the type of Reset.
2: OSCCON register Reset values are dependent on configuration fuses and by the type of Reset.
TABLE 4-23: NVM REGISTER MAP

All
Resets
NVMCON 0760 WR WREN WRERR — — — — — — ERASE — — NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000(1)
NVMKEY 0766 — — — — — — — — NVMKEY<7:0> 0000
Note 1: Reset value shown is for a POR only. The value on other Reset states is dependent on the state of the memory write or erase operations at the time of Reset.
TABLE 4-24: PMD REGISTER MAP

All
Resets
PMD1 0770 T5MD T4MD T3MD T2MD T1MD — — — I2C1MD U2MD U1MD SPI2MD SPI1MD — — ADC1MD 0000
PMD2 0772 — — — IC5MD IC4MD IC3MD IC2MD IC1MD — — — OC5MD OC4MD OC3MD OC2MD OC1MD 0000
PMD3 0774 — — — — — CMPMD RTCCMD PMPMD CRCPMD — — — — — I2C2MD — 0000
4.2.5 SOFTWARE STACK 4.3 Interfacing Program and Data
In addition to its use as a working register, the W15 Memory Spaces
register in PIC24F devices is also used as a Software The PIC24F architecture uses a 24-bit wide program
Stack Pointer. The pointer always points to the first space and 16-bit wide data space. The architecture is
available free word and grows from lower to higher also a modified Harvard scheme, meaning that data
addresses. It pre-decrements for stack pops and can also be present in the program space. To use this
post-increments for stack pushes, as shown in data successfully, it must be accessed in a way that
Figure 4-4. Note that for a PC push during any CALL preserves the alignment of information in both spaces.
instruction, the MSB of the PC is zero-extended before
the push, ensuring that the MSB is always clear. Aside from normal execution, the PIC24F architecture
provides two methods by which program space can be
Note: A PC push during exception processing accessed during operation:
will concatenate the SRL register to the
• Using table instructions to access individual bytes
MSB of the PC prior to the push.
or words anywhere in the program space
The Stack Pointer Limit Value register (SPLIM), associ- • Remapping a portion of the program space into
ated with the Stack Pointer, sets an upper address the data space (Program Space Visibility)
boundary for the stack. SPLIM is uninitialized at Reset.
Table instructions allow an application to read or write
As is the case for the Stack Pointer, SPLIM<0> is
to small areas of the program memory. This makes the
forced to ‘0’ because all stack operations must be
method ideal for accessing data tables that need to be
word-aligned. Whenever an EA is generated using
updated from time to time. It also allows access to all
W15 as a source or destination pointer, the resulting
bytes of the program word. The remapping method
address is compared with the value in SPLIM. If the
allows an application to access a large block of data on
contents of the Stack Pointer (W15) and the SPLIM
a read-only basis, which is ideal for look-ups from a
register are equal, and a push operation is performed,
large table of static data. It can only access the least
a stack error trap will not occur. The stack error trap will
significant word of the program word.
occur on a subsequent push operation. Thus, for
example, if it is desirable to cause a stack error trap 4.3.1 ADDRESSING PROGRAM SPACE
when the stack grows beyond address 2000h in RAM,
initialize the SPLIM with the value, 1FFEh. Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
Similarly, a Stack Pointer underflow (stack error) trap is needed to create a 23-bit or 24-bit program address
generated when the Stack Pointer address is found to from 16-bit data registers. The solution depends on the
be less than 0800h. This prevents the stack from interface method to be used.
interfering with the Special Function Register (SFR)
space. For table operations, the 8-bit Table Memory Page
Address register (TBLPAG) is used to define a 32K word
A write to the SPLIM register should not be immediately region within the program space. This is concatenated
followed by an indirect read operation using W15. with a 16-bit EA to arrive at a full 24-bit program space
address. In this format, the Most Significant bit of
FIGURE 4-4: CALL STACK FRAME TBLPAG is used to determine if the operation occurs in
the user memory (TBLPAG<7> = 0) or the configuration
0000h 15 0 memory (TBLPAG<7> = 1).
For remapping operations, the 8-bit Program Space
Visibility Page Address register (PSVPAG) is used to
Stack Grows Towards
define a 16K word page in the program space. When

Higher Address
the Most Significant bit of the EA is ‘1’, PSVPAG is con-

PC<15:0> W15 (before CALL)
catenated with the lower 15 bits of the EA to form a
000000000 PC<22:16> 23-bit program space address. Unlike table operations,
<Free Word> W15 (after CALL)
this limits remapping operations strictly to the user
memory area.
POP : [--W15] Table 4-25 and Figure 4-5 show how the program EA is
PUSH : [W15++] created for table operations and remapping accesses
from the data EA. Here, P<23:0> refers to a program
space word, whereas D<15:0> refers to a data space
word.

TABLE 4-25: PROGRAM SPACE ADDRESS CONSTRUCTION
Access Program Space Address
Access Type
Space <23> <22:16> <15> <14:1> <0>
Instruction Access User 0 PC<22:1> 0
(Code Execution) 0xx xxxx xxxx xxxx xxxx xxx0
TBLRD/TBLWT User TBLPAG<7:0> Data EA<15:0>
(Byte/Word Read/Write) 0xxx xxxx xxxx xxxx xxxx xxxx
Configuration TBLPAG<7:0> Data EA<15:0>
1xxx xxxx xxxx xxxx xxxx xxxx
Program Space Visibility User 0 PSVPAG<7:0> Data EA<14:0>(1)
(Block Remap/Read) 0 xxxx xxxx xxx xxxx xxxx xxxx
Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is PSVPAG<0>.
FIGURE 4-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1) 0 Program Counter 0
23 Bits
EA 1/0
Table Operations(2) 1/0 TBLPAG
8 Bits 16 Bits
24 Bits
Select
1 EA 0
Program Space Visibility(1)
(Remapping)
0 PSVPAG
8 Bits 15 Bits
23 Bits
User/Configuration Byte Select

Space Select
Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word
alignment of data in the program and data spaces.
2: Table operations are not required to be word-aligned. Table read operations are permitted
in the configuration memory space.

4.3.2 DATA ACCESS FROM PROGRAM 2. TBLRDH (Table Read High): In Word mode, it
MEMORY USING TABLE maps the entire upper word of a program address
INSTRUCTIONS (P<23:16>) to a data address. Note that
D<15:8>, the ‘phantom’ byte, will always be ‘0’.
The TBLRDL and TBLWTL instructions offer a direct
In Byte mode, it maps the upper or lower byte of
method of reading or writing the lower word of any
the program word to D<7:0> of the data
address within the program space without going through
address, as above. Note that the data will
data space. The TBLRDH and TBLWTH instructions are
always be ‘0’ when the upper ‘phantom’ byte is
the only method to read or write the upper 8 bits of a
selected (Byte Select = 1).
program space word as data.
In a similar fashion, two table instructions, TBLWTH
The PC is incremented by two for each successive
and TBLWTL, are used to write individual bytes or
24-bit program word. This allows program memory
words to a program space address. The details of
addresses to directly map to data space addresses.
their operation are explained in Section 5.0 “Flash
Program memory can thus be regarded as two 16-bit
Program Memory”.
word-wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL For all table operations, the area of program memory
access the space which contains the least significant space to be accessed is determined by the Table
data word, and TBLRDH and TBLWTH access the space Memory Page Address register (TBLPAG). TBLPAG
which contains the upper data byte. covers the entire program memory space of the
device, including user and configuration spaces. When
Two table instructions are provided to move byte or
TBLPAG<7> = 0, the table page is located in the user
word-sized (16-bit) data to and from program space.
memory space. When TBLPAG<7> = 1, the page is
Both function as either byte or word operations.
located in configuration space.
1. TBLRDL (Table Read Low): In Word mode, it
maps the lower word of the program space Note: Only table read operations will execute in
location (P<15:0>) to a data address (D<15:0>). the configuration memory space, and only
then, in implemented areas, such as the
In Byte mode, either the upper or lower byte of
Device ID. Table write operations are not
the lower program word is mapped to the lower
allowed.
byte of a data address. The upper byte is
selected when byte select is ‘1’; the lower byte
is selected when it is ‘0’.
FIGURE 4-6: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

Program Space
TBLPAG
Data EA<15:0>
02
23 15 0
000000h 23 16 8 0
00000000
00000000
020000h
00000000
030000h
00000000
‘Phantom’ Byte
TBLRDH.B (Wn<0> = 0)
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
The address for the table operation is determined by the data EA

within the page defined by the TBLPAG register.
800000h
Only read operations are shown; write operations are also valid in
the user memory area.

4.3.3 READING DATA FROM PROGRAM 24-bit program word are used to contain the data. The
MEMORY USING PROGRAM SPACE upper 8 bits of any program space locations used as
VISIBILITY data should be programmed with ‘1111 1111’ or
‘0000 0000’ to force a NOP. This prevents possible
The upper 32 Kbytes of data space may optionally be issues should the area of code ever be accidentally
mapped into any 16K word page of the program space. executed.
This provides transparent access of stored constant
data from the data space without the need to use Note: PSV access is temporarily disabled during
special instructions (i.e., TBLRDL/H). table reads/writes.
Program space access through the data space occurs if For operations that use PSV and are executed outside
the Most Significant bit of the data space EA is ‘1’ and a REPEAT loop, the MOV and MOV.D instructions will
Program Space Visibility is enabled by setting the PSV require one instruction cycle in addition to the specified
bit in the CPU Control register (CORCON<2>). The execution time. All other instructions will require two
location of the program memory space to be mapped instruction cycles in addition to the specified execution
into the data space is determined by the Program Space time.
Visibility Page Address register (PSVPAG). This 8-bit
For operations that use PSV which are executed inside
register defines any one of 256 possible pages of
a REPEAT loop, there will be some instances that
16K words in program space. In effect, PSVPAG func-
require two instruction cycles in addition to the
tions as the upper 8 bits of the program memory
specified execution time of the instruction:
address, with the 15 bits of the EA functioning as the
lower bits. Note that by incrementing the PC by 2 for • Execution in the first iteration
each program memory word, the lower 15 bits of data • Execution in the last iteration
space addresses directly map to the lower 15 bits in the • Execution prior to exiting the loop due to an
corresponding program space addresses. interrupt
Data reads to this area add an additional cycle to the • Execution upon re-entering the loop after an
instruction being executed, since two program memory interrupt is serviced
fetches are required. Any other iteration of the REPEAT loop will allow the
Although each data space address, 8000h and higher, instruction accessing data, using PSV, to execute in a
maps directly into a corresponding program memory single cycle.
address (see Figure 4-7), only the lower 16 bits of the
FIGURE 4-7: PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> = 1 and EA<15> = 1:
Program Space Data Space

PSVPAG 23 15 0
000000h 0000h
02 Data EA<14:0>
010000h
018000h
The data in the page
designated by
PSVPAG is mapped
into the upper half of
the data memory 8000h
space....
PSV Area
...while the lower
15 bits of the EA
specify an exact
FFFFh address within the
PSV area. This corre-
sponds exactly to the
same lower 15 bits of
the actual program
800000h
space address.

5.0 FLASH PROGRAM MEMORY RTSP is accomplished using TBLRD (Table Read) and
TBLWT (Table Write) instructions. With RTSP, the user
Note: This data sheet summarizes the features of may write program memory data in blocks of 64 instruc-
this group of PIC24F devices. It is not tions (192 bytes) at a time and erase program memory
intended to be a comprehensive reference in blocks of 512 instructions (1536 bytes) at a time.
source. For more information, refer to the
“PIC24F Family Reference Manual”, 5.1 Table Instructions and Flash
“Program Memory” (DS39715). Programming
The PIC24FJ64GA004 family of devices contains inter- Regardless of the method used, all programming of
nal Flash program memory for storing and executing Flash memory is done with the table read and table
application code. The memory is readable, writable and write instructions. These allow direct read and write
erasable when operating with VDD over 2.25V. access to the program memory space from the data
Flash memory can be programmed in three ways: memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
• In-Circuit Serial Programming™ (ICSP™)
formed using the TBLPAG<7:0> bits and the Effective
• Run-Time Self-Programming (RTSP) Address (EA) from a W register, specified in the table
• Enhanced In-Circuit Serial Programming instruction, as shown in Figure 5-1.
(Enhanced ICSP)
The TBLRDL and the TBLWTL instructions are used to
ICSP allows a PIC24FJ64GA004 family device to be read or write to bits<15:0> of program memory.
serially programmed while in the end application circuit. TBLRDL and TBLWTL can access program memory in
This is simply done with two lines for the programming both Word and Byte modes.
clock and programming data (which are named PGCx
The TBLRDH and TBLWTH instructions are used to read
and PGDx, respectively), and three other lines for
or write to bits<23:16> of program memory. TBLRDH
power (VDD), ground (VSS) and Master Clear (MCLR).
and TBLWTH can also access program memory in Word
This allows customers to manufacture boards with
or Byte mode.
unprogrammed devices and then program the micro-
controller just before shipping the product. This also
allows the most recent firmware or a custom firmware
to be programmed.
FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS
24 Bits
Using
Program 0 Program Counter 0
Counter
Working Reg EA
Using 1/0 TBLPAG Reg

Table
Instruction
8 Bits 16 Bits
User/Configuration Byte
Space Select 24-Bit EA Select

5.2 RTSP Operation 5.3 Enhanced In-Circuit Serial
The PIC24F Flash program memory array is organized
Programming
into rows of 64 instructions or 192 bytes. RTSP allows Enhanced In-Circuit Serial Programming uses an
the user to erase blocks of eight rows (512 instructions) on-board bootloader, known as the Program Executive
at a time and to program one row at a time. It is also (PE), to manage the programming process. Using an
possible to program single words. SPI data frame format, the Program Executive can
The 8-row erase blocks and single row write blocks are erase, program and verify program memory. For more
edge-aligned, from the beginning of program memory, on information on Enhanced ICSP, see the device
boundaries of 1536 bytes and 192 bytes, respectively. programming specification.
When data is written to program memory using TBLWT
instructions, the data is not written directly to memory. 5.4 Control Registers
Instead, data written using table writes is stored in There are two SFRs used to read and write the
holding latches until the programming sequence is program Flash memory: NVMCON and NVMKEY.
executed.
The NVMCON register (Register 5-1) controls which
Any number of TBLWT instructions can be executed blocks are to be erased, which memory type is to be
and a write will be successfully performed. However, programmed and when the programming cycle starts.
64 TBLWT instructions are required to write the full row
of memory. NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
To ensure that no data is corrupted during a write, any the user must consecutively write 55h and AAh to the
unused addresses should be programmed with NVMKEY register. Refer to Section 5.5 “Programming
FFFFFFh. This is because the holding latches reset to Operations” for further details.
an unknown state, so if the addresses are left in the
Reset state, they may overwrite the locations on rows
5.5 Programming Operations
which were not rewritten.
The basic sequence for RTSP programming is to set up A complete programming sequence is necessary for
a Table Pointer, then do a series of TBLWT instructions programming or erasing the internal Flash in RTSP
to load the buffers. Programming is performed by mode. During a programming or erase operation, the
setting the control bits in the NVMCON register. processor stalls (waits) until the operation is finished.
Setting the WR bit (NVMCON<15>) starts the opera-
Data can be loaded in any order and the holding regis- tion and the WR bit is automatically cleared when the
ters can be written to multiple times before performing operation is finished.
a write operation. Subsequent writes, however, will
wipe out any previous writes. Configuration Word values are stored in the last two
locations of program memory. Performing a page erase
Note: Writing to a location multiple times without operation on the last page of program memory clears
erasing it is not recommended. these values and enables code protection. As a result,
All of the table write operations are single-word writes avoid performing page erase operations on the last
(2 instruction cycles), because only the buffers are writ- page of program memory.
ten. A programming cycle is required for programming
each row.

REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
WR WREN WRERR — — — — —
bit 15 bit 8
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

(1) (1) (1)
— ERASE — — NVMOP3 NVMOP2 NVMOP1 NVMOP0(1)
bit 7 bit 0
Legend: SO = Settable Only bit

bit 15 WR: Write Control bit

1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is
cleared by hardware once operation is complete
0 = Program or erase operation is complete and inactive
bit 14 WREN: Write Enable bit
1 = Enables Flash program/erase operations
0 = Inhibits Flash program/erase operations
bit 13 WRERR: Write Sequence Error Flag bit
1 = An improper program or erase sequence attempt or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0 = The program or erase operation completed normally
bit 6 ERASE: Erase/Program Enable bit
1 = Performs the erase operation specified by the NVMOP<3:0> bits on the next WR command
0 = Performs the program operation specified by the NVMOP<3:0> bits on the next WR command
bit 3-0 NVMOP<3:0>: NVM Operation Select bits(1)
1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)(2)
0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1)
0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0)
0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1)
Note 1: All other combinations of NVMOP<3:0> are unimplemented.

2: Available in ICSP™ mode only. Refer to the device programming specifications.

5.5.1 PROGRAMMING ALGORITHM FOR 4. Write the first 64 instructions from data RAM into
FLASH PROGRAM MEMORY the program memory buffers (see Example 5-1).
The user can program one row of Flash program memory 5. Write the program block to Flash memory:
at a time. To do this, it is necessary to erase the 8-row a) Set the NVMOPx bits to ‘0001’ to configure
erase block containing the desired row. The general for row programming. Clear the ERASE bit
process is: and set the WREN bit.
1. Read eight rows of program memory b) Write 55h to NVMKEY.
(512 instructions) and store in data RAM. c) Write AAh to NVMKEY.
2. Update the program data in RAM with the d) Set the WR bit. The programming cycle
desired new data. begins and the CPU stalls for the duration
3. Erase the block (see Example 5-1): of the write cycle. When the write to Flash
memory is done, the WR bit is cleared
a) Set the NVMOPx bits (NVMCON<3:0>) to
automatically.
‘0010’ to configure for block erase. Set the
ERASE (NVMCON<6>) and WREN 6. Repeat Steps 4 and 5, using the next available
(NVMCON<14>) bits. 64 instructions from the block in data RAM by
incrementing the value in TBLPAG, until all
b) Write the starting address of the block to be
512 instructions are written back to Flash
erased into the TBLPAG and W registers.
memory.
c) Write 55h to NVMKEY.
For protection against accidental operations, the write
d) Write AAh to NVMKEY.
initiate sequence for NVMKEY must be used to allow
e) Set the WR bit (NVMCON<15>). The erase any erase or program operation to proceed. After the
cycle begins and the CPU stalls for the dura- programming command has been executed, the user
tion of the erase cycle. When the erase is must wait for the programming time until programming
done, the WR bit is cleared automatically. is complete. The two instructions following the start of
the programming sequence should be NOPs, as shown
in Example 5-3.
EXAMPLE 5-1: ERASING A PROGRAM MEMORY BLOCK

; Set up NVMCON for block erase operation
MOV #0x4042, W0 ;
MOV W0, NVMCON ; Initialize NVMCON
; Init pointer to row to be ERASED
MOV #tblpage(PROG_ADDR), W0 ;
MOV W0, TBLPAG ; Initialize PM Page Boundary SFR
MOV #tbloffset(PROG_ADDR), W0 ; Initialize in-page EA[15:0] pointer
TBLWTL W0, [W0] ; Set base address of erase block
DISI #5 ; Block all interrupts with priority <7
; for next 5 instructions
MOV #0x55, W0
MOV W0, NVMKEY ; Write the 55 key
MOV #0xAA, W1 ;
MOV W1, NVMKEY ; Write the AA key
BSET NVMCON, #WR ; Start the erase sequence
NOP ; Insert two NOPs after the erase
NOP ; command is asserted

EXAMPLE 5-2: LOADING THE WRITE BUFFERS
; Set up NVMCON for row programming operations
MOV #0x4001, W0 ;
MOV W0, NVMCON ; Initialize NVMCON
; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
MOV #0x0000, W0 ;
MOV W0, TBLPAG ; Initialize PM Page Boundary SFR
MOV #0x6000, W0 ; An example program memory address
; Perform the TBLWT instructions to write the latches
; 0th_program_word
MOV #LOW_WORD_0, W2 ;
MOV #HIGH_BYTE_0, W3 ;
TBLWTL W2, [W0] ; Write PM low word into program latch
TBLWTH W3, [W0++] ; Write PM high byte into program latch
; 1st_program_word
; 2nd_program_word
•
•
•
; 63rd_program_word
TBLWTH W3, [W0] ; Write PM high byte into program latch
EXAMPLE 5-3: INITIATING A PROGRAMMING SEQUENCE

DISI #5 ; Block all interrupts with priority <7
; for next 5 instructions
MOV #0x55, W0
MOV W0, NVMKEY ; Write the 55 key
MOV #0xAA, W1 ;
MOV W1, NVMKEY ; Write the AA key
BSET NVMCON, #WR ; Start the erase sequence
NOP ; 2 NOPs required after setting WR
NOP ;
BTSC NVMCON, #15 ; Wait for the sequence to be completed
BRA $-2 ;

5.5.2 PROGRAMMING A SINGLE WORD instructions write the desired data into the write latches
OF FLASH PROGRAM MEMORY and specify the lower 16 bits of the program memory
address to write to. To configure the NVMCON register
If a Flash location has been erased, it can be pro-
for a word write, set the NVMOPx bits (NVMCON<3:0>)
grammed using table write instructions to write an
to ‘0011’. The write is performed by executing the unlock
instruction word (24-bit) into the write latch. The
sequence and setting the WR bit (see Example 5-4).
TBLPAG register is loaded with the 8 Most Significant
Bytes of the Flash address. The TBLWTL and TBLWTH
EXAMPLE 5-4: PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY

; Setup a pointer to data Program Memory
MOV #tblpage(PROG_ADDR), W0 ;
MOV W0, TBLPAG ;Initialize PM Page Boundary SFR
MOV #tbloffset(PROG_ADDR), W0 ;Initialize a register with program memory address
MOV #LOW_WORD_N, W2 ;
MOV #HIGH_BYTE_N, W3 ;
; Setup NVMCON for programming one word to data Program Memory

MOV #0x4003, W0 ;
MOV W0, NVMCON ; Set NVMOP bits to 0011
DISI #5 ; Disable interrupts while the KEY sequence is written

MOV #0x55, W0 ; Write the key sequence
MOV W0, NVMKEY
MOV #0xAA, W0
MOV W0, NVMKEY
BSET NVMCON, #WR ; Start the write cycle
NOP ; 2 NOPs required after setting WR
NOP ;

6.0 RESETS Any active source of Reset will make the SYSRST
signal active. Many registers associated with the CPU
Note: This data sheet summarizes the features of and peripherals are forced to a known Reset state.
this group of PIC24F devices. It is not Most registers are unaffected by a Reset; their status is
intended to be a comprehensive reference unknown on POR and unchanged by all other Resets.
“PIC24F Family Reference Manual”, Note: Refer to the specific peripheral or CPU
“Reset” (DS39712). section of this manual for register Reset
states.
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The All types of device Reset will set a corresponding status
following is a list of device Reset sources: bit in the RCON register to indicate the type of Reset
(see Register 6-1). A Power-on Reset will clear all bits
• POR: Power-on Reset except for the BOR and POR bits (RCON<1:0>) which
• MCLR: Pin Reset are set. The user may set or clear any bit at any time
• SWR: RESET Instruction during code execution. The RCON bits only serve as
• WDT: Watchdog Timer Reset status bits. Setting a particular Reset status bit in
• BOR: Brown-out Reset software will not cause a device Reset to occur.
• CM: Configuration Mismatch Reset The RCON register also has other bits associated with
• TRAPR: Trap Conflict Reset the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
• IOPUWR: Illegal Opcode Reset
of this manual.
• UWR: Uninitialized W Register Reset
A simplified block diagram of the Reset module is Note: The status bits in the RCON register
shown in Figure 6-1. should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM
RESET
Instruction
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
VDD Rise POR

Detect SYSRST
VDD
Brown-out BOR
Reset
Enable Voltage Regulator
Trap Conflict
Illegal Opcode
Configuration Mismatch
Uninitialized W Register

REGISTER 6-1: RCON: RESET CONTROL REGISTER(1)
R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
TRAPR IOPUWR — — — — CM PMSLP
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1

EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR
bit 7 bit 0
Legend:
bit 15 TRAPR: Trap Reset Flag bit

1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode or Uninitialized W register used as an
Address Pointer caused a Reset
0 = An illegal opcode or Uninitialized W register Reset has not occurred
bit 9 CM: Configuration Word Mismatch Reset Flag bit
1 = A Configuration Word Mismatch Reset has occurred
0 = A Configuration Word Mismatch Reset has not occurred
bit 8 PMSLP: Program Memory Power During Sleep bit
1 = Program memory bias voltage remains powered during Sleep
0 = Program memory bias voltage is powered down during Sleep and voltage regulator enters Standby
mode
bit 7 EXTR: External Reset (MCLR) Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
bit 6 SWR: Software Reset (Instruction) Flag bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
bit 5 SWDTEN: Software Enable/Disable of WDT bit(2)
1 = WDT is enabled
0 = WDT is disabled
bit 4 WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
bit 3 SLEEP: Wake from Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.

REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED)
bit 2 IDLE: Wake-up from Idle Flag bit
1 = Device has been in Idle mode
0 = Device has not been in Idle mode
bit 1 BOR: Brown-out Reset Flag bit
1 = A Brown-out Reset has occurred (note that BOR is also set after a Power-on Reset)
0 = A Brown-out Reset has not occurred
bit 0 POR: Power-on Reset Flag bit
1 = A Power-on Reset has occurred
0 = A Power-on Reset has not occurred
Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
TABLE 6-1: RESET FLAG BIT OPERATION

Flag Bit Setting Event Clearing Event
TRAPR (RCON<15>) Trap Conflict Event POR
IOPUWR (RCON<14>) Illegal Opcode or Uninitialized W Register Access POR
CM (RCON<9>) Configuration Mismatch Reset POR
EXTR (RCON<7>) MCLR Reset POR
SWR (RCON<6>) RESET Instruction POR
WDTO (RCON<4>) WDT Time-out PWRSAV Instruction, POR
SLEEP (RCON<3>) PWRSAV #SLEEP Instruction POR
IDLE (RCON<2>) PWRSAV #IDLE Instruction POR
BOR (RCON<1>) POR, BOR —
POR (RCON<0>) POR —
Note: All Reset flag bits may be set or cleared by the user software.

6.1 Clock Source Selection at Reset 6.2 Device Reset Times
If clock switching is enabled, the system clock source at The Reset times for various types of device Reset are
device Reset is chosen, as shown in Table 6-2. If clock summarized in Table 6-3. Note that the system Master
switching is disabled, the system clock source is always Reset Signal, SYSRST, is released after the POR and
selected according to the Oscillator Configuration bits. PWRT delay times expire.
Refer to Section 8.0 “Oscillator Configuration” for The time that the device actually begins to execute
further details. code will also depend on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
TABLE 6-2: OSCILLATOR SELECTION vs. the PLL lock time. The OST and PLL lock times occur
TYPE OF RESET (CLOCK in parallel with the applicable SYSRST delay times.
SWITCHING ENABLED) The FSCM delay determines the time at which the
Reset Type Clock Source Determinant FSCM begins to monitor the system clock source after
the SYSRST signal is released.
POR FNOSC<2:0> Configuration bits
BOR (CW2<10:8>)
MCLR COSC<2:0> Control bits

WDTO (OSCCON<14:12>)
SWR
TABLE 6-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS

System Clock
Reset Type Clock Source SYSRST Delay Notes
Delay
POR(6) EC TPOR + TPWRT + TRST — 1, 2, 7
FRC, FRCDIV TPOR + TPWRT + TRST TFRC 1, 2, 3, 7
LPRC TPOR + TPWRT + TRST TLPRC 1, 2, 3, 7
ECPLL TPOR + TPWRT + TRST TLOCK 1, 2, 4, 7
FRCPLL TPOR + TPWRT + TRST TFRC + TLOCK 1, 2, 3, 4, 7
XT, HS, SOSC TPOR + TPWRT + TRST TOST 1, 2, 5, 7
XTPLL, HSPLL TPOR + TPWRT + TRST TOST + TLOCK 1, 2, 4, 5, 7
BOR EC TPWRT + TRST — 2, 7
FRC, FRCDIV TPWRT + TRST TFRC 2, 3, 7
LPRC TPWRT + TRST TLPRC 2, 3, 7
ECPLL TPWRT + TRST TLOCK 2, 4, 7
FRCPLL TPWRT + TRST TFRC + TLOCK 2, 3, 4, 7
XT, HS, SOSC TPWRT + TRST TOST 2, 5, 7
XTPLL, HSPLL TPWRT + TRST TFRC + TLOCK 2, 3, 4, 7
All Others Any Clock TRST — 7
Note 1: TPOR = Power-on Reset delay.
2: TPWRT = 64 ms nominal if regulator is disabled (ENVREG tied to VSS).
3: TFRC and TLPRC = RC Oscillator Start-up Times.
4: TLOCK = PLL Lock Time.
5: TOST = Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing the
oscillator clock to the system.
6: If Two-Speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC,
and in such cases, FRC start-up time is valid.
7: TRST = Internal State Reset Timer

6.2.1 POR AND LONG OSCILLATOR 6.2.2.1 FSCM Delay for Crystal and PLL
START-UP TIMES Clock Sources
The oscillator start-up circuitry and its associated delay When the system clock source is provided by a crystal
timers are not linked to the device Reset delays that oscillator and/or the PLL, a small delay, TFSCM, will
occur at power-up. Some crystal circuits (especially automatically be inserted after the POR and PWRT
low-frequency crystals) will have a relatively long delay times. The FSCM will not begin to monitor the
start-up time. Therefore, one or more of the following system clock source until this delay expires. The FSCM
conditions is possible after SYSRST is released: delay time is nominally 100 s and provides additional
• The oscillator circuit has not begun to oscillate. time for the oscillator and/or PLL to stabilize. In most
cases, the FSCM delay will prevent an oscillator failure
• The Oscillator Start-up Timer has not expired (if a
trap at a device Reset when the PWRT is disabled.
crystal oscillator is used).
• The PLL has not achieved a lock (if PLL is used). 6.3 Special Function Register Reset
The device will not begin to execute code until a valid States
clock source has been released to the system. There-
Most of the Special Function Registers (SFRs) associ-
fore, the oscillator and PLL start-up delays must be
ated with the PIC24F CPU and peripherals are reset to a
considered when the Reset delay time must be known.
particular value at a device Reset. The SFRs are
6.2.2 FAIL-SAFE CLOCK MONITOR grouped by their peripheral or CPU function and their
Reset values are specified in each section of this manual.
(FSCM) AND DEVICE RESETS
The Reset value for each SFR does not depend on the
If the FSCM is enabled, it will begin to monitor the
type of Reset, with the exception of four registers. The
system clock source when SYSRST is released. If a
Reset value for the Reset Control register, RCON, will
valid clock source is not available at this time, the
depend on the type of device Reset. The Reset value
device will automatically switch to the FRC oscillator
for the Oscillator Control register, OSCCON, will
and the user can switch to the desired crystal oscillator
depend on the type of Reset and the programmed
in the Trap Service Routine.
values of the FNOSCx bits in the CW2 register (see
Table 6-2). The RCFGCAL and NVMCON registers are
only affected by a POR.

NOTES:

7.0 INTERRUPT CONTROLLER 7.1.1 ALTERNATE INTERRUPT VECTOR
TABLE
Note: This data sheet summarizes the features of
The Alternate Interrupt Vector Table (AIVT) is located
this group of PIC24F devices. It is not
after the IVT, as shown in Figure 7-1. Access to the AIVT
intended to be a comprehensive reference
is provided by the ALTIVT control bit (INTCON2<15>). If
the ALTIVT bit is set, all interrupt and exception
“PIC24F Family Reference Manual”,
processes will use the alternate vectors instead of the
“Interrupts” (DS39707).
default vectors. The alternate vectors are organized in
The PIC24F interrupt controller reduces the numerous the same manner as the default vectors.
peripheral interrupt request signals to a single interrupt The AIVT supports emulation and debugging efforts by
request signal to the PIC24F CPU. It has the following providing a means to switch between an application
features: and a support environment without requiring the inter-
• Up to 8 processor exceptions and software traps rupt vectors to be reprogrammed. This feature also
• 7 user-selectable priority levels enables switching between applications for evaluation
of different software algorithms at run time. If the AIVT
• Interrupt Vector Table (IVT) with up to 118 vectors
is not needed, the AIVT should be programmed with
• A unique vector for each interrupt or exception the same addresses used in the IVT.
source
• Fixed priority within a specified user priority level 7.2 Reset Sequence
• Alternate Interrupt Vector Table (AIVT) for debug
support A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
• Fixed interrupt entry and return latencies
The PIC24F devices clear their registers in response to
a Reset which forces the PC to zero. The micro-
7.1 Interrupt Vector Table controller then begins program execution at location,
The Interrupt Vector Table (IVT) is shown in Figure 7-1. 000000h. The user programs a GOTO instruction at the
The IVT resides in program memory, starting at location, Reset address, which redirects program execution to
000004h. The IVT contains 126 vectors, consisting of the appropriate start-up routine.
8 non-maskable trap vectors, plus up to 118 sources of Note: Any unimplemented or unused vector
interrupt. In general, each interrupt source has its own locations in the IVT and AIVT should be
vector. Each interrupt vector contains a 24-bit wide programmed with the address of a default
address. The value programmed into each interrupt vec- interrupt handler routine that contains a
tor location is the starting address of the associated RESET instruction.
Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority; this is linked to their position in the vector table.
All other things being equal, lower addresses have a
higher natural priority. For example, the interrupt asso-
ciated with Vector 0 will take priority over interrupts at
any other vector address.
PIC24FJ64GA004 family devices implement
non-maskable traps and unique interrupts. These are
summarized in Table 7-1 and Table 7-2.

FIGURE 7-1: PIC24F INTERRUPT VECTOR TABLE
Reset – GOTO Instruction 000000h

Reset – GOTO Address 000002h
Reserved 000004h
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0 000014h
Interrupt Vector 1
—
—
—
Interrupt Vector 52 00007Ch
Interrupt Vector Table (IVT)(1)
Interrupt Vector 53 00007Eh
Decreasing Natural Order Priority
—
—
—
Interrupt Vector 116 0000FCh
Interrupt Vector 117 0000FEh
Reserved 000100h
Reserved 000102h
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 1
—
—
— Alternate Interrupt Vector Table (AIVT)(1)
Interrupt Vector 52 00017Ch
Interrupt Vector 53 00017Eh
—
—
—
Interrupt Vector 116
Interrupt Vector 117 0001FEh
Start of Code 000200h
Note 1: See Table 7-2 for the interrupt vector list.
TABLE 7-1: TRAP VECTOR DETAILS

Vector Number IVT Address AIVT Address Trap Source
0 000004h 000104h Reserved
1 000006h 000106h Oscillator Failure
2 000008h 000108h Address Error
3 00000Ah 00010Ah Stack Error
4 00000Ch 00010Ch Math Error
5 00000Eh 00010Eh Reserved
6 000010h 000110h Reserved
7 000012h 0001172h Reserved

TABLE 7-2: IMPLEMENTED INTERRUPT VECTORS
Vector AIVT Interrupt Bit Locations
Interrupt Source IVT Address
Number Address Flag Enable Priority
ADC1 Conversion Done 13 00002Eh 00012Eh IFS0<13> IEC0<13> IPC3<6:4>

Comparator Event 18 000038h 000138h IFS1<2> IEC1<2> IPC4<10:8>
CRC Generator 67 00009Ah 00019Ah IFS4<3> IEC4<3> IPC16<14:12>
External Interrupt 0 0 000014h 000114h IFS0<0> IEC0<0> IPC0<2:0>
External Interrupt 1 20 00003Ch 00013Ch IFS1<4> IEC1<4> IPC5<2:0>
External Interrupt 2 29 00004Eh 00014Eh IFS1<13> IEC1<13> IPC7<6:4>
I2C1 Master Event 17 000036h 000136h IFS1<1> IEC1<1> IPC4<6:4>
I2C1 Slave Event 16 000034h 000034h IFS1<0> IEC1<0> IPC4<2:0>
I2C2 Master Event 50 000078h 000178h IFS3<2> IEC3<2> IPC12<10:8>
I2C2 Slave Event 49 000076h 000176h IFS3<1> IEC3<1> IPC12<6:4>
Input Capture 1 1 000016h 000116h IFS0<1> IEC0<1> IPC0<6:4>
Input Capture 2 5 00001Eh 00011Eh IFS0<5> IEC0<5> IPC1<6:4>
Input Capture 3 37 00005Eh 00015Eh IFS2<5> IEC2<5> IPC9<6:4>
Input Change Notification 19 00003Ah 00013Ah IFS1<3> IEC1<3> IPC4<14:12>
Output Compare 1 2 000018h 000118h IFS0<2> IEC0<2> IPC0<10:8>
Parallel Master Port 45 00006Eh 00016Eh IFS2<13> IEC2<13> IPC11<6:4>
Real-Time Clock/Calendar 62 000090h 000190h IFS3<14> IEC3<14> IPC15<10:8>
SPI1 Error 9 000026h 000126h IFS0<9> IEC0<9> IPC2<6:4>
SPI1 Event 10 000028h 000128h IFS0<10> IEC0<10> IPC2<10:8>
SPI2 Error 32 000054h 000154h IFS2<0> IEC0<0> IPC8<2:0>
SPI2 Event 33 000056h 000156h IFS2<1> IEC2<1> IPC8<6:4>
Timer1 3 00001Ah 00011Ah IFS0<3> IEC0<3> IPC0<14:12>
Timer2 7 000022h 000122h IFS0<7> IEC0<7> IPC1<14:12>
Timer3 8 000024h 000124h IFS0<8> IEC0<8> IPC2<2:0>
Timer4 27 00004Ah 00014Ah IFS1<11> IEC1<11> IPC6<14:12>
Timer5 28 00004Ch 00014Ch IFS1<12> IEC1<12> IPC7<2:0>
UART1 Error 65 000096h 000196h IFS4<1> IEC4<1> IPC16<6:4>
UART1 Receiver 11 00002Ah 00012Ah IFS0<11> IEC0<11> IPC2<14:12>
UART1 Transmitter 12 00002Ch 00012Ch IFS0<12> IEC0<12> IPC3<2:0>
UART2 Error 66 000098h 000198h IFS4<2> IEC4<2> IPC16<10:8>
UART2 Receiver 30 000050h 000150h IFS1<14> IEC1<14> IPC7<10:8>
UART2 Transmitter 31 000052h 000152h IFS1<15> IEC1<15> IPC7<14:12>
Low-Voltage Detect (LVD) 72 0000A4h 000124h IFS4<8> IEC4<8> IPC17<2:0>

7.3 Interrupt Control and Status The INTTREG register contains the associated inter-
Registers rupt vector number and the new CPU Interrupt Priority
Level, which are latched into the Vector Number
The PIC24FJ64GA004 family of devices implements a (VECNUM<6:0>) and the Interrupt Level (ILR<3:0>) bit
total of 29 registers for the interrupt controller: fields in the INTTREG register. The new Interrupt
• INTCON1 Priority Level is the priority of the pending interrupt.
• INTCON2 The interrupt sources are assigned to the IFSx, IECx
• IFS0 through IFS4 and IPCx registers in the same sequence that they are
listed in Table 7-2. For example, the INT0 (External
• IEC0 through IEC4
Interrupt 0) is shown as having a vector number and a
• IPC0 through IPC12, IPC15, IPC16 and IPC18 natural order priority of 0. Thus, the INT0IF status bit is
• INTTREG found in IFS0<0>, the INT0IE enable bit in IEC0<0>
Global interrupt control functions are controlled from and the INT0IP<2:0> priority bits in the first position of
INTCON1 and INTCON2. INTCON1 contains the Inter- IPC0 (IPC0<2:0>).
rupt Nesting Disable (NSTDIS) bit, as well as the Although they are not specifically part of the interrupt
control and status flags for the processor trap sources. control hardware, two of the CPU control registers con-
The INTCON2 register controls the external interrupt tain bits that control interrupt functionality. The ALU
request signal behavior and the use of the Alternate STATUS Register (SR) contains the IPL<2:0> bits
Interrupt Vector Table. (SR<7:5>). These indicate the current CPU Interrupt
The IFSx registers maintain all of the interrupt request Priority Level. The user may change the current CPU
flags. Each source of interrupt has a status bit which is priority level by writing to the IPLx bits.
set by the respective peripherals, or external signal, The CORCON register contains the IPL3 bit, which
and is cleared via software. together with IPL<2:0>, also indicates the current CPU
The IECx registers maintain all of the interrupt enable priority level. IPL3 is a read-only bit so that trap events
bits. These control bits are used to individually enable cannot be masked by the user software.
interrupts from the peripherals or external signals. All Interrupt registers are described in Register 7-1
The IPCx registers are used to set the Interrupt Priority through Register 7-31, in the following pages.
Level (IPL) for each source of interrupt. Each user
interrupt source can be assigned to one of eight priority
levels.

REGISTER 7-1: SR: ALU STATUS REGISTER (IN CPU)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — DC(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

IPL2(2,3) IPL1(2,3) IPL0(2,3) RA(1) N(1) OV(1) Z(1) C(1)
bit 7 bit 0
Legend:
bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3)

111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
Note 1: See Register 3-1 for the description of the remaining bit(s) that are not dedicated to interrupt control functions.
2: The IPLx bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt Priority Level.
The value in parentheses indicates the Interrupt Priority Level if IPL3 = 1.
3: The IPLx Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
REGISTER 7-2: CORCON: CPU CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0

— — — — IPL3(2) PSV(1) — —
bit 7 bit 0

bit 3 IPL3: CPU Interrupt Priority Level Status bit(2)

1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
Note 1: See Register 3-2 for the description of the remaining bit(s) that are not dedicated to interrupt control functions.
2: The IPL3 bit is concatenated with the IPL<2:0: bits (SR<7:5>) to form the CPU Interrupt priority Level.

REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
NSTDIS — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

— — — MATHERR ADDRERR STKERR OSCFAIL —
bit 7 bit 0
Legend:
bit 15 NSTDIS: Interrupt Nesting Disable bit

1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
bit 4 MATHERR: Arithmetic Error Trap Status bit
1 = Overflow trap has occurred
0 = Overflow trap has not occurred
bit 3 ADDRERR: Address Error Trap Status bit
1 = Address error trap has occurred
0 = Address error trap has not occurred
bit 2 STKERR: Stack Error Trap Status bit
1 = Stack error trap has occurred
0 = Stack error trap has not occurred
bit 1 OSCFAIL: Oscillator Failure Trap Status bit
1 = Oscillator failure trap has occurred
0 = Oscillator failure trap has not occurred
bit 0 Unimplemented: Read as ‘0’

REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0
ALTIVT DISI — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — INT2EP INT1EP INT0EP
bit 7 bit 0
Legend:
bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit

1 = Uses Alternate Interrupt Vector Table
0 = Uses standard (default) Interrupt Vector Table
bit 14 DISI: DISI Instruction Status bit
1 = DISI instruction is active
0 = DISI instruction is not active
bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge

REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF
bit 7 bit 0
Legend:

bit 13 AD1IF: A/D Conversion Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit
bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit
bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit
bit 9 SPF1IF: SPI1 Fault Interrupt Flag Status bit
bit 8 T3IF: Timer3 Interrupt Flag Status bit
bit 6 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit
bit 5 IC2IF: Input Capture Channel 2 Interrupt Flag Status bit

REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED)
bit 0 INT0IF: External Interrupt 0 Flag Status bit

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — INT1IF CNIF CMIF MI2C1IF SI2C1IF
bit 7 bit 0
Legend:
bit 15 U2TXIF: UART2 Transmitter Interrupt Flag Status bit

bit 14 U2RXIF: UART2 Receiver Interrupt Flag Status bit
bit 3 CNIF: Input Change Notification Interrupt Flag Status bit
bit 2 CMIF: Comparator Interrupt Flag Status bit
bit 1 MI2C1IF: Master I2C1 Event Interrupt Flag Status bit
bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit

U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0
— — PMPIF — — — OC5IF —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0

IC5IF IC4IF IC3IF — — — SPI2IF SPF2IF
bit 7 bit 0
Legend:

bit 13 PMPIF: Parallel Master Port Interrupt Flag Status bit
bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit
bit 0 SPF2IF: SPI2 Fault Interrupt Flag Status bit

U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

— RTCIF — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0

— — — — — MI2C2IF SI2C2IF —
bit 7 bit 0
Legend:

bit 14 RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit
bit 2 MI2C2IF: Master I2C2 Event Interrupt Flag Status bit
bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — LVDIF
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0

— — — — CRCIF U2ERIF U1ERIF —
bit 7 bit 0
Legend:

bit 8 LVDIF: Low-Voltage Detect Interrupt Flag Status bit
bit 3 CRCIF: CRC Generator Interrupt Flag Status bit
bit 2 U2ERIF: UART2 Error Interrupt Flag Status bit
bit 1 U1ERIF: UART1 Error Interrupt Flag Status bit

REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE(1)
bit 7 bit 0
Legend:

bit 13 AD1IE: A/D Conversion Complete Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit
bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit
bit 10 SPI1IE: SPI1 Transfer Complete Interrupt Enable bit
bit 9 SPF1IE: SPI1 Fault Interrupt Enable bit
bit 8 T3IE: Timer3 Interrupt Enable bit
bit 6 OC2IE: Output Compare Channel 2 Interrupt Enable bit
bit 5 IC2IE: Input Capture Channel 2 Interrupt Enable bit
Note 1: If INTxIE = 1, this external interrupt input must be configured to an available RPn pin. See Section 10.4
“Peripheral Pin Select (PPS)” for more information.

REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED)
bit 0 INT0IE: External Interrupt 0 Enable bit(1)

U2TXIE U2RXIE INT2IE(1) T5IE T4IE OC4IE OC3IE —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — INT1IE(1) CNIE CMIE MI2C1IE SI2C1IE
bit 7 bit 0
Legend:
bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit

bit 14 U2RXIE: UART2 Receiver Interrupt Enable bit
bit 3 CNIE: Input Change Notification Interrupt Enable bit
bit 2 CMIE: Comparator Interrupt Enable bit
bit 1 MI2C1IE: Master I2C1 Event Interrupt Enable bit
bit 0 SI2C1IE: Slave I2C1 Event Interrupt Enable bit

U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0
— — PMPIE — — — OC5IE —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0

IC5IE IC4IE IC3IE — — — SPI2IE SPF2IE
bit 7 bit 0
Legend:

bit 13 PMPIE: Parallel Master Port Interrupt Enable bit
bit 1 SPI2IE: SPI2 Event Interrupt Enable bit
bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit

U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0
— RTCIE — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0

— — — — — MI2C2IE SI2C2IE —
bit 7 bit 0
Legend:

bit 14 RTCIE: Real-Time Clock/Calendar Interrupt Enable bit
bit 2 MI2C2IE: Master I2C2 Event Interrupt Enable bit
bit 1 SI2C2IE: Slave I2C2 Event Interrupt Enable bit

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — LVDIE
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0

— — — — CRCIE U2ERIE U1ERIE —
bit 7 bit 0
Legend:

bit 8 LVDIE: Low-Voltage Detect Interrupt Enable Status bit
bit 3 CRCIE: CRC Generator Interrupt Enable bit
bit 2 U2ERIE: UART2 Error Interrupt Enable bit
bit 1 U1ERIE: UART1 Error Interrupt Enable bit

REGISTER 7-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0
bit 7 bit 0
Legend:

bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits
•
•
•
bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits
•
•
•
bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits
•
•
•

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— IC2IP2 IC2IP1 IC2IP0 — — — —
bit 7 bit 0
Legend:

•
•
•
•
•
•
•
•
•

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0
bit 7 bit 0
Legend:

bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits
•
•
•
bit 10-8 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits
•
•
•
bit 6-4 SPF1IP<2:0>: SPI1 Fault Interrupt Priority bits
•
•
•
•
•
•

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0
bit 7 bit 0
Legend:

bit 6-4 AD1IP<2:0>: A/D Conversion Complete Interrupt Priority bits
•
•
•
bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits
•
•
•

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— MI2C1P2 MI2C1P1 MI2C1P0 — SI2C1P2 SI2C1P1 SI2C1P0
bit 7 bit 0
Legend:

bit 14-12 CNIP<2:0>: Input Change Notification Interrupt Priority bits
•
•
•
bit 10-8 CMIP<2:0>: Comparator Interrupt Priority bits
•
•
•
bit 6-4 MI2C1P<2:0>: Master I2C1 Event Interrupt Priority bits
•
•
•
bit 2-0 SI2C1P<2:0>: Slave I2C1 Event Interrupt Priority bits
•
•
•

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — INT1IP2 INT1IP1 INT1IP0
bit 7 bit 0
Legend:

•
•
•

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— OC3IP2 OC3IP1 OC3IP0 — — — —
bit 7 bit 0
Legend:

•
•
•
•
•
•
•
•
•

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0
bit 7 bit 0
Legend:

bit 14-12 U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits
•
•
•
bit 10-8 U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits
•
•
•
•
•
•
•
•
•

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0
bit 7 bit 0
Legend:

bit 6-4 SPI2IP<2:0>: SPI2 Event Interrupt Priority bits
•
•
•
bit 2-0 SPF2IP<2:0>: SPI2 Fault Interrupt Priority bits
•
•
•

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— IC3IP2 IC3IP1 IC3IP0 — — — —
bit 7 bit 0
Legend:

•
•
•
•
•
•
•
•
•

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— OC5IP2 OC5IP1 OC5IP0 — — — —
bit 7 bit 0
Legend:

•
•
•

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— PMPIP2 PMPIP1 PMPIP0 — — — —
bit 7 bit 0
Legend:

bit 6-4 PMPIP<2:0>: Parallel Master Port Interrupt Priority bits
•
•
•

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0
— — — — — MI2C2P2 MI2C2P1 MI2C2P0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— SI2C2P2 SI2C2P1 SI2C2P0 — — — —
bit 7 bit 0
Legend:

bit 10-8 MI2C2P<2:0>: Master I2C2 Event Interrupt Priority bits
•
•
•
bit 6-4 SI2C2P<2:0>: Slave I2C2 Event Interrupt Priority bits
•
•
•

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0
— — — — — RTCIP2 RTCIP1 RTCIP0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:

bit 10-8 RTCIP<2:0>: Real-Time Clock/Calendar Interrupt Priority bits
•
•
•

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— U1ERIP2 U1ERIP1 U1ERIP0 — — — —
bit 7 bit 0
Legend:

bit 14-12 CRCIP<2:0>: CRC Generator Error Interrupt Priority bits
•
•
•
bit 10-8 U2ERIP<2:0>: UART2 Error Interrupt Priority bits
•
•
•
bit 6-4 U1ERIP<2:0>: UART1 Error Interrupt Priority bits
•
•
•

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — LVDIP2 LVDIP1 LVDIP0
bit 7 bit 0
Legend:

bit 2-0 LVDIP<2:0>: Low-Voltage Detect Interrupt Priority bits
•
•
•

REGISTER 7-31: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
R-0 U-0 R/W-0 U-0 R-0 R-0 R-0 R-0
CPUIRQ — VHOLD — ILR3 ILR2 ILR1 ILR0
bit 15 bit 8
U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

— VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
bit 7 bit 0
Legend:
bit 15 CPUIRQ: Interrupt Request from Interrupt Controller CPU bit

1 = An interrupt request has occurred but has not yet been Acknowledged by the CPU; this happens
when the CPU priority is higher than the interrupt priority
0 = No interrupt request is unacknowledged
bit 13 VHOLD: Vector Number Capture Configuration bit
1 = VECNUMx bits contain the value of the highest priority pending interrupt
0 = VECNUMx bits contain the value of the last Acknowledged interrupt (i.e., the last interrupt that has
occurred with higher priority than the CPU, even if other interrupts are pending)
bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits
1111 = CPU Interrupt Priority Level is 15
•
•
•
bit 6-0 VECNUM<6:0>: Pending Interrupt Vector ID bits (pending vector number is VECNUM + 8)
0111111 = Interrupt vector pending is Number 135
•
•
•

7.4 Interrupt Setup Procedures 7.4.3 TRAP SERVICE ROUTINE
A Trap Service Routine (TSR) is coded like an ISR,
7.4.1 INITIALIZATION except that the appropriate trap status flag in the
To configure an interrupt source: INTCON1 register must be cleared to avoid re-entry
1. Set the NSTDIS Control bit (INTCON1<15>) if into the TSR.
nested interrupts are not desired.
7.4.4 INTERRUPT DISABLE
2. Select the user-assigned priority level for the
interrupt source by writing the control bits in the All user interrupts can be disabled using the following
appropriate IPCx register. The priority level will procedure:
depend on the specific application and type of 1. Push the current SR value onto the software
interrupt source. If multiple priority levels are not stack using the PUSH instruction.
desired, the IPCx register control bits for all 2. Force the CPU to Priority Level 7 by inclusive
enabled interrupt sources may be programmed ORing the value, OEh, with SRL.
to the same non-zero value.
To enable user interrupts, the POP instruction may be
Note: At a device Reset, the IPCx registers are used to restore the previous SR value.
initialized, such that all user interrupt
sources are assigned to Priority Level 4. Note that only user interrupts with a priority level of 7 or
less can be disabled. Trap sources (Levels 8-15)
3. Clear the interrupt flag status bit associated with cannot be disabled.
the peripheral in the associated IFSx register.
The DISI instruction provides a convenient way to
4. Enable the interrupt source by setting the disable interrupts of Priority Levels 1-6 for a fixed
interrupt enable control bit associated with the period of time. Level 7 interrupt sources are not
source in the appropriate IECx register. disabled by the DISI instruction.
7.4.2 INTERRUPT SERVICE ROUTINE
The method that is used to declare an ISR and initialize
the IVT with the correct vector address will depend on
the programming language (i.e., ‘C’ or assembler) and
the language development toolsuite that is used to
develop the application. In general, the user must clear
the interrupt flag in the appropriate IFSx register for the
source of the interrupt that the ISR handles. Otherwise,
the ISR will be re-entered immediately after exiting the
routine. If the ISR is coded in assembly language, it
must be terminated using a RETFIE instruction to
unstack the saved PC value, SRL value and old CPU
priority level.

8.0 OSCILLATOR • Software-controllable switching between various
clock sources
CONFIGURATION
• Software-controllable postscaler for selective
Note: This data sheet summarizes the features of clocking of CPU for system power savings
this group of PIC24F devices. It is not • A Fail-Safe Clock Monitor (FSCM) that detects
intended to be a comprehensive reference clock failure and permits safe application recovery
source. For more information, refer to the or shutdown
A simplified diagram of the oscillator system is shown
“Oscillator” (DS39700).
in Figure 8-1.
The oscillator system for PIC24FJ64GA004 family
devices has the following features:
• A total of four external and internal oscillator options
as clock sources, providing 11 different clock modes
• On-chip 4x PLL to boost internal operating frequency
on select internal and external oscillator sources
FIGURE 8-1: PIC24FJ64GA004 FAMILY CLOCK DIAGRAM
Primary Oscillator PIC24FJ64GA004 Family
XT, HS, EC
OSCI CLKO
XTPLL, HSPLL CLKDIV<14:12>

OSCO ECPLL,FRCPLL
4 x PLL
Postscaler
CPU
8 MHz
Postscaler
4 MHz
FRC FRCDIV
Oscillator 8 MHz
(nominal)
Peripherals
CLKDIV<10:8>
FRC
LPRC LPRC
Oscillator 31 kHz (nominal)
Secondary Oscillator
SOSC
SOSCI
SOSCEN
Enable
SOSCO Oscillator Clock Control Logic
Fail-Safe
Clock
Monitor
WDT, PWRT
Clock Source Option

for Other Modules

8.1 CPU Clocking Scheme 8.2 Initial Configuration on POR
The system clock source can be provided by one of The oscillator source (and operating mode) that is
four sources: used at a device Power-on Reset event is selected
• Primary Oscillator (POSC) on the OSCI and using Configuration bit settings. The Oscillator Config-
OSCO pins uration bit settings are located in the Configuration
registers in the program memory (refer to
• Secondary Oscillator (SOSC) on the SOSCI and
Section 24.1 “Configuration Bits” for further
SOSCO pins
details). The Primary Oscillator Configuration bits,
• Fast Internal RC (FRC) Oscillator POSCMD<1:0> (Configuration Word 2<1:0>), and the
• Low-Power Internal RC (LPRC) Oscillator Initial Oscillator Select Configuration bits,
The primary oscillator and FRC sources have the FNOSC<2:0> (Configuration Word 2<10:8>), select
option of using the internal 4x PLL. The frequency of the oscillator source that is used at a Power-on Reset.
the FRC clock source can optionally be reduced by the The FRC Primary Oscillator with Postscaler (FRCDIV)
programmable clock divider. The selected clock source is the default (unprogrammed) selection. The Second-
generates the processor and peripheral clock sources. ary Oscillator, or one of the internal oscillators, may be
chosen by programming these bit locations.
The processor clock source is divided by two to pro-
duce the internal instruction cycle clock, FCY. In this The Configuration bits allow users to choose between
document, the instruction cycle clock is also denoted the various clock modes, shown in Table 8-1.
by FOSC/2. The internal instruction cycle clock, FOSC/2,
can be provided on the OSCO I/O pin for some 8.2.1 CLOCK SWITCHING MODE
operating modes of the primary oscillator. CONFIGURATION BITS
The FCKSM<1:0> Configuration bits (Configuration
Word 2<7:6>) are used to jointly configure device clock
switching and the Fail-Safe Clock Monitor (FSCM).
Clock switching is enabled only when FCKSM1 is
programmed (‘0’). The FSCM is enabled only when
FCKSM<1:0> are both programmed (‘00’).
TABLE 8-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION

Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0> Notes
Fast RC Oscillator with Postscaler Internal 11 111 1, 2
(FRCDIV)
(Reserved) Internal xx 110 1
Low-Power RC Oscillator (LPRC) Internal 11 101 1
Secondary (Timer1) Oscillator Secondary 00 100 1
(SOSC)
Primary Oscillator (XT) with PLL Primary 01 011
Module (XTPLL)
Primary Oscillator (EC) with PLL Primary 00 011
Module (ECPLL)
Primary Oscillator (HS) Primary 10 010
Primary Oscillator (XT) Primary 01 010
Primary Oscillator (EC) Primary 00 010
Fast RC Oscillator with PLL Module Internal 11 001 1
(FRCPLL)
Fast RC Oscillator (FRC) Internal 11 000 1
Note 1: OSCO pin function is determined by the OSCIOFCN Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.

8.3 Control Registers The Clock Divider register (Register 8-2) controls the
features associated with Doze mode, as well as the
The operation of the oscillator is controlled by three postscaler for the FRC oscillator.
Special Function Registers:
The FRC Oscillator Tune register (Register 8-3) allows
• OSCCON the user to fine-tune the FRC oscillator over a range of
• CLKDIV approximately ±12%.
• OSCTUN
The OSCCON register (Register 8-1) is the main con-
trol register for the oscillator. It controls clock source
switching and allows the monitoring of clock sources.
REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER

U-0 R-0 R-0 R-0 U-0 R/W-x(1) R/W-x(1) R/W-x(1)
— COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0
bit 15 bit 8
R/SO-0 R/W-0 R-0(3) U-0 R/CO-0 U-0 R/W-0 R/W-0

(2)
CLKLOCK IOLOCK LOCK — CF — SOSCEN OSWEN
bit 7 bit 0
Legend: CO = Clearable Only bit SO = Settable Only bit


bit 14-12 COSC<2:0>: Current Oscillator Selection bits
111 = Fast RC Oscillator with Postscaler (FRCDIV)
110 = Reserved
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)
bit 10-8 NOSC<2:0>: New Oscillator Selection bits(1)
110 = Reserved
Note 1: Reset values for these bits are determined by the FNOSCx Configuration bits.
2: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In
addition, if the IOL1WAY Configuration bit is ‘1’ once the IOLOCK bit is set, it cannot be cleared.
3: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.

REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
bit 7 CLKLOCK: Clock Selection Lock Enable bit
If FSCM is enabled (FCKSM1 = 1):
1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit
If FSCM is disabled (FCKSM1 = 0):
Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
bit 6 IOLOCK: I/O Lock Enable bit(2)
1 = I/O lock is active
0 = I/O lock is not active
bit 5 LOCK: PLL Lock Status bit(3)
1 = PLL module is in lock or PLL module start-up timer is satisfied
0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled
bit 3 CF: Clock Fail Detect bit
1 = FSCM has detected a clock failure
0 = No clock failure has been detected
bit 1 SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit
1 = Enables Secondary Oscillator
0 = Disables Secondary Oscillator
bit 0 OSWEN: Oscillator Switch Enable bit
1 = Initiates an oscillator switch to a clock source specified by the NOSC<2:0> bits
0 = Oscillator switch is complete
Note 1: Reset values for these bits are determined by the FNOSCx Configuration bits.
2: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In
addition, if the IOL1WAY Configuration bit is ‘1’ once the IOLOCK bit is set, it cannot be cleared.
3: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.

REGISTER 8-2: CLKDIV: CLOCK DIVIDER REGISTER
ROI DOZE2 DOZE1 DOZE0 DOZEN(1) RCDIV2 RCDIV1 RCDIV0
bit 15 bit 8
U-0 U-1 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:
bit 15 ROI: Recover on Interrupt bit

1 = Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1
0 = Interrupts have no effect on the DOZEN bit
bit 14-12 DOZE<2:0>: CPU Peripheral Clock Ratio Select bits
111 = 1:128
110 = 1:64
101 = 1:32
100 = 1:16
011 = 1:8
010 = 1:4
001 = 1:2
000 = 1:1
bit 11 DOZEN: DOZE Enable bit(1)
1 = DOZE<2:0> bits specify the CPU peripheral clock ratio
0 = CPU peripheral clock ratio is set to 1:1
bit 10-8 RCDIV<2:0>: FRC Postscaler Select bits
111 = 31.25 kHz (divide-by-256)
110 = 125 kHz (divide-by-64)
101 = 250 kHz (divide-by-32)
100 = 500 kHz (divide-by-16)
011 = 1 MHz (divide-by-8)
Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs.

REGISTER 8-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — TUN5(1) TUN4(1) TUN3(1) TUN2(1) TUN1(1) TUN0(1)
bit 7 bit 0
Legend:

bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1)
011111 = Maximum frequency deviation
011110 =



000001 =
000000 = Center frequency, oscillator is running at factory calibrated frequency
111111 =



100001 =
100000 = Minimum frequency deviation
Note 1: Increments or decrements of TUN<5:0> may not change the FRC frequency in equal steps over the FRC
tuning range and may not be monotonic.
8.4 Clock Switching Operation 8.4.1 ENABLING CLOCK SWITCHING

With few limitations, applications are free to switch To enable clock switching, the FCKSM1 Configuration
between any of the four clock sources (POSC, SOSC, bit in Flash Configuration Word 2 must be programmed
FRC and LPRC) under software control and at any to ‘0’. (Refer to Section 24.1 “Configuration Bits” for
time. To limit the possible side effects that could result further details.) If the FCKSM1 Configuration bit is
from this flexibility, PIC24F devices have a safeguard unprogrammed (‘1’), the clock switching function and
lock built into the switching process. Fail-Safe Clock Monitor function are disabled. This is
the default setting.
Note: The Primary Oscillator mode has three
The NOSCx control bits (OSCCON<10:8>) do not
different submodes (XT, HS and EC)
control the clock selection when clock switching is dis-
which are determined by the POSCMDx
abled. However, the COSCx bits (OSCCON<14:12>)
Configuration bits. While an application
will reflect the clock source selected by the FNOSCx
can switch to and from Primary Oscillator
Configuration bits.
mode in software, it cannot switch
between the different primary submodes The OSWEN control bit (OSCCON<0>) has no effect
without reprogramming the device. when clock switching is disabled; it is held at ‘0’ at all
times.

8.4.2 OSCILLATOR SWITCHING A recommended code sequence for a clock switch
SEQUENCE includes the following:
At a minimum, performing a clock switch requires this 1. Disable interrupts during the OSCCON register
basic sequence: unlock and write sequence.
1. If desired, read the COSCx bits 2. Execute the unlock sequence for the OSCCON
(OSCCON<14:12>) to determine the current high byte by writing 78h and 9Ah to
oscillator source. OSCCON<15:8> in two back-to-back
instructions.
2. Perform the unlock sequence to allow a write to
the OSCCON register high byte. 3. Write the new oscillator source to the NOSCx
bits in the instruction immediately following the
3. Write the appropriate value to the NOSCx bits
unlock sequence.
(OSCCON<10:8>) for the new oscillator source.
4. Execute the unlock sequence for the OSCCON
4. Perform the unlock sequence to allow a write to
low byte by writing 46h and 57h to
the OSCCON register low byte.
OSCCON<7:0> in two back-to-back instructions.
5. Set the OSWEN bit to initiate the oscillator
5. Set the OSWEN bit in the instruction immediately
switch.
following the unlock sequence.
Once the basic sequence is completed, the system 6. Continue to execute code that is not
clock hardware responds automatically as follows: clock-sensitive (optional).
1. The clock switching hardware compares the 7. Invoke an appropriate amount of software delay
COSCx bits with the new value of the NOSCx (cycle counting) to allow the selected oscillator
bits. If they are the same, then the clock switch and/or PLL to start and stabilize.
is a redundant operation. In this case, the 8. Check to see if OSWEN is ‘0’. If it is, the switch
OSWEN bit is cleared automatically and the was successful. If OSWEN is still set, then check
clock switch is aborted. the LOCK bit to determine the cause of failure.
2. If a valid clock switch has been initiated, the
The core sequence for unlocking the OSCCON register
LOCK (OSCCON<5>) and CF (OSCCON<3>)
and initiating a clock switch is shown in Example 8-1.
bits are cleared.
3. The new oscillator is turned on by the hardware
EXAMPLE 8-1: BASIC CODE SEQUENCE
if it is not currently running. If a crystal oscillator
FOR CLOCK SWITCHING
must be turned on, the hardware will wait until
the OST expires. If the new source is using the .global __reset
.include "p24fxxxx.inc"
PLL, then the hardware waits until a PLL lock is
.text
detected (LOCK = 1). __reset:
4. The hardware waits for 10 clock cycles from the ;Place the new oscillator selection in W0
new clock source and then performs the clock ;OSCCONH (high byte) Unlock Sequence
switch. DISI #18
5. The hardware clears the OSWEN bit to indicate a PUSH w1
PUSH w2
successful clock transition. In addition, the
PUSH w3
NOSCx bit values are transferred to the COSCx MOV #OSCCONH, w1
bits. MOV #0x78, w2
6. The old clock source is turned off at this time, with MOV #0x9A, w3
the exception of LPRC (if WDT or FSCM are MOV.b w2, [w1]
enabled) or SOSC (if SOSCEN remains set). MOV.b w3, [w1]
;Set new oscillator selection
Note 1: The processor will continue to execute MOV.b WREG, OSCCONH
code throughout the clock switching ;OSCCONL (low byte) unlock sequence
sequence. Timing-sensitive code should MOV #OSCCONL, w1
not be executed during this time. MOV #0x46, w2
MOV #0x57, w3
2: Direct clock switches between any MOV.b w2, [w1]
Primary Oscillator mode with PLL and MOV.b w3, [w1]
FRCPLL mode are not permitted. This ;Start oscillator switch operation
applies to clock switches in either direc- BSET OSCCON, #0
tion. In these instances, the application POP w3
must switch to FRC mode as a transitional POP w2
clock source between the two PLL modes. POP w1
.end

8.4.3 SECONDARY OSCILLATOR 8.4.4 OSCILLATOR LAYOUT
LOW-POWER OPERATION On low pin count devices, such as those in the
Note: This feature is implemented only on PIC24FJ64GA004 family, due to pinout limitations, the
PIC24FJ64GA004 family devices with a SOSC is more susceptible to noise than other PIC24F
major silicon revision level of B or later devices. Unless proper care is taken in the design and
(DEVREV register value is 3042h or layout of the SOSC circuit, it is possible for
greater). inaccuracies to be introduced into the oscillator’s
period.
The Secondary Oscillator (SOSC) can operate in two
In general, the crystal circuit connections should be as
distinct levels of power consumption based on device
short as possible. It is also good practice to surround
configuration. In Low-Power mode, the oscillator
the crystal circuit with a ground loop or ground plane.
operates in a low gain, low-power state. By default, the
For more detailed information on crystal circuit design,
oscillator uses a higher gain setting, and therefore,
please refer to the “PIC24F Family Reference Manual”,
requires more power. The Secondary Oscillator Mode
“Oscillator” (DS39700) and Microchip Application
Selection bits, SOSCSEL<1:0> (CW2<12:11>),
Notes: AN826, “Crystal Oscillator Basics and Crystal
determine the oscillator’s power mode.
Selection for rfPIC® and PICmicro® Devices”
When Low-Power mode is used, care must be taken in (DS00826) and AN849, “Basic PICmicro® Oscillator
the design and layout of the SOSC circuit to ensure that Design” (DS00849).
the oscillator will start up and oscillate properly. The
lower gain of this mode makes the SOSC more
sensitive to noise and requires a longer start-up time.

9.0 POWER-SAVING FEATURES Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset.
Note: This data sheet summarizes the features of When the device exits these modes, it is said to
this group of PIC24F devices. It is not “wake-up”.
Note: SLEEP_MODE and IDLE_MODE are con-
stants defined in the assembler include
file for the selected device.
“Power-Saving Features” (DS39698).
Additional power-saving tips can also be
found in Appendix B: “Additional Guid- 9.2.1 SLEEP MODE
ance for PIC24FJ64GA004 Family Sleep mode includes these features:
Applications” of this document. • The system clock source is shut down. If an
The PIC24FJ64GA004 family of devices provides the on-chip oscillator is used, it is turned off.
ability to manage power consumption by selectively • The device current consumption will be reduced
managing clocking to the CPU and the peripherals. In to a minimum provided that no I/O pin is sourcing
general, a lower clock frequency and a reduction in the current.
number of circuits being clocked constitutes lower • The Fail-Safe Clock Monitor does not operate
consumed power. All PIC24F devices manage power during Sleep mode since the system clock source
consumption in four different ways: is disabled.
• Clock Frequency • The LPRC clock will continue to run in Sleep
• Instruction-Based Sleep and Idle modes mode if the WDT is enabled.
• Software Controlled Doze mode • The WDT, if enabled, is automatically cleared
prior to entering Sleep mode.
• Selective Peripheral Control in Software
• Some device features or peripherals may
Combinations of these methods can be used to selec- continue to operate in Sleep mode. This includes
tively tailor an application’s power consumption, while items such as the Input Change Notification on
still maintaining critical application features, such as the I/O ports, or peripherals that use an external
timing-sensitive communications. clock input. Any peripheral that requires the
system clock source for its operation will be
9.1 Clock Frequency and Clock disabled in Sleep mode.
Switching Additional power reductions can be achieved by
PIC24F devices allow for a wide range of clock disabling the on-chip voltage regulator whenever Sleep
frequencies to be selected under application control. If mode is invoked. This is done by clearing the PMSLP
the system clock configuration is not locked, users can bit (RCON<8>). Disabling the regulator adds an addi-
choose low-power or high-precision oscillators by simply tional delay of about 190 s to the device wake-up
changing the NOSCx bits. The process of changing a time. It is recommended that applications not using the
system clock during operation, as well as limitations to voltage regulator leave the PMSLP bit set. For addi-
the process, are discussed in more detail in Section 8.0 tional details on the regulator and Sleep mode, see
“Oscillator Configuration”. Section 24.2.5 “Voltage Regulator Standby Mode”.
The device will wake-up from Sleep mode on any of
9.2 Instruction-Based Power-Saving these events:
Modes • On any interrupt source that is individually
enabled.
PIC24F devices have two special power-saving modes
• On any form of device Reset.
that are entered through the execution of a special
PWRSAV instruction. Sleep mode stops clock operation • On a WDT time-out.
and halts all code execution; Idle mode halts the CPU On wake-up from Sleep, the processor will restart with
and code execution, but allows peripheral modules to the same clock source that was active when Sleep
continue operation. The assembly syntax of the mode was entered.
PWRSAV instruction is shown in Example 9-1.
EXAMPLE 9-1: PWRSAV INSTRUCTION SYNTAX

PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode
PWRSAV #IDLE_MODE ; Put the device into IDLE mode

9.2.2 IDLE MODE It is also possible to use Doze mode to selectively
reduce power consumption in event driven applica-
Idle mode includes these features:
tions. This allows clock-sensitive functions, such as
• The CPU will stop executing instructions. synchronous communications, to continue without
• The WDT is automatically cleared. interruption while the CPU Idles, waiting for something
• The system clock source remains active. By to invoke an interrupt routine. Enabling the automatic
default, all peripheral modules continue to operate return to full-speed CPU operation on interrupts is
normally from the system clock source, but can enabled by setting the ROI bit (CLKDIV<15>). By
also be selectively disabled (see Section 9.4 default, interrupt events have no effect on Doze mode
“Selective Peripheral Module Control”). operation.
• If the WDT or FSCM is enabled, the LPRC will
also remain active. 9.4 Selective Peripheral Module
The device will wake from Idle mode on any of these Control
events: Idle and Doze modes allow users to substantially
• Any interrupt that is individually enabled. reduce power consumption by slowing or stopping the
• Any device Reset. CPU clock. Even so, peripheral modules still remain
clocked and thus, consume power. There may be
• A WDT time-out.
cases where the application needs what these modes
On wake-up from Idle, the clock is reapplied to the CPU do not provide: the allocation of power resources to
and instruction execution begins immediately, starting CPU processing with minimal power consumption from
with the instruction following the PWRSAV instruction or the peripherals.
the first instruction in the ISR.
PIC24F devices address this requirement by allowing
9.2.3 INTERRUPTS COINCIDENT WITH peripheral modules to be selectively disabled, reducing
or eliminating their power consumption. This can be
POWER SAVE INSTRUCTIONS
done with two control bits:
Any interrupt that coincides with the execution of a
• The Peripheral Enable bit, generically named,
PWRSAV instruction will be held off until entry into Sleep
“XXXEN”, located in the module’s main control
or Idle mode has completed. The device will then
SFR.
wake-up from Sleep or Idle mode.
• The Peripheral Module Disable (PMD) bit,
generically named, “XXXMD”, located in one of
9.3 Doze Mode
the PMD control registers.
Generally, changing clock speed and invoking one of Both bits have similar functions in enabling or disabling
the power-saving modes are the preferred strategies its associated module. Setting the PMD bit for a module
for reducing power consumption. There may be cir- disables all clock sources to that module, reducing its
cumstances, however, where this is not practical. For power consumption to an absolute minimum. In this
example, it may be necessary for an application to state, the control and status registers associated with
maintain uninterrupted synchronous communication, the peripheral will also be disabled, so writes to those
even while it is doing nothing else. Reducing system registers will have no effect and read values will be
clock speed may introduce communication errors, invalid. Many peripheral modules have a corresponding
while using a power-saving mode may stop PMD bit.
communications completely.
In contrast, disabling a module by clearing its XXXEN
Doze mode is a simple and effective alternative method bit disables its functionality, but leaves its registers
to reduce power consumption while the device is still available to be read and written to. Power consumption
executing code. In this mode, the system clock contin- is reduced, but not by as much as the PMD bit does.
ues to operate from the same source and at the same Most peripheral modules have an enable bit;
speed. Peripheral modules continue to be clocked at exceptions include capture, compare and RTCC.
the same speed while the CPU clock speed is reduced.
Synchronization between the two clock domains is To achieve more selective power savings, peripheral
maintained, allowing the peripherals to access the modules can also be selectively disabled when the
SFRs while the CPU executes code at a slower rate. device enters Idle mode. This is done through the
control bit of the generic name format, “XXXIDL”. By
Doze mode is enabled by setting the DOZEN bit default, all modules that can operate during Idle mode
(CLKDIV<11>). The ratio between peripheral and core will do so. Using the disable on Idle feature allows fur-
clock speed is determined by the DOZE<2:0> bits ther reduction of power consumption during Idle mode,
(CLKDIV<14:12>). There are eight possible enhancing power savings for extremely critical power
configurations, from 1:1 to 1:256, with 1:1 being the applications.
default.

10.0 I/O PORTS When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
Note: This data sheet summarizes the features of a general purpose output pin is disabled. The I/O pin
this group of PIC24F devices. It is not may be read, but the output driver for the parallel port
intended to be a comprehensive reference bit will be disabled. If a peripheral is enabled, but the
source. For more information, refer to the peripheral is not actively driving a pin, that pin may be
“PIC24F Family Reference Manual”, “I/O driven by a port.
Ports with Peripheral Pin Select (PPS)” All port pins have three registers directly associated
(DS39711). with their operation as digital I/O. The Data Direction
All of the device pins (except VDD, VSS, MCLR and register (TRISx) determines whether the pin is an input
OSCI/CLKI) are shared between the peripherals and or an output. If the data direction bit is a ‘1’, then the pin
the Parallel I/O (PIO) ports. All I/O input ports feature is an input. All port pins are defined as inputs after a
Schmitt Trigger inputs for improved noise immunity. Reset. Reads from the Output Latch register (LATx),
read the latch. Writes to the latch, write the latch.
Reads from the port (PORTx), read the port pins, while
10.1 Parallel I/O (PIO) Ports writes to the port pins, write the latch.
A Parallel I/O port that shares a pin with a peripheral is, Any bit and its associated data and control registers
in general, subservient to the peripheral. The periph- that are not valid for a particular device will be
eral’s output buffer data and control signals are disabled. That means the corresponding LATx and
provided to a pair of multiplexers. The multiplexers TRISx registers and the port pin will read as zeros.
select whether the peripheral or the associated port
When a pin is shared with another peripheral or func-
has ownership of the output data and control signals of
tion that is defined as an input only, it is nevertheless,
the I/O pin. The logic also prevents “loop through”, in
regarded as a dedicated port because there is no
which a port’s digital output can drive the input of a
other competing source of outputs.
peripheral that shares the same pin. Figure 10-1 shows
how ports are shared with other peripherals and the
associated I/O pin to which they are connected.
FIGURE 10-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Peripheral Module Output Multiplexers

Peripheral Input Data
Peripheral Module Enable

I/O
Peripheral Output Enable
1 Output Enable
Peripheral Output Data
0
1 Output Data
PIO Module
Read TRIS 0
Data Bus
D Q I/O Pin
WR TRIS
CK
TRIS Latch
D Q
WR LAT +
CK
WR PORT
Data Latch
Read LAT
Input Data
Read PORT

10.1.1 OPEN-DRAIN CONFIGURATION TABLE 10-1: INPUT VOLTAGE LEVELS
In addition to the PORT, LAT and TRIS registers for Tolerated
Port or Pin Description
data control, each port pin can also be individually con- Input
figured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx, PORTA<4:0> VDD Only VDD input levels
associated with each port. Setting any of the bits con- PORTB<15:12> are tolerated.
figures the corresponding pin to act as an open-drain PORTB<4:0>
output.
PORTC<2:0>(1)
The open-drain feature allows the generation of PORTA<10:7>(1) 5.5V Tolerates input levels
outputs higher than VDD (e.g., 5V) on any desired above VDD, useful for
digital only pins by using external pull-up resistors. The PORTB<11:5>
most standard logic.
maximum open-drain voltage allowed is the same as PORTC<9:3>(1)
the maximum VIH specification. Note 1: Unavailable on 28-pin devices.
10.2 Configuring Analog Port Pins 10.3 Input Change Notification

The use of the AD1PCFG and TRIS registers control The Input Change Notification function of the I/O ports
the operation of the A/D port pins. The port pins that are allows the PIC24FJ64GA004 family of devices to gen-
desired as analog inputs must have their correspond- erate interrupt requests to the processor in response to
ing TRIS bit set (input). If the TRIS bit is cleared a Change-of-State (COS) on selected input pins. This
(output), the digital output level (VOH or VOL) will be feature is capable of detecting input Change-of-States
converted. even in Sleep mode, when the clocks are disabled.
When reading the PORT register, all pins configured as Depending on the device pin count, there are up to
analog input channels will read as cleared (a low level). 22 external signals that may be selected (enabled) for
generating an interrupt request on a Change-of-State.
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin that is defined as There are four control registers associated with the CN
a digital input (including the ANx pins) may cause the module. The CNEN1 and CNEN2 registers contain the
input buffer to consume current that exceeds the interrupt enable control bits for each of the CN input
device specifications. pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
10.2.1 I/O PORT WRITE/READ TIMING Each CN pin also has a weak pull-up connected to it.
One instruction cycle is required between a port The pull-ups act as a current source that is connected
direction change or port write operation and a read to the pin, and eliminate the need for external resistors
operation of the same port. Typically, this instruction when push button or keypad devices are connected.
would be a NOP. The pull-ups are enabled separately using the CNPU1
and CNPU2 registers, which contain the control bits for
10.2.2 ANALOG INPUT PINS AND each of the CN pins. Setting any of the control bits
VOLTAGE CONSIDERATIONS enables the weak pull-ups for the corresponding pins.
The voltage tolerance of pins used as device inputs is When the internal pull-up is selected, the pin pulls up to
dependent on the pin’s input function. Pins that are used VDD – 0.7V (typical). Make sure that there is no external
as digital only inputs are able to handle DC voltages up pull-up source when the internal pull-ups are enabled,
to 5.5V, a level typical for digital logic circuits. In contrast, as the voltage difference can cause a current path.
pins that also have analog input functions of any kind
Note: Pull-ups on Change Notification pins
can only tolerate voltages up to VDD. Voltage excursions
should always be disabled whenever the
beyond VDD on these pins are always to be avoided.
port pin is configured as a digital output.
Table 10-1 summarizes the input capabilities. Refer to
Section 27.1 “DC Characteristics” for more details.
EXAMPLE 10-1: PORT WRITE/READ EXAMPLE

MOV 0xFF00, W0 ; Configure PORTB<15:8> as inputs
MOV W0, TRISBB ; and PORTB<7:0> as outputs
NOP ; Delay 1 cycle
BTSS PORTB, #13 ; Next Instruction

10.4 Peripheral Pin Select (PPS) 10.4.2.1 Peripheral Pin Select Function
Priority
A major challenge in general purpose devices is provid-
ing the largest possible set of peripheral features while Pin-selectable peripheral outputs (for example, OC and
minimizing the conflict of features on I/O pins. The chal- UART transmit) take priority over any general purpose
lenge is even greater on low pin count devices similar digital functions permanently tied to that pin, such as
to the PIC24FJ64GA family. In an application that PMP and port I/O. Specialized digital outputs, such as
needs to use more than one peripheral multiplexed on USB functionality, take priority over PPS outputs on the
a single pin, inconvenient work arounds in application same pin. The pin diagrams at the beginning of this
code or a complete redesign may be the only option. data sheet list peripheral outputs in order of priority.
Refer to them for priority concerns on a particular pin.
The Peripheral Pin Select feature provides an alterna-
tive to these choices by enabling the user’s peripheral Unlike devices with fixed peripherals, pin-selectable
set selection and their placement on a wide range of peripheral inputs never take ownership of a pin. The
I/O pins. By increasing the pinout options available on pin’s output buffer is controlled by the pin’s TRIS bit
a particular device, users can better tailor the setting or by a fixed peripheral on the pin. If the pin is
microcontroller to their entire application, rather than configured in Digital mode, then the PPS input will
trimming the application to fit the device. operate correctly, reading the input. If an analog func-
tion is enabled on the same pin, the pin-selectable
The Peripheral Pin Select feature operates over a fixed
input will be disabled.
subset of digital I/O pins. Users may independently
map the input and/or output of any one of many digital 10.4.3 CONTROLLING PERIPHERAL PIN
peripherals to any one of these I/O pins. Peripheral Pin
SELECT
Select is performed in software and generally does not
require the device to be reprogrammed. Hardware Peripheral Pin Select features are controlled through
safeguards are included that prevent accidental or two sets of Special Function Registers: one to map
spurious changes to the peripheral mapping once it has peripheral inputs and one to map outputs. Because
been established. they are separately controlled, a particular peripheral’s
input and output (if the peripheral has both) can be
10.4.1 AVAILABLE PINS placed on any selectable function pin without
constraint.
The Peripheral Pin Select feature is used with a range
of up to 26 pins; the number of available pins is depen- The association of a peripheral to a peripheral-selectable
dent on the particular device and its pin count. Pins that pin is handled in two different ways, depending on if an
support the Peripheral Pin Select feature include the input or an output is being mapped.
designation, “RPn”, in their full pin designation, where
“RP” designates a remappable peripheral and “n” is the 10.4.3.1 Input Mapping
remappable pin number. See Table 1-2 for pinout The inputs of the Peripheral Pin Select options are
options in each package offering. mapped on the basis of the peripheral; that is, a control
register associated with a peripheral dictates the pin it
10.4.2 AVAILABLE PERIPHERALS will be mapped to. The RPINRx registers are used to
The peripherals managed by the Peripheral Pin Select configure peripheral input mapping (see Register 10-1
are all digital only peripherals. These include general through Register 10-14). Each register contains two
serial communications (UART and SPI), general pur- sets of 5-bit fields, with each set associated with one of
pose timer clock inputs, timer-related peripherals (input the pin-selectable peripherals. Programming a given
capture and output compare) and external interrupt peripheral’s bit field with an appropriate 5-bit value
inputs. Also included are the outputs of the comparator maps the RPn pin with that value to that peripheral. For
module, since these are discrete digital signals. any given device, the valid range of values for any of
the bit fields corresponds to the maximum number of
The Peripheral Pin Select module is not applied to
Peripheral Pin Selections supported by the device.
I2C™, Change Notification inputs, RTCC alarm outputs
or peripherals with analog inputs.
A key difference between pin select and non-pin select
peripherals is that pin select peripherals are not asso-
ciated with a default I/O pin. The peripheral must
always be assigned to a specific I/O pin before it can be
used. In contrast, non-pin select peripherals are always
available on a default pin, assuming that the peripheral
is active and not conflicting with another peripheral.

TABLE 10-2: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1)
Configuration
Input Name Function Name Register
Bits
External Interrupt 1 INT1 RPINR0 INTR1<4:0>
External Interrupt 2 INT2 RPINR1 INTR2R<4:0>
Timer2 External Clock T2CK RPINR3 T2CKR<4:0>
Input Capture 1 IC1 RPINR7 IC1R<4:0>
Output Compare Fault A OCFA RPINR11 OCFAR<4:0>
Output Compare Fault B OCFB RPINR11 OCFBR<4:0>
UART1 Receive U1RX RPINR18 U1RXR<4:0>
UART1 Clear-to-Send U1CTS RPINR18 U1CTSR<4:0>
UART2 Receive U2RX RPINR19 U2RXR<4:0>
UART2 Clear-to-Send U2CTS RPINR19 U2CTSR<4:0>
SPI1 Data Input SDI1 RPINR20 SDI1R<4:0>
SPI1 Clock Input SCK1IN RPINR20 SCK1R<4:0>
SPI1 Slave Select Input SS1IN RPINR21 SS1R<4:0>
SPI2 Data Input SDI2 RPINR22 SDI2R<4:0>
SPI2 Clock Input SCK2IN RPINR22 SCK2R<4:0>
SPI2 Slave Select Input SS2IN RPINR23 SS2R<4:0>
Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.

10.4.3.2 Output Mapping 10.4.3.3 Mapping Limitations
In contrast to inputs, the outputs of the Peripheral Pin The control schema of the Peripheral Pin Select is
Select options are mapped on the basis of the pin. In extremely flexible. Other than systematic blocks that
this case, a control register associated with a particular prevent signal contention, caused by two physical pins
pin dictates the peripheral output to be mapped. The being configured as the same functional input or two
RPORx registers are used to control output mapping. functional outputs configured as the same pin, there
Like the RPINRx registers, each register contains two are no hardware enforced lockouts. The flexibility
5-bit fields; each field being associated with one RPn extends to the point of allowing a single input to drive
pin (see Register 10-15 through Register 10-27). The multiple peripherals or a single functional output to
value of the bit field corresponds to one of the periph- drive multiple output pins.
erals and that peripheral’s output is mapped to the pin
(see Table 10-3). 10.4.4 CONTROLLING CONFIGURATION
Because of the mapping technique, the list of peripher- CHANGES
als for output mapping also includes a null value of Because peripheral remapping can be changed during
‘00000’. This permits any given pin to remain discon- run time, some restrictions on peripheral remapping
nected from the output of any of the pin-selectable are needed to prevent accidental configuration
peripherals. changes. PIC24F devices include three features to
prevent alterations to the peripheral map:
TABLE 10-3: SELECTABLE OUTPUT • Control register lock sequence
SOURCES (MAPS FUNCTION • Continuous state monitoring
TO OUTPUT) • Configuration bit remapping lock
Output Function
Function Output Name 10.4.4.1 Control Register Lock
Number(1)
NULL(2) 0 NULL Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes will
C1OUT 1 Comparator 1 Output
appear to execute normally, but the contents of the
C2OUT 2 Comparator 2 Output registers will remain unchanged. To change these reg-
U1TX 3 UART1 Transmit isters, they must be unlocked in hardware. The register
U1RTS(3) 4 UART1 Request-to-Send lock is controlled by the IOLOCK bit (OSCCON<6>).
Setting IOLOCK prevents writes to the control
U2TX 5 UART2 Transmit
registers; clearing IOLOCK allows writes.
U2RTS(3) 6 UART2 Request-to-Send
To set or clear IOLOCK, a specific command sequence
SDO1 7 SPI1 Data Output must be executed:
SCK1OUT 8 SPI1 Clock Output
1. Write 46h to OSCCON<7:0>.
SS1OUT 9 SPI1 Slave Select Output
2. Write 57h to OSCCON<7:0>.
SDO2 10 SPI2 Data Output
3. Clear (or set) IOLOCK as a single operation.
SCK2OUT 11 SPI2 Clock Output
Unlike the similar sequence with the oscillator’s LOCK
SS2OUT 12 SPI2 Slave Select Output bit, IOLOCK remains in one state until changed. This
OC1 18 Output Compare 1 allows all of the Peripheral Pin Selects to be configured
OC2 19 Output Compare 2 with a single unlock sequence, followed by an update
OC3 20 Output Compare 3 to all control registers, then locked with a second lock
sequence.
OC4 21 Output Compare 4
OC5 22 Output Compare 5 10.4.4.2 Continuous State Monitoring
Note 1: Value assigned to the RPn<4:0> pins corre- In addition to being protected from direct writes, the
sponds to the peripheral output function contents of the RPINRx and RPORx registers are
number. constantly monitored in hardware by shadow registers.
2: The NULL function is assigned to all RPn If an unexpected change in any of the registers occurs
outputs at device Reset and disables the (such as cell disturbances caused by ESD or other
RPn output function. external events), a Configuration Mismatch Reset will
3: IrDA® BCLK functionality uses this output. be triggered.

10.4.4.3 Configuration Bit Pin Select Lock The assignment of a peripheral to a particular pin does
not automatically perform any other configuration of the
As an additional level of safety, the device can be con-
pin’s I/O circuitry. In theory, this means adding a
figured to prevent more than one write session to the
pin-selectable output to a pin may mean inadvertently
RPINRx and RPORx registers. The IOL1WAY
driving an existing peripheral input when the output is
(CW2<4>) Configuration bit blocks the IOLOCK bit
driven. Users must be familiar with the behavior of
from being cleared after it has been set once. If
other fixed peripherals that share a remappable pin and
IOLOCK remains set, the register unlock procedure will
know when to enable or disable them. To be safe, fixed
not execute and the Peripheral Pin Select Control reg-
digital peripherals that share the same pin should be
isters cannot be written to. The only way to clear the bit
disabled when not in use.
and re-enable peripheral remapping is to perform a
device Reset. Along these lines, configuring a remappable pin for a
specific peripheral does not automatically turn that fea-
In the default (unprogrammed) state, IOL1WAY is set,
ture on. The peripheral must be specifically configured
restricting users to one write session. Programming
for operation and enabled, as if it were tied to a fixed pin.
IOL1WAY allows users unlimited access (with the
Where this happens in the application code (immediately
proper use of the unlock sequence) to the Peripheral
following device Reset and peripheral configuration or
Pin Select registers.
inside the main application routine) depends on the
10.4.5 CONSIDERATIONS FOR peripheral and its use in the application.
PERIPHERAL PIN SELECTION A final consideration is that Peripheral Pin Select func-
tions neither override analog inputs, nor reconfigure
The ability to control Peripheral Pin Selection intro-
pins with analog functions for digital I/O. If a pin is
duces several considerations into application design
configured as an analog input on device Reset, it must
that could be overlooked. This is particularly true for
be explicitly reconfigured as a digital I/O when used
several common peripherals that are available only as
with a Peripheral Pin Select.
remappable peripherals.
Example 10-2 shows a configuration for bidirectional
The main consideration is that the Peripheral Pin
communication with flow control using UART1. The
Selects are not available on default pins in the device’s
following input and output functions are used:
default (Reset) state. Since all RPINRx registers reset
to ‘11111’ and all RPORx registers reset to ‘00000’, all • Input Functions: U1RX, U1CTS
Peripheral Pin Select inputs are tied to RP31 and all • Output Functions: U1TX, U1RTS
Peripheral Pin Select outputs are disconnected.
Note: In tying Peripheral Pin Select inputs to EXAMPLE 10-2: CONFIGURING UART1
RP31, RP31 does not have to exist on a INPUT AND OUTPUT
device for the registers to be reset to it. FUNCTIONS
// Unlock Registers
This situation requires the user to initialize the device
__builtin_write_OSCCONL(OSCCON & 0xBF);
with the proper peripheral configuration before any
other application code is executed. Since the IOLOCK // Configure Input Functions (Table 10-2))
bit resets in the unlocked state, it is not necessary to // Assign U1RX To Pin RP0
execute the unlock sequence after the device has RPINR18bits.U1RXR = 0;
come out of Reset. For application safety, however, it is // Assign U1CTS To Pin RP1
best to set IOLOCK and lock the configuration after RPINR18bits.U1CTSR = 1;
writing to the control registers. // Configure Output Functions (Table 10-3)
// Assign U1TX To Pin RP2
Because the unlock sequence is timing critical, it must RPOR1bits.RP2R = 3;
be executed as an assembly language routine in the // Assign U1RTS To Pin RP3
same manner as changes to the oscillator configura- RPOR1bits.RP3R = 4;
tion. If the bulk of the application is written in C or
another high-level language, the unlock sequence // Lock Registers
should be performed by writing in-line assembly. __builtin_write_OSCCONL(OSCCON | 0x40);
Choosing the configuration requires the review of all

Peripheral Pin Selects and their pin assignments,
especially those that will not be used in the application.
In all cases, unused pin-selectable peripherals should
be disabled completely. Unused peripherals should
have their inputs assigned to an unused RPn pin
function. I/O pins with unused RPn functions should be
configured with the null peripheral output.

10.5 Peripheral Pin Select Registers Note: Input and output register values can only be
The PIC24FJ64GA004 family of devices implements a changed if IOLOCK (OSCCON<6>) = 0.
total of 27 registers for remappable peripheral See Section 10.4.4.1 “Control Register
configuration: Lock” for a specific command sequence.
• Input Remappable Peripheral Registers (14)
• Output Remappable Peripheral Registers (13)
REGISTER 10-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — — INT1R4 INT1R3 INT1R2 INT1R1 INT1R0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:

bit 12-8 INT1R<4:0>: Assign External Interrupt 1 (INT1) to the Corresponding RPn Pin bits

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — INT2R4 INT2R3 INT2R2 INT2R1 INT2R0
bit 7 bit 0
Legend:

bit 4-0 INT2R<4:0>: Assign External Interrupt 2 (INT2) to the Corresponding RPn Pin bits

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — — T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

bit 7 bit 0
Legend:

bit 12-8 T3CKR<4:0>: Assign Timer3 External Clock (T3CK) to the Corresponding RPn Pin bits

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

bit 7 bit 0
Legend:


U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — — IC2R4 IC2R3 IC2R2 IC2R1 IC2R0
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

bit 7 bit 0
Legend:

bit 12-8 IC2R<4:0>: Assign Input Capture 2 (IC2) to the Corresponding RPn Pin bits

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

bit 7 bit 0
Legend:


U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

bit 7 bit 0
Legend:


U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — — OCFBR4 OCFBR3 OCFBR2 OCFBR1 OCFBR0
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0
bit 7 bit 0
Legend:

bit 12-8 OCFBR<4:0>: Assign Output Compare Fault B (OCFB) to the Corresponding RPn Pin bits
bit 4-0 OCFAR<4:0>: Assign Output Compare Fault A (OCFA) to the Corresponding RPn Pin bits

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — — U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0
bit 7 bit 0
Legend:

bit 12-8 U1CTSR<4:0>: Assign UART1 Clear-to-Send (U1CTS) to the Corresponding RPn Pin bits
bit 4-0 U1RXR<4:0>: Assign UART1 Receive (U1RX) to the Corresponding RPn Pin bits

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — — U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — U2RXR4 U2RXR3 U2RXR2 U2RXR1 U2RXR0
bit 7 bit 0
Legend:

bit 12-8 U2CTSR<4:0>: Assign UART2 Clear-to-Send (U2CTS) to the Corresponding RPn Pin bits
bit 4-0 U2RXR<4:0>: Assign UART2 Receive (U2RX) to the Corresponding RPn Pin bits

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — — SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0
bit 7 bit 0
Legend:

bit 12-8 SCK1R<4:0>: Assign SPI1 Clock Input (SCK1IN) to the Corresponding RPn Pin bits
bit 4-0 SDI1R<4:0>: Assign SPI1 Data Input (SDI1) to the Corresponding RPn Pin bits

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — SS1R4 SS1R3 SS1R2 SS1R1 SS1R0
bit 7 bit 0
Legend:

bit 4-0 SS1R<4:0>: Assign SPI1 Slave Select Input (SS1IN) to the Corresponding RPn Pin bits

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — — SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0
bit 7 bit 0
Legend:

bit 12-8 SCK2R<4:0>: Assign SPI2 Clock Input (SCK2IN) to the Corresponding RPn Pin bits
bit 4-0 SDI2R<4:0>: Assign SPI2 Data Input (SDI2) to the Corresponding RPn Pin bits

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — SS2R4 SS2R3 SS2R2 SS2R1 SS2R0
bit 7 bit 0
Legend:

bit 4-0 SS2R<4:0>: Assign SPI2 Slave Select Input (SS2IN) to the Corresponding RPn Pin bits

REGISTER 10-15: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — RP1R4 RP1R3 RP1R2 RP1R1 RP1R0
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:

bit 12-8 RP1R<4:0>: Peripheral Output Function is Assigned to RP1 Output Pin bits
(see Table 10-3 for peripheral function numbers)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — RP17R4(1) RP17R3(1) RP17R2(1) RP17R1(1) RP17R0(1)
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:

bit 12-8 RP17R<4:0>: Peripheral Output Function is Assigned to RP17 Output Pin bits(1)
Note 1: These bits are only available on the 44-pin devices; otherwise, they read as ‘0’.

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
(1) (1) (1) (1)
— — — RP21R4 RP21R3 RP21R2 RP21R1 RP21R0(1)
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

(1) (1) (1) (1)
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

(1) (1) (1) (1)
bit 7 bit 0
Legend:


11.0 TIMER1 Figure 11-1 presents a block diagram of the 16-bit timer
module.
Note: This data sheet summarizes the features of To configure Timer1 for operation:
intended to be a comprehensive reference 1. Set the TON bit (= 1).
source. For more information, refer to the 2. Select the timer prescaler ratio using the
“PIC24F Family Reference Manual”, TCKPS<1:0> bits.
“Timers” (DS39704). 3. Set the Clock and Gating modes using the TCS
and TGATE bits.
The Timer1 module is a 16-bit timer which can serve as
4. Set or clear the TSYNC bit to configure
the time counter for the Real-Time Clock (RTC), or
synchronous or asynchronous operation.
operate as a free-running, interval timer/counter.
Timer1 can operate in three modes: 5. Load the timer period value into the PR1
register.
• 16-Bit Timer
6. If interrupts are required, set the Timer1 Inter-
• 16-Bit Synchronous Counter rupt Enable bit, T1IE. Use the priority bits,
• 16-Bit Asynchronous Counter T1IP<2:0>, to set the interrupt priority.
Timer1 also supports these features:
• Timer Gate Operation
• Selectable Prescaler Settings
• Timer Operation During CPU Idle and Sleep
modes
• Interrupt on 16-Bit Period Register Match or
Falling Edge of External Gate Signal
FIGURE 11-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM
TCKPS<1:0>
SOSCO/ TON 2
1x
T1CK
Gate Prescaler
SOSCEN Sync 01 1, 8, 64, 256
SOSCI
TCY 00
TGATE
TGATE TCS
1 Q D
Set T1IF
0 Q CK
0
Reset
TMR1
1 Sync
Comparator TSYNC
Equal
PR1

REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON — TSIDL — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0

— TGATE TCKPS1 TCKPS0 — TSYNC TCS —
bit 7 bit 0
Legend:
bit 15 TON: Timer1 On bit

1 = Starts 16-bit Timer1
0 = Stops 16-bit Timer1
bit 13 TSIDL: Timer1 Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4 TCKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit
When TCS = 1:
1 = Synchronizes external clock input
0 = Does not synchronize external clock input
When TCS = 0:
bit 1 TCS: Timer1 Clock Source Select bit
1 = External clock from T1CK pin (on the rising edge)
0 = Internal clock (FOSC/2)

12.0 TIMER2/3 AND TIMER4/5 To configure Timer2/3 or Timer4/5 for 32-bit operation:
1. Set the T32 bit (T2CON<3> or T4CON<3> = 1).
2. Select the prescaler ratio for Timer2 or Timer4
using the TCKPS<1:0> bits.
source. For more information, refer to the 3. Set the Clock and Gating modes using the TCS
“PIC24F Family Reference Manual”, and TGATE bits. If TCS is set to the external
“Timers” (DS39704). clock, RPINRx (TxCK) must be configured to an
available RPn pin. See Section 10.4 “Peripheral
The Timer2/3 and Timer4/5 modules are 32-bit timers, Pin Select (PPS)” for more information.
which can also be configured as four independent, 16-bit 4. Load the timer period value. PR3 (or PR5) will
timers with selectable operating modes. contain the most significant word of the value
As a 32-bit timer, Timer2/3 and Timer4/5 operate in while PR2 (or PR4) contains the least significant
three modes: word.
• Two independent, 16-bit timers (Timer2 and 5. If interrupts are required, set the Timer3/5 Inter-
Timer3) with all 16-bit operating modes (except rupt Enable bit, T3IE or T5IE; use the priority
Asynchronous Counter mode) bits, T3IP<2:0> or T5IP<2:0>, to set the interrupt
priority. Note that while Timer2 or Timer4
• Single 32-bit timer
controls the timer, the interrupt appears as a
• Single 32-bit synchronous counter Timer3 or Timer5 interrupt.
They also support these features: 6. Set the TON bit (= 1).
• Timer gate operation The timer value, at any point, is stored in the register
• Selectable prescaler settings pair, TMR3:TMR2 (or TMR5:TMR4). TMR3 (TMR5)
• Timer operation during Idle and Sleep modes always contains the most significant word of the count,
while TMR2 (TMR4) contains the least significant word.
• Interrupt on a 32-Bit Period register match
• A/D Event Trigger (Timer2/3 only) To configure any of the timers for individual 16-bit
operation:
Individually, all four of the 16-bit timers can function as
synchronous timers or counters. They also offer the 1. Clear the T32 bit corresponding to that timer
features listed above, except for the A/D Event Trigger; (T2CON<3> for Timer2 and Timer3 or
this is implemented only with Timer3. The operating T4CON<3> for Timer4 and Timer5).
modes and enabled features are determined by setting 2. Select the timer prescaler ratio using the
the appropriate bit(s) in the T2CON, T3CON, T4CON TCKPS<1:0> bits.
and T5CON registers. T2CON and T4CON are shown 3. Set the Clock and Gating modes using the TCS
in generic form in Register 12-1; T3CON and T5CON and TGATE bits. See Section 10.4 “Peripheral
are shown in generic form in Register 12-2. Pin Select (PPS)” for more information.
For 32-bit timer/counter operation, Timer2 and Timer4 4. Load the timer period value into the PRx register.
are the least significant word; Timer3 and Timer4 are 5. If interrupts are required, set the Timerx Interrupt
the most significant word of the 32-bit timers. Enable bit, TxIE; use the priority bits, TxIP<2:0>,
to set the interrupt priority.
Note: For 32-bit operation, T3CON and T5CON
control bits are ignored. Only T2CON and 6. Set the TON bit (TxCON<15> = 1).
T4CON control bits are used for setup and
control. Timer2 and Timer4 clock and gate
inputs are utilized for the 32-bit timer
modules, but an interrupt is generated
with the Timer3 or Timer5 interrupt flags.

FIGURE 12-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM
TCKPS<1:0>
T2CK TON 2
1x
(T4CK)
Gate Prescaler
Sync 01 1, 8, 64, 256
TCY 00
TGATE TGATE(2)
TCS(2)
1 Q D
Set T3IF (T5IF)
Q CK
0
PR3 PR2
(PR5) (PR4)
A/D Event Trigger(3)

Equal
Comparator
MSB LSB
TMR3 TMR2
(TMR4) Sync
Reset (TMR5)
16
Read TMR2 (TMR4)(1)

Write TMR2 (TMR4)(1)
16
TMR3HLD 16
(TMR5HLD)
Data Bus<15:0>
Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are
respective to the T2CON and T4CON registers.
2: This peripheral’s inputs must be assigned to an available RPn pin before use. Please see
Section 10.4 “Peripheral Pin Select (PPS)” for more information.
3: The A/D Event Trigger is available only on Timer2/3.

FIGURE 12-2: TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
TCKPS<1:0>
TON 2
T2CK 1x
(T4CK)
Gate Prescaler
Sync 01 1, 8, 64, 256
TGATE 00
TCY TCS(1)
1 Q D TGATE(1)
Set T2IF (T4IF)
0 Q CK
Reset
TMR2 (TMR4) Sync
Comparator
Equal
PR2 (PR4)
Note 1: This peripheral’s inputs must be assigned to an available RPn pin before use. Please see
FIGURE 12-3: TIMER3 AND TIMER5 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
TCKPS<1:0>
T3CK TON 2
(T5CK) Sync 1x
Prescaler
01 1, 8, 64, 256
TGATE 00
TCY TCS(1)
1 Q D TGATE(1)
Set T3IF (T5IF) Q CK
0
Reset
TMR3 (TMR5)
A/D Event Trigger(2)

Comparator
Equal
PR3 (PR5)
Note 1: This peripheral’s inputs must be assigned to an available RPn pin before use. Please see
2: The A/D Event Trigger is available only on Timer3.

REGISTER 12-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON — TSIDL — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0

(1) (2)
— TGATE TCKPS1 TCKPS0 T32 — TCS —
bit 7 bit 0
Legend:
bit 15 TON: Timerx On bit

When TxCON<3> = 1:
1 = Starts 32-bit Timerx/y
0 = Stops 32-bit Timerx/y
When TxCON<3> = 0:
1 = Starts 16-bit Timerx
0 = Stops 16-bit Timerx
bit 13 TSIDL: Timerx Stop in Idle Mode bit
bit 6 TGATE: Timerx Gated Time Accumulation Enable bit
When TCS = 1:
When TCS = 0:
bit 5-4 TCKPS<1:0>: Timerx Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3 T32: 32-Bit Timer Mode Select bit(1)
1 = Timerx and Timery form a single 32-bit timer
0 = Timerx and Timery act as two 16-bit timers
In 32-bit mode, T3CON control bits do not affect 32-bit timer operation.
bit 1 TCS: Timerx Clock Source Select bit(2)
1 = External clock from pin, TxCK (on the rising edge)
Note 1: In 32-bit mode, the T3CON or T5CON control bits do not affect 32-bit timer operation.
2: If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. For more information, see
Section 10.4 “Peripheral Pin Select (PPS)”.

REGISTER 12-2: TyCON: TIMER3 AND TIMER5 CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
(1) TSIDL(1)
TON — — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0

— TGATE(1) TCKPS1(1) TCKPS0(1) — — TCS(1,2) —
bit 7 bit 0
Legend:
bit 15 TON: Timery On bit(1)

1 = Starts 16-bit Timery
0 = Stops 16-bit Timery
bit 13 TSIDL: Timery Stop in Idle Mode bit(1)
bit 6 TGATE: Timery Gated Time Accumulation Enable bit(1)
When TCS = 1:
When TCS = 0:
bit 5-4 TCKPS<1:0>: Timery Input Clock Prescale Select bits(1)
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 1 TCS: Timery Clock Source Select bit(1,2)
1 = External clock from pin, TyCK (on the rising edge)
Note 1: When 32-bit operation is enabled (T2CON<3> or T4CON<3> = 1), these bits have no effect on Timery
operation; all timer functions are set through T2CON and T4CON.
2: If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. See Section 10.4 “Peripheral
Pin Select (PPS)” for more information.

NOTES:

13.0 INPUT CAPTURE
“Input Capture” (DS39701).
FIGURE 13-1: INPUT CAPTURE x BLOCK DIAGRAM
From 16-Bit Timers

TMRy TMRx
16 16
1 0 ICTMR
(ICxCON<7>)
Prescaler Edge Detection Logic FIFO
Counter and R/W
(1, 4, 16) Clock Synchronizer Logic
ICx Pin
ICM<2:0> (ICxCON<2:0>)
3 Mode Select
FIFO
ICOV, ICBNE (ICxCON<4:3>)
ICxBUF
ICI<1:0>
Interrupt
ICxCON Logic
System Bus
Set Flag ICxIF
(in IFSx Register)
Note 1: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
2: This peripheral’s inputs must be assigned to an available RPn pin before use. Please see Section 10.4

13.1 Input Capture Registers
REGISTER 13-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
— — ICSIDL — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-0, HC R-0, HC R/W-0 R/W-0 R/W-0

ICTMR ICI1 ICI0 ICOV ICBNE ICM2(1) ICM1(1) ICM0(1)
bit 7 bit 0
Legend: HC = Hardware Clearable bit


bit 13 ICSIDL: Input Capture x Stop in Idle Control bit
1 = Input capture module will halt in CPU Idle mode
0 = Input capture module will continue to operate in CPU Idle mode
bit 7 ICTMR: Input Capture x Timer Select bit
1 = TMR2 contents are captured on capture event
0 = TMR3 contents are captured on capture event
bit 6-5 ICI<1:0>: Select Number of Captures per Interrupt bits
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
bit 4 ICOV: Input Capture x Overflow Status Flag bit (read-only)
1 = Input capture overflow occurred
0 = No input capture overflow occurred
bit 3 ICBNE: Input Capture x Buffer Empty Status bit (read-only)
1 = Input capture buffer is not empty, at least one more capture value can be read
0 = Input capture buffer is empty
bit 2-0 ICM<2:0>: Input Capture x Mode Select bits(1)
111 = Input capture functions as interrupt pin only when device is in Sleep or Idle mode (rising edge
detect only, all other control bits are not applicable)
110 = Unused (module is disabled)
101 = Capture mode, every 16th rising edge
100 = Capture mode, every 4th rising edge
011 = Capture mode, every rising edge
010 = Capture mode, every falling edge
001 = Capture mode, every edge (rising and falling) – ICI<1:0> bits do not control interrupt generation
for this mode
000 = Input capture module is turned off
Note 1: RPINRx (ICxRx) must be configured to an available RPn pin. For more information, see Section 10.4
“Peripheral Pin Select (PPS)”.

14.0 OUTPUT COMPARE 10. To initiate another single pulse output, change the
Timer and Compare register settings, if needed,
Note: This data sheet summarizes the features of and then issue a write to set the OCMx bits to
this group of PIC24F devices. It is not ‘100’. Disabling and re-enabling the timer and
intended to be a comprehensive reference clearing the TMRy register are not required, but
source. For more information, refer to the may be advantageous for defining a pulse from a
“PIC24F Family Reference Manual”, known event time boundary.
“Output Compare” (DS39706).
The output compare module does not have to be dis-
abled after the falling edge of the output pulse. Another
14.1 Setup for Single Output Pulse pulse can be initiated by rewriting the value of the
Generation OCxCON register.
When the OCM<2:0> control bits (OCxCON<2:0>) are
14.2 Setup for Continuous Output
set to ‘100’, the selected output compare channel
initializes the OCx pin to the low state and generates a Pulse Generation
single output pulse. When the OCM<2:0> control bits (OCxCON<2:0>) are
To generate a single output pulse, the following steps set to ‘101’, the selected output compare channel initial-
are required (these steps assume the timer source is izes the OCx pin to the low state and generates output
initially turned off, but this is not a requirement for the pulses on each and every compare match event.
module operation): For the user to configure the module for the generation
1. Determine the instruction clock cycle time. Take of a continuous stream of output pulses, the following
into account the frequency of the external clock steps are required (these steps assume the timer
to the timer source (if one is used) and the timer source is initially turned off, but this is not a requirement
prescaler settings. for the module operation):
2. Calculate the time to the rising edge of the output 1. Determine the instruction clock cycle time. Take
pulse relative to the TMRy start value (0000h). into account the frequency of the external clock
3. Calculate the time to the falling edge of the pulse to the timer source (if one is used) and the timer
based on the desired pulse width and the time to prescaler settings.
the rising edge of the pulse. 2. Calculate the time to the rising edge of the output
4. Write the values computed in Steps 2 and 3 pulse relative to the TMRy start value (0000h).
above into the Output Compare x register, 3. Calculate the time to the falling edge of the pulse
OCxR, and the Output Compare x Secondary based on the desired pulse width and the time to
register, OCxRS, respectively. the rising edge of the pulse.
5. Set the Timery Period register, PRy, to a value 4. Write the values computed in Steps 2 and 3 above
equal to or greater than the value in OCxRS, the into the Output Compare x register, OCxR, and
Output Compare x Secondary register. the Output Compare x Secondary register,
6. Set the OCMx bits to ‘100’ and the OCTSEL OCxRS, respectively.
(OCxCON<3>) bit to the desired timer source. 5. Set the Timery Period register, PRy, to a value
The OCx pin state will now be driven low. equal to or greater than the value in OCxRS.
7. Set the TON (TyCON<15>) bit to ‘1’, which 6. Set the OCMx bits to ‘101’ and the OCTSEL bit to
enables the compare time base to count. the desired timer source. The OCx pin state will
8. Upon the first match between TMRy and OCxR, now be driven low.
the OCx pin will be driven high. 7. Enable the compare time base by setting the TON
9. When the incrementing timer, TMRy, matches the (TyCON<15>) bit to ‘1’.
Output Compare x Secondary register, OCxRS, 8. Upon the first match between TMRy and OCxR,
the second and trailing edge (high-to-low) of the the OCx pin will be driven high.
pulse is driven onto the OCx pin. No additional 9. When the compare time base, TMRy, matches the
pulses are driven onto the OCx pin and it remains OCxRS, the second and trailing edge (high-to-low)
at low. As a result of the second compare match of the pulse is driven onto the OCx pin.
event, the OCxIF interrupt flag bit is set, which 10. As a result of the second compare match event,
will result in an interrupt if it is enabled, by the OCxIF interrupt flag bit set.
setting the OCxIE bit. For further information 11. When the compare time base and the value in its
on peripheral interrupts, refer to Section 7.0 respective Timery Period register match, the
“Interrupt Controller”. TMRy register resets to 0x0000 and resumes
counting.
12. Steps 8 through 11 are repeated and a continuous
stream of pulses is generated indefinitely. The
OCxIF flag is set on each OCxRS/TMRy compare
match event.

14.3 Pulse-Width Modulation Mode EQUATION 14-1: CALCULATING THE PWM
PERIOD(1)
Note: This peripheral contains input and output
functions that may need to be configured PWM Period = [(PRy) + 1] • TCY • (Timer Prescale Value)
by the Peripheral Pin Select. See Where:
Section 10.4 “Peripheral Pin Select PWM Frequency = 1/[PWM Period]
(PPS)” for more information.
Note 1: Based on TCY = 2 * TOSC; Doze mode
The following steps should be taken when configuring and PLL are disabled.
the output compare module for PWM operation:
1. Set the PWM period by writing to the selected
Timery Period register (PRy). Note: A PRy value of N will produce a PWM
period of N + 1 time base count cycles. For
2. Set the PWM duty cycle by writing to the OCxRS
example, a value of 7 written into the PRy
register.
register will yield a period consisting of
3. Write the OCxR register with the initial duty cycle. 8 time base cycles.
4. Enable interrupts, if required, for the timer and
output compare modules. The output compare 14.3.2 PWM DUTY CYCLE
interrupt is required for PWM Fault pin utilization.
5. Configure the output compare module for one The PWM duty cycle is specified by writing to the
of two PWM Operation modes by writing to the OCxRS register. The OCxRS register can be written to
Output Compare Mode bits, OCM<2:0> at any time, but the duty cycle value is not latched into
(OCxCON<2:0>). OCxR until a match between PRy and TMRy occurs
(i.e., the period is complete). This provides a double
6. Set the TMRy prescale value and enable the time
buffer for the PWM duty cycle and is essential for glitch-
base by setting TON (TyCON<15>) = 1.
less PWM operation. In the PWM mode, OCxR is a
Note: The OCxR register should be initialized read-only register.
before the output compare module is first Some important boundary parameters of the PWM duty
enabled. The OCxR register becomes a cycle include:
read-only Duty Cycle register when the
• If the Output Compare x register, OCxR, is loaded
module is operated in the PWM modes.
with 0000h, the OCx pin will remain low (0% duty
The value held in OCxR will become the
cycle).
PWM duty cycle for the first PWM period.
The contents of the Output Compare x • If OCxR is greater than PRy (Timery Period
Secondary register, OCxRS, will not be register), the pin will remain high (100% duty
transferred into OCxR until a time base cycle).
period match occurs. • If OCxR is equal to PRy, the OCx pin will be low
for one time base count value and high for all
14.3.1 PWM PERIOD other count values.
The PWM period is specified by writing to PRy, the See Example 14-1 for PWM mode timing details.
Timery Period register. The PWM period can be Table 14-1 and Table 14-2 show example PWM
calculated using Equation 14-1. frequencies and resolutions for a device operating at
4 and 16 MIPS.
EQUATION 14-2: CALCULATION FOR MAXIMUM PWM RESOLUTION(1)
log10 (F PWM
FCY
)
• (Timer Prescale Value)
bits
Maximum PWM Resolution (bits) =
log10(2)
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.

EXAMPLE 14-1: PWM PERIOD AND DUTY CYCLE CALCULATIONS(1)
1. Find the Timer Period register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL
(32 MHz device clock rate) and a Timer2 prescaler setting of 1:1.
TCY = 2 • TOSC = 62.5 ns
PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 s
PWM Period = (PR2 + 1) • TCY • (Timer2 Prescale Value)
19.2 s = (PR2 + 1) • 62.5 ns • 1
PR2 = 306
2. Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz device clock rate:
PWM Resolution = log10 (FCY/FPWM)/log102) bits
= (log10 (16 MHz/52.08 kHz)/log102) bits
= 8.3 bits
Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled.
TABLE 14-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)(1)
PWM Frequency 7.6 Hz 61 Hz 122 Hz 977 Hz 3.9 kHz 31.3 kHz 125 kHz
Timer Prescaler Ratio 8 1 1 1 1 1 1
Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh
Resolution (bits) 16 16 15 12 10 7 5
TABLE 14-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)(1)
PWM Frequency 30.5 Hz 244 Hz 488 Hz 3.9 kHz 15.6 kHz 125 kHz 500 kHz
Timer Prescaler Ratio 8 1 1 1 1 1 1
Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh
Resolution (bits) 16 16 15 12 10 7 5

FIGURE 14-1: OUTPUT COMPARE x MODULE BLOCK DIAGRAM
Set Flag bit

OCxIF(1)
OCxRS(1)
OCx(1)
OCxR (1) Output S Q
Logic R
Output Enable
3
OCM<2:0> OCFA or OCFB(2)
Comparator Mode Select(4)
0 1 OCTSEL 0 1
16 16
TMR Register Inputs Period Match Signals

from Time Bases from Time Bases
(see Note 3) (see Note 3)
Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective Output Compare
Channels 1 through 5.
2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel.
3: Each output compare channel can use one of two selectable time bases. Refer to the device data sheet for
the time bases associated with the module.
4: This peripheral’s inputs and outputs must be assigned to an available RPn pin before use. Please see

14.4 Output Compare Register
REGISTER 14-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
— — OCSIDL — — — — —
bit 15 bit 8
U-0 U-0 U-0 R-0, HC R/W-0 R/W-0 R/W-0 R/W-0

(1) (1)
— — — OCFLT OCTSEL OCM2 OCM1 OCM0(1)
bit 7 bit 0


bit 13 OCSIDL: Output Compare x Stop in Idle Mode Control bit
1 = Output Compare x halts in CPU Idle mode
0 = Output Compare x continues to operate in CPU Idle mode
bit 4 OCFLT: PWM Fault Condition Status bit
1 = PWM Fault condition has occurred (cleared in HW only)
0 = No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111)
bit 3 OCTSEL: Output Compare x Timer Select bit
1 = Timer3 is the clock source for Output Compare x
0 = Timer2 is the clock source for Output Compare x
Refer to the device data sheet for specific time bases available to the output compare module.
bit 2-0 OCM<2:0>: Output Compare x Mode Select bits(1)
111 = PWM mode on OCx; Fault pin, OCFx, is enabled(2)
110 = PWM mode on OCx; Fault pin, OCFx, is disabled(2)
101 = Initializes OCx pin low, generates continuous output pulses on OCx pin
100 = Initializes OCx pin low, generates single output pulse on OCx pin
011 = Compare event toggles OCx pin
010 = Initializes OCx pin high, compare event forces OCx pin low
001 = Initializes OCx pin low, compare event forces OCx pin high
000 = Output compare channel is disabled
Note 1: RPORx (OCx) must be configured to an available RPn pin. For more information, see Section 10.4
“Peripheral Pin Select (PPS)”.
2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel.

NOTES:

15.0 SERIAL PERIPHERAL To set up the SPIx module for the Standard Master
mode of operation:
INTERFACE (SPI)
1. If using interrupts:
Note: This data sheet summarizes the features of a) Clear the SPIxIF bit in the respective IFSx
this group of PIC24F devices. It is not register.
b) Set the SPIxIE bit in the respective IECx
register.
“Serial Peripheral Interface (SPI)” c) Write the SPIxIP bits in the respective IPCx
(DS39699) register to set the interrupt priority.
2. Write the desired settings to the SPIxCON1
The Serial Peripheral Interface (SPI) module is a and SPIxCON2 registers with the MSTEN bit
synchronous serial interface useful for communicating (SPIxCON1<5>) = 1.
with other peripheral or microcontroller devices. These 3. Clear the SPIROV bit (SPIxSTAT<6>).
peripheral devices may be serial EEPROMs, shift reg-
4. Enable SPIx operation by setting the SPIEN bit
isters, display drivers, A/D Converters, etc. The SPI
(SPIxSTAT<15>).
module is compatible with the SPI and SIOP Motorola®
interfaces. 5. Write the data to be transmitted to the SPIxBUF
register. Transmission (and reception) will start
The module supports operation in two buffer modes. In as soon as data is written to the SPIxBUF
Standard mode, data is shifted through a single serial register.
buffer. In Enhanced Buffer mode, data is shifted
through an 8-level FIFO buffer. To set up the SPIx module for the Standard Slave mode
of operation:
Note: Do not perform read-modify-write opera-
1. Clear the SPIxBUF register.
tions (such as bit-oriented instructions) on
the SPIxBUF register in either Standard or 2. If using interrupts:
Enhanced Buffer mode. a) Clear the SPIxIF bit in the respective IFSx
register.
The module also supports a basic framed SPI protocol
b) Set the SPIxIE bit in the respective IECx
while operating in either Master or Slave mode. A total
register.
of four framed SPI configurations are supported.
c) Write the SPIxIP bits in the respective IPCx
The SPI serial interface consists of four pins: register to set the interrupt priority.
• SDIx: Serial Data Input 3. Write the desired settings to the SPIxCON1
• SDOx: Serial Data Output and SPIxCON2 registers with the MSTEN bit
• SCKx: Shift Clock Input or Output (SPIxCON1<5>) = 0.
• SSx: Active-Low Slave Select or Frame 4. Clear the SMP bit (SPIxCON1<9>).
Synchronization I/O Pulse 5. If the CKE bit is set, then the SSEN bit
(SPIxCON1<7>) must be set to enable the SSx
The SPI module can be configured to operate using 2,
pin.
3 or 4 pins. In the 3-pin mode, SSx is not used. In the
2-pin mode, both SDOx and SSx are not used. 6. Clear the SPIROV bit (SPIxSTAT<6>).
7. Enable SPIx operation by setting the SPIEN bit
Block diagrams of the module in Standard and
(SPIxSTAT<15>).
Enhanced modes are shown in Figure 15-1 and
Figure 15-2.
Depending on the pin count, PIC24FJ64GA004 family
devices offer one or two SPI modules on a single
device.
Note: In this section, the SPI modules are
referred to together as SPIx or separately
as SPI1 and SPI2. Special Function Reg-
isters will follow a similar notation. For
example, SPIxCON1 or SPIxCON2 refers
to the control register for the SPI1 or SPI2
module.

FIGURE 15-1: SPIx MODULE BLOCK DIAGRAM (STANDARD MODE)
SCKx 1:1 to 1:8 1:1/4/16/64

Secondary Primary FCY
Prescaler Prescaler
SSx/FSYNCx
Sync Control Select
Control Clock Edge SPIxCON1<1:0>
Shift Control SPIxCON1<4:2>

SDOx
Enable
SDIx bit 0 Master Clock
SPIxSR
Transfer Transfer
SPIxBUF
Read SPIxBUF Write SPIxBUF
16
Internal Data Bus

To set up the SPIx module for the Enhanced Buffer To set up the SPIx module for the Enhanced Buffer
Master mode of operation: Slave mode of operation:
1. If using interrupts: 1. Clear the SPIxBUF register.
a) Clear the SPIxIF bit in the respective IFSx 2. If using interrupts:
register. • Clear the SPIxIF bit in the respective IFSx
b) Set the SPIxIE bit in the respective IECx register.
register. • Set the SPIxIE bit in the respective IECx
c) Write the SPIxIP bits in the respective IPCx register.
register. • Write the SPIxIP bits in the respective IPCx
2. Write the desired settings to the SPIxCON1 and register to set the interrupt priority.
SPIxCON2 registers with the MSTEN bit 3. Write the desired settings to the SPIxCON1 and
(SPIxCON1<5>) = 1. SPIxCON2 registers with the MSTEN bit
3. Clear the SPIROV bit (SPIxSTAT<6>). (SPIxCON1<5>) = 0.
4. Select Enhanced Buffer mode by setting the 4. Clear the SMP bit.
SPIBEN bit (SPIxCON2<0>). 5. If the CKE bit is set, then the SSEN bit must be
5. Enable SPIx operation by setting the SPIEN bit set, thus enabling the SSx pin.
(SPIxSTAT<15>). 6. Clear the SPIROV bit (SPIxSTAT<6>).
6. Write the data to be transmitted to the SPIxBUF 7. Select Enhanced Buffer mode by setting the
register. Transmission (and reception) will start SPIBEN bit (SPIxCON2<0>).
as soon as data is written to the SPIxBUF 8. Enable SPIx operation by setting the SPIEN bit
register. (SPIxSTAT<15>).
FIGURE 15-2: SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)
SCKx 1:1 to 1:8 1:1/4/16/64

Secondary Primary FCY
Prescaler Prescaler
SSx/FSYNCx
Sync Control Select
Control Clock Edge SPIxCON1<1:0>
Shift Control SPIxCON1<4:2>

SDOx
Enable
bit 0 Master Clock
SDIx
SPIxSR
Transfer Transfer
8-Level FIFO 8-Level FIFO

Receive Buffer Transmit Buffer
SPIxBUF
Read SPIxBUF Write SPIxBUF
16
Internal Data Bus

REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 R-0 R-0 R-0
(1)
SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0
bit 15 bit 8
R-0 R/C-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0

SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF
bit 7 bit 0

bit 15 SPIEN: SPIx Enable bit(1)

1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables module
bit 13 SPISIDL: SPIx Stop in Idle Mode bit
bit 10-8 SPIBEC<2:0>: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode)
Master mode:
Number of SPI transfers pending.
Slave mode:
Number of SPI transfers unread.
bit 7 SRMPT: SPIx Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode)
1 = SPIx Shift register is empty and ready to send or receive
0 = SPIx Shift register is not empty
bit 6 SPIROV: SPIx Receive Overflow Flag bit
1 = A new byte/word is completely received and discarded; the user software has not read the previous
data in the SPIxBUF register
0 = No overflow has occurred
bit 5 SRXMPT: SPIx Receive FIFO Empty bit (valid in Enhanced Buffer mode)
1 = Receive FIFO is empty
0 = Receive FIFO is not empty
bit 4-2 SISEL<2:0>: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)
111 = Interrupt when the SPIx transmit buffer is full (SPITBF bit is set)
110 = Interrupt when the last bit is shifted into SPIxSR; as a result, the TX FIFO is empty
101 = Interrupt when the last bit is shifted out of SPIxSR; now the transmit is complete
100 = Interrupt when one data is shifted into the SPIxSR; as a result, the TX FIFO has one open spot
011 = Interrupt when the SPIx receive buffer is full (SPIRBF bit set)
010 = Interrupt when the SPIx receive buffer is 3/4 or more full
001 = Interrupt when data is available in the receive buffer (SRMPT bit is set)
000 = Interrupt when the last data in the receive buffer is read; as a result, the buffer is empty
(SRXMPT bit is set)
Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 10.4

REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED)
bit 1 SPITBF: SPIx Transmit Buffer Full Status bit
1 = Transmit has not yet started, SPIxTXB is full
0 = Transmit has started, SPIxTXB is empty
In Standard Buffer mode:
Automatically set in hardware when CPU writes the SPIxBUF location, loading SPIxTXB. Automatically
cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR.
In Enhanced Buffer mode:
Automatically set in hardware when CPU writes the SPIxBUF location, loading the last available buffer
location. Automatically cleared in hardware when a buffer location is available for a CPU write.
bit 0 SPIRBF: SPIx Receive Buffer Full Status bit
1 = Receive is complete, SPIxRXB is full
0 = Receive is not complete, SPIxRXB is empty
In Standard Buffer mode:
Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically
cleared in hardware when the core reads the SPIxBUF location, reading SPIxRXB.
In Enhanced Buffer mode:
Automatically set in hardware when SPIx transfers data from SPIxSR to the buffer, filling the last unread
buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from
SPIxSR.
Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 10.4

REGISTER 15-2: SPIxCON1: SPIx CONTROL REGISTER 1
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — DISSCK(1) DISSDO(2) MODE16 SMP CKE(3)
bit 15 bit 8

SSEN(4) CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0
bit 7 bit 0
Legend:

bit 12 DISSCK: Disables SCKx Pin bit (SPI Master modes only)(1)
1 = Internal SPI clock is disabled; pin functions as I/O
0 = Internal SPI clock is enabled
bit 11 DISSDO: Disables SDOx Pin bit(2)
1 = SDOx pin is not used by the module; pin functions as I/O
0 = SDOx pin is controlled by the module
bit 10 MODE16: Word/Byte Communication Select bit
1 = Communication is word-wide (16 bits)
0 = Communication is byte-wide (8 bits)
bit 9 SMP: SPIx Data Input Sample Phase bit
Master mode:
1 = Input data is sampled at end of data output time
0 = Input data is sampled at middle of data output time
Slave mode:
SMP must be cleared when SPIx is used in Slave mode.
bit 8 CKE: SPIx Clock Edge Select bit(3)
1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6)
0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6)
bit 7 SSEN: Slave Select Enable bit (Slave mode)(4)
1 = SSx pin is used for Slave mode
0 = SSx pin is not used by the module; pin is controlled by port function
bit 6 CKP: Clock Polarity Select bit
1 = Idle state for the clock is a high level; active state is a low level
0 = Idle state for the clock is a low level; active state is a high level
bit 5 MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
Note 1: If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin
Select (PPS)” for more information.
2: If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin
3: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed
SPI modes (FRMEN = 1).
4: If SSEN = 1, SSx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select

REGISTER 15-2: SPIxCON1: SPIx CONTROL REGISTER 1 (CONTINUED)
bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)
111 = Secondary prescale 1:1
...
bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)
11 = Primary prescale 1:1
Note 1: If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin
2: If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin
3: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed
SPI modes (FRMEN = 1).
4: If SSEN = 1, SSx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select
REGISTER 15-3: SPIxCON2: SPIx CONTROL REGISTER 2

R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
FRMEN SPIFSD SPIFPOL — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — — SPIFE SPIBEN
bit 7 bit 0
Legend:
bit 15 FRMEN: Framed SPIx Support bit

1 = Framed SPIx support is enabled
0 = Framed SPIx support is disabled
bit 14 SPIFSD: SPIx Frame Sync Pulse Direction Control on SSx Pin bit
1 = Frame sync pulse input (slave)
0 = Frame sync pulse output (master)
bit 13 SPIFPOL: SPIx Frame Sync Pulse Polarity bit (Frame mode only)
1 = Frame sync pulse is active-high
0 = Frame sync pulse is active-low
bit 1 SPIFE: SPIx Frame Sync Pulse Edge Select bit
1 = Frame sync pulse coincides with first bit clock
0 = Frame sync pulse precedes first bit clock
bit 0 SPIBEN: SPIx Enhanced Buffer Enable bit
1 = Enhanced Buffer is enabled
0 = Enhanced Buffer is disabled (Legacy mode)

FIGURE 15-3: SPIx MASTER/SLAVE CONNECTION (STANDARD MODE)
PROCESSOR 1 (SPI Master) PROCESSOR 2 (SPI Slave)
SDOx SDIx
Serial Receive Buffer Serial Receive Buffer

(SPIxRXB)(2) (SPIxRXB)(2)
Shift Register SDIx SDOx Shift Register

(SPIxSR) (SPIxSR)
MSb LSb MSb LSb
Serial Transmit Buffer Serial Transmit Buffer

(SPIxTXB)(2) (SPIxTXB)(2)
Serial Clock
SPIx Buffer SCKx SCKx SPIx Buffer
(SPIxBUF)(2) (SPIxBUF)(2)
SSx(1)
MSTEN (SPIxCON1<5>) = 1) SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0
Note 1: Using the SSx pin in Slave mode of operation is optional.

2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory
mapped to SPIxBUF.
FIGURE 15-4: SPIx MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES)
PROCESSOR 1 (SPI Enhanced Buffer Master) PROCESSOR 2 (SPI Enhanced Buffer Slave)
SDOx SDIx
Shift Register SDIx SDOx Shift Register

(SPIxSR) (SPIxSR)
MSb LSb MSb LSb
8-Level FIFO Buffer 8-Level FIFO Buffer
SPIx Buffer Serial Clock SPIx Buffer

(SPIxBUF)(2) SCKx SCKx (SPIxBUF)(2)
SSx SSx(1)
MSTEN (SPIxCON1<5>) = 1 and SSEN (SPIxCON1<7>) = 1,

SPIBEN (SPIxCON2<0>) = 1 MSTEN (SPIxCON1<5>) = 0 and
SPIBEN (SPIxCON2<0>) = 1
Note 1: Using the SSx pin in Slave mode of operation is optional.

2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory
mapped to SPIxBUF.

FIGURE 15-5: SPIx MASTER, FRAME MASTER CONNECTION DIAGRAM
PIC24F PROCESSOR 2
(SPI Slave, Frame Slave)
SDOx SDIx
SDIx SDOx
Serial Clock
SCKx SCKx
SSx SSx
Frame Sync
Pulse
FIGURE 15-6: SPIx MASTER, FRAME SLAVE CONNECTION DIAGRAM
PIC24F PROCESSOR 2
SPI Master, Frame Slave)
SDOx SDIx
SDIx SDOx
Serial Clock
SCKx SCKx
SSx SSx
Frame Sync
Pulse
FIGURE 15-7: SPIx SLAVE, FRAME MASTER CONNECTION DIAGRAM
PIC24F PROCESSOR 2
(SPI Slave, Frame Slave)
SDOx SDIx
SDIx SDOx
Serial Clock
SCKx SCKx
SSx SSx
Frame Sync
Pulse
FIGURE 15-8: SPIx SLAVE, FRAME SLAVE CONNECTION DIAGRAM
PIC24F PROCESSOR 2
(SPI Master, Frame Slave)
SDOx SDIx
SDIx SDOx
Serial Clock
SCKx SCKx
SSx SSx
Frame Sync
Pulse

EQUATION 15-1: RELATIONSHIP BETWEEN DEVICE AND SPIx CLOCK SPEED(1)
FCY
FSCK =
Primary Prescaler * Secondary Prescaler
TABLE 15-1: SAMPLE SCKx FREQUENCIES(1,2)

Secondary Prescaler Settings
FCY = 16 MHz
1:1 2:1 4:1 6:1 8:1
Primary Prescaler Settings 1:1 Invalid 8000 4000 2667 2000
4:1 4000 2000 1000 667 500
16:1 1000 500 250 167 125
64:1 250 125 63 42 31
FCY = 5 MHz
Primary Prescaler Settings 1:1 5000 2500 1250 833 625
4:1 1250 625 313 208 156
16:1 313 156 78 52 39
64:1 78 39 20 13 10
2: SCKx frequencies are shown in kHz.

16.0 INTER-INTEGRATED CIRCUIT 16.2 Communicating as a Master in a
(I2C™) Single Master Environment
Note: This data sheet summarizes the features of The details of sending a message in Master mode
this group of PIC24F devices. It is not depends on the communications protocol for the device
intended to be a comprehensive reference being communicated with. Typically, the sequence of
source. For more information, refer to events is as follows:
the “PIC24F Family Reference Manual”, 1. Assert a Start condition on SDAx and SCLx.
“Inter-Integrated Circuit™ (I2C™)” 2. Send the I 2C device address byte to the slave
(DS39702). with a write indication.
The Inter-Integrated Circuit™ (I2C™) module is a serial 3. Wait for and verify an Acknowledge from the
interface useful for communicating with other periph- slave.
eral or microcontroller devices. These peripheral 4. Send the first data byte (sometimes known as
devices may be serial EEPROMs, display drivers, A/D the command) to the slave.
Converters, etc. 5. Wait for and verify an Acknowledge from the
The I 2C
module supports these features: slave.
6. Send the serial memory address low byte to the
• Independent master and slave logic
slave.
• 7-bit and 10-bit device addresses
7. Repeat Steps 4 and 5 until all data bytes are
• General call address, as defined in the I2C protocol sent.
• Clock stretching to provide delays for the 8. Assert a Repeated Start condition on SDAx and
processor to respond to a slave data request SCLx.
• Both 100 kHz and 400 kHz bus specifications 9. Send the device address byte to the slave with
• Configurable address masking a read indication.
• Multi-Master modes to prevent loss of messages 10. Wait for and verify an Acknowledge from the
in arbitration slave.
• Bus Repeater mode, allowing the acceptance of 11. Enable master reception to receive serial
all messages as a slave regardless of the address memory data.
• Automatic SCL 12. Generate an ACK or NACK condition at the end
A block diagram of the module is shown in Figure 16-1. of a received byte of data.
13. Generate a Stop condition on SDAx and SCLx.
16.1 Peripheral Remapping Options
The I2 C
modules are tied to fixed pin assignments and
cannot be reassigned to alternate pins using Peripheral
Pin Select. To allow some flexibility with peripheral
multiplexing, the I2C1 module in all devices can be
reassigned to the alternate pins, designated as ASCL1
and ASDA1, during device configuration.
Pin assignment is controlled by the I2C1SEL Configu-
ration bit; programming this bit (= 0) multiplexes the
module to the ASCL1 and ASDA1 pins.

FIGURE 16-1: I2C™ BLOCK DIAGRAM
Internal
Data Bus
I2CxRCV
Read
Shift
SCLx Clock
I2CxRSR
LSB
SDAx Address Match

Match Detect Write
I2CxMSK
Write Read
I2CxADD
Read
Start and Stop

Bit Detect
Write
Start and Stop

Bit Generation I2CxSTAT
Control Logic
Read
Collision Write
Detect
I2CxCON
Acknowledge
Generation Read
Clock
Stretching
Write
I2CxTRN
LSB
Read
Shift Clock
Reload
Control
Write
BRG Down Counter I2CxBRG
Read
TCY/2

16.3 Setting Baud Rate When 16.4 Slave Address Masking
Operating as a Bus Master The I2CxMSK register (Register 16-3) designates
To compute the Baud Rate Generator reload value, use address bit positions as “don’t care” for both 7-Bit and
Equation 16-1. 10-Bit Addressing modes. Setting a particular bit loca-
tion (= 1) in the I2CxMSK register causes the slave
EQUATION 16-1: COMPUTING BAUD RATE module to respond whether the corresponding address
bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK
RELOAD VALUE(1)
is set to ‘00100000’, the slave module will detect both
addresses, ‘00000000’ and ‘00100000’.
FCY
FSCL = ---------------------------------------------------------------------
-
FCY - To enable address masking, the IPMI (Intelligent
I2CxBRG + 1 + -----------------------------
10 000 000 Peripheral Management Interface) must be disabled by
or clearing the IPMIEN bit (I2CxCON<11>).
Note: As a result of changes in the I2C™ proto-
I2CxBRG =  ------------ – ------------------------------ – 1
FCY FCY
 FSCL 10 000 000 col, the addresses in Table 16-2 are
reserved and will not be Acknowledged in
Note 1: Based on FCY = FOSC/2; Doze mode Slave mode. This includes any address
and PLL are disabled. mask settings that include any of these
addresses.
TABLE 16-1: I2C™ CLOCK RATES(1)

Required I2CxBRG Value
Actual
System FCY
(Decimal) (Hexadecimal) FSCL
FSCL
100 kHz 16 MHz 157 9D 100 kHz
100 kHz 8 MHz 78 4E 100 kHz
100 kHz 4 MHz 39 27 99 kHz
400 kHz 16 MHz 37 25 404 kHz
400 kHz 8 MHz 18 12 404 kHz
400 kHz 4 MHz 9 9 385 kHz
400 kHz 2 MHz 4 4 385 kHz
1 MHz 16 MHz 13 D 1.026 MHz
1 MHz 8 MHz 6 6 1.026 MHz
1 MHz 4 MHz 3 3 0.909 MHz
TABLE 16-2: I2C™ RESERVED ADDRESSES(1)

Slave R/W
Description
Address Bit
0000 000 0 General Call Address(2)
0000 000 1 Start Byte
0000 001 x Cbus Address
0000 010 x Reserved
0000 011 x Reserved
0000 1xx x HS Mode Master Code
1111 1xx x Reserved
1111 0xx x 10-Bit Slave Upper Byte(3)
Note 1: The address bits listed here will never cause an address match, independent of the address mask settings.
2: The address will be Acknowledged only if GCEN = 1.
3: A match on this address can only occur on the upper byte in 10-Bit Addressing mode.

REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0
I2CEN — I2CSIDL SCLREL(1) IPMIEN A10M DISSLW SMEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC

GCEN STREN(1) ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0

bit 15 I2CEN: I2Cx Enable bit

1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0 = Disables the I2Cx module; all I2C™ pins are controlled by port functions
bit 13 I2CSIDL: I2Cx Stop in Idle Mode bit
1 = Discontinues module operation when device enters an Idle mode
bit 12 SCLREL: SCLx Release Control bit (when operating as I2C Slave)(1)
1 = Releases SCLx clock
0 = Holds SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear
at the beginning of slave transmission. Hardware is clear at the end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware is clear at the beginning of slave
transmission.
bit 11 IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit
1 = IPMI Support mode is enabled; all addresses are Acknowledged
0 = IPMI mode is disabled
bit 10 A10M: 10-Bit Slave Addressing bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
bit 9 DISSLW: Disable Slew Rate Control bit
1 = Slew rate control is disabled
0 = Slew rate control is enabled
bit 8 SMEN: SMBus Input Levels bit
1 = Enables I/O pin thresholds compliant with the SMBus specification
0 = Disables the SMBus input thresholds
bit 7 GCEN: General Call Enable bit (when operating as I2C slave)
1 = Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for
reception)
0 = General call address is disabled
bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)(1)
Used in conjunction with the SCLREL bit.
1 = Enables software or receive clock stretching
0 = Disables software or receive clock stretching
Note 1: In Slave mode, the module will not automatically clock stretch after receiving the address byte.

REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that will be transmitted when the software initiates an Acknowledge sequence.
1 = Sends a NACK during Acknowledge
0 = Sends an ACK during Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master, applicable during master receive)
1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits the ACKDT data bit.
Hardware is clear at the end of master Acknowledge sequence.
0 = Acknowledge sequence is not in progress
bit 3 RCEN: Receive Enable bit (when operating as I2C master)
1 = Enables Receive mode for I2C. Hardware is clear at the end of eighth bit of master receive data byte.
0 = Receive sequence is not in progress
bit 2 PEN: Stop Condition Enable bit (when operating as I2C master)
1 = Initiates Stop condition on SDAx and SCLx pins. Hardware is clear at the end of master Stop sequence.
0 = Stop condition is not in progress
bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1 = Initiates Repeated Start condition on SDAx and SCLx pins. Hardware is clear at the end of master
Repeated Start sequence.
0 = Repeated Start condition is not in progress
bit 0 SEN: Start Condition Enable bit (when operating as I2C master)
1 = Initiates Start condition on SDAx and SCLx pins. Hardware is clear at the end of master Start sequence.
0 = Start condition is not in progress
Note 1: In Slave mode, the module will not automatically clock stretch after receiving the address byte.

REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER
R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC
ACKSTAT(1) TRSTAT — — — BCL GCSTAT ADD10
bit 15 bit 8
R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC
IWCOL I2COV D/A P S R/W RBF TBF
bit 7 bit 0
Legend: C = Clearable bit HS = Hardware Settable bit

HSC = Hardware Settable/Clearable bit
bit 15 ACKSTAT: Acknowledge Status bit(1)

1 = NACK was detected last
0 = ACK was detected last
Hardware is set or clear at the end of Acknowledge.
bit 14 TRSTAT: Transmit Status bit (when operating as I2C™ master, applicable to master transmit operation)
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware is set at the beginning of master transmission. Hardware is clear at the end of slave Acknowledge.
bit 10 BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No collision
Hardware is set at the detection of bus collision.
bit 9 GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware is set when an address matches the general call address. Hardware is clear at Stop detection.
bit 8 ADD10: 10-Bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware is set at the match of the 2nd byte of matched 10-bit address. Hardware is clear at Stop detection.
bit 7 IWCOL: I2Cx Write Collision Detect bit
1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy
0 = No collision
Hardware is set at the occurrence of a write to I2CxTRN while busy (cleared by software).
bit 6 I2COV: I2Cx Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register is still holding the previous byte
0 = No overflow
Hardware is set at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
Note 1: In both Master and Slave modes, the ACKSTAT bit is only updated when transmitting data resulting in the
reception of an ACK or NACK from another device. Do not check the state of ACKSTAT when receiving
data, either as a slave or a master. Reading ACKSTAT after receiving address or data bytes returns an
invalid result.

REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
bit 5 D/A: Data/Address bit (when operating as I2C slave)
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was a device address
Hardware is clear at a device address match. Hardware is set by a write to I2CxTRN or by reception of
a slave byte.
bit 4 P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware is set or clear when Start, Repeated Start or Stop is detected.
bit 3 S: Start bit
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
Hardware is set or clear when Start, Repeated Start or Stop is detected.
bit 2 R/W: Read/Write Information bit (when operating as I2C slave)
1 = Read – Indicates data transfer is output from slave
0 = Write – Indicates data transfer is input to slave
Hardware is set or clear after reception of an I 2C device address byte.
bit 1 RBF: Receive Buffer Full Status bit
1 = Receive is complete, I2CxRCV is full
0 = Receive is not complete, I2CxRCV is empty
Hardware is set when I2CxRCV is written with received byte. Hardware is clear when software reads
I2CxRCV.
bit 0 TBF: Transmit Buffer Full Status bit
1 = Transmit is in progress, I2CxTRN is full
0 = Transmit is complete, I2CxTRN is empty
Hardware is set when software writes I2CxTRN. Hardware is clear at completion of data transmission.
Note 1: In both Master and Slave modes, the ACKSTAT bit is only updated when transmitting data resulting in the
reception of an ACK or NACK from another device. Do not check the state of ACKSTAT when receiving
data, either as a slave or a master. Reading ACKSTAT after receiving address or data bytes returns an
invalid result.
REGISTER 16-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — AMSK9 AMSK8
bit 15 bit 8

AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0
bit 7 bit 0
Legend:

bit 9-0 AMSK<9:0>: Mask for Address Bit x Select bits
1 = Enables masking for bit x of incoming message address; bit match is not required in this position
0 = Disables masking for bit x; bit match is required in this position

NOTES:

17.0 UNIVERSAL ASYNCHRONOUS • Baud Rates Ranging from 1 Mbps to 15 bps at
16 MIPS
RECEIVER TRANSMITTER
• 4-Deep, First-In-First-Out (FIFO) Transmit Data
(UART) Buffer
Note: This data sheet summarizes the features of • 4-Deep FIFO Receive Data Buffer
this group of PIC24F devices. It is not • Parity, Framing and Buffer Overrun Error Detection
intended to be a comprehensive reference • Support for 9-bit mode with Address Detect
source. For more information, refer to the (9th bit = 1)
“PIC24F Family Reference Manual”, • Transmit and Receive Interrupts
“UART” (DS39708).
• Loopback mode for Diagnostic Support
The Universal Asynchronous Receiver Transmitter • Support for Sync and Break Characters
(UART) module is one of the serial I/O modules available • Supports Automatic Baud Rate Detection
in the PIC24F device family. The UART is a full-duplex, • IrDA Encoder and Decoder Logic
asynchronous system that can communicate with
• 16x Baud Clock Output for IrDA Support
peripheral devices, such as personal computers,
LIN/J2602, RS-232 and RS-485 interfaces. The module A simplified block diagram of the UART is shown in
also supports a hardware flow control option with the Figure 17-1. The UART module consists of these key
UxCTS and UxRTS pins, and also includes an IrDA® important hardware elements:
encoder and decoder. • Baud Rate Generator
The primary features of the UART module are: • Asynchronous Transmitter
• Full-Duplex, 8 or 9-Bit Data Transmission through • Asynchronous Receiver
the UxTX and UxRX Pins
Note: In this section, the UART modules are
• Even, Odd or No Parity Options (for 8-bit data)
referred to together as UARTx or
• One or Two Stop bits separately as UART1 and UART2.
• Hardware Flow Control Option with UxCTS and
UxRTS Pins
• Fully Integrated Baud Rate Generator with 16-Bit
Prescaler
FIGURE 17-1: UARTx SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA® BCLKx
Hardware Flow Control UxRTS

UxCTS
UARTx Receiver UxRX
UARTx Transmitter UxTX
Note: This peripheral’s inputs and outputs must be assigned to an available RPn pin before use. Please
see Section 10.4 “Peripheral Pin Select (PPS)” for more information.

17.1 UARTx Baud Rate Generator (BRG) The maximum baud rate (BRGH = 0) possible is
FCY/16 (for UxBRG = 0) and the minimum baud rate
The UARTx module includes a dedicated 16-bit Baud possible is FCY/(16 * 65536).
Rate Generator. The UxBRG register controls the
period of a free-running, 16-bit timer. Equation 17-1 Equation 17-2 shows the formula for computation of
shows the formula for computation of the baud rate the baud rate with BRGH = 1.
with BRGH = 0.
EQUATION 17-2: UARTx BAUD RATE WITH
EQUATION 17-1: UARTx BAUD RATE WITH BRGH = 1(1)
BRGH = 0(1) FCY
Baud Rate =
FCY 4 • (UxBRG + 1)
Baud Rate =
16 • (UxBRG + 1)
FCY
UxBRG = –1
4 • Baud Rate
FCY –1
UxBRG =
16 • Baud Rate
Note 1: Based on FCY = FOSC/2; Doze mode
and PLL are disabled.
Note 1: Based on FCY = FOSC/2; Doze mode
and PLL are disabled.
The maximum baud rate (BRGH = 1) possible is FCY/4
(for UxBRG = 0) and the minimum baud rate possible
Example 17-1 shows the calculation of the baud rate is FCY/(4 * 65536).
error for the following conditions:
Writing a new value to the UxBRG register causes the
• FCY = 4 MHz BRG timer to be reset (cleared). This ensures the BRG
• Desired Baud Rate = 9600 does not wait for a timer overflow before generating the
new baud rate.
EXAMPLE 17-1: BAUD RATE ERROR CALCULATION (BRGH = 0)(1)

Desired Baud Rate = FCY/(16 (UxBRG + 1))
Solving for UxBRG value:
UxBRG = ((FCY/Desired Baud Rate)/16) – 1
UxBRG = ((4000000/9600)/16) – 1
UxBRG = 25
Calculated Baud Rate = 4000000/(16 (25 + 1))
= 9615
Error = (Calculated Baud Rate – Desired Baud Rate)
Desired Baud Rate
= (9615 – 9600)/9600
= 0.16%

17.2 Transmitting in 8-Bit Data Mode 17.5 Receiving in 8-Bit or 9-Bit Data
1. Set up the UARTx:
Mode
a) Write appropriate values for data, parity and 1. Set up the UARTx (as described in Section 17.2
Stop bits. “Transmitting in 8-Bit Data Mode”).
b) Write appropriate baud rate value to the 2. Enable the UARTx.
UxBRG register. 3. A receive interrupt will be generated when one
c) Set up transmit and receive interrupt enable or more data characters have been received as
and priority bits. per interrupt control bits, URXISEL<1:0>.
2. Enable the UARTx. 4. Read the OERR bit to determine if an overrun
3. Set the UTXEN bit (causes a transmit interrupt error has occurred. The OERR bit must be reset
2 cycles after being set). in software.
4. Write data byte to lower byte of UxTXREG word. 5. Read UxRXREG.
The value will be immediately transferred to the The act of reading the UxRXREG character will move
Transmit Shift Register (TSR) and the serial bit the next character to the top of the receive FIFO,
stream will start shifting out with the next rising including a new set of PERR and FERR values.
edge of the baud clock.
5. Alternately, the data byte may be transferred 17.6 Operation of UxCTS and UxRTS
while UTXEN = 0 and then the user may set Control Pins
UTXEN. This will cause the serial bit stream to
begin immediately because the baud clock will UARTx Clear-to-Send (UxCTS) and Request-to-Send
start from a cleared state. (UxRTS) are the two hardware-controlled pins that are
6. A transmit interrupt will be generated as per associated with the UARTx module. These two pins
interrupt control bits, UTXISEL<1:0>. allow the UARTx to operate in Simplex and Flow
Control mode. They are implemented to control the
17.3 Transmitting in 9-Bit Data Mode transmission and reception between the Data Terminal
Equipment (DTE). The UEN<1:0> bits in the UxMODE
1. Set up the UARTx (as described in Section 17.2 register configure these pins.
“Transmitting in 8-Bit Data Mode”).
2. Enable the UARTx. 17.7 Infrared Support
3. Set the UTXEN bit (causes a transmit interrupt
The UARTx module provides two types of infrared
2 cycles after being set).
UART support: one is the IrDA clock output to support
4. Write UxTXREG as a 16-bit value only. external IrDA encoder and decoder device (legacy
5. A word write to UxTXREG triggers the transfer module support), and the other is the full implementa-
of the 9-bit data to the TSR. The serial bit stream tion of the IrDA encoder and decoder. Note that
will start shifting out with the first rising edge of because the IrDA modes require a 16x baud clock, they
the baud clock. will only work when the BRGH bit (UxMODE<3>) is ‘0’.
6. A transmit interrupt will be generated as per the
setting of control bits, UTXISEL<1:0>. 17.7.1 EXTERNAL IrDA SUPPORT – IrDA
CLOCK OUTPUT
17.4 Break and Sync Transmit To support external IrDA encoder and decoder devices,
Sequence the BCLKx pin (same as the UxRTS pin) can be
configured to generate the 16x baud clock. With
The following sequence will send a message frame UEN<1:0> = 11, the BCLKx pin will output the 16x
header made up of a Break, followed by an auto-baud baud clock if the UARTx module is enabled. It can be
Sync byte. used to support the IrDA codec chip.
1. Configure the UARTx for the desired mode.
2. Set UTXEN and UTXBRK – sets up the Break 17.7.2 BUILT-IN IrDA ENCODER AND
character. DECODER
3. Load the UxTXREG with a dummy character to The UARTx has full implementation of the IrDA
initiate transmission (value is ignored). encoder and decoder as part of the UARTx module.
4. Write ‘55h’ to UxTXREG – loads the Sync The built-in IrDA encoder and decoder functionality is
character into the transmit FIFO. enabled using the IREN bit (UxMODE<12>). When
enabled (IREN = 1), the receive pin (UxRX) acts as the
5. After the Break has been sent, the UTXBRK bit
input from the infrared receiver. The transmit pin
is reset by hardware. The Sync character now
(UxTX) acts as the output to the infrared transmitter.
transmits.

REGISTER 17-1: UxMODE: UARTx MODE REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0(3) R/W-0(3)
UARTEN(1) — USIDL IREN(2) RTSMD — UEN1 UEN0
bit 15 bit 8
R/C-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL
bit 7 bit 0
Legend: C = Clearable bit HC = Hardware Clearable bit

bit 15 UARTEN: UARTx Enable bit(1)

1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0 = UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption is
minimal
bit 13 USIDL: UARTx Stop in Idle Mode bit
bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2)
1 = IrDA encoder and decoder are enabled
0 = IrDA encoder and decoder are disabled
bit 11 RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin in Simplex mode
0 = UxRTS pin in Flow Control mode
bit 9-8 UEN<1:0>: UARTx Enable bits(3)
11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin is controlled by PORT latches
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by PORT latches
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins are controlled by PORT
latches
bit 7 WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit
1 = UARTx will continue to sample the UxRX pin; interrupt is generated on falling edge, bit is cleared in
hardware on following rising edge
0 = No wake-up is enabled
bit 6 LPBACK: UARTx Loopback Mode Select bit
1 = Enables Loopback mode
0 = Loopback mode is disabled
bit 5 ABAUD: Auto-Baud Enable bit
1 = Enables baud rate measurement on the next character – requires reception of a Sync field (55h);
cleared in hardware upon completion
0 = Baud rate measurement is disabled or completed
Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See
2: This feature is only available for the 16x BRG mode (BRGH = 0).
3: Bit availability depends on pin availability.

REGISTER 17-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 4 RXINV: Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
bit 3 BRGH: High Baud Rate Enable bit
1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1 PDSEL<1:0>: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0 STSEL: Stop Bit Selection bit
1 = Two Stop bits
0 = One Stop bit
2: This feature is only available for the 16x BRG mode (BRGH = 0).
3: Bit availability depends on pin availability.

REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0 R-1
UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN(1) UTXBF TRMT
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0

URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA
bit 7 bit 0
Legend: C = Clearable bit HC = Hardware Clearable bit

bit 15,13 UTXISEL<1:0>: UARTx Transmission Interrupt Mode Selection bits

11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR) and as a result, the
transmit buffer becomes empty
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least
one character open in the transmit buffer)
bit 14 UTXINV: IrDA® Encoder Transmit Polarity Inversion bit
If IREN = 0:
1 = UxTX Idle state is ‘0’
If IREN = 1:
bit 11 UTXBRK: UARTx Transmit Break bit
1 = Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0 = Sync Break transmission is disabled or completed
bit 10 UTXEN: UARTx Transmit Enable bit(1)
1 = Transmit is enabled, UxTX pin is controlled by UARTx
0 = Transmit is disabled, any pending transmission is aborted and buffer is reset; UxTX pin is controlled
by the PORT register
bit 9 UTXBF: UARTx Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
bit 8 TRMT: Transmit Shift Register Empty bit (read-only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
bit 7-6 URXISEL<1:0>: UARTx Receive Interrupt Mode Selection bits
11 = Interrupt is set on RSR transfer, making the receive buffer full (i.e., has 4 data characters)
10 = Interrupt is set on RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)
0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer;
receive buffer has one or more characters

REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect
0 = Address Detect mode is disabled
bit 4 RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Receiver is active
bit 3 PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character (character at the top of the receive FIFO)
0 = Parity error has not been detected
bit 2 FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character (character at the top of the receive FIFO)
0 = Framing error has not been detected
bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only)
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed (clearing a previously set OERR bit (1  0 transition) will reset
the receiver buffer and the RSR to the empty state)
bit 0 URXDA: UARTx Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data; at least one more character can be read
0 = Receive buffer is empty

REGISTER 17-3: UxTXREG: UARTx TRANSMIT REGISTER
U-x U-x U-x U-x U-x U-x U-x W-x
— — — — — — — UTX8
bit 15 bit 8
W-x W-x W-x W-x W-x W-x W-x W-x

UTX7 UTX6 UTX5 UTX4 UTX3 UTX2 UTX1 UTX0
bit 7 bit 0
Legend:

bit 8 UTX8: UARTx Data of the Transmitted Character bit (in 9-bit mode)
bit 7-0 UTX<7:0>: UARTx Data of the Transmitted Character bits
REGISTER 17-4: UxRXREG: UARTx RECEIVE REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0
— — — — — — — URX8
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

URX7 URX6 URX5 URX4 URX3 URX2 URX1 URX0
bit 7 bit 0
Legend:

bit 8 URX8: UARTx Data of the Received Character bit (in 9-bit mode)
bit 7-0 URX<7:0>: UARTx Data of the Received Character bits

18.0 PARALLEL MASTER PORT Key features of the PMP module include:
(PMP) • Up to 16 Programmable Address Lines
• One Chip Select Line
• Programmable Strobe Options:
intended to be a comprehensive reference - Individual Read and Write Strobes or;
source. For more information, refer to the - Read/Write Strobe with Enable Strobe
“PIC24F Family Reference Manual”, • Address Auto-Increment/Auto-Decrement
“Parallel Master Port (PMP)” (DS39713). • Programmable Address/Data Multiplexing
The Parallel Master Port (PMP) module is a parallel • Programmable Polarity on Control Signals
8-bit I/O module, specifically designed to communicate • Legacy Parallel Slave Port Support
with a wide variety of parallel devices, such as commu- • Enhanced Parallel Slave Support:
nication peripherals, LCDs, external memory devices - Address Support
and microcontrollers. Because the interface to parallel - 4-Byte Deep Auto-Incrementing Buffer
peripherals varies significantly, the PMP is highly
• Programmable Wait States
configurable.
• Selectable Input Voltage Levels
Note: A number of the pins for the PMP are not
present on PIC24FJ64GA004 devices.
Refer to the specific device’s pinout to
determine which pins are available.
FIGURE 18-1: PARALLEL MASTER PORT (PMP) MODULE OVERVIEW
Address Bus
Data Bus
Control Lines
PMA<0>
PIC24F PMALL
Parallel Master Port
PMA<1>
PMALH
(1) Up to 11-Bit Address

PMA<10:2> EEPROM
PMCS1
PMBE
PMRD FIFO
PMRD/PMWR Microcontroller LCD
Buffer
PMWR
PMENB
PMD<7:0>
PMA<7:0>
PMA<15:8>
8-Bit Data
Note 1: PMA<10:2> are not available on 28-pin devices.

REGISTER 18-1: PMCON: PARALLEL PORT CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
(1) (1)
PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0(2) U-0 R/W-0(2) R/W-0 R/W-0 R/W-0

CSF1 CSF0 ALP — CS1P BEP WRSP RDSP
bit 7 bit 0
Legend:
bit 15 PMPEN: PMP Enable bit

1 = PMP is enabled
0 = PMP is disabled, no off-chip access is performed
bit 13 PSIDL: PMP Stop in Idle Mode bit
bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits(1)
11 = Reserved
10 = All 16 bits of address are multiplexed on the PMD<7:0> pins
01 = Lower 8 bits of address are multiplexed on the PMD<7:0> pins, upper 3 bits are multiplexed on
PMA<10:8>
00 = Address and data appear on separate pins
bit 10 PTBEEN: PMP Byte Enable Port Enable bit (16-Bit Master mode)
1 = PMBE port is enabled
0 = PMBE port is disabled
bit 9 PTWREN: PMP Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port is enabled
0 = PMWR/PMENB port is disabled
bit 8 PTRDEN: PMP Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port is enabled
0 = PMRD/PMWR port is disabled
bit 7-6 CSF<1:0>: Chip Select Function bits
11 = Reserved
10 = PMCS1 functions as chip set
01 = Reserved
00 = Reserved
bit 5 ALP: Address Latch Polarity bit(2)
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
bit 3 CS1P: Chip Select 1 Polarity bit(2)
1 = Active-high (PMCS1/PMCS1)
0 = Active-low (PMCS1/PMCS1)
Note 1: PMA<10:2> bits are not available on 28-pin devices.

2: These bits have no effect when their corresponding pins are used as address lines.

REGISTER 18-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)
bit 2 BEP: Byte Enable Polarity bit
1 = Byte enable is active-high (PMBE)
0 = Byte enable is active-low (PMBE)
bit 1 WRSP: Write Strobe Polarity bit
For Slave Modes and Master Mode 2 (PMMODE<9:8> = 00, 01, 10):
1 = Write strobe is active-high (PMWR)
0 = Write strobe is active-low (PMWR)
For Master Mode 1 (PMMODE<9:8> = 11):
1 = Enable strobe is active-high (PMENB)
0 = Enable strobe is active-low (PMENB)
bit 0 RDSP: Read Strobe Polarity bit
For Slave Modes and Master Mode 2 (PMMODE<9:8> = 00, 01, 10):
1 = Read strobe is active-high (PMRD)
0 = Read strobe is active-low (PMRD)
For Master Mode 1 (PMMODE<9:8> = 11):
1 = Read/write strobe is active-high (PMRD/PMWR)
0 = Read/write strobe is active-low (PMRD/PMWR)

2: These bits have no effect when their corresponding pins are used as address lines.

REGISTER 18-2: PMMODE: PARALLEL PORT MODE REGISTER
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0
bit 15 bit 8

(1) (1) (1)
WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0 WAITE1 WAITE0(1)
bit 7 bit 0
Legend:
bit 15 BUSY: Busy bit (Master mode only)

1 = Port is busy (not useful when the processor stall is active)
0 = Port is not busy
bit 14-13 IRQM<1:0>: Interrupt Request Mode bits
11 = Interrupt is generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)
or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only)
10 = No interrupt is generated, processor stall is activated
01 = Interrupt is generated at the end of the read/write cycle
00 = No interrupt is generated
bit 12-11 INCM<1:0>: Increment Mode bits
11 = PSP read and write buffers auto-increment (Legacy PSP mode only)
10 = Decrements ADDR<10:0> by 1 every read/write cycle
01 = Increments ADDR<10:0> by 1 every read/write cycle
00 = No increment or decrement of address
bit 10 MODE16: 8/16-Bit Mode bit
1 = 16-Bit Mode: Data register is 16 bits, a read or write to the Data register invokes two 8-bit transfers
0 = 8-Bit Mode: Data register is 8 bits, a read or write to the Data register invokes one 8-bit transfer
bit 9-8 MODE<1:0>: Parallel Port Mode Select bits
11 = Master Mode 1 (PMCS1, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>)
10 = Master Mode 2 (PMCS1, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>)
01 = Enhanced PSP, control signals (PMRD, PMWR, PMCS1, PMD<7:0> and PMA<1:0>)
00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1 and PMD<7:0>)
bit 7-6 WAITB<1:0>: Data Setup to Read/Write Wait State Configuration bits(1)
11 = Data wait of 4 TCY; multiplexed address phase of 4 TCY
bit 5-2 WAITM<3:0>: Read to Byte Enable Strobe Wait State Configuration bits
1111 = Wait of additional 15 TCY
...
0001 = Wait of additional 1 TCY
0000 = No additional wait cycles (operation forced into one TCY)
bit 1-0 WAITE<1:0>: Data Hold After Strobe Wait State Configuration bits(1)
11 = Wait of 4 TCY
10 = Wait of 3 TCY
01 = Wait of 2 TCY
00 = Wait of 1 TCY
Note 1: WAITBx and WAITEx bits are ignored whenever WAITM<3:0> = 0000.

REGISTER 18-3: PMADDR: PARALLEL PORT ADDRESS REGISTER
U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
(1) (1)
— CS1 — — — ADDR10 ADDR9 ADDR8(1)
bit 15 bit 8

(1) (1) (1) (1) (1) (1) (1)
ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0(1)
bit 7 bit 0
Legend:

bit 14 CS1: Chip Select 1 bit
1 = Chip Select 1 is active
0 = Chip Select 1 is inactive
bit 10-0 ADDR<10:0>: Parallel Port Destination Address bits(1)
REGISTER 18-4: PMAEN: PARALLEL PORT ENABLE REGISTER

U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— PTEN14 — — — PTEN10(1) PTEN9(1) PTEN8(1)
bit 15 bit 8

PTEN7(1) PTEN6(1) PTEN5(1) PTEN4(1) PTEN3(1) PTEN2(1) PTEN1 PTEN0
bit 7 bit 0
Legend:

bit 14 PTEN14: PMCS1 Strobe Enable bit
1 = PMCS1 pin functions as chip select
0 = PMCS1 pin functions as port I/O
bit 10-2 PTEN<10:2>: PMP Address Port Enable bits(1)
1 = PMA<10:2> function as PMP address lines
0 = PMA<10:2> function as port I/O
bit 1-0 PTEN<1:0>: PMALH/PMALL Strobe Enable bits
1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL
0 = PMA1 and PMA0 pads functions as port I/O

REGISTER 18-5: PMSTAT: PARALLEL PORT STATUS REGISTER
R-0 R/W-0, HS U-0 U-0 R-0 R-0 R-0 R-0
IBF IBOV — — IB3F IB2F IB1F IB0F
bit 15 bit 8
R-1 R/W-0, HS U-0 U-0 R-1 R-1 R-1 R-1

OBE OBUF — — OB3E OB2E OB1E OB0E
bit 7 bit 0
Legend: HS = Hardware Settable bit

bit 15 IBF: Input Buffer Full Status bit

1 = All writable Input Buffer registers are full
0 = Some or all of the writable Input Buffer registers are empty
bit 14 IBOV: Input Buffer Overflow Status bit
1 = A write attempt to a full Input Byte register occurred (must be cleared in software)
0 = No overflow occurred
bit 11-8 IB3F:IB0F: Input Buffer x Status Full bits
1 = Input Buffer x contains data that has not been read (reading buffer will clear this bit)
0 = Input Buffer x does not contain any unread data
bit 7 OBE: Output Buffer Empty Status bit
1 = All readable Output Buffer registers are empty
0 = Some or all of the readable Output Buffer registers are full
bit 6 OBUF: Output Buffer Underflow Status bit
1 = A read occurred from an empty Output Byte register (must be cleared in software)
0 = No underflow occurred
bit 3-0 OB3E:OB0E Output Buffer x Status Empty bits
1 = Output Buffer x is empty (writing data to the buffer will clear this bit)
0 = Output Buffer x contains data that has not been transmitted

REGISTER 18-6: PADCFG1: PAD CONFIGURATION CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

(1)
— — — — — — RTSECSEL PMPTTL
bit 7 bit 0
Legend:

bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1)
1 = RTCC seconds clock is selected for the RTCC pin
0 = RTCC alarm pulse is selected for the RTCC pin
bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt Trigger input buffers
Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL) bit needs to be set.

FIGURE 18-2: LEGACY PARALLEL SLAVE PORT EXAMPLE
Address Bus
Master PIC24F Slave
Data Bus
PMD<7:0> PMD<7:0>
Control Lines
PMCS1 PMCS1
PMRD PMRD
PMWR PMWR
FIGURE 18-3: ADDRESSABLE PARALLEL SLAVE PORT EXAMPLE
Master PIC24F Slave

PMA<1:0>
PMA<1:0>
PMD<7:0> Write Read

PMD<7:0> Address Address
Decode Decode
PMDOUT1L (0) PMDIN1L (0)

PMCS1 PMCS1 PMDOUT1H (1) PMDIN1H (1)
PMRD PMRD PMDOUT2L (2) PMDIN2L (2)
PMWR PMWR PMDOUT2H (3) PMDIN2H (3)
Address Bus
Data Bus
Control Lines
TABLE 18-1: SLAVE MODE ADDRESS RESOLUTION

PMA<1:0> Output Register (Buffer) Input Register (Buffer)
00 PMDOUT1<7:0> (0) PMDIN1<7:0> (0)
01 PMDOUT1<15:8> (1) PMDIN1<15:8> (1)
10 PMDOUT2<7:0> (2) PMDIN2<7:0> (2)
11 PMDOUT2<15:8> (3) PMDIN2<15:8> (3)
FIGURE 18-4: MASTER MODE, DEMULTIPLEXED ADDRESSING (SEPARATE READ AND

WRITE STROBES, SINGLE CHIP SELECT)
PIC24F PMA<10:0>
PMD<7:0>
PMCS1
PMRD Address Bus

Data Bus
PMWR Control Lines

FIGURE 18-5: MASTER MODE, PARTIALLY MULTIPLEXED ADDRESSING (SEPARATE READ
AND WRITE STROBES, SINGLE CHIP SELECT)
PIC24F PMA<10:8>
PMD<7:0>
PMA<7:0>
PMCS1
Address Bus
PMALL
Multiplexed
PMRD Data and
Address Bus
PMWR Control Lines
FIGURE 18-6: MASTER MODE, FULLY MULTIPLEXED ADDRESSING (SEPARATE READ AND
WRITE STROBES, SINGLE CHIP SELECT)
PMD<7:0>
PIC24F PMA<7:0>
PMA<15:8>
PMCS1
PMALL
PMALH
Multiplexed
PMRD Data and
Address Bus
PMWR Control Lines
FIGURE 18-7: EXAMPLE OF A MULTIPLEXED ADDRESSING APPLICATION
PIC24F
PMD<7:0> 373 A<7:0>
A<15:0>
PMALL
D<7:0>
D<7:0>
CE
A<15:8>
373 OE WR
PMALH
PMCS1 Address Bus
PMRD Data Bus
PMWR Control Lines
FIGURE 18-8: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION

PIC24F
PMD<7:0> 373 A<7:0>
A<10:0>
PMALL
D<7:0>
D<7:0>
A<10:8> CE
PMA<10:8>
OE WR Address Bus
PMCS1
Data Bus
PMRD
Control Lines
PMWR

FIGURE 18-9: EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION
PIC24F Parallel Peripheral

PMD<7:0> AD<7:0>
PMALL ALE
PMCS1 CS Address Bus
PMRD RD Data Bus
PMWR WR Control Lines
FIGURE 18-10: PARALLEL EEPROM EXAMPLE (UP TO 11-BIT ADDRESS, 8-BIT DATA)
PIC24F Parallel EEPROM

PMA<n:0> A<n:0>
PMD<7:0> D<7:0>
PMCS1 CE
Address Bus
PMRD OE
Data Bus
PMWR WR
Control Lines
FIGURE 18-11: PARALLEL EEPROM EXAMPLE (UP TO 11-BIT ADDRESS, 16-BIT DATA)
PIC24F Parallel EEPROM

PMA<n:0> A<n:1>
PMD<7:0> D<7:0>
PMBE A0
PMCS1 CE
Address Bus
PMRD OE
Data Bus
PMWR WR
Control Lines
FIGURE 18-12: LCD CONTROL EXAMPLE (BYTE MODE OPERATION)
PIC24F LCD Controller

PM<7:0> D<7:0>
PMA0 RS
PMRD/PMWR R/W Address Bus
PMCS1 E Data Bus
Control Lines

19.0 REAL-TIME CLOCK AND Key features include:
CALENDAR (RTCC) • Time data in hours, minutes and seconds, with a
granularity of one-half second
Note: This data sheet summarizes the features of • 24-hour format (military time) display option
• Calendar data as date, month and year
source. For more information, refer to the • Automatic, hardware-based day of week and leap
“PIC24F Family Reference Manual”, year calculations for dates from 2000 through
“Real-Time Clock and Calendar 2099
(RTCC)” (DS39696). • Time and calendar data in BCD format for
compact firmware
The Real-Time Clock and Calendar (RTCC) provides • Highly configurable alarm function
on-chip, hardware-based clock and calendar function-
• External output pin with selectable alarm signal or
ality with little or no CPU overhead. It is intended for
seconds “tick” signal output
applications where accurate time must be maintained
for extended periods, with minimal CPU activity and • Time base input from Secondary Oscillator (SOSC)
with limited power resources, such as battery-powered or the T1CK digital clock input (32.768 kHz)
applications. • User calibration feature with auto-adjust
A simplified block diagram of the module is shown in
Figure 19-1.The SOSC and RTCC will both remain
running while the device is held in Reset with MCLR,
and will continue running after MCLR is released.
FIGURE 19-1: RTCC BLOCK DIAGRAM
RTCC Clock Domain CPU Clock Domain
RCFGCAL
32.768 kHz Input
RTCC Prescalers
(SOSC or T1CK) ALCFGRPT
YEAR
0.5s
MTHDY
RTCC Timer RTCVAL
WKDYHR
Alarm
Event MINSEC
Comparator
ALMTHDY
Compare Registers
ALRMVAL ALWDHR
with Masks
ALMINSEC
Repeat Counter
RTCC Interrupt
RTCC Interrupt Logic
Alarm Pulse
RTCC Pin
RTCOE

19.1 RTCC Module Registers TABLE 19-2: ALRMVAL REGISTER
MAPPING
The RTCC module registers are organized into three
categories: ALRMPTR Alarm Value Register Window
• RTCC Control Registers <1:0> ALRMVAL<15:8> ALRMVAL<7:0>
• RTCC Value Registers
00 ALRMMIN ALRMSEC
• Alarm Value Registers
01 ALRMWD ALRMHR
19.1.1 REGISTER MAPPING 10 ALRMMNTH ALRMDAY
To limit the register interface, the RTCC Timer and Alarm 11 — —
Time registers are accessed through corresponding reg- Considering that the 16-bit core does not distinguish
ister pointers. The RTCC Value register window between 8-bit and 16-bit read operations, the user must
(RTCVALH and RTCVALL) uses the RTCPTR<1:0> bits be aware that when reading either the ALRMVALH
(RCFGCAL<9:8>) to select the desired Timer register or ALRMVALL, the bytes will decrement the
pair (see Table 19-1). ALRMPTR<1:0> value. The same applies to the
By writing the RTCVALH byte, the RTCC Pointer value RTCVALH or RTCVALL bytes with the RTCPTR<1:0>
(the RTCPTR<1:0> bits) decrements by one until the being decremented.
bits reach ‘00’. Once they reach ‘00’, the MINUTES
Note: This only applies to read operations and
and SECONDS value will be accessible through
not write operations.
RTCVALH and RTCVALL until the pointer value is
manually changed.
19.1.2 WRITE LOCK
TABLE 19-1: RTCVAL REGISTER MAPPING In order to perform a write to any of the RTCC Timer
registers, the RTCWREN bit (RCFGCAL<13>) must be
RTCPTR RTCC Value Register Window set (refer to Example 19-1).
<1:0> RTCVAL<15:8> RTCVAL<7:0> Note: To avoid accidental writes to the timer, it is
00 MINUTES SECONDS recommended that the RTCWREN bit
(RCFGCAL<13>) is kept clear at any
01 WEEKDAY HOURS
other time. For the RTCWREN bit to be
10 MONTH DAY set, there is only 1 instruction cycle time
11 — YEAR window allowed between the 55h/AA
sequence and the setting of RTCWREN;
The Alarm Value register window (ALRMVALH and
therefore, it is recommended that code
ALRMVALL) uses the ALRMPTR bits (ALCFGRPT<9:8>)
follow the procedure in Example 19-1.
to select the desired Alarm register pair (see Table 19-2).
By writing the ALRMVALH byte, the Alarm Pointer
value (the ALRMPTR<1:0> bits) decrements by one
until the bits reach ‘00’. Once they reach ‘00’, the
ALRMMIN and ALRMSEC value will be accessible
through ALRMVALH and ALRMVALL until the pointer
value is manually changed.
EXAMPLE 19-1: SETTING THE RTCWREN BIT

asm volatile("push w7");
asm volatile("push w8");
asm volatile("disi #5");
asm volatile("mov #0x55, w7");
asm volatile("mov w7, _NVMKEY");
asm volatile("mov #0xAA, w8");
asm volatile("mov w8, _NVMKEY");
asm volatile("bset _RCFGCAL, #13"); //set the RTCWREN bit
asm volatile("pop w8");
asm volatile("pop w7");

19.1.3 RTCC CONTROL REGISTERS
REGISTER 19-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1)

R/W-0 U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0
RTCEN(2) — RTCWREN RTCSYNC HALFSEC(3) RTCOE RTCPTR1 RTCPTR0
bit 15 bit 8

CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0
bit 7 bit 0
Legend:
bit 15 RTCEN: RTCC Enable bit(2)

1 = RTCC module is enabled
0 = RTCC module is disabled
bit 13 RTCWREN: RTCC Value Registers Write Enable bit
1 = RTCVALH and RTCVALL registers can be written to by the user
0 = RTCVALH and RTCVALL registers are locked out from being written to by the user
bit 12 RTCSYNC: RTCC Value Registers Read Synchronization bit
1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple
resulting in an invalid data read. If the register is read twice and results in the same data, the data
can be assumed to be valid.
0 = RTCVALH, RTCVALL or ALCFGRPT register can be read without concern over a rollover ripple
bit 11 HALFSEC: Half-Second Status bit(3)
1 = Second half period of a second
0 = First half period of a second
bit 10 RTCOE: RTCC Output Enable bit
1 = RTCC output is enabled
0 = RTCC output is disabled
bit 9-8 RTCPTR<1:0>: RTCC Value Register Window Pointer bits
Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers;
the RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’.
RTCVAL<15:8>:
00 = MINUTES
01 = WEEKDAY
10 = MONTH
11 = Reserved
RTCVAL<7:0>:
00 = SECONDS
01 = HOURS
10 = DAY
11 = YEAR
Note 1: The RCFGCAL register is only affected by a POR.

2: A write to the RTCEN bit is only allowed when RTCWREN = 1.
3: This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register.

REGISTER 19-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1)
bit 7-0 CAL<7:0>: RTCC Drift Calibration bits
01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute
...
01111111 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute
00000000 = No adjustment
11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute
...
10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute
Note 1: The RCFGCAL register is only affected by a POR.

2: A write to the RTCEN bit is only allowed when RTCWREN = 1.
3: This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register.
REGISTER 19-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — — RTSECSEL(1) PMPTTL
bit 7 bit 0
Legend:

bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1)
1 = RTCC seconds clock is selected for the RTCC pin
0 = RTCC alarm pulse is selected for the RTCC pin
bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt Trigger input buffers
Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL) bit needs to be set.

REGISTER 19-3: ALCFGRPT: ALARM CONFIGURATION REGISTER
ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0
bit 15 bit 8

ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0
bit 7 bit 0
Legend:
bit 15 ALRMEN: Alarm Enable bit

1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 00h and
CHIME = 0)
0 = Alarm is disabled
bit 14 CHIME: Chime Enable bit
1 = Chime is enabled; ARPT<7:0> bits are allowed to roll over from 00h to FFh
0 = Chime is disabled; ARPT<7:0> bits stop once they reach 00h
bit 13-10 AMASK<3:0>: Alarm Mask Configuration bits
0000 = Every half second
0001 = Every second
0010 = Every 10 seconds
0011 = Every minute
0100 = Every 10 minutes
0101 = Every hour
0110 = Once a day
0111 = Once a week
1000 = Once a month
1001 = Once a year (except when configured for February 29th, once every 4 years)
101x = Reserved; do not use
11xx = Reserved; do not use
bit 9-8 ALRMPTR<1:0>: Alarm Value Register Window Pointer bits
Points to the corresponding Alarm Value registers when reading ALRMVALH and ALRMVALL registers;
the ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’.
ALRMVAL<15:8>:
00 = ALRMMIN
01 = ALRMWD
10 = ALRMMNTH
11 = Unimplemented
ALRMVAL<7:0>:
00 = ALRMSEC
01 = ALRMHR
10 = ALRMDAY
11 = Unimplemented
bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits
11111111 = Alarm will repeat 255 more times
...
00000000 = Alarm will not repeat
The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to
FFh unless CHIME = 1.

19.1.4 RTCVAL REGISTER MAPPINGS
REGISTER 19-4: YEAR: YEAR VALUE REGISTER(1)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0
bit 7 bit 0
Legend:

bit 7-4 YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit bits
Contains a value from 0 to 9.
bit 3-0 YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit bits
Note 1: A write to this register is only allowed when RTCWREN = 1.
REGISTER 19-5: MTHDY: MONTH AND DAY VALUE REGISTER(1)

U-0 U-0 U-0 R-x R-x R-x R-x R-x
— — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0
bit 15 bit 8
U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0
bit 7 bit 0
Legend:

bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit
Contains a value of ‘0’ or ‘1’.
bit 11-8 MTHONE<3:0<: Binary Coded Decimal Value of Month’s Ones Digit bits
bit 5-4 DAYTEN<1:0:> Binary Coded Decimal Value of Day’s Tens Digit bits
bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits

REGISTER 19-6: WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1)
U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x
— — — — — WDAY2 WDAY1 WDAY0
bit 15 bit 8

— — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0
bit 7 bit 0
Legend:

bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits
bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits
bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits
REGISTER 19-7: MINSEC: MINUTES AND SECONDS VALUE REGISTER

U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0
bit 15 bit 8

— SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0
bit 7 bit 0
Legend:

bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits
bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits
bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits
bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits

19.1.5 ALRMVAL REGISTER MAPPINGS
REGISTER 19-8: ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER(1)

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0
bit 15 bit 8

— — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0
bit 7 bit 0
Legend:

bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit
Contains a value of ‘0’ or ‘1’.
bit 11-8 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits
bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits
bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits

REGISTER 19-9: ALWDHR: ALARM WEEKDAY AND HOURS VALUE REGISTER(1)
U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x
— — — — — WDAY2 WDAY1 WDAY0
bit 15 bit 8

— — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0
bit 7 bit 0
Legend:

bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits
bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits
bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits
REGISTER 19-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER

— MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0
bit 15 bit 8

— SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0
bit 7 bit 0
Legend:

bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits
bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits
bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits
bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits

19.2 Calibration 19.3 Alarm
The real-time crystal input can be calibrated using the • Configurable from half second to one year
periodic auto-adjust feature. When properly calibrated, • Enabled using the ALRMEN bit
the RTCC can provide an error of less than 3 seconds (ALCFGRPT<15>, Register 19-3)
per month. This is accomplished by finding the number • One-time alarm and repeat alarm options are
of error clock pulses and storing the value into the available
lower half of the RCFGCAL register. The 8-bit signed
value, loaded into the lower half of RCFGCAL, is multi- 19.3.1 CONFIGURING THE ALARM
plied by four and will be either added or subtracted from
the RTCC timer, once every minute. Refer to the steps The alarm feature is enabled using the ALRMEN bit.
below for RTCC calibration: This bit is cleared when an alarm is issued. Writes to
ALRMVAL should only take place when ALRMEN = 0.
1. Using another timer resource on the device, the
user must find the error of the 32.768 kHz As shown in Figure 19-2, the interval selection of the
crystal. alarm is configured through the AMASK<3:0> bits
(ALCFGRPT<13:10>). These bits determine which and
2. Once the error is known, it must be converted to
how many digits of the alarm must match the clock
the number of error clock pulses per minute.
value for the alarm to occur.
EQUATION 19-1: The alarm can also be configured to repeat based on a
(Ideal Frequency† – Measured Frequency) * 60 = preconfigured interval. The amount of times this occurs,
Clocks per Minute once the alarm is enabled, is stored in the ARPT<7:0>
† Ideal frequency = 32,768 Hz bits (ALCFGRPT<7:0>). When the value of the ARPTx
bits equals 00h and the CHIME bit (ALCFGRPT<14>) is
3. a) If the oscillator is faster then ideal (negative cleared, the repeat function is disabled and only a
result form Step 2), the RCFGCAL register value single alarm will occur. The alarm can be repeated up
needs to be negative. This causes the specified to 255 times by loading ARPT<7:0> with FFh.
number of clock pulses to be subtracted from
After each alarm is issued, the value of the ARPTx bits
the timer counter, once every minute.
is decremented by one. Once the value has reached
b) If the oscillator is slower then ideal (positive 00h, the alarm will be issued one last time, after which,
result from Step 2), the RCFGCAL register value the ALRMEN bit will be cleared automatically and the
needs to be positive. This causes the specified alarm will turn off.
number of clock pulses to be subtracted from
Indefinite repetition of the alarm can occur if CHIME
the timer counter, once every minute.
(ALCFGRPT<14>) = 1. Instead of the alarm being dis-
4. Divide the number of error clocks per minute by abled when the value of the ARPTX bits reaches 00h, it
4 to get the correct CAL<7:0> bits value and rolls over to FFh and continues counting indefinitely
load the RCFGCAL register with the correct while CHIME is set.
value.
(Each 1-bit increment in the CALx bits value 19.3.2 ALARM INTERRUPT
adds or subtracts 4 pulses). At every alarm event, an interrupt is generated. In addi-
Writes to the lower half of the RCFGCAL register tion, an alarm pulse output is provided that operates at
should only occur when the timer is turned off or half the frequency of the alarm. This output is
immediately after the rising edge of the seconds pulse. completely synchronous to the RTCC clock and can be
used as a trigger clock to other peripherals.
Note: It is up to the user to include in the error
value the initial error of the crystal, drift Note: Changing any of the registers, other then
due to temperature and drift due to crystal the RCFGCAL and ALCFGRPT registers
aging. and the CHIME bit while the alarm is
enabled (ALRMEN = 1), can result in a
false alarm event leading to a false alarm
interrupt. To avoid a false alarm event, the
timer and alarm values should only be
changed while the alarm is disabled
(ALRMEN = 0). It is recommended that
the ALCFGRPT register and CHIME bit be
changed when RTCSYNC = 0.

FIGURE 19-2: ALARM MASK SETTINGS
Day of
Alarm Mask Setting the
(AMASK<3:0>) Week Month Day Hours Minutes Seconds
0000 – Every half second
0001 – Every second
0010 – Every 10 seconds s
0011 – Every minute s s
0100 – Every 10 minutes m s s
0101 – Every hour m m s s
0110 – Every day h h m m s s
0111 – Every week d h h m m s s
1000 – Every month d d h h m m s s
1001 – Every year(1) m m d d h h m m s s
Note 1: Annually, except when configured for February 29.

NOTES:

20.0 PROGRAMMABLE CYCLIC Consider the following equation:
REDUNDANCY CHECK (CRC) EQUATION 20-1: CRC POLYNOMIAL
GENERATOR
x16 + x12 + x5 + 1
intended to be a comprehensive reference To program this polynomial into the CRC generator,
source. For more information, refer to the the CRC register bits should be set as shown in
“PIC24F Family Reference Manual”, Table 20-1.
“Programmable Cyclic Redundancy
Check (CRC)” (DS39714). TABLE 20-1: EXAMPLE CRC SETUP
The programmable CRC generator offers the following Bit Name Bit Value
features: PLEN<3:0> 1111
• User-programmable polynomial CRC equation X<15:1> 000100000010000
• Interrupt output
Note that for the value of X<15:1>, the 12th bit and the
• Data FIFO 5th bit are set to ‘1’, as required by the equation. The
The module implements a software configurable CRC 0 bit, required by the equation, is always XORed. For a
generator. The terms of the polynomial and its length 16-bit polynomial, the 16th bit is also always assumed
can be programmed using the X<15:1> bits to be XORed; therefore, the X<15:1> bits do not have
(CRCXOR<15:1>) and the PLEN<3:0> bits the 0 bit or the 16th bit.
(CRCCON<3:0>), respectively. A simplified block diagram of the module is shown in
Figure 20-1. The general topology of the shift engine is
shown in Figure 20-2.
FIGURE 20-1: CRC BLOCK DIAGRAM
CRCDAT
Variable FIFO FIFO Empty Event

Set CRCIF
(8x16 or 16x8)
Shift Clock (2 FCY)

CRC Shift Engine
CRCWDAT

FIGURE 20-2: CRC SHIFT ENGINE DETAIL
CRCWDAT
Read/Write Bus
X(1)(1) X(2)(1) X(n)(1)
Shift Buffer Bit 0 Bit 1 Bit 2 Bit n(2)

Data
Note 1: Each XOR stage of the shift engine is programmable. See text for details.
2: Polynomial Length n is determined by ([PLEN<3:0>] + 1).
20.1 User Interface To empty words already written into a FIFO, the
CRCGO bit must be set to ‘1’ and the CRC shifter
20.1.1 DATA INTERFACE allowed to run until the CRCMPT bit is set.
To start serial shifting, a ‘1’ must be written to the Also, to get the correct CRC reading, it will be
CRCGO bit. necessary to wait for the CRCMPT bit to go high before
reading the CRCWDAT register.
The module incorporates a FIFO that is 8 deep when
PLEN<3:0> (CRCCON<3:0>) > 7 and 16 deep, other- If a word is written when the CRCFUL bit is set, the
wise. The data for which the CRC is to be calculated VWORDx Pointer will roll over to 0. The hardware will
must first be written into the FIFO. The smallest data then behave as if the FIFO is empty. However, the con-
element that can be written into the FIFO is one byte. dition to generate an interrupt will not be met; therefore,
For example, if PLEN<3:0> = 5, then the size of the no interrupt will be generated (See Section 20.1.2
data is PLEN<3:0> + 1 = 6. When loading data, the “Interrupt Operation”).
two MSbs of the data byte are ignored. At least one instruction cycle must pass after a write to
Once data is written into the CRCWDAT MSb (as CRCWDAT before a read of the VWORDx bits is done.
defined by PLENx), the value of VWORD<4:0>
(CRCCON<12:8>) increments by one. When 20.1.2 INTERRUPT OPERATION
CRCGO = 1 and VWORDx > 0, a word of data to be When the VWORD<4:0> bits make a transition from a
shifted is moved from the FIFO into the shift engine. value of ‘1’ to ‘0’, an interrupt will be generated. Note
When the data word moves from the FIFO to the shift that the CRC calculation is not complete at this point;
engine, the VWORDx bits decrement by one. The serial an additional time of (PLEN + 1)/2 clock cycles is
shifter continues to receive data from the FIFO, shifting required before the output can be read.
until the VWORDx bits reach 0. The last bit of data will
be shifted through the CRC module (PLENx + 1)/2 clock 20.2 Operation in Power Save Modes
cycles after the VWORDx bits reach 0. This is when the
module is completed with the CRC calculation. 20.2.1 SLEEP MODE
Therefore, for a given value of PLENx, it will take If Sleep mode is entered while the module is operating,
(PLENx + 1)/2 * VWORDx number of clock cycles to the module will be suspended in its current state until
complete the CRC calculations. clock execution resumes.
When the VWORD<4:0> bits reach 8 (or 16), the
CRCFUL bit will be set. When the VWORD<4:0> bits 20.2.2 IDLE MODE
reach 0, the CRCMPT bit will be set. To continue full module operation in Idle mode, the
To continually feed data into the CRC engine, the CSIDL bit must be cleared prior to entry into the mode.
recommended mode of operation is to initially “prime” If CSIDL = 1, the module will behave the same way as
the FIFO with a sufficient number of words, so no inter- it does in Sleep mode; pending interrupt events will be
rupt is generated before the next word can be written. passed on, even though the module clocks are not
Once that is done, start the CRC by setting the CRCGO available.
bit to ‘1’. From that point onward, the VWORDx bits
should be polled. If they read less than 8 or 16, another
word can be written into the FIFO.

20.3 Registers
There are four registers used to control programmable
CRC operation:
• CRCCON
• CRCXOR
• CRCDAT
• CRCWDAT
REGISTER 20-1: CRCCON: CRC CONTROL REGISTER

U-0 U-0 R/W-0 R-0 R-0 R-0 R-0 R-0
— — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0
bit 15 bit 8
R-0 R-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CRCFUL CRCMPT — CRCGO PLEN3 PLEN2 PLEN1 PLEN0
bit 7 bit 0
Legend:

bit 13 CSIDL: CRC Stop in Idle Mode bit
bit 12-8 VWORD<4:0>: Pointer Value bits
Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN<3:0> > 7 or
16 when PLEN<3:0> 7.
bit 7 CRCFUL: CRC FIFO Full bit
1 = FIFO is full
0 = FIFO is not full
bit 6 CRCMPT: CRC FIFO Empty Bit
1 = FIFO is empty
0 = FIFO is not empty
bit 4 CRCGO: CRC Start bit
1 = Starts CRC serial shifter
0 = CRC serial shifter is turned off
bit 3-0 PLEN<3:0>: Polynomial Length bits
Denotes the length of the polynomial to be generated minus 1.

REGISTER 20-2: CRCXOR: CRC XOR POLYNOMIAL REGISTER
X15 X14 X13 X12 X11 X10 X9 X8
bit 15 bit 8

X7 X6 X5 X4 X3 X2 X1 —
bit 7 bit 0
Legend:
bit 15-1 X<15:1>: XOR of Polynomial Term Xn Enable bits


21.0 10-BIT HIGH-SPEED A/D A block diagram of the A/D Converter is shown in
Figure 21-1.
CONVERTER
To perform an A/D conversion:
1. Configure the A/D module:
intended to be a comprehensive reference a) Select the port pins as analog inputs
source. For more information, refer to the (AD1PCFG<15:0>).
“PIC24F Family Reference Manual”, b) Select the voltage reference source to
“10-Bit A/D Converter” (DS39705). match the expected range on the analog
inputs (AD1CON2<15:13>).
The 10-bit A/D Converter has the following key c) Select the analog conversion clock to
features: match the desired data rate with the
• Successive Approximation (SAR) conversion processor clock (AD1CON3<7:0>).
• Conversion speeds of up to 500 ksps d) Select the appropriate sample/conversion
• Up to 13 analog input pins sequence (AD1CON1<7:5> and
AD1CON3<12:8>).
• External voltage reference input pins
e) Select how conversion results are
• Automatic Channel Scan mode
presented in the buffer (AD1CON1<9:8>).
• Selectable conversion trigger source
f) Select the interrupt rate (AD1CON2<5:2>).
• 16-word conversion result buffer
g) Turn on the A/D module (AD1CON1<15>).
• Selectable Buffer Fill modes
2. Configure the A/D interrupt (if required):
• Four result alignment options
a) Clear the AD1IF bit.
• Operation during CPU Sleep and Idle modes
b) Select the A/D interrupt priority.
Depending on the particular device pinout, the 10-bit
A/D Converter can have up to three analog input pins,
designated AN0 through AN12. In addition, there are
two analog input pins for external voltage reference
connections. These voltage reference inputs may be
shared with other analog input pins. The actual number
of analog input pins and the external voltage reference
input configuration will depend on the specific device.

FIGURE 21-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM
Internal Data Bus
AVDD
16
AVSS VR Select VR+
VREF+ VR-
Comparator
VREF-
VINH
VR- VR+
S/H DAC
AN0 VINL
AN1 VINH
10-Bit SAR Conversion Logic
AN2
MUX A
AN3 Data Formatting
AN4
VINL
AN5 ADC1BUF0:
ADC1BUFF
AN6(1)
AD1CON1
AN7(1)
AD1CON2
AD1CON3
AN8(1)
VINH AD1CHS
MUX B
AN9 AD1PCFG
AD1CSSL
AN10 VINL
AN11
Sample Control Control Logic
AN12 Conversion Control
Input MUX Control
VBG(2) Pin Config. Control
Note 1: Analog Channels, AN6 through AN8, are available on 44-pin devices only.
2: Band Gap Voltage (VBG) reference is internally connected to Analog Channel AN15, which does not appear on any pin.

REGISTER 21-1: AD1CON1: A/D CONTROL REGISTER 1
R/W-0 U-0 R/C-0 U-0 U-0 U-0 R/W-0 R/W-0
(1)
ADON — ADSIDL — — — FORM1 FORM0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0, HSC R/W-0, HSC
SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE
bit 7 bit 0
Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit

bit 15 ADON: A/D Operating Mode bit(1)

1 = A/D Converter module is operating
0 = A/D Converter is off
bit 13 ADSIDL: A/D Stop in Idle Mode bit
bit 9-8 FORM<1:0>: Data Output Format bits
11 = Signed fractional (sddd dddd dd00 0000)
10 = Fractional (dddd dddd dd00 0000)
01 = Signed integer (ssss sssd dddd dddd)
00 = Integer (0000 00dd dddd dddd)
bit 7-5 SSRC<2:0>: Conversion Trigger Source Select bits
111 = Internal counter ends sampling and starts conversion (auto-convert)
110 = Reserved
10x = Reserved
011 = Reserved
010 = Timer3 compare ends sampling and starts conversion
001 = Active transition on INT0 pin ends sampling and starts conversion
000 = Clearing the SAMP bit ends sampling and starts conversion
bit 2 ASAM: A/D Sample Auto-Start bit
1 = Sampling begins immediately after last conversion completes; SAMP bit is auto-set
0 = Sampling begins when SAMP bit is set
bit 1 SAMP: A/D Sample Enable bit
1 = A/D Sample-and-Hold (S/H) amplifier is sampling input
0 = A/D Sample-and-Hold amplifier is holding
bit 0 DONE: A/D Conversion Status bit
1 = A/D conversion is done
0 = A/D conversion is NOT done
Note 1: The ADC1BUFn registers do not retain their values when ADON is cleared. Read out any conversion
values from the buffer before disabling the module.

R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0
VCFG2 VCFG1 VCFG0 — — CSCNA — —
bit 15 bit 8
R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BUFS — SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS
bit 7 bit 0
Legend:
bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits
VCFG<2:0> VR+ VR-

000 AVDD* AVSS*
001 External VREF+ Pin AVSS*
010 AVDD* External VREF- Pin
011 External VREF+ Pin External VREF- Pin
1xx AVDD* AVSS*
* AVDD and AVSS inputs are tied to VDD and VSS on 28-pin devices.

bit 10 CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexer Setting bit
1 = Scans inputs
0 = Does not scan inputs
bit 7 BUFS: Buffer Fill Status bit (valid only when BUFM = 1)
1 = A/D is currently filling Buffer 08-0F, user should access data in 00-07
0 = A/D is currently filling Buffer 00-07, user should access data in 08-0F
bit 5-2 SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits
1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence
1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence
.....
0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence
0000 = Interrupts at the completion of conversion for each sample/convert sequence
bit 1 BUFM: Buffer Mode Select bit
1 = Buffer configured as two 8-word buffers (ADC1BUFn<15:8> and ADC1BUFn<7:0>)
0 = Buffer configured as one 16-word buffer (ADC1BUFn<15:0>)
bit 0 ALTS: Alternate Input Sample Mode Select bit
1 = Uses MUX A input multiplexer settings for first sample, then alternates between MUX B and MUX A
input multiplexer settings for all subsequent samples
0 = Always uses MUX A input multiplexer settings

R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADRC — — SAMC4 SAMC3 SAMC2 SAMC1 SAMC0
bit 15 bit 8

ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0
bit 7 bit 0
Legend:
bit 15 ADRC: A/D Conversion Clock Source bit

1 = A/D internal RC clock
0 = Clock derived from system clock
bit 12-8 SAMC<4:0>: Auto-Sample Time bits
11111 = 31 TAD
·····
00001 = 1 TAD
00000 = 0 TAD (not recommended)
bit 7-0 ADCS<7:0>: A/D Conversion Clock Select bits
11111111
······ = Reserved
01000000
00111111 = 64 • TCY
······
00000001 = 2 • TCY
00000000 = TCY

REGISTER 21-4: AD1CHS: A/D INPUT SELECT REGISTER
R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0NB — — — CH0SB3(1,2) CH0SB2(1,2) CH0SB1(1,2) CH0SB0(1,2)
bit 15 bit 8
R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

CH0NA — — — CH0SA3(1,2) CH0SA2(1,2) CH0SA1(1,2) CH0SA0(1,2)
bit 7 bit 0
Legend:
bit 15 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is VR-
bit 11-8 CH0SB<3:0>: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits(1,2)
1111 = Channel 0 positive input is AN15 (band gap voltage reference)
1100 = Channel 0 positive input is AN12
·····
bit 7 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is VR-
bit 3-0 CH0SA<3:0>: Channel 0 Positive Input Select for MUX A Multiplexer Setting bits(1,2)
1111 = Channel 0 positive input is AN15 (band gap voltage reference)
·····
Note 1: Combinations, ‘1101’ and ‘1110’, are unimplemented; do not use.

2: Analog Channels, AN6, AN7 and AN8, are unavailable on 28-pin devices; do not use.

REGISTER 21-5: AD1PCFG: A/D PORT CONFIGURATION REGISTER
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PCFG15 — — PCFG12 PCFG11 PCFG10 PCFG9 PCFG8(1)
bit 15 bit 8

(1) PCFG6(1)
PCFG7 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
Legend:
bit 15 PCFG15: Analog Input Pin Configuration Control bit

1 = Band gap voltage reference is disabled
0 = Band gap voltage reference is enabled
bit 12-0 PCFG<12:0>: Analog Input Pin Configuration Control bits(1)
1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read is enabled
0 = Pin is configured in Analog mode; I/O port read is disabled, A/D samples pin voltage
Note 1: Analog Channels, AN6, AN7 and AN8, are unavailable on 28-pin devices; leave these corresponding bits set.
REGISTER 21-6: AD1CSSL: A/D INPUT SCAN SELECT REGISTER

R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSSL15 — — CSSL12 CSSL11 CSSL10 CSSL9 CSSL8(1)
bit 15 bit 8

(1)
CSSL7 CSSL6(1) CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0
bit 7 bit 0
Legend:
bit 15 CSSL15: Band Gap Reference Input Pin Scan Selection bit
1 = Band gap voltage reference channel is selected for input scan
0 = Band gap voltage reference channel is omitted from input scan
bit 12-0 CSSL<12:0>: A/D Input Pin Scan Selection bits(1)
1 = Corresponding analog channel is selected for input scan
0 = Analog channel is omitted from input scan
Note 1: Analog Channels, AN6, AN7 and AN8, are unavailable on 28-pin devices; leave these corresponding bits
cleared.

EQUATION 21-1: A/D CONVERSION CLOCK PERIOD(1)
TAD = TCY • (ADCS +1)
TAD
ADCS = –1
TCY
Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled.
FIGURE 21-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL
VDD RSS  5 k(Typical)

RIC  250 Sampling
VT = 0.6V Switch
Rs ANx RSS
CHOLD
VA CPIN ILEAKAGE = DAC Capacitance
VT = 0.6V 500 nA = 4.4 pF (Typical)
6-11 pF
(Typical)
VSS
Legend: CPIN = Input Capacitance

VT = Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to
various junctions
RIC = Interconnect Resistance
RSS = Sampling Switch Resistance
CHOLD = Sample/Hold Capacitance (from DAC)
Note: CPIN value depends on device package and is not tested. The effect of CPIN is negligible if Rs  5 k.

FIGURE 21-3: A/D TRANSFER FUNCTION
Digital Output Code

Binary (Decimal)
11 1111 1111 (1023)

11 1111 1110 (1022)
10 0000 0011 (515)
10 0000 0010 (514)

10 0000 0001 (513)
10 0000 0000 (512)

01 1111 1111 (511)
01 1111 1110 (510)
01 1111 1101 (509)
00 0000 0001 (1)
00 0000 0000 (0)

512 * (VR+ - VR-)
1023 * (VR+ - VR-)
VR +
VINH - VINL
VR+ - VR-
VR -
0
1024
Voltage Level
1024
1024
VR- +
VR - +
VR- +

NOTES:

22.0 COMPARATOR MODULE
“Output Compare” (DS39706).
FIGURE 22-1: COMPARATOR I/O OPERATING MODES
C1NEG CMCON<6>
C1EN
C1INV
C1IN+
VIN-
C1IN-
C1OUT(1)
C1POS C1
C1IN+
VIN+ C1OUTEN
CVREF
C2NEG CMCON<7>
C2EN
C2INV
C2IN+
VIN-
C2IN- C2OUT(1)
C2POS C2
C2IN+
VIN+ C2OUTEN
CVREF
Note 1: This peripheral’s outputs must be assigned to an available RPn pin before use. Please see

REGISTER 22-1: CMCON: COMPARATOR CONTROL REGISTER
R/W-0 U-0 R/C-0 R/C-0 R/W-0 R/W-0 R/W-0 R/W-0
CMIDL — C2EVT C1EVT C2EN C1EN C2OUTEN(1) C1OUTEN(2)
bit 15 bit 8
R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

C2OUT C1OUT C2INV C1INV C2NEG C2POS C1NEG C1POS
bit 7 bit 0

bit 15 CMIDL: Comparator Stop in Idle Mode bit

1 = When device enters Idle mode, module does not generate interrupts; module is still enabled
0 = Continues normal module operation in Idle mode
bit 13 C2EVT: Comparator 2 Event
1 = Comparator output changed states
0 = Comparator output did not change states
bit 12 C1EVT: Comparator 1 Event
1 = Comparator output changed states
0 = Comparator output did not change states
bit 11 C2EN: Comparator 2 Enable
1 = Comparator is enabled
0 = Comparator is disabled
bit 10 C1EN: Comparator 1 Enable
1 = Comparator is enabled
0 = Comparator is disabled
bit 9 C2OUTEN: Comparator 2 Output Enable(1)
1 = Comparator output is driven on the output pad
0 = Comparator output is not driven on the output pad
bit 8 C1OUTEN: Comparator 1 Output Enable(2)
1 = Comparator output is driven on the output pad
0 = Comparator output is not driven on the output pad
bit 7 C2OUT: Comparator 2 Output bit
When C2INV = 0:
1 = C2 VIN+ > C2 VIN-
0 = C2 VIN+ < C2 VIN-
When C2INV = 1:
0 = C2 VIN+ > C2 VIN-
1 = C2 VIN+ < C2 VIN-
Note 1: If C2OUTEN = 1, the C2OUT peripheral output must be configured to an available RPn pin. See
2: If C1OUTEN = 1, the C1OUT peripheral output must be configured to an available RPn pin. See

REGISTER 22-1: CMCON: COMPARATOR CONTROL REGISTER (CONTINUED)
bit 6 C1OUT: Comparator 1 Output bit
When C1INV = 0:
1 = C1 VIN+ > C1 VIN-
0 = C1 VIN+ < C1 VIN-
When C1INV = 1:
0 = C1 VIN+ > C1 VIN-
1 = C1 VIN+ < C1 VIN-
bit 5 C2INV: Comparator 2 Output Inversion bit
1 = C2 output is inverted
0 = C2 output is not inverted
bit 4 C1INV: Comparator 1 Output Inversion bit
1 = C1 output is inverted
0 = C1 output is not inverted
bit 3 C2NEG: Comparator 2 Negative Input Configure bit
1 = Input is connected to VIN+
0 = Input is connected to VIN-
See Figure 22-1 for the Comparator modes.
bit 2 C2POS: Comparator 2 Positive Input Configure bit
0 = Input is connected to CVREF
bit 1 C1NEG: Comparator 1 Negative Input Configure bit
0 = Input is connected to VIN-
bit 0 C1POS: Comparator 1 Positive Input Configure bit
0 = Input is connected to CVREF
Note 1: If C2OUTEN = 1, the C2OUT peripheral output must be configured to an available RPn pin. See
2: If C1OUTEN = 1, the C1OUT peripheral output must be configured to an available RPn pin. See

NOTES:

23.0 COMPARATOR VOLTAGE output voltage, each with 16 distinct levels. The range
to be used is selected by the CVRR bit (CVRCON<5>).
REFERENCE The primary difference between the ranges is the size
Note: This data sheet summarizes the features of of the steps selected by the CVREF Selection bits
this group of PIC24F devices. It is not (CVR<3:0>), with one range offering finer resolution.
intended to be a comprehensive reference The comparator reference supply voltage can come
source. For more information, refer to from either VDD and VSS, or the external VREF+ and
the “PIC24F Family Reference Manual”, VREF-. The voltage source is selected by the CVRSS
“Comparator Voltage Reference bit (CVRCON<4>).
Module” (DS39709).
The settling time of the comparator voltage reference
must be considered when changing the CVREF
23.1 Configuring the Comparator output.
Voltage Reference
The comparator voltage reference module is controlled
through the CVRCON register (Register 23-1). The
comparator voltage reference provides two ranges of
FIGURE 23-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
VREF+
AVDD 8R
CVRSS = 0
CVR<3:0>
CVREN R
R
16-to-1 MUX
16 Steps CVREF
R
R
CVRR 8R
CVRSS = 1
VREF-
CVRSS = 0
AVSS

REGISTER 23-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0
bit 7 bit 0
Legend:

bit 7 CVREN: Comparator Voltage Reference Enable bit
1 = CVREF circuit is powered on
0 = CVREF circuit is powered down
bit 6 CVROE: Comparator VREF Output Enable bit
1 = CVREF voltage level is output on the CVREF pin
0 = CVREF voltage level is disconnected from the CVREF pin
bit 5 CVRR: Comparator VREF Range Selection bit
1 = CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step-size
0 = CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step-size
bit 4 CVRSS: Comparator VREF Source Selection bit
1 = Comparator reference source, CVRSRC = VREF+ – VREF-
0 = Comparator reference source, CVRSRC = AVDD – AVSS
bit 3-0 CVR<3:0>: Comparator VREF Value Selection 0  CVR<3:0>  15 bits
When CVRR = 1:
CVREF = (CVR<3:0>/24) • (CVRSRC)
When CVRR = 0:
CVREF = 1/4 • (CVRSRC) + (CVR<3:0>/32) • (CVRSRC)

24.0 SPECIAL FEATURES 24.1.1 CONSIDERATIONS FOR
CONFIGURING PIC24FJ64GA004
Note: This data sheet summarizes the features FAMILY DEVICES
of this group of PIC24F devices. It is not
intended to be a comprehensive refer- In PIC24FJ64GA004 family devices, the configuration
ence source. For more information, refer bytes are implemented as volatile memory. This means
to the following sections of the “PIC24F that configuration data must be programmed each time
Family Reference Manual”: the device is powered up. Configuration data is stored
in the two words at the top of the on-chip program
• “Watchdog Timer (WDT)” memory space, known as the Flash Configuration
(DS39697) Words. Their specific locations are shown in
• “High-Level Device Integration” Table 24-1. These are packed representations of the
(DS39719) actual device Configuration bits, whose actual
• “Programming and Diagnostics” locations are distributed among five locations in config-
(DS39716) uration space. The configuration data is automatically
loaded from the Flash Configuration Words to the
PIC24FJ64GA004 family devices include several proper Configuration registers during device Resets.
features intended to maximize application flexibility and
reliability, and minimize cost through elimination of Note: Configuration data is reloaded on all types
external components. These are: of device Resets.
• Flexible Configuration
• Watchdog Timer (WDT) TABLE 24-1: FLASH CONFIGURATION
• Code Protection
WORD LOCATIONS FOR
• JTAG Boundary Scan Interface
DEVICES
• In-Circuit Serial Programming
• In-Circuit Emulation Configuration Word
Device Addresses
24.1 Configuration Bits 1 2
The Configuration bits can be programmed (read as ‘0’), PIC24FJ16GA 002BFEh 002BFCh
or left unprogrammed (read as ‘1’), to select various PIC24FJ32GA 0057FEh 0057FCh
device configurations. These bits are mapped starting at
program memory location, F80000h. A complete list of PIC24FJ48GA 0083FEh 0083FCh
locations is shown in Table 24-1. A detailed explanation PIC24FJ64GA 00ABFEh 00ABFCh
of the various bit functions is provided in Register 24-1
through Register 24-4. When creating applications for these devices, users
should always specifically allocate the location of the
Note that address, F80000h, is beyond the user program Flash Configuration Word for configuration data. This is
memory space. In fact, it belongs to the configuration to make certain that program code is not stored in this
memory space (800000h-FFFFFFh), which can only be address when the code is compiled.
accessed using table reads and table writes.
The Configuration bits are reloaded from the Flash
Configuration Word on any device Reset.
The upper byte of both Flash Configuration Words in
program memory should always be ‘1111 1111’. This
makes them appear to be NOP instructions in the
remote event that their locations are ever executed by
accident. Since Configuration bits are not implemented
in the corresponding locations, writing ‘1’s to these
locations has no effect on device operation.

REGISTER 24-1: CW1: FLASH CONFIGURATION WORD 1
U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1
— — — — — — — —
bit 23 bit 16
r-x R/PO-1 R/PO-1 R/PO-1 R/PO-1 r-1 R/PO-1 R/PO-1

r JTAGEN GCP GWRP DEBUG r ICS1 ICS0
bit 15 bit 8
R/PO-1 R/PO-1 r R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1

FWDTEN WINDIS r FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0
bit 7 bit 0
Legend: r = Reserved bit

R = Readable bit PO = Program Once bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared

bit 15 Reserved: The value is unknown; program as ‘0’
bit 14 JTAGEN: JTAG Port Enable bit
1 = JTAG port is enabled
0 = JTAG port is disabled
bit 13 GCP: General Segment Program Memory Code Protection bit
1 = Code protection is disabled
0 = Code protection is enabled for the entire program memory space
bit 12 GWRP: General Segment Code Flash Write Protection bit
1 = Writes to program memory are allowed
0 = Writes to program memory are disabled
bit 11 DEBUG: Background Debugger Enable bit
1 = Device resets into Operational mode
0 = Device resets into Debug mode
bit 10 Reserved: Always maintain as ‘1’
bit 9-8 ICS<1:0>: Emulator Pin Placement Select bits
11 = Emulator EMUC1/EMUD1 pins are shared with PGC1/PGD1
00 = Reserved; do not use
bit 7 FWDTEN: Watchdog Timer Enable bit
1 = Watchdog Timer is enabled
0 = Watchdog Timer is disabled
bit 6 WINDIS: Windowed Watchdog Timer Disable bit
1 = Standard Watchdog Timer is enabled
0 = Windowed Watchdog Timer is enabled; FWDTEN must be ‘1’
bit 5 Reserved
bit 4 FWPSA: WDT Prescaler Ratio Select bit
1 = Prescaler ratio of 1:128
0 = Prescaler ratio of 1:32

REGISTER 24-1: CW1: FLASH CONFIGURATION WORD 1 (CONTINUED)
bit 3-0 WDTPS<3:0>: Watchdog Timer Postscaler Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1

REGISTER 24-2: CW2: FLASH CONFIGURATION WORD 2
U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1
— — — — — — — —
bit 23 bit 16
R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1

(1) (1) (1) (1)
IESO WUTSEL1 WUTSEL0 SOSCSEL1 SOSCSEL0 FNOSC2 FNOSC1 FNOSC0
bit 15 bit 8
R/PO-1 R/PO-1 R/PO-1 R/PO-1 r R/PO-1 R/PO-1 R/PO-1

FCKSM1 FCKSM0 OSCIOFCN IOL1WAY r I2C1SEL POSCMD1 POSCMD0
bit 7 bit 0
Legend: r = Reserved bit

R = Readable bit PO = Program Once bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared

bit 15 IESO: Internal External Switchover bit
1 = IESO mode (Two-Speed Start-up) is enabled
0 = IESO mode (Two-Speed Start-up) is disabled
bit 14-13 WUTSEL<1:0>: Voltage Regulator Standby Mode Wake-up Time Select bits(1)
11 = Default regulator start-up time is used
01 = Fast regulator start-up time is used
x0 = Reserved; do not use
bit 12-11 SOSCSEL<1:0>: Secondary Oscillator Power Mode Select bits(1)
11 = Default (High Drive Strength) mode
01 = Low-Power (Low Drive Strength) mode
x0 = Reserved; do not use
bit 10-8 FNOSC<2:0>: Initial Oscillator Select bits
110 = Reserved
bit 7-6 FCKSM<1:0>: Clock Switching and Fail-Safe Clock Monitor Configuration bits
1x = Clock switching and Fail-Safe Clock Monitor are disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
bit 5 OSCIOFCN: OSCO Pin Configuration bit
If POSCMD<1:0> = 11 or 00:
1 = OSCO/CLKO/RA3 functions as CLKO (FOSC/2)
0 = OSCO/CLKO/RA3 functions as port I/O (RA3)
If POSCMD<1:0> = 10 or 01:
OSCIOFCN has no effect on OSCO/CLKO/RA3.
Note 1: These bits are implemented only in devices with a major silicon revision level of B or later (DEVREV regis-
ter value is 3042h or greater). Refer to Section 28.0 “Packaging Information” in the device data sheet
for the location and interpretation of product date codes.

REGISTER 24-2: CW2: FLASH CONFIGURATION WORD 2 (CONTINUED)
bit 4 IOL1WAY: IOLOCK One-Way Set Enable bit
1 = The IOLOCK (OSCCON<6>) bit can be set once, provided the unlock sequence has been
completed. Once set, the Peripheral Pin Select registers cannot be written to a second time.
0 = The IOLOCK (OSCCON<6>) bit can be set and cleared as needed, provided the unlock sequence
has been completed
bit 3 Reserved
bit 2 I2C1SEL: I2C1 Pin Select bit
1 = Use default SCL1/SDA1 pins
0 = Use alternate SCL1/SDA1 pins
bit 1-0 POSCMD<1:0:> Primary Oscillator Configuration bits
11 = Primary oscillator is disabled
10 = HS Oscillator mode is selected
01 = XT Oscillator mode is selected
00 = EC Oscillator mode is selected
Note 1: These bits are implemented only in devices with a major silicon revision level of B or later (DEVREV regis-
ter value is 3042h or greater). Refer to Section 28.0 “Packaging Information” in the device data sheet
for the location and interpretation of product date codes.
REGISTER 24-3: DEVID: DEVICE ID REGISTER

U U U U U U U U
— — — — — — — —
bit 23 bit 16
U U R R R R R R
— — FAMID7 FAMID6 FAMID5 FAMID4 FAMID3 FAMID2
bit 15 bit 8
R R R R R R R R
FAMID1 FAMID0 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0
bit 7 bit 0
Legend: R = Read-only bit U = Unimplemented bit

bit 13-6 FAMID<7:0>: Device Family Identifier bits
00010001 = PIC24FJ64GA004 family
bit 5-0 DEV<5:0>: Individual Device Identifier bits
000100 = PIC24FJ16GA002
000101 = PIC24FJ32GA002
000110 = PIC24FJ48GA002
000111 = PIC24FJ64GA002
001100 = PIC24FJ16GA004
001101 = PIC24FJ32GA004
001110 = PIC24FJ48GA004
001111 = PIC24FJ64GA004

REGISTER 24-4: DEVREV: DEVICE REVISION REGISTER
U U U U U U U U
— — — — — — — —
bit 23 bit 16
U U U U U U U R
— — — — — — — MAJRV2
bit 15 bit 8
R R U U U R R R
MAJRV1 MAJRV0 — — — DOT2 DOT1 DOT0
bit 7 bit 0
Legend: R = Read-only bit U = Unimplemented bit

bit 8-6 MAJRV<2:0>: Major Revision Identifier bits
bit 2-0 DOT<2:0>: Minor Revision Identifier bits

24.2 On-Chip Voltage Regulator FIGURE 24-1: CONNECTIONS FOR THE
ON-CHIP REGULATOR
All of the PIC24FJ64GA004 family devices power their
core digital logic at a nominal 2.5V. This may create an
Regulator Enabled (DISVREG tied to VSS):
issue for designs that are required to operate at a
higher typical voltage, such as 3.3V. To simplify system 3.3V
design, all devices in the PIC24FJ64GA004 family PIC24FJ64GA
incorporate an on-chip regulator that allows the device VDD
to run its core logic from VDD.
DISVREG
The regulator is controlled by the DISVREG pin. Tying
VSS to the pin enables the regulator, which in turn, pro- VDDCORE/VCAP
vides power to the core from the other VDD pins. When CEFC
(10 F typ) VSS
the regulator is enabled, a low-ESR capacitor (such as
ceramic) must be connected to the VDDCORE/VCAP pin
(Figure 24-1). This helps to maintain the stability of the
regulator. The recommended value for the filter capacitor Regulator Disabled (DISVREG tied to VDD):
is provided in Section 27.1 “DC Characteristics”.
2.5V(1) 3.3V(1)
If DISVREG is tied to VDD, the regulator is disabled. In
this case, separate power for the core logic at a nomi- PIC24FJ64GA
nal 2.5V must be supplied to the device on the VDD
VDDCORE/VCAP pin to run the I/O pins at higher voltage DISVREG
levels, typically 3.3V. Alternatively, the VDDCORE/VCAP
and VDD pins can be tied together to operate at a lower VDDCORE/VCAP
nominal voltage. Refer to Figure 24-1 for possible VSS
configurations.
24.2.1 VOLTAGE REGULATOR TRACKING

MODE AND LOW-VOLTAGE Regulator Disabled (VDD tied to VDDCORE):
DETECTION
2.5V(1)
When it is enabled, the on-chip regulator provides a PIC24FJ64GA
constant voltage of 2.5V nominal to the digital core
VDD
logic.
DISVREG
The regulator can provide this level from a VDD of about
2.5V, all the way up to the device’s VDDMAX. It does not VDDCORE/VCAP
have the capability to boost VDD levels below 2.5V. In
VSS
order to prevent “brown out” conditions, when the volt-
age drops too low for the regulator, the regulator enters
Tracking mode. In Tracking mode, the regulator output
follows VDD, with a typical voltage drop of 100 mV. Note 1: These are typical operating voltages. Refer
to Section 27.1 “DC Characteristics” for
When the device enters Tracking mode, it is no longer the full operating ranges of VDD and
possible to operate at full speed. To provide information VDDCORE.
about when the device enters Tracking mode, the
on-chip regulator includes a simple, Low-Voltage
Detect (LVD) circuit. When VDD drops below full-speed 24.2.2 ON-CHIP REGULATOR AND BOR
operating voltage, the circuit sets the Low-Voltage When the on-chip regulator is enabled,
Detect Interrupt Flag, LVDIF (IFS4<8>). This can be PIC24FJ64GA004 family devices also have a simple
used to generate an interrupt and put the application brown-out capability. If the voltage supplied to the reg-
into a low-power operational mode or trigger an orderly ulator is inadequate to maintain the tracking level, the
shutdown. regulator Reset circuitry will generate a Brown-out
Low-Voltage Detection is only available when the Reset. This event is captured by the BOR flag bit
regulator is enabled. (RCON<1>). The brown-out voltage levels are
specified in Section 27.1 “DC Characteristics”.

24.2.3 ON-CHIP REGULATOR AND POR When the regulator’s Standby mode is turned off
(PMSLP = 1), Flash program memory stays powered
When the voltage regulator is enabled, it takes approx-
in Sleep mode and the device can wake-up in less than
imately 10 µs for it to generate output. During this time,
10 s. When PMSLP is set, the power consumption
designated as TVREG, code execution is disabled.
while in Sleep mode will be approximately 40 A higher
TVREG is applied every time the device resumes oper-
than power consumption when the regulator is allowed
ation after any power-down, including Sleep mode.
to enter Standby mode.
TVREG is determined by the setting of the PMSLP bit
(RCON<8>) and the WUTSELx Configuration bits
(CW2<14:13>). For more information on TVREG, see 24.3 Watchdog Timer (WDT)
Section 27.0 “Electrical Characteristics”. For PIC24FJ64GA004 family devices, the WDT is
If the regulator is disabled, a separate Power-up Timer driven by the LPRC oscillator. When the WDT is
(PWRT) is automatically enabled. The PWRT adds a enabled, the clock source is also enabled.
fixed delay of 64 ms nominal delay at device start-up The nominal WDT clock source from LPRC is 31 kHz.
(POR or BOR only). When waking up from Sleep with This feeds a prescaler that can be configured for either
the regulator disabled, TVREG is used to determine the 5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
wake-up time. To decrease the device wake-up time The prescaler is set by the FWPSA Configuration bit.
when operating with the regulator disabled, the PMSLP With a 31 kHz input, the prescaler yields a nominal
bit can be set. WDT Time-out period (TWDT) of 1 ms in 5-bit mode or
4 ms in 7-bit mode.
24.2.4 POWER-UP REQUIREMENTS
A variable postscaler divides down the WDT prescaler
The on-chip regulator is designed to meet the power-up
output and allows for a wide range of time-out periods.
requirements for the device. If the application does not
The postscaler is controlled by the WDTPS<3:0> Con-
use the regulator, then strict power-up conditions must
figuration bits (CW1<3:0>), which allow the selection of
be adhered to. While powering up, VDDCORE must
a total of 16 settings, from 1:1 to 1:32,768. Using the
never exceed VDD by 0.3 volts.
prescaler and postscaler, time-out periods, ranges from
Note: For more information, see Section 27.0 1 ms to 131 seconds can be achieved.
“Electrical Characteristics”. The WDT, prescaler and postscaler are reset:
• On any device Reset
24.2.5 VOLTAGE REGULATOR STANDBY
MODE • On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
When enabled, the on-chip regulator always consumes after changing the NOSCx bits) or by hardware
a small incremental amount of current over IDD/IPD, (i.e., Fail-Safe Clock Monitor)
including when the device is in Sleep mode, even
• When a PWRSAV instruction is executed
though the core digital logic does not require power. To
(i.e., Sleep or Idle mode is entered)
provide additional savings in applications where power
resources are critical, the regulator automatically • When the device exits Sleep or Idle mode to
places itself into Standby mode whenever the device resume normal operation
goes into Sleep mode. This feature is controlled by the • By a CLRWDT instruction during normal execution
PMSLP bit (RCON<8>). By default, this bit is cleared, If the WDT is enabled, it will continue to run during
which enables Standby mode. Sleep or Idle modes. When the WDT time-out occurs,
For select PIC24FJ64GA004 family devices, the time the device will wake the device and code execution will
required for regulator wake-up from Standby mode is continue from where the PWRSAV instruction was
controlled by the WUTSEL<1:0> Configuration bits executed. The corresponding SLEEP or IDLE bits
(CW2<14:13>). The default wake-up time for all (RCON<3:2>) will need to be cleared in software after
devices is 190 s. Where the WUTSELx Configuration the device wakes up.
bits are implemented, a fast wake-up option is also The WDT Flag bit, WDTO (RCON<4>), is not auto-
available. When WUTSEL<1:0> = 01, the regulator matically cleared following a WDT time-out. To detect
wake-up time is 25 s. subsequent WDT events, the flag must be cleared in
Note: This feature is implemented only on software.
PIC24FJ64GA004 family devices with a Note: The CLRWDT and PWRSAV instructions
major silicon revision level of B or later clear the prescaler and postscaler counts
(DEVREV register value is 3042h or when executed.
greater).

24.3.1 WINDOWED OPERATION 24.3.2 CONTROL REGISTER
The Watchdog Timer has an optional Fixed Window The WDT is enabled or disabled by the FWDTEN
mode of operation. In this Windowed mode, CLRWDT Configuration bit. When the FWDTEN Configuration bit
instructions can only reset the WDT during the last 1/4 is set, the WDT is always enabled.
of the programmed WDT period. A CLRWDT instruction
The WDT can be optionally controlled in software when
executed before that window causes a WDT Reset,
the FWDTEN Configuration bit has been programmed
similar to a WDT time-out.
to ‘0’. The WDT is enabled in software by setting the
Windowed WDT mode is enabled by programming the SWDTEN control bit (RCON<5>). The SWDTEN
WINDIS Configuration bit (CW1<6>) to ‘0’. control bit is cleared on any device Reset. The software
WDT option allows the user to enable the WDT for
critical code segments and disable the WDT during
non-critical segments for maximum power savings.
FIGURE 24-2: WDT BLOCK DIAGRAM
SWDTEN
LPRC Control
FWDTEN Wake from Sleep
FWPSA WDTPS<3:0>
Prescaler WDT Postscaler WDT Overflow

LPRC Input (5-bit/7-bit) Counter 1:1 to 1:32.768 Reset
31 kHz 1 ms/4 ms
All Device Resets
Transition to
New Clock Source
Exit Sleep or
Idle Mode
CLRWDT Instr.
PWRSAV Instr.
Sleep or Idle Mode

24.4 JTAG Interface 24.6 In-Circuit Serial Programming
PIC24FJ64GA004 family devices implement a JTAG PIC24FJ64GA004 family microcontrollers can be seri-
interface, which supports boundary scan device ally programmed while in the end application circuit.
testing. This is simply done with two lines for clock (PGCx) and
data (PGDx), and three other lines for power, ground
24.5 Program Verification and and the programming voltage. This allows customers to
Code Protection manufacture boards with unprogrammed devices and
then program the microcontroller just before shipping
For all devices in the PIC24FJ64GA004 family, the the product. This also allows the most recent firmware
on-chip program memory space is treated as a single or a custom firmware to be programmed.
block. Code protection for this block is controlled by
one Configuration bit, GCP. This bit inhibits external 24.7 In-Circuit Debugger
reads and writes to the program memory space. It has
no direct effect in normal execution mode. When MPLAB® ICD 2 is selected as a debugger, the
in-circuit debugging functionality is enabled. This func-
Write protection is controlled by the GWRP bit in Con-
tion allows simple debugging functions when used with
figuration Word 1. When GWRP is programmed to ‘0’,
MPLAB IDE. Debugging functionality is controlled
internal write and erase operations to program memory
through the EMUCx (Emulation/Debug Clock) and
are blocked.
EMUDx (Emulation/Debug Data) pins.
24.5.1 CONFIGURATION REGISTER To use the in-circuit debugger function of the device,
PROTECTION the design must implement ICSP connections to
MCLR, VDD, VSS, PGCx, PGDx and the
The Configuration registers are protected against
EMUDx/EMUCx pin pair. In addition, when the feature
inadvertent or unwanted changes, or reads in two
is enabled, some of the resources are not available for
ways. The primary protection method is the same as
general use. These resources include the first 80 bytes
that of the RP registers – shadow registers contain a
of data RAM and two I/O pins.
complimentary value which is constantly compared
with the actual value.
To safeguard against unpredictable events, Configura-
tion bit changes, resulting from individual cell level
disruptions (such as ESD events), will cause a parity
error and trigger a device Reset.
The data for the Configuration registers is derived from
the Flash Configuration Words in program memory.
When the GCP bit is set, the source data for device
configuration is also protected as a consequence.

25.0 DEVELOPMENT SUPPORT 25.1 MPLAB X Integrated Development
Environment Software
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user
of software and hardware development tools: interface for Microchip and third-party software, and
• Integrated Development Environment hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
- MPLAB® X IDE Software
MPLAB X IDE is an entirely new IDE with a host of free
• Compilers/Assemblers/Linkers software components and plug-ins for high-
- MPLAB XC Compiler performance application development and debugging.
- MPASMTM Assembler Moving between tools and upgrading from software
- MPLINKTM Object Linker/ simulators to hardware debugging and programming
MPLIBTM Object Librarian tools is simple with the seamless user interface.
- MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs,
Various Device Families a configurable watch window and a feature-rich editor
• Simulators that includes code completion and context menus,
- MPLAB X SIM Software Simulator MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
• Emulators
multiple projects with simultaneous debugging, MPLAB
- MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced
• In-Circuit Debuggers/Programmers users.
- MPLAB ICD 3 Feature-Rich Editor:
- PICkit™ 3
• Color syntax highlighting
• Device Programmers
• Smart code completion makes suggestions and
- MPLAB PM3 Device Programmer provides hints as you type
• Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined
Evaluation Kits and Starter Kits rules
• Third-party development tools • Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker

25.2 MPLAB XC Compilers 25.4 MPLINK Object Linker/
The MPLAB XC Compilers are complete ANSI C
MPLIB Object Librarian
compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable
and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link
integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using
ease of use. MPLAB XC Compilers run on Windows, directives from a linker script.
Linux or MAC OS X.
The MPLIB Object Librarian manages the creation and
For easy source level debugging, the compilers provide modification of library files of precompiled code. When
debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only
IDE. the modules that contain that routine will be linked in
The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be
devices and commands, with no time or memory used efficiently in many different applications.
restrictions, and offer sufficient code optimization for The object linker/library features include:
most applications.
• Efficient linking of single libraries instead of many
MPLAB XC Compilers include an assembler, linker and smaller files
utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping
files that can then be archived or linked with other relo- related modules together
catable object files and archives to create an execut-
• Flexible creation of libraries with easy module
able file. MPLAB XC Compiler uses the assembler to
listing, replacement, deletion and extraction
produce its object file. Notable features of the assem-
bler include:
25.5 MPLAB Assembler, Linker and
• Support for the entire device instruction set
Librarian for Various Device
• Support for fixed-point and floating-point data
Families
• Command-line interface
• Rich directive set MPLAB Assembler produces relocatable machine
• Flexible macro language code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
• MPLAB X IDE compatibility
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
25.3 MPASM Assembler then be archived or linked with other relocatable object
The MPASM Assembler is a full-featured, universal files and archives to create an executable file. Notable
macro assembler for PIC10/12/16/18 MCUs. features of the assembler include:
The MPASM Assembler generates relocatable object • Support for the entire device instruction set
files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data
files, MAP files to detail memory usage and symbol • Command-line interface
reference, absolute LST files that contain source lines • Rich directive set
and generated machine code, and COFF files for • Flexible macro language
debugging.
• MPLAB X IDE compatibility
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process

25.6 MPLAB X SIM Software Simulator 25.8 MPLAB ICD 3 In-Circuit Debugger
The MPLAB X SIM Software Simulator allows code
System
development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is
ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware
level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and
examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash
a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful,
logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB
buffer and logic analyzer display extend the power of IDE.
the simulator to record and track program execution,
The MPLAB ICD 3 In-Circuit Debugger probe is
actions on I/O, most peripherals and internal registers.
connected to the design engineer’s PC using a high-
The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target
symbolic debugging using the MPLAB XC Compilers, with a connector compatible with the MPLAB ICD 2 or
and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers.
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software 25.9 PICkit 3 In-Circuit Debugger/
development tool.
Programmer
25.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program-
Emulator System ming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is
Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full-
Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the tar-
programs all 8, 16 and 32-bit MCU, and DSC devices get via a Microchip debug (RJ-11) connector (compati-
with the easy-to-use, powerful graphical user interface of ble with MPLAB ICD 3 and MPLAB REAL ICE). The
the MPLAB X IDE. connector uses two device I/O pins and the Reset line
The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial
PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™).
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11) 25.10 MPLAB PM3 Device Programmer
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection The MPLAB PM3 Device Programmer is a universal,
(CAT5). CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display
downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod-
significant advantages over competitive emulators ular, detachable socket assembly to support various
including full-speed emulation, run-time variable package types. The ICSP cable assembly is included
watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB
probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program
three meters) interconnection cables. PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.

25.11 Demonstration/Development 25.12 Third-Party Development Tools
Boards, Evaluation Kits, and Microchip also offers a great collection of tools from
Starter Kits third-party vendors. These tools are carefully selected
A wide variety of demonstration, development and to offer good value and unique functionality.
evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers
DSCs allows quick application development on fully from companies, such as SoftLog and CCS
functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel
areas for adding custom circuitry and provide applica- and Trace Systems
tion firmware and source code for examination and • Protocol Analyzers from companies, such as
modification. Saleae and Total Phase
The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as
temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex
interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies,
EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstra-
tion software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.

26.0 INSTRUCTION SET SUMMARY The literal instructions that involve data movement may
use some of the following operands:
Note: This chapter is a brief summary of the • A literal value to be loaded into a W register or file
PIC24F Instruction Set Architecture (ISA) register (specified by the value of ‘k’)
and is not intended to be a comprehensive
• The W register or file register where the literal
reference source.
value is to be loaded (specified by ‘Wb’ or ‘f’)
The PIC24F instruction set adds many enhancements However, literal instructions that involve arithmetic or
to the previous PIC® MCU instruction sets, while main- logical operations use some of the following operands:
taining an easy migration from previous PIC MCU
• The first source operand which is a register ‘Wb’
instruction sets. Most instructions are a single program
without any address modifier
memory word. Only three instructions require two
program memory locations. • The second source operand which is a literal
value
Each single-word instruction is a 24-bit word divided
• The destination of the result (only if not the same
into an 8-bit opcode, which specifies the instruction
as the first source operand) which is typically a
type and one or more operands, which further specify
register ‘Wd’ with or without an address modifier
the operation of the instruction. The instruction set is
highly orthogonal and is grouped into four basic The control instructions may use some of the following
categories: operands:
• Word or byte-oriented operations • A program memory address
• Bit-oriented operations • The mode of the table read and table write
• Literal operations instructions
• Control operations All instructions are a single word, except for certain
double-word instructions, which were made
Table 26-1 shows the general symbols used in
double-word instructions so that all the required infor-
describing the instructions. The PIC24F instruction set
mation is available in these 48 bits. In the second word,
summary in Table 26-2 lists all the instructions, along
the 8 MSbs are ‘0’s. If this second word is executed as
with the status flags affected by each instruction.
an instruction (by itself), it will execute as a NOP.
Most word or byte-oriented W register instructions
Most single-word instructions are executed in a single
(including barrel shift instructions) have three
instruction cycle, unless a conditional test is true or the
operands:
Program Counter (PC) is changed as a result of the
• The first source operand which is typically a instruction. In these cases, the execution takes two
register ‘Wb’ without any address modifier instruction cycles, with the additional instruction
• The second source operand which is typically a cycle(s) executed as a NOP. Notable exceptions are the
register ‘Ws’ with or without an address modifier BRA (unconditional/computed branch), indirect
• The destination of the result which is typically a CALL/GOTO, all table reads and writes, and
register ‘Wd’ with or without an address modifier RETURN/RETFIE instructions, which are single-word
instructions but take two or three cycles.
However, word or byte-oriented file register instructions
have two operands: Certain instructions that involve skipping over the sub-
sequent instruction require either two or three cycles if
• The file register specified by the value, ‘f’
the skip is performed, depending on whether the
• The destination, which could either be the file instruction being skipped is a single-word or two-word
register ‘f’ or the W0 register, which is denoted as instruction. Moreover, double-word moves require two
‘WREG’ cycles. The double-word instructions execute in two
Most bit-oriented instructions (including simple instruction cycles.
rotate/shift instructions) have two operands:
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register
(specified by a literal value or indirectly by the
contents of register, ‘Wb’)

TABLE 26-1: SYMBOLS USED IN OPCODE DESCRIPTIONS
Field Description
#text Means literal defined by “text”

(text) Means “content of text”
[text] Means “the location addressed by text”
{ } Optional field or operation
<n:m> Register bit field
.b Byte mode selection
.d Double-Word mode selection
.S Shadow register select
.w Word mode selection (default)
bit4 4-bit bit selection field (used in word addressed instructions) {0...15}
C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr Absolute address, label or expression (resolved by the linker)
f File register address {0000h...1FFFh}
lit1 1-bit unsigned literal {0,1}
lit4 4-bit unsigned literal {0...15}
lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
lit23 23-bit unsigned literal {0...8388608}; LSB must be ‘0’
None Field does not require an entry, may be blank
PC Program Counter
Slit10 10-bit signed literal {-512...511}
Wb Base W register {W0..W15}
Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo Destination W register 
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn Dividend, Divisor working register pair (direct addressing)
Wn One of 16 working registers {W0..W15}
Wnd One of 16 destination working registers {W0..W15}
Wns One of 16 source working registers {W0..W15}
WREG W0 (working register used in file register instructions)
Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }

TABLE 26-2: INSTRUCTION SET OVERVIEW
Assembly # of # of Status Flags
Assembly Syntax Description
Mnemonic Words Cycles Affected
ADD ADD f f = f + WREG 1 1 C, DC, N, OV, Z

ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z
ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z
ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z
ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z
ADDC ADDC f f = f + WREG + (C) 1 1 C, DC, N, OV, Z
ADDC f,WREG WREG = f + WREG + (C) 1 1 C, DC, N, OV, Z
ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C, DC, N, OV, Z
ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C, DC, N, OV, Z
ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C, DC, N, OV, Z
AND AND f f = f .AND. WREG 1 1 N, Z
AND f,WREG WREG = f .AND. WREG 1 1 N, Z
AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N, Z
AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N, Z
AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N, Z
ASR ASR f f = Arithmetic Right Shift f 1 1 C, N, OV, Z
ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C, N, OV, Z
ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C, N, OV, Z
ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N, Z
ASR Wb,#lit4,Wnd Wnd = Arithmetic Right Shift Wb by lit4 1 1 N, Z
BCLR BCLR f,#bit4 Bit Clear f 1 1 None
BCLR Ws,#bit4 Bit Clear Ws 1 1 None
BRA BRA C,Expr Branch if Carry 1 1 (2) None
BRA GE,Expr Branch if Greater than or Equal 1 1 (2) None
BRA GEU,Expr Branch if Unsigned Greater than or Equal 1 1 (2) None
BRA GT,Expr Branch if Greater than 1 1 (2) None
BRA GTU,Expr Branch if Unsigned Greater than 1 1 (2) None
BRA LE,Expr Branch if Less than or Equal 1 1 (2) None
BRA LEU,Expr Branch if Unsigned Less than or Equal 1 1 (2) None
BRA LT,Expr Branch if Less than 1 1 (2) None
BRA LTU,Expr Branch if Unsigned Less than 1 1 (2) None
BRA N,Expr Branch if Negative 1 1 (2) None
BRA NC,Expr Branch if Not Carry 1 1 (2) None
BRA NN,Expr Branch if Not Negative 1 1 (2) None
BRA NOV,Expr Branch if Not Overflow 1 1 (2) None
BRA NZ,Expr Branch if Not Zero 1 1 (2) None
BRA OV,Expr Branch if Overflow 1 1 (2) None
BRA Expr Branch Unconditionally 1 2 None
BRA Z,Expr Branch if Zero 1 1 (2) None
BRA Wn Computed Branch 1 2 None
BSET BSET f,#bit4 Bit Set f 1 1 None
BSET Ws,#bit4 Bit Set Ws 1 1 None
BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None
BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None
BTG BTG f,#bit4 Bit Toggle f 1 1 None
BTG Ws,#bit4 Bit Toggle Ws 1 1 None
BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None
(2 or 3)
BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None
(2 or 3)

TABLE 26-2: INSTRUCTION SET OVERVIEW (CONTINUED)
BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None

(2 or 3)
BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None
(2 or 3)
BTST BTST f,#bit4 Bit Test f 1 1 Z
BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C
BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z
BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C
BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z
BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z
BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C
BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z
CALL CALL lit23 Call Subroutine 2 2 None
CALL Wn Call Indirect Subroutine 1 2 None
CLR CLR f f = 0x0000 1 1 None
CLR WREG WREG = 0x0000 1 1 None
CLR Ws Ws = 0x0000 1 1 None
CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO, Sleep
COM COM f f=f 1 1 N, Z
COM f,WREG WREG = f 1 1 N, Z
COM Ws,Wd Wd = Ws 1 1 N, Z
CP CP f Compare f with WREG 1 1 C, DC, N, OV, Z
CP Wb,#lit5 Compare Wb with lit5 1 1 C, DC, N, OV, Z
CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C, DC, N, OV, Z
CP0 CP0 f Compare f with 0x0000 1 1 C, DC, N, OV, Z
CP0 Ws Compare Ws with 0x0000 1 1 C, DC, N, OV, Z
CPB CPB f Compare f with WREG, with Borrow 1 1 C, DC, N, OV, Z
CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C, DC, N, OV, Z
CPB Wb,Ws Compare Wb with Ws, with Borrow 1 1 C, DC, N, OV, Z
(Wb – Ws – C)
CPSEQ CPSEQ Wb,Wn Compare Wb with Wn, Skip if = 1 1 None
(2 or 3)
CPSGT CPSGT Wb,Wn Compare Wb with Wn, Skip if > 1 1 None
(2 or 3)
CPSLT CPSLT Wb,Wn Compare Wb with Wn, Skip if < 1 1 None
(2 or 3)
CPSNE CPSNE Wb,Wn Compare Wb with Wn, Skip if  1 1 None
(2 or 3)
DAW DAW.B Wn Wn = Decimal Adjust Wn 1 1 C
DEC DEC f f = f –1 1 1 C, DC, N, OV, Z
DEC f,WREG WREG = f –1 1 1 C, DC, N, OV, Z
DEC Ws,Wd Wd = Ws – 1 1 1 C, DC, N, OV, Z
DEC2 DEC2 f f=f–2 1 1 C, DC, N, OV, Z
DEC2 f,WREG WREG = f – 2 1 1 C, DC, N, OV, Z
DEC2 Ws,Wd Wd = Ws – 2 1 1 C, DC, N, OV, Z
DISI DISI #lit14 Disable Interrupts for k Instruction Cycles 1 1 None
DIV DIV.SW Wm,Wn Signed 16/16-bit Integer Divide 1 18 N, Z, C, OV
DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N, Z, C, OV
DIV.UW Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N, Z, C, OV
DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N, Z, C, OV
EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None
FBCL FFBCL Ws, Wnd Find Bit Change from left (MSb) Side 1 1 None
FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C
FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C

GOTO GOTO Expr Go to Address 2 2 None

GOTO Wn Go to Indirect 1 2 None
INC INC f f=f+1 1 1 C, DC, N, OV, Z
INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z
INC Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, Z
INC2 INC2 f f=f+2 1 1 C, DC, N, OV, Z
INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z
INC2 Ws,Wd Wd = Ws + 2 1 1 C, DC, N, OV, Z
IOR IOR f f = f .IOR. WREG 1 1 N, Z
IOR f,WREG WREG = f .IOR. WREG 1 1 N, Z
IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N, Z
IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N, Z
IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N, Z
LNK LNK #lit14 Link Frame Pointer 1 1 None
LSR LSR f f = Logical Right Shift f 1 1 C, N, OV, Z
LSR f,WREG WREG = Logical Right Shift f 1 1 C, N, OV, Z
LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C, N, OV, Z
LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N, Z
LSR Wb,#lit4,Wnd Wnd = Logical Right Shift Wb by lit4 1 1 N, Z
MOV MOV f,Wn Move f to Wn 1 1 None
MOV [Wns+Slit10],Wnd Move [Wns+Slit10] to Wnd 1 1 None
MOV f Move f to f 1 1 N, Z
MOV f,WREG Move f to WREG 1 1 None
MOV #lit16,Wn Move 16-bit Literal to Wn 1 1 None
MOV.b #lit8,Wn Move 8-bit Literal to Wn 1 1 None
MOV Wn,f Move Wn to f 1 1 None
MOV Wns,[Wns+Slit10] Move Wns to [Wns+Slit10] 1 1 None
MOV Wso,Wdo Move Ws to Wd 1 1 None
MOV WREG,f Move WREG to f 1 1 None
MOV.D Wns,Wd Move Double from W(ns):W(ns+1) to Wd 1 2 None
MOV.D Ws,Wnd Move Double from Ws to W(nd+1):W(nd) 1 2 None
MUL MUL.SS Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) 1 1 None
MUL.SU Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) 1 1 None
MUL.US Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws) 1 1 None
MUL.UU Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws) 1 1 None
MUL.SU Wb,#lit5,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5) 1 1 None
MUL.UU Wb,#lit5,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5) 1 1 None
MUL f W3:W2 = f * WREG 1 1 None
NEG NEG f f=f+1 1 1 C, DC, N, OV, Z
NEG f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z
NEG Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, Z
NOP NOP No Operation 1 1 None
NOPR No Operation 1 1 None
POP POP f Pop f from Top-of-Stack (TOS) 1 1 None
POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None
POP.D Wnd Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) 1 2 None
POP.S Pop Shadow Registers 1 1 All
PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None
PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None
PUSH.D Wns Push W(ns):W(ns+1) to Top-of-Stack (TOS) 1 2 None
PUSH.S Push Shadow Registers 1 1 None

PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep

RCALL RCALL Expr Relative Call 1 2 None
RCALL Wn Computed Call 1 2 None
REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None
REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None
RESET RESET Software Device Reset 1 1 None
RETFIE RETFIE Return from Interrupt 1 3 (2) None
RETLW RETLW #lit10,Wn Return with Literal in Wn 1 3 (2) None
RETURN RETURN Return from Subroutine 1 3 (2) None
RLC RLC f f = Rotate Left through Carry f 1 1 C, N, Z
RLC f,WREG WREG = Rotate Left through Carry f 1 1 C, N, Z
RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C, N, Z
RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N, Z
RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N, Z
RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N, Z
RRC RRC f f = Rotate Right through Carry f 1 1 C, N, Z
RRC f,WREG WREG = Rotate Right through Carry f 1 1 C, N, Z
RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C, N, Z
RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N, Z
RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N, Z
RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N, Z
SE SE Ws,Wnd Wnd = Sign-Extended Ws 1 1 C, N, Z
SETM SETM f f = FFFFh 1 1 None
SETM WREG WREG = FFFFh 1 1 None
SETM Ws Ws = FFFFh 1 1 None
SL SL f f = Left Shift f 1 1 C, N, OV, Z
SL f,WREG WREG = Left Shift f 1 1 C, N, OV, Z
SL Ws,Wd Wd = Left Shift Ws 1 1 C, N, OV, Z
SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N, Z
SL Wb,#lit4,Wnd Wnd = Left Shift Wb by lit4 1 1 N, Z
SUB SUB f f = f – WREG 1 1 C, DC, N, OV, Z
SUB f,WREG WREG = f – WREG 1 1 C, DC, N, OV, Z
SUB #lit10,Wn Wn = Wn – lit10 1 1 C, DC, N, OV, Z
SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C, DC, N, OV, Z
SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C, DC, N, OV, Z
SUBB SUBB f f = f – WREG – (C) 1 1 C, DC, N, OV, Z
SUBB f,WREG WREG = f – WREG – (C) 1 1 C, DC, N, OV, Z
SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C, DC, N, OV, Z
SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C, DC, N, OV, Z
SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C, DC, N, OV, Z
SUBR SUBR f f = WREG – f 1 1 C, DC, N, OV, Z
SUBR f,WREG WREG = WREG – f 1 1 C, DC, N, OV, Z
SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C, DC, N, OV, Z
SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C, DC, N, OV, Z
SUBBR SUBBR f f = WREG – f – (C) 1 1 C, DC, N, OV, Z
SUBBR f,WREG WREG = WREG – f – (C) 1 1 C, DC, N, OV, Z
SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C, DC, N, OV, Z
SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C, DC, N, OV, Z
SWAP SWAP.b Wn Wn = Nibble Swap Wn 1 1 None
SWAP Wn Wn = Byte Swap Wn 1 1 None

TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None

TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None
TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None
TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None
ULNK ULNK Unlink Frame Pointer 1 1 None
XOR XOR f f = f .XOR. WREG 1 1 N, Z
XOR f,WREG WREG = f .XOR. WREG 1 1 N, Z
XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N, Z
XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N, Z
XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N, Z
ZE ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C, Z, N

NOTES:

27.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC24FJ64GA004 family electrical characteristics. Additional information will
be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC24FJ64GA004 family are listed below. Exposure to these maximum rating
conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other
conditions above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings(†)

Ambient temperature under bias.............................................................................................................-40°C to +135°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V)
Voltage on any digital only pin with respect to VSS .................................................................................. -0.3V to +6.0V
Voltage on VDDCORE with respect to VSS ................................................................................................. -0.3V to +3.0V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin (Note 1)................................................................................................................250 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports (Note 1)....................................................................................................200 mA
Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 27-1).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.

27.1 DC Characteristics
FIGURE 27-1: PIC24FJ64GA004 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
3.00V
2.75V 2.75V
Voltage (VDDCORE)(1)
2.50V PIC24FJ64GA004/32GA004/64GA002/32GA002
2.35V
2.25V
2.00V
16 MHz 32 MHz
Frequency
For frequencies between 16 MHz and 32 MHz, FMAX = (45.7 MHz/V) * (VDDCORE – 2V) + 16 MHz.
Note 1: WHEN the voltage regulator is disabled, VDD and VDDCORE must be maintained so that
VDDCOREVDD3.6V.
FIGURE 27-2: PIC24FJ64GA004 FAMILY VOLTAGE-FREQUENCY GRAPH

(EXTENDED TEMPERATURE)
3.00V
2.75V 2.75V
Voltage (VDDCORE)(1)
2.50V PIC24FJ64GA004/32GA004/64GA002/32GA002
2.35V
2.25V
2.00V
16 MHz 24 MHz
Frequency
For frequencies between 16 MHz and 24 MHz, FMAX = (22.9 MHz/V) * (VDDCORE – 2V) + 16 MHz.
Note 1: WHEN the voltage regulator is disabled, VDD and VDDCORE must be maintained so that
VDDCOREVDD3.6V.

TABLE 27-1: THERMAL OPERATING CONDITIONS
Rating Symbol Min Typ Max Unit
PIC24FJ64GA004 Family:
Operating Junction Temperature Range TJ -40 — +140 °C
Operating Ambient Temperature Range TA -40 — +125 °C
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD –  IOH) PD PINT + PI/O W
I/O Pin Power Dissipation:
PI/O =  ({VDD – VOH} x IOH) +  (VOL x IOL)
Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W
TABLE 27-2: THERMAL PACKAGING CHARACTERISTICS

Characteristic Symbol Typ Max Unit Notes
Package Thermal Resistance, 300 mil SOIC JA 49 — °C/W (Note 1)
Package Thermal Resistance, 6x6x0.9 mm QFN JA 33.7 — °C/W (Note 1)
Package Thermal Resistance, 8x8x1 mm QFN JA 28 — °C/W (Note 1)
Package Thermal Resistance, 10x10x1 mm TQFP JA 39.3 — °C/W (Note 1)
Note 1: Junction to ambient thermal resistance; Theta-JA (JA) numbers are achieved by package simulations.

TABLE 27-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Param
Symbol Characteristic Min Typ(1) Max Units Conditions
No.
Operating Voltage
DC10 Supply Voltage
VDD VBORMIN — 3.6 V Regulator enabled
VDD VDDCORE — 3.6 V Regulator disabled
VDDCORE 2.0 — 2.75 V Regulator disabled
DC12 VDR RAM Data Retention 1.5 — — V
Voltage(2)
DC16 VPOR VDD Start Voltage — — VSS V
to Ensure Internal
Power-on Reset Signal
DC17 SVDD VDD Rise Rate 0.05 — — V/ms 0-3.3V in 0.1s
to Ensure Internal 0-2.5V in 60 ms
Power-on Reset Signal
DC18 VBOR Brown-out Reset 1.8 2.1 2.2 V
Voltage
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: This is the limit to which VDD can be lowered without losing RAM data.

TABLE 27-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Parameter No. Typical(1) Max Units Conditions

Operating Current (IDD): PMD Bits are Set(2)
DC20 0.650 0.850 mA -40°C
DC20a 0.650 0.850 mA +25°C
2.0V(3)
DC20b 0.650 0.850 mA +85°C
DC20c 0.650 0.850 mA +125°C
1 MIPS
DC20d 1.2 1.6 mA -40°C
DC20e 1.2 1.6 mA +25°C
3.3V(4)
DC20f 1.2 1.6 mA +85°C
DC20g 1.2 1.6 mA +125°C
DC23 2.6 3.4 mA -40°C
DC23a 2.6 3.4 mA +25°C
2.0V(3)
DC23b 2.6 3.4 mA +85°C
DC23c 2.6 3.4 mA +125°C
4 MIPS
DC23d 4.1 5.4 mA -40°C
DC23e 4.1 5.4 mA +25°C
3.3V(4)
DC23f 4.1 5.4 mA +85°C
DC23g 4.1 5.4 mA +125°C
DC24 13.5 17.6 mA -40°C
DC24a 13.5 17.6 mA +25°C
2.5V(3)
DC24b 13.5 17.6 mA +85°C
DC24c 13.5 17.6 mA +125°C
16 MIPS
DC24d 15 20 mA -40°C
DC24e 15 20 mA +25°C
3.3V(4)
DC24f 15 20 mA +85°C
DC24g 15 20 mA +125°C
DC31 13 17 A -40°C
DC31a 13 17 A +25°C
2.0V(3)
DC31b 20 26 A +85°C
DC31c 40 50 A +125°C
LPRC (31 kHz)
DC31d 54 70 A -40°C
DC31e 54 70 A +25°C
3.3V(4)
DC31f 95 124 A +85°C
DC31g 120 260 A +125°C
Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the
current consumption. The test conditions for all IDD measurements are as follows: OSCI driven with external square
wave from rail-to-rail. All I/O pins are configured as inputs and pulled to VDD.
MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No
peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set.
3: On-chip voltage regulator is disabled (DISVREG tied to VDD).
4: On-chip voltage regulator is enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect
(BOD) are enabled.

TABLE 27-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Parameter
Typical(1) Max Units Conditions
No.
Idle Current (IIDLE): Core Off, Clock On Base Current, PMD Bits are Set(2)
DC40 150 200 A -40°C
DC40a 150 200 A +25°C
2.0V(3)
DC40b 150 200 A +85°C
DC40c 165 220 A +125°C
1 MIPS
DC40d 250 325 A -40°C
DC40e 250 325 A +25°C
3.3V(4)
DC40f 250 325 A +85°C
DC40g 275 360 A +125°C
DC43 0.55 0.72 mA -40°C
DC43a 0.55 0.72 mA +25°C
2.0V(3)
DC43b 0.55 0.72 mA +85°C
DC43c 0.60 0.8 mA +125°C
4 MIPS
DC43d 0.82 1.1 mA -40°C
DC43e 0.82 1.1 mA +25°C
3.3V(4)
DC43f 0.82 1.1 mA +85°C
DC43g 0.91 1.2 mA +125°C
DC47 3 4 mA -40°C
DC47a 3 4 mA +25°C
2.5V(3)
DC47b 3 4 mA +85°C
DC47c 3.3 4.4 mA +125°C
16 MIPS
DC47d 3.5 4.6 mA -40°C
DC47e 3.5 4.6 mA +25°C
3.3V(4)
DC47f 3.5 4.6 mA +85°C
DC47g 3.9 5.1 mA +125°C
DC50 0.85 1.1 mA -40°C
DC50a 0.85 1.1 mA +25°C
2.0V(3)
DC50b 0.85 1.1 mA +85°C
DC50c 0.94 1.2 mA +125°C
FRC (4 MIPS)
DC50d 1.2 1.6 mA -40°C
DC50e 1.2 1.6 mA +25°C
3.3V(4)
DC50f 1.2 1.6 mA +85°C
DC50g 1.3 1.8 mA +125°C
are not tested.
2: The test conditions for all IIDLE measurements are as follows: OSCI driven with external square wave from
rail-to-rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled.
CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating and all
of the Peripheral Module Disable (PMD) bits are set.
(BOD) are enabled.

TABLE 27-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED)
Parameter
No.
Idle Current (IIDLE): Core Off, Clock On Base Current, PMD Bits are Set(2)
DC51 4 6 A -40°C
DC51a 4 6 A +25°C
2.0V(3)
DC51b 8 16 A +85°C
DC51c 20 50 A +125°C
LPRC (31 kHz)
DC51d 42 55 A -40°C
DC51e 42 55 A +25°C
3.3V(4)
DC51f 70 91 A +85°C
DC51g 100 180 A +125°C
are not tested.
2: The test conditions for all IIDLE measurements are as follows: OSCI driven with external square wave from
rail-to-rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled.
CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating and all
of the Peripheral Module Disable (PMD) bits are set.
(BOD) are enabled.

TABLE 27-6: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Parameter
No.
Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2)
DC60 0.1 1 A -40°C
DC60a 0.15 1 A +25°C
DC60m 2.2 7.4 A +60°C 2.0V(3)
DC60b 3.7 12 A +85°C
DC60j 15 50 A +125°C
DC60c 0.2 1 A -40°C
DC60d 0.25 1 A +25°C
DC60n 2.6 15 A +60°C 2.5V(3) Base Power-Down Current(5)
DC60e 4.2 25 A +85°C
DC60k 16 100 A +125°C
DC60f 3.3 9 A -40°C
DC60g 3.5 10 A +25°C
DC60o 6.7 22 A +60°C 3.3V(4)
DC60h 9 30 A +85°C
DC60l 36 120 A +125°C
DC61 1.75 3 A -40°C
DC61a 1.75 3 A +25°C
DC61m 1.75 3 A +60°C 2.0V(3)
DC61b 1.75 3 A +85°C
DC61j 3.5 6 A +125°C
DC61c 2.4 4 A -40°C
DC61d 2.4 4 A +25°C
DC61n 2.4 4 A +60°C 2.5V(3) Watchdog Timer Current: IWDT(5)
DC61e 2.4 4 A +85°C
DC61k 4.8 8 A +125°C
DC61f 2.8 5 A -40°C
DC61g 2.8 5 A +25°C
DC61o 2.8 5 A +60°C 3.3V(4)
DC61h 2.8 5 A +85°C
DC61l 5.6 10 A +125°C
Note 1: Data in the Typical column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and
pulled high. WDT, etc., are all switched off.
4: On-chip voltage regulator is enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out
Detect (BOD) are enabled.
5: The  current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.

TABLE 27-6: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED)
Parameter
No.
Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2)
DC62 8 16 A -40°C
DC62a 12 16 A +25°C
DC62m 12 16 A +60°C 2.0V(3)
DC62b 12 16 A +85°C
DC62j 18 23 A +125°C
DC62c 9 16 A -40°C
DC62d 12 16 A +25°C
RTCC + Timer1 w/32 kHz Crystal:
DC62n 12 16 A +60°C 2.5V(3)
RTCC, ITI32(5)
DC62e 12.5 16 A +85°C
DC62k 20 25 A +125°C
DC62f 10.3 18 A -40°C
DC62g 13.4 18 A +25°C
DC62o 14.0 18 A +60°C 3.3V(4)
DC62h 14.2 18 A +85°C
DC62l 23 28 A +125°C
DC63 2 — A -40°C
DC63a 2 — A +25°C 2.0V(3)
DC63b 6 — A +85°C
DC63c 2 — A -40°C RTCC + Timer1 w/Low-Power
32 kHz Crystal
DC63d 2 — A +25°C 2.5V (3)
(SOCSEL<1:0> = 01): RTCC,
DC63e 7 — A +85°C ITI32(5)
DC63f 2 — A -40°C
DC63g 3 — A +25°C 3.3V(4)
DC63h 7 — A +85°C
Note 1: Data in the Typical column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and
pulled high. WDT, etc., are all switched off.
4: On-chip voltage regulator is enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out
Detect (BOD) are enabled.
5: The  current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.

TABLE 27-7: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Param
Sym Characteristic Min Typ(1) Max Units Conditions
No.
VIL Input Low Voltage(4)
DI10 I/O Pins VSS — 0.2 VDD V
DI11 PMP Pins VSS — 0.15 VDD V PMPTTL = 1
DI15 MCLR VSS — 0.2 VDD V
DI16 OSCI (XT mode) VSS — 0.2 VDD V
DI17 OSCI (HS mode) VSS — 0.2 VDD V
DI18 I/O Pins with I2C™ Buffer VSS — 0.3 VDD V SMBus disabled
DI19 I/O Pins with SMBus Buffer VSS — 0.8 V SMBus enabled
VIH Input High Voltage(4)
DI20 I/O Pins:
with Analog Functions 0.8 VDD — VDD V
Digital Only 0.8 VDD — 5.5 V
DI21 PMP Pins:
with Analog Functions 0.25 VDD + 0.8 — VDD V PMPTTL = 1
Digital Only 0.25 VDD + 0.8 — 5.5 V
DI25 MCLR 0.8 VDD — VDD V
DI26 OSCI (XT mode) 0.7 VDD — VDD V
DI27 OSCI (HS mode) 0.7 VDD — VDD V
DI28 I/O Pins with I2C Buffer:
with Analog Functions 0.7 VDD — VDD V
Digital Only 0.7 VDD — 5.5 V
DI29 I/O Pins with SMBus Buffer:
with Analog Functions
Digital Only 2.1 — VDD V
2.1 — 5.5 v 2.5V  VPIN  VDD
DI30 ICNPU CNxx Pull-up Current 50 250 400 A VDD = 3.3V, VPIN = VSS
and are not tested.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Refer to Table 1-2 for I/O pin buffer types.
5: Parameter is characterized but not tested.
6: Non-5V tolerant pins, VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not
tested.
7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources greater
than 5.5V.
8: Injection currents > | 0 | can affect the performance of all analog peripherals (e.g., A/D, comparators,
internal band gap reference, etc.)
9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro-
vided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.

TABLE 27-7: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
Param
No.
DI31 IPU Maximum Load Current — — 30 µA VDD = 2.0V
for Digital High Detection
— — 100 µA VDD = 3.3V
with Internal Pull-up
IIL Input Leakage Current(2,3)
DI50 I/O Ports — — +1 A VSS  VPIN  VDD,
Pin at high-impedance
DI51 Analog Input Pins — — +1 A VSS  VPIN  VDD,
Pin at high-impedance
DI55 MCLR — — +1 A VSS VPIN VDD
DI56 OSCI — — +1 A VSS VPIN VDD,
XT and HS modes
IICL Input Low Injection
Current
DI60a 0 — -5(5,8) mA All pins except VDD, VSS,
AVDD, AVSS, MCLR, VCAP,
RB11, SOSCI, SOSCO,
D+, D-, VUSB, and VBUS
IICH Input High Injection
Current
DI60b 0 — +5(6,7,8) mA All pins except VDD, VSS,
AVDD, AVSS, MCLR, VCAP,
RB11, SOSCI, SOSCO,
D+, D-, VUSB, and VBUS,
and all 5V tolerant pins(7)
IICT Total Input Injection
Current
DI60c (sum of all I/O and control -20(9) — +20(9) mA Absolute instantaneous
pins) sum of all ± input injection
currents from all I/O pins
(| IICL + | IICH |)  IICT)
and are not tested.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Refer to Table 1-2 for I/O pin buffer types.
5: Parameter is characterized but not tested.
6: Non-5V tolerant pins, VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not
tested.
7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources greater
than 5.5V.
8: Injection currents > | 0 | can affect the performance of all analog peripherals (e.g., A/D, comparators,
internal band gap reference, etc.)
9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro-
vided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.

TABLE 27-8: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Param
No.
VOL Output Low Voltage
DO10 All I/O Pins — — 0.4 V IOL = 8.5 mA, VDD = 3.6V
— — 0.4 V IOL = 5.0 mA, VDD = 2.0V
DO16 All I/O Pins — — 0.4 V IOL = 8.0 mA, VDD = 3.6V, +125°C
— — 0.4 V IOL = 4.5 mA, VDD = 2.0V, +125°C
VOH Output High Voltage
DO20 All I/O Pins 3 — — V IOH = -3.0 mA, VDD = 3.6V
1.65 — — V IOH = -1.0 mA, VDD = 2.0V
DO26 All I/O Pins 3 — — V IOH = -2.5 mA, VDD = 3.6V, +125°C
1.65 — — V IOH = -0.5 mA, VDD = 2.0V, +125°C
Note 1: Data in “Typ” column is at +25°C unless otherwise stated. Parameters are for design guidance only and are not
tested.
TABLE 27-9: DC CHARACTERISTICS: PROGRAM MEMORY

Param
No.
Program Flash Memory
D130 EP Cell Endurance 10000 — — E/W -40C to +125C
D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operating voltage
D132B VPEW VDDCORE for Self-Timed 2.25 — 2.75 V
Write
D133A TIW Self-Timed Write Cycle — 3 — ms
Time
D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications are
violated
D135 IDDP Supply Current during — 7 — mA
Programming
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.

TABLE 27-10: COMPARATOR SPECIFICATIONS
Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
Symbol Characteristic Min Typ Max Units Comments
No.
D300 VIOFF Input Offset Voltage* — 10 30 mV
D301 VICM Input Common-Mode Voltage* 0 — VDD V
D302 CMRR Common-Mode Rejection 55 — — dB
Ratio*
300 TRESP Response Time*(1) — 150 400 ns
301 TMC2OV Comparator Mode Change to — — 10 s
Output Valid*
* Parameters are characterized but not tested.
Note 1: Response time is measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
TABLE 27-11: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS

Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
Symbol Characteristic Min Typ Max Units Comments
No.
VRD310 CVRES Resolution VDD/24 — VDD/32 LSb
VRD311 CVRAA Absolute Accuracy — — 1 LSb
VRD312 CVRUR Unit Resistor Value (R) — 2k — 
VR310 TSET Settling Time(1) — — 10 s
Note 1: Settling time is measured while CVRR = 1 and the CVR<3:0> bits transition from ‘0000’ to ‘1111’.
TABLE 27-12: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS

Operating Conditions: -40°C < TA < +125°C (unless otherwise stated)
Param
Symbol Characteristics Min Typ Max Units Comments
No.
VRGOUT Regulator Output Voltage — 2.5 — V
VBG Band Gap Reference Voltage — 1.2 — V
CEFC External Filter Capacitor 4.7 10 — F Series resistance < 3 Ohm
Value recommended;
< 5 Ohm required
TVREG Voltage Regulator Start-up — 10 — s POR, BOR or when
Time PMSLP = 1
— 25 — s PMSLP = 0,
WUTSEL<1:0> = 01(1)
— 190 — s PMSLP = 0,
WUTSEL<1:0> = 11(2)
TPWRT — 64 — ms DISVREG = VDD
Note 1: Available only in devices with a major silicon revision level of B or later (DEVREV register value is 3042h
or greater).
2: WUTSELx Configuration bits setting is applicable only in devices with a major silicon revision level of B or
later. This specification also applies to all devices prior to Revision Level B whenever PMSLP = 0.

27.2 AC Characteristics and Timing Parameters
The information contained in this section defines the PIC24FJ64GA004 family AC characteristics and timing
parameters.
TABLE 27-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

Operating temperature -40°C  TA  +85°C for Industrial
AC CHARACTERISTICS
Operating voltage VDD range as described in Section 27.1 “DC Characteristics”.
FIGURE 27-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for All Pins Except OSCO Load Condition 2 – for OSCO
VDD/2
Pin CL
RL
VSS
CL
Pin RL = 464
CL = 50 pF for all pins except OSCO
VSS
15 pF for OSCO output
TABLE 27-14: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS

Param
Symbol Characteristic Min Typ(1) Max Units Conditions
No.
DO50 COSC2 OSCO/CLKO Pin — — 15 pF In XT and HS modes when
external clock is used to drive
OSCI
DO56 CIO All I/O Pins and OSCO — — 50 pF EC mode
DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode
and are not tested.

FIGURE 27-4: EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
OSCI
OS20
OS30 OS30 OS31 OS31
OS25
CLKO
OS40 OS41
TABLE 27-15: EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 2.0 to 3.6V (unless otherwise stated)
AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial
Param
No.
OS10 FOSC External CLKI Frequency DC — 32 MHz EC, -40°C  TA  +85°C
(External clocks allowed 4 — 8 MHz ECPLL, -40°C  TA  +85°C
only in EC mode) DC — 24 MHz EC, -40°C  TA  +125°C
4 — 6 MHz ECPLL, -40°C  TA  +125°C
Oscillator Frequency 3 — 10 MHz XT
3 — 8 MHz XTPLL, -40°C  TA  +85°C
10 — 32 MHz HS, -40°C  TA  +85°C
31 — 33 kHz SOSC
3 — 6 MHz XTPLL, -40°C  TA  +125°C
10 — 24 MHz HS, -40°C  TA  +125°C
OS20 TOSC TOSC = 1/FOSC — — — — See Parameter OS10 for
FOSC value
OS25 TCY Instruction Cycle Time(2) 62.5 — DC ns
OS30 TosL, External Clock In (OSCI) 0.45 x TOSC — — ns EC
TosH High or Low Time
OS31 TosR, External Clock In (OSCI) — — 20 ns EC
TosF Rise or Fall Time
OS40 TckR CLKO Rise Time(3) — 6 10 ns
OS41 TckF CLKO Fall Time(3) — 6 10 ns
and are not tested.
2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type, under standard operating conditions, with
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an
external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.” cycle time
limit is “DC” (no clock) for all devices.
3: Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the
Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).

TABLE 27-16: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.0V TO 3.6V)
Param
Sym Characteristic(1) Min Typ(2) Max Units Conditions
No.
OS50 FPLLI PLL Input Frequency 3 — 8 MHz ECPLL, HSPLL, XTPLL modes,
Range -40°C  TA  +85°C
3 — 6 MHz ECPLL, HSPLL, XTPLL modes,
-40°C  TA  +125°C
OS51 FSYS PLL Output Frequency 8 — 32 MHz -40°C  TA  +85°C
Range 8 — 24 MHz -40°C  TA  +125°C
OS52 TLOCK PLL Start-up Time — — 2 ms
(Lock Time)
OS53 DCLK CLKO Stability (Jitter) -2 1 2 % Measured over 100 ms period
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
TABLE 27-17: INTERNAL RC OSCILLATOR SPECIFICATIONS

AC CHARACTERISTICS Operating temperature -40°C  TA +85°C for Industrial
Param
Sym Characteristic Min Typ Max Units Conditions
No.
TFRC FRC Start-up Time — 15 — s
TLPRC LPRC Start-up Time — 40 — s
TABLE 27-18: AC CHARACTERISTICS: INTERNAL RC ACCURACY

Param
Characteristic Min Typ Max Units Conditions
No.
F20 Internal FRC @ 8 MHz(1) -2 — 2 % +25°C
-5 — 5 % -40°C  TA +85°C 3.0V  VDD  3.6V
-7 — 7 % +125°C
F21 LPRC @ 31 kHz(2) -15 — 15 % +25°C
-15 — 15 % -40°C  TA +85°C 3.0V  VDD  3.6V
-30 — 30 % +125°C
Note 1: Frequency calibrated at +25°C and 3.3V. OSCTUN bits can be used to compensate for temperature drift.
2: Change of LPRC frequency as VDD changes.

FIGURE 27-5: CLKO AND I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
Old Value New Value
(Output)
DO31
DO32
Note: Refer to Figure 27-3 for load conditions.
TABLE 27-19: CLKO AND I/O TIMING REQUIREMENTS

Param
No.
DO31 TIOR Port Output Rise Time — 10 25 ns
DO32 TIOF Port Output Fall Time — 10 25 ns
DI35 TINP INTx Pin High or Low 20 — — ns
Time (output)
DI40 TRBP CNx High or Low Time 2 — — TCY
(input)
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.

TABLE 27-20: A/D MODULE SPECIFICATIONS
Param
Symbol Characteristic Min. Typ Max. Units Conditions
No.
Device Supply
AD01 AVDD Module VDD Supply Greater of: — Lesser of: V
VDD – 0.3 VDD + 0.3
or 2.0 or 3.6
AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.3 V
Reference Inputs
AD05 VREFH Reference Voltage High AVSS + 1.7 — AVDD V
AD06 VREFL Reference Voltage Low AVSS — AVDD – 1.7 V
AD07 VREF Absolute Reference AVSS – 0.3 — AVDD + 0.3 V
Voltage
AD08 IVREF Reference Voltage Input — — 1.25 mA Measured during conversion,
Current 3.3V, +25°C (Note 1)
AD09 ZREF Reference Input Impedance — 10k —  Measured during sampling,
3.3V, +25°C
Analog Input
AD10 VINH-VINL Full-Scale Input Span VREFL — VREFH V (Note 1)
AD11 VIN Absolute Input Voltage AVSS – 0.3 — AVDD + 0.3 V
AD12 VINL Absolute VINL Input Voltage AVSS – 0.3 AVDD/2 V
AD13 — Leakage Current — ±1 ±610 nA VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V,
Source Impedance = 2.5 k
AD17 RIN Recommended — — 2.5K  10-bit
Impedance of Analog
Voltage Source
A/D Accuracy
AD20b Nr Resolution — 10 — bits
AD21b INL Integral Nonlinearity — ±1 <±2 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD22b DNL Differential Nonlinearity — ±1 <±1.25 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD23b GERR Gain Error — ±1 ±3 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD24b EOFF Offset Error — ±1 ±2 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD25b — Monotonicity(2) — — — — Guaranteed
Note 1: Measurements are taken with external VREF+ and VREF- used as the A/D voltage reference.
2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

TABLE 27-21: A/D CONVERSION TIMING REQUIREMENTS(1)
Param
Symbol Characteristic Min. Typ Max. Units Conditions
No.
Clock Parameters
AD50 TAD A/D Clock Period 75 — — ns TCY = 75 ns, AD1CON3 in
default state
AD51 tRC A/D Internal RC Oscillator — 250 — ns
Period
Conversion Rate
AD55 tCONV Conversion Time — 12 — TAD
AD56 FCNV Throughput Rate — — 500 ksps AVDD  2.7V
AD57 tSAMP Sample Time — 1 — TAD
Clock Parameters
AD61 tPSS Sample Start Delay from 2 — 3 TAD
Setting Sample bit (SAMP)
Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.

NOTES:

28.0 PACKAGING INFORMATION
28.1 Package Marking Information
28-Lead SPDIP (.300”) Example
XXXXXXXXXXXXXXXXX PIC24FJ16GA002
XXXXXXXXXXXXXXXXX -I/SP e3
YYWWNNN 1310017
28-Lead SSOP (5.30 mm) Example
XXXXXXXXXXXX 24FJ16GA002
XXXXXXXXXXXX /SS e3
YYWWNNN 1310017
28-Lead SOIC (7.50 mm) Example
XXXXXXXXXXXXXXXXXXXX PIC24FJ16GA002/SO e3
XXXXXXXXXXXXXXXXXXXX 1310017
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

28-Lead QFN (6X6 mm) Example
XXXXXXXX 24FJ48GA
XXXXXXXX 002/ML e3
YYWWNNN 1310017
44-Lead QFN (8x8x0.9 mm) Example
XXXXXXXXXX 24FJ32GA
XXXXXXXXXX 004-I/ML e3
XXXXXXXXXX 1310017
YYWWNNN
44-Lead TQFP (10x10x1 mm) Example
XXXXXXXXXX 24FJ32GA
XXXXXXXXXX 004-I/PT e3
XXXXXXXXXX 1310017
YYWWNNN

28.2 Package Details
The following sections give the technical details of the packages.
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NOTES:

APPENDIX A: REVISION HISTORY
Revision A (March 2007) • Updates Section 2.0 “Guidelines for Getting

Started with 16-Bit Microcontrollers” with the
Original data sheet for the PIC24FJ64GA004 family of most current information on VCAP selection.
devices.
• Replaces Table 6-3 (Reset Delay Times) with an
updated version.
Revision B (March 2007) • Updates Section 7.0 ”Interrupt Controller” by
Changes to Table 26-8; packaging diagrams updated. adding a description of the INTTREG register
(Register 7-31).
Revision C (January 2008) • Updates Section 8.0 ”Oscillator Configuration”
by correcting the external oscillator inputs in
• Update of electrical specifications to include DC Figure 8-1 and a new unlock code sequence in
characteristics for Extended Temperature Example 8-1.
devices. • Replaces Example 10-2 with a new code example.
• Update for A/D converter chapter to include • Updates Section 19.0 ”Real-Time Clock and
information on internal band gap voltage Calendar (RTCC)” to add introductory text and
reference. amend input sources in Figure 19-1.
• Added “Appendix B: “Additional Guidance for • Updates Section 20.0 ”Programmable Cyclic
PIC24FJ64GA004 Family Applications”. Redundancy Check (CRC) Generator” with a
• General revisions to incorporate corrections more current version (no technical changes to the
included in document errata to date (DS80333). module or its operation).
• Updates Section 26.0 ”Instruction Set Summary”:
Revision D (January 2010) - Updates syntax of ASR, DAW, LSR, MOV
• Update of electrical specifications to include 60°C and SL instructions to conform with the
specifications for power-down current to DC Programmer’s Reference Manual
characteristics. - Adds previously omitted instruction, FBCL
• Removes references to JTAG programming • Adds to Section 27.0 ”Electrical Characteristics”:
throughout the document. - New Specification DC18 (VBOR) to Table 27-3
• Other minor typographic corrections throughout. - New Specifications DI60a (IICL), DI60b (IICH)
and DI60c (IICT) to Table 27-7
Revision E (May 2013) - New Table 27-10 (Comparator Specifications)
and Table 27-11 (Comparator Voltage Refer-
• Updates all pin diagrams to indicate 5V tolerant
ence Specifications); previous Table 27-10 is
pins.
now renumbered as Table 27-12, and all
• Updates all package labeling diagrams. subsequent tables renumbered accordingly
• Changes the VREGS bit name (RCON<8>) to - New Table 27-17 (Internal RC Oscillator
PMSLP in all occurrences throughout the data Specifications)
sheet; also updates the description of the bit’s
- New specifications, AD08 (IVREF), AD09
functionality in Register 6-1. (The actual operation
(ZREF) and AD13 (Leakage Current), to
of the bit remains unchanged.)
Table 27-20
• Adds additional explanatory text to the following
- Combines previous Table 27-15 (AC Charac-
sections:
teristics: Internal RC Accuracy) and
- Section 9.2.1 ”Sleep Mode” Table 27-16 (Internal RC Accuracy) into a
- Section 10.4.2.1 ”Peripheral Pin Select new Table 27-18 (AC Characteristics: Internal
Function Priority” RC Accuracy)
- Section 24.2.3 ”On-Chip Regulator and • Other minor typographic corrections throughout.
POR”

APPENDIX B: ADDITIONAL FIGURE B-1: POWER REDUCTION
GUIDANCE FOR EXAMPLE FOR CONSTANT
VOLTAGE SUPPLIES
PIC24FJ64GA004
FAMILY
PIC24FJ64GA
APPLICATIONS
VDD
B.1 Additional Methods for Power DISVREG
Reduction 3.0V D1
2.3V
Coin Cell VDDCORE
Devices in the PIC24FJ64GA004 family include a num-
ber of core features to significantly reduce the applica- VSS
tion’s power requirements. For truly power-sensitive
applications, it is possible to further reduce the
application’s power demands by taking advantage of
the device’s regulator architecture. These methods A similar method can be used for non-regulated
help decrease power in two ways: by disabling the sources (Figure B-2). In this case, it can be beneficial
internal voltage regulator to eliminate its power con- to use a low quiescent current, external voltage regula-
sumption, and by reducing the voltage on VDDCORE to tor. Devices, such as the MCP1700, consume only
lower the device’s dynamic current requirements. 1 A to regulate to 2V or 2.5V, which is lower than the
Using these methods, it is possible to reduce Sleep current required to power the internal voltage regulator.
currents (IPD) from 3.5 A to 250 nA (typical values,
refer to Parameters DC60d and DC60g in Table 27-6). FIGURE B-2: POWER REDUCTION
For dynamic power consumption, the reduction in
EXAMPLE FOR
VDDCORE from 2.5V provided by the regulator, to 2.0V,
NON-REGULATED SUPPLIES
can provide a power reduction of about 30%.
When using a regulated power source or a battery with
a constant output voltage, it is possible to decrease
PIC24FJ64GA
power consumption by disabling the regulator. In this
case (Figure B-1), a simple diode can be used to VDD
reduce the voltage from 3V or greater to the 2V-2.5V
required for VDDCORE. This method is only advised on DISVREG
3.3V
power supplies, such as Lithium Coin cells, which 2.0V
VDDCORE
‘AA’ MCP1700
maintain a constant voltage over the life of the battery.
VSS

INDEX
A Recommended Minimum Connections....................... 17
Reset System ............................................................. 53
A/D Converter
Analog Input Model ................................................... 200 Shared I/O Port Structure ......................................... 105
Transfer Function...................................................... 201 Simplified UARTx Module......................................... 159
SPIx Master/Frame Master Connection ................... 149
AC Characteristics
A/D Conversion Requirements ................................. 249 SPIx Master/Frame Slave Connection ..................... 149
A/D Specifications..................................................... 248 SPIx Master/Slave Connection
(Enhanced Buffer Mode) .................................. 148
CLKO and I/O Requirements .................................... 247
External Clock Requirements ................................... 245 SPIx Master/Slave Connection
Internal RC Accuracy ................................................ 246 (Standard Mode)............................................... 148
SPIx Module (Enhanced Mode)................................ 143
Internal RC Oscillator Specifications......................... 246
PLL Clock Specifications .......................................... 246 SPIx Module (Standard Mode) ................................. 142
Temperature and Voltage Specifications .................. 244 SPIx Slave/Frame Master Connection ..................... 149
SPIx Slave/Frame Slave Connection ....................... 149
Additional Guidance for Family Applications..................... 268
Assembler Suggested Placement of Oscillator Circuit ................. 21
MPASM Assembler................................................... 220 System Clock.............................................................. 95
Timer2 and Timer4 (16-Bit Synchronous Mode) ...... 129
B Timer2/3 and Timer4/5 (32-Bit Mode) ...................... 128
Block Diagrams Timer3 and Timer5 (16-Bit Synchronous Mode) ...... 129
10-Bit High-Speed A/D Converter............................. 194 Watchdog Timer (WDT)............................................ 217
16-Bit Timer1 ............................................................ 125 C
Accessing Program Memory with
C Compilers
Table Instructions ............................................... 45
MPLAB C18.............................................................. 220
Addressable Parallel Slave Port Example ................ 174
Code Examples
Addressing for Table Registers................................... 47
Basic Clock Switching Example ............................... 101
CALL Stack Frame...................................................... 43
Configuring UART1 Input and Output
Comparator I/O Operating Modes............................. 203
Functions (PPS) ............................................... 110
Comparator Voltage Reference ................................ 207
Erasing a Program Memory Block.............................. 50
CPU Programmer’s Model .......................................... 25
I/O Port Read/Write .................................................. 106
CRC Module ............................................................. 189
Initiating a Programming Sequence ........................... 51
CRC Shift Engine...................................................... 190
Loading the Write Buffers ........................................... 51
Data Access from Program Space
Setting the RTCWREN Bit ........................................ 178
Address Generation ............................................ 44
Single-Word Flash Programming ............................... 52
I2C Module ................................................................ 152
Input Capture x ......................................................... 133 Code Protection ................................................................ 218
Comparator Voltage Reference
LCD Control Example, Byte Mode ............................ 176
Legacy Parallel Slave Port Example......................... 174 Configuring ............................................................... 207
Load Conditions for Timing Specifications................ 244 Configuration Bits ............................................................. 209
Core Features....................................................................... 7
MCLR Pin Connections............................................... 18
On-Chip Regulator Connections ............................... 215 CPU
Output Compare x..................................................... 138 Arithmetic Logic Unit (ALU) ........................................ 27
Control Registers........................................................ 26
Parallel EEPROM (Up to 11-Bit Address,
16-Bit Data)....................................................... 176 Core Registers............................................................ 25
Parallel EEPROM (Up to 11-Bit Address, Programmer’s Model .................................................. 23
CRC
8-Bit Data)......................................................... 176
Parallel Master Port (PMP) Module Overview .......... 167 Operation in Power Save Modes.............................. 190
PIC24F CPU Core ...................................................... 24 Setup Example ......................................................... 189
User Interface ........................................................... 190
PIC24FJ64GA004 Family (General) ........................... 10
PMP 8-Bit Multiplexed Addressing and Customer Change Notification Service............................. 273
Data Application................................................ 176 Customer Notification Service .......................................... 273
Customer Support............................................................. 273
PMP Master Mode, Demultiplexed Addressing ........ 174
PMP Master Mode, Fully D
Multiplexed Addressing..................................... 175
Data Memory
PMP Master Mode, Partially
Address Space ........................................................... 31
Multiplexed Addressing..................................... 175
Memory Map............................................................... 31
PMP Multiplexed Addressing Application ................. 175
Near Data Space ........................................................ 32
PMP Partially Multiplexed
Organization ............................................................... 32
Addressing Application ..................................... 175
SFR Space ................................................................. 32
PSV Operation ............................................................ 46
Software Stack ........................................................... 43
Real-Time Clock and Calendar (RTCC) ................... 177

DC Characteristics I2C
Comparator Specifications ........................................ 243 Baud Rate Setting When Operating as
Comparator Voltage Reference Bus Master ....................................................... 153
Specifications.................................................... 243 Clock Rates .............................................................. 153
I/O Pin Input Specifications ....................................... 240 Master in a Single Master Environment
I/O Pin Output Specifications .................................... 242 Communication................................................. 151
Idle Current (IIDLE) .................................................... 236 Peripheral Remapping Options................................. 151
Internal Voltage Regulator Specifications ................. 243 Reserved Addresses ................................................ 153
Operating Current (IDD)............................................. 235 Slave Address Masking ............................................ 153
Power-Down Current (IPD) ........................................ 238 ICSP Operations
Program Memory Specifications ............................... 242 Analog and Digital Pins Configuration ........................ 22
Temperature and Voltage Specifications .................. 234 ICSP Pins ........................................................................... 20
Details on Individual Family Members .................................. 8 Idle Mode .......................................................................... 104
Development Support ....................................................... 219 In-Circuit Debugger........................................................... 218
Device Features (Summary) ................................................. 9 In-Circuit Serial Programming (ICSP)............................... 218
DISVREG Pin.................................................................... 215 Instruction Set
Doze Mode........................................................................ 104 Opcode Symbol Descriptions ................................... 224
Overview................................................................... 225
E Summary .................................................................. 223
Electrical Characteristics Inter-Integrated Circuit. See I2C.
Absolute Maximum Ratings ...................................... 231 Internet Address ............................................................... 273
Capacitive Loading Requirements on Interrupts
Output Pins ....................................................... 244 Alternate Interrupt Vector Table (AIVT) ...................... 59
Thermal Operating Conditions .................................. 233 and Reset Sequence .................................................. 59
Thermal Packaging ................................................... 233 Implemented Vectors.................................................. 61
V/F Graphs (Extended Temperature) ....................... 232 Interrupt Vector Table (IVT) ........................................ 59
V/F Graphs (Industrial Temperature) ........................ 232 Registers .................................................................... 62
Equations Setup and Service Procedures ................................... 94
A/D Conversion Clock Period ................................... 200 Trap Vectors ............................................................... 60
Baud Rate Reload Calculation .................................. 153 Vector Table ............................................................... 60
Calculating the PWM Period ..................................... 136
Calculation for Maximum PWM Resolution............... 136 J
CRC Polynomial........................................................ 189 JTAG Interface.................................................................. 218
Device and SPIx Clock Speed Relationship ............. 150
UARTx Baud Rate with BRGH = 0............................ 160 M
UARTx Baud Rate with BRGH = 1............................ 160 Master Clear Pin (MCLR) ................................................... 18
Errata .................................................................................... 6 Microchip Internet Web Site.............................................. 273
External Oscillator Pins ....................................................... 21 MPLAB ASM30 Assembler, Linker, Librarian ................... 220
MPLAB Integrated Development
F Environment Software .............................................. 219
Flash Configuration Words.......................................... 30, 209 MPLAB PM3 Device Programmer .................................... 221
Flash Program Memory MPLAB REAL ICE In-Circuit Emulator System ................ 221
and Table Instructions................................................. 47 MPLINK Object Linker/MPLIB Object Librarian ................ 220
Enhanced ICSP Operation.......................................... 48
Operations .................................................................. 48 N
Programming Algorithm .............................................. 50 Near Data Space ................................................................ 32
RTSP Operation.......................................................... 48
Single-Word Programming.......................................... 52
O
Oscillator Configuration
G Clock Switching ........................................................ 100
Getting Started Guidelines .................................................. 17 Sequence ......................................................... 101
CPU Clocking Scheme ............................................... 96
I Initial Configuration on POR ....................................... 96
I/O Ports Oscillator Modes ......................................................... 96
Analog Port Pins Configuration ................................. 106 Output Compare
Input Change Notification.......................................... 106 Continuous Output Pulse Generation Setup............. 135
Open-Drain Configuration ......................................... 106 PWM Mode ............................................................... 136
Parallel (PIO) ............................................................ 105 Period and Duty Cycle Calculation ................... 137
Peripheral Pin Select ................................................ 107 Single Output Pulse Generation Setup..................... 135
Pull-ups ..................................................................... 106

P Registers
Packaging AD1CHS (A/D Input Select)...................................... 198
Details ....................................................................... 253 AD1CON1 (A/D Control 1)........................................ 195
AD1CON2 (A/D Control 2)........................................ 196
Marking ..................................................................... 251
Parallel Master Port. See PMP. AD1CON3 (A/D Control 3)........................................ 197
Peripheral Enable Bits ...................................................... 104 AD1CSSL (A/D Input Scan Select)........................... 199
AD1PCFG (A/D Port Configuration) ......................... 199
Peripheral Module Disable (PMD) Bits ............................. 104
Peripheral Pin Select (PPS) .............................................. 107 ALCFGRPT (Alarm Configuration) ........................... 181
Available Peripherals and Pins ................................. 107 ALMINSEC (Alarm Minutes and
Seconds Value) ................................................ 185
Configuration Control ................................................ 109
Considerations for Use ............................................. 110 ALMTHDY (Alarm Month and Day Value) ................ 184
Input Mapping ........................................................... 107 ALWDHR (Alarm Weekday and Hours Value) ......... 185
CLKDIV (Clock Divider) .............................................. 99
Mapping Exceptions.................................................. 109
Output Mapping ........................................................ 109 CMCON (Comparator Control) ................................. 204
Peripheral Priority ..................................................... 107 CORCON (CPU Control) ...................................... 27, 63
CRCCON (CRC Control) .......................................... 191
Registers........................................................... 111–124
Pinout Descriptions ....................................................... 11–16 CRCXOR (CRC XOR Polynomial) ........................... 192
PMSLP Bit CVRCON (Comparator Voltage
Reference Control) ........................................... 208
and Wake-up Time.................................................... 103
Power Supply Pins .............................................................. 18 CW1 (Flash Configuration Word 1) .......................... 210
Power-Saving Features .................................................... 103 CW2 (Flash Configuration Word 2) .......................... 212
DEVID (Device ID).................................................... 213
Clock Frequency and Switching................................ 103
Instruction-Based Modes .......................................... 103 DEVREV (Device Revision)...................................... 214
Selective Peripheral Power Control .......................... 104 I2CxCON (I2Cx Control)........................................... 154
I2CxMSK (I2Cx Slave Mode Address Mask)............ 157
Power-up Requirements ................................................... 216
Product Identification System ........................................... 275 I2CxSTAT (I2Cx Status) ........................................... 156
Program Memory ICxCON (Input Capture x Control)............................ 134
IEC0 (Interrupt Enable Control 0) ............................... 72
Access Using Table Instructions................................. 45
Address Construction.................................................. 43 IEC1 (Interrupt Enable Control 1) ............................... 74
Address Space............................................................ 29 IEC2 (Interrupt Enable Control 2) ............................... 75
IEC3 (Interrupt Enable Control 3) ............................... 76
Flash Configuration Words ......................................... 30
Memory Map ............................................................... 29 IEC4 (Interrupt Enable Control 4) ............................... 77
Organization................................................................ 30 IFS0 (Interrupt Flag Status 0) ..................................... 66
IFS1 (Interrupt Flag Status 1) ..................................... 68
Program Space Visibility (PSV) .................................. 46
Program Verification ......................................................... 218 IFS2 (Interrupt Flag Status 2) ..................................... 69
Pulse-Width Modulation. See PWM. IFS3 (Interrupt Flag Status 3) ..................................... 70
IFS4 (Interrupt Flag Status 4) ..................................... 71
R INTCON1 (Interrupt Control 1) ................................... 64
Reader Response ............................................................. 274 INTCON2 (Interrupt Control 2) ................................... 65
Register Maps INTTREG (Interrupt Control and Status) .................... 93
A/D Converter (ADC) .................................................. 39 IPC0 (Interrupt Priority Control 0) ............................... 78
Clock Control .............................................................. 42 IPC1 (Interrupt Priority Control 1) ............................... 79
CPU Core.................................................................... 33 IPC10 (Interrupt Priority Control 10) ........................... 88
CRC ............................................................................ 40 IPC11 (Interrupt Priority Control 11) ........................... 88
Dual Comparator......................................................... 40 IPC12 (Interrupt Priority Control 12) ........................... 89
I2C............................................................................... 36 IPC15 (Interrupt Priority Control 15) ........................... 90
ICN.............................................................................. 33 IPC16 (Interrupt Priority Control 16) ........................... 91
Input Capture .............................................................. 35 IPC18 (Interrupt Priority Control 18) ........................... 92
Interrupt Controller ...................................................... 34 IPC2 (Interrupt Priority Control 2) ............................... 80
NVM ............................................................................ 42 IPC3 (Interrupt Priority Control 3) ............................... 81
Output Compare ......................................................... 36 IPC4 (Interrupt Priority Control 4) ............................... 82
Pad Configuration ....................................................... 38 IPC5 (Interrupt Priority Control 5) ............................... 83
Parallel Master/Slave Port .......................................... 40 IPC6 (Interrupt Priority Control 6) ............................... 84
Peripheral Pin Select (PPS)........................................ 41 IPC7 (Interrupt Priority Control 7) ............................... 85
PMD ............................................................................ 42 IPC8 (Interrupt Priority Control 8) ............................... 86
PORTA........................................................................ 38 IPC9 (Interrupt Priority Control 9) ............................... 87
PORTB........................................................................ 38 MINSEC (RTCC Minutes and Seconds Value) ........ 183
PORTC ....................................................................... 38 MTHDY (RTCC Month and Day Value).................... 182
Real-Time Clock and Calendar (RTCC) ..................... 40 NVMCON (Flash Memory Control)............................. 49
SPI .............................................................................. 37 OCxCON (Output Compare x Control) ..................... 139
Timers ......................................................................... 35 OSCCON (Oscillator Control)..................................... 97
UART .......................................................................... 37 OSCTUN (FRC Oscillator Tune) .............................. 100

PADCFG1 (Pad Configuration Control) ............ 173, 180 Revision History................................................................ 267
PMADDR (Parallel Port Address) ............................. 171 RTCC
PMAEN (Parallel Port Enable) .................................. 171 Alarm Configuration .................................................. 186
PMCON (Parallel Port Control) ................................. 168 Alarm Mask Settings................................................. 187
PMMODE (Parallel Port Mode) ................................. 170 Calibration ................................................................ 186
PMSTAT (Parallel Port Status) ................................. 172 Register Mapping...................................................... 178
RCFGCAL (RTCC Calibration Write Lock................................................................. 178
and Configuration) ............................................ 179
RCON (Reset Control) ................................................ 54 S
RPINR0 (Peripheral Pin Select Input 0) .................... 111 Serial Peripheral Interface. See SPI.
RPINR1 (Peripheral Pin Select Input 1) .................... 111 SFR Space ......................................................................... 32
RPINR11 (Peripheral Pin Select Input 11) ................ 114 Sleep Mode....................................................................... 103
RPINR18 (Peripheral Pin Select Input 18) ................ 115 Software Simulator (MPLAB SIM) .................................... 221
RPINR19 (Peripheral Pin Select Input 19) ................ 115 Software Stack.................................................................... 43
RPINR20 (Peripheral Pin Select Input 20) ................ 116 Special Features................................................................... 8
RPINR21 (Peripheral Pin Select Input 21) ................ 116 SPI
RPINR22 (Peripheral Pin Select Input 22) ................ 117 Enhanced Buffer Master Mode Setup....................... 143
RPINR23 (Peripheral Pin Select Input 23) ................ 117 Enhanced Buffer Slave Mode Setup......................... 143
RPINR3 (Peripheral Pin Select Input 3) .................... 112 Standard Master Mode Setup................................... 141
RPINR4 (Peripheral Pin Select Input 4) .................... 112 Standard Slave Mode Setup..................................... 141
RPINR7 (Peripheral Pin Select Input 7) .................... 113
RPINR8 (Peripheral Pin Select Input 8) .................... 113
T
RPINR9 (Peripheral Pin Select Input 9) .................... 114 Timer1............................................................................... 125
RPOR0 (Peripheral Pin Select Output 0) .................. 118 Timer2/3 and Timer4/5 ..................................................... 127
RPOR1 (Peripheral Pin Select Output 1) .................. 118 Timing Diagrams
RPOR10 (Peripheral Pin Select Output 10) .............. 123 CLKO and I/O ........................................................... 247
RPOR11 (Peripheral Pin Select Output 11) .............. 123 External Clock........................................................... 245
RPOR12 (Peripheral Pin Select Output 12) .............. 124
U
RPOR2 (Peripheral Pin Select Output 2) .................. 119
RPOR3 (Peripheral Pin Select Output 3) .................. 119 UART
RPOR4 (Peripheral Pin Select Output 4) .................. 120 Baud Rate Generator (BRG) .................................... 160
RPOR5 (Peripheral Pin Select Output 5) .................. 120 Break and Sync Transmit Sequence ........................ 161
RPOR6 (Peripheral Pin Select Output 6) .................. 121 IrDA Support ............................................................. 161
RPOR7 (Peripheral Pin Select Output 7) .................. 121 Operation of UxCTS and UxRTS Control Pins ......... 161
RPOR8 (Peripheral Pin Select Output 8) .................. 122 Receiving in 8-Bit or 9-Bit Data Mode....................... 161
RPOR9 (Peripheral Pin Select Output 9) .................. 122 Transmitting in 8-Bit Data Mode ............................... 161
SPIxCON1 (SPIx Control 1) ...................................... 146 Transmitting in 9-Bit Data Mode ............................... 161
SPIxCON2 (SPIx Control 2) ...................................... 147 Universal Asynchronous Receiver Transmitter. See UART.
SPIxSTAT (SPIx Status and Control) ....................... 144 Unused I/Os........................................................................ 22
SR (ALU STATUS) ............................................... 26, 63 V
T1CON (Timer1 Control)........................................... 126
VDDCORE/VCAP Pin ........................................................... 215
TxCON (Timer2 and Timer4 Control)........................ 130
Voltage Regulator (On-Chip) ............................................ 215
TyCON (Timer3 and Timer5 Control)........................ 131
and BOR ................................................................... 215
UxMODE (UARTx Mode) .......................................... 162
and POR ................................................................... 216
UxRXREG (UARTx Receive) .................................... 166
Low-Voltage Detection (LVD) ................................... 215
UxSTA (UARTx Status and Control) ......................... 164
Standby Mode .......................................................... 216
UxTXREG (UARTx Transmit) ................................... 166
Tracking Mode .......................................................... 215
WKDYHR (RTCC Weekday and Hours Value) ......... 183
Voltage Regulator Pins ....................................................... 19
YEAR (RTCC Year Value) ........................................ 182
Resets W
Brown-out Reset (BOR) .............................................. 53
Watchdog Timer (WDT).................................................... 216
Clock Source Selection ............................................... 56
Windowed Operation ................................................ 217
Configuration Mismatch Reset (CM) ........................... 53
WWW Address ................................................................. 273
Delay Times ................................................................ 56
WWW, On-Line Support ....................................................... 6
Device Reset Times .................................................... 56
Illegal Opcode Reset (IOPUWR) ................................ 53
Master Clear Pin Reset (MCLR) ................................. 53
Power-on Reset (POR) ............................................... 53
RCON Flags Operation ............................................... 55
SFR States.................................................................. 57
Software RESET Instruction (SWR) ........................... 53
Trap Conflict Reset (TRAPR)...................................... 53
Uninitialized W Register Reset (UWR)........................ 53
Watchdog Timer Reset (WDT).................................... 53

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READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
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Device: PIC24FJ64GA004 Family Literature Number: DS39881E
Questions:
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7. How would you improve this document?

PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PIC 24 FJ 64 GA0 04 T - I / PT - XXX Examples:

a) PIC24FJ32GA002-I/ML:
Microchip Trademark General Purpose PIC24F, 32-Kbyte Program
Memory, 28-Pin, Industrial Temp.,
Architecture QFN Package.
Flash Memory Family b) PIC24FJ64GA004-E/PT:
General Purpose PIC24F, 64-Kbyte Program
Program Memory Size (KB) Memory, 44-Pin, Extended Temp.,
Product Group TQFP Package.
Pin Count
Tape and Reel Flag (if applicable)
Temperature Range
Package
Pattern
Architecture 24 = 16-bit modified Harvard without DSP
Flash Memory Family FJ = Flash program memory
Product Group GA0 = General purpose microcontrollers
Pin Count 02 = 28-pin

04 = 44-pin
Temperature Range E = -40C to +125C (Extended)

I = -40C to +85C (Industrial)
Package SP = SPDIP
SO = SOIC
SS = SSOP
ML = QFN
PT = TQFP
Pattern Three-digit QTP, SQTP, Code or Special Requirements

(blank otherwise)
ES = Engineering Sample

NOTES:

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications.
PIC32 logo, rfPIC and UNI/O are registered trademarks of
MICROCHIP MAKES NO REPRESENTATIONS OR
Microchip Technology Incorporated in the U.S.A. and other
WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control
QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip
FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, chipKIT,
devices in life support and/or safety applications is entirely at chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
hold harmless Microchip from any and all damages, claims, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
suits, or expenses resulting from such use. No licenses are Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
conveyed, implicitly or otherwise, under any Microchip MPLINK, mTouch, Omniscient Code Generation, PICC,
intellectual property rights. PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62077-201-0
QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
== ISO/TS 16949 ==
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

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PIC24FJ64GA004 FAMILY

28/44-Pin General Purpose, 16-Bit Flash Microcontrollers

High-Performance CPU Analog Features

 2010-2013 Microchip Technology Inc. DS39881E-page 1

28-Pin SPDIP, SSOP, SOIC

DS39881E-page 2  2010-2013 Microchip Technology Inc.

 2010-2013 Microchip Technology Inc. DS39881E-page 3

DS39881E-page 4  2010-2013 Microchip Technology Inc.

 2010-2013 Microchip Technology Inc. DS39881E-page 5

TO OUR VALUED CUSTOMERS

Most Current Data Sheet

Customer Notification System

DS39881E-page 6  2010-2013 Microchip Technology Inc.

 2010-2013 Microchip Technology Inc. DS39881E-page 7

DS39881E-page 8  2010-2013 Microchip Technology Inc.

Operating Frequency DC – 32 MHz

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Interrupt Data Bus

PSV & Table Data Latch

Address Latch Read AGU

VDDCORE/VCAP VDD, VSS MCLR

DS39881E-page 10  2010-2013 Microchip Technology Inc.

AN0 2 27 19 I ANA A/D Analog Inputs.

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CN0 12 9 34 I ST Interrupt-on-Change Inputs.

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OSCI 9 6 30 I ANA Main Oscillator Input Connection.

PMD2 21 18 8 I/O ST/TTL

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RA0 2 27 19 I/O ST PORTA Digital I/O.

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RP0 4 1 21 I/O ST Remappable Peripheral.

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T1CK 12 9 34 I ST Timer1 Clock.

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Getting started with the PIC24FJ64GA004 family of

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Refer to Section 24.2 “On-Chip Voltage Regulator”

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Capacitance Change (%)

capacitors very attractive in many types of applications. -10

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2.8 Unused I/Os

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PSV & Table

Address Bus EA MUX

Data Latch ROM Latch

Instruction Literal Data

DS39881E-page 24  2010-2013 Microchip Technology Inc.

FIGURE 3-2: PROGRAMMER’S MODEL

Stack Pointer Limit

Registers or bits shadowed for PUSH.S and POP.S instructions.

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R/W-0(1) R/W-0(1) R/W-0(1) R-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 15-9 Unimplemented: Read as ‘0’

DS39881E-page 26  2010-2013 Microchip Technology Inc.