PCB Design For Low-EMI DC - DC Converters

PCB Design for Low-EMI
DC/DC Converters
By Jens Hedrich, Senior Field Application Engineer at MPS
Introduction
Every switch-mode power supply presents a wide-band noise source. Integrating a DC/DC converter
from the car board net into an automotive control unit and still fulfilling the EMC requirements of
automotive OEMs is a difficult task.
Typically, noise from the DC/DC converter and other high-speed circuits radiates via connected cables
that provide an effective antenna path. To block this potential radiation path, filter circuitry is required at
each cable connection point. This filtering is only effective if no H- or E-fields from the noise source couple
into the filter components or cables.
In close-field environments, the amplitude of the fields falls by 1 over distance squared (1/d2). Therefore,
a certain minimum distance is required between the noise source, filter components, and connector.
Unfortunately, PCB size and connector positions for the cables are usually pre-defined by mechanical
constraints. Additionally, the maximum component height may be very limited in certain areas of the PCB,
and two-sided assembly may not be possible. These conditions necessitate careful component
placement and PCB layout — especially when working within highly regulated industries such as
automotive manufacturing.
Real Estate Planning
To avoid directly coupling the E- and H-fields of the DC/DC converter into connectors and cables, the
circuit must be placed as far from the PCB connection points as possible (see Figure 1).
Figure 1: Place Noise Source Max Distance from Connector and Cable
Only distance or additional shielding can reduce the field strength at the EMC filters, connector and cable
to the necessary low levels. Shielding can replace distance!
It is best to use a two-side assembled PCB with at least four layers, where the DC/DC circuit and filter
components are placed on opposite sides of the board. At least one inner layer should be solid GND to
minimize cross-coupling from the noise source into the filter circuits.
In systems where the DC/DC circuit must be placed very close to the connector, effective shielding must
be considered early in the design process. Thermally necessary heatsinks can sometimes be utilized for
shielding. Ideally, the inductor, the DC/DC IC with power MOSFETs, and its decoupling capacitors are
all located under the shield.
Article #0030 Rev. 1.0 MonolithicPower.com 1

1/20/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2023 MPS. All Rights Reserved.
ARTICLE – PCB DESIGN FOR LOW-EMI DC/DC CONVERTERS
PCB Layout Guidelines

In a step-down converter, the main field sources are:
• High di/dt loop (hot loop), formed by the two power switches and CIN, which radiates wide-band
magnetic fields
• SW node between power FETs and the inductor, with strong E-field radiation
• The inductor, which radiates E-fields and H-fields
AC-magnetic fields are shielded by solid metal areas that allow the induction of eddy currents. Due to its
high conductivity, copper is very effective. Any conductor in the path of the potential difference that returns
to a fixed potential on the PCB will effectively shield E-field radiation.
Any high di/dt loop radiates H-fields proportional to the loop area and current amplitude. Place the input
capacitor close to the two power switches with a low-impedance connection to minimize the antenna loop
area.
To further reduce the magnetic fields from this loop, place two sets of capacitors symmetrically at the
power switches. Ideally, the peak currents in both loops will be half of the original, reducing the H-field
by 6dB. The orientation of the two loops is opposite, which further reduces the radiated H-field. (1)
There should be a solid GND area in the layer under the DC/DC circuit, spaced with a distance of less
than 100µm. In this copper area, the high di/dt currents flowing through the circuit components and PCB
traces induce eddy currents. The eddy currents run opposite to the original currents on the component
side, and their magnetic fields cancel the original field. This works best if the eddy current can mirror-
image the high di/dt loop current from the component side with minimal distance.
This reduces H-field radiation from the component side of the PCB. In an ideal case (super-conduction,
zero distance, and perfect matching of both loop shapes), it would be canceled by the H-fields from the
eddy currents.
Since the GND copper area under the DC/DC circuit has impedance, the high di/dt eddy currents create
potential differences and make the area noisy. This noisy GND area must be separated from the system
GND area, especially from any GND reference for filters and connectors. In a multi-layer PCB, these are
separated by shaping the individual layers and by the impedance of the connecting vias between them.
A 3-dimensional view of the multi-layer PCB illustrates this concept (see Figure 2).
Figure 2: 3-Dimensional PCB View – Layout is Part of the Circuit

Note:
1) See Henry W. Ott, Electromagnetic Compatibility Engineering, John Wiley, 2009.

On the top layer, the input capacitor (CIN) and the two power FETs join a VIN area and a PGND area
(shown in red) that are connected to inner layers through vias. For the VIN path, the component after the
vias must be an inductive element (e.g. a 1µH to 2µH coil). The high di/dt current from the switch transition
is then forced to flow only in CIN, and not across the PCB.
The PGND area is not directly connected to any other GND on the component side, only through vias to
the PGND area under the DC/DC block (shown in blue). The goal is to keep high-frequency currents on
the component side, separating the noise from the “outside world.” At least one layer should be solid
GND for the full size of the PCB to provide a low-impedance system reference. Remember, layout is part
of the circuit.
Should Copper Be Placed Under the Inductor?
Some PCB layout tools have a pre-setting that does not allow copper under an inductor core. Views on
this topic range from no copper at all to copper directly under the coil on the component side of PCB.
Figure 3: 4-Layer PCB with No Copper Under the Coil

Figure 3 shows a sketch of the magnetic fields around the coil with no copper under the coil in any layer
of a 4-layer PCB. The strong magnetic field lines from the coil are present on the bottom side of the PCB
and close around the PCB, effectively coupling into any connected cable. Filter components on the PCB
are bypassed through the air. This makes it very difficult, if not impossible, to meet automotive OEM EMC
levels.
Figure 4 shows the PCB layout with copper directly under the coil on the component side.
Figure 4: Effects of Copper Under Coil in PCB

This provides an area for eddy currents to cancel the magnetic field already on the outside of the PCB.
Inner Layer 2 and Bottom Layer are clean. EMC filter components can be effectively placed on the bottom
side. The magnetic field of the eddy currents somewhat reduces the effective inductance of the coil
(typically less than 5%). The eddy currents also create some losses in the GND copper. Another small
disadvantage of copper directly under the inductor core is an increased parasitic capacitance from the
winding to GND. However, in most designs this effect is not dominant as the capacitance is very low.
PCB Layout Example: MPQ443x Family
The MPQ443x family are 40V synchronous buck converters with low operating quiescent current and
output currents from 1A to 3.5A, ideal for automotive and industrial applications.
On the top side of the PCB, the MPQ4430 IC (U1) has symmetric CIN sets (C1A-C1D). The GND of
these capacitors is directly connected to the IC PGND pins, which is the source of the bottom FETs. This
local GND area is very noisy. On the component side, this GND area is not directly connected to any
other GND area. The only connection is through vias to the GND area in the layer under the DC/DC
circuit. In this configuration, the high di/dt current from the power stage stays on the component side. The
highest current density is on the inner edges of the traces, between VIN and PGND, shown in the green
ellipse of the example (see Figure 5).
Figure 5: MPQ4430 PCB Top-Side Layout

VIN is connected to Layer 3 by vias. Due to the vias’ inductance, the high-frequency part of the input
current remains on the top side. CIN9 damps this VIN node at the IC, but as it is 6mm high and cathode-
connected to GND, it also blocks part of the E-field radiation from the SW node and coil.
The cut around the DC/DC block on the top side keeps all high-frequency current within this area. Without
the cut, a fraction of the hot loop currents would still flow at the corner of the PCB, making the area noisy.
The high dV/dt SW node is connected to the inductor, which is typically large and radiates E-field. For
most inductors, the E-field radiation is lower if the start-of-winding is connected to the SW node.
One trick to reduce E-field radiation from the coil is to place the output capacitors (C2A & C2B) on both
sides of the coil. This works best if the capacitors are as high as or higher than the coil. In general, a
smaller-sized, lower-profile inductor typically provides better EMC performance than a larger, higher coil.

Figure 6: Inner Layer 1 Recommended PCB Layout

Inner Layer 1 of the EMC-optimized board is GND. It should be placed 70µm under the top side (see
Figure 6). This GND area is noisy. A cutout in the GND area around the DC/DC block prevents residual
currents from flowing at the edges of the layer under the connector and filter components. The cut should
have two narrow openings exactly where VIN and VOUT are routed to the DC/DC circuit in the layer
underneath, providing a defined local return path.
Results: Conducted Emissions 30MHz to 100MHz
With fSW = 470kHz and spread spectrum frequency modulation (SSFM), the CE test result from 30MHz
to 108MHz is about 0dBµV, only a few dB above system noise (see Figure 7).
Figure 7: CE Test Results, 30MHz to 108MHz

The MPQ4431 switching at 470kHz with a 0805 2.2µH inductor and two 0805 output capacitors passed
a low-frequency RE monopole test without additional shielding or SSFM (see Figure 8).

Figure 8: Low-Frequency Monopole Test Results

Conclusion
With the view that layout, with its parasitic elements, is part of the circuit, PCB design can be optimized
for low EMI in DC/DC converters. The MPQ4431 buck converter from MPS demonstrates that careful
component placement and board layout help make it possible to meet the strict EMC limits within the
automotive industry.


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PCB Design for Low-EMI

Article #0030 Rev. 1.0 MonolithicPower.com 1

PCB Layout Guidelines

Figure 2: 3-Dimensional PCB View – Layout is Part of the Circuit

Article #0030 Rev. 1.0 MonolithicPower.com 2

Figure 3: 4-Layer PCB with No Copper Under the Coil

Figure 4: Effects of Copper Under Coil in PCB

Article #0030 Rev. 1.0 MonolithicPower.com 3

Figure 5: MPQ4430 PCB Top-Side Layout

Article #0030 Rev. 1.0 MonolithicPower.com 4

Figure 6: Inner Layer 1 Recommended PCB Layout

Figure 7: CE Test Results, 30MHz to 108MHz

Article #0030 Rev. 1.0 MonolithicPower.com 5

Figure 8: Low-Frequency Monopole Test Results

Article #0030 Rev. 1.0 MonolithicPower.com 6

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