Signal Integrity

Related terms:

Algorithms, Interconnection, Software, Power Consumption, Supply Voltage, Trans-

mission Line, Power Supply Noise

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Learn more about Signal Integrity

Sequential Machines
Marilyn Wolf, in The Physics of Computing, 2017

4.2.6 Noise and reliability in logic and interconnect

Signal integrity refers to the challenges posed by ensuring that wires carry correct,
uncorrupted values. We moved to digital circuits in large part to minimize the
effect of effects that corrupt signals in analog circuits. But digital circuits are also
susceptible to noise. As the sizes of transistors and wires scale with Moore's Law,
signal integrity becomes increasingly challenging. Fig. 4.13 outlines the sources of
noise in combinational logic [She98]:

Figure 4.13. Sources of noise in digital circuits.

•
Variations in power and ground voltages affect the operation of gates as we •
will see in the next section.
Crosstalk between wires introduces noise. We will study this problem in detail•
in Section 4.3.
Coupling of a gate's output to its input affects its delay as will be shown in
Section 4.2.8.

> Read full chapter

PCB Design
Ian Grout, in Digital Systems Design with FPGAs and CPLDs, 2008

Signal Integrity
Signal integrity affects the electrical signals as they pass through the tracks in the
PCB. Ideally, the signal should not be altered by the electrical properties of the track.
However, a real track will alter the shape of the signal and so corrupt its integrity.

If care is not taken to ensure a high level of signal integrity when designing the PCB
layout, then manufacturing problems can occur in that:

• It will cause the design to work incorrectly in some cases, but not all cases.

• The design might actually fail completely.

• The design might operate slower than expected (and required).

Signal integrity problems can be created by a number of problems, including:

• The tracks’ own parasitic resistance, capacitance, and inductance will be al-
tered.
• Cross-talk between two or more different tracks will occur because of a capac-
itive coupling between the tracks resulting from the PCB substrate insulation.
• For high-frequency signals, the characteristic impedance of the transmission
line that the track creates does not match the signal source and destination.

An example where the track resistance and capacitance can create a parasitic resis-
tor-capacitor (RC) network that is modeled as a single resistor and capacitor is shown
in Figure 3.14. Applying a digital clock signal, a square wave voltage waveform, to
the RC network causes a change in the observed waveform at the output. The output
becomes an exponential waveform with a time constant = R.C. Such an effect can
cause circuit failure.
Figure 3.14. RC time constant effect

> Read full chapter

PCB design for signal integrity

Hanqiao Zhang, ... Jeff Ou, in High Speed Digital Design, 2015

Power Integrity
Power delivery has been identified as one of the key factors that impact signal
integrity performance. It refers not only to power supply noise degrading signal
jitter performance but also throughout the interconnect as power delivery noise
coupling to signals. While high-frequency power supply noise is typically handled
at silicon and package substrate level, power delivery noise coupling to input\output
(IO) interconnect must be focused on at the PCB system levels, especially for IOs
that are located around voltage regular (VR) region. Cost reduction efforts to shrink
board size and move IO routing closer to VR increase the risks of noise coupling.

Silicon and packaging design engineers have put a significant amount of research
effort into how to link power delivery performance to signal integrity. Its coverage
ranges from analysis methodologies and designing test structures for more accurate
characterization of PDIO performance, to the best design rules to balance between
cost and performance. A lot of progress has been made in this area, especially on
analysis methodology and cost reduction designs. For example, methodology has
been changed from decoupled power integrity and signal integrity analysis to power
and IO co-simulation methodologies. Further, ideal voltage supply buffer models are
changed to power-aware IO driver models. A tremendous amount of engineering
work has also been done on how to optimize power supply design for good-enough
IO design at Intel. However, there are still many gaps that need to be filled regarding
more accurate and efficient modeling and simulation methodologies, including
the worst yet realistic loading conditions, and precise performance specifications.

Besides effective and sufficient power delivery solutions to supply power for signals,
good system-level interconnect co-designs including IO interconnects and power
delivery networks are also equally important for a reliable system. There are many
cases that demonstrate that without considering overall system-level interconnect
designs, the system will not be stable and is vulnerable for fails. Those cases may
be divided into two typical categories. One is IO signaling routed too close to
VR, resulting in a significant amount of coupled noise. The other category is an
improperly designed power delivery network that causes higher system-level noises
that couple to IOs.

Although a classic motherboard-level voltage regulator with buck converter type

topology only switches at 100's of KHz, its sharp rising and falling edge still contains
high-frequency energy. Figure 2.88 illustrates a typical spectrum of the voltage wave-
form at a VR phase node. One may observe that there is noticeably high-frequency
energy that can be coupled to signals.

Figure 2.88. Left: placement of VR, IO routing, and CPU. Right: voltage waveform at
VR phase node and its short-time FFT spectrum (STFFT).

Therefore, certain design rules between power and signaling need to be defined in
that vicinity besides signaling itself. For example, Intel Corporation's published plat-
form design guidance (PDG) typically lists general design guidance to lower the risks
of noise coupling from VR to signaling. Industry-wide, more efforts are still ongoing
to establish a reliable and efficient methodology that is capable of capturing noises
from VR with different transient behaviors. With recently developed methodologies
that allow full switch VR models to predict system-level power delivery performance,
a methodology to capture VR noises coupling to IO should be feasible.

Related to power delivery noise coupling, decoupling capacitors work with a very
different noise generation and coupling mechanism than direct VR noise coupling
to IO. It is well known that in order to effectively design a power delivery network
by using decoupling capacitors, capacitor placement is critically important to ensure
the smallest loop inductance. It is not only for a good power delivery solution but
also for a minimized noise level.

Figure 2.89 illustrates typical mistakes in layout. On the left side of the layout, the
power network is surrounded by ground vias. On the right, the power network is far
from ground vias. If there are no good ground return vias for the power network, a
big loop antenna will be set up and unexpected noises will be coupled to IOs. It is
very noticeable that with the smaller return loop, field strength could be minimized
and therefore less noise coupled to the signaling that is routed at the region, as
shown in Figure 2.89.

Figure 2.89. Left: Poor (left) and good (right) layout. Right: Corresponding field
distributions.

In summary, power delivery directly impacts signal integrity from power supply
noise and power network coupling noises. Fully independent design practice with
respect to power delivery or signal integrity is not sufficient to guarantee a healthy
system. Accurate and efficient methodologies are needed to incorporate both
power network and signal network in order to capture their couplings.

> Read full chapter

Data Center Architectures and Oppor-

tunities for Silicon Photonics
Daryl Inniss, Roy Rubenstein, in Silicon Photonics, 2017

7.6 Adding Photonics to Ultralarge-Scale Chips

The benefits of copackaging include higher-performance chips, lower-power con-
sumption, and greater signal integrity although it will require considerable devel-
opment work before it is commercially deployed in volume.

Will an optics and photonics union end at copackaging? Extrapolating, could not
optics end up in the chip, not just bolted alongside? Integrating optics within the
chip would enable optical communications inside the chip and to other such chips.
A group of US academics in a paper published in the scientific journal Nature have
demonstrated just that: a microprocessor that integrates logic and silicon photonics
in one chip, with the optics enabling communications between chips [28].

Vladimir Stojanovic, one of the academics involved in the project and based at the
University of California, Berkeley, claims it is the first time a microprocessor has
communicated with the external world using something other than electronics.

The chip features two processor cores, as shown in Fig. 7.11, and 1 MB of on-chip
memory, and comprises 70 million transistors and 850 optical components. The chip
is also notable in that the researchers achieved their goal of fabricating it on a stan-
dard IBM 45-nm CMOS line without any alteration. They managed to implement
the photonics functions using a CMOS process tuned for digital logic—what they
call “zero-change” silicon photonics.

Figure 7.11. Optical interconnection integrated with microprocessors.

Reprinted by permission from Macmillan Publishers Ltd: Chen Sun et.al., Sin-
gle-chip microprocessor that communicates directly using light, Nature 528,
534–538 (24 December 2015), copyright 2015.

Pursuing a zero-change process was initially met with skepticism, says Stojanovic.
People thought that making no changes to the process would prove too restrictive
and lead to very poor optical device performance. Indeed, the first designs didn’t
work. But the team slowly mastered the process, making simple optical devices
before moving onto more complex designs.
The chip uses a micro-ring resonator for modulation, while the laser source is exter-
nal to the chip. The modulator, which is known to be sensitive to small temperature
changes, is corrected with on-chip electronics.

The team has demonstrated two of its microprocessor chips talking to each other.
One processor talked to the memory of the second chip that was 4 m away. Two
chips were used rather than one—going off-chip before returning—to prove that
the communication was indeed optical as there is an internal electrical bus on the
chip linking the processor and memory.

For the demonstration, a single laser operating at 1183 nm feeds the two paths link-
ing the memory and processor. Each link operates at 2.5 Gb/s for a total bandwidth
of 5 Gb/s.

However, for the demonstration, the microprocessor was clocked at one-eightieth

of its 1.65-GHz clock speed—20.7 MHz—because only one wavelength was used to
carry data and a higher clock speed would have flooded the link.

The microprocessor design can support 11 wavelengths for a total bandwidth of

55 Gb/s, while the silicon photonics technology itself will support between 16 and
32 wavelengths overall.

The group is lab-testing a new iteration of the chip that promises to run the
processor at full clock speed. The factor-of-80 speedup is supported by using 10
wavelengths instead of one, each at 10 Gb/s, while the design will support duplex
communications. The latest chip also features improved optical functions. “It has
better devices all over the place: better modulators, photodetectors, and gratings. It
keeps evolving,” says Stojanovic.

The microprocessor development is hugely impressive. The demonstration is in

effect two generations ahead of what’s being developed today with transceivers. But
the work already shows two things. One is that on-chip photonics can work alongside
complex logic in the form of a two-core processor and memory. And the researchers
achieved the photonics design without altering a standard CMOS process.

Optical communications using silicon photonics inside a chip is a long way off.
The researchers deliberately chose to demonstrate chip-to-chip communications
because they recognize that is the next big opportunity. As Stojanovic says, that is
where the biggest bang for the buck is.

> Read full chapter

Noise Analysis and Design in Deep Sub-

micron Technology
Mohamed Elgamel, Magdy Bayoumi, in The Electrical Engineering Handbook, 2005

7.3.1 Signal Encoding Techniques

Increased coupling effect between interconnects in ultra deep submicron technol-
ogy not only aggravates the power-delay metrics but also deteriorates the signal
integrity due to capacitive and inductive cross talk noises. Conventional approaches
to interconnect synthesis are aimed at optimal interconnect structures in terms of
interconnect topology, wire width and spacing, and buffer location and sizes (Cong,
1999).

Signal encoding schemes have been proposed to minimize transition activities

on busses while ignoring crosscoupled capacitances. When statistical properties
are unknown a priori, the bus-invert method (Stan and Burleson, 1995) and the
on-line adaptive scheme (Benini et al., 1999) can be applied to encode randomly
distributed signals. On the other hand, highly correlated access patterns exhibit a
spatiotemporal locality that can be exploited for energy reduction (Panda and Dutt,
1996) in Gray code (Mehta et al., 1996; Su et al., 1994), the TO method (Benini et al.,
1997), the workingzone encoding (Musoll et al., 1998), the combined bus-invert/TO
(Benini et al., 1998), and the coupling-driven method (Kim et al., 2000). Lower
bounds for minimum achievable transition activity have been derived for noiseless
busses in (Ramprasad et al., 1999) and for noisy busses in Hegde and Shanbhag
(1998). In Zhang et al., (1998), a segmentation method was introduced to reduce
power consumption. Specification transformation approaches have also been used
to reduce the number of memory accesses at the behavioral level (Catthoor et al.,
1994). The effectiveness of various encoding schemes was compared at the system
level by Fornaciari et al. (1999).

Bus-Invert Encoding
The bus-invert encoding has been introduced to reduce the bus activity: the en-
coding is derived from the Hamming distance between the consecutive binary
numbers. If the Hamming distance of the two consecutive binary numbers is more
than half of the word length, the latter binary number is sent in inverted polarity by
asserting an additional signal line that indicates bus inversion (Stan and Burleson,
1995). The number can be used to reduce the weight (the number of ones or zeros)
of the binary numbers if the bus-inversion decision is made when the weight is more
than half of the bus width. The bus-invert method is as follows:

1. Compute the Hamming distance (the number of bits in which they differ)
between the present bus value (also counting the present invert line of Figure
7.7) and the next data value.FIGURE 7.7. Invert Signal in Bus-InvertMethod
2.
 If the Hamming distance is larger than n/2, set invert equal to 1 (and thus
make the next bus value equal to the inverted next data value).
3. Otherwise let the invert equal 0 (and make the next bus value equal to the next
data value).
4. At the receiver side, the contents of the bus must be conditionally inverted
according to the invert line unless the data are not stored encoded as they are
(e.g., in a RAM). In any case, the value of the invert must be transmitted over
the bus (the method increases the number of bus lines from n to n + 1).

The Gray code has only a 1-bit difference in consecutive numbers for addressing.
Due to locality of program execution, Gray code addressing can significantly reduce
the number of bit switches. Experimental results show that for typical programs run-
ning on an RISC microprocessor, using Gray code addressing reduces the switching
activity at the address lines by 30 to 50% compared to using normal binary code
addressing.

In TO Encoding, the bus transitions are reduced by freezing the address lines when
consecutive patterns are found to be sequential. An extra bus line is employed to
inform the receiver side regardless if the current pattern is sequential.

The basis of the working zone encoding (WZE) technique is as follows:

1. The WZE takes into account the locality of the memory references: applications
favor a few working zones of their address space at each instant. In such cases,
a reference can be described by an identifier of the working zone and by an
offset. This encoding is sent through the bus.
2. The offset can be specified with respect to the base address of the zone or to the
previous reference to that zone. Because all small offsets should be encoded
in a one-hot code, the latter approach is the most convenient. As a simple
example, consider an application that works with three vectors (A, B, and C)
as shown in Figure 7.8. Memory references are often interleaved among the
three vectors and frequently close to the previous reference to the vector. Thus,
if both the sender and the receiver had three registers (henceforth named p)
holding a pointer to each active working zone, the sender would only need
to send:a.The offset of the current memory reference with respect to the one
associated with the current working zoneb.An identifier of the currentFIGURE
7.8. Address Space for Three Vectors.Adapted from Musoll et al. (1998). © 2004
IEEE.Copyright © 2004

To reduce the number of transitions, the offset is encoded in a one-hot code. Because
the one-hot code produces two transitions if the previous reference was also in
the one-hot code and an average of n/2 transitions when the previous reference
is arbitrary, using a transition-signaling code reduces the number of transitions
(Musoll et al., 1998).
Coupling-Driven Signal Encoding
The key idea in coupling-driven signal encoding is that transforming the signal
sequences traveling on-chip busses that are closely placed could alleviate coupling
effects (Kim et al., 2000). Small blocks of encoding and decoding logic are employed
at the transmitter and receiver of on-chip busses as shown in Figure 7.9.

FIGURE 7.9. Tightly Crosscoupled On-Chip Busses in a System-Level Chip Design.

Adapted from Kim et al. (2000). © 2004 IEEE.

Copyright © 2004

There are four types of possible transitions when dynamic charge distribution is
considered over cross coupling capacitances as in Figure 7.10. Two parallel wires are
placed with minimum spacing. A type I transition occurs when one of the signals
switches while the other stays unchanged such that the cross coupling capacitance
is then charged up to klCxV, where the coefficient k1 is introduced as a reference
for other types of transition. In a type II transition, one bus switches from low to
high while the other switches from high to low. The effective capacitance will be
larger than k1 by a factor of k2, the value of which is usually k2 = 2. In a type III
transition, both signals switch simultaneously, and Cx will not be charged. Because
of possible misalignment of the two transitions, however, the amount of power
consumption varies according to the dynamic characteristics by a factor of k3. In
a type IV transition, there is no dynamic charge distribution over cross coupling
capacitance. Thus, k4 is set to zero.
FIGURE 7.10. Transition Types. (A) This circuit shows single line switching; (B) Both
lines are switching in the opposite direction; (C) Both lines are switching in the same
direction; (D) No switching is occurring here.

There are some assumptions. First, synchronous latches are located at the trans-
mitter side, thus all the transitions take place at the same time on the bus. The
simultaneous transitions exclude type III transitions by setting k3 = 0. The achieved
results are on the lower end of power savings. Second, statistics on the information
source are not given in advance. Hence, this scheme is suitable for data bus encod-
ing, where it is difficult to extract accurate probabilistic information off-line. An
enumeration method is employed to represent the coupling effect. If a bus line Bi is
located between two other lines, a signal transition on Bi can trigger charge shifts on
both coupling capacitances connected to Bi−1 and Bi+1, respectively. In other words,
two couplings can be initiated at most by a signal transition. Thus, 2(N-1) bits are
sufficient to represent the whole set of couplings in an N-bit bus per bus cycle.
According to the types of correlated transition between neighboring busses, the
coupling encoder generates a codeword as follows: 00 for a type III or IV transition,
01 for a type I transition, and 11 for a type II transition. The reason 11 is assigned
to a type II transition is that switchings in different directions require the change in
polarity of the charge stored in the coupling capacitance, hence consuming about
twice the amount of charge required for a type I transition. The codeword 11, instead
of 10, helps to make a decision on data inversion using a majority voter because the
majority voter outputs high when at least eight input lines are high out of fifteen
inputs. The majority voter can be implemented by using either full-adder circuitry
or resistors and a voltage comparator. The control signal inv can be transmitted to
the receiver using extra bus lines or extra transfer cycles. One problem of additional
bus lines for control is the area overhead that may not be allowed due to physical
constraints. In some cases, widening the space between signal bus lines can reduce
the coupling effects more effectively than introducing extra control lines because the
coupling capacitance is inversely proportional to net space. Temporal redundancy is
an alternative and uses extra clock cycles to transfer control signals.

> Read full chapter

Board-Level Design Decisions and Allo-
cation
R.C. Cofer, Benjamin F. Harding, in Rapid System Prototyping with FPGAs, 2006

6.8 Signal Integrity

No longer does designing with an FPGA include just proper implementation of
HDL code and logic. The FPGA designer must know and understand important
signal integrity issues that have become a critical part of FPGA design. Good signal
integrity practices will limit the amount of cross-talk, ground bounce, and ringing
by controlling and implementing proper noise margins, impedance matching, and
decoupling. Signal integrity is especially critical for high-speed design. High-speed
design may require extra FPGA device power decoupling, external controlled imped-
ance PCB traces and signal trace termination. The topics addressed in this section
include signal protocol choices and implementation addressing single-ended and
differential signal use, control impedance, and signal termination.

These topics and additional signal integrity design guidance are covered in
high-speed design application notes and user guides from each manufacturer. It is
highly advisable that these design guidelines addressing this very complex topic be
followed. This will help to ensure reliable FPGA design.

6.8.1 Signal Protocol Choices and Implementation

Each FPGA manufacturer tries to support as many signal and interface protocols
as possible for the target applications for their specific device families. Each I/O
bank can support specific I/O protocols, levels and standards. In general, most I/O
blocks have not been designed for heavy loads or extreme conditions. Generally
they have been optimized for medium to light loads and high performance. With
care, signals can be distributed between I/O banks set up to support the appropriate
standards and FPGA devices can be used to translate between digital communication
protocols. Most I/O standards are set through a combination of reference voltages
and FPGA internal modes and software switches. Take care to make sure that conflicting
I/O standards have not been assigned to the same I/O bank.

Beyond a certain speed range, it becomes attractive to move signals across dif-
ferential signal trace pairs. Further detail on high-performance I/O is presented in
Chapter 16, Advanced I/O. Higher performance signal interfaces and signal integrity
become more critical when high-speed serial or parallel interfaces such as DDR,
DDR2 or QDR memory interfaces are implemented. Adjustable signal slew rates help
characterize signal performance. Many SSOs can create additional system noise and
affect system performance.

Signals with fast data or clock rates or fast edge rates can cause traces to behave like
transmission lines. For “high-speed” design (generally 50 MHz and higher) imped-
ance control becomes important, even for short runs. Following FPGA manufacturer
high-speed design suggestions can improve system reliability and performance
significantly.

Unterminated signals or poorly controlled signal impedance can cause signal re-
flections. The reflections may degrade signal quality and limit maximum system
performance. Signal termination requires adding additional components, typically
in either a serial or parallel configuration. Termination generally occurs at either
the source or destination of a PCB trace. Some FPGA families support termination
internal to the component. Designers should be aware that signal termination
internal to the FPGA package will increase the power dissipated within the device.
This should be taken into consideration when conducting FPGA thermal analysis.
The variations and details of signal termination are beyond this text, but extensive
technical guidance is usually provided by manufacturers and third-party sources.

> Read full chapter

Unrepeatered Transmission
Herve Fevrier, ... Wayne S. Pelouch, in Undersea Fiber Communication Systems
(Second Edition), 2016

7.5 Optical impairments and limitations

Although today’s cable systems transport digital data, the propagation of the optical
channels inside the line fiber is essentially an analog process with multiple interac-
tions between different factors that can potentially degrade signal integrity beyond
the capacity of the receiver to properly recover it.

In the preceding section, it was shown how transmitting at a higher optical power
and using forward Raman amplification improves the OSNR. However, there are
limitations due to nonlinear optical effects on the maximum signal power in the line
fiber. Linear impairments also occur during fiber propagation but they do not really
cause any serious issue due to the modest length of unrepeatered cable systems
and the performance of coherent receivers. Figure 7.12 shows the different optical
transmission impairments that may limit the reach or capacity of unrepeatered cable
systems.
Figure 7.12. Optical impairments experienced by the optical carriers in multi-chan-
nel single-span transmission.

7.5.1 Limitations induced by linear effects

7.5.1.1 Attenuation

Attenuation is obviously a key factor as many unrepeatered cable systems are

loss-limited, with a strong coupling between achievable capacity and end-to-end
span loss. For instance, for a given transmission technology of the interface card
(e.g., bit rate and modulation format), the number of wavelength-multiplexed op-
tical channels that can be effectively transmitted decreases as the end-to-end loss
increases.

Material and process advances have been pushing the limits of the lowest attenu-
ation achievable in optical fiber well beyond what was predicted 20 years ago. The
most recent works reported an attenuation as low as 0.146 dB/km at 1560 nm [10].

7.5.1.2 Chromatic and polarization mode dispersion

Neither chromatic dispersion nor polarization mode dispersion (PMD) is an issue in

unrepeatered cable systems because the modest fiber length results in cumulated
dispersions that can be easily compensated by digital signal processing, as widely
used in coherent systems.

7.5.2 Limitations induced by nonlinear effects

Above a given optical power threshold, optical fiber properties can be modified due
to nonlinear effects occurring during light propagation [28–30]. This applies to both
the signal waves that carry the information to be transmitted and the pump waves
that may be used for remote or distributed Raman amplification. For both kinds of
waves, unrepeatered systems usually involve very large optical powers that are at the
edge of the nonlinear effects thresholds. These nonlinear interactions can be divided
into three main categories: (1) Kerr effects, (2) Brillouin effect and (3) Raman effect.

7.5.2.1 Kerr effects

The refractive index of the waveguide is modulated by the fluctuations in the signal(s)
intensity via the Kerr effect as described by the following relation:

(7.21)

where n is the fiber refractive index, n0 the linear part of the fiber refractive index,
n2 the nonlinear index coefficient, Aeff the fiber core effective area and P the
optical power. This nonlinear effect can broaden the channel spectrum and therefore
interplay with the fiber chromatic dispersion, resulting in pulse distortion and
broadening. The Kerr effect is usually decomposed into three different contributions
that are actually closely related.

When a signal travels alone through the fiber, its modulated power induces a
self-phase modulation (SPM). By contrast, the presence of several channels in a
WDM transmission generates on each signal a cross-phase modulation (XPM), a
process through which the intensity fluctuations in a particular channel are convert-
ed to phase fluctuations in the other channels [31]. SPM and XPM impairments are
of the same nature between unrepeatered and repeatered systems except that they
occur over a single span instead of being cumulated over several cascaded spans
with a lower strength within each span (see Chapter 5).

When the WDM signals are well phase-matched (i.e. moderate fiber chromatic
dispersion), the Kerr effect produces four-wave mixing (FWM): new waves can be
generated via third-order intermodulation process. FWM can transfer a fraction of
the channel powers to the frequency of the other channels through the generation of
FWM waves. FWM waves can impair system performance due to homodyne crosstalk
leading to amplitude interferences during the quadratic detection at the photodiode
level.

The FWM between WDM channels is well documented [28] but FWM can also occur
between Raman pumps and WDM signals, and between Raman pumps, depending
on the zero chromatic dispersion wavelength of the line fiber.

In LEAF fiber with a zero chromatic dispersion wavelength close to 1500 nm, there-
fore between the Raman pumps and signals wavelengths, forward Raman pumping
can cause a FWM effect at the beginning of the fiber span between the pumps and
signals waves with FMW waves created inside the WDM spectrum. Another case is
when the zero chromatic dispersion wavelength falls between the pump wavelengths
in a backward pumping scheme: the FWM effect between the pump waves at the
end of the fiber span can result in FWM waves falling inside the WDM spectrum.
Both cases are illustrated in Figure 7.13 [18]. Fibers with a zero chromatic dispersion
wavelength close to 1500 nm are not common in unrepeatered cable systems but
one needs to be aware of this specific FWM configuration if such cases are met.

Figure 7.13. Four-wave mixing (FWM) in non-zero dispersion-shifted fibers with

a zero chromatic dispersion wavelength a) between the Raman pumps and signal
wavelengths in a forward pumping scheme, and b) between the pump wavelengths
in a backward pumping scheme.

7.5.2.2 Stimulated Brillouin scattering

Stimulated Brillouin scattering (SBS) is an inelastic phenomenon resulting from the

scattering of an incoming photon inside the optical fiber, resulting in a higher fiber
back reflection at large launched power [28]. A simple SBS-suppression method
consists of modulating the signal laser current with a small amplitude and low
frequency, which induces laser chirp and permits launch powers up to about 20 dBm
with moderate overmodulation amplitude.

7.5.2.3 Stimulated Raman scattering

Stimulated Raman scattering (SRS) is an inelastic phenomenon resulting from the

scattering of an incoming photon inside the optical fiber, as described in subsection
7.4.2. If we approximate the Raman gain spectrum by a triangular profile such that
gr(v) increases linearly versus the frequency from 0 to 13.2 THz, then the tilt induced
by SRS is expressed in decibels by [32]:

(7.22)

where gR is the Raman gain, Leff the effective length of the fiber, Aeff the effective
fiber area, Pout the total input power in the fiber (W) and Δ the optical bandwidth
(nm).

For a given fiber type, Eq. 7.22 demonstrates that the tilt induced by SRS during
fiber propagation depends only on the total launched power and the wavelength
bandwidth. The SRS tilt can be compensated by linear channel preemphasis with
a reverse slope at the transmit end and an adequate gain shaping of the Raman
amplifiers present in the link.

7.5.2.4 Summary

From this section, it clearly appears that the ideal fiber for a high-performance
unrepeatered cable system shall exhibit low attenuation, high chromatic dispersion
and large effective core area. These three features reduce the amount of optical
amplification to be implemented (and thus the amount of optical noise that will be
generated) along the optical path and push back the fiber nonlinearities threshold.

On another line, it is worth noting that unrepeatered systems lead to a larger

signal independence than repeatered systems. Because of the smaller number of
amplification devices involved in an unrepeatered system, the potential impacts
upon common equipment performances and interactions with existing wavelengths
when new wavelengths are added to a fiber pair already equipped are lower. Another
factor favoring the lack of impact upon existing traffic is the number of fiber pairs
(typically 12 or 24 in an unrepeatered cable system to be compared with 4 or 6 in
a repeatered system). This higher fiber count enables more flexible strategies when
new capacity needs to be added to the subsea cable system.

> Read full chapter

Advanced Interconnect
R.C. Cofer, Benjamin F. Harding, in Rapid System Prototyping with FPGAs, 2006

16.6 Summary
FPGA manufacturers continue to advance the performance of FPGA interconnec-
tion functionality by supporting more I/O protocols and standards. The areas of
improvement include performance, flexibility, broad standard and protocol support,
signal integrity enhancement, and reduced cost of implementation. Modern FPGAs
incorporate advanced I/O to extend FPGA's interconnection capability.

FPGA manufacturers continue to develop and incorporate advanced dedicated I/O

circuitry and dedicated hard IP structures, advanced dedicated clock circuits and
routing to implement higher speed interconnection capabilities. Examples include
serial transceiver circuitry, Gigabit Ethernet MAC and IOB dual-registers to support
DDR memory interfaces.

Incorporating these advanced features within an FPGA's internal logic fabric and
I/O blocks supports increased system-level integration, higher performance and
reduced design complexity and development effort. FPGA manufacturers also con-
tinue to develop soft IP and design tool enhancements, which make it easier
to implement common high-performance interconnection functionality. Targeted
advanced interconnection applications include DDR, DDR-2, Rapid IO, and Gigabit
Ethernet.

> Read full chapter

System on Chip (SoC) Design and Test

Swarup Bhunia, Mark Tehranipoor, in Hardware Security, 2019

3.8.3 At-Speed Delay Test Challenges

As circuit complexity and functional frequency increase, power integrity and timing
integrity are becoming more and more important to circuit design and test. The
test power consumption, supply voltage noise, and crosstalk noise caused by signal
coupling effect, and hot spots caused by nonuniform on-chip temperature will
significantly impact yield and reliability. As shown in Fig. 3.22, with technology node
shrinking, the percentage of delay caused by coupling effect between signal lines
(crosstalk noise), and IR-drop on power and ground lines (power supply noise), is re-
sponsible for a larger portion. Power supply noise and crosstalk noise are becoming
two important noises that impact circuit's timing integrity. The lower supply rails in
today's ICs mean much less immunity from signal integrity problems that tie directly
into power integrity [40]. Supply voltages on many high-end ICs are now down to
1 V and below, leading to decreasing margins for voltage fluctuation. Simultaneous
switching noise can cause ground to fluctuate, leading to difficult-to-isolate
signal-integrity problems and timing issues. What makes it more challenging is that
power, timing, and signal integrity (SI) effects are all interdependent at 90-nm and
below.

Figure 3.22. Parasitic effects with respect to process node.

Timing failures are often the result of a combination of weak points in a design and
silicon abnormalities, which reduce the noise immunity of the design and expose it
to SI issues. For example, a poor power planning or missing power vias can incur
on-chip power droop for some test vectors. The power droop can impact a gate(s)
on a critical path and it may cause timing failure. This failure may only be recreated
with certain test vectors as inputs. If the corresponding test vector is not included
in the test pattern set, the failure becomes an escape and cannot be reproduced
during diagnosis with the current test pattern set. Current automatic test pattern
generation tools are not aware of the switching distribution on the layout and the
pattern-induced noises. There are escapes and “No Problem Found” parts returned
by customers, which have passed the tests using the layout-unaware test patterns
generated by ATPG tools. Thus, high-quality test patterns are imperative to capture
noise-induced delay problems during production test and identify noise-related
failures during diagnosis [41,42].

> Read full chapter

Channel modeling and simulation

Hanqiao Zhang, ... Jeff Ou, in High Speed Digital Design, 2015
Pre-Layout Modeling
If design differences are significant, pre-layout modeling will be done according to
board layout requirements for signal-to-signal and signal-to-ground separation.

Models may be drawn manually in 3D FEM solvers. Some software includes via
wizards to simplify the modeling process. A simplified process for creating the
physical via model is:

1. Build the stackup.

2. Build the signal vias and pads.

3. Create an anti-pad around signal via barrels.

4. Add ground vias and pads.

5. Add signal trace and ports.

The following guidelines should be used when developing the physical model:

1. Do not include pads on unused signal layers. Removal of pads on unused

internal layers is a common manufacturing capability with significant signal
integrity benefits. The only pads should be on both external layers and any
internal layer(s) used for signal transition.
2. Consider an accurate number of signal-to-ground vias and realistic ground
via placement as much as possible. An optimistic return path will lead to
underestimated losses and crosstalk in the model.
3. Ensure that the transmission line is routed at the geometries (trace width,
spacing, etc.) and characteristic impedance of the remainder of the intercon-
nect.
4. Attach transmission lines to lumped ports. Transmission lines connecting the
lumped port to the via should be long enough to establish TEM and uniform
waves. Creating transmission line segments that are too long interferes with
the flexibility to pair the model with short routing or alternate routing imped-
ances. The minimum length is a function of dielectric thickness. Approximately
10 times the distance to the primary reference plane is recommended.
5. Convert power planes to ground planes. This is accomplished by intersecting
all power and ground planes with the return path or ground vias in the model.
6. Hollowed cylinders are preferred but not be required. High-frequency current
follows on the outer edge of the via barrel, making the hollow feature negligi-
ble.

> Read full chapter

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