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    Study On Equalizers: Anik Sengupta Sohom Das

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    Study On Equalizers: Anik Sengupta Sohom Das

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    Equalizers

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    53 views11 pages

    Study On Equalizers: Anik Sengupta Sohom Das

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    AnikSengupta

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    © All Rights Reserved
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    of 11

    Study

    On
    Equalizers

    Anik Sengupta
    Sohom Das
    EQUALIZATION

    An ideal cable could propagate all frequency components without any loss. In reality, all
    the electrical transmitting mediums have finite signalling bandwidth which limits the data
    rate of binary signalling. Equalization schemes have been developed both at the
    transmitter side and the receiver side to compensate the loss of transmitting mediums
    and extend a channel’s maximum data rate.

    There are many different types of equalizers.

    · ZFE – Zero Forcing Equalizer

    · MMSE-LE – Minimize Mean Square Error-Linear Equalizer

    · DFE – Decision Feedback Equalizer

    · MLSE – Maximum Likelihood Sequence Equalizer

    The channel can be thought of as a filter. And the equalizer is basically the inverse
    channel, that nullifies the distortion caused by the filter(channel).

    Typical channel input and output data streams


    As we can see, the output waveform never really reaches its steady state value,
    furthermore we see that for some data around the 23 ns mark, we get error in the output
    bits.

    TX feed-forward equalization (FFE) acts as an FIR filter and pre-distorts transmitted


    pulse in order to invert channel distortion. At the receiver side, RX FIR, continuous time
    linear equalizer (CTLE) and decision feedback equalizer (DFE) are implemented as part
    of receiver circuits and flatten the system response through conditioning the receiving
    signal. Figure 1 shows a high-speed electrical link using TX FFE equalization and RX
    CTLE+DFE equalization.
    FEED FORWARD EQUALIZATION

    Transmit equalization is the most common technique in high-speed links design. It is


    usually implemented through an FIR filter. It pre-distorts or shapes the data over several
    bit periods in order to invert the channel loss/distortion. The low frequency components
    get de-emphasized in order to flatten the channel response. Without an FIR equalizer,
    the TX driver transmits 1 as a single pulse as the red curve shown in Figure 2(a). The
    pulse is dispersed by the channel loss/distortion. It is shown as the red curve in Figure
    2(b) with pre-curse ISI and post-curse ISI. By using FFE, the pulse is shaped as the
    blue curve shown in Figure 2(a). The pulse is shaped based on the channel response.
    The pulses at time -1 and +1 are generated to cancel the channel pulse response’s ISI.
    The equalized pulse is shown as the blue curve in Figure 2(b).

    TX FFE can be implemented as a FIR filter by using unit time delay elements (flip-flops)
    and current steering DAC circuit as shown in Figure 3(a). Compared with implementing
    a FIR filter at the receiver side, it is generally easier to build high-speed digital-to-analog
    converters versus receive-side analog-to-digital converters. However, the transmitter is
    limited by the peak transmitting power across the channel due to driver voltage
    headroom. Channel response flattening is realized through attenuating low-frequency
    signal content as shown in Figure 3(b).
    Pros:

    • High speed DAC is relatively easy to implement compared with receiver high speed
    ADC.

    • TX FFE can cancel precursor ISI

    • Due to the digital nature of the TX FFE, the noise is not amplified.

    • 5-6-bit resolution can be achieved.

    Cons:

    • To flatten the channel response, low frequency content is attenuated due to the peak
    power limitation.

    • To tune the FIR taps, a feedback path from receiver side is required to detect channel
    response.

    Structure of Transmitter:
    To mitigate the effects of channel loss, a 4-tap feed-forward equalizer (FFE) is included
    in the transmitter.

    The complete transmitter architecture is shown in Fig 2. To facilitate the testing, a built-
    in 27-1 (pseudo-random sequence) PRBS generator is included to provide eight
    625Mbps pseudo-random inputs for the 4:1 MUX stage. The blocks of 4:1 MUX and 2:1
    MUX serialize the input data into 5Gbps. As a result, the FFE with 4 taps exhibits
    sufficient gain in high frequency. The Fig.3 illustrates the response of FFE having 4
    taps. Another issue is the parasitic capacitance caused by the taps. Adding more taps
    implies linear increase of parasitic capacitance at the output node. Since bandwidth is
    inversely proportional to this capacitance. Thus, in this design, we choose 4 taps as a
    compromise between bandwidth and accuracy. The PLL is responsible for multiplying a
    reference clock by 40, providing 5GHz clock for the transmitter.

    The FFE structure is shown in Fig.4. The data streams are shifted by in unit interval (UI)
    for the first tap of FFE. Additional shifting yields the delayed data for the remaining 3
    taps of the FFE. After sign selection, the output of these currents are summed together
    in the line termination loads

    The system performance of an FFE is dictated primarily by two parameters: the tap
    spacing (also known as tap delay) and the number of taps. Fractionally-spaced FFE
    structures have been utilized for more than two decades. In particular, Gitlin’s work on
    T/2 spaced equalization demonstrates that this type of equalizer not only reduces
    aliasing but also directly improves performance .Such a T/2 spaced structure doubles
    the equalizer frequency domain range.

    A delay element can be implemented by using either a passive transmission line or an


    active unity-gain buffer. On-chip transmission lines have been used in various FFEs
    with low power dissipation being their main advantage over active unity-gain buffers.
    Transmission lines can be formed by strip lines, coplanar waveguides or lumped
    elements. In a lumped element transmission line, on-chip spiral inductors and
    capacitors are cascaded. At frequencies above 10 Gb/s, the parasitic capacitances of
    the transistors used in the FFE multipliers usually play the role of the transmission line
    capacitors. Thus, in contrast to the active delay approach where multiplier input and
    output capacitances directly limit the delay element bandwidth, the lumped element
    topology absorbs the capacitance and therefore reduces the bandwidth degradation.
    The lumped element approach, however, does suffer from some disadvantages. First,
    because multiple inductors are connected in series, the accuracy of their models is
    critical in predicting the FFE behavior. Second, the parasitic resistance of the inductors
    and their interconnections accumulates and limits the number of realizable FFE taps
    and the total delay of all taps. Third, the gain/loss of each tap is not well controlled,
    which reduces the overall equalizer performance. Due to this limitation, the highest total
    delay of all taps of 40 Gb/s FFE published to date has not exceeded 75 ps. A combined
    approach is used that generates the required tap delay through the use of both passive
    and active delay elements. The active elements isolate each tap, and eliminate the
    need for larger die area for transmission lines. In addition, because transmission line
    modelling is not supported by industry standard CMOS CAD tools, the use of active
    elements is also more attractive from a practical point of view. At the same time the
    output currents are delayed through passive elements, absorbing the multiplier output
    capacitance and providing large bandwidth at the output. In this structure, the effective
    tap delay is the difference between the two delay elements. The delays for the active
    and passive elements are designed to be 15.5 ps and 3 ps, respectively, resulting in an
    effective tap delay of 12.5 ps. In addition, since the passive delay element accounts for
    only 25% of the total tap delay, its modelling inaccuracy plays a smaller role in the
    equalizer performance.
    DECISION FEEDBACK EQUALIZER

    A decision feedback equalizer (DFE) is a type of adaptive, non-linear filter and it uses
    feedback of detected symbols to produce an estimation of the transmission channel. it
    contains a forward filter and a feedback filter.

    The forward filter is a linear filter and the feedback filter is fed with the decisions made
    on the equalized signal to input to a tapped delay line and produces the output which is
    typically is subtracted from the output of the linear equalizer.

    Block Diagram of DFE with one tap

    DFE works on the principle that, once the present symbol is correctly predicted, one can
    remove the ISI contribution caused by this symbol from subsequent future symbols
    (Postcursor ISI).

    Precursor ISI refers to the ISI caused by the preceding bits. Postcursor ISI is caused by
    succeeding bits.

    Precursor and Postcursor ISI


    This is determined by the time it takes for the symbols to reach from the transmitter to
    the receiver and the rate at which symbols are transmitted. For example, if propagation
    time is the same as that for which the transmitter produces 5 symbols, then we can
    assume that these 5 symbols will interfere with each other, as they exist in the same
    time frame in the channel.

    (a) A four tap DFE system (b) Removal of postcursor ISI by DFE system

    (a) Eye diagram before DFE (b) Eye Diagram after use of DFE

    The first eye diagram has a much more closed eye, this is due to the fact that the output
    cannot reach its maximum value as the symbol changes from 0 to 1 over and over
    again, due to ISI. The second eye diagram is much more open, due to the effect of the
    DFE.
    (a) (b) ©

    Bit Response of DFE (five tap) depending on channel characteristics

    Fig ( a ), shows us channel characteristics of two different channels (one in red which is
    lossy as well as very erratic, another in blue, which is lossy but smooth).
    Fig ( b ), shows us the bit response of the smooth channel (blue curve), and the bit
    response after using DFE (black curve). We can see we are getting good results.
    Fig ( c ), shows us the bit response of the bumpy channel (red curve), and the bit
    response after using DFE (black curve). It is evident that DFE does not produce a good
    waveform, there is no significant improvement from the original bit response.

    Furthermore, it is evident that the DFE is vulnerable to ‘error propagation’, where the
    initial error is fed back to cause a sequence of errors. Another problem is that it can only
    equalize the postcursor ISI, precursor ISI remains unchecked.

    Pros:

    • Can boost high frequency content without noise and crosstalk amplification
    • Filter tap coefficients can be adaptively tuned without any back-channel

    Cons:

    • Cannot cancel precursor ISI


    • Chance for error propagation
    • Critical feedback timing path
    Conclusion:

    Difference between FFE and DFE:

    FFE DFE

    Can mitigate the pre‐cursor channel Cannot equalize ISI arising from
    response in low‐BW channels. pre‐cursor channel response.

    Can compensate ISI arising from Can only compensate ISI from a
    transient TL loss over wide time‐spans fixed time‐span.

    FFE + DFE

    •Guarantees max. performance from the SerDes.

    •Advantage:

    - DFE permits use of low‐frequency de‐emphasis at TX resulting in a larger


    received signal envelope, smaller signal/crosstalk ratio

    - System capable of employing continuous adaptive equalization of its feedback


    taps to optimize performance.

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