Chapter 4

CIRCUIT DESIGN CONCEPTS FOR ESD

PROTECTION

1. INTRODUCTION

The internal ESD protection requires the placement of adequate on-chip

protection devices on the I/O and on the power supply pins to reliably
bypass the ESD energy before it can damage the sensitive circuits. The on-
chip protection scheme should have an explicit and robust path for the ESD
currents to flow between any pair of pins. In general, pad protection net-
works shunt I/O pins to the ground or VDD bus under stress events. For each
input pin, a dedicated protection network, that is completely passive under
normal operating conditions, has to be added. For each output pin, the ESD
protection level is determined by the intrinsic robustness of the output buffer
transistors plus that of the dedicated protection devices. A good protection
element should minimize the nominal performance and/or voltage degra-
dation to the I/O circuit due to its insertion and provide a low-impedance
shunt path for the ESD current. The protection element must be capable of
handling multiple ESD events without itself being destroyed. It should also
not interfere with the I/O circuit during its normal operation. Hence, a
perfect protection device should have the following characteristic:
x Very low on-resistance
x Triggering voltage should be above the worst case operating supply
voltage (VDD + 10%)
x Almost instantaneous turn-on time

85
O. Semenov et al. (eds.), ESD Protection Device and Circuit Design for Advanced
CMOS Technologies, 85–116.
© Springer Science+Business Media B.V. 2008
86 Chapter 4

x Very high energy handling capability

x Only trigger during ESD events, not during normal operation
x Very low parasitics to minimize performance degradation of I/O circuit
x Consumes small area
Very low on-resistance allows it to shunt large amount of current with no
voltage rise from an ohmic voltage drop. It is clear that a real ESD protect-
tion device can not have all of these characteristics, but these criteria provide
a list of optimizations and compromises to be struck when the protection
circuit is designed.
The ESD devices used for I/O protection in deep submicron CMOS
technologies can be combined in two groups: non-snapback protection
devices and snapback protection devices. The first group includes diodes,
zener diodes and punch through transient voltage suppressors (TVS). The
second group typically includes MOSFETs, lateral double diffused MOS
(LDMOS) transistors, silicon-controlled rectifiers (SCR) and low voltage
triggered SCRs (LVTSCR).
This chapter describes the general principles used to develop the ESD
protection circuits that not only meet the ESD objectives but also meet the
functional objectives of the I/O. At the beginning of this chapter the different
ESD protection circuits for different applications are considered. The second
part of the chapter describes the design flow of ESD protection circuits. It
covers the ESD device simulations and calibration, mixed-mode (device-
circuit) simulations and chip level ESD simulations. The design of special
test structures for ESD network verification and ESD measurement concepts
are also considered in this chapter.

2. ESD PROTECTION NETWORKS

Today’s ICs pack the complex operations of multiple functional sub-

systems, such us analog, RF circuits, memory, digital signal processing
(DSP) units, input/output controls, onto one single “system on a chip”
(SoC) design. Since each functional sub-system may have a unique supply
voltage requirement, multiple power supplies are distributed across the IC
and form complex internal power networks. Both the heterogeneous nature
of SoCs and multiple supply domains are resulting in complex on-chip
ESD protection networks and they are typically optimized for the given
application of the IC.
Circuit Design Concepts for ESD Protection 87

Different ESD protection elements should be combined to form a

protection network. One well-known I/O ESD protection circuit is a pi-
network as shown in Figure 4-1 [1]. During the ESD stress, the secondary
ESD clamp triggers first and then the voltage drop through the resistor is
increased and it triggers the primary ESD clamp. Subsequently, most of ESD
energy is bypassed through the primary ESD clamp. The major advantages
of the pi-protection network are the voltage division and safer triggering of
ESD devices. The first advantage ensures the lower voltage stress in the
internal node, and the second one gives lower trigger voltage in comparison
with using the primary ESD clamp only.
For the digital ICs the multi ESD bus strategy is popular as shown in
Figure 4-2 [1]. In this case, each I/O pad has multi ESD clamps with respect
to ESD buses, which are typically ground bus and power bus. The power line
should also have the power ESD clamp. For the ESD current path between

Figure 4-1. The pi-ESD protection network for I/O. (Adapted from [1].)

Figure 4-2. The general ESD protection network of whole chip.

88 Chapter 4

pad and the VDD or the VSS, simple diodes in a forward biased configuration
can be used if the VDD is equal or higher than the pad voltage. If the pad
voltage is higher than VDD then a suitable diode chain can be used. The ESD
current path between VDD and VSS is provided by the core clamp. This
device is normally off during the circuit operation. During the ESD event it
has low impedance path. The current path between VSS and pad is provi-
ded by the forward biased diode. Here one diode is generally sufficient.
Typically, diodes provide the current path from the pad to VDD and NMOS
core clamp provides the current path between VDD and VSS [2].
Some circuits must work in an environment where input voltage levels
exceed the supply lines. Examples of these are multiplexers and switches.
For instance, the inputs can be specified with a 24 V over-voltage rating,
even though the supplies are rated at 12 V. Having inputs exceeding the
supply lines becomes challenging, because typical protection techniques, as
shown in Figure 4-2, can not be used. One technique, which can solve this
issue, is to allow the inputs to be tied to an isolated bus on chip [3]. This
technique is illustrated in Figure 4-3. When the ESD/EOS event is happened
on I/O pad, its energy is dissipated through the forward biased I/O ESD
diode, floating rail #1, supply clamp, floating rail #2 and ESD diode connec-
ted to the grounded (V-) pad or other grounded I/O pad, respectively.

Figure 4-3. ESD protection network for input voltages that exceed supply levels. (Adapted
from [3].)
Circuit Design Concepts for ESD Protection 89

The supply busses and ESD busses are typically used to provide a low
ohmic path between any couple of pins during the ESD event. In the
simplest form the supply busses are organized as a ring at the perimeter of
the IC for the IO supply and a power mesh in the centre of the IC for the
core supply. Any resistance along this path will count for the ESD design
window of the core protection. This resistance can be controlled by the
width of the metal busses and the distance between the supply pads and
connections on the package substrate. Typical values for wirebond ICs with
an acceptable density of supply pads are 1–2 ȍ [4]. For the 2 kV HBM ESD
stress, which is equivalent to a discharge current of 1.3 A, this leads to a
voltage drop of 1.3–2.6 V.

Figure 4-4. ESD protection network for coupling between two power domains in mixed-mode
ICs. (Adapted from [6].)

In most modern designs a simple power domain arrangement is not any

longer used. Especially for low power designs, for example mobile appli-
cations, there are a larger number of power domains both for core and
for IO circuitry, which should be independently powered. Similarly, a high-
integration giga-scale SoC chips often have multiple and separated power
lines, since the analog, RF, memory and digital circuits have different
voltage and ESD noise requirements [5, 6]. In addition, the VSS lines are
often decoupled to avoid cross-talk between the domains. The typical ESD
protection network for multi-VDD ICs is shown in Figure 4-4, where the
bi-directional diode strings are connected between the VDD1 and VDD2, and
between the VSS1 and VSS2. The number of diodes in the diode string between
the separated power lines depends on the voltage level or the noise level
between these power lines. The diode strings are designed to conduct the
ESD current between the separated power lines to avoid the ESD damage of
internal circuits, when the IC is under the ESD stress. At normal operating
90 Chapter 4

conditions, the diode string is designed to block the voltage or noise between
the separated power lines.
Diode-based ESD power networks are commonly used in many appli-
cations due to easy implementation and area efficiency. However, diode-
based ESD networks are not favored in view of noise margins needed for
mixed mode (digital-analog) circuit operations. In a single n-well CMOS
process, the stringing of diodes causes formation of parasitic PNP bipolar
transistors and during PNP transistor operation some fraction of the emitter
current can sink into the substrate. In the noisy environment due to digital
switching, the delay elements within the voltage-controlled oscillator (VCO)
become sensitive to the Power-Ground (PG) noise. A change in the supply-
ground coupling of a VCO shifts the oscillation frequency. The magnitude of
the error depends on the delay element’s sensitivity to PG noise and the loop
bandwidth. Ground noise coupling through the protection diodes results in
fluctuations in the control voltage and on the local ground of the VCO.
In addition, if the CMOS IC has several separated power pines to supply
different circuit blocks, the ESD current will be discharged through one or
more diode strings connected between the separated power lines [6]. The
multiple diode-strings in the ESD current discharging paths lead to a higher
path resistance and longer delay to bypass the ESD current away from the
internal circuits of the CMOS IC with separated power pins. It may result
into the damage of internal circuits. Hence, the diode-based ESD power
protection network can be not suitable for the CMOS ICs, which have

Figure 4-5. Whole-chip ESD protection design with two ESD buses for mixed-voltage pins.
(Adapted from [7].)
Circuit Design Concepts for ESD Protection 91

much more than 2–3 separated power pins. To overcome the limitations of
conventional diode-based ESD power protection network, the ESD buses
ESD protection scheme was developed [7, 8]. By using ESD busses, the
ESD stress current can be quickly discharged far away from the internal
circuits or interface circuits of CMOS ICs. A simplified version of whole-
chip ESD protection design with two ESD busses is shown in Figure 4-5. In
this figure, the ESD conduction circuits can be the bi-directional ESD cells,
such as dual-mode SCR or two NMOS triggered SCR devices [8]. Typical
power rail ESD clamp circuits include gate grounded NMOS transistors
(GG-MOSFETs), RC triggered PMOSFETs and NMOSFETs, stacked diode
strings, and NMOS triggered SCR devices.

3. DISTRIBUTED ESD PROTECTION NETWORKS

The previously mentioned ESD protection networks have some limitations

and disadvantages. The first primary disadvantage is that power ESD clamps
require a large layout area. Two or more rail clamps, the size of an on-chip
wire bond pad, are often needed to dissipate the required ESD current. Since
these power clamp circuits are quite large, they must be placed wherever
space is available in the pad ring. This is typically in power and ground pad
cells or in large spacer cells between pads. This results in the second primary
disadvantage of active MOSFET-based ESD protection networks. In many
chip applications, large banks of tightly packed I/O pads must be placed,
offering no room for large ESD rail clamp circuits. In these “pad limited”
designs, I/O ESD robustness is reduced with increasing distance from the
remote rail clamps, simply due to bus resistance, which is typically 1–2 ȍ.
For the 2 kV HBM ESD stress, which is equivalent to a discharge current of
1.3 A, this leads to a voltage drop of 1.3–2.6 V. As a result, each new chip
design should be optimized in respect to the size and location of the power
clamps and the power bus resistances in order to protect I/O pads.
To overcome disadvantages of ESD protection networks based on the
large transient triggered MOSFET rail clamp circuits, which described in
details in Chapter 5, distributed active MOSFET power clamp ESD net-
works were developed [9, 10]. In an ideal on-chip ESD network, rail clamps
should be placed in close proximity to all external pads to minimize
the impact of power rail resistance. In a distributed ESD network, rail clamp
NMOS transistors are distributed in each I/O pad cell, while the primary
clamp triggering elements remain remotely placed in power and ground pad
cells. In other words, small rail clamp circuits and buffer circuits are placed
in each I/O pad cell, and the primary RC trigger is placed in remote
locations, like the power and ground pad cells. This distributed rail clamp
92 Chapter 4

ESD network is illustrated in Figure 4-6. A small NMOS transistor, a buffer

circuit, and a small capacitor are placed in each I/O pad cell. In each power
or ground pad cell a complete large rail clamp circuit, including large
NMOS transistor, buffer, and RC circuit, is placed. A key feature of this
approach is that the output of RC trigger in each of power pad cells is
connected to the small clamps in each I/O pad cell by a narrow metal bus
(ESD_RC). Note that both the small capacitors (C2), placed in each I/O pad
cell, and the ESD_RC bus resistance supplement the remote large capacitor
C1 and resistor R1 in the distributed rail clamp operation. The shown in
Figure 4-6 ESD network there is no problem with delayed turn-on of the
distributed clamps since, for positive VDD to VSS zaps, each clamp is trig-
gered on locally, by capacitors C1 or C2. The time-out function, on the other
hand, is controlled remotely, via the resistor R1. For this reason, this design
can tolerate a narrow, somewhat resistive ESD_RC bus. A key feature of the
distributed approach is that for any stressed pad in a group of I/Os, the ESD
stress does not fall only on the small clamp local to the stressed pad. This
local clamp and its neighbors on each side work in parallel to safely dis-
sipate the ESD current. Due to this distributed protection, the clamps in
each I/O may be sized quite small to minimize their layout area.

Figure 4-6. Distributed rail clamp ESD network with remote trigger. (Adapted from [10].)

The important issue of distributed rail clamp ESD networks is the opti-
mization of ESD element sizing in each I/O pad and large clamp circuits. In
distributed ESD network design, the large rail clamps are only needed to
terminate a group of distributed small rail clamps. Therefore, the I/O pad
ESD devices should be sized so that in the center of a very large I/O group,
the distributed small clamps provide full protection, with no assistance from
the distant large clamps. It was found, that as the number of I/O pads in
particular group increases, the optimum ESD device sizes are reduced and
eventually saturated. For example, for the relatively high bus resistance
Circuit Design Concepts for ESD Protection 93

Figure 4-7. Optimized widths of small rail clamp NMOSFET for 0.25 ȝm CMOS technology.
(Adapted from [10].)

networks, the ESD NMOSFET sizes are effectively saturated at about 21

pads. In case of low bus resistance networks, the ESD NMOSFET sizes are
effectively saturated at about 60 pads [10]. The calculated optimal I/O pad
ESD device sizes for the center I/O in the unterminated 61 I/O pads group,
for the full range of bus resistance values, are shown in Figure 4-7.
In this figure, rvdd and rvss values represent the incremental (pad-to-pad)
VDD and VSS bus resistances, respectively. A second set of optimizations
should be performed to determine the minimum width of the large rail clamp
NMOSFET in the power pads at both ends of the I/O group to effectively
terminate the network of distributed small rail clamps. One possible ap-
proach to do this analysis is to optimize the large rail clamp NMOSFET
width based on the ESD stress applied to a single I/O pad terminated on both
sides with large rail clamp circuits. The small rail clamp NMOSFET width
in the I/O pad can be fixed at the values determined from the previous
optimizations. Using this procedure, it was calculated the optimum large rail
clamp NMOSFET width for the full range of bus resistance values [10]. In
Figure 4-8, the optimum ESD device width is plotted as a function of rvdd for
the three different rvss values. From this figure, we can conclude that the
optimized large rail clamp width is slightly increased with decreasing of bus
resistance. The optimum large rail clamp NMOSFET width falls within a
narrow 1,800–2,000 µm range. The distributed rail clamp ESD protection
network was first implemented in 0.25 µm CMOS technology and currently
is widely used in Freescale Semiconductor for different products.
94 Chapter 4

Figure 4-8. Optimized widths of large rail clamp NMOSFET for 0.25 ȝm CMOS technology.
(Adapted from [10].)

3.1 Distributed Boosted ESD Networks

It is well known that for a given drain-to-source voltage (Vds), the conduc-
tance of an NMOSFET increases as the gate-to-source voltage (Vgs) is
increased. In the boosted ESD rail configuration [11], it was found a way to
apply a larger Vgs voltage to the gate of ESD MOSFET (M0) in a large
clamp circuit during the ESD event. Figure 4-9 shows a general schematic of
the boosted active MOSFET rail clamp configuration [12]. Note that there
are two changes in boosted configuration in comparison with the non-
boosted configuration. First, a very narrow Boost bus, with two parasitic bus
resistors R1 = 20 ȍ, was added. The Boost bus serves as a power supply bus
for the rail clamp trigger circuit. Note, that the drain of M0 remains con-
nected to VDD. Second, a relatively small (20 µm widths) VPNP protection
device (A2) in diode configuration was added in each I/O pad cell. The A2
device couples ESD current onto the Boost bus from the stressed I/O pad.
The primary ESD current path is through A1, M0 and B protection devices
and there is a very little current flow through A2 device in the stressed I/O
pad. Therefore, the voltage drop on the Boost bus at stressed I/O is only
about a diode drop below the I/O pad voltage. In addition, an insignificant
voltage drop is seen across the two Boost bus resistors R1. It was shown by
Stockinger et al. [12] that in boosted ESD rail protection network, the Vgs
voltage of rail clamp NMOSFET (M0) is ~2 u higher than the Vgs voltage of
rail clamp protection device in non-boosted ESD railprotection network at
the same Vds voltage. As a result, the rail clamp NMOSFET (M0) may
Circuit Design Concepts for ESD Protection 95

Figure 4-9. Boosted rail clamp ESD protection network. (Adapted from [12].)

pass significantly higher ESD current. For the same ESD robustness, M0
transistor can be smaller by 2.3 u in boosted ESD rail protection network in
comparison with non-boosted ESD rail protection network.
An obvious concern with the boosted ESD rail clamp configuration is
that the clamp NMOS M0 may be at increased risk of damage under the
Vgs > Vds boosted bias conditions. At an ESD event, the boosted ESD rail
protection network should be optimized to avoid the snapback operating
mode of M0 transistor and Vgs voltage should be not higher than the gate
oxide breakdown voltage for the given CMOS technology.
In case of distributed boosted ESD networks shown in Figure 4-10, the
single large boosted active MOSFET rail clamp (M0) can be split into
multiple, much smaller clamp NMOS devices M1, connected in parallel, and
distributed in each of the I/O and power supply pad cells for efficient,
uniform ESD protection. The incremental parasitic bus resistances R1, R2,
R3, and R4 for each bus are shown between each pad cell. In the boosted
and distributed ESD rail clamp network shown in Figure 4-10, the ESD bus
serves as the high current rail clamp anode bus and the VSS bus serves as the
cathode bus. Therefore, it is important that these two buses should be as
wide as possible to ensure the low resistance to ESD currents flowing around
the chip periphery. The Boost and Trigger buses do not move significant
current during an ESD event, and may, therefore, be much more narrow and
resistive. Each I/O pad cell in Figure 4-10 contains a small rail clamp
NMOSFET M1 and ESD diodes A1, A2, and B. A1 and A2 represent the
emitter-base junction diodes of the VPNP devices A1 and A2 shown in
Figure 4-9. The VSS pad cell contains the same ESD elements as the I/O pad
cells and also provides a convenient location for a remote ESD rail clamp
96 Chapter 4

Figure 4-10. Optimized boosted and distributed ESD network. (Adapted from [12].) Nodal
voltages are shown for 3.8 A ESD event applied at I/O1 with I/O2 grounded.

trigger circuit. This trigger circuit is defined as remote because, in addition

to the local NMOSFET M1, it also drives, via the Trigger bus, NMOSFET
devices M1 beyond the VSS pad cell. With remote trigger circuits, no local
trigger circuits are needed in the I/O pad cells, saving significant layout area.
Since there is very little IR voltage drop along the Boost and Trigger buses,
trigger circuits may be placed in some distance from the stressed pad and
some distance from the distributed clamp NMOS devices, which they drive.
In a non-boosted network, large IR voltage drops along the ESD bus make it
almost impossible to effectively use remote trigger circuits in this manner.
The ESD bus may be either a floating bus, not directly connected to any
external power supply, or may also serve as a positive power supply (i.e.
VDD) bus. For ICs, where the ESD bus is also a VDD bus connected to the
external VDD pad, VDD zaps positive to grounded I/O can be a problem. The
VDD pad has the same design as the VSS pad shown in Figure 4-10. Under
this zap condition, the large voltage drop across A2 can be seen at the trigger
circuit that can be damaged, since there is no voltage drop at A1. In addition,
it may not adequately protect the PMOSET of output buffer in the grounded
pad [12]. It is possible that the PMOSFET in the grounded I/O pad may be
stressed such that its drain voltage will be higher than the first breakdown
voltage (Vt1). To solve this problem, the large clamp NMOS devices (M0)
can be placed in each VDD pad cell, to locally compensate for the ESD
clamp performance reduction with hot zaps at VDD. In this case, the large
clamp NMOS devices (M0) can terminate a group of distributed small
rail clamp NMOS devices (M1), and can locally protect I/O buffers from
the ESD event at VDD pad.
Circuit Design Concepts for ESD Protection 97

4. CIRCUIT DESIGN FLOW FOR ESD

The goal of the ESD protection strategy is to avoid damage both due to
the high discharge currents and due to the extreme over-voltage in ICs. In
sub-100 nm CMOS technologies even an over-voltage of 2–3 V can cause
damage to the core devices. Hence, it is become a challenging task to simu-
ltaneously optimize a given ESD strategy under conflicting and restrictive
constraints of area, performance and ESD requirements. The restrictive
nature of these circuit constraints are reflected by the narrowing of ESD
design window which will be discussed subsequently in this section. In this
context, device simulations provide a rare insight into ESD device behavior
under high current and voltage conditions. Based on the process description,
the detailed analysis of the device behavior can be performed and design
improvements can be carried out in relatively short time.
In most modern designs a simple power domain arrangement is not any
longer used. For example, there are a large number of power domains for
core as well as for I/O circuitry that should be independently powered in
low power, mobile applications. Needless to say, there are several inde-
pendent VDD supplies. In addition, the VSS lines are decoupled to avoid
the cross-talk between the domains. As a result realizing effective and
efficient ESD becomes a challenging task. “How the ESD discharge cur-
rent can safely pass through an arbitrary combination of pins and power
domains?” becomes an important consideration. The evaluation only
pass/fail HBM/MM conditions for the ESD test structures, as it was in
past, can not be applied for VLSI designs in sub-100 nm technologies. Due
to the significantly thinner gate oxide of core transistors in these tech-
nologies, the CDM stress conditions become critical. The CDM ESD failures
occur typically in cores instead of IO blocks as it was observed in previous
CMOS technologies for HBM/MM ESD events. Often, CDM failures are
placed in interface regions of multi-power domains. Since in CDM stress
charges are localized inside of the cores, it’s extremely difficult to predict
their discharge path. Hence, the ESD design strategy must consider the real
discharge conditions at the chip level. However, this requires the deve-
lopment of a new IC level ESD simulation approaches.

4.1 Device Simulation and Calibration

One has freedom to choose from a large selection of ESD protection device
types. However, it depends on the process technology and the circuit
application. Nevertheless, all protection devices must satisfy certain condi-
tions concerning their I-V characteristics, which are described by the ESD
98 Chapter 4

Figure 4-11. ESD design window between the VDD and the gate oxide breakdown voltage of
the core circuit.

design window shown in Figure 4-11. Many of the ESD protection devices
operate in a so-called snap-back mode. The protection device should not
limit the normal operation of ICs. It means that its breakdown voltage (Vt1)
must be above the signal range (VDD) plus some noise margin and the
holding voltage (Vh) should be also higher than the VDD to avoid latch-up
susceptibility under normal operating conditions.
With CMOS technology scaling, the gate oxide thickness of MOSFETs
in core circuit is drastically reduced. As a result, the gate oxide breakdown
voltage is also diminished as depicted in Figure 4-12 and the width of the
ESD window for the core protection is shrunk to ~3–4 V for the 100 nm

Figure 4-12. Breakdown voltage of gate oxide for 100 ns duration stress pulses and supply
voltage as a function of CMOS technology generation. (Adapted from [4].)
Circuit Design Concepts for ESD Protection 99

CMOS technology node [4]. This ESD window must guarantee the safe
operation of core circuit at the full operational temperature range. Needless
to say, it requires a balancing of the protection device features, behavior
under nominal conditions, and a careful analysis concerning impact of
process fluctuations.

Figure 4-13. Representation of typical ESD development flow. (Adapted from [14].)

Moving from the given technology to the next one is a major challenge
for ESD development, since in general there can be no simple and smooth
transfer of protection concepts from the preceding technology. Traditionally,
ESD development flow uses quantitative process data at an early stage [13,
14]. Based on the detailed description of the process steps, commercial
process simulators can generate 2-D and 3-D structures, which include all
the information about materials, topology and doping profiles. Using the
simulated structures as an input for a device simulation, all essential ESD
parameters can be examined. The standard ESD design methodology based
on process and device simulations is shown in Figure 4-13. This methodology
can be implemented in companies that have their own fabs for chip pro-
duction, since they have the detailed information about the technology
100 Chapter 4

process [15]. However, the fabless companies are typically have limited
technology information and they can not properly perform process simu-
lations. In addition, they can not modify technology steps to optimize ESD
devices, because ICs technology is typically optimized for functional or core
transistors, but not for ESD devices. Hence, the ESD design methodology,
shown in Figure 4-13, can not be practically used by fables companies.
Therefore if the process simulations are not possible due to the limited techno-
logy information, the following strategy for ESD device calibration can be
used.
x At the first step, all available information from the technology file in a
given circuit simulation environment should be collected for the given
technology. For example, in case of ESD MOSFET it can be gate oxide
thickness (Tox), effective channel length (Leff), channel and poly-silicon
dopings, threshold voltage (Vth), leakage and drive currents at normal
operating conditions and device geometry parameters. These parameters
should be used to create the device structure in a device simulator and
calibrate it at normal operating conditions.
x For ESD devices, accurate high-current device models, which adequa-
tely capture the device breakdown and post-breakdown behavior, are of
particular interest. For MOSFET devices this means that simulation
models must match experimental triggering voltage (Vt1) and post-
snapback “on” resistance (Ron). Mixed-mode simulation is used to run a
snapback analysis of the device. Less well known device parameters
such as typically doping profile are adjusted to achieve a match to
available experimental data, which can be TLP I-V curve. This procedure
is generally known as inverse modeling.
x If sufficient agreement could not be achieved by previous steps, the
physical model coefficients in device simulator are adjusted as a final
calibration step.
This calibration strategy was used for design of ESD protection devices
(MOSFET and LVTSCR) implemented in 180 nm and 130 nm CMOS
technologies [16, 17]. The synthesized MOSFET structure based on the
reverse engineering approach is shown in Figure 4-14. The doping profile
parameters were adjusted to match electrical test data, which included I-V
characteristics at normal operating conditions and TLP data.
A mixed-mode (circuit-device) simulator was used to perform quasi-DC
snapback simulations. The obtained results were compared with TLP data as
shown in Figure 4-15. The TLP pulse duration was 100 ns and the rise time
(10–90%) was 10 ns. The excellent agreement is seen between measured
Circuit Design Concepts for ESD Protection 101

Figure 4-14. Synthesized ESD N-MOSFET structure (0.18 ȝm CMOS technology). (Adapted
from [16].)

Figure 4-15. ESD N-MOSFET (50 ȝm width): I-V TLP data and simulation results. (Adapted
from [16].)

data and simulation results. A good match was obtained for the key ESD
parameters such as triggering voltage (Vt1), holding voltage (Vh) and post-
snapback “on” resistance (Ron).
102 Chapter 4

4.2 Mixed-Mode ESD Simulation

The mixed-mode (device-circuit) simulation provides the capability for

in-depth studies of device level effects as well as analysis of larger circuits
with complex interactions within of I/O buffer circuits embedded in chip
environment. The mixed-mode simulations are widely used for the detailed
analysis of ESD events in relatively small (10–20 devices) circuits [14, 17,
18]. Each active device in these circuits is implemented as a Finite Element

Figure 4-16. I/O ESD protection circuits simulated in mixed-mode. (Adapted from [18].)

Figure 4-17. Mixed-mode simulation results of circuit shown in Figure 4-16 at 2 kV HBM
ESD stress. (Adapted from [18].)
Circuit Design Concepts for ESD Protection 103

(physical structure) model (FEM) optimized and calibrated in a previous

step of ESD design flow. The number of devices, which can be simu-
ltaneously simulated, is relatively small due to the significant increase of
simulation time with increase of number of active devices. Figure 4-16
represents the ESD protection circuit and I/O pre-buffer simulated in mixed-
mode. Each transistor in this circuit was implemented as a physical device
structure (see Figure 4-14) optimized and calibrated for 180 nm CMOS
technology.
The results of mixed-mode simulations at 2 kV HBM ESD stress are
depicted in Figure 4-17 [18]. In this figure, Vg_M0 is the gate voltage of
ESD transistor M0 and Vpad is the pad voltage at 2 kV HBM ESD stress
applied to the I/O pad.

4.3 Chip-Level ESD Simulation

Mixed-level circuit-device simulation is a powerful tool for the ESD stress

analysis of semiconductor products. Physical finite-element (FEM) level
models are utilized for MOSFETs and other devices involved in the high-
voltage high-current ESD event. Embedding these devices in realistic circuit
simulation environment including probe, chip and interconnect parasitics
(R, L, C) assures the required level of accuracy. CPU requirements (time and
memory) for such simulations depend on the total number of degrees of
freedom. Each circuit element contributes to this number, with FEM-level
devices contributing the most. On a modern PC, complete I/O buffer circuits
can be implemented with up to 20–30 MOSFETs modeled at the FEM level.
In certain cases it is possible to identify circuit blocks which are not
involved in the high-voltage high-current ESD event. Therefore, simulating
devices in these blocks on the physical FEM level is not necessary.
Analytical models such as the industry standard BSIM3 model can be used
instead to cover the low voltage range of operation. Some advanced ESD
simulators, for example SEQUOIA ESD [19], have the capability to include
a number of BSIM3 level devices along with FEM-level MOSFETs and
other circuit elements (R, L, C). Automatic voltage/current checks can be
included in low voltage circuit blocks to make sure that all BSIM3 devices
operate in the allowed current/voltage range.
The ability to combine FEM-level and BSIM3 MOSFET models in one
circuit greatly extends the applicability of mixed-mode analysis. Large circuits
with substantial numbers (100 s) of low voltage device and a number of
FEM-level devices can now be simulated on a regular PC. To make sure that
all device models are operating in their valid range, automatic current/voltage
monitors can be included in the circuit. If for example a peak voltage monitor
104 Chapter 4

indicates that a narrow core logic device is driven close to its triggering
voltage, this indicates potential device failure. This simulation can then be
repeated using a FEM-level model for the device in question to study its
behavior in greater detail.
Let’s consider an example where a mixed approach is possible with a
part of the circuit described using BSIM3 MOSFET models while some
circuit elements are subject to high-current high-voltage ESD stress and are
modeled on the FEM level. We compare results produced by this mixed
approach to a full FEM-level simulation. The example circuit is a gate-
grounded MOSFET (ggMOSFET) based transient clamp with a low pass
inverter circuit used to pull up the gate of the protection device for faster
triggering and enhanced ESD protection [20]. The ggMOS ESD protection
device is designed to enter impact-ionization induced snapback. It is
therefore simulated on the physical FEM-level. The inverter circuit on the
other hand is designed to provide a gate bias for the protection ggMOSFET
and should not conduct a large current. Under certain conditions the inverter
can be represented with BSIM3 MOSFET models.
To verify the validity of this hypothesis, two different simulations were
performed using: (a) full FEM models for all MOSFETs, and (b) BSIM3
models for the inverter and an FEM model for the ESD MOSFET (M10) as
shown in Figure 4-18. MOSFETs with a gate length of 0.25 ȝm and
triggering voltage of about 9 V (FEM model, grounded gate) were used. In
this figure, ESD MOSFET (M10) was implemented as a physical FEM
model and transistors M11 and M12 in CMOS inverter were created as a
BSIM3 models. Transient response of the transient ESD clamp circuit
(Figure 4-18) during a Human Body Model (HBM) discharge is controlled
by the RC time constant of the low pass filter C1, R6. If this time constant is
properly selected, it raises the gate potential of the ESD MOSFET clamp
long enough during the ESD pulse to help it absorb the ESD current. On the
other hand, the RC time constant must be small enough to not negatively
affect circuit performance. The choice of this time constant is therefore
critical for adequate circuit operation. Figure 4-19 shows the peak pad
voltage (VM2) at 2 kV HBM ESD stress as a function of (C1*R6) time for
two cases, when all transistors were implemented as a FEM model and a
mixed BSIM3-FEM model.
Both simulations show reasonably good agreement for larger time cons-
tants while higher discrepancy is observed for smaller time constants (C1*R6
” 2 ns). Practically, traditional transient MOSFET based ESD protection
circuits have the large RC network needed to trigger the clamp and keep it
in a conducting state for the entire duration of the ESD event, which is
~600–700 ns for the HBM ESD stress. Hence, the mixed BSIM3-FEM
Circuit Design Concepts for ESD Protection 105

model can be used for HBM ESD simulations for all practicalpurposes.
Note that the BSIM3 compact model of transistors for SPICE-like simu-
lations in TCAD environment can be extracted from the technology file
provided by the fab or BSIM3 model can be extracted from the physical

Figure 4-18. Transient ESD clamp circuit with FEM level transistor M10 and a BSIM3 level
inverter (M11, M12). (Adapted from [20].)

Figure 4-19. Peak pad voltage of transient ESD clamp circuit vs. (C1×R6) time calculated
using the full FEM model and the mixed BSIM3-FEM model. (Adapted from [20].)
106 Chapter 4

device model using automatic extraction tool embedded in some ESD/device

simulators, for example Sequoia ESD [19].
Simulation techniques are widely used for the development of ESD
protection on various levels reaching from process to circuit simulation.
However, due to the complexity of the required simulation the ESD simu-
lation of a complete IC is still a major challenge. Even under normal
operational conditions a full chip compact simulation is not applicable to
designs with 100 million gates or more. Beyond this, the ESD-relevant
models for the compact simulation are even more complex, including the
snapback behavior of ESD transistors and thermal effects. Fortunately, for
the analysis of the overall voltage drop in the power net during the ESD
discharge a very much simplified I-V characteristics can be used neglecting
the snapback mode. It was shown that all ESD devices operating in a
snapback mode can be descried by a bimodal I-V characteristic, where each
branch is monotonic as shown in Figure 4-20 [4, 15]. One of the states
reproduces the breakdown characteristic of the device without triggering the
bipolar transistor, i.e. without the snapback, the second state describes the
high current branch of the device after the snapback. Both characteristics
consist of a high-ohmic regime modeled by a linear I-V dependency, which
changes to a low-ohmic behavior (Rdiff and Rbd) beyond the breakdown
voltage (Vbd) and the holding voltage (Vh), respectively. In the standard
circuit simulators, both states of the bimodal characteristic are examined and
the worst case of ESD scenario is extracted, which is determined in
accordance with the given physical constraints. This approach avoids the

Figure 4-20. ESD devices and circuit are modeled either in the breakdown or snapback
branch of their I-V characteristic. The snapback mode is not modeled.
Circuit Design Concepts for ESD Protection 107

necessity to consider transient effects. It can be reasonable for HBM and

MM discharges, where the total current of the ESD event is a well-defined
by the external parameter. A damage is detected, if the critical current It2 or
the upper limit voltage of the ESD design window is exceeded. This method
was used to analyze the ESD robustness of a pad ring of a 300 pin IC. It was
simulated for 1,600 different stress combinations on a 360 MHz RISC
processor within 8 h [4].
In case of CDM stress, the ESD analysis is more complicated since the
discharge current is determined by the charge stored on the IC. This requires
the consideration of the capacitances of the supply networks and the package.
A transient analysis including the RC times of the different discharge paths
should be performed.

4.4 Test Chip Development

The robustness of ESD protection devices is very sensitive to layout. The

thermal damages of ESD protection structures usually come from current
crowding induced local over-heating stemming from layout discontinuities.
For example, the current crowding occurs at the corners and edges of
diffusion/metal layers. Therefore, layout is an extremely important for
realizing robust ESD protection circuits. Figure 4-21 shows the layout
examples of devices (single finger MOSFET on the top and multi-finger

Figure 4-21. The layout of ESD MOSFETs to avoid current crowing: the single finger device
shown on the top row and the multi-finger device shown on the bottom row. (Adapted from
[1].)
108 Chapter 4

MOSFET on the bottom) to avoid current crowing in the ESD device [1].
Unfortunately, layout issues of ESD protection devices can not be analyzed
using 2-D device simulators, which are typically used in ESD protection
circuit design flow. To investigate the impact of layout on ESD robustness,
the ESD test structures should be implemented in silicon. The layout design
guide for ESD protection devices was developed by SEMATECH [21].
Nowadays, the design of modern high performance digital and analog RF
circuits leaves very small window for ESD circuits design due to the high
sensitivity of the core of high speed digital and RF circuits to any parasitics.
The most critical components are the low noise amplifier (LNA) and the
power amplifier (PA) due to the high requirements on their RF performance.
To avoid the RF circuit performance degradation, the careful minimization
of the ESD device RC parasitics is required [22–24].
For example, a typical requirement on the total input parasitic capaci-
tance (Cpar) of a 2 GHz CMOS LNA is in the order of few hundreds fF.
The actual limiting factors are the required LNA gain and noise figure. Both
parameters are direct functions of Cpar and degrade when Cpar or the opera-
ting frequency increase. To estimate the impact of ESD parasitics on the
performance degradation of high speed digital and analog RF circuits,
the test circuits with ESD protection elements should be implemented in
silicon. The LNA with ESD protection elements can be used to verify the
ESD RC parasitics, as it shown in Figure 4-22. Note, that instead of shown
ESD protection elements other ESD devices can be used for RC paracitics
verification.

Figure 4-22. Common source LNA with added ESD protection within dotted boxes. (Adapted
from [23].)
Circuit Design Concepts for ESD Protection 109

In order to examine the impact of ESD RC parasitics on high performance

digital circuits, the test structure consisting of 40-stage ring oscillator (RO)
was proposed [25]. The effect of ESD parasitics is determined by the degra-
dation of operating frequency of ring oscillator due to the adding of ESD
protection elements. The general concept of this test structure is depicted in
Figure 4-23. For example, a 15-stage 4.7 GHz ring oscillator was imple-
mented in 180 nm CMOS process [26]. In this test circuit the dual-
directional NPNPN ESD structures [27] were used instead of ESD diodes.
The measurement data shown, that in single-load case where only one node
had ESD protection, a 50% clock speed reduction occurs due to the para-
sitic capacitances of ESD structures. It was found that optimized for 4 kV
HBM stress dual-directional NPNPN ESD structure has 90 fF of parasitic
junction capacitance and 29 fF of parasitic capacitance of Cu intercon-
nects [26].

Figure 4-23. The test circuit diagram with p+-nwell diode-based ESD protection network
designed around the core (ring oscillator) circuit.

For mixed-signal ICs, the analysis of digital noise coupling to analog and
design for its avoidance is very important. The sources of digital noise
coupling are capacitive coupling, coupling through the power supply net,
and coupling through the substrate. The noise is also generated through ESD
protection networks in a multiple power supply system, which has different
VDD for digital and analog blocks.
Diode-based ESD power networks are commonly used in many appli-
cations due to easy implementation and area efficiency. However, these
protection networks are not favored in view of noise margins needed for
circuit operation. To verify the relationship between noise margin and ESD
performance of diode-based power clamp circuits, the special test circuits
was developed [5], as shown in Figure 4-24.
110 Chapter 4

Figure 4-24. Test circuit diagram for measurement of PLL jitter under ground noise injected
through the ESD power protection circuit. (Adapted from [5].)

Test structure consists of digital switching noise generator, an analog

phase-locked loop (PLL) as noise monitor, and an ESD power clamp circuit
as a Power/Ground noise propagation path. A surge of current from VSSNS
through a protection diode circuit inductively induces voltage fluctuations in
VSSPLL. A protection diode circuit forms a return path between two inductors
on the VSSNS and the VSSPLL pins, which causes the effective potential of the
PLL ground to fluctuate and thus changes the output frequency and phase of
the voltage-controlled oscillator (VCO) integrated in PLL block. When
VSSNS is less than the turn-on voltage of the diode clamp, the jitter per-
formance of PLL block has a slight influence on noise magnitude due to
capacitive coupling. When the peak ground noise exceeds the turn-on volt-
age, the ground feed-through causes a significant increase of the jitter. From
experimental results, it was found that the statistical distribution of jitter
broadens as the ground noise becomes larger than the turn-on voltage of a
clamp circuit. Thus, a higher number of diodes should be used for better
noise margin [5]. However, the increasing the number of diodes raises the
“on” resistance of a forward-biased diode clamp, which degrades the ESD
performance.

4.5 ESD Measurements

The final step of circuit design flow for ESD protection is the ESD mea-
surements. ESD tests determine the electrical properties of integrated circuits
and their elements such as transistors, resistors and diodes at current levels
and time scales typical for ESD events, amps of current and nano-seconds of
time. The test method that has been almost universally adapted over the last
few years is the transmission line pulse (TLP) measurement. The detailed
description of TLP equipment and measurement technique was discussed in
Circuit Design Concepts for ESD Protection 111

Chapter 2. TLP measurements can be made on full circuits, in a way similar

to HBM and MM measurements, they can be made on sub-circuits like
input/output buffers or power supply clamps, or they can be made on in-
dividual circuit elements such as transistors or diodes [28]. Recent mea-
surements of “real HBM” events indicate that under dry conditions the rise
time is in fact much faster than the specifications for HBM testing [29]. For
humid conditions the “real HBM” rise time becomes longer. It is therefore
important that a protection scheme be able to function over a wide range of
rise times, both to cover the wide range of rise times of the specification but
also the wide range of real world rise times. TLP measurements can easily
vary the rise time and verify protection over a range of rise times. HBM
simulators are more limited. Due to equipment constraints, most high pin
count simulators have rise times about 8–9 ns. The flexibility of TLP
measurements allows the exploration of device performance over a wider
range on stress conditions. TLP measurements can be made on sub-circuits,
as already mentioned. As an example we consider a dynamically triggered
power supply clamp, shown in Figure 4-25 [28].

Figure 4-25. Schematic of dynamically triggered power supply clamp based on a large
NMOSFET.

Power supply clamps are an important part of any ESD strategy. They
are not only important for the protection of ESD stress between power
supplies and ground, but can help protect inputs and output buffers with the
use of steering diodes. Steering diodes are placed between Inputs/Outputs
and power/ground buses and are used to direct an ESD stress through a
power supply clamp. A TLP I-V measurement of a dynamically triggered
power supply clamp is shown in Figure 4-26. At low current the device
shows the expected linear behavior. At a little below 5 V, the I-V curve
shows an increase in conductivity. This is likely the onset of bipolar action
as the drain diode of large N-MOSFET reaches its avalanche point. This
112 Chapter 4

Figure 4-26. TLP I-V curve and leakage evaluation of power supply clamp. (Adapted from
[28].)

provides an additional conductivity mechanism. At about 6.7 A the leakage

increases dramatically and clamp is damaged by the high current.
Parameters extracted from the TLP measurements can be used to estimate
the ESD behavior and ESD robustness of developed protection network.
The obtained data can predict the triggering mechanisms such as bipolar
snapback, calculate voltage drops for various current levels and predict the
stress level at which device damage will occur. Generally, ESD test chip
should contain not only the ESD protection elements themselves, but also the
devices that constitute the output driver and the input receiver. Only when the
I-V characteristics of each of these components are compared, the effec-
tiveness of an ESD protection strategy can be determined.
The Human Body Model (HBM) and the Machine Model (MM) are the
general ESD test methods, which are also widely used for commercial ICs.
Generally, there are VDD, VSS and Pin-to-Pin ESD test modes, as shown in
Figure 4-27.
Since ESD charge may have positive or negative polarity, each test mode
should be performed twice. After I/O pins and power pins are tested by
ESD simulator, ESD robustness of the IC is decided by the worst case.
Most device manufacturers follow the general procedure defined by the
MIL-STD-883C method 3,015:
Circuit Design Concepts for ESD Protection 113

Figure 4-27. HBM and MM ESD test modes.

x Selection of Pin Combination: VSS Mode, VDD Mode, Pin-to-Pin Mode.

 In principle, all the pins are required to be stressed against every
other pin in turn, which is practically unfeasible.
 Thus a reasonable judgment must be made for the worst case of
pin-to-pin combination.
x Injection Pulses: Three positive and then three negative stress pulses with
pulse interval at least a 300 ms between consecutive zaps.
x ESD Pass Level: Worst Case ESD Performance.
x Test Sample Number: At least three samples in each Modes & Stress
Level.
The DC I-V curve after ESD zapping of each I/O, VDD and VSS pins is
compared with the DC I-V curve before ESD zapping, to fix any curve
shifting, which indicates that the ESD protection circuit is failed at the given
ESD stress level.
114 Chapter 4

5. SUMMARY

A good on-chip ESD protection network should have the following

characteristics: (1) fast triggering to avoid premature ESD failure due to
accidental turn-on of competing internal parasitic structure; (2) high cur-
rent handling capability, good heat dissipation capability, and low dis-
charging impedance to boost the ESD robustness; and (3) low parasitic
effects to minimize negative impacts on core circuits. All these ESD
features are critical for ESD protection design evaluation. ESD phenomena
include different coupling effects, such as thermal, process, device, circuit,
and layout issues. Starting from the sub-100 nm CMOS technologies, the
protection development goes much beyond the development of a specific
optimized protection element. A sophisticated protection network has to be
designed, which covers both the I/O circuit and the core region, where low
oxides thickness and low junction breakdown voltages lead to hard
constraints on the maximum voltage overshoot during ESD. In especially,
designs with multiple power supply domains will complicate the ESD supply
protection concept extremely. To achieve a good ESD robustness it will be
necessary to consider the ESD protection as integral part of the IC
development starting from the concept phase. To support this and to extract
the necessary data for an ESD optimization, the following steps of design
flow of ESD protection network should be performed:
x Process/Device simulation and calibration
x Mixed-Mode ESD simulation
x Chip-level ESD simulation
x Test chip development
x ESD measurements
Today, due to the narrow design window and the higher complexity of the
power supply concepts, the ESD protection becomes much more an overall
problem of the IC, which has to be considered right from the IC’s concept
phase. As the technology continue to progress deep into the sub-100 nm
range, process advances will be sure to have additional impact on ESD.
With the development of good ESD modeling tools these problems should
be predictable as well as solvable at the process development step. The
ESD requirements thus need to be a part of the technology definition from
the start.
Circuit Design Concepts for ESD Protection 115

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