Index

o o o o o o o o Background Equalizer Pre-emphasis Continuous-Time Linear Equalizer Decision Feedback Equalizer Digital Equalizer Adapatation Case study - LE+DFE - Equalizer+CDR - Digital EQ + ADC

Background
o Todays High-Speed Links - Todays applications require data to be transmitted in Gbps range, often in unfriendly environment - Channels no longer look ideal Inter-Symbol Interference(ISI), Reflections and cross-talks - Needs wide bandwidth for high speed signaling by equalization techniques - Need more circuits to compensate them Equalizers, redundancy encoders/decoders, etc.

Background
o Band-limited Channels - Causes the high-frequency signal content to be attenuated much more severely than the low-frequency content

Background
o High-Speed Link Architecture with Equalization - Consists of Serializer/Deserializer, Equalizer, PLL and CDR - Most channels are low pass filter

Equalizer
o Equalization - Boost high-frequencies relative to lower frequencies (to perfectly counter the attenuation at each freuency) - Ideal equalizer has a transfer function that is the inverse of the channel transfer function, making it a high-pass filter - This is expressed mathematically as Heq(f)=H-1channel(f)

Equalizer
o Equalizer Design Tradeoffs

[1] S. Gondi, A 10-Gb/s CMOS Adaptive Equalizer for Backplane Applications, ISSCC, 2005 6

Pre-emphasis
o TX FIR filter pre-distorts transmitted pulse in order to invert channel distortion at the cost of attenuated transmit signal(de-emphasis) o Use EQ technique at Transmitter side o Attenuates low-frequencies(de-emphasis) - Need to be careful about output amplitude : limited output power o Challenge : - EMI problem and How to set EQ weights?(unknown channel loss)

Pre-emphasis
o Two-Tap FIR Filter o ISI gets reduced by boosting transition bits

Pre-emphasis
o Transmitter with 4-tap FIR filter

[2] M. Sorna, A 6.4Gb/s CMOS SerDes Core with Feedforward and Decision-Feedback Equalization, ISSCC, 2005 9

Pre-emphasis
o Implementation - Adds 1-bit delayed to Output driver - Compensation gain is digitally controlled(externally)

10

Pre-emphasis
o Implementation - Compensation gain boosts up to 9dB (3-bit digital control externally)

11

Continuous-time Linear EQ
o Feed-Forward Equalizer(FFE) - Widen bandwidth(BW) to Nyquist of data rate with boosting high frequency component o Challenge : poor SNR property - Causes high frequency noise boosting

12

Continuous-time Linear EQ
o Linear RX equalizer - Doesnt discriminate between signal, noise, and cross-talk - Signal-to-distortion (ISI) ratio is improved - SNR(Signal-to-Noise Ratio) is worse

13

Continuous-time Linear EQ
o Input amplifier with RC degeneration can provide frequency peaking with gain at Nyquist frequency - Cancel both precursor and long-tail ISI o Potentially limited by gain-bandwidth of amplifier o Tune degeneration resistor and capacitor to adjust zero frequency and 1st pole which sets peaking and DC gain o Challenge : - Sensitive to PVT variations and can be hard to tune - Amplifier must be designed for input linear range (Often Tx Equalizer provides some low frequency attenuation)

14

Continuous-time Linear EQ
o RC source degeneration structure has a good linearity

15

Continuous-time Linear EQ
o Implementation-(I) - 2nd cascaded capacitance degeneration filter(up to 10dB boosting) - Capacitor value is selected 3-bit digital signal externally

2.4Gbps EQ(10dB), 0.35m CMOS

16

Continuous-time Linear EQ
o Implementation-(II) - 3rd cascaded RS degeneration with Negative capacitance(up to 25dB) - Varactor(cap) is controlled by adaptive algorithm

EQ unit cell - 5Gbps EQ(25dB), - 0.13m CMOS RF

17

Decision Feedback EQ
o Non-Linear Equalizer - Just subtract post-cursor ISI - Requires a feed-forward equalizer for precursor ISI o DFE cancels ISI without amplifying noise or crosstalk - Suitable for noisy backplane o Error Propagation in DFE - Decision errors at the output of the slicer can cause a corrupted estimate of the post-cursor ISI by the post-cursor equalizer

18

Decision Feedback EQ
o Symbol Response for FFE & DFE

19

Decision Feedback EQ

1UI > tD = tc2q + tmulti + tsum + tsetup

Decision Feedback EQ

o Make decisions for -/+ and MUX selects correct decision o Loop-Unrolling(speculation) DFE is preferable for Low-Power design because No High-Speed Analog Feedback Path
21

Decision Feedback EQ
o If we dont compromise speed at all, - Power and area increase exponentially

[3] Yasuo Hidaka, A 4-Channel 10.3Gb/s Backplane Transceiver Macro with 35dB Equalizer and Sign-Based ZeroForcing Adaptive Control, ISSCC, 2009 22

Digital EQ
o A common trend in digital communications has been the increasing use of digital signal processing o A digital DFE equalizer offers advantages over traditional analog DFE equalizer approaches - Flexibility of Design - Ease of programmability - Consistency of Performance - Extensibility for different channel characteristics, and robustness to process variations. - Realizing benefits from advancing process technology - Improved production test and debug diagnostics o challenge : requires ADC to convert digital domain (large power dissipation, large area, high speed operation)
23

Digital EQ
o Digital filters using look-up tables for receive EQ. o All post-cursor ISI can be more efficiently cancelled with DFE

24

Adaptation Algorithm
Two basic techniques for setting Equalizer Coefficients o Set and forget - Based on manual channel measurement - Calculate on basis of a single-bit-response o Adaptation - Use an optimizing algorithm to find minimum - Optimize multiple variables at once - Adapt once or continuously adaptive

25

Adaptation Algorithm
o Least Mean Square(LMS) Algorithm - Maximizes Vertical Eye opening - Minimizes =E[e2] at center of eye o Jitter Measurement(Zero-Forcing) Algorithm - Maximizes Horizontal Eye opening - Minimize ISI at the zero crossings - Minimizes =E[e2] at zero crossings

26

Adaptation Algorithm

27

Adaptation Algorithm
o Conventional Continuous-time Equalizer - Only one adaptation loop for high-frequency boosting

28

Adaptation Algorithm
o Joint adaptive equalizer - Dual loop architecture to balance low-frequency and high-frequency parts

[4] J. S. Choi, A 0.18-um CMOS 3.5-Gb/s Continuous-Time Adaptive Cable Equalizer Using Enhanced LowFrequency Gain control Method, JSSC, 2004

29

Adaptation Algorithm
o Two feedback loops - High-frequency boost control in the equalizer filter - DC level control in the comparator

[1] S. Gondi, A 10-Gb/s CMOS Adaptive Equalizer for Backplane Applications, ISSCC, 2005 30

Adaptation Algorithm
o ISI Detection - Data-dependent ISI detection algorithm - measures minimum bit width when 1101 or 0010 pattern

[5] Yan-Bin Luo, A 250Mb/s-to-3.4Gb/s HDMI Receiver with Adaptive Loop Updating Frequencies and an Adaptive Equalizer, ISSCC, 2009 31

Case study I
o Combined LE + DFE structure - Linear Equalizer(LE) to cancel long-tail ISI - 1-tap speculative DFE to achieve fastest speed

LE cancels long-tail ISI except 1st post-cursor ISI

1-tap speculative DFE cancels 1st post-cursor ISI

[3] Yasuo Hidaka, A 4-Channel 10.3Gb/s Backplane Transceiver Macro with 35dB Equalizer and Sign-Based ZeroForcing Adaptive Control, ISSCC, 2009 32

Case study I
o Advantages - Fastest achievable speed - Low power and small area - High capability of loss compensation - Low noise enhancement at high frequency o challenge - Adaptive control

[3] Yasuo Hidaka, A 4-Channel 10.3Gb/s Backplane Transceiver Macro with 35dB Equalizer and Sign-Based ZeroForcing Adaptive Control, ISSCC, 2009 33

Case study II
o Merged Equalizer+CDR architecture - Receiver needs to perform CDR as well as equalization - EQ and CDR output are used for LMS algorithm

[6] Chih-Fan Liao, A 40Gb/s CMOS Serial-Link Receiver with Adaptive Equalization and CDR ISSCC, 2008 34

Case study III

[7] M. harwood, A 12.5Gb/s SerDes in 65nm CMOS Using a Baud Rate ADC with Digital RX Equalization and Clock Recovery, ISSCC, 2007 35

References
[1] S. Gondi, A 10-Gb/s CMOS Adaptive Equalizer for Backplane Applications, IEEE, ISSCC, 2005 [2] M. Sorna, A 6.4Gb/s CMOS SerDes Core with Feedforward and Decision -Feedback Equalization, IEEE, ISSCC, 2005 [3] Yasuo Hidaka, A 4-Channel 10.3Gb/s Backplane Transceiver Macro with 35dB Equalizer and Sign-Based Zero-Forcing Adaptive Control, IEEE, ISSCC, 2009 [4] J. S. Choi, A 0.18-um CMOS 3.5-Gb/s Continuous-Time Adaptive Cable Equalizer Using Enhanced Low-Frequency Gain control Method, IEEE, JSSC, 2004 [5] Yan-Bin Luo, A 250Mb/s-to-3.4Gb/s HDMI Receiver with Adaptive Loop Updating Frequencies and an Adaptive Equalizer, IEEE, ISSCC, 2009 [6] Chih-Fan Liao, A 40Gb/s CMOS Serial-Link Receiver with Adaptive Equalization and CDR, IEEE, ISSCC, 2008 [7] M. harwood, A 12.5Gb/s SerDes in 65nm CMOS Using a Baud Rate ADC with Digital RX Equalization and Clock Recovery, IEEE, ISSCC, 2007 [8] Stephen H. hall, Advanced Signal integrity for High-Speed Digital Designs, Wiley, 2009 36