Digital Phase Locked Loop

Digital Phase Locked Loop (DPLL)
1. Introduction
A Phase Locked Loop is a closed-loop control system that is used for the purpose of
synchronization of the phase and frequency with that of an incoming signal. There are
basically three components in a PLL; the Phase and Frequency detector (PFD), the loop filter
and the Voltage Controlled Oscillator (VCO). The VCO is the heart of any PLL. The
mechanism by which this VCO operates decides the type of the PLL circuit being used.
Fig 1: Basic Block diagram of PLL[3]

The analog PLL or the Linear PLL has been in use since a long time. It basically uses
a multiplier circuit for serving the purpose of the PFD and a first order filter for the low pass
filter and a typical analog VCO. analogue PLLs suffer from major drawbacks related to
their analogue nature. These include aging and temperature drift effects, the sensitivity to
component tolerances and operating conditions. In an attempt to combat the aforementioned
drawbacks, Digital Phase-Locked Loops (DPLLs) were introduced in the 1970s.
DPLL is a modified PLL (phase locked loop) which is designed using all digital block
for the processing. Its operation is analogous to that of the PLL. DPLLs offer several
advantages over analog PLLs, particularly for microprocessor applications. DPLLs generally
have shorter lock times, and they are easier to integrate with digital components on mixedsignal integrated circuits (ICs). They also consume less area on ICs than analog PLLs,
reducing die sizes and production costs[2]. As fabrication technologies improve, DPLLs will
continue to shrink, whereas analog PLLs will not.
2. Description of DPLL
The basic block of the ADPLL consists of a Digital Phase detector, Digital controlled
oscillator, Digital loop filter [1]. There three main parts of the DPLL same as that of the PLL
but they are designed and constructed differently for the fact the input signal dealt by the
different system, and FPGA is digital.
Fig 2: Basic Block diagram of DPLL[1]

Digital phase-locked loops can be classified into two major categories depending
on the type of sampling process.
1. Uniform sampling DPLLs
2. Non-uniform sampling DPLLs
The DPLLs can be also classified according to the mechanization of the
phase detector into five types as follows
1. The flip-flop DPLL (FF-DPLL)
2. The Nyquist-rate DPLL (NR-DPLL)
3. The lead-lag DPLL (LL-DPLL), a.k.a binary-quantized DPLL (BQ-DPLL)
4. Exclusive-OR DPLL (XOR-DPLL)
5. Zero-crossing DPLL (ZC-DPLL)
Types 2 above belongs to uniform sampling, while the others belong to nonuniform
sampling.
Here an Exclusive-OR DPLL is implemented.
3. Implemented DPLL
An exclusive-OR gate as a phase detector [17]. K-counter as a digital filter and an incrementdecrement (I/D) counter with a divide-by-N counter as a DCO.
Fig 3: Block Diagram of Implemented DPLL [1]

The phase error detector (PED) compares the phase of the input signal, in,with that of the
loop output, out, and gives an error signal d defined as follows
d = Ko e
where Ko is the gain of the PED and e = in out.
The output of the PED can also be expressed as follows
d = (%H %L)/100(cycles)
where %H and %L represent percentage high and low logic levels, respectively, during
one cycle. Hence d (in cycles) varies between +1 and -1. When e = 1/4 cycle (/2 rad) then
%H = %L, hence d = 0 2 (mod 2) = 1 cycle, therefore Ko = 4. The output of the phase
detector controls the operation of the K-counter which consists of two divide-by-K counters,
an up-counter and a down-counter, both triggered by a clock of rate Mfo, where fo is the
center frequency and M is an integer.
The output C of this counter, which is connected to the increment input (INR) of the
I/D counter, generates a pulse when the K-counter ends an up cycle, while the borrow
output B which is connected to the decrement input (DCR) generates a pulse on the end of a
down cycle. A pulse applied to the INR input adds 1/2 cycle to the I/D output, while a
pulse on the DCR input deletes 1/2 cycle. The I/D counter clock runs at a frequency of
2Nfo, where N is the modulus of the divide-by-N counter that follows the I/D counter. The
I/D counter is merely a divide-by-2 counter if no INR or DCR pulses are applied, hence
its output frequency can be given by
F = Nfo + 1/2[KoeMfo/K] (Hz) = Nfo + 2eMfo/K.
The factor 1/2 above came from the fact that the I/D counter adds or deletes half a cycle when
INR or DCR pulses are applied, respectively. The output frequency can be expressed as
fout = fo + 2eMfo/(KN) (Hz).
Since d varies between +1 and 1, e varies between +1/4 and 1/4 cycles, hence lock
range can be derived as follows
= |fin fo|max
= |fout fo|max
= Mfo/(2KN)
and lock range = 2 = Mfo/(KN) . There exists a phase error between the input and the output
signals even at locking, i.e. when fout = fin, which is given by
e = KN(fin fo)/(2Mfo)
4. VHDL Program code

DPLL.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DPLL is
port(v1,kclk:in std_logic;v2:inout std_logic);
end entity;
architecture struc of DPLL is
component kcounter is
Port ( kclk,up_dn : in STD_LOGIC;
c,b: out STD_LOGIC );
end component;
component dco is
port(dec,inc:in std_logic;
CLKout:out std_logic);
end component;
component xordpll is
Port ( a,b : in STD_LOGIC;
c: out STD_LOGIC );
end component;
signal temp1:std_logic:='0';
signal xor_out:std_logic:='0';
signal c,b:std_logic:='0';
begin
xordpll1:xordpll port map(v1,v2,xor_out);
pd1: kcounter port map(kclk,xor_out,b,c);
dco1:dco port map(b,c,temp1);
v2<=temp1;
end architecture;
pd.vhd
library IEEE;
entity xordpll is
port(a,b:in stdlogic;c:out std_logic);
end entity;
architecture beh of xordpll is
begin
c<=a xor b;
end architecture;
kloopcounter.vhd
library IEEE;
entity kcounter is
Port ( kclk,up_dn : in
STD_LOGIC;
-- input clock
c,b : out STD_LOGIC); -- direction of counter (up or

down)
end kcounter;
architecture Behavioral of kcounter is
--signal clk_div : STD_LOGIC_VECTOR (3 downto 0) := X"0";
signal up_count
: STD_LOGIC_VECTOR (7 downto 0) := X"00";
signal dn_count
: STD_LOGIC_VECTOR (7 downto 0) := X"00";
begin
-- clock divider
--process (CLK)
--begin
-- if (CLK'Event and CLK = '1') then
-- clk_div <= clk_div + '1';
--end if;
--end process;
-- up/down counter
process (kclk,up_dn)
begin
if(up_dn='1') then
if (kclk'Event and kclk= '1') then
--if (DIR = '1') then
up_count <= up_count + '1';
-- counting up
--elsif (DIR = '0') then
--count <= count - '1';
-- counting down
--nd if;
c<= up_count(7);
end if;
elsif (up_dn='0') then
if (kclk'Event and kclk= '1') then
--if (DIR = '1') then
dn_count <= dn_count + '1';
-- counting up
--elsif (DIR = '0') then
--count <= count - '1';
-- counting down
--nd if;
b<= dn_count(7);
end if;
end if;
end process;
end Behavioral;
dco.vhd
library IEEE;
use IEEE.math_real.ALL;
entity dco is
port ( dec,inc: in std_logic;
CLKout:out std_logic);
end dco;
architecture arch of dco is
--signal counter: integer:=0;
signal temp : std_logic:= '1';
begin
process
variable N : integer := 5;
variable T : time := 30 ns;
variable control : std_logic_vector(1 downto 0);
begin
control:=dec&inc;
if(control="10") then
T:=T+50 ns;
for i in 0 to N loop
temp<=not temp;
wait for T;
temp<=not temp;
wait for T;
end loop;
--end if;
elsif(control="01") then
T:=T-50 ns;
temp<=not temp;
wait for T;
temp<=not temp;
wait for T;
--N:=N-2;
end loop;
T:=T;
temp<=not temp;
wait for T;
temp<=not temp;
wait for T;
--N:=N-2;
end loop;
T:=T;
temp<=not temp;
wait for T;
temp<=not temp;
wait for T;
--N:=N-2;
end loop;
end if;
clkout<=temp;
end process;
end arch;
5. References
1. Digital Phase Lock Loops, Architectures and Applications by SALEH R. AL-ARAJI
ZAHIR M. HUSSAIN and MAHMOUD A. AL-QUTAYRI, Springer publications.
2. S. Walters and T. Troudet, Digital Phase-Locked Loop with Jitter Bounded, IEEE
Transactions on Circuits and Systems, Vol. 36, No. 7, July 1989.

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Digital Phase Locked Loop (DPLL)

Fig 1: Basic Block diagram of PLL[3]

Fig 2: Basic Block diagram of DPLL[1]

Fig 3: Block Diagram of Implemented DPLL [1]

4. VHDL Program code

c,b : out STD_LOGIC); -- direction of counter (up or

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