PCB design course & checklist

Michael Dunn - October 13, 2013

Do you design or define PCB layouts? If so, what rules and checks do you have in place to make sure
your results are... optimal?

Over the years, I've created a PCB design checklist to keep me out of trouble. I share these nuggets
with my layout person as required. Allow me to share some with you.

Starting out
The first thing I always say is "Do not let the tools dictate the board. Imagine how the board should
be, then implement it. If it's too difficult, consider new tools. But still implement it." I think that's
self-explanatory.

Planning is the critical first step. Plan a stackup. Plan the part placement. I'm sure you can chime in
with more.

In my book, stackup is almost an art. There are so many dimensions to consider, and some always
conflict. Reduce cost by minimizing layers, but don't go so far that it takes an extra month to lay out
the board, SI suffers, or you just can't fit all those parts into the space allotted. You usually want to
keep the layout balanced around the center of the stack. This minimizes warpage, which is a really
bad thing when you have large SMT components.

Try to have your board fab team selected before you start. They can answer general and DFM-
related questions and help you get your controlled-impedance traces right. The fab will almost
always make slight adjustments to your controlled-impedance traces to compensate for their
processes. The tighter your design is, the more you'll have to concern yourself with this.

Make sure all special requirements are spelled out, whether in documentation or as part of the
schematic. These can be things like high-current nets, thermal sinks, length matching, controlled
impedance... but I'm getting ahead of myself. We'll get to some of those in the high-speed area.
Sometimes you can draw a schematic to hint at the required layout. A classic example is a single-
point ground node. Of course, this only works if your board designer knows to look at the schematic
and can understand your notations!

On any design that's even approaching high-speed, I always insist on a good density of ground vias
sprinkled throughout the board, so that a good scope-probe ground is always available, no matter
where you're probing. These should be circled on both sides for easy identification. Hell, they should
glow in the dark.

I'm a great fan of flooding – on lower-speed double-sided boards, at least. Flooding unused areas
with ground (and power sometimes) is a great way to improve power quality. It can improve etch
consistency and reduce coupling, and it is a good idea environmentally – there's that much less
copper to be eaten away.

A similar concept is thieving, which is often used on higher-speed multilayer boards. Here, empty
areas are filled, not with a solid flood, but with a pattern of dots, a grid, or something similar. This
helps maintain an even copper density over the layer, which again helps with warpage. Given the
concerns I've read about floating islands on high-speed boards (leading to coupling or a resonant
patch), dots are probably better than grids.

High speed
Once again, planning plays a critical role. Where will all your critical nets live in the stackup? What
impedances are required? Do I have enough layers to route them all cleanly?

I'm sure everyone knows never to cross a plane gap with a high-speed signal. But consider this
situation. A trace runs between a ground plane and a power plane. However, the power plane is cut
up – it handles several different voltages. What do you do?

When I first ran into this, I intuitively felt that, if the ground plane was significantly closer to the
signal layer than the power plane, you could cross power gaps without much of a problem. I played
with a stackup editor to see how far the power plane would have to be to stop having much effect on
trace impedance. Sure enough, this provided good SI. I later read an article by SI guru Eric Bogatin
that covered this exact situation. He said the split plane should be at least four times farther from
the signal than the reference plane.

"Impedance coupons" (test traces) should always be requested from the board shop. This way,
there's never any doubt that your boards are within spec. And definitely enlist the shop's guidance if
you have multiple impedances on your PCB.

Avoid vias as much as possible, though there are ways to impedance-match vias to the trace. Make
sure your layout tool places pads only on the required layers, and consider blind/buried vias. If a
signal changes reference planes when passing through a via, add an adjacent ground via. If one of
the reference planes is power, decouple the power at that point.

High-speed nuggets

● Consider via-in-pad. Though this adds cost, total cost may be reduced if you can eliminate a couple
of layers.
● Remove planes (and traces) as required – on edge connectors, for example, or under pads and
components that need minimal capacitance.
● Consider power/ground plane pairs placed as closely as your board shop can manufacture. This
provides great distributed high-frequency decoupling capacitance.
● This may be extreme, but I keep silkscreen legend off very high-speed traces. And make sure
production won't stick labels there!
● I bury clock traces whenever possible. This provides a significant EMI improvement over
microstrip. If you can't, surrounding the clock trace with well grounded shield traces may have a
similar effect. Remember to compensate for the impedance change.
● Route with curves, not angles.
● Minimize power inductance by placing power layers closest to the side where the most critical
components using that voltage are.
● For the same reason, I usually place ground layers at L2 and L(n-1).
● Ground planes should extend beyond the power plane and trace area to maintain proper
impedances and reduce emissions.
● Add ground stitching vias wherever the natural via density is low.

Diff pairs, EMI, decoupling...

So far, we've looked at PCB basics and high-speed layout issues. Let's continue with the high-speed
thread, diff-pairs, and decoupling.

One more nugget comes to mind: Very high-speed traces can benefit from being rotated off-axis to
decouple them from the board's fiberglass weave. Remember, glass-epoxy boards actually have
woven fiberglass in them. Trace characteristics can vary slightly depending on where they are
situated relative to the weave. Routing a trace 10 to 45 degrees off-axis will tend to average out this
effect.

Differential pairs
Through experimentation with impedance planning software, I discovered how diff-pair impedance
versus geometry has areas of higher and lower sensitivity. Try it yourself. I'm always sure to design
my pairs such that they're in a low-sensitivity region of the curve, so that small manufacturing
variations don't result in out-of-spec impedances.

If a diff pair isn't straight, it should alternate left and right bends. If this is not possible, small
equalization kinks should be placed at each bend to keep the two signals aligned.

One reads of tightly and loosely coupled pairs. I don't know if there's an exact definition of the
dividing line between the types. I tend to prefer loosely coupled; insist on them, in fact, if the pair is
"pseudo-differential," where the two signals might not switch in perfect synchrony (well, as perfect
as matters). This means that each line has half the impedance of the pair. On the other hand, the
lines of a tightly coupled pair have a higher single-ended impedance – maybe 60% of the pair.

Decoupling
Traces to decoupling caps should be as short and wide as possible. Via-in-pad is ideal. If not, then
putting both vias on the sides of the pads instead of the more typical ends reduces the ESL. Even
better: two vias per pad, one on each side.

Decoupling effectiveness can also be increased by using better caps: 0204 caps (as opposed to 0402)
for example have their contacts on the long edges, not the short ones, which reduces ESL. So-called
"X2Y" caps (available from several manufacturers) also greatly improve high-frequency performance,
and also find use as well balanced pairs for common-mode filtering.

Try to place caps on the side of the board closest to their voltage plane. Via length can easily
become the dominant HF limitation.

Determine the decoupling style best suited to each component. Decouplers are most commonly
routed directly to the planes. Sometimes though, a "feedthrough" approach might work better,
where the power-plane via connects to one side of the cap's pad, and a trace connects the other side
of the pad to the load. This acts as a tiny LC filter and affords some isolation to the load. In one
instance, the datasheet for a part I was using even recommended doing this on the ground side, but I
have some doubts about that! Still, I did follow their recommendation.
Let's conclude with an assortment of tips, and a quick look at EMI.

Odds and ends

If possible, run your finished board through an SI simulator. I've used HyperLynx. Altium Designer
has one built in. For starters, this will alert you to potential crosstalk problems. What software have
you used?

Most people will tell you to always have a solid ground plane. After all, careful component layout can
do a pretty good job of localizing noise. But adding the occasional slot can further improve this
isolation if done correctly. I've used the technique with power supply sections, analog areas, and
sensitive high-frequency receivers.

Shield or guard sensitive nets and components. Don't forget to think in three dimensions!

Thermal vias sink heat away from components and into the planes. If they need to be placed in the
thermal pad copper, you'll want to ensure the solder doesn't drain out the holes! Vias can be capped
or copper-filled to prevent this. Copper-filling also improves thermal conductivity.

Speaking of thermal pads, it's a good idea to "window" the paste mask (add a grid to reduce solder
coverage to about 75 percent). This prevents the component from floating up on a puddle of solder,
rendering all connections but ground floating. An assembly house will generally do this if you give
them a solid paste mask, but I'd rather be certain and do it myself.

EMI
If you have connectors going to the outside world, EMI possibilities are multiplied. One technique to
reduce emissions is to have separate chassis and circuit grounds. The metal connector shells are
soldered to a chassis ground plane. This can be on the same layers as the circuit ground planes – you
don't want the chassis plane to overlap with any circuit planes. What about the signals? If possible,
run them through ferrites, CM chokes, or similar filtration.

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These filter components can straddle the gap between the planes. Depending on the signals, you
might also hang caps from them to chassis ground. Even your signal grounds should get this
treatment. There shouldn't be any unfiltered traces overlapping chassis ground, unless it's an I/O
signal that isn't amenable to such treatment (in which case you'll probably have to extend the circuit
ground plane right up to the connector). ESD protection components can also live on the chassis
ground plane.

PCB mounting holes can all be connected to the chassis ground plane or left floating. Should you
connect circuit and chassis grounds together in any way? I've often seen a resistor or capacitor
between them, or a parallel combination. And I've read various opinions of what is best. It may be
safest to leave room for both, and determine what works best empirically.

OK, that concludes my checklist. Please chime in with some of the tips and techniques you use to
make good boards. EMI experts, in particular, I'm sure I've left lots of EMI gaps to be filled.

Also see:

● PCB Technology
● Analog Fundamentals: High-Speed PCB Design
● Review: Right The First Time, by Lee Ritchey
● PCB layout considerations for non-isolated switching power supplies
● A Practical Guide to High-Speed Printed-Circuit-Board Layout
● PC boards: Materials and processing are now a hot technology
● Power-integrity simulation keeps your planes perfect, part 1
● Selecting PCB materials for high-frequency applications
● Via spacing on high-performance PCBs
● DesignCon SMEs: Tough Path to 25G+ High-Speed Signals

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