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DRV8812
SLVS997G – OCTOBER 2009 – REVISED OCTOBER 2015

DRV8812 Dual-Bridge Motor Controller IC

1 Features 3 Description
•
1 8.2-V to 45-V Operating Supply Voltage Range The DRV8812 provides an integrated motor driver
solution for printers, scanners, and other automated
• 1.6-A Maximum Drive Current at 24 V and equipment applications. The device has two H-bridge
TA = 25°C drivers, and can drive a bipolar stepper motor or two
• Dual H-Bridge Current Control Motor Driver DC motors. The output driver block for each consists
– Drive a Bipolar Stepper or Two DC Motors of N-channel power MOSFET’s configured as full H-
bridges to drive the motor windings. The DRV8812 is
– Four Level Winding Current Control capable of driving up to 1.6-A of output current (with
• Multiple Decay Modes proper heatsinking, at 24 V and 25°C).
– Mixed Decay A simple parallel digital control interface is compatible
– Slow Decay with industry-standard devices. Decay mode is
– Fast Decay programmable.
• Industry Standard Parallel Digital Control Interface Internal shutdown functions are provided for over
• Low Current Sleep Mode current protection, short circuit protection, under
voltage lockout and overtemperature.
• Built In 3.3-V Reference Output Small Package
and Footprint The DRV8812 is available in a 28-pin HTSSOP
• Protection Features package with PowerPAD™ and in a 28-pin QFN
package PowerPAD™ (Eco-friendly: RoHS & no
– Overcurrent Protection (OCP) Sb/Br).
– Thermal Shutdown (TSD)
– VM Undervoltage Lockout (UVLO) Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
– Fault Condition Indication Pin (nFAULT)
HTSSOP (28) 9.70 mm x 4.40 mm
DRV8812
2 Applications VQFN (28) 5.00 mm x 5.00 mm

• Automatic Teller Machines (1) For all available packages, see the orderable addendum at
the end of the datasheet.
• Money Handling Machines
• Video Security Cameras
• Printers
• Scanners
• Office Automation Machines
• Gaming Machines
• Factory Automation
• Robotics
Simplified Schematic
8.2 V to 45 V

PHASE DRV8812
+

ENBL 1.6 A M
Controller

Decay Mode Stepper

Stepper
Current Lvl Motor + -
Driver
nFAULT
1.6 A
Current
Control

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8 Application and Implementation ........................ 13
2 Applications ........................................................... 1 8.1 Application Information............................................ 13
3 Description ............................................................. 1 8.2 Typical Application ................................................. 13
4 Revision History..................................................... 2 9 Power Supply Recommendations...................... 16
5 Pin Configuration and Functions ......................... 3 9.1 Bulk Capacitance .................................................... 16
9.2 Power Supply and Logic Sequencing ..................... 16
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5 10 Layout................................................................... 17
6.2 ESD Ratings.............................................................. 5 10.1 Layout Guidelines ................................................. 17
6.3 Recommended Operating Conditions....................... 5 10.2 Layout Example .................................................... 17
6.4 Thermal Information .................................................. 5 10.3 Thermal Consideration.......................................... 18
6.5 Electrical Characteristics........................................... 6 11 Device and Documentation Support ................. 19
6.6 Typical Characteristics .............................................. 7 11.1 Third-Party Products Disclaimer ........................... 19
7 Detailed Description .............................................. 8 11.2 Community Resources.......................................... 19
7.1 Overview ................................................................... 8 11.3 Trademarks ........................................................... 19
7.2 Functional Block Diagram ......................................... 8 11.4 Electrostatic Discharge Caution ............................ 19
7.3 Feature Description................................................... 9 11.5 Glossary ................................................................ 19
7.4 Device Functional Modes........................................ 10 12 Mechanical, Packaging, and Orderable
Information ........................................................... 19

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (August 2013) to Revision G Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 5

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5 Pin Configuration and Functions

PWP Package
28 Pin HTSSOP
Top View

CP1 1 28 GND
CP2 2 27 BI1
VCP 3 26 BI0
VMA 4 25 AI1
AOUT1 5 24 AI0
ISENA 6 23 BPHASE
AOUT2 7 GND 22 BENBL
BOUT2 8 (PPAD) 21 AENBL
ISENB 9 20 APHASE
BOUT1 10 19 DECAY
VMB 11 18 nFAULT
AVREF 12 17 nSLEEP
BVREF 13 16 nRESET
GND 14 15 V3P3OUT

RHD Package
28-Pin VQFN
Top View
BPHASE

APHASE
DECAY
BENBL
AENBL
AI0
AI1

26
28
27

25
24
23
22

BI0 1 21 nFAULT
BI1 2 20 nSLEEP
GND 3 19 nRESET
GND
CP1 4 (PPAD)
18 V3P3OUT
CP2 5 17 GND
VCP 6 16 BVREF
VMA 7 15 AVREF
10
11
12
13
14
8
9

BOUT2
ISENB

VMB
BOUT1
AOUT1
ISENA
AOUT2

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Pin Functions
PIN EXTERNAL COMPONENTS
I/O (1) DESCRIPTION
NAME PWP RHD OR CONNECTIONS
POWER AND GROUND
GND 14, 28 3, 17 - Device ground
VMA 4 7 - Bridge A power supply Connect to motor supply (8.2-V to 45-V). Both
pins must be connected to the same supply,
VMB 11 14 - Bridge B power supply bypassed with a 0.1uF capacitor to GND, and
connected to appropriate bulk capacitance.
Bypass to GND with a 0.47-μF 6.3-V ceramic
V3P3OUT 15 18 O 3.3-V regulator output
capacitor. Can be used to supply VREF.
CP1 1 4 IO Charge pump flying capacitor Connect a 0.01-μF 50-V capacitor between
CP2 2 5 IO Charge pump flying capacitor CP1 and CP2.
Connect a 0.1-μF 16-V ceramic capacitor and
VCP 3 6 IO High-side gate drive voltage
a 1-MΩ resistor to VM.
CONTROL
AENBL 21 24 I Bridge A enable Logic high to enable bridge A
APHASE 20 23 I Bridge A phase (direction) Logic high sets AOUT1 high, AOUT2 low
AI0 24 27 I Sets bridge A current: 00 = 100%,
Bridge A current set
AI1 25 28 I 01 = 71%, 10 = 38%, 11 = 0
BENBL 22 25 I Bridge B enable Logic high to enable bridge B
BPHASE 23 26 I Bridge B phase (direction) Logic high sets BOUT1 high, BOUT2 low
BI0 26 1 I Sets bridge B current: 00 = 100%,
Bridge B current set
BI1 27 2 I 01 = 71%, 10 = 38%, 11 = 0
Low = slow decay, open = mixed decay,
DECAY 19 22 I Decay mode
high = fast decay
Active-low reset input initializes internal logic
nRESET 16 19 I Reset input
and disables the H-bridge outputs
Logic high to enable device, logic low to enter
nSLEEP 17 20 I Sleep mode input
low-power sleep mode
AVREF 12 15 I Bridge A current set reference input Reference voltage for winding current set.
Can be driven individually with an external
DAC for microstepping, or tied to a reference
BVREF 13 16 I Bridge B current set reference input (e.g., V3P3OUT). A 0.01-µF bypass capacitor
to GND is recommended.
STATUS
Logic low when in fault condition (overtemp,
nFAULT 18 21 OD Fault
overcurrent)
OUTPUT
ISENA 6 9 IO Bridge A ground / Isense Connect to current sense resistor for bridge A
ISENB 9 12 IO Bridge B ground / Isense Connect to current sense resistor for bridge B
AOUT1 5 8 O Bridge A output 1
Connect to motor winding A
AOUT2 7 10 O Bridge A output 2
BOUT1 10 13 O Bridge B output 1
Connect to motor winding B
BOUT2 8 11 O Bridge B output 2

(1) Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output

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6 Specifications
6.1 Absolute Maximum Ratings
(1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VMx Power supply voltage –0.3 47 V
VMx Power supply ramp rate 1 V/µs
Digital pin voltage –0.5 7 V
VREF Input voltage –0.3 4 V
(3)
ISENSEx pin voltage –0.8 0.8 V
Peak motor drive output current, t < 1 μS Internally limited A
Continuous motor drive output current (4) 0 1.6 A
Continuous total power dissipation See Thermal Information
TJ Operating virtual junction temperature –40 150 °C
TA Operating ambient temperature –40 85 °C
Tstg Storage temperature –60 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Transients of ±1 V for less than 25 ns are acceptable
(4) Power dissipation and thermal limits must be observed.

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000 V
V(ESD) Electrostatic discharge Charged device model (CDM), per JEDEC specification JESD22-C101,
±500 V
all pins (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VM Motor power supply voltage range (1) 8.2 45 V
VREF VREF input voltage (2) 1 3.5 V
IV3P3 V3P3OUT load current 1 mA

(1) All VM pins must be connected to the same supply voltage.

(2) Operational at VREF between 0 V and 1 V, but accuracy is degraded.

6.4 Thermal Information

DRV8812
PWP RHD
THERMAL METRIC (1) UNIT
(HTSSOP) (VQFN)
28 PINS 28 PINS
RθJA Junction-to-ambient thermal resistance 38.9 35.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 23.3 25.1 °C/W
RθJB Junction-to-board thermal resistance 21.2 8.2 °C/W
ψJT Junction-to-top characterization parameter 0.8 0.3 °C/W
ψJB Junction-to-board characterization parameter 20.9 8.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.6 1.1 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

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6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES
IVM VM operating supply current VM = 24 V, fPWM < 50 kHz 5 8 mA
IVMQ VM sleep mode supply current VM = 24 V 10 20 μA
VUVLO VM undervoltage lockout voltage VM rising 7.8 8.2 V
V3P3OUT REGULATOR
IOUT = 0 to 1 mA, VM = 24 V, TJ = 25°C 3.18 3.30 3.42 V
V3P3 V3P3OUT voltage
IOUT = 0 to 1 mA 3.10 3.30 3.50 V
LOGIC-LEVEL INPUTS
VIL Input low voltage 0.6 0.7 V
VIH Input high voltage 2 5.25 V
VHYS Input hysteresis 0.45 V
IIL Input low current VIN = 0 –20 20 μA
IIH Input high current VIN = 3.3 V 100 μA
nFAULT OUTPUT (OPEN-DRAIN OUTPUT)
VOL Output low voltage IO = 5 mA 0.5 V
IOH Output high leakage current VO = 3.3 V 1 μA
DECAY INPUT
VIL Input low threshold voltage For slow decay mode 0 0.8 V
VIH Input high threshold voltage For fast decay mode 2 V
IIN Input current ±40 µA
H-BRIDGE FETS
VM = 24 V, I O = 1 A, TJ = 25°C 0.63 Ω
RDS(ON) HS FET on resistance
VM = 24 V, IO = 1 A, TJ = 85°C 0.76 0.90 Ω
VM = 24 V, IO = 1 A, TJ = 25°C 0.65 Ω
RDS(ON) LS FET on resistance
VM = 24 V, IO = 1 A, TJ = 85°C 0.78 0.90 Ω
IOFF Off-state leakage current –20 20 μA
MOTOR DRIVER
fPWM Internal PWM frequency 50 kHz
tBLANK Current sense blanking time 3.75 μs
tR Rise time VM = 24 V 100 360 ns
tF Fall time VM = 24 V 80 250 ns
tDEAD Dead time 400 ns
tDEG Input deglitch time 1.3 2.9 µs
PROTECTION CIRCUITS
IOCP Overcurrent protection trip level 1.8 5 A
tTSD Thermal shutdown temperature Die temperature 150 160 180 °C
CURRENT CONTROL
IREF xVREF input current xVREF = 3.3 V –3 3 μA
xVREF = 3.3 V, 100% current setting 635 660 685 mV
VTRIP xISENSE trip voltage xVREF = 3.3 V, 71% current setting 445 469 492 mV
xVREF = 3.3 V, 38% current setting 225 251 276 mV
AISENSE Current sense amplifier gain Reference only 5 V/V

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6.6 Typical Characteristics

7.0 14

13
6.5
12
6.0
11

IVMQ ( A)
IVM (mA)

5.5 10

9
5.0
-40°C
8
25°C 25°C
4.5
85°C 7 85°C
125°C 125°C
4.0 6
10 15 20 25 30 35 40 45 10 15 20 25 30 35 40 45
V(VMx) (V) C001 V(VMx) (V) C002

Figure 1. IVMx vs V(VMx) Figure 2. IVMxQ vs V(VMx)

2000 2000
-40°C 25°C 10 V
85°C 125°C 24 V
1800 1800
45 V
RDS(ON) HS + LS (mŸ)
RDS(ON) HS + LS (mŸ)

1600 1600

1400 1400

1200 1200

1000 1000

800 800
10 15 20 25 30 35 40 45 ±50 ±25 0 25 50 75 100 125
V(VMx) (V) C003 TA (ƒC) C004

Figure 3. RDS(ON) vs V(VMx) Figure 4. RDS(ON) vs Temperature

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7 Detailed Description

7.1 Overview
The DRV8812 is an integrated motor driver solution for a bipolar stepper motor or two brushed DC motors. The
device integrates two NMOS H-bridges, current sense, regulation circuitry, and detailed fault detection. The
DRV8813 can be powered with a supply voltage between 8.2 V and 45 V and is capable of providing an output
current up to 1.6 A full-scale.
A PHASE/ENBL interface allows for simple interfacing to the controller circuit. The winding current control allows
the external controller to adjust the regulated current that is provided to the motor. The current regulation is
highly configurable, with three decay modes of operation. Fast, slow, and mixed decay can be selected
depending on the application requirements.
A low-power sleep mode is included which allows the system to save power when not driving the motor.

7.2 Functional Block Diagram

VM

VM

CP1
Internal Int. VCC

Reference & LS Gate 0.01mF

Drive CP2
Regs Charge VM
Pump
V3P3OUT
3.3V VCP
3.3V
0.1mF
Thermal
HS Gate
Shut down Drive 1MW
VM
AVREF VMA

BVREF
AOUT1
+
APHASE Motor Step
DCM
Driver A Motor
AENBL -
AOUT2
AI0
+ -
AI1
ISENA

BPHASE

BENBL

BI0 Control VM
Logic VMB
BI1

DECAY BOUT1

nRESET Motor
DCM
Driver B
nSLEEP BOUT2

nFAULT ISENB

GND GND

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7.3 Feature Description

7.3.1 PWM Motor Drivers
The DRV8812 contains two H-bridge motor drivers with current-control PWM circuitry. A block diagram of the
motor control circuitry is shown in Figure 5. A bipolar stepper motor is shown, but the drivers can also drive two
separate DC motors.

Figure 5. Motor Control Circuitry

Note that there are multiple VM motor power supply pins. All VM pins must be connected together to the motor
supply voltage.

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7.4 Device Functional Modes

7.4.1 Bridge Control

The xPHASE input pins control the direction of current flow through each H-bridge. The xENBL input pins enable
the H-bridge outputs when active high. Table 1 shows the logic.

Table 1. H-Bridge Logic

xENBL xPHASE xOUT1 xOUT2
0 X Z Z
1 1 H L
1 0 L H

7.4.2 Current Regulation

The current through the motor windings is regulated by a fixed-frequency PWM current regulation, or current
chopping. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage
and inductance of the winding. Once the current hits the current chopping threshold, the bridge disables the
current until the beginning of the next PWM cycle.
For stepping motors, current regulation is normally used at all times, and can changing the current can be used
to microstep the motor. For DC motors, current regulation is used to limit the start-up and stall current of the
motor.
The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor
connected to the xISEN pins, multiplied by a factor of 5, with a reference voltage. The reference voltage is input
from the xVREF pins, and is scaled by a 2-bit DAC that allows current settings of 100%, 71%, 38% of full-scale,
plus zero.
The full-scale (100%) chopping current is calculated in Equation 1.
VREFX
ICHOP
5 u RISENSE (1)
Example:
If a 0.5-Ω sense resistor is used and the VREFx pin is 3.3 V, the full-scale (100%) chopping current will be
3.3 V / (5 x 0.5 Ω) = 1.32 A.
Two input pins per H-bridge (xI1 and xI0) are used to scale the current in each bridge as a percentage of the full-
scale current set by the VREF input pin and sense resistance. The function of the pins is shown in
Table 2.

Table 2. H-Bridge Pin Functions

RELATIVE CURRENT
xI1 xI0
(% FULL-SCALE CHOPPING CURRENT)
1 1 0% (Bridge disabled)
1 0 38%
0 1 71%
0 0 100%

Note that when both xI bits are 1, the H-bridge is disabled and no current flows.
Example:
If a 0.5-Ω sense resistor is used and the VREF pin is 3.3 V, the chopping current will be 1.32 A at the 100%
setting (xI1, xI0 = 00). At the 71% setting (xI1, xI0 = 01) the current will be 1.32 A x 0.71 = 0.937 A, and at
the 38% setting (xI1, xI0 = 10) the current will be 1.32 A x 0.38 = 0.502 A. If (xI1, xI0 = 11) the bridge will be
disabled and no current will flow.

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7.4.3 Decay Mode

During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until the PWM
current chopping threshold is reached. This is shown in Figure 6 as case 1. The current flow direction shown
indicates the state when the xENBL pin is high.
Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or
slow decay.
In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to
allow winding current to flow in a reverse direction. As the winding current approaches zero, the bridge is
disabled to prevent any reverse current flow. Fast decay mode is shown in Figure 6 as case 2.
In slow decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is
shown in Figure 6 as case 3.

Figure 6. Decay Mode

The DRV8812 supports fast decay, slow decay and a mixed decay mode. Slow, fast, or mixed decay mode is
selected by the state of the DECAY pin - logic low selects slow decay, open selects mixed decay operation, and
logic high sets fast decay mode. Note that the DECAY pin sets the decay mode for both H-bridges.
Mixed decay mode begins as fast decay, but at a fixed period of time (75% of the PWM cycle) switches to slow
decay mode for the remainder of the fixed PWM period.

7.4.4 Blanking Time

After the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a fixed period of time
before enabling the current sense circuitry. This blanking time is fixed at 3.75 μs. Note that the blanking time also
sets the minimum on time of the PWM.

7.4.5 nRESET and nSLEEP Operation

The nRESET pin, when driven active low, resets the internal logic. It also disables the H-bridge drivers. All inputs
are ignored while nRESET is active.

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Driving nSLEEP low will put the device into a low power sleep state. In this state, the H-bridges are disabled, the
gate drive charge pump is stopped, the V3P3OUT regulator is disabled, and all internal clocks are stopped. In
this state all inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time
(approximately 1 ms) needs to pass before the motor driver becomes fully operational.

7.4.6 Protection Circuits

The DRV8812 is fully protected against undervoltage, overcurrent and overtemperature events.

7.4.6.1 Overcurrent Protection (OCP)

An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled and the
nFAULT pin will be driven low. The device will remain disabled until either nRESET pin is applied, or VM is
removed and re-applied.
Overcurrent conditions on both high and low side devices; i.e., a short to ground, supply, or across the motor
winding will all result in an overcurrent shutdown. Note that overcurrent protection does not use the current sense
circuitry used for PWM current control, and is independent of the ISENSE resistor value or VREF voltage.

7.4.6.2 Thermal Shutdown (TSD)

If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be
driven low. Once the die temperature has fallen to a safe level operation will automatically resume.

7.4.6.3 Undervoltage Lockout (UVLO)

If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all circuitry in the
device will be disabled and internal logic will be reset. Operation will resume when VM rises above the UVLO
threshold.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DRV8812 can be used to control a bipolar stepper motor. The PHASE/ENBL interface controls the outputs
and current control can be implemented with the internal current regulation circuitry. Detailed fault reporting is
provided with the internal protection circuits and nFAULT pin.

8.2 Typical Application

DRV8812

CP1 GND
0.01uF
CP2 BI1

VCP BI0
0.01uF 1MŸ 0.1uF
VMA AI1

AOUT1 AI0
+

400mŸ
VM Stepper Motor ISENA BPHASE
-

AOUT2 BENBL
+
100uF + -
BOUT2 AENBL
400mŸ
ISENB APHASE
V3P3OUT
BOUT1 DECAY
10kŸ
VMB nFAULT
0.01uF V3P3OUT
AVREF nSLEEP
10kŸ
BVREF nRESET
30kŸ
PPAD

V3P3OUT
GND V3P3OUT
0.47uF

Figure 7. Typical Application Schematic

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Typical Application (continued)

8.2.1 Design Requirements

Table 3. Design Parameters

PARAMETER REFERENCE VALUE
Supply voltage VM 24 V
Motor winding
RL 3.9 Ω
resistance
Motor winding
IL 2.9 mH
inductance
Sense resistor
RSENSE 400 mΩ
value
Target full-scale
IFS 1.25 A
current

8.2.2 Detailed Design Procedure

8.2.2.1 Current Regulation

In a stepper motor, the set full-scale current (IFS) is the maximum current driven through either winding. This
quantity depends on the xVREF analog voltage and the sense resistor value (RSENSE). During stepping, IFS
defines the current chopping threshold (ITRIP) for the maximum current step. The gain of DRV8812 is set for 5
V/V.
xVREF(V) xVREF(V)
IFS (A)
A v u RSENSE (:) 5 u RSENSE (:) (2)
To achieve IFS = 1.25 A with RSENSE of 0.2 Ω, xVREF should be 1.25 V.

8.2.2.2 Decay Modes

The DRV8812 supports three different decay modes: slow decay, fast decay, and mixed decay. The current
through the motor windings is regulated using a fixed-frequency PWM scheme. This means that after any drive
phase, when a motor winding current has hit the current chopping threshold (ITRIP), the DRV8812 will place the
winding in one of the three decay modes until the PWM cycle has expired. Afterward, a new drive phase starts.
The blanking time, tBLANK, defines the minimum drive time for the current chopping. ITRIP is ignored during tBLANK,
so the winding current may overshoot the trip level.

8.2.2.3 Sense Resistor

For optimal performance, it is important for the sense resistor to be:
• Surface-mount
• Low inductance
• Rated for high enough power
• Placed closely to the motor driver
The power dissipated by the sense resistor equals Irms2 x R. For example, if the rms motor current is 2-A and a
100-m Ω sense resistor is used, the resistor will dissipate 2 A ² × 0.1 Ω = 0.4 W. The power quickly increases
with greater current levels.
Resistors typically have a rated power within some ambient temperature range, along with a de-rated power
curve for high ambient temperatures. When a PCB is shared with other components generating heat, margin
should be added. It is always best to measure the actual sense resistor temperature in a final system, along with
the power MOSFETs, as those are often the hottest components.
Because power resistors are larger and more expensive than standard resistors, it is common practice to use
multiple standard resistors in parallel, between the sense node and ground. This distributes the current and heat
dissipation.

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Product Folder Links: DRV8812

 DRV8812
www.ti.com SLVS997G – OCTOBER 2009 – REVISED OCTOBER 2015

8.2.3 Application Curves

Figure 8. DRV8828 Current Limiting Figure 9. DRV8828 Direction Change

Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: DRV8812
DRV8812
SLVS997G – OCTOBER 2009 – REVISED OCTOBER 2015 www.ti.com

9 Power Supply Recommendations

The DRV8812 is designed to operate from an input voltage supply (VMx) range between 8.2 and 45 V. Two
0.1-µF ceramic capacitors rated for VMx must be placed as close as possible to the VMA and VMB pins
respectively (one on each pin). In addition to the local decoupling caps, additional bulk capacitance is required
and must be sized accordingly to the application requirements.

9.1 Bulk Capacitance

Bulk capacitance sizing is an important factor in motor drive system design. It is dependent on a variety of factors
including:
• Type of power supply
• Acceptable supply voltage ripple
• Parasitic inductance in the power supply wiring
• Type of motor (brushed DC, brushless DC, stepper)
• Motor startup current
• Motor braking method
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. You should size the bulk capacitance to meet acceptable
voltage ripple levels.
The data sheet generally provides a recommended value but system level testing is required to determine the
appropriate sized bulk capacitor.

Parasitic Wire
Inductance
Power Supply Motor Drive System

VM

+ + Motor
Motor
– Driver
Driver
GND

Local IC Bypass
Bulk Capacitor Capacitor

Figure 10. Setup of Motor Drive System With External Power Supply

9.2 Power Supply and Logic Sequencing

There is no specific sequence for powering-up the DRV8812. It is okay for digital input signals to be present
before VMx is applied. After VMx is applied to the DRV8812, it begins operation based on the status of the
control pins.

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 DRV8812
www.ti.com SLVS997G – OCTOBER 2009 – REVISED OCTOBER 2015

10 Layout

10.1 Layout Guidelines

The VMA and VMB pins should be bypassed to GND using low-ESR ceramic bypass capacitors with a
recommended value of 0.1-μF rated for VMx. This capacitor should be placed as close to the VMA and VMB pins
as possible with a thick trace or ground plane connection to the device GND pin.
The VMA and VMB pins must be bypassed to ground using an appropriate bulk capacitor. This component may
be an electrolytic and should be located close to the DRV8812.
A low-ESR ceramic capacitor must be placed in between the CPL and CPH pins. TI recommends a value of
0.01-μF rated for VMx. Place this component as close to the pins as possible.
A low-ESR ceramic capacitor must be placed in between the VMA and VCP pins. TI recommends a value of 0.1-
μF rated for 16 V. Place this component as close to the pins as possible. Also, place a 1-MΩ resistor between
VCP and VMA.
Bypass V3P3 to ground with a ceramic capacitor rated 6.3 V. Place this bypass capacitor as close to the pin as
possible

10.2 Layout Example

CP1 GND
0.1 µF
0.01 µF
CP2 BI1

VCP BI0
1 0Ÿ 0.1 µF
VMA AI1

AOUT1 AI0

ISENA BPHASE

RISENA AOUT2 BENBL

BOUT2 AENBL

ISENB APHASE

RISENB BOUT1 DECAY

VMB nFAULT
0.1 µF
+

AVREF nSLEEP

BVREF nRESET

GND V3P3OUT

0.47 µF

Figure 11. DRV8812 Layout Example

Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: DRV8812
DRV8812
SLVS997G – OCTOBER 2009 – REVISED OCTOBER 2015 www.ti.com

10.3 Thermal Consideration

10.3.1 Thermal Protection

The DRV8812 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately
150°C, the device will be disabled until the temperature drops to a safe level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.

10.3.2 Power Dissipation

Power dissipation in the DRV8812 is dominated by the power dissipated in the output FET resistance, or RDS(ON).
Average power dissipation when running a stepper motor can be roughly estimated by Equation 3.
2
PTOT 4 u RDS(ON) u IOUT(RMS)
(3)
where PTOT is the total power dissipation, RDS(ON) is the resistance of each FET, and IOUT(RMS) is the RMS output
current being applied to each winding. IOUT(RMS) is equal to the approximately 0.7x the full-scale output current
setting. The factor of 4 comes from the fact that there are two motor windings, and at any instant two FETs are
conducting winding current for each winding (one high-side and one low-side).
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must
be taken into consideration when sizing the heatsink.

10.3.3 Heatsinking
The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad
must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane,
this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs
without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area
is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and
bottom layers.
For details about how to design the PCB, refer to TI application report SLMA002, "PowerPAD™ Thermally
Enhanced Package" and TI application brief SLMA004, "PowerPAD™ Made Easy", available at www.ti.com.
In general, the more copper area that can be provided, the more power can be dissipated.

18 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated

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 DRV8812
www.ti.com SLVS997G – OCTOBER 2009 – REVISED OCTOBER 2015

11 Device and Documentation Support

11.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Links: DRV8812
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

DRV8812PWP ACTIVE HTSSOP PWP 28 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 DRV8812

DRV8812PWPR ACTIVE HTSSOP PWP 28 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 DRV8812

DRV8812RHDR ACTIVE VQFN RHD 28 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV8812

DRV8812RHDT ACTIVE VQFN RHD 28 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV8812

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Apr-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8812PWPR HTSSOP PWP 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
DRV8812RHDR VQFN RHD 28 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2
DRV8812RHDT VQFN RHD 28 250 180.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Apr-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DRV8812PWPR HTSSOP PWP 28 2000 350.0 350.0 43.0
DRV8812RHDR VQFN RHD 28 3000 346.0 346.0 33.0
DRV8812RHDT VQFN RHD 28 250 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Apr-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
DRV8812PWP PWP HTSSOP 28 50 530 10.2 3600 3.5

Pack Materials-Page 3
 PACKAGE OUTLINE
RHD0028B SCALE 2.500
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

5.15
B A
4.85

PIN 1 INDEX AREA

5.15
4.85

1.0
0.8

SEATING PLANE
0.05 0.08 C
0.00 3.15 0.1

2X 3
SYMM (0.2) TYP
8 14
EXPOSED
THERMAL PAD

7 15

SYMM 29
2X 3 3.15 0.1

24X 0.5
1
21

PIN 1 ID 0.30
28X
28 22 0.18
0.1 C A B
0.65
28X 0.05
0.45
4226146/A 08/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RHD0028B VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 3.15)
SYMM
28 22 SEE SOLDER MASK
DETAIL

28X (0.75)

28X (0.24) 21
1

24X (0.5)

29 SYMM
(4.65)

(1.325)
(R0.05) TYP

7
15

( 0.2) TYP
VIA

8 14
(1.325)

(4.65)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 18X
0.07 MIN
0.07 MAX ALL AROUND
ALL AROUND
METAL UNDER
METAL EDGE SOLDER MASK

EXPOSED METAL
SOLDER MASK EXPOSED SOLDER MASK
OPENING METAL OPENING

NON SOLDER MASK

DEFINED SOLDER MASK DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4226146/A 08/2020
NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RHD0028B VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(0.785) TYP
28 22

28X (0.75)

28X (0.24) 1 21

24X (0.5)

(0.785) TYP
29
SYMM (4.65)

(R0.05) TYP

4X (1.37)

15

8 14
4X (1.37)
SYMM

(4.65)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL
SCALE: 20X

EXPOSED PAD 29
76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4226146/A 08/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 GENERIC PACKAGE VIEW
TM
PWP 28 PowerPAD TSSOP - 1.2 mm max height
4.4 x 9.7, 0.65 mm pitch SMALL OUTLINE PACKAGE

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224765/B

www.ti.com
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