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DRV8874
SLVSF66A – AUGUST 2019 – REVISED DECEMBER 2019

DRV8874 H-Bridge Motor Driver With Integrated Current Sense and Regulation
1 Features 3 Description
1• N-channel H-bridge motor driver The DRV8874 is an integrated motor driver with N-
channel H-bridge, charge pump, current sensing and
– Drives one bidirectional brushed DC motor proportional output, current regulation, and protection
– Two unidirectional brushed DC motors circuitry. The charge pump improves efficiency by
– Other resistive and inductive loads supporting N-channel MOSFET half bridges and
100% duty cycle driving. The family of devices come
• 4.5-V to 37-V operating supply voltage range
in pin-to-pin RDS(on) variants to support different loads
• Pin to pin RDS(on) variants with minimal design changes.
– DRV8874: 200-mΩ (High-Side + Low-Side) An internal current mirror architecture on the IPROPI
– DRV8876: 700-mΩ (High-Side + Low-Side) pin implements current sensing and regulation. This
• High output current capability eliminates the need for a large power shunt resistor,
saving board area and reducing system cost. The
– DRV8874: 6-A Peak
IPROPI current-sense output allows a microcontroller
– DRV8876: 3.5-A Peak to detect motor stall or changes in load conditions.
• Integrated current sensing and regulation Using the external voltage reference pin, VREF,
• Proportional current output (IPROPI) these devices can regulate the motor current during
start-up and high-load events without interaction from
• Selectable current regulation (IMODE) a microcontroller.
– Cycle-by-cycle or fixed off time
A low-power sleep mode achieves ultra-low quiescent
• Selectable input control modes (PMODE) current draw by shutting down most of the internal
– PH/EN and PWM H-bridge control modes circuitry. Internal protection features include supply
– Independent half-bridge control mode undervoltage lockout, charge pump undervoltage,
output overcurrent, and device overtemperature.
• Supports 1.8-V, 3.3-V, and 5-V logic inputs Fault conditions are indicated on nFAULT.
• Ultra low-power sleep mode
View our full portfolio of brushed motor drivers on
– <1-µA @ VVM = 24-V, TJ = 25°C ti.com.
• Spread spectrum clocking for low electromagnetic
(1)
interference (EMI) Device Information
• Integrated protection features PART NUMBER PACKAGE BODY SIZE (NOM)

– Undervoltage lockout (UVLO) DRV8874 HTSSOP (16) 5.00 mm × 4.40 mm

– Charge pump undervoltage (CPUV) (1) For all available packages, see the orderable addendum at
the end of the data sheet.
– Overcurrent protection (OCP)

xx
– Automatic retry or outputs latched off Simplified Schematic
(IMODE)
4.5 to 37 V
– Thermal shutdown (TSD)

xx
– Automatic fault recovery

xxx
DRV887x
nSLEEP
– Fault indicator pin (nFAULT) x
x

Control Inputs

xxx
H-Bridge
Controller

Motor Driver
2 Applications
nFAULT
• Brushed DC motors Current Sense
IPROPI
• Major and small home appliances IPROPI
RIPROPI

• Vacuum, humanoid, and toy robotics Protection

• Printers and scanners

• Smart meters
• ATMs, currency counters, and EPOS
• Servo motors and actuators

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8 Application and Implementation ........................ 20
2 Applications ........................................................... 1 8.1 Application Information............................................ 20
3 Description ............................................................. 1 8.2 Typical Application .................................................. 20
4 Revision History..................................................... 2 9 Power Supply Recommendations...................... 30
5 Pin Configuration and Functions ......................... 3 9.1 Bulk Capacitance .................................................... 30
6 Specifications......................................................... 4 10 Layout................................................................... 31
6.1 Absolute Maximum Ratings ...................................... 4 10.1 Layout Guidelines ................................................. 31
6.2 ESD Ratings.............................................................. 4 10.2 Layout Example .................................................... 31
6.3 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 32
6.4 Thermal Information .................................................. 5 11.1 Documentation Support ........................................ 32
6.5 Electrical Characteristics........................................... 5 11.2 Receiving Notification of Documentation Updates 32
6.6 Typical Characteristics .............................................. 8 11.3 Community Resources.......................................... 32
7 Detailed Description .............................................. 9 11.4 Trademarks ........................................................... 32
7.1 Overview ................................................................... 9 11.5 Electrostatic Discharge Caution ............................ 32
7.2 Functional Block Diagram ......................................... 9 11.6 Glossary ................................................................ 32
7.3 Feature Description................................................. 10 12 Mechanical, Packaging, and Orderable
7.4 Device Functional Modes........................................ 18 Information ........................................................... 33

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (May 2019) to Revision A Page

• Changed Current Regulation section with a workaround for transients that are longer than the current regulation
deglitch time.......................................................................................................................................................................... 13
• Added additional description to Fixed Off-Time Current Regulation Section ....................................................................... 13
• Changed calculations in Power Dissipation and Output Current Capability ........................................................................ 21
• Added thermal plots for and description for PWP ................................................................................................................ 22
• Added power-up plots........................................................................................................................................................... 26

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5 Pin Configuration and Functions

DRV8874 PWP Package
16-Pin HTSSOP With Exposed Thermal Pad
Top View

EN/IN1 1 16 PMODE

PH/IN2 2 15 GND

nSLEEP 3 14 CPL

nFAULT 4 13 CPH
Thermal
Pad
VREF 5 12 VCP

IPROPI 6 11 VM

IMODE 7 10 OUT2

OUT1 8 9 PGND

Pin Functions
PIN
TYPE DESCRIPTION
NAME PWP
CPH 13 PWR Charge pump switching node. Connect a X5R or X7R, 22-nF, VM-rated ceramic capacitor
CPL 14 PWR between the CPH and CPL pins.
EN/IN1 1 I H-bridge control input. See Control Modes. Internal pulldown resistor.
GND 15 PWR Device ground. Connect to system ground.
Current regulation and overcurrent protection mode. See Current Regulation. Quad-level
IMODE 7 I
input.
IPROPI 6 O Analog current output proportional to load current. See Current Sensing.
Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor
nFAULT 4 OD
for open-drain operation. See Protection Circuits.
Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode.
nSLEEP 3 I
See Device Functional Modes. Internal pulldown resistor.
OUT1 8 O H-bridge output. Connect to the motor or other load.
OUT2 10 O H-bridge output. Connect to the motor or other load.
PGND 9 PWR Device power ground. Connect to system ground.
PH/IN2 2 I H-bridge control input. See Control Modes. Internal pulldown resistor.
PMODE 16 I H-bridge control input mode. See Control Modes. Tri-level input.
Charge pump output. Connect a X5R or X7R, 100-nF, 16-V ceramic capacitor between the
VCP 12 PWR
VCP and VM pins.
4.5-V to 37-V power supply input. Connect a 0.1-µF bypass capacitor to ground, as well as
VM 11 PWR
sufficient Bulk Capacitance rated for VM.
External reference voltage input to set internal current regulation limit. See Current
VREF 5 I
Regulation.
PAD — — Thermal pad. Connect to system ground.

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6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Power supply pin voltage VM –0.3 40 V
Voltage difference between ground pins GND, PGND –0.3 0.3 V
Charge pump pin voltage CPH, VCP VVM – 0.3 VVM + 7 V
Charge pump low-side pin voltage CPL –0.3 VVM + 0.3 V
EN/IN1, IMODE, nSLEEP, PH/IN2,
Logic pin voltage –0.3 5.75 V
PMODE
Open-drain output pin voltage nFAULT –0.3 5.75 V
Output pin voltage OUT1, OUT2 –0.9 VVM + 0.9 V
Internally Internally
Output pin current OUT1, OUT2 A
Limited Limited
–0.3 5.75 V
Proportional current output pin voltage IPROPI
–0.3 VVM + 0.3 V
Reference input pin voltage VREF –0.3 5.75 V
Ambient temperature, TA –40 125 °C
Junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V(ESD) V
discharge Charged device model (CDM), per JEDEC specification JESD22-C101 (2) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000
V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500
V may actually have higher performance.

6.3 Recommended Operating Conditions

over operating temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VVM Power supply voltage VM 4.5 37 V
VIN Logic input voltage EN/IN1, MODE, nSLEEP, PH/IN2 0 5.5 V
fPWM PWM frequency EN/IN1, PH/IN2 0 100 kHz
VOD Open drain pullup voltage nFAULT 0 5.5 V
IOD Open drain output current nFAULT 0 5 mA
IOUT (1) Peak output current OUT1, OUT2 0 6 A
IIPROPI Current sense output current IPROPI 0 3 mA
VVREF Current limit reference voltage VREF 0 3.6 V
TA Operating ambient temperature –40 125 °C
TJ Operating junction temperature –40 150 °C

(1) Power dissipation and thermal limits must be observed

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6.4 Thermal Information

DRV8874
THERMAL METRIC (1) PWP (HTSSOP) UNIT
16 PINS
RθJA Junction-to-ambient thermal resistance 36.0 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 27.3 °C/W
RθJB Junction-to-board thermal resistance 11.1 °C/W
ΨJT Junction-to-top characterization parameter 0.4 °C/W
ΨJB Junction-to-board characterization parameter 11.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.7 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Electrical Characteristics

4.5 V ≤ VVM ≤ 37 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VCP, VM)
VVM = 24 V, nSLEEP = 0 V, TJ = 25°C 0.75 1 µA
IVMQ VM sleep mode current
nSLEEP = 0 V 5 µA
VVM = 24 V, nSLEEP = 5 V,
IVM VM active mode current 3 7 mA
EN/IN1 = PH/IN2 = 0 V
tWAKE Turnon time VVM > VUVLO, nSLEEP = 5 V to active 1 ms
tSLEEP Turnoff time nSLEEP = 0 V to sleep mode 1 ms
VVCP Charge pump regulator voltage VCP with respect to VM, VVM = 24 V 5 V
fVCP Charge pump switching frequency 400 kHz
LOGIC-LEVEL INPUTS (EN/IN1, PH/IN2, nSLEEP)
VVM < 5 V 0 0.7
VIL Input logic low voltage V
VVM ≥ 5 V 0 0.8
VIH Input logic high voltage 1.5 5.5 V
200 mV
VHYS Input hysteresis
nSLEEP 50 mV
IIL Input logic low current VI = 0 V –5 5 µA
IIH Input logic high current VI = 5 V 50 75 µA
RPD Input pulldown resistance To GND 100 kΩ
TRI-LEVEL INPUTS (PMODE)
VTIL Tri-level input logic low voltage 0 0.65 V
VTIZ Tri-level input Hi-Z voltage 0.9 1.1 1.2 V
VTIH Tri-level input logic high voltage 1.5 5.5 V
ITIL Tri-level input logic low current VI = 0 V –50 –32 µA
ITIZ Tri-level input Hi-Z current VI = 1.1 V –10 10 µA
ITIH Tri-level input logic high current VI = 5 V 113 150 µA
RTPD Tri-level pulldown resistance To GND 44 kΩ
RTPU Tri-level pullup resistance To internal 5 V 156 kΩ
QUAD-LEVEL INPUTS (IMODE)
VQI2 Quad-level input level 1 Voltage to set quad-level 1 0 0.45 V
RQI2 Quad-level input level 2 Resistance to GND to set quad-level 2 18.6 20 21.4 kΩ
RQI3 Quad-level input level 3 Resistance to GND to set quad-level 3 57.6 62 66.4 kΩ
VQI4 Quad-level input level 4 Voltage to set quad-level 4 2.5 5.5 V
RQPD Quad-level pulldown resistance To GND 136 kΩ
RQPU Quad-level pullup resistance To internal 5 V 68 kΩ

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Electrical Characteristics (continued)

4.5 V ≤ VVM ≤ 37 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPEN-DRAIN OUTPUTS (nFAULT)
VOL Output logic low voltage IOD = 5 mA 0.3 V
IOZ Output logic high current VOD = 5 V –2 2 µA
DRIVER OUTPUTS (OUT1, OUT2)
RDS(on)_HS High-side MOSFET on resistance VVM = 24 V, IO = 2 A, TJ = 25°C 100 120 mΩ
RDS(on)_LS Low-side MOSFET on resistance VVM = 24 V, IO = –2 A, TJ = 25°C 100 120 mΩ
VSD Body diode forward voltage ISD = 1 A 0.9 V
tRISE Output rise time VVM = 24 V, OUTx rising 10% to 90% 150 ns
tFALL Output fall time VVM = 24 V, OUTx falling 90% to 10% 150 ns
EN/IN1, PH/IN2 to OUTx, 200 Ω from
tPD Input to output propagation delay 400 ns
OUTx to GND
tDEAD Output dead time Body diode conducting 100 ns
CURRENT SENSE AND REGULATION (IPROPI, VREF)
AIPROPI Current mirror scaling factor 450 µA/A
IOUT < 0.4 A
–30 30 mA
5.5 V ≤ VVM ≤ 37 V
0.4 A ≤ IOUT < 1 A
–7.5 7.5
(1)
5.5 V ≤ VVM ≤ 37 V
AERR Current mirror scaling error
1 A ≤ IOUT < 2 A
–6 6 %
5.5 V ≤ VVM ≤ 37 V
2 A ≤ IOUT ≤ 4 A
–5.5 5.5
5.5 V ≤ VVM ≤ 37 V
tOFF Current regulation off time 25 µs
tDELAY Current sense delay time 1.6 µs
tDEG Current regulation deglitch time 0.6 µs
tBLK Current regulation blanking time 1.1 µs
PROTECTION CIRCUITS
VVM rising 4.3 4.45 4.6 V
VUVLO Supply undervoltage lockout (UVLO)
VVM falling 4.2 4.35 4.5 V
VUVLO_HYS Supply UVLO hysteresis 100 mV
tUVLO Supply undervoltage deglitch time 10 µs
VCPUV Charge pump undervoltage lockout VCP with respect to VM, VVCP falling 2.25 V
IOCP Overcurrent protection trip point 6 10 A
tOCP Overcurrent protection deglitch time 3 µs
tRETRY Overcurrent protection retry time 2 ms
TTSD Thermal shutdown temperature 160 175 190 °C
THYS Thermal shutdown hysteresis 20 °C

(1) At low currents, the IPROPI output has a fixed offset error with respect to the IOUT current through the low-side power MOSFETs.

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EN/IN1 or
PH/IN2 tFALL
tRISE

ttPDt

OUTx (V)

ttBLKt ttOFFt

ITRIP
OUTx (A)

tDEG

VREF
IPROPI (V)

ttDELAYt

Figure 1. Timing Parameter Diagram

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6.6 Typical Characteristics

1.4 2
VVM = 4.5 V
1.2 1.75 VVM = 13.5 V
VVM = 24 V
IVMQ Supply Current (PA)

IVMQ Supply Current (PA)

1.5 VVM = 37 V
1
1.25
0.8
1
0.6
0.75
0.4 TJ = -40°C 0.5
TJ = 25°C
0.2 TJ = 125°C
0.25
TJ = 150°C
0 0
0 5 10 15 20 25 30 35 40 -40 -20 0 20 40 60 80 100 120 140 160
VM Supply Voltage (V) 74_I
Junction Temperature (°C) 74_I

Figure 2. Sleep Current (IVMQ) vs. Supply Voltage (VVM) Figure 3. Sleep Current (IVMQ) vs. Junction Temperature
3.06 3.05
TJ = -40°C
3.03 3.025
TJ = 25°C
3 TJ = 125°C 3
TJ = 150°C

IVM Supply Current (mA)

IVM Supply Current (mA)

2.975
2.97
2.95
2.94
2.925
2.91
2.9
2.88
2.875
2.85
2.85 VVM = 4.5 V
2.82 VVM = 13.5 V
2.825
VVM = 24 V
2.79 2.8 VVM = 37 V
2.76 2.775
0 5 10 15 20 25 30 35 40 -40 -20 0 20 40 60 80 100 120 140 160
VM Supply Voltage (V) 74_I
Junction Temperature (°C) 74_I

Figure 4. Active Current (IVM) vs. Supply Voltage (VVM) Figure 5. Active Current (IVM) vs. Junction Temperature
0.14 0.14
0.135 0.135
0.13 0.13
0.125 0.125
0.12 0.12
0.115 0.115
RDS(on)_HS (:)
RDS(on)_LS (:)

0.11
0.11
0.105
0.105
0.1
0.1
0.095
0.09 0.095
0.085 VVM = 4.5 V 0.09 VVM = 4.5 V
0.08 VVM = 13.5 V 0.085 VVM = 13.5 V
0.075 VVM = 24 V 0.08 VVM = 24 V
VVM = 37 V 0.075 VVM = 37 V
0.07
0.065 0.07
-40 -20 0 20 40 60 80 100 120 140 160 -40 -20 0 20 40 60 80 100 120 140 160
Junction Temperature (°C) 74_L
Junction Temperature (°C) 74_H

Figure 6. Low-Side RDS(on) vs. Junction Temperature Figure 7. High-Side RDS(on) vs. Junction Temperature
460 456
458 454
456 452
AIPROPI from OUT1 (PA/A)

AIPROPI from OUT2 (PA/A)

454
450
452
448
450
446
448
444
446 IOUT = 0.3 A IOUT = 0.3 A
IOUT = 0.4 A 442 IOUT = 0.4 A
444
IOUT = 1 A 440 IOUT = 1 A
442 IOUT = 2 A IOUT = 2 A
440 IOUT = 4 A 438 IOUT = 4 A
438 436
-40 -20 0 20 40 60 80 100 120 140 160 -40 -20 0 20 40 60 80 100 120 140 160
Ambient Temperature (qC) 74_A
Ambient Temperature (°C) 74_A

Figure 8. OUT1 Current Sense Error vs. Junction Figure 9. OUT2 Current Sense Error vs. Junction
Temperature Temperature

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7 Detailed Description

7.1 Overview
The DRV887x family of devices are brushed DC motor drivers that operate from 4.5 to 37-V supporting a wide
range of output load currents for various types of motors and loads. The devices integrate an H-bridge output
power stage that can be operated in different control modes set by the PMODE pin setting. This allows for driving
a single bidirectional brushed DC motor, two unidirectional brushed DC motors, or other output load
configurations. The devices integrate a charge pump regulator to support more efficient high-side N-channel
MOSFETs and 100% duty cycle operation. The devices operate from a single power supply input (VM) which can
be directly connected to a battery or DC voltage supply. The nSLEEP pin provides an ultra-low power mode to
minimize current draw during system inactivity.
The DRV887x family of devices also integrate current sense output using current mirrors on the low-side power
MOSFETs. The IPROPI pin sources a small current that is proportional to the current in the MOSFETs. This
current can be converted to a proportional voltage using an external resistor (RIPROPI). The integrated current
sensing allows the DRV887x devices to limit the output current with a fixed off-time PWM chopping scheme and
provide load information to the external controller to detect changes in load or stall conditions. The integrated
current sensing outperforms traditional external shunt resistor sensing by providing current information even
during the off-time slow decay recirculating period and removing the need for an external power shunt resistor.
The off-time PWM current regulation level can be configured during motor operation through the VREF pin to
limit the load current accordingly to the system demands.
A variety of integrated protection features protect the device in the case of a system fault. These include
undervoltage lockout (UVLO), charge pump undervoltage (CPUV), overcurrent protection (OCP), and
overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin.

7.2 Functional Block Diagram

VM
VM VM
Gate Driver
0.1 …F VVCP VVCP
VCP
0.1 …F
VCP HS
CPH Charge OUT1
Pump VDD
0.022 …F
CPL
LS
VDD
GND Internal
Regulator
ISEN1
Power
Digital VM
Core Gate Driver
nSLEEP
VVCP

EN/IN1
HS
OUT2
PH/IN2 VDD
Control
Inputs
PMODE LS
3-Level
PGND
IMODE
4-Level ISEN2 VVCC
VVCC
VREF RPU
+ Fault Output
IPROPI nFAULT
Clamp ±
IPROPI Current ISEN1
Sense ISEN2
RIPROPI

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7.3 Feature Description

7.3.1 External Components
Table 1 lists the recommended external components for the device.

Table 1. Recommended External Components

COMPONENT PIN 1 PIN 2 RECOMMENDED
CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated.
CVM2 VM GND Bulk Capacitance, VM-rated.
CVCP VCP VM X5R or X7R, 100-nF, 16-V ceramic capacitor
CFLY CPH CPL X5R or X7R, 22-nF, VM-rated ceramic capacitor
RIMODE IMODE GND See Current Regulation.
RPMODE PMODE GND See Control Modes.
RnFAULT VCC nFAULT Pullup resistor, IOD ≤ 5-mA
RIPROPI IPROPI GND See Current Sensing.

7.3.2 Control Modes

The DRV887x family of devices provides three modes to support different control schemes with the EN/IN1 and
PH/IN2 pins. The control mode is selected through the PMODE pin with either logic low, logic high, or setting the
pin Hi-Z as shown in Table 2. The PMODE pin state is latched when the device is enabled through the nSLEEP
pin. The PMODE state can be changed by taking the nSLEEP pin logic low, waiting the tSLEEP time, changing the
PMODE pin input, and then enabling the device by taking the nSLEEP pin back logic high.

Table 2. PMODE Functions

PMODE STATE CONTROL MODE
PMODE = Logic Low PH/EN
PMODE = Logic High PWM
PMODE = Hi-Z Independent Half-Bridge

VM VM

1 Forward drive 1 Reverse drive

2 Slow decay (brake) 22 Slow decay (brake)

1 1
3 High-Z (coast) 3 High-Z (coast)
OUT1 OUT2 OUT1 OUT2
2 2
3 3

Forward Reverse

Figure 10. H-Bridge States

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The inputs can accept static or pulse-width modulated (PWM) voltage signals for either 100% or PWM drive
modes. The device input pins can be powered before VM is applied with no issues. By default, the EN/IN1 and
PH/IN2 pins have an internal pulldown resistor to ensure the outputs are Hi-Z if no inputs are present.
The sections below show the truth table for each control mode. Note that these tables do not take into account
the internal current regulation feature. Additionally, the DRV887x family of devices automatically handles the
dead-time generation when switching between the high-side and low-side MOSFET of a half-bridge.
Figure 10 describes the naming and configuration for the various H-bridge states.

7.3.2.1 PH/EN Control Mode (PMODE = Logic Low)

When the PMODE pin is logic low on power up, the device is latched into PH/EN mode. PH/EN mode allows for
the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is
shown in Table 3.

Table 3. PH/EN Control Mode

nSLEEP EN PH OUT1 OUT2 DESCRIPTION
0 X X Hi-Z Hi-Z Sleep, (H-Bridge Hi-Z)
1 0 X L L Brake, (Low-Side Slow Decay)
1 1 0 L H Reverse (OUT2 → OUT1)
1 1 1 H L Forward (OUT1 → OUT2)

7.3.2.2 PWM Control Mode (PMODE = Logic High)

When the PMODE pin is logic high on power up, the device is latched into PWM mode. PWM mode allows for
the H-bridge to enter the Hi-Z state without taking the nSLEEP pin logic low. The truth table for PWM mode is
shown in Table 4.

Table 4. PWM Control Mode

nSLEEP IN1 IN2 OUT1 OUT2 DESCRIPTION
0 X X Hi-Z Hi-Z Sleep, (H-Bridge Hi-Z)
1 0 0 Hi-Z Hi-Z Coast, (H-Bridge Hi-Z)
1 0 1 L H Reverse (OUT2 → OUT1)
1 1 0 H L Forward (OUT1 → OUT2)
1 1 1 L L Brake, (Low-Side Slow Decay)

7.3.2.3 Independent Half-Bridge Control Mode (PMODE = Hi-Z)

When the PMODE pin is Hi-Z on power up, the device is latched into independent half-bridge control mode. This
mode allows for each half-bridge to be directly controlled in order to support high-side slow decay or driving two
independent loads. The truth table for independent half-bridge mode is shown in Table 5.
In independent half-bridge control mode, current sensing and feedback are still available, but the internal current
regulation is disabled since each half-bridge is operating independently. Additionally, if both low-side MOSFETs
are conducting current at the same time, the IPROPI scaled output will be the sum of the currents. See Current
Sense and Regulation for more information.

Table 5. Independent Half-Bridge Control Mode

nSLEEP INx OUTx DESCRIPTION
0 X Hi-Z Sleep, (H-Bridge Hi-Z)
1 0 L OUTx Low-Side On
1 1 H OUTx High-Side On

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7.3.3 Current Sense and Regulation

The DRV887x family of devices integrate current sensing, regulation, and feedback. These features allow for the
device to sense the output current without an external sense resistor or sense circuitry reducing system size,
cost, and complexity. This also allows for the devices to limit the output current in the case of motor stall or high
torque events and give detailed feedback to the controller about the load current through a current proportional
output.

7.3.3.1 Current Sensing

The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power
MOSFETs in the H-bridge scaled by AIPROPI. The IPROPI output current can be calculated by Equation 1. The
ILSx in Equation 1 is only valid when the current flows from drain to source in the low-side MOSFET. If current
flows from source to drain, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake,
slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side
MOSFETs.
IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) (1)
The current is measured by an internal current mirror architecture that removes the needs for an external power
sense resistor. Additionally, the current mirror architecture allows for the motor winding current to be sensed in
both the drive and brake low-side slow-decay periods allowing for continuous current monitoring in typical
bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed
because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in
either drive or slow-decay modes and measuring the current before switching back to coast mode again. In the
case of independent PWM mode and both low-side MOSFETs are carrying current, the IPROPI output will be the
sum of the two low-side MOSFET currents.
The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a
proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load
current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter
(ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full
range of the controller ADC is utilized. Additionally, the DRV887x devices implement an internal IPROPI voltage
clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of
output overcurrent or unexpected high current events.
The corresponding IPROPI voltage to the output current can be calculated by Equation 2.
VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) (2)

Control OUT
Inputs ILOAD

VREF
+ LS
±

IPROPI GND
Clamp
Integrated
Current Sense
MCU IPROPI IPROPI
ADC
+
VPROPI RIPROPI AIPROPI
±

Copyright © 2017, Texas Instruments Incorporated

Figure 11. Integrated Current Sensing

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The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the DRV887x internal current sensing
circuit. This time is the delay from the low-side MOSFET enable command to the IPROPI output being ready. If
the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side
MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output.

7.3.3.2 Current Regulation

The DRV887x family of devices integrate current regulation using either a fixed off-time or cycle-by-cycle PWM
current chopping scheme. The current chopping scheme is selectable through the IMODE quad-level input. This
allows the devices to limit the output current in case of motor stall, high torque, or other high current load events.
The IMODE level can be set by leaving the pin floating (Hi-Z), connecting the pin to GND, or connecting a
resistor between IMODE and GND. The IMODE pin state is latched when the device is enabled through the
nSLEEP pin. The IMODE state can be changed by taking the nSLEEP pin logic low, waiting the tSLEEP time,
changing the IMODE pin input, and then enabling the device by taking the nSLEEP pin back logic high. The
IMODE input is also used to select the device response to an overcurrent event. See more details in the
Protection Circuits section.
The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater
than GND (if current feedback is not required) or if current feedback is required, setting VVREF and RIPROPI such
that VIPROPI never reaches the VVREF threshold. In independent half-bridge control mode (PMODE = Hi-Z), the
internal current regulation is automatically disabled since the outputs are operating independently and the current
sense and regulation is shared between half-bridges.

Table 6. IMODE Functions

IMODE FUNCTION
nFAULT
IMODE STATE Current Chopping Overcurrent Response
Mode Response
Quad-Level 1 RIMODE = GND Fixed Off-Time Automatic Retry Overcurrent Only
Current Chopping and
Quad-Level 2 RIMODE = 20 kΩ to GND Cycle-By-Cycle Automatic Retry
Overcurrent
Current Chopping and
Quad-Level 3 RIMODE = 62 kΩ to GND Cycle-By-Cycle Outputs Latched Off
Overcurrent
Quad-Level 4 RIMODE = Hi-Z Fixed Off-Time Outputs Latched Off Overcurrent Only

The current chopping threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI
output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF
with an internal comparator.
ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) (3)
For example, if VVREF = 2.5 V, RIPROPI = 1500 Ω, and AIPROPI = 455 μA/A, then ITRIP will be approximately 3.66 A.
When the ITRIP threshold is exceeded, the outputs will enter a current chopping mode according to the IMODE
setting. The ITRIP comparator has both a blanking time (tBLK) and a deglitch time (tDEG). The internal blanking time
helps to prevent voltage and current transients during output switching from effecting the current regulation.
These transients may be caused by a capacitor inside the motor or on the connections to the motor terminals.
The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In
certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the
IPROPI pin, close to the DRV887x, will help filter the transients on IPROPI output so current regulation does not
prematurely trigger. The capacitor value can be adjusted as needed, however large capacitor values may slow
down the response time of the current regulation circuitry.
The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It
indicates the combined effect of offset error added to the IOUT current and gain error.

7.3.3.2.1 Fixed Off-Time Current Chopping

In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON)
for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs
unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of
brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs changes during the tOFF
time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs.

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The fixed off-time mode allows for a simple current chopping scheme without involvement from the external
controller. This is shown in Figure 12. Fixed off-time mode will support 100% duty cycle current regulation since
the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the
EN/IN1 or PH/IN2 pins to reset the outputs.

ITRIP
IOUT

VOUT

Control
Input
tOFF tOFF tOFF

Figure 12. Off-Time Current-Regulation

7.3.3.2.2 Cycle-By-Cycle Current Chopping

In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON)
after IOUT exceeds ITRIP until the next control input edge on the EN/IN1 or PH/IN2 pins. This allows for additional
control of the current chopping scheme by the external controller. This is shown in Figure 13. Cycle-by-cycle
mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the
outputs after the brake, low-side slow decay state has been entered.

ITRIP
IOUT

VOUT

Control
Input

Re-enable Re-enable

Figure 13. Cycle-By-Cycle Current Regulation

In cycle-by-cycle mode, the device will also indicate whenever the H-bridge enters internal current chopping by
pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control
inputs or the load has reached the ITRIP threshold. This is shown in Figure 14. nFAULT will be released whenever
the next control input edge is received by the device and the outputs are reset.

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Control
Input

ITRIP

IOUT Drive Decay Drive Chop Decay Drive

VOUT

VIPROPI

nFAULT

Figure 14. Cycle-By-Cycle Current Regulation Where nFAULT Acts as Current Chopping Indicator

No device functionality is affected when the nFAULT pin is pulled low for the current chopping indicator. The
nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device
fault (outlined in the Protection Circuits section) from the current chopping indicator, the nFAULT pin can be
compared with the control inputs. The current chopping indicator can only assert when the control inputs are
commanding a forward or reverse drive state (Figure 10). If the nFAULT pin behavior deviates from the operation
shown in Figure 14 then one of the following situations has occurred:
• If a device fault has occurred, then the nFAULT pin pulls low to indicate a fault condition rather than current
chopping. Depending on the device fault, nFAULT may remain low even when the control inputs are
commanding the high-Z or slow-decay states.
• When the control inputs transition from drive to slow decay, the nFAULT pin will go high for tBLK then be
pulled low again if IOUT > ITRIP. This may be caused by a PWM frequency or duty cycle on the control inputs
with a off-time that is too short for the IOUT current to decay below the ITRIP threshold. Figure 15 shows an
example of this condition. The condition IOUT > ITRIP can be viewed on an oscilloscope as VIPROPI > VREF.

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Chan. 1 = EN Chan. 2 = nFAULT

Chan. 3 = VREF Chan. 4 = IPROPI

Figure 15. nFAULT Pin When VIPROPI > VVREF with PH/EN Mode and PWM Signal on EN Pin

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7.3.4 Protection Circuits

The DRV887x family of devices are fully protected against supply undervoltage, charge pump undervoltage,
output overcurrent, and device overtemperature events.

7.3.4.1 VM Supply Undervoltage Lockout (UVLO)

If at any time the supply voltage on the VM pin falls below the undervoltage lockout threshold voltage (VUVLO), all
MOSFETs in the H-bridge will be disabled and the nFAULT pin driven low. The charge pump is disabled in this
condition. Normal operation will resume when the undervoltage condition is removed and VM rises above the
VUVLO threshold.

7.3.4.2 VCP Charge Pump Undervoltage Lockout (CPUV)

If at any time the charge pump voltage on the VCP pin falls below the undervoltage lockout threshold voltage
(VCPUV), all MOSFETs in the H-bridge will be disabled and the nFAULT pin driven low. Normal operation will
resume when the undervoltage condition is removed and VCP rises above the VCPUV threshold.

7.3.4.3 OUTx Overcurrent Protection (OCP)

An analog current limit circuit on each MOSFET limits the peak current out of the device even in hard short
circuit events.
If the output current exceeds the overcurrent threshold, IOCP, for longer than tOCP, all MOSFETs in the H-bridge
will be disabled and the nFAULT pin driven low. The overcurrent response can be configured through the IMODE
pin as shown in Table 6.
In automatic retry mode, the MOSFETs will be disabled and nFAULT pin driven low for a duration of tRETRY. After
tRETRY, the MOSFETs are re-enabled according to the state of the EN/IN1 and PH/IN2 pins. If the overcurrent
condition is still present, the cycle repeats; otherwise normal device operation resumes.
In latched off mode, the MOSFETs will remain disabled and nFAULT pin driven low until the device is reset
through either the nSLEEP pin or by removing the VM power supply.
In Independent Half-Bridge Control Mode (PMODE = Hi-Z), the OCP behavior is slightly modified. If an
overcurrent event is detected, only the corresponding half-bridge will be disabled and the nFAULT pin driven low.
The other half-bridge will continue normal operation. This allows for the device to manage independent fault
events when driving independent loads. If an overcurrent event is detected in both half-bridges, both half-bridges
will be disabled and the nFAULT pin driven low. In automatic retry mode, both half-bridges share the same
overcurrent retry timer. If an overcurrent event occurs first in one half-bridge and then later in the secondary half-
bridge, but before tRETRY has expired, the retry timer for the first half-bridge will be reset to tRETRY and both half-
bridges will enable again after the retry timer expires.

7.3.4.4 Thermal Shutdown (TSD)

If the die temperature exceeds the overtemperature limit TTSD, all MOSFET in the H-bridge will be disabled and
the nFAULT pin driven low. Normal operation will resume when the overtemperature condition is removed and
the die temperature drops below the TTSD threshold.

7.3.4.5 Fault Condition Summary

Table 7. Fault Condition Summary

FAULT CONDITION REPORT H-BRIDGE RECOVERY
CBC Mode & Active
ITRIP Indicator nFAULT Control Input Edge
IOUT > ITRIP Low-Side Slow Decay
VM Undervoltage Lockout (UVLO) VM < VUVLO nFAULT Disabled VM > VUVLO
VCP Undervoltage Lockout (CPUV) VCP < VCPUV nFAULT Disabled VCP > VCPUV
tRETRY or Reset
Overcurrent (OCP) IOUT > IOCP nFAULT Disabled
(Set by IMODE)
Thermal Shutdown (TSD) TJ > TTSD nFAULT Disabled TJ < TTSD – THYS

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7.3.5 Pin Diagrams

7.3.5.1 Logic-Level Inputs

Figure 16 shows the input structure for the logic-level input pins EN/IN1, PH/IN2, and nSLEEP.

100 k

Figure 16. Logic-Level Input

7.3.5.2 Tri-Level Inputs

Figure 17 shows the input structure for the tri-level input pin PMODE.

5V

+
156 k
±

+
44 k
±

Figure 17. PMODE Tri-Level Input

7.3.5.3 Quad-Level Inputs

Figure 18 shows the input structure for the quad-level input pin IMODE.

5V ±

+
68 k
±

+
136 k
±

Figure 18. Quad-Level Input

7.4 Device Functional Modes

The DRV887x family of devices have several different modes of operation depending on the system inputs.

7.4.1 Active Mode

After the supply voltage on the VM pin has crossed the undervoltage threshold VUVLO, the nSLEEP pin is logic
high, and tWAKE has elapsed, the device enters its active mode. In this mode, the H-bridge, charge pump, and
internal logic are active and the device is ready to receive inputs. The input control mode (PMODE) and current
control modes (IMODE) will be latched when the device enters active mode.

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Device Functional Modes (continued)

7.4.2 Low-Power Sleep Mode
The DRV887x family of devices support a low power mode to reduce current consumption from the VM pin when
the driver is not active. This mode is entered by setting the nSLEEP pin logic low and waiting for tSLEEP to elapse.
In sleep mode, the H-bridge, charge pump, internal 5-V regulator, and internal logic are disabled. The device
relies on a weak pulldown to ensure all of the internal MOSFETs remain disabled. The device will not respond to
any inputs besides nSLEEP while in low-power sleep mode.

7.4.3 Fault Mode

The DRV887x family of devices enter a fault mode when a fault is encountered. This is utilized to protect the
device and the output load. The device behavior in the fault mode is described in Table 7 and depends on the
fault condition. The device will leave the fault mode and re-enter the active mode when the recovery condition is
met.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DRV887x family of devices can be used in a variety of applications that require either a half-bridge or H-
bridge power stage configuration. Common application examples include brushed DC motors, solenoids, and
actuators. The device can also be utilized to drive many common passive loads such as LEDs, resistive
elements, relays, etc. The application examples below will highlight how to use the device in bidirectional current
control applications requiring an H-bridge driver and dual unidirectional current control applications requiring two
half-bridge drivers.

8.2 Typical Application

8.2.1 Primary Application
In the primary application example, the device is configured to drive a bidirectional current through an external
load (such as a brushed DC motor) using an H-bridge configuration. The H-bridge polarity and duty cycle are
controlled with a PWM and IO resource from the external controller to the EN/IN1 and PH/IN2 pins. The device is
configured for the PH/EN control mode by tying the PMODE pin to GND. The current limit threshold (ITRIP) is
generated with an external resistor divider from the control logic supply voltage (VCC). The device is configured
for the fixed off-time current regulation scheme by tying the IMODE pin to GND. The load current is monitored
with an ADC from the controller to detect the voltage across RIPROPI.
VCC

Controller 1 16
PWM EN/IN1 DRV887x PMODE
2 15
I/O PH/IN2 GND
VCC 3 14 0.022 …F
I/O nSLEEP CPL
10 k
4 13
I/O nFAULT CPH
Thermal
VREF 5 12 0.1 …F
Pad
ADC VREF VCP VM
6 11
IPROPI VM
RIPROPI 7 10 0.1 …F CBulk
IMODE OUT2
VCC 8 9
OUT1 PGND
RREF1
VREF
RREF2

BDC

Figure 19. Typical Application Schematic

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Typical Application (continued)

8.2.1.1 Design Requirements

Table 8. Design Parameters

REFERENCE DESIGN PARAMETER EXAMPLE VALUE
VM Motor and driver supply voltage 24 V
VCC Controller supply voltage 3.3 V
IRMS Output RMS current 0.5 A
fPWM Switching frequency 20 kHz
ITRIP Current regulation trip point 1A
AIPROPI Current sense scaling factor 455 µA/A
RIPROPI IPROPI external resistor 5.5 kΩ
VREF Current regulation reference voltage 2.5 V
VADC Controller ADC reference voltage 2.5 V
RREF1 VREF external resistor 16 kΩ
RREF2 VREF external resistor 50 kΩ
TA PCB ambient temperature –20 to 85 °C
TJ Device max junction temperature 150 °C
RθJA Device junction to ambient thermal resistance 35 °C/W

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Current Sense and Regulation

The DRV887x family of devices provide integrated regulation and sensing out the output current.
The current sense feedback is configured by scaling the RIPROPI resistor to properly sense the scaled down
output current from IPROPI within the dynamic voltage range of the controller ADC. An example of this is shown.
RIPROPI <= VADC / (ITRIP x AIPROPI) (4)
RIPROPI = 5.5 kΩ <= 2.5 V / (1 A x 455 µA/A) (5)
If VADC = 2.5 V, ITRIP = 1 A, and AIPROPI = 455 µA/A then to maximize the dynamic IPROPI voltage range an
RIPROPI of approximately 5.5 kΩ should be selected.
The accuracy tolerance of RIPROPI can be selected based on the application requirements. 10%, 5%, 1%, 0.1%
are all valid tolerance values. The typical recommendation is 1% for best tradeoff between performance and cost.
The output current regulation trip point (ITRIP) is configured with a combination of VREF and RIPROPI. Since RIPROPI
was previously calculated and AIPROPI is a constant, all the remains is to calculate VREF.
VREF = RIPROPI x (ITRIP x AIPROPI) (6)
VREF = 2.5 V = 5.5 kΩ x (1 A x 455 µA/A) (7)
If RIPROPI = 5.5 kΩ, ITRIP = 1 A, and AIPROPI = 455 µA/A then VREF should be set to 2.5 V.
VREF can be generated with a simple resistor divider (RREF1 and RREF2) from the controller supply voltage. The
resistor sizing can be achieved by selecting a value for RREF1 and calculating the required value for RREF2.

8.2.1.2.2 Power Dissipation and Output Current Capability

The output current and power dissipation capabilities of the device are heavily dependent on the PCB design and
external system conditions. This section provides some guidelines for calculating these values.
Total power dissipation for the device is composed of three main components. These are the quiescent supply
current dissipation, the power MOSFET switching losses. and the power MOSFET RDS(on) (conduction) losses.
While other factors may contribute additional power losses, these other items are typically insignificant compared
to the three main items.
PTOT = PVM + PSW + PRDS (8)
PVM can be calculated from the nominal supply voltage (VM) and the IVM active mode current specification.

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PVM = VM x IVM (9)

PVM = 0.096 W = 24 V x 4 mA (10)
PSW can be calculated from the nominal supply voltage (VM), average output current (IRMS), switching frequency
(fPWM) and the device output rise (tRISE) and fall (tFALL) time specifications.
PSW = PSW_RISE + PSW_FALL (11)
PSW_RISE = 0.5 x VM x IRMS x tRISE x fPWM (12)
PSW_FALL = 0.5 x VM x IRMS x tFALL x fPWM (13)
PSW_RISE = 0.018 W = 0.5 x 24 V x 0.5 A x 150 ns x 20 kHz (14)
PSW_FALL = 0.018 W = 0.5 x 24 V x 0.5 A x 150 ns x 20 kHz (15)
PSW = 0.036 W = 0.018 W + 0.018 W (16)
PRDS can be calculated from the device RDS(on) and average output current (IRMS)
PRDS = IRMS2 x (RDS(ON)_HS + RDS(ON)_LS) (17)
It should be noted that RDS(ON) has a strong correlation with the device temperature. A curve showing the
normalized RDS(on) with temperature can be found in the Typical Characteristics curves. Assuming a device
temperature of 85 °C it can be expected that RDS(on) will see an increase of ~1.25 based on the normalized
temperature data.
PRDS = 0.0625 W = (0.5 A)2 x (100 mΩ x 1.25 + 100 mΩ x 1.25) (18)
By adding together the different power dissipation components it can be verified that the expected power
dissipation and device junction temperature is within design targets.
PTOT = PVM + PSW + PRDS (19)
PTOT = 0.194 W = 0.096 W + 0.036 W + 0.0625 W (20)
The device junction temperature can be calculated with the PTOT, device ambient temperature (TA), and package
thermal resistance (RθJA). The value for RθJA is heavily dependent on the PCB design and copper heat sinking
around the device.
TJ = (PTOT x RθJA) + TA (21)
TJ = 92°C = (0.194 W x 35 °C/W) + 85°C (22)
It should be ensured that the device junction temperature is within the specified operating region. Other methods
exist for verifying the device junction temperature depending on the measurements available.
Additional information on motor driver current ratings and power dissipation can be found in Thermal
Performance and Related Documentation.

8.2.1.2.3 Thermal Performance

The datasheet-specified junction-to-ambient thermal resistance, RθJA, is primarily useful for comparing various
drivers or approximating thermal performance. However, the actual system performance may be better or worse
than this value depending on PCB stackup, routing, number of vias, and copper area around the thermal pad.
The length of time the driver drives a particular current will also impact power dissipation and thermal
performance. This section considers how to design for steady-state and transient thermal conditions.
The data in this section was simulated using the following criteria:
• 2-layer PCB, standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness.
• Top layer: DRV887x HTSSOP package footprint and copper plane heatsink. Top layer copper area is
varied in simulation.
• Bottom layer: ground plane thermally connected through vias under the thermal pad for DRV887x. Bottom
layer copper area varies with top copper area. Thermal vias are only present under the thermal pad (grid
pattern with 1.2mm spacing).
• 4-layer PCB, standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness.
• Top layer: DRV887x HTSSOP package footprint and copper plane heatsink. Top layer copper area is
varied in simulation. Inner planes were kept at 1-oz.
• Mid layer 1: GND plane thermally connected to DRV887x thermal pad through vias. The area of the
ground plane is 74.2 mm x 74.2 mm.
• Mid layer 2: power plane, no thermal connection.

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• Bottom layer: signal layer with small copper pad underneath DRV887x and thermally connected through
via stitching from the TOP and internal GND planes. Bottom layer thermal pad is the same size as the
package (5 mm x 4.4 mm). Bottom pad size remains constant as top copper plane is varied. Thermal vias
are only present under the thermal pad (grid pattern with 1.2mm spacing).
Figure 20 shows an example of the simulated board for the HTSSOP package. Table 9 shows the dimensions of
the board that were varied for each simulation.

Figure 20. HTSSOP PCB model top layer

Table 9. Dimension A for 16-pin PWP package

2
Cu area (mm ) Dimension A (mm)
2 16.43
4 22.35
8 30.68
16 42.42

8.2.1.2.3.1 Steady-State Thermal Performance

"Steady-state" conditions assume that the motor driver operates with a constant RMS current over a long period
of time. Figure 21, Figure 22, Figure 23, and Figure 24 show how RθJA and ΨJB (junction-to-board
characterization parameter) change depending on copper area, copper thickness, and number of layers of the
PCB for the HTSSOP package. More copper area, more layers, and thicker copper planes decrease RθJA and
ΨJB, which indicate better thermal performance from the PCB layout.

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40 11
4L 1oz 4L 1oz
38 4L 2oz 10.5 4L 2oz
10
36
9.5
34
RTJA (qC/W)

<JB (qC/W)
9
32
8.5
30
8
28
7.5
26 7

24 6.5
0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16
Top layer copper area (cm2) 4L_R
Top layer copper area (cm2) 4L_P

Figure 21. HTSSOP, 4-layer PCB junction-to-ambient Figure 22. HTSSOP, 4-layer PCB junction-to-board
thermal resistance vs copper area characterization parameter vs copper area

160 30
2L 1oz 2L 1oz
2L 2oz 27.5 2L 2oz
140
25
120 22.5

RTJA (qC/W)
RTJA (qC/W)

20
100
17.5
80
15

60 12.5
10
40
7.5
20 5
0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16
Top layer copper area (cm2) 2L_R
Top layer copper area (cm2) 2L_P

Figure 23. HTSSOP, 2-layer PCB junction-to-ambient Figure 24. HTSSOP, 2-layer PCB junction-to-board
thermal resistance vs copper area characterization parameter vs copper area

8.2.1.2.3.2 Transient Thermal Performance

The motor driver may experience different transient driving conditions that cause large currents to flow for a short
duration of time. These may include
• Motor start-up when the rotor is not yet spinning at full speed.
• Fault conditions when there is a supply or ground short to one of the motor outputs, and the device goes into
and out of overcurrent protection.
• Briefly energizing a motor or solenoid for a limited time, then de-energizing.
For these transient cases, the duration of drive time is another factor that impacts thermal performance. In
transient cases, the thermal impedance parameter ZθJA denotes the junction-to-ambient thermal performance.
Figure 25 and Figure 26 show the simulated thermal impedances for 1-oz and 2-oz copper layouts for the
HTSSOP package. These graphs indicate better thermal performance with short current pulses. For short
periods of drive time, the device die size and package dominates the thermal performance. For longer drive
pulses, board layout has a more significant impact on thermal performance. Both graphs show the curves for
thermal impedance split due to number of layers and copper area as the duration of the drive pulse duration
increases. Long pulses can be considered steady-state performance.

24 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

 DRV8874
www.ti.com SLVSF66A – AUGUST 2019 – REVISED DECEMBER 2019

100
70
50

30
20

10
ZTJA (qC/W)

7
5
2 cm^2, 4-layer
3 4 cm^2, 4-layer
8 cm^2, 4-layer
2
16 cm^2, 4-layer
2 cm^2, 2-layer
1 4 cm^2, 2-layer
8cm^2, 2-layer
0.7
16cm^2, 2-layer
0.5

0.3
0.2
0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.3 0.50.7 1 2 3 4 5 6 78 10 20 30 50 70 100 200300 500 1000
Pulse Duration (s) 1oz_

Figure 25. HTSSOP package junction-to-ambient thermal impedance for 1-oz copper layouts

100
70
50

30
20

10
ZTJA (qC/W)

7
5

3 2 cm^2, 4-layer
4 cm^2, 4-layer
2 8 cm^2, 4-layer
16 cm^2, 4-layer
1 2 cm^2, 2-layer
4 cm^2, 2-layer
0.7 8cm^2, 2-layer
0.5 16cm^2, 2-layer

0.3
0.2
0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.3 0.50.7 1 2 3 4 5 6 78 10 20 30 50 70 100 200300 500 1000
Pulse Duration (s) 2oz_

Figure 26. HTSSOP package Junction-to-ambient thermal impedance for 2-oz copper layouts

Copyright © 2019, Texas Instruments Incorporated Submit Documentation Feedback 25

DRV8874
SLVSF66A – AUGUST 2019 – REVISED DECEMBER 2019 www.ti.com

8.2.1.3 Application Curves

Chan. 1 = VM Chan. 2 = nFAULT Chan. 3 = nSLEEP Chan. 1 = VM Chan. 2 = nFAULT Chan. 3 = nSLEEP
Chan. 4 = IOUT Chan. 4 = IOUT

Figure 27. Device Power-up with Supply Voltage (VM) Figure 28. Device Power-up with nSLEEP
Ramp

Chan. 1 = OUT1 Chan. 2 = OUT2 Chan. 3 = EN/IN1 Chan. 1 = OUT1 Chan. 2 = OUT2 Chan. 3 = IPROPI
Chan. 4 = IOUT Chan. 4 = IOUT

Figure 29. Driver PWM Operation (PH/EN) Figure 30. Driver PWM Operation With Current Feedback

26 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

 DRV8874
www.ti.com SLVSF66A – AUGUST 2019 – REVISED DECEMBER 2019

Chan. 1 = OUT1 Chan. 2 = OUT2 Chan. 3 = EN/IN1 Chan. 1 = OUT1 Chan. 2 = OUT2 Chan. 3 = EN/IN1
Chan. 4 = IOUT Chan. 4 = IOUT

Figure 31. Driver PWM Operation With Current Chopping Figure 32. Driver Full On Operation With Current Chopping

8.2.2 Alternative Application

In the alternative application example, the device is configured to drive a unidirectional current through two
external loads (such as two brushed DC motors) using a dual half-bridge configuration. The duty cycle of each
half-bridge is controlled with a PWM resource from the external controller to the EN/IN1 and PH/IN2 pins. The
device is configured for the independent half-bridge control mode by leaving the PMODE pin floating. Since the
current regulation scheme is disabled in the independent half-bridge control mode, the VREF pin is tied to VCC.
The combined load current is monitored with an ADC from the controller to detect the voltage across RIPROPI.
VCC

Controller 1 16
PWM EN/IN1 DRV887x PMODE X
2 15
PWM PH/IN2 GND
VCC 3 14 0.022 …F
I/O nSLEEP CPL
10 k
4 13
I/O nFAULT CPH
Thermal
VCC 5 12 0.1 …F
Pad
ADC VREF VCP VM
6 11
IPROPI VM
RIPROPI 7 10 0.1 …F CBulk
IMODE OUT2
8 9
OUT1 PGND

VM VM

BDC BDC

Figure 33. Typical Application Schematic

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DRV8874
SLVSF66A – AUGUST 2019 – REVISED DECEMBER 2019 www.ti.com

8.2.2.1 Design Requirements

Table 10. Design Parameters

REFERENCE DESIGN PARAMETER EXAMPLE VALUE
VM Motor and driver supply voltage 24 V
VCC Controller supply voltage 3.3 V
IRMS1 Output 1 RMS current 0.5 A
IPEAK1 Output 1 peak current 1A
IRMS2 Output 2 RMS current 0.25 A
IPEAK2 Output 2 peak current 0.5 A
fPWM Switching frequency 20 kHz
AIPROPI Current sense scaling factor 455 µA/A
RIPROPI IPROPI external resistor 4.8 kΩ
VADC Controller ADC reference voltage 3.3 V
TA PCB ambient temperature –20 to 85 °C
TJ Device max junction temperature 150 °C
RθJA Device junction to ambient thermal resistance 35 °C/W

8.2.2.2 Detailed Design Procedure

Refer to the Primary Application Detailed Design Procedure section for a detailed design procedure example.
The majority of the design concepts apply to the alternative application example. A few changes to the procedure
are outlined below.

8.2.2.2.1 Current Sense and Regulation

In the alternative application for two half-bridge loads, the IPROPI output will be the combination of the two
outputs currents. The current sense feedback resistor RIPROPI should be scaled appropriately to stay within the
dynamic voltage range of the controller ADC. An example of this is shown
RIPROPI <= VADC / ((IPEAK1 + IPEAK2) x AIPROPI) (23)
RIPROPI = 4.8 kΩ <= 3.3 V / ((1 A + 0.5 A) x 455 µA/A) (24)
If VADC = 3.3 V, IPEAK1 = 1 A, IPEAK2 = 0.5 A, and AIPROPI = then to maximize the dynamic IPROPI voltage range
an RIPROPI of approximately 4.8 kΩ should be selected.
The accuracy tolerance of RIPROPI can be selected based on the application requirements. 10%, 5%, 1%, 0.1%
are all valid tolerance values. The typical recommendation is 1% for best tradeoff between performance and cost.
In independent half-bridge mode, the internal current regulation of the device is disabled. VREF can be set directly
to the supply reference for the controller ADC.

28 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

 DRV8874
www.ti.com SLVSF66A – AUGUST 2019 – REVISED DECEMBER 2019

8.2.2.3 Application Curves

Chan. 1 = OUT1 Chan. 2 = OUT2 Chan. 3 = EN/IN1 Chan. 1 = OUT1 Chan. 2 = OUT2 Chan. 3 = EN/IN1
Chan. 4 = PH/IN2 Chan. 4 = PH/IN2

Figure 34. Independent Half-Bridge PWM Operation Figure 35. Independent Half-Bridge PWM Operation

Copyright © 2019, Texas Instruments Incorporated Submit Documentation Feedback 29

DRV8874
SLVSF66A – AUGUST 2019 – REVISED DECEMBER 2019 www.ti.com

9 Power Supply Recommendations

9.1 Bulk Capacitance

Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk
capacitance is generally beneficial, while the disadvantages are increased cost and physical size.
The amount of local bulk capacitance needed depends on a variety of factors, including:
• The highest current required by the motor or load
• The capacitance of the power supply and ability to source current
• The amount of parasitic inductance between the power supply and motor system
• The acceptable voltage ripple of the system
• The motor braking method (if applicable)
The inductance between the power supply and motor drive system limits how the rate current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended minimum value, but system level testing is required to
determine the appropriately sized bulk capacitor.

Parasitic Wire
Inductance
Power Supply Motor Drive System

VBB

+ + Motor
± Driver

GND

Local IC Bypass
Bulk Capacitor Capacitor

Figure 36. System Supply Parasitics Example

30 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

 DRV8874
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10 Layout

10.1 Layout Guidelines

Since the DRV887x family of devices are integrated power MOSFETs device capable of driving high current,
careful attention should be paid to the layout design and external component placement. Some design and layout
guidelines are provided below.
• Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor, the VCP to VM charge
pump storage capacitor, and the charge pump flying capacitor. X5R and X7R types are recommended.
• The VM power supply and VCP, CPH, CPL charge pump capacitors should be placed as close to the device
as possible to minimize the loop inductance.
• The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close
as possible to the device to minimize the loop inductance.
• VM, OUT1, OUT2, and PGND carry the high current from the power supply to the outputs and back to
ground. Thick metal routing should be utilized for these traces as is feasible.
• PGND and GND should connect together directly on the PCB ground plane. They are not intended to be
isolated from each other.
• The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane
(when available) through thermal vias to maximize the PCB heat sinking.
• A recommended land pattern for the thermal vias is provided in the package drawing section.
• The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking.

10.2 Layout Example

10.2.1 HTSSOP Layout Example

EN/IN1 1 16 PMODE

PH/IN2 2 15 GND

nSLEEP 3 14 CPL
0.022 …F
nFAULT 4 13 CPH
Thermal
Pad
VREF 5 12 VCP
0.1 …F
VIPROPI IPROPI 6 11 VM VM
RIPROPI 0.1 …F CBULK
IMODE 7 10 OUT2

OUT1 8 9 PGND

MOT+ MOT-

Figure 37. HTSSOP (PWP) Example Layout

Copyright © 2019, Texas Instruments Incorporated Submit Documentation Feedback 31

DRV8874
SLVSF66A – AUGUST 2019 – REVISED DECEMBER 2019 www.ti.com

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Calculating Motor Driver Power Dissipation application report
• Texas Instruments, Current Recirculation and Decay Modes application report
• Texas Instruments, PowerPAD™ Made Easy application report
• Texas Instruments, PowerPAD™ Thermally Enhanced Package application report
• Texas Instruments, Understanding Motor Driver Current Ratings application report
• Texas Instruments, Best Practices for Board Layout of Motor Drivers application report
• Texas Instruments, Motor Drives Layout Guide application report
• Texas Instruments, DRV8874 Evaluation Module (EVM) tool folder

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

32 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

 DRV8874
www.ti.com SLVSF66A – AUGUST 2019 – REVISED DECEMBER 2019

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2019, Texas Instruments Incorporated Submit Documentation Feedback 33

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

DRV8874PWPR ACTIVE HTSSOP PWP 16 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 8874

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF DRV8874 :

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

• Automotive: DRV8874-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Apr-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8874PWPR HTSSOP PWP 16 3000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Apr-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DRV8874PWPR HTSSOP PWP 16 3000 367.0 367.0 38.0

Pack Materials-Page 2
 PACKAGE OUTLINE
PWP0016J SCALE 2.500
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

6.6 C SEATING
TYP PLANE
6.2
A 0.1 C
PIN 1 INDEX
AREA
14X 0.65
16
1

2X
5.1
4.55
4.9
NOTE 3

8
9
4.5 0.30
B 16X
4.3 0.19
0.1 C A B

(0.15) TYP

SEE DETAIL A

8 9

0.25
3.55 GAGE PLANE 1.2 MAX
2.68

0.75 0.15
0 -8 0.50 0.05
1 16 DETAIL A
A 20

TYPICAL
2.46 THERMAL
1.75 PAD

4223595/A 03/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PWP0016J TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

(3.4)
NOTE 8 METAL COVERED
(2.46) BY SOLDER MASK
16X (1.5)
SYMM SEE DETAILS

16X (0.45) 1 16

(1.3) TYP
(R0.05) TYP

SYMM (0.65)
(3.55) (5)
NOTE 8
14X (0.65)

( 0.2) TYP
VIA 8 9

SOLDER MASK (1.35) TYP

DEFINED PAD
(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
15.000

4223595/A 03/2017
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
8. Size of metal pad may vary due to creepage requirement.
9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
PWP0016J TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

(2.46)
16X (1.5) BASED ON METAL COVERED
0.125 THICK BY SOLDER MASK
STENCIL

16X (0.45) 1 16

(R0.05) TYP

SYMM (3.55)
BASED ON
0.125 THICK
STENCIL
14X (0.65)

8 9

SYMM SEE TABLE FOR

DIFFERENT OPENINGS
FOR OTHER STENCIL
(5.8) THICKNESSES

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 2.75 X 3.97
0.125 2.46 X 3.55 (SHOWN)
0.15 2.25 X 3.24
0.175 2.08 X 3.00

4223595/A 03/2017
NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.

www.ti.com
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