Low-Noise Programmable Linear Hall Effect Sensors With Adjustable Bandwidth (50 KHZ Maximum) and Analog Output

A1360, A1361, and A1362
Low-Noise Programmable Linear Hall Effect Sensors with

Adjustable Bandwidth (50 kHz Maximum) and Analog Output
Features and Benefits Description
• 1 mm case thickness provides greater coupling for current New applications for linear output Hall effect sensors, such
sensing applications
as current measurement, require both high accuracy and
• Customer programmable offset and sensitivity
• Factory programmed 0% / °C sensitivity temperature coefficient increased sensor bandwidth. The Allegro® A1360, A1361, and
• Programmability at end-of-line A1362 programmable linear Hall effect sensors are designed
• Selectable unipolar or bipolar quiescent voltage levels specifically to achieve both goals. Available in a through-hole
• Selectable sensitivity ranges between 0.7 and 1.4 mV/G (A1360), SIP (single in-line package), the A136x Hall effect sensors
1.4 to 4.5 mV/G (A1361) and 4.5 to 16 mV/G (A1362) are sensitive and temperature-stable. The accuracy of these
• Device bandwidth selectable under 50 kHz, via capacitor on devices is enhanced via programmability on the device VOUT
FILTER pin pin. A capacitor to ground on the FILTER pin on the A136x
• Ratiometric sensitivity, quiescent voltage output, and clamps for can be used to tune the device bandwidth in a range less than
interfacing with application DAC
50 kHz.
• Temperature-stable quiescent voltage output and sensitivity
• Precise recoverability after temperature cycling These ratiometric Hall effect sensors provide a voltage
• Output voltage clamps provide short circuit diagnostic capabilities output that is proportional to the applied magnetic field. The
• Wide ambient temperature range: – 40°C to 150°C quiescent output voltage is user-adjustable around either
• Resistant to mechanical stress
50% (bidirectional configuration) or 10% (unidirectional
Package: 4 pin SIP (suffix KT) configuration) of the supply voltage, VCC. The device sensitivity
is adjustable within three guaranteed ranges: 0.7 to 1.4 mV/G
(A1360), 1.4 to 4.5 mV/G (A1361), and 4.5 to 16 mV/G
1 mm case thickness (A1362).
Each BiCMOS monolithic circuit integrates a Hall element,
temperature-compensation circuitry to reduce the intrinsic
sensitivity drift of the Hall element, a small-signal high-gain
amplifier, a clamped low-impedance output stage, and a
proprietary dynamic offset cancellation technique.
Not to scale Continued on the next page…
Functional Block Diagram

V+
VCC
To subcircuits
Ratiometric Program/Lock
Hall Drive
Trim Control
Sensitivity
Sensitivity Temperature Offset FILTER
Coefficient
C.BYPASS
Dynamic Offset
+
Cancellation
+
Signal Recovery – VOUT
– (Programming)
GND
A1360-DS
A1360, A1361, Low-Noise Programmable Linear Hall Effect Sensors with
and A1362 Adjustable Bandwidth (50 kHz Maximum) and Analog Output
Description (continued)
The features of these linear Hall effect sensors make them ideal for are provided in an extremely thin case (1 mm thick), 4-pin SIP
meeting high accuracy requirements in automotive and industrial (single in-line package, suffix KT) that is lead (Pb) free, with 100%
applications. Device specifications are guaranteed over an extended matte tin leadframe plating.
ambient temperature range: –40 °C to 150 °C. The A136x sensors
Selection Guide1
Sensitivity Range
Part Number Packing2
(mV/G)
A1360LKTTN-T 4000 pieces per 13-in. reel 0.7 to 1.4
A1361LKTTN-T 4000 pieces per 13-in. reel 1.4 to 4.5
A1362LKTTN-T 4000 pieces per 13-in. reel 4.5 to 16
1All variants are programmable for unidirectional or bidirectional use.
2Contact Allegro for additional packing options.
Absolute Maximum Ratings

Characteristic Symbol Notes Rating Units
Forward Supply Voltage VCC 8 V
Reverse Supply Voltage VRCC –0.1 V
Forward Output Voltage VOUT 28 V
Reverse Output Voltage VROUT –0.1 V
Forward Filter Voltage VFILTER 8 V
Reverse Filter Voltage VRFILTER –0.1 V
Output Source Current IOUT(SOURCE) VOUT to GND 3 mA
Output Sink Current IOUT(SINK) VCC to VOUT 10 mA
Ambient Operating Temperature TA Range L –40 to 150 °C
Storage Temperature Tstg –65 to 165 °C
Junction Temperature TJ(max) 165 °C
Pin-out Diagram Terminal List Table

Number Name Description
1 VCC Input power supply; use bypass capacitor to connect to ground
2 VOUT Output signal; also used for programming
3 FILTER Terminal for external filter capacitor for bandwidth setting
4 GND Ground
1 2 3 4
Allegro MicroSystems, Inc. 2

115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
OPERATING CHARACTERISTICS valid over full operating temperature range, TA; CBYPASS = 0.1 μF, VCC = 5 V, unless otherwise specified
Characteristic Symbol Test Conditions Min. Typ. Max. Units
Electrical Characteristics
Supply Voltage VCC 4.5 5.0 5.5 V
Supply Current ICC No load on VOUT – 9.2 12 mA
TA = 25°C, CL (of test probe) = 10 pF, CBYPASS =
Power-On Time1 tPO – 30 – μs
open; Sens = 4.5 mV/G
Supply Zener Clamp Voltage VZ TA = 25°C, ICC = 13 mA 6 7.6 – V
Small signal –3 dB, 100 G(P-P) magnetic input
Internal Bandwidth BWi 50 – – kHz
signal, CFILTER = open, CL = 10 nF
Small signal –3 dB, 100 G(P-P) magnetic input
Filtered Bandwidth BWf – – 50 kHz
signal, CFILTER = 1 nF, CL = 10 nF
Chopping Frequency2 fC TA = 25°C – 210 – kHz
Output Characteristics
TA = 25°C, impulse magnetic field of 400 G,
Propagation Delay Time1 tpd – 2 – μs
CFILTER = open, CL = 10 nF
Rise Time1 tr – 7 – μs
Response Time1 tRESPONSE TA = 25°C, CL = 10 nF – 9 – μs
Delay to Clamp1 tCLP – 30 – μs
A1360 4.73 4.76 4.79 V
TA = 25°C, B = 600 G, Sens = 5.0
VCLP(HIGH) A1361 4.73 4.76 4.79 V
mV/G, RL(PULLDWN) = 10 kΩ
A1362 4.67 4.8 4.91 V
Output Voltage Clamp3
A1360 0.30 0.32 0.34 V
TA = 25°C, B = 600 G, Sens = 5.0
VCLP(LOW) A1361 0.30 0.32 0.34 V
mV/G, RL(PULLUP) = 10 kΩ
A1362 0.30 0.32 0.34 V
TA = 25°C, CL = 10 nF, Sens = 1.5 mV/G,
– 8 – mV
CFILTER = 1 nF (BWf = 50 kHz)
TA = 25°C, CL = 10 nF, Sens = 6.6 mV/G,
Noise (peak-to-peak)4 VN(p-p) – 8.5 – mV
TA = 25°C, CL = 10 nF, Sens = 6.6 mV/G,
– 38 – mV
DC Output Resistance ROUT – <1 – Ω
RL(PULLUP) VOUT to VCC 4.7 – – kΩ
Output Load Resistance
RL (PULLDWN) VOUT to GND 4.7 – – kΩ
Output Load Capacitance CL VOUT to GND – – 10 nF
CL = 10 nF, CFLITER = 1 nF (BW = 50 kHz),
Phase Shift5 ΔΦ magnetic input signal frequency = 1 kHz with – 2.5 – deg.
1 V(p-p) output signal
Output Slew Rate6 SR Sens = 4.5 mV/G, CL = 10 nF – 210 – V/ms
Continued on the next page…

OPERATING CHARACTERISTICS (continued) valid over full operating temperature range, TA; CBYPASS = 0.1 μF, VCC = 5 V, unless otherwise specified
Pre-Programming Target7
Pre-Programming Quiescent
VOUT(Q)PRE B = 0 G, TA = 25°C – 2.0 – V
Voltage Output
A1360 – 0.5 – mV/G
Pre-Programming Sensitivity SensPRE A1361 TA = 25°C – 1.1 – mV/G
A1362 – 2.7 – mV/G
Quiescent Voltage Output Programming
VOUT(Q)UNIinit – VCLP(LOW) – V
Initial Quiescent Voltage Output8 B = 0 G, TA = 25°C
VOUT(Q)BIinit – VOUT(Q)PRE – V
Coarse Quiescent Voltage Output
– 1 – bit
Programming Bits9
Guaranteed Quiescent Voltage VOUT(Q)UNI 0.40 – 1.15 V
B = 0 G, TA = 25°C
Output Range3,10 VOUT(Q)BI 2.15 – 2.85 V
Quiescent Voltage Output
– 8 – bit
Programming Bits
Average Quiescent Voltage
StepVOUT(Q) TA = 25°C 3.6 3.85 4.1 mV
Output Step Size11,12
Quiescent Output Voltage StepVOUT(Q) ×
ErrPGVOUT(Q) TA = 25°C – – mV
Programming Resolution13 ±0.5
Sensitivity Programming
Initial Sensitivity Sensinit TA = 25°C – SensPRE – mV/G
A1360 0.7 – 1.4 mV/G
Guaranteed Sensitivity Range3,14 Sens A1361 TA = 25°C 1.4 – 4.5 mV/G
A1362 4.5 – 16 mV/G
Sensitivity Programming Bits – 8 – bit
A1360 4.6 5.3 6.0 μV/G
Average Sensitivity Step Size11.12 StepSENS A1361 TA = 25°C 15 16 17 μV/G
A1362 74 79 83 μV/G
Sensitivity Programming StepSENS ×
ErrPGSENS TA = 25°C – – μV/G
Resolution13 ±0.5
Lock Bit Programming
Overall Programming Lock Bit LOCK – 1 – bit
Factory-Programmed Sensitivity Temperature Coefficient
Sensitivity Temperature
TCSENS –0.025 0 0.025 %/°C
Coefficient15
Error Components
A1360 –2.5 – 2.5 %
Linearity Sensitivity Error16 LinERR A1361 –1.1 – 1.1 %
A1362 –1 – 1 %
A1360 –3 – 3 %
Symmetry Sensitivity Error17 SymERR A1361 –2 – 2 %
A1362 –1 – 1 %
Ratiometry Quiescent Voltage
RatERRVOUT(Q) – < ±1.5 – %
Output Error18
Ratiometry Sensitivity Error18 RatERRSENS – < ±1.5 – %
Ratiometry Clamp Error19 RatSENSCLP TA = 25°C – < ±1.5 – %
Continued on the next page…

OPERATING CHARACTERISTICS (continued) valid over full operating temperature range, TA; CBYPASS = 0.1 μF, VCC = 5 V, unless otherwise specified
Drift Characteristics
A1360 –10 – 34 mV
A1361 VOUT(Q) = VOUT(Q)(min) –13 – 3 mV
Quiescent Voltage Output Drift A1362 –17 – 5 mV
∆VOUT(Q)
Through Temperature Range1 A1360 –26 – 35 mV
A1361 VOUT(Q) = VOUT(Q)(max) –29 – 21 mV
A1362 –26 – 5 mV
Sensitivity Drift Due to Package
∆SensPKG TA = 25°C, after temperature cycling – < ±1 – %
Hysteresis1
1 See Characteristic Definitions section.
2 fC varies up to approximately ±20% over the full operating ambient temperature range, TA, and process.
3 Sens, V
OUT(Q), VCLP(LOW), and VCLP(HIGH) scale with VCC due to ratiometry.
4 Noise is dependent on the sensitivity of the device and the filter capacitance. An 8 mV peak-to-peak noise floor exists that is independent of device sensitivity. This noise
floor attenuates proportionate to the filter capacitance (and device bandwidth).

5 Unit of measure (phase degrees) in reference to the magnetic input signal.
6 High-to-low transition of output voltage is a function of external load components and device sensitivity.
7 Raw device characteristic values before any programming.
8V
OUT(Q)UNIinit typically starts below the lower clamp voltage, VCLP(LOW). When programming the fine quiescent duty cycle for this parameter, several codes may need to be
addressed before VOUT(Q)UNI can be measured above VCLP(LOW).
9 Bits for selecting between V
OUT(Q)UNI and VOUT(Q)BI programming ranges.
10 V
OUT(Q)(max) is the value available with all programming fuses blown (maximum programming code set). The VOUT(Q) range is the total range from VOUT(Q)init up to and
including VOUT(Q)(max). See Characteristic Definitions section. Quiescent Voltage Output may drift by an additional ±10 mV over the lifetime of this product.
11 Step size is larger than required, in order to provide for manufacturing spread. See Characteristic Definitions section.
12 Non-ideal behavior in the programming DAC can cause the step size at each significant bit rollover code to be greater than twice the maximum specified value of
StepVOUT(Q) or StepSENS.
13 Overall programming value accuracy. See Characteristic Definitions section.
14 Sens(max) is the value available with all programming fuses blown (maximum programming code set). Sens range is the total range from Sens
init up to and including
Sens(max). See Characteristic Definitions section. Sensitivity may drift by an additional ±2% over the lifetime of this product.
15 Programmed at 150°C and calculated relative to 25°C.
16 Linearity is only guaranteed for output voltage ranges of ±2 V from the quiescent output for bidirectional devices and +2 V from the quiescent output for unidirectional
devices. These linearity ranges are only valid within the operating output range of the device. The operating output range is confined to the region between the output clamps.
Linearity may shift by up to +/- 1 % over the lifetime of this product.
17 Symmetry error is only valid for bidirectional devices. Symmetry may shift by up to ±1% over the lifetime of this product.
18 Percent change from actual value at V
CC = 5 V, for a given temperature, over the guaranteed supply voltage operating range.
19 Percent change from actual value at V
CC = 5 V, TA = 25°C, over the guaranteed supply voltage operating range.

Thermal Characteristics may require derating at maximum conditions

Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance RθJA 1-layer PCB with copper limited to solder pads 174 ºC/W
*Additional thermal information available on Allegro website.
Power Dissipation versus Ambient Temperature

900
800
700
600
Power Dissipation, PD (mW)
(R
QJ
500
A
=
17
4
ºC
400
/W
)
300
200
100
0
20 40 60 80 100 120 140 160 180
Temperature, TA (°C)

Characteristic Data
Bandwidth Range
100
BW(max)
10
Bandwidth, BW (kHz)
Guaranteed
Range
1
0.1 BW(min)
0.01
0.1 1 10 100 1000 10,000
Capacitance External Capacitor on FILTER Pin, CF (nF)
Step Response
Sens = 2.2 mV/G
Output (mV)
350 G
Excitation Signal

Noise versus Filter Capacitance

Sens = 6.6 mV/G
50
45
40
35
30
Vn(p-p) (mV)
25
20
15
10
5
0
0 100 200 300 400 500
CF (nF)
Power On Time versus Filter Capacitance

Unidirectional Device
180
160
140
120
100
B = 300 G
tPO (μs)
80
60
40
20
0
0 10 20 30 40 50
CF (nF)
Power On Time versus Filter Capacitance

Bidirectional Device
250
200
B = 300 G
150
tPO (μs)
B=0G
100
50
0
0 10 20 30 40 50
CF (nF)

Characteristic Definitions
Power-On Time When the supply is ramped to its operating volt- Rise Time (tr) The time interval between a) when the sensor
age, the device requires a finite time to power its internal com- reaches 10% of its full scale value, and b) when it reaches 90%
ponents before responding to an input magnetic field. Power-On of its full scale value. The rise time to a step response is used to
Time, tPO , is defined as: the time it takes for the output voltage derive the bandwidth of the linear sensor, in which ƒ(–3 dB) =
to settle within ±10% of its steady state value under an applied 0.35 / tr. Both tr and tRESPONSE are detrimentally affected by eddy
magnetic field, after the power supply has reached its minimum current losses observed in the conductive IC ground plane.
specified operating voltage, VCC(min), as shown in the following
chart.
V
VCC
VCC(typ.)
VOUT
90% VOUT
(%) Applied Magnetic Field
VCC(min.) 90
tPO
t1 t2
Transducer Output
t1= time at which power supply reaches 10
minimum specified operating voltage 0
t
Rise Time, tr
t2= time at which output voltage settles
within ±10% of its steady state value
under an applied magnetic field
0
+t
Propagation Delay Time (tpd) The time required for the sensor Response Time (tRESPONSE) The time interval between a) when
output to reflect a change in the applied magnetic field. Propaga- the applied magnetic field reaches 90% of its final value, and b)
tion delay can be considered as a fixed time offset and may be when the sensor reaches 90% of its output corresponding to the
compensated. applied magnetic field.
(%) Applied Magnetic Field (%) Applied Magnetic Field
90 90
Transducer Output Transducer Output
0 0
t t
Propagation Delay Time, tpd Response Time, tRESPONSE

Delay to Clamp A large magnetic input step may cause the clamp Average Quiescent Voltage Output Step Size The average qui-
to overshoot its steady state value. The Delay to Clamp, tCLP , is escent voltage output step size for a single device is determined
defined as: the time it takes for the output voltage to settle within using the following calculation:
±1% of its steady state value, after initially passing through its VOUT(Q)maxcode –VOUT(Q)init
steady state voltage, as shown in the following chart. StepVOUT(Q) = . (1)
2n–1
V Magnetic Input where:
n is the number of available programming bits in the trim range,
VCLP(HIGH)
VOUT
2n–1 is the value of the maximum programming code in the
tCLP range, and
VOUT(Q)maxcode is the quiescent voltage output at code 2n–1.
t1 t2
Quiescent Voltage Output Programming Resolution The
programming resolution for any device is half of its programming
step size. Therefore, the typical programming resolution will be:
t1= time at which output voltage initially
reaches steady state clamp voltage ErrPGVOUT(Q)(typ) = 0.5 × Step .
VOUT(Q)(typ)
t2= time at which output voltage settles to (2)
within 1% of steady state clamp voltage
Quiescent Voltage Output Drift Through Temperature Range
Note: Times apply to both high clamp
(shown) and low clamp. Due to internal component tolerances and thermal considerations,
the quiescent voltage output, VOUT(Q), may drift from its nominal
0 value over the operating ambient temperature, TA. For purposes
t
of specification, the Quiescent Voltage Output Drift Through
Temperature Range, ∆VOUT(Q) (mV), is defined as:
Quiescent Voltage Output In the quiescent state (no significant
magnetic field: B = 0 G), the output, VOUT(Q), has a constant ratio ∆VOUT(Q) = VOUT(Q)(TA) –VOUT(Q)(25°C) . (3)
to the supply voltage, VCC, throughout the entire operating ranges
of VCC and ambient temperature, TA. VOUT(Q), should be calculated using the actual measured values
Guaranteed Quiescent Voltage Output Range The quiescent of VOUT(Q)(TA) and VOUT(Q)(25°C) , rather than programming target
voltage output, VOUT(Q), can be programmed around its nominal values.
value of 2.5 V, within the guaranteed quiescent voltage range Sensitivity The presence of a south polarity magnetic field, per-
limits: VOUT(Q)(min) and VOUT(Q)(max). The available guaranteed pendicular to the branded surface of the package face, increases
programming range for VOUT(Q) falls within the distributions of the output voltage from its quiescent value toward the supply
the initial, VOUT(Q)init, and the maximum programming code for voltage rail. The amount of the output voltage increase is propor-
setting VOUT(Q), as shown in the following diagram. tional to the magnitude of the magnetic field applied. Conversely,
the application of a north polarity field decreases the output
voltage from its quiescent value. This proportionality is specified
VOUT(Q)init(typ) as the magnetic sensitivity, Sens (mV/G), of the device, and it is
defined for bipolar devices as:
Guaranteed Output
Programming VOUT(BPOS) – VOUT(BNEG)
Range, VOUT(Q) Sens = , (4)
BPOS – BNEG
and for unipolar devices as:
Distribution for Distribution for
VOUT(Q)init Max Code VOUT(Q) VOUT(BPOS) – VOUT(Q)
Sens = , (5)
VOUT(Q)(min) VOUT(Q)(max) BPOS
where BPOS and BNEG are two magnetic fields with opposite
polarities.

Guaranteed Sensitivity Range The magnetic sensitivity, Sens, where Sens(25°C)1 is the programmed value of sensitiv-
can be programmed around its nominal value, 0.7 to 16 mV/G ity at TA = 25°C, and Sens(25°C)2 is the value of sensitivity at
depending on device type, within the sensitivity range limits:
Sens(min) and Sens(max). Refer to the Guaranteed Quiescent TA = 25°C, after temperature cycling TA up to 150°C, down to
Voltage Output Range section for a conceptual explanation of –40°C, and back to up 25°C.
how value distributions and ranges are related.
Linearity Sensitivity Error The 136x family is designed to
Average Sensitivity Step Size Refer to the Average Quiescent
provide a linear output in response to a ramping applied magnetic
Voltage Output Step Size section for a conceptual explanation.
field. Consider two magnetic fields, B1 and B2. Ideally, the sen-
Sensitivity Programming Resolution Refer to the Quiescent
Voltage Output Programming Resolution section for a conceptual sitivity of a device is the same for both fields, for a given supply
explanation. voltage and temperature. Linearity error is present when there is a
Sensitivity Temperature Coefficient Device sensitivity changes difference between the sensitivities measured at B1 and B2.
as temperature changes, with respect to its programmed sensitiv-
Linearity Error is calculated separately for the positive
ity temperature coefficient, TCSENS. TCSENS is programmed at
150°C, and calculated relative to the nominal sensitivity program- (LinERRPOS) and negative (LinERRNEG ) applied magnetic fields.
ming temperature of 25°C. TCSENS (%/°C) is defined as: Linearity error (%) is measured and defined as:
⎛SensT2 – SensT1 ⎞⎛ 1 ⎞
TCSens = ⎜⎜ × 100%⎟⎟ ⎜⎜ ⎟⎟ , (6) ⎛ SensBPOS2 ⎞
⎝ SensT1 ⎠ ⎝T2–T1⎠ LinERRPOS = ⎜⎜1– ⎟⎟ × 100% ,
⎝ SensBPOS1 ⎠
where T1 is the nominal Sens programming temperature of 25°C, (9)
and T2 is the TCSENS programming temperature of 150°C. The ⎛ SensBNEG2⎞
LinERRNEG = ⎜⎜1– ⎟⎟ × 100% ,
ideal value of Sens over the full ambient temperature range,
⎝ SensBNEG1⎠
SensEXPECTED(TA), is defined as:
SensEXPECTED(TA) = SensT1 [1 + TCSENS (TA –T1) / 100%] (7) where:
SensEXPECTED(TA) should be calculated using the actual measured |VOUT(Bx) – VOUT(Q)|

SensBx = , (10)
values of SensT1 and TCSENS rather than programming target Bx
values.
and BPOSx and BNEGx are positive and negative magnetic fields,
Sensitivity Drift Due to Package Hysteresis Package stress and
relaxation can cause the device sensitivity at TA = 25°C to change with respect to the quiescent voltage output such that
during and after temperature cycling. |BPOS2| = 2 ×|BPOS1| and |BNEG2| = 2 ×|BNEG1|. Then:
For purposes of specification, the sensitivity drift due to package

LinERR = max( LinERRPOS , LinERRNEG) . (11)
hysteresis, ∆SensPKG, is defined as:
Sens(25°C)2 – Sens(25°C)1
∆SensPKG = × 100% , (8) Note that unipolar devices only have positive linearity error,
Sens(25°C)1
LinERRPOS.

Symmetry Sensitivity Error The magnetic sensitivity of an in the supply voltage relative to 5 V, and the measured change in
A136x device is constant for any two applied magnetic fields of each characteristic.
equal magnitude and opposite polarities.
The ratiometric error in quiescent voltage output, RatERRVOUT(Q)
Symmetry error, SymERR (%), is measured and defined as: (%), for a given supply voltage, VCC, is defined as:
⎛ SensBPOS ⎞ ⎛ VOUT(Q)(VCC) / VOUT(Q)(5V) ⎞
SymERR = ⎜⎜1– ⎟⎟ × 100% , (12) RatERRVOUT(Q) = ⎜⎜1– ⎟⎟ × 100% . (13)
⎝ SensBNEG ⎠ ⎝ VCC / 5 V ⎠
where SensBx is as defined in equation 4, and BPOS and BNEG are The ratiometric error in magnetic sensitivity, RatERRSENS (%), for
positive and negative magnetic fields such that |BPOS| = |BNEG|. a given supply voltage, VCC, is defined as:
Note that the symmetry error specification is only valid for bipolar
⎛ Sens(VCC) / Sens(5V) ⎞
devices. RatERRSENS = ⎜⎜1– ⎟⎟ × 100% . (14)
⎝ VCC / 5 V ⎠
Ratiometry Error The A136x devices feature ratiometric output.
This means that the quiescent voltage output, VOUT(Q) , magnetic The ratiometric error in the clamp voltages, RatERRCLP (%), for a
sensitivity, Sens, and clamp voltage, VCLP(HIGH) and VCLP(LOW), given supply voltage, VCC, is defined as:
are proportional to the supply voltage, VCC. In other words, when ⎛ VCLP(VCC) / VCLP(5V) ⎞
the supply voltage increases or decreases by a certain percent- RatERRCLP = ⎜⎜1– ⎟⎟ × 100% , (15)
⎝ VCC / 5 V ⎠
age, each characteristic also increases or decreases by the same
percentage. Error is the difference between the measured change where VCLP is either VCLP(HIGH) or VCLP(LOW).

Typical Application Drawing
V+
VCC VOUT
A136x
FILTER
CBYPASS GND CL
0.1 μF
CFILTER
Chopper Stabilization Technique

When using Hall-effect technology, a limiting factor for its original spectrum at base band, while the dc offset becomes
switchpoint accuracy is the small signal voltage developed a high-frequency signal. The magnetic-sourced signal then can
across the Hall element. This voltage is disproportionally small pass through a low-pass filter, while the modulated dc offset is
relative to the offset that can be produced at the output of the suppressed. The chopper stabilization technique uses a 210 kHz
Hall sensor. This makes it difficult to process the signal while high frequency clock.
maintaining an accurate, reliable output over the specified oper-
ating temperature and voltage ranges. For demodulation process, a sample and hold technique is used,
Chopper stabilization is a unique approach used to minimize where the sampling is performed at twice the chopper frequency
Hall offset on the chip. The patented Allegro technique, namely (420 kHz). This high-frequency operation allows a greater
Dynamic Quadrature Offset Cancellation, removes key sources sampling rate, which results in higher accuracy and faster signal-
of the output drift induced by thermal and mechanical stresses. processing capability. This approach desensitizes the chip to the
This offset reduction technique is based on a signal modulation- effects of thermal and mechanical stresses, and produces devices
demodulation process. that have extremely stable quiescent Hall output voltages and
The undesired offset signal is separated from the magnetic field- precise recoverability after temperature cycling. This technique
induced signal in the frequency domain, through modulation. is made possible through the use of a BiCMOS process, which
The subsequent demodulation acts as a modulation process for allows the use of low-offset, low-noise amplifiers in combination
the offset, causing the magnetic field-induced signal to recover with high-density logic integration and sample-and-hold circuits.
Regulator
Clock/Logic
Low-Pass
Hall Element Filter
Sample and
Hold
Amp
Concept of Chopper Stabilization Technique

Programming Guidelines
Overview for that kit is available for download free of charge, and provides
additional information on programming these devices.
Programming is accomplished by sending a series of input volt-
age pulses serially through the VOUT pin of the device. A unique Definition of Terms
combination of different voltage level pulses controls the internal
programming logic of the device to select a desired programmable Register One of several sections of the programming logic that
parameter and change its value. control the bit fields storing the code choices for setting program-
ming modes and programmable parameters.
There are three voltage levels that must be taken into account
Bit Field The set of internal fuses controlled by a single register.
when programming. These levels are referred to as high,
Each fuse in a bit field represents a binary digit in the code setting
VP(HIGH), mid, VP(MID), and low, VP(LOW). There are two program-
for that register. The internal logic of the device interprets that
ming pulse levels. A high voltage pulse, VPH, refers to a VP(LOW)
code and applies the result to a programmable parameter of the
–VP(HIGH) –VP(LOW) sequence. A mid voltage pulse, VPM, refers device. Individual fuses can be temporarily activated for testing of
to a VP(LOW) –VP(MID) –VP(LOW) sequence. the result, or permanently blown.
The 136x features four modes used during programming: Hold Key A series of one or more consecutive mid voltage pulses that
mode, Try mode, Blow mode, and Lock mode: indicate by their quantity the register being addressed. The quan-
• In Hold mode, the value of two programmable parameters may tity of mid voltage pulses corresponds to the decimal equivalent
be set and measured simultaneously. The parameter values are of the binary value of the register being addressed. For example,
stored temporarily, and reset after cycling the supply voltage. the LSB of a zone is bit 0 (binary 0), corresponding to register 1,
• In Try mode, the value of a single programmable parameter may and indicated by key 1 (decimal 1), a single mid voltage pulse.
be set and measured. The parameter value is stored temporarily,
Code A series of one or more consecutive mid voltage pulses that
and resets after cycling the supply voltage. (Note that other
indicate by their quantity the combination of fuses to be activated
parameters cannot be accessed simultaneously in this mode.)
or blown in the currently-selected register. The quantity of pulses
• In Blow mode, the value of a single programmable parameter in the code corresponds to the decimal equivalent of the binary
may be set permanently by blowing solid-state fuses internal to value of the bits (links) to be activated or blown. The LSB of a bit
the device. Additional parameters may be blown sequentially. field is bit 0, activated by code 1 (decimal 1), a single mid voltage
• In Lock mode, a device-level fuse is blown, blocking the further pulse.
programming of all parameters.
Addressing Indicating the target register or bit field setting by
The programming sequence is designed to help prevent the device incrementing the key or code by means of pulse trains of consecu-
from being programmed accidentally; for example, as a result of tive mid voltage pulses transmitted through the VOUT pin of the
noise on the supply line. Any programmable variable power sup- device. During the addressing process, each parameter can be
ply can be used to generate the pulse waveforms, although Allegro measured, before either blowing the fuses to permanently set the
highly recommends using the Allegro Sensor Evaluation Kit, programming code (and parameter value), or cycling the power to
available on the Allegro Web site On-line Store. The manual reset the unblown bits.

Zone The 136x programming logic is designed to accept up to internal to the device. After a bit (fuse) has been blown, it cannot
two different key-code combinations sequentially without cycling be reset.
the supply. The first key-code combination is interpreted as
Blow Pulse A high voltage pulse of sufficient duration to blow the
addressing a register in the first zone, and the second key-code
addressed fuse.
combination is interpreted as addressing a register in the second
zone. All of the parameter registers are located in either the first Cycling the Supply Powering-down, and then powering-up the
or second zone. The first zone must be entered and exited before supply voltage. Cycling the supply is used to clear the program-
the parameter registers available in the second zone may be ming settings in Try mode.
accessed.
Fuse Blowing Applying a high voltage pulse of sufficient dura-
tion to permanently set an addressed bit by blowing a fuse
Programming Pulse Requirements, protocol at TA = 25°C

Characteristic Symbol Notes Min. Typ. Max. Units
VP(LOW) – – 5.5 V
Programming Voltage VP(MID) Measured at the VOUT pin. 14 15 16 V
VP(HIGH) 26 27 28 V
Minimum supply current required to ensure proper
fuse blowing. In addition, a minimum capacitance,
Programming Current IP CBLOW = 0.1 μF, must be connected between the 300 – – mA
VOUT and GND pins during programming, to provide
the current necessary for fuse blowing.
Duration of VP(LOW) voltage level for separating
tLOW VP(MID) and VP(HIGH) pulses, and delay time after the 40 – – μs
final VBLOW pulse.
Pulse Width
Duration of VP(MID) and VP(HIGH) pulses for register
tACTIVE 40 – – μs
selection or bit field addressing.
tBLOW Duration of VP(HIGH) pulses for fuse blowing. 40 – – μs
Rise time required for transitions from VP(LOW) to
Pulse Rise Time tPr 5 – 100 μs
either VP(MID) or VP(HIGH).
Fall time required for transitions from VP(HIGH) or
Pulse Fall Time tPf 5 – 100 μs
VP(MID) to VP(LOW).

Programming Procedures
Parameter Selection the VOUT pin with no VCC supply interruptions. As each addi-
Each of the four programmable parameters can be accessed tional pulse in the code is transmitted, the overall setting of the
through its corresponding parameter register. These registers are bit field increments by 1, up to the maximum possible code for
located in two distinct zones in the A136x devices: that register (see the Programming Logic table). The A136x logic
interprets the overall setting (the binary sum of all of the acti-
Zone 1, Register 1:
vated or blown fuses) and applies it to the value of the parameter,
• Fine sensitivity, Sens
according to the step size for the parameter (shown in the Electri-
Zone 2, Register 1:
cal Characteristics table).
• Fine quiescent voltage output, VOUT(Q)
Zone 2, Register 2: Addressing activates the corresponding fuse locations in the
• Coarse quiescent voltage output, VOUT(Q) given bit field by incrementing the binary value of an internal
• Overall device locking, LOCK DAC. Measurements can be taken after each pulse to determine
if the desired result for the programmable parameter has been
To select the register in the first zone, a sequence of one VPH reached. Cycling the supply voltage resets all the locations in the
pulse, the key for the register, and a second VPH pulse (with no bit field that have unblown fuses to their initial states.
VCC supply interruptions) must be applied serially to the VOUT
Code 2n –2
Code 2n –1
pin. The pulse train used for selection of the first register, key 1,
Code 2n
Code 1
Code 2
Code 3
is shown in figure 1.
V+
V+
VP(MID)
VP(HIGH)
VP(LOW)
VP(MID) tACTIVE tLOW
0
VP(LOW)
tLOW Figure 2. Bit field addressing pulse train. Addressing the bit field by incre-
tACTIVE
menting the code causes the programmable parameter value to change.
0 The number of bits available for a given programming code, n, varies
among parameters; for example, the bit field for Sensitivity has 8 bits avail-
able, which allows 255 separate codes to be used.
Figure 1. Voltage pulse sequence required to select the first
programmable register in the first zone. Fuse Blowing
After the falling edge of the second VPH pulse, the bit field of the After the required code is found for a given parameter, its value
selected register may be addressed with the appropriate code (see can be set permanently by blowing individual fuses in the appro-
Bit Field Addressing section, below). priate register bit field. Blowing is accomplished by applying a
high voltage pulse, called a blow pulse, of sufficient duration to
The first zone must be traversed before the second zone can be permanently set an addressed bit by blowing a fuse internal to the
accessed. After completing any bit field addressing in the first device. Due to power requirements, the fuse for each bit in the
zone, to enter the second zone, apply a third VPH pulse. As in bit field must be blown individually. To accomplish this, the code
the first zone, this must be followed by the key for the parameter representing the desired parameter value must be translated to a
register, then a VPH pulse and the bit field code (with no VCC binary number. For example, as shown in figure 3, decimal code
supply interruptions). 5 is equivalent to the binary number 101. Therefore bit 2 (code
4) must be addressed and blown, the device power supply cycled,
Bit Field Addressing
and then bit 0 (code 1) addressed and blown. The order of blow-
After the register of a programmable parameter has been selected ing bits, however, is not important. Blowing bit 0 first, and then
as described above, the code pulses must be applied serially to bit 2, is acceptable.

Additional Guidelines
Bit Field Selection (Decimal Equivalent)
Address Code Format Code 5
The additional guidelines in this section should be followed to
(Binary)
Code in Binary
1 0 1
ensure the proper behavior of these devices:
Fuse Blowing • A 0.1 μF blowing capacitor, CBLOW, must be mounted between

Target Bits Bit 2 Bit 0
the VOUT pin and the GND pin during programming, to ensure
Fuse Blowing
Address Code Format
Code 4 Code 1 enough current is available to blow fuses.
(Decimal Equivalents)
• The CBLOW blowing capacitor must be replaced in the final
Figure 3. Example of code 5 broken into its binary components, application with a suitable CL. (The maximum load capacitance
equaling code 4 and code 1.
is 10 nF for proper operation.) The power supply used for
Note: After blowing, the programming is not reversible, even programming must be capable of delivering at least 26 V and
after cycling the supply power. Although a register bit field fuse 300 mA. Be careful to observe the tLOW delay time before
cannot be reset after it is blown, additional bits within the same powering down the device after blowing each bit.
register can be blown at any time until the device is locked. For • The following programming order is recommended:
example, if bit 1 (binary 10) has been blown, it is still possible to
1. Coarse VOUT(Q)
blow bit 0. The end result would be binary 11 (decimal code 3).
2. Sens
Locking the Device 3. VOUT(Q)
After the desired code for each parameter is programmed, the 4. LOCK (only after all other parameters have been
device can be locked to prevent further programming of any programmed and validated, because this prevents any further
parameters. See the Lock Mode section for lock pulse sequence. programming of the device)

Programming Modes
Hold Mode desired code is found for each register, cycle the supply and blow
the bit field using Blow mode.
Hold mode allows multiple programmable parameters to be
tested simultaneously without permanently setting any values. Note: For accurate time measurements, the blow capacitor,
With the 136x programming logic, only two parameters located CBLOW, should be removed during output voltage measurement.
in different zones can be addressed together. For example, only Also note that both the Sensitivity and Fine Quiescent Voltage
the sensitivity and fine quiescent voltage offset parameters can be Output registers should not be blown simultaneously. See the
temporarily set and tested simultaneously without permanently Blow Mode section for additional information.
setting their values. For unidirectional devices, the unidirectional
bit must be permanently blown before using the Hold Mode to Try Mode
temporarily set and test the sensitivity and fine quiescent voltage
Try mode allows a single programmable parameter to be tested
offset.
without permanently setting its value. Try mode is a required step
Powering the VCC supply automatically causes the device to of parameter blowing. (See the Blow Mode section for additional
enter the first zone. Applying a high pulse, mid pulse, high pulse information.) To select a parameter register in the first zone,
sequence selects the Sensitivity register. The sensitivity can be set power the supply and enter the appropriate key-code pulse com-
to the desired value by applying the appropriate code pulses. bination (see figure 5). To select a parameter register in the sec-
The next high-level pulse transitions the programming logic into ond zone, power the supply and apply two high voltage pulses,
the second zone. Applying one mid level pulse causes the logic followed by the appropriate key-code pulse combination (see
to enter the Fine Quiescent Voltage Output register, and another Figure 6). When addressing the bit field, each VPM pulse incre-
high-level pulse causes the logic to enter the Fine Quiescent ments the value of the parameter register, up to the maximum
Voltage Output bit field. The fine quiescent voltage output can possible code (see the Programming Logic table). The addressed
be set to the desired level by applying the appropriate number of parameter value is stored in the device even after the program-
mid-level pulses to the VOUT pin. (See figure 4.) ming drive voltage is removed from the VOUT pin, allowing its
The addressed parameter values will be stored in the device logic value to be measured.
even after the programming drive voltage is removed from the Note: For accurate time measurements, the blow capacitor,
VOUT pin, allowing the output to be measured at any time dur- CBLOW, should be removed during output voltage measurement.
ing the programming process.
To reset the bit field, and thus the value of the programmable
parameter, cycle the VCC supply voltage.
Figure 4. Hold sequence for testing Sens and VOUT(Q) parameters

together.
Figure 5. Pulses to enter Try mode, zone 1. Example shown is for
addressing the Sensitivity register. After addressing desired code,
After addressing and measuring the sensor output, cycle the sup- cycle the supply to reset the bit field or apply a blow pulse to make the
ply to reset all of the register values. Registers can be addressed parameter value permanent.
and re-addressed an indefinite number of times. Once the final

zone, enter the appropriate key-code combination and then apply

a single blow pulse on the VOUT pin. This is diagrammed as
follows:
Zone 1: VPH → Key → VPH → Code for Single Bit → VPH →
VPH → VPH
Zone 2: VPH → VPH → VPH → Key → VPH → Code for
Single Bit → VPH
Figure 6. Pulses to enter Try mode, zone 2. Example shown is Note: During a single blowing sequence, only one programmable
for addressing the Fine Quiescent Voltage Output register. After parameter in a single zone should be set at a time. After each
addressing desired code, cycle the supply to reset the bit field or apply
a blow pulse to make the parameter value permanent. blow sequence the supply should be cycled before attempting to
blow additional bits.
Blow Mode Lock Mode
After the required value of the programmable parameter is To lock the device, address the LOCK bit and apply a blow pulse
addressed using Try mode, its corresponding code can be blown with CBLOW in place. The LOCK bit is located in zone 2, register
to make its value permanent. To do this, select the required
2, code 4. After locking the device, no future programming of any
parameter register and the appropriate code. (See the Fuse Blow-
parameter is possible.
ing section. Recall that each bit of a desired code must be blown
individually before cycling the supply.) If the desired parameter The lock sequence is:
is in the first zone, enter the appropriate key-code combination
and then apply two high-level voltage pulses followed by an VPH → VPH → VPH → VPM → VPM →VPH → VPM → VPM
additional blow pulse. If the desired parameter is in the second → VPM → VPM → VPH

Programming State Machine
Initial State To enter the Bit Field Addressing state, send one VPH pulse on the
VOUT pin.
After system power-up, the programming logic is reset to a
known state. This is referred to as the Initial state. All the bit field Note: When parameter selection for zone 1 is bypassed (by send-
ing a second VPH pulse) no register is selected, and VPM pulses
locations that have intact fuses are set to logic 0. While in the Ini-
are ignored until after the VPH pulse is sent to enter zone 2.
tial state, any VPM pulses on the VOUT pin are ignored. To enter
the zone 1 Parameter Selection state, apply a single VPH pulse on Bit Field Addressing State
VOUT pin. To enter the zone 2 Parameter Selection state, apply a This state allows the selection of the individual bit fields to be
sequence of three VPH pulses on the VOUT pin. programmed in the selected parameter register (see the Program-
ming Logic table). To leave this state, either cycle device power
Parameter Selection State or blow the fuses for the selected code.
This state allows the selection of the parameter register contain- Note: Merely addressing the bit field does not permanently set
ing the bit fields to be programmed. To select a parameter register the value of the selected programming parameter; fuses must be
within the chosen zone, increment through the keys by sending blown to do so.
VPM pulses on the VOUT pin. Register keys select among the fol- Fuse Blowing State
lowing programming parameters in zone 1: To blow an addressed bit field, apply a VPH pulse on the VOUT
1 pulse – Sens, pin. Power to the device should then be cycled before additional
and the following programming parameters in zone 2: programming is attempted.
1 pulse – VOUT(Q) Note: Each bit representing a decimal code must be blown indi-
2 pulses – Coarse VOUT(Q) and LOCK vidually (see the Fuse Blowing section).
Power-up VPM = VP(LOW) → VP(MID) → VP(LOW)

Initial VPH = VP(LOW) → VP(HIGH) → VP(LOW)
VPH VPM
Parameter Selection Parameter Selection
(Zone 1) (Zone 2)
[Key sequence] VPM VPH VPH VPM [Key sequence]
V
VOUT(Q) PM V Coarse VPM
Sens OUT(Q)
VPM (Fine) or Lock
VPH VPH VPH
VPH
Bit Field Addressing Bit Field Addressing
VPM [Code sequence] VPH VPM
[Code sequence]
VPM VPM
VPM VPM 2n –1 VPM 2n – 1 VPM
1 2 n= bits in 1 2 n= bits in
register register
VPH VPH VPH VPH VPH VPH
Fuse Blowing
User Power-down
Required

Programming Logic Table

Programmable Parameter Bit Field Address
Register Selection Binary Format Decimal Description
Zone
(Key) (MSB → LSB) Equivalent Code
Sens 00000000 0 Initial value (Sensinit)
1
(1) 11111111 255 Maximum value of sensitivity (Sens) in range
00000000 0 Initial value for selected programming region (VOUT(Q)init)
VOUT(Q)
(1) Maximum value of fine VOUT(Q) in range for selected
11111111 255
bidirectional or unidirectional device
2 Coarse VOUT(Q) Switch from default bidirectional (VOUT(Q)BI) device to
00000001 1
(2) (VOUT(Q)UNI) device
LOCK LOCK bit, enables permanent locking of all programming
00000100 4
(2) bit fields in the device

Constructing a Current Sensor Using the A136x
To construct a current sensor using the A136x, first consider a of the core has a radius of 9 mm. Using this setup with a gap of
current carrying wire that we want to observe. As dictated by 1.7 mm, a field strength results that is on the order of 7 G / A at
Ampere’s Law, a magnetic field is produced around the wire the Hall sensor in the A136x.
that is proportional to the amount of current flowing through
the wire. By passing this wire through a soft magnetic core, the The recommended core material for construction of the concen-
magnetic flux produced by the wire can be concentrated and trator depends on the specific application. If high flux saturation
directed through a gap in the core. The magnetic flux density can is desired, then an alloy such as HyPerm49 is recommended.
be measured by inserting the A136x SIP into the gap in the core. For lower-current level sensing applications, a material such as
As a result, the output of the A136x sensor will be proportional HyMu80 may be desired. (HyMu80 has lower magnetic flux
to the amount of current flowing through the wire. saturation than HyPerm49, therefore more HyMu80 mate-
The example feedthrough current sensing setup shown below rial is required to carry the same amount of flux compared
(figure 7) has a core made of “mu metal” that is 2 mm thick to Hyperm49.) If frequency response is a concern, then eddy
and 4 mm wide. The inner radius of the core is 14.5 mm and currents can be reduced by either laminating the HyPerm49 or
the outer radius is 18.5 mm. The wire going through the center HyMu80 alloys, or by using a ferrite core.
Application-specific housing
Ø18 mm
Ring concentrator
4 mm
Current-conducting wire
Ø37 mm
1.7 mm 2 mm
A136x
Center Hall element in gap
Figure 7. The example current sensor setup used to generate the data in this section was
constructed with a split-ring concentrator and an A136x sensor. A copper wire was fed
through the concentrator, and the A136x placed in its gap. This approximates a typical
ammeter application on a thick wire, such as shown in the left view. Note that such
applications usually have a protective housing, which should be taken into consideration
when designing the final application. The housing is beyond the scope of this example.

Flux Density per Ampere vs. Gap for a Feedthrough Sensor

The flux density measured by the A136x SIP is related to the
size of the gap cut into the core. The larger the gap in the core,
14
12
the smaller the flux density per ampere of applied current (see
G/A at the Gap Center
10
figure 8).
8
Figure 9 depicts the magnetic flux density through the center of
6
the SIP as a function of SIP to core alignment. Note that a core
4
with a larger cross-sectional area would reduce the attenuation
2
in flux density that results from any SIP misalignment. The flat
0
0.5 1 1.5 2 2.5 3 3.5 portion of the curve in figure 9 would span a larger distance in
Gap (mm)
millimeters if the cross-sectional area of the core were increased.
Figure 8. The flux density per ampere measured by the A136x Hall sen-
sor is related to the core gap, as shown. This figure assumes that the
current sensing application is constructed using the example setup.
7.0
Interior side of Exterior side of

6.5
Ring concentrator Concentrator Concentrator
6.0
Magnetic Flux Intensity, B (G)
Magnetic flux in gap

Wire
5.5
Measurement plane
(midplane of gap)
5.0
4.5
4.0
3.5
+B 3.0
–2.0 –1.0 0 1.0 2.0
–2 0
mm
2 Radial Displacement from Concentrator Centerline (mm)
Figure 9. Side view of example current-conducting wire and split ring concentrator (left), and
magnetic profile (right) through the midplane of the gap in the split ring concentrator. The flux
denisty through the center of the gap varies between the inside and the outside of the gap.

Improving Sensing System Accuracy Using the FILTER Pin
In low-frequency sensing applications, it is often advantageous over temperature. Therefore, signal attenuation will vary as a
to add a simple RC filter to the output of the sensor. Such a low- function of temperature. Note that the input impedance, RINTFC ,
pass filter improves the signal-to-noise ratio, and therefore the of commonly available analog-to-digital converters (ADC) can
resolution, of the sensor output signal. However, the addition of be as low as 10 kΩ.
an RC filter to the output of a sensor IC can result in undesirable
sensor output attenuation — even for dc signals. The A136x contains an internal resistor with buffer amplifier that
can be connected via the FILTER pin to the PCB. With this cir-
Signal attenuation, ∆VATT , is a result of the resistive divider
cuit architecture, users can implement a simple RC filter via the
effect between the resistance of the external filter, REXT (see fig-
ure 10), and the input impedance and resistance of the customer addition of a capacitor, CFILTER (see figure 11) from the FILTER
interface circuit, RINTFC. The transfer function of this resistive pin to ground. The buffer amplifier inside of the A136x (located
divider is given by: after the internal resistor and FILTER pin connection) eliminates
⎛ RINTFC ⎞ the attenuation caused by the resistive divider effect described in
∆VATT = VOUT ⎜⎜ ⎟
. (16) equation 16. Therefore, the A136x device is ideal for use in high-
⎝ REXT + RINTFC ⎠ accuracy applications that require a large signal-to-noise ratio
Even if REXT and RINTFC are designed to match, the two individ- and cannot afford the signal attenuation associated with the use
ual resistance values will most likely drift by different amounts of an external RC low-pass filter.
V+
VCC Standard Hall Effect Device
Low Pass Filter

Dynamic Offset
Cancellation
Figure 10. When a low pass filter is constructed externally VOUT

Resistive Divider
Filter
Out
to a standard Hall effect device, a resistive divider may Amp
REXT Application
exist between the filter resistor, REXT, and the application Interface
Circuit
load resistance, RINTFC. This resistive divider (shaded CEXT
CBYPASS RINTFC
area) will cause excessive attenuation, as given by the 0.01 μF
Gain Offset
transfer function shown in equation 16.

Trim
Control
GND
V+
Allegro A136x
VCC
Ratiometric Program/Lock FILTER

Hall Drive
Programming
Logic
Figure 11. The FILTER pin provided CFILTER
on the A136x device allows separate Sens TC Trim Sensitivity Trim VOUT(Q)
8 Fine Bits
8 Bits
control of SNR, avoiding the attenua- 1 Coarse Bit
(Factory (Customer (Customer
tion effects from the standard resistor CBYPASS
Programmed) Programmed) Programmed)
divider solution, shown in figure 10. 0.01 μF Buffer Amplifier

Dynamic Offset
and Resistor
+
Cancellation
+
Signal Recovery – VOUT
–
Application
Interface
Circuit
RINTFC
GND

Package KT, 4-Pin SIP
5.22
10°
B
C 2.60 1.00
1.08 C
3.45 C
0.54
0.89 A
MAX
12.14 0.42 0.22
0.89
MAX
1 2 3 4
1.51
D
1.27 1.00
5.22
All dimensions nominal, not for tooling use

Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
A Dambar removal protrusion (16X)

B Active Area Depth 0.37 mm
C Hall element, not to scale
D Thermoplastic Molded Lead Bar for alignment during shipment
Copyright ©2008, Allegro MicroSystems, Inc.

The products described herein are manufactured under one or more of the following U.S. patents: 5,045,920; 5,264,783; 5,442,283; 5,389,889;
5,581,179; 5,517,112; 5,619,137; 5,621,319; 5,650,719; 5,686,894; 5,694,038; 5,729,130; 5,917,320; and other patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to per-
mit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:

www.allegromicro.com

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A1360, A1361, and A1362

Low-Noise Programmable Linear Hall Effect Sensors with

Not to scale Continued on the next page…

Functional Block Diagram

Absolute Maximum Ratings

Pin-out Diagram Terminal List Table

Allegro MicroSystems, Inc. 2

Continued on the next page…

Allegro MicroSystems, Inc. 3

Continued on the next page…

Allegro MicroSystems, Inc. 4

floor attenuates proportionate to the filter capacitance (and device bandwidth).

Allegro MicroSystems, Inc. 5

Thermal Characteristics may require derating at maximum conditions

*Additional thermal information available on Allegro website.

Power Dissipation versus Ambient Temperature

Allegro MicroSystems, Inc. 6

Allegro MicroSystems, Inc. 7

Noise versus Filter Capacitance

Power On Time versus Filter Capacitance

Power On Time versus Filter Capacitance

Allegro MicroSystems, Inc. 8

(%) Applied Magnetic Field

(%) Applied Magnetic Field (%) Applied Magnetic Field

Transducer Output Transducer Output

Allegro MicroSystems, Inc. 9

Allegro MicroSystems, Inc. 10

SensEXPECTED(TA) should be calculated using the actual measured |VOUT(Bx) – VOUT(Q)|

For purposes of specification, the sensitivity drift due to package

Allegro MicroSystems, Inc. 11

Allegro MicroSystems, Inc. 12

Typical Application Drawing

Chopper Stabilization Technique

Concept of Chopper Stabilization Technique

Allegro MicroSystems, Inc. 13

Allegro MicroSystems, Inc. 14

Programming Pulse Requirements, protocol at TA = 25°C

Allegro MicroSystems, Inc. 15

Allegro MicroSystems, Inc. 16

Fuse Blowing • A 0.1 μF blowing capacitor, CBLOW, must be mounted between

Allegro MicroSystems, Inc. 17

Figure 4. Hold sequence for testing Sens and VOUT(Q) parameters

Allegro MicroSystems, Inc. 18

zone, enter the appropriate key-code combination and then apply

Allegro MicroSystems, Inc. 19

Programming State Machine

Power-up VPM = VP(LOW) → VP(MID) → VP(LOW)

VPH VPH VPH VPH VPH VPH

Allegro MicroSystems, Inc. 20

Programming Logic Table

Allegro MicroSystems, Inc. 21

Constructing a Current Sensor Using the A136x

Center Hall element in gap

Allegro MicroSystems, Inc. 22

Flux Density per Ampere vs. Gap for a Feedthrough Sensor

Interior side of Exterior side of

Magnetic flux in gap

Allegro MicroSystems, Inc. 23

Improving Sensing System Accuracy Using the FILTER Pin