A1324, A1325, and A1326

Low-Noise Linear Hall-Effect Sensor ICs with Analog Output

FEATURES AND BENEFITS DESCRIPTION

• Temperature-stable quiescent output voltage and sensitivity New applications for linear output Hall-effect devices, such
• Output voltage proportional to magnetic flux density as displacement, angular position, and current measurement,
• Low-noise output increases accuracy require high accuracy in conjunction with small package size.
• Precise recoverability after temperature cycling The Allegro™ A1324, A1325, and A1326 linear Hall-effect
• Ratiometric rail-to-rail output sensor ICs are designed specifically to achieve both goals. This
• Wide ambient temperature range: –40°C to 150°C temperature-stable device is available in a miniature surface
• Immune to mechanical stress mount package (SOT23W) and an ultra-mini through-hole
• Solid-state reliability single in-line package.
• Enhanced EMC performance for stringent automotive
These ratiometric Hall effect sensor ICs provide a voltage
applications
output that is proportional to the applied magnetic field. They
feature a quiescent voltage output of 50% of the supply voltage.
The A1324/25/26 feature factory programmed sensitivities of
PACKAGES 5.0 mV/G, 3.125 mV/G, and 2.5 mV/G, respectively.
3-pin ultramini SIP 3-pin SOT23-W The features of these linear devices make them ideal for
1.5 mm × 4 mm × 3 mm 2 mm × 3 mm × 1 mm use in automotive and industrial applications requiring high
(suffix UA) (suffix LH) accuracy, and operate through an extended temperature range,
–40°C to 150°C.
Each BiCMOS monolithic circuit integrates a Hall element,
temperature-compensating circuitry to reduce the intrinsic
sensitivity drift of the Hall element, a small-signal high-gain
amplifier, a clamped low-impedance output stage, and a
proprietary dynamic offset cancellation technique.
These devices are available in a 3-pin ultra-mini SIP package
Approximate footprint (UA), and a 3-pin surface mount SOT-23 style package (LH).
Both are lead (Pb) free, with 100% matte tin leadframe plating.

Functional Block Diagram

V+

To All Subcircuits

VCC
Dynamic Offset
Cancellation

Tuned Filter

VOUT

Sensitivity and Offset

Sensitivity TC

Trim Control

GND

A1324-DS, Rev. 9 June 16, 2022

MCO-0000598
A1324, A1325,
Low-Noise Linear Hall-Effect Sensor ICs with Analog Output
and A1326

SELECTION GUIDE
Sensitivity (Typ.)
Part Number Packing [1] Package
(mV/G)
A1324LLHLT-T 3,000 pieces per reel 3-pin SOT-23W surface mount
A1324LLHLX-T 10,000 pieces per reel 3-pin SOT-23W surface mount 5.000
A1324LUA-T [2] 500 pieces per bag 3-pin ultramini SIP through hole mount
A1325LLHLT-T 3,000 pieces per reel 3-pin SOT-23W surface mount
A1325LLHLX-T 10,000 pieces per reel 3-pin SOT-23W surface mount 3.125
A1325LUA-T [2] 500 pieces per bag 3-pin ultramini SIP through hole mount
A1326LLHLT-T 3,000 pieces per reel 3-pin SOT-23W surface mount
A1326LLHLX-T 10,000 pieces per reel 3-pin SOT-23W surface mount 2.500
A1326LUA-T [2] 500 pieces per bag 3-pin ultramini SIP through hole mount

[1] Contact Allegro™ for additional packing options.

[2] Contact factory for availability.

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Notes Rating Unit
Forward Supply Voltage VCC 8 V
Reverse Supply Voltage VRCC –0.1 V
Forward Output Voltage VOUT 15 V
Reverse Output Voltage VROUT –0.1 V
Output Source Current IOUT(SOURCE) VOUT to GND 2 mA
Output Sink Current IOUT(SINK) VCC to VOUT 10 mA
Operating Ambient Temperature TA L temperature range –40 to 150 °C
Maximum Junction Temperature TJ(max) 165 °C
Storage Temperature Tstg –65 to 170 °C

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A1324, A1325,
Low-Noise Linear Hall-Effect Sensor ICs with Analog Output
and A1326

THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic Symbol Test Conditions* Value Unit
Package LH, on 4-layer PCB with copper limited to solder pads 228 °C/W
Package LH, on 2-layer PCB with 0.463 in.2 of copper area each
Package Thermal Resistance RθJA 110 °C/W
side, connected by thermal vias
Package UA, on 1-layer PCB with copper limited to solder pads 165 °C/W

*Additional thermal information available on the Allegro website.

Pinout Diagrams Terminal List Table

Number
3 Name Function
LH UA
Input power supply; tie to GND with
VCC 1 1
bypass capacitor
Output signal; also used for
VOUT 2 3
programming
GND 3 2 Ground
1 2 1 2 3

LH Package UA Package

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A1324, A1325,
Low-Noise Linear Hall-Effect Sensor ICs with Analog Output
and A1326

OPERATING CHARACTERISTICS: Valid throughout TA range, CBYPASS = 0.1 µF, VCC = 5 V, unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit [1]
ELECTRICAL CHARACTERISTICS
Supply Voltage VCC 4.5 5.0 5.5 V
Supply Current ICC No load on VOUT – 6.9 9 mA
Power-On Time [2] tPO TA = 25°C, CL (PROBE) = 10 pF – 32 – µs
Supply Zener Clamp Voltage VZ TA = 25°C, ICC = 12 mA 6 8.3 – V
Internal Bandwidth BWi Small signal, –3 dB – 17 – kHz
Chopping Frequency [3] fC TA = 25°C – 400 – kHz
OUTPUT CHARACTERISTICS
Quiescent Voltage Output VOUT(Q) B = 0 G, TA = 25°C 2.425 2.500 2.575 V
A1324, TA = 25°C, CBYPASS = 0.1 µF – 7.0 – mV(p-p)
Output Referred Noise VN A1325, TA = 25°C, CBYPASS = 0.1 µF – 4.4 – mV(p-p)
A1326, TA = 25°C, CBYPASS = 0.1 µF – 3.5 – mV(p-p)
TA = 25°C, CBYPASS = open, no load on VOUT,
Input Referred RMS Noise Density VNRMS – 1.3 – mG/√Hz
f << BWi
DC Output Resistance ROUT – <1 – Ω
VOUT to VCC 4.7 – – kΩ
Output Load Resistance RL
VOUT to GND 4.7 – – kΩ
Output Load Capacitance CL VOUT to GND – – 10 nF
VOUT(sat)HIGH RPULLDOWN = 4.7 kΩ, VCC = 5 V 4.7 – – V
Output Saturation Voltage
VOUT(sat)LOW RPULLUP = 4.7 kΩ, VCC = 5 V – – 0.30 V
MAGNETIC CHARACTERISTICS
A1324, TA = 25°C 4.750 5.000 5.250 mV/G
Sensitivity Sens A1325, TA = 25°C 2.969 3.125 3.281 mV/G
A1326, TA = 25°C 2.375 2.500 2.625 mV/G
LH package; programmed at TA = 150°C,
– 0 – %/°C
calculated relative to Sens at 25°C
Sensitivity Temperature Coefficient TCSens
UA package; programmed at TA = 150°C,
– 0.03 – %/°C
calculated relative to Sens at 25°C
ERROR COMPONENTS
Sensitivity Drift at Maximum Ambient LH package; from hot to room temperature –5 – 5 %
∆Sens(TAmax)
Operating Temperature UA package; from hot to room temperature –2.5 – 7.5 %
Sensitivity Drift at Minimum Ambient LH package; from cold to room temperature –3.5 – 8.5 %
∆Sens(TAmin)
Operating Temperature UA package; from cold to room temperature –6 – 4 %

Continued on the next page…

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A1324, A1325,
Low-Noise Linear Hall-Effect Sensor ICs with Analog Output
and A1326

OPERATING CHARACTERISTICS (continued): Valid throughout TA range, CBYPASS = 0.1 µF, VCC = 5 V, unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit [1]
ERROR COMPONENTS (continued)
Quiescent Voltage Output Drift
∆VOUT(Q) Defined in terms of magnetic flux density, B –10 – 10 G
Through Temperature Range
Linearity Sensitivity Error LinERR –1.5 – 1.5 %
Symmetry Sensitivity Error SymERR –1.5 – 1.5 %
Ratiometry Quiescent Voltage Throughout supply voltage range (relative to
RatVOUT(Q) –1.3 – 1.3 %
Output Error [4] VCC = 5 V)
Throughout supply voltage range (relative to
–1.5 – 1.5 %
VCC = 5 V), TA = 25°C and 150°C
Ratiometry Sensitivity Error [4] RatSens
Throughout supply voltage range (relative to
–2 – 2 %
VCC = 5 V), TA = –40°C
Sensitivity Drift Due to Package
∆SensPKG TA = 25°C, after temperature cycling – ±2 – %
Hysteresis

[1] 1 G (gauss) = 0.1 mT (millitesla).

[2] See Characteristic Definitions section.
[3] f varies up to approximately ±20% over the full operating ambient temperature range and process.
C
[4] Percent change from actual value at V
CC = 5 V, for a given temperature.

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A1324, A1325,
Low-Noise Linear Hall-Effect Sensor ICs with Analog Output
and A1326

CHARACTERISTIC DEFINITIONS
Power-On Time. When the supply is ramped to its operating defined as:
voltage, the device output requires a finite time to react to an
VOUT(B+) – VOUT(B–)
input magnetic field. Power-On Time is defined as the time it Sens = (2)
takes for the output voltage to begin responding to an applied B(+) – B(–)

magnetic field after the power supply has reached its minimum where B(+) and B(–) are two magnetic fields with opposite
specified operating voltage, VCC(min). polarities.
V Sensitivity Temperature Coefficient. The device sensitivity
VCC changes with temperature, with respect to its sensitivity tem-
VCC(typ.)
VOUT perature coefficient, TCSENS . TCSENS is programmed at 150°C,
90% VOUT
and calculated relative to the nominal sensitivity programming
temperature of 25°C. TCSENS (%/°C) is defined as:
SensT2 – SensT1  1 
TCSens =  × 100%   (3)
VCC(min.)
 SensT1   T2–T1
tPO
t1 t2 where T1 is the nominal Sens programming temperature of 25°C,
and T2 is the TCSENS programming temperature of 150°C.
t1= time at which power supply reaches
minimum specified operating voltage The ideal value of sensitivity through the temperature range,
t2= time at which output voltage settles SensIDEAL(TA), is defined as:
within ±10% of its steady state value
under an applied magnetic field
SensIDEAL(TA) = SensT1 × (100% + TCSENS(TA –T1) ) (4)
0
+t
Sensitivity Drift Through Temperature Range. Second
Quiescent Voltage Output. In the quiescent state (that is, order sensitivity temperature coefficient effects cause the mag-
with no significant magnetic field: B = 0), the output, VOUT(Q) , netic sensitivity to drift from its ideal value through the operating
equals a ratio of the supply voltage, VCC , throughout the entire ambient temperature, TA. For purposes of specification, the sensi-
operating range of VCC and the ambient temperature, TA . tivity drift through temperature range, ∆SensTC , is defined as:

Quiescent Voltage Output Drift Through Temperature SensTA – SensIDEAL(TA)

Range. Due to internal component tolerances and thermal con-
∆SensTC =
SensIDEAL(TA)
× 100% (5)

siderations, the quiescent voltage output, VOUT(Q) , may drift from
Sensitivity Drift Due to Package Hysteresis. Package
its nominal value through the operating ambient temperature
stress and relaxation can cause the device sensitivity at TA = 25°C
range, TA . For purposes of specification, the Quiescent Voltage
to change during or after temperature cycling. This change in
Output Drift Through Temperature Range, ∆VOUT(Q) (mV), is
sensitivity follows a hysteresis curve.
defined as:
For purposes of specification, the Sensitivity Drift Due to Pack-
∆VOUT(Q) = VOUT(Q)TA – VOUT(Q)25°C (1) age Hysteresis, ∆SensPKG , is defined as:

Sensitivity. The presence of a south-polarity magnetic field Sens(25°C)2 – Sens(25°C)1
∆SensPKG =
Sens(25°C)1
× 100% (6)
perpendicular to the branded surface of the package increases the

output voltage from its quiescent value toward the supply voltage
where Sens(25°C)1 is the programmed value of sensitivity at
rail. The amount of the output voltage increase is proportional
TA = 25°C, and Sens(25°C)1 is the value of sensitivity at TA = 25°C
to the magnitude of the magnetic field applied. Conversely, the
after temperature cycling TA up to 150°C, down to –40°C, and
application of a north polarity field will decrease the output volt-
back to up 25°C.
age from its quiescent value. This proportionality is specified
as the magnetic sensitivity, Sens (mV/G), of the device and is Linearity Sensitivity Error. The 132x is designed to provide

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A1324, A1325,
Low-Noise Linear Hall-Effect Sensor ICs with Analog Output
and A1326

linear output in response to a ramping applied magnetic field. Symmetry Error (%), is measured and defined as:
Consider two magnetic fields, B1 and B2. Ideally the sensitivity
 SensB(+) 
of a device is the same for both fields for a given supply voltage SymERR = 1–  × 100% (11)
and temperature. Linearity sensitivity error is present when there  SensB(–) 
is a difference between the sensitivities measured at B1 and B2.
where SensBx is defined as in equation 9, and B(+), B(–) are posi-
Linearity Sensitivity Error is calculated separately for the posi- tive and negative magnetic fields such that |B(+)| = |B(–)|.
tive (LINERR+) and negative (LINERR– ) applied magnetic fields.
Ratiometry Error. The A132x features a ratiometric output.
Linearity Sensitivity Error (%) is measured and defined as:
This means that the quiescent voltage output, VOUT(Q) , magnetic
 SensB(++)  sensitivity, Sens, and clamp voltages, VCLPHIGH and VCLPLOW ,
LinERR+ = 1–  × 100% are proportional to the supply voltage, VCC. In other words, when
 SensB(+) 
the supply voltage increases or decreases by a certain percent-
 SensB(– –)  age, each characteristic also increases or decreases by the same
LinERR– = 1–  × 100% (7) percentage. Error is the difference between the measured change
 SensB(–) 
in the supply voltage, relative to 5 V, and the measured change in
and each characteristic.
LinERR = max(| LinERR+| , |LinERR–| ) (8) The ratiometric error in quiescent voltage output, RatVOUT(Q)
where: (%), for a given supply voltage, VCC, is defined as:
|V – VOUT(Q)|   VOUT(Q)VCC ⁄ VOUT(Q)5V 
SensBx =  OUT(Bx)  (9) RatVOUT(Q) = 1–  × 100% (12)
 BX   VCC ⁄ 5 V 

and B(++), B(+), B(– –), and B(–) are positive and negative mag- The ratiometric error in magnetic sensitivity, RatSENS (%), for a
netic fields with respect to the quiescent voltage output such that given supply voltage, VCC, is defined as:
|B(++)| > |B(+)| and |B(– –)| > |B(– )| .
 SensVCC ⁄ Sens5V 
Symmetry Sensitivity Error. The magnetic sensitivity of a RatVOUT(Q) = 1–  × 100% (13)
 VCC ⁄ 5 V 
device is constant for any two applied magnetic fields of equal
magnitude and opposite polarities.

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A1324, A1325,
Low-Noise Linear Hall-Effect Sensor ICs with Analog Output
and A1326

Typical Characteristics
(30 pieces, 3 fabrication lots)

Average Supply Current versus Ambient Temperature

VCC = 5 V
12

11

10

9
ICCav (mA)

4
– 40 25 150
TA (°C)

Average Postive Linearity versus Ambient Temperature Average Negative Linearity versus Ambient Temperature
VCC = 5 V VCC = 5 V
105 105
104 104
103 103
102 102
Lin+av (%)

Lin–av (%)

101 101
100 100
99 99
98 98
97 97
96 96
95 95
– 40 25 150 – 40 25 150
TA (°C) TA (°C)

Average Quiescent Voltage Output Ratiometry versus Ambient Temperature Average Sensitivity Ratiometry versus Ambient Temperature

101.0 102.0
100.8 VCC VCC
101.5
100.6 5.5 to 5.0 V 5.5 to 5.0 V
101.0
RatSens(av) (%)

100.4 4.5 to 5.0 V 4.5 to 5.0 V

RatVOUTQ(av) (%)

100.2 100.5

100.0 100.0
99.8
99.5
99.6
99.0
99.4
99.2 98.5

99.0 98.0
– 40 25 150 – 40 25 150
TA (°C) TA (°C)

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A1324, A1325,
Low-Noise Linear Hall-Effect Sensor ICs with Analog Output
and A1326

Typical Characteristics, continued

(30 pieces, 3 fabrication lots)

Average Absolute Quiescent Voltage Output versus Ambient Temperature Quiescent Voltage Output versus Supply Voltage
VCC = 5 V TA = 25°C
2.565 3.0
A1324 2.9 A1324
2.545
A1325 2.8 A1325
VOUT(Q)av (V)

2.525 A1326 2.7 A1326

VOUT(Q) (V)
2.6
2.505
2.5
2.485 2.4

2.465 2.3
2.2
2.445
2.1
2.425 2.0
– 40 25 150 4.5 5 5.5
VCC (V)
TA (°C)

Average Absolute Sensitivity versus Ambient Temperature Average Sensitivity versus Supply Voltage
VCC = 5 V TA = 25°C
6.0 6.0

5.5 5.5
A1324
A1324 5.0
5.0
Sensav (mV/G)

Sensav (mV/G)

4.5
4.5 4.0
4.0 3.5
A1325
3.5 3.0
A1325 A1326
2.5
3.0
A1326 2.0
2.5 1.5
2.0 1.0
– 40 25 150 4.5 5 5.5
TA (°C) VCC (V)

Average Quiescent Voltage Output Drift versus Ambient Temperature Average Sensitivity Drift versus Ambient Temperature
∆VOUT(Q)av values relative to 25°C, VCC = 5 V ∆Sensav values relative to 25°C, VCC = 5 V
10 10
8 8
6 6
4 4
∆VOUT(Q)av (G)

∆Sensav (%)

2 2
0 0
-2 -2
-4 -4
-6 -6
-8 -8
-10 -10
– 40 25 150 – 40 25 150
TA (°C) TA (°C)

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A1324, A1325,
Low-Noise Linear Hall-Effect Sensor ICs with Analog Output
and A1326

V+ VOUT
1[1] 2[3]
VCC VOUT

A132x
CBYPASS
0.1 µF GND
3[2]
Pin numbers in brackets
refer to the UA package

Typical Application Circuit

Chopper Stabilization Technique

When using Hall-effect technology, a limiting factor for switch filter, while the modulated DC offset is suppressed. In addition
point accuracy is the small signal voltage developed across the to the removal of the thermal and stress related offset, this novel
Hall element. This voltage is disproportionally small relative to technique also reduces the amount of thermal noise in the Hall IC
the offset that can be produced at the output of the Hall IC. This while completely removing the modulated residue resulting from
makes it difficult to process the signal while maintaining an accu- the chopper operation. The chopper stabilization technique uses a
rate, reliable output over the specified operating temperature and high frequency sampling clock. For demodulation process, a sam-
voltage ranges. Chopper stabilization is a unique approach used ple-and-hold technique is used. This high-frequency operation
to minimize Hall offset on the chip. Allegro employs a technique
allows a greater sampling rate, which results in higher accuracy
to remove key sources of the output drift induced by thermal and
and faster signal-processing capability. This approach desensi-
mechanical stresses. This offset reduction technique is based on
a signal modulation-demodulation process. The undesired offset tizes the chip to the effects of thermal and mechanical stresses,
signal is separated from the magnetic field-induced signal in the and produces devices that have extremely stable quiescent Hall
frequency domain, through modulation. The subsequent demodu- output voltages and precise recoverability after temperature
lation acts as a modulation process for the offset, causing the cycling. This technique is made possible through the use of a
magnetic field-induced signal to recover its original spectrum at BiCMOS process, which allows the use of low-offset, low-noise
baseband, while the DC offset becomes a high-frequency signal. amplifiers in combination with high-density logic integration and
The magnetic-sourced signal then can pass through a low-pass sample-and-hold circuits.

Regulator

Clock/Logic

Hall Element

Amp

Anti-Aliasing Tuned
LP Filter Filter

Concept of Chopper Stabilization Technique

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A1324, A1325,
Low-Noise Linear Hall-Effect Sensor ICs with Analog Output
and A1326

Package LH, 3-Pin SOT23W

For Reference Only – Not for Tooling Use

(Reference Allegro DWG-0000628, Rev. 1)
NOT TO SCALE
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown

+0.125
2.975 –0.075

1.49
4°±4°
3 Active Area Depth
0.28 ±0.04 mm
+0.020
0.180–0.053

2.40
0.96 0.70
+0.10 +0.19
2.90 –0.20 1.91 –0.06

Hall element 1.00

(not to scale) 0.25 MIN
0.38 NOM

0.95
1 2
PCB Layout Reference View
0.55 REF 0.25 BSC All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
Seating Plane to meet application process requirements and PCB layout tolerances
Gauge Plane

8× 10° ±5° Branded Face

0.57 ±0.04
3× 1.00 ±0.13 C XXX
0.10 C 0.41 ±0.04
SEATING
PLANE
+0.10 1
0.05 –0.05
Standard Branding Reference View 1
0.95 BSC
0.40 ±0.10
Line 1 = Three digit assigned brand number

Branding scale and appearance at supplier discretion

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A1324, A1325,
Low-Noise Linear Hall-Effect Sensor ICs with Analog Output
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Package UA, 3-Pin SIP

For Reference Only – Not For Tooling Use

(Reference DWG-0000404, Rev. 1)
NOT TO SCALE
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown

Ejector pin flash Mold gate and tie bar

protrusion protrusion zone

R0.25 MAX (2×) 5° (2×) 0.56 MAX

45° (2×) XXX

1.52 ±0.05 1.68 MAX
0.10 MAX
5° (2×) 1

Standard Branding Reference View

+0.08
4.09 –0.05
Line 1 = Logo A
Line 2 = Three digit assigned brand number
3.00 ±0.05
Branding scale and appearance at supplier discretion

Mold gate and tie bar

protrusion zone 0.15 MAX

Ejector pin +0.05 0.50 ±0.08 Active Area Depth

(far side) 2.04 0.08 –0.00
Including gate and
tie bar burrs
Ejector pin flash
protrusion
1.44
3.10 MAX +0.08
3.02 –0.05
Hall Element
(not to scale) 45°
10° (3×)

1.02 MAX 0.79 REF

0.51 REF

0.05 NOM
0.05 NOM

14.99 ±0.25 +0.03

0.41 –0.06

0.10 MAX

0.10 MAX
Dambar Trim Detail

1.27 NOM (2×) +0.05

0.43 –0.07 (3×)

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A1324, A1325,
Low-Noise Linear Hall-Effect Sensor ICs with Analog Output
and A1326

Revision History
Number Date Description
3 September 16, 2013 Update product selection
4 September 26, 2013 Fixed UA package drawing
5 February 14, 2019 Minor editorial updates
6 February 21, 2020 Minor editorial updates
Added variant with 3-pin ultramini SIP through hole mount with 2.54 mm lead spacing to Selection
7 June 8, 2020
Guide (page 2)
8 June 11, 2020 Removed leadform variant (page 2)
9 June 16, 2022 Updated package drawings (pages 11-12) and minor editorial updates

Copyright 2022, Allegro MicroSystems.

Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.

For the latest version of this document, visit our website:

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