A1357

Two-Wire High Precision Linear Hall-Effect Sensor IC

With Pulse Width Modulated Output Current
Features and Benefits Description
▪ Two-wire output enables reduced wiring costs in The A1357 device is a high precision, programmable two-wire
long wire systems Hall-effect linear sensor IC with a pulse width modulated
▪ Simultaneous programming of PWM carrier frequency, (PWM) current. The A1357 device converts an analog signal
quiescent duty cycle (QDC), and sensitivity for system from its internal Hall sensor element to a digitally encoded
optimization PWM signal. The coupled noise immunity of the digitally
▪ Fully differential signal path increases EMC immunity and encoded PWM is far superior to the noise immunity of an
reduces output offset drifts analog output signal.
▪ Factory programmed sensitivity temperature coefficient
The BiCMOS, monolithic circuit inside of the A1357 integrates
and quiescent duty cycle drift
a Hall element, precision temperature-compensating circuitry
▪ Programmability at end-of-line
to reduce the intrinsic sensitivity and offset drift of the Hall
▪ Pulse width modulated (PWM) current output provides
element, a small-signal high-gain amplifier, proprietary
increased noise and EMC immunity compared to an
dynamic offset cancellation circuits, and PWM conversion
analog output
circuitry. The dynamic offset cancellation circuits reduce the
▪ Precise recoverability after temperature cycling
residual offset voltage of the Hall element that is normally
• Duty cycle clamps provide short circuit diagnostic
caused by device overmolding, temperature dependencies,
capabilities
and thermal stress. The high frequency offset cancellation
▪ Optional 50% duty cycle calibration test mode at device
(chopping) clock allows for a greater sampling rate, which
power up
increases the accuracy of the output current signal and results
▪ Wide ambient temperature range: –40°C to 150°C
in faster signal processing capability.
▪ Resistant to mechanical stress
The A1357 sensor is provided in a lead (Pb) free 3-pin single
Package: 3-pin SIP (suffix KB) inline package (KB suffix), with 100% matte tin leadframe
plating.
Not to scale

Functional Block Diagram

VSUPPLY

VCC (and PWM Carrier

programming) Generation

Regulator
PWM
1 Frequency Trim

CBYBASS 1

Signal
Chopper Signal Conditioning
Amp Recovery
Switches

Voltage Controlled
Current Source
Sensitivity Temperature % Duty
Trim Cycle % Duty Cycle
Compensation Temperature
Coefficient

GND

A1357-DS, Rev. 1 February 19, 2019

MCO-0000602
 Two-Wire High Precision Linear Hall-Effect Sensor IC
A1357
With Pulse Width Modulated Output Current

Selection Guide
Part Number Packing*
A1357LKB-T 500 pieces per bag
A1357LKBTN-T 4000 pieces per 13-in. reel
*Contact Allegro™ for additional packing options

Absolute Maximum Ratings

Characteristic Symbol Notes Rating Unit
Forward Supply Voltage VCC 28 V
Reverse Supply Voltage VRCC –18 V
Forward Supply Current ICC 50 mA
Reverse Supply Current IRCC –50 mA
Operating Ambient Temperature TA L temperature range –40 to 150 ºC
Maximum Junction Temperature TJ(max) 165 ºC
Storage Temperature Tstg VCC = 0 V –65 to 170 ºC

Pin-out Diagram
Terminal List Table
Number Name Function
Input power supply; use bypass capacitor to connect to ground; also
1 VCC
used for programming
2 GND Ground

3 NC No connect

1 2 3

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 Two-Wire High Precision Linear Hall-Effect Sensor IC
A1357
With Pulse Width Modulated Output Current

OPERATING CHARACTERISTICS Valid over full operating temperature range, TA , VCC = 4.5 to 18 V, CBYPASS = 0.1 µF, unless
otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit1
Electrical Characteristics
Supply Voltage2 VCC 4.5 – 18 V
ICC_LOW – 6 8 mA
Supply Current
ICC_HIGH 12 – 16.5 mA
Supply Current Ratio 2 – – –
Supply Zener Clamp Voltage VZsupply ICC = 18 mA, TA = 25ºC 28 – – V
Power-On Time3,4 tPO fpwm = 1 kHz – – 5 ms
Small signal –3 dB, 100 G(P-P) magnetic input
Internal Bandwidth BWi – 400 – Hz
signal, TA = 25 C°
Chopping Frequency5 fC TA = 25°C – 200 – kHz
Output Current Characteristics
PWMOUT Rise Time3,4 tr VCC pin, No CBYPASS or RSENSE, TA = 25 C° – 6.5 – mA/µs
PWMOUT Fall Time3,4 tf VCC pin, No CBYPASS or RSENSE, TA = 25 C° – 6.5 – mA/µs
Maximum Propagation Delay3,4 tPROP TA = 25 C° – 2 3 ms
Impulse magnetic field of 300 G, fpwm = 1 kHz,
Response Time3,4 tRESPONSE – 2 3.125 ms
slew rate < 120 G/ms, TA = 25 C°
Measured over 1000 output PWM clock periods,
Duty Cycle Jitter3,4,6 JitterPWM – – ±0.090 %D
3 sigma values, Sens = 60 m% / G, TA = 25 C°
DCLP(HIGH) 90 – 95 %D
Clamp Duty Cycle
DCLP(LOW) 5 – 10 %D
Pre-Programming Target7
Pre-Programming Quiescent Current
D(Q)PRE B = 0 G, TA = 25°C – 50 – %D
Duty Cycle
Pre-Programming Sensitivity SensPRE TA = 25°C – 25 – (m% D)/G
Pre-Programming PWMOUT Carrier
fPWMPRE TA = 25°C – 1.5 – kHz
Frequency
Quiescent Current Duty Cycle Programming
Initial Quiescent Current Duty Cycle D(Q)init B = 0 G, TA = 25°C – D(Q)PRE – %D
Guaranteed Quiescent Current Duty
D(Q) B = 0 G, TA = 25°C 40 – 60 %D
Cycle Output Range8
Quiescent Current Duty Cycle
– 9 – bit
Programming Bits
Average Quiescent Current Duty Cycle
StepD(Q) TA = 25°C 0.091 0.103 0.115 %D
Step Size9,10
Quiescent Current Duty Cycle StepD(Q)
ErrPGD(Q) TA = 25°C – – %D
Programming Resolution11 × ±0. 5

Continued on the next page…

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 Two-Wire High Precision Linear Hall-Effect Sensor IC
A1357
With Pulse Width Modulated Output Current

OPERATING CHARACTERISTICS (continued) Valid over full operating temperature range, TA , VCC = 4.5 to 18 V,
CBYPASS = 0.1 µF, unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
Sensitivity Programming
Initial Sensitivity Sensinit TA = 25°C – SensPRE – (% D)/G
Range_
TA = 25°C – 1 – bit
Sensitivity Programming Bits Selection
Fine TA = 25°C – 8 – bit
SensRange1 TA = 25°C 35 – 70 (m% D)/G
Guaranteed Sensitivity Range
SensRange2 TA = 25°C 70 – 145 (m% D)/G
StepSENS1 TA = 25°C 215 300 375 (µ% D)/G
Average Sensitivity Step Size9,10
StepSENS2 TA = 25°C 430 600 750 (µ% D)/G
StepSENS
Sensitivity Programming Resolution11 ErrPGSENS TA = 25°C – – (µ% D)/G
× ±0. 5
Carrier Frequency Programming
Initial Carrier Frequency fPWMinit TA = 25°C – fPWMPRE – Hz
Carrier Frequency Programming Range fPWM TA = 25°C 0.9 1 1.1 kHz
Carrier Frequency Programming Bits – 4 – bit
Average Carrier Frequency Step Size9,10 StepfPWM TA = 25°C 38 54 70 Hz
Carrier Frequency Programming StepfPWM
ErrPGfPWM TA = 25°C – – Hz
Resolution11 × ±0. 5
Calibration Test Mode
Calibration Test Mode Selection Bit – 1 – bit
Calibration Test Mode Duration4 tCAL fPWM = 1 kHz 45 50 55 ms
Output Duty Cycle During Calibration
DCAL 49 50 51 %D
Mode4
Lock Bit Programming
Overall Programming Lock Bit LOCK – 1 – bit
Factory Programmed Sensitivity Temperature Coefficient And Drift Characteristics
SensTC_
Sensitivity Temperature Coefficient12 TA = 150°C – 0.11 – %/°C
NdFeB
Sensitivity Drift Through Temperature
ΔSensTC TA = 150°C – < ±3 – %
Range13
Sensitivity Drift Due to Package
ΔSensPKG TA = 150°C, after temperature cycling – < ±1 – %
Hysteresis3

Continued on the next page…

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 Two-Wire High Precision Linear Hall-Effect Sensor IC
A1357
With Pulse Width Modulated Output Current

OPERATING CHARACTERISTICS (continued) Valid over full operating temperature range, TA , VCC = 4.5 to 18 V,
CBYPASS = 0.1 µF, unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
Factory Programmed Quiescent Current Duty Cycle Drift
Quiescent Current Duty Cycle
DTC(Q) TA = 150°C – 0 – (% D)/°C
Temperature Coefficient12
Quiescent Current Duty Cycle Drift
ΔD(Q) Sens = SensPRE, TA = 150°C – < ±0.35 – %D
Through Temperature Range14
Error Components
Linearity Sensitivity Error LinERR – < ±1.5 – %
Symmetry Sensitivity Error SymERR – < ±1.5 – %
11 G (gauss) = 0.1 mT (millitesla).
2Supply Voltage is the voltage drop between device supply and ground pins. It does not include a drop through a sense resistor.
3See Characteristic Definitions section.
4Guaranteed by design only. Characterized but not tested in production.
5f varies up to approximately ±20% through the full operating ambient temperature range, T , and process.
C A 
6Jitter is dependent on the sensitivity of the device.
7Raw device characteristic values before any programming.
8D (max) is the value available with all programming fuses blown (maximum programming code set). The D
(Q) (Q) range is the total range from D(Q)(min)
up to and including D(Q)(max). See Characteristic Definitions section.
9Step size is larger than required, in order to provide for manufacturing spread. See Characteristic Definitions section.
10Non-ideal behavior in the programming DAC can cause the step size at each significant bit rollover code to be greater than twice the maximum
specified value of StepD(Q) , StepSENS , or StepfPWM .
11Overall programming value accuracy. See Characteristic Definitions section.
12Programmed at 150°C and calculated relative to 25°C.
13Sensitivity drift from expected value at T after programming SENS . See Characteristic Definitions section.
A TC
14D
(Q) drift from expected value at TA after programming DTC(Q).

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 Two-Wire High Precision Linear Hall-Effect Sensor IC
A1357
With Pulse Width Modulated Output Current

THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance RθJA 1-layer PCB with copper limited to solder pads 177 ºC/W
*Additional thermal data available on the Allegro Web site.

Power Derating Curve

20

VCC(max)
Maximum Allowable VCC (V)

15

10

5
VCC(min)

0
20 40 60 80 100 120 140 160
Ambient Temperature, TA (ºC)

Power Dissipation versus Ambient Temperature

900

800
Power Dissipation, PD (mW)

700

600

500

400

300

200

100

0
20 40 60 80 100 120 140 160

Ambient Temperature, TA (ºC)

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 Two-Wire High Precision Linear Hall-Effect Sensor IC
A1357
With Pulse Width Modulated Output Current
Characteristic Definitions

Power-On Time When the supply is ramped to its operating Average Quiescent Current Duty Cycle Step Size The
voltage, the device requires a finite time to power its internal Average Quiescent Current Duty Cycle Step Size, StepD(Q) , for a
components before supplying a valid PWM output duty-cycle. single device is determined using the following calculation:
Power-On Time, tPO, is defined as the time it takes for the output D(Q)(max) – D(Q)(min)
voltage to settle within ±10% of its steady state value after the StepD(Q) = , (1)
power supply has reached its minimum specified operating volt- 2n –1
age, VCC(min). (See figure 1.) where:

Propagation Delay Traveling time of signal from input Hall n is the number of available programming bits in the trim range,
plate to output stage of device. (See figure 2.) 2n – 1 is the value of programming steps in the range,
Response Time The time interval, tRESPONSE , between D(Q)(max) is the maximum reached quiescent duty cycle, and
a) when the applied magnetic field reaches 90% of its final value,
and b) when the sensor IC reaches 90% of its output correspond- D(Q)(min) is minimum reached quiescent duty cycle.
ing to the applied magnetic field. (See figure 2.)
PWMOUT Rise Time The time, tr , elapsed between 10% and ADC – DC corresponds to the A field
BDC – DC corresponds to the B field
90% of the rising signal value when output current switches from CDC – DC corresponds to the 0.9 × C field

low to high states.

PWMOUT Fall Time The time, tf , elapsed between 90% and 1 ms 0.9 × C
10% of the falling signal value when output current switches
C
from high to low states. B-field B
A
Quiescent Current Duty Cycle In the quiescent state (no Time
significant magnetic field: B = 0 G), the Quiescent Current Duty ADC BDC CDC

Cycle, D(Q), equals a specific programmed duty cycle throughout Icc

the entire operating ranges of VCC and ambient temperature, TA.
Guaranteed Quiescent Current Duty Cycle Range The Propagation Response
Delay
Quiescent Current Duty Cycle, D(Q), can be programmed around Time

its nominal value of 50% D, within the Guaranteed Quiescent

Duty Cycle Range limits: D(Q)(min) and D(Q)(max). The available
guaranteed programming range for D(Q) falls within the distribu-
tions of the minimum and the maximum programming code for
Figure 2. Definitions of Propagation Delay and Response Time
setting D(Q). (See figure 3.)

VCC
Guaranteed D(Q)
Programming
Range
VCC(min)

Time
ICC

Time
First valid duty cycle Min Code D(Q) Max Code D(Q)
Initial D(Q)
Distribution Distribution Distribution
tPO
D(Q)(min) D(Q)(max)

Figure 1. Definition of Power-On Time Figure 3. Definition of Guaranteed Quiescent Voltage Output Range

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 Two-Wire High Precision Linear Hall-Effect Sensor IC
A1357
With Pulse Width Modulated Output Current

Quiescent Current Duty Cycle Output Programming Sensitivity Programming Resolution Refer to the Quies-
Resolution The programming resolution for any device is half cent Current Duty Cycle Programming Resolution section for a
of its programming step size. Therefore, the typical programming conceptual explanation.
resolution will be: Carrier Frequency Target The PWMOUT signal Carrier
Frequency Programming Range, fPWM, can be programmed to its
ErrPGD(Q)(typ) = 0.5 × StepD(Q)(typ) . (2) typical value of 1 kHz.

Quiescent Duty Cycle Output Drift through Tempera- Average Carrier Frequency Step Size Refer to the Average
ture Range Due to internal component tolerances and thermal Quiescent Current Duty Cycle Step Size section for a conceptual
considerations, the Quiescent Duty Cycle Temperature Coef- explanation.
ficient, DTC(Q), may drift from its nominal value over the operat- Carrier Frequency Programming Resolution Refer to the
ing ambient temperature, TA. For purposes of specification, the Quiescent Durrent Duty Cycle Programming Resolution section
Quiescent Duty Cycle Output Drift Through Temperature Range, for a conceptual explanation.
∆D(Q) (% D), is defined as:
Sensitivity Temperature Coefficient Device sensitiv-
∆D(Q) = D(Q)(TA) – D(Q)(25°C) , (3) ity changes as temperature changes, with respect to its pro-
grammed Sensitivity Temperature Coefficient, SensTC. SensTC
where D(Q)(TA) is the quiescent duty cycle measured at TA and is programmed at 150°C, and calculated relative to the nominal
D(Q)(25°C) is the quiescent duty cycle measured at 25°C. sensitivity programming temperature of 25°C. SensTC (%/°C) is
defined as:
Sensitivity The presence of a south polarity magnetic field,
perpendicular to the branded surface of the package face, SensT2 – SensT1  1 
increases the current duty cycle from its quiescent value toward
SensTC =  × 100%   , (6)
 SensT1  T2–T1
the maximum duty cycle limit. The amount of the current duty
cycle increase is proportional to the magnitude of the magnetic where T1 is the nominal Sens programming temperature of 25°C,
field applied. Conversely, the application of a north polarity and T2 is the programming temperature of 150°C. The expected
field decreases the current duty cycle from its quiescent value. value of Sens through the full ambient temperature range,
This proportionality is specified as the magnetic Sensitiv- SensEXPECTED(TA), is defined as:
ity, Sens ((% D)/G), of the device, and it is defined for bipolar SensT1× [100% +SensTC (TA –T1)]
devices as: SensEXPECTED(TA) = . (7)
100 %
D(BPOS) – D(BNEG)
Sens = , (4) SensEXPECTED (TA) should be calculated using the actual measured
BPOS – BNEG values of SensT1 and SensTC rather than programming target
and for unipolar devices as: values.
D(BPOS) – D(Q)
Sens = , (5) Sensitivity Drift Through Temperature Range Second
BPOS order Sensitivity Temperature Coefficient effects cause the mag-
where BPOS and BNEG are two magnetic fields with opposite netic Sensitivity, Sens, to drift from its expected value through
polarities. the operating ambient temperature range, TA. For purposes of
specification, the Sensitivity Drift Through Temperature Range,
Guaranteed Sensitivity Range The magnetic Sensitivity can ∆SensTC , is defined as:
be programmed from its initial value, Sensinit , to a value within
the Guaranteed Sensitivity Range limits: SensRange(min) and SensTA – SensEXPECTED(TA)
∆SensTC =
SensEXPECTED(TA)
× 100% . (8)
SensRange(max).

Average Sensitivity Step Size Refer to the Average Qui- Sensitivity Drift Due to Package Hysteresis Package
escent Current Duty Cycle Step Size section for a conceptual stress and relaxation can cause the device Sensitivity at TA =
explanation. 25°C to change during and after temperature cycling.

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 Two-Wire High Precision Linear Hall-Effect Sensor IC
A1357
With Pulse Width Modulated Output Current

For purposes of specification, the Sensitivity Drift Due to Pack- 2 × BPOS1 and BNEG2 = 2 × BNEG1.
age Hysteresis, ∆SensPKG, is defined as:
Then:
Sens(25°C)2 – Sens(25°C)1
∆SensPKG = × 100% , (9) LinERR = max( LinERRPOS , LinERRNEG) . (12)
Sens(25°C)1

where Sens(25°C)1 is the programmed value of sensitivity at TA = Note that unipolar devices only have positive linearity error
25°C, and Sens(25°C)2 is the value of sensitivity at TA = 25°C, (LinERRPOS).
after temperature cycling TA up to 150°C, down to –40°C, and
back to up 25°C. Symmetry Sensitivity Error The magnetic sensitivity of the
A1357 device is constant for any two applied magnetic fields of
Linearity Sensitivity Error The A1357 is designed to provide equal magnitude and opposite polarities. Symmetry Sensitivity
a linear current output in response to a ramping applied magnetic Error, SymERR (%), is measured and defined as:
field. Consider two magnetic fields, B1 and B2. Ideally, the sen-
sitivity of a device is the same for both fields, for a given supply  SensBPOS 
voltage and temperature. Linearity error is present when there is a SymERR = 1–  × 100% , (13)
SensBNEG 
difference between the sensitivities measured at B1 and B2. 
where SensBx is as defined in equation 11, and BPOS and BNEG
Linearity Sensitivity Error is calculated separately for the positive
are positive and negative magnetic fields such that |BPOS| =
(LinERRPOS) and negative (LinERRNEG ) applied magnetic fields.
|BNEG|. Note that the Symmetry Sensitivity Error specification is
Linearity error (%) is measured and defined as:
valid only for bipolar devices.
 SensBPOS2 
LinERRPOS = 1–  × 100% , Duty Cycle Jitter The duty cycle of the PWMOUT output may
 SensBPOS1  vary slightly over time despite the presence of a constant applied
 SensBNEG2 magnetic field and a constant Carrier Frequency, fPWM , for the
LinERRNEG = 1–  × 100% , (10) PWMOUT signal. This phenomenon is known as jitter, and is
 SensBNEG1
defined as:
where:
1 n

|D(Bx) – D(Q)|
JitterPWM =
n
DBi ± 3 σ , (14)

i=1
SensBx =
Bx
. (11)
where DB1 ,…, DBn are the sampled duty cycles in a constant
and BPOSx and BNEGx are positive and negative magnetic fields, applied magnetic field, B, measured over 1000 PWM clock peri-
with respect to the quiescent current duty cycle such that BPOS2 = ods, and JitterPWM is given in % D.

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 Two-Wire High Precision Linear Hall-Effect Sensor IC
A1357
With Pulse Width Modulated Output Current

Typical Application Circuit

The current switching performed by the Hall sensor IC can be VCC(min) is the A1357 minimum supply voltage.
observed as voltage switching. To do so, place a sense resistor,
Substituting into equation 15:
RSENSE , between the supply and the A1357 VCC pin (see figure
4), or between the A1357 GND pin and ground (figure 5). There 12 V > RSENSE × 16.5 mA + 4.5 V ,
is an advantage to putting the sense resistor between the supply
therefore:
and the A1357 VCC pin, because the resistor can then provide
additional device protection from supply transients. RSENSE ≤ (12 – 4.5) V / 16.5 mA

When specifying value of the RSENSE and the applied supply volt- ≤ 454 Ω .
age in the application, the following equation must be applied, in It can be seen that RSENSE is proportional to VSUPPLY . The higher
order to provide enough voltage to allow the A1357 to power-up: the value of RSENSE , the higher the application supply voltage
VSUPPLY > RSENSE × ICC_HIGH(max) + VCC(min) , (15) required.
where ICC(max) is the maximum A1357 supply current and The recommended minimum CBYPASS value is 0.01 µF.

RSENSE

1 1
VCC VCC
VSUPPLY VSUPPLY
A1357 A1357
CBYPASS CBYPASS
0.1 µF 0.1 µF
GND GND
2 2

RSENSE

Figure 4. High-side PWM voltage sensing configuration Figure 5. Low-side PWM voltage sensing configuration

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 Two-Wire High Precision Linear Hall-Effect Sensor IC
A1357
With Pulse Width Modulated Output Current
Programming Guidelines

Overview Definition of Terms

Programming is accomplished by sending a series of input volt- Register The section of the programming logic that controls the
age pulses serially through the VCC pin of the device. A unique choice of programmable modes and parameters.
combination of different voltage level pulses controls the internal
Bit Field The internal fuses unique to each register, represented
programming logic of the device to select a programmable
as a binary number. Changing the bit field settings of a particular
parameter and change its value. There are three voltage levels
register causes its programmable parameter to change, based on
that must be taken into account when programming. These levels
the internal programming logic.
are referred to as high, VP(HIGH) , mid, VP(M ID), and low, VP(LOW) .
Key A series of mid-level voltage pulses used to select a register,
The A1357 features Try mode, Blow mode and Lock mode:
with a value expressed as the decimal equivalent of the binary
• In Try mode, the value of multiple programmable parameters value. The LSB of a register is denoted as key 1, or bit 0.
may be set and measured simultaneously. The parameter values
are stored temporarily, and reset after cycling the supply volt- Code The number used to identify the combination of fuses
age. activated in a bit field, expressed as the decimal equivalent of the
binary value. The LSB of a bit field is denoted as code 1, or bit 0.
• In Blow mode, the value of a single programmable parameter
may be set and measured, and then permanently set by blowing Addressing Increasing the bit field code of a selected register
solid-state fuses internal to the device. Additional parameters by serially applying a pulse train through the VCC pin of the
may be blown sequentially. This mode also is used for blow- device. Each parameter can be measured during the addressing
ing the device-level fuse (when Lock mode is enabled), which process, but the internal fuses must be blown before the program-
permanently blocks the further programming of all parameters. ming code (and parameter value) becomes permanent.
• Lock mode prevents all future programming of the device. This Fuse Blowing Applying a high voltage pulse of sufficient
is accomplished by blowing a special fuse using Blow mode. duration to permanently set an addressed bit by blowing a fuse
The programming sequence is designed to help prevent the internal to the device. After a bit (fuse) has been blown, it cannot
device from being programmed accidentally; for example, as a be reset.
result of noise on the supply line. Although any programmable
Blow Pulse A high voltage pulse of sufficient duration to blow
variable power supply can be used to generate the pulse wave-
the addressed fuse.
forms, Allegro highly recommends using the Allegro Sensor
Evaluation Kit, available on the Allegro website On-line Store. Cycling the Supply Powering-down, and then powering-up the
The manual for that kit is available for download free of charge, supply voltage. Cycling the supply is used to clear the program-
and provides additional information on programming this device. ming settings in Try mode.
Programming Pulse Requirements, Protocol at TA = 25 °C
Characteristic Symbol Notes Min. Typ. Max. Unit
VP(LOW) 4.5 5 5.5 V
Programming
VP(MID) Measured at the VCC pin. 13 15 16 V
Voltage
VP(HIGH) 26 27 28 V
Minimum supply current required to ensure proper fuse blowing. In addition, a
minimum capacitance, CBLOW = 0.1 µF, must be connected between the supply and
Programming
IP GND pins during programming to provide the current necessary for fuse blowing. 300 – – mA
Current
The blowing capacitor should be removed and the load capacitance used for properly
programming duty cycle measurements.
tLOW Duration of VP(LOW) for separating VP(MID) and VP(HIGH) pulses. 40 – – µs
Pulse Width tACTIVE Duration of VP(MID) and VP(HIGH) pulses for register selection or bit field addressing. 40 – – µs
tBLOW Duration of VP(HIGH) pulses for fuse blowing. 40 – – µs
Pulse Rise Time tPr Rise time required for transitions from VP(LOW) to either VP(MID) or VP(HIGH). 5 – 100 µs
Pulse Fall Time tPf Fall time required for transitions from VP(HIGH) to either VP(MID) or VP(LOW). 5 – 100 µs

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 Two-Wire High Precision Linear Hall-Effect Sensor IC
A1357
With Pulse Width Modulated Output Current

Programming Procedures

Mode and Parameter Selection Bit Field Addressing

Each programmable mode and parameter can be accessed through After a programmable parameter has been selected, a VP(HIGH)
specific registers. To select a register, a sequence of voltage pulse transitions the programming logic into the bit field address-
pulses consisting of a VP(HIGH) pulse, a series of VP(MID) pulses, ing state. Applying a series of VP(MID) pulses to the VCC pin of
and a VP(HIGH) pulse (with no VCC supply interruptions) must be the device, as shown in figure 7, increases by one the bit field of
the selected parameter.
applied serially to the supply pin. The quantity of VP(MID) pulses
is called the key, and uniquely identifies each register. The pulse When addressing the bit field, the quantity of VP(MID) pulses
train used for selection of the first register, key 1, is shown in is represented by a decimal number called a code. Addressing
figure 6. activates the corresponding fuse locations in the given bit field
by increasing the binary value of an internal DAC. The value of
The A1357 has two registers that select among the three program- the bit field (and code) increases by one with the falling edge
mable modes: of each VP(MID) pulse, up to the maximum possible code (see
the Programming Logic table). As the value of the bit field code
• Register Mode 1:
increases, the value of the programmable parameter changes.
Blow and Lock modes Measurements can be taken after each pulse to determine if the
• Register Mode 2: required result for the programmable parameter has been reached.
Cycling the supply voltage resets all the locations in the bit field
Try mode that have unblown fuses to their initial states.
And there are four registers that select among the four program-
Fuse Blowing
mable parameters: After the required code is found for a given parameter, its value
• Register 1: can be set permanently by blowing individual fuses in the appro-
priate register bit field. Blowing is accomplished by applying a
Sensitivity, Sens VP(HIGH) pulse, called a blow pulse, of sufficient duration at the
• Register 2: VP(HIGH) level to permanently set an addressed bit by blowing a
fuse internal to the device. Due to power requirements, the fuse
Quiescent Current Duty Cycle, D(Q)
for each bit in the bit field must be blown individually. To accom-
• Register 3: plish this, the code representing the required parameter value
Pulse width modulated carrier frequency , fPWM must be translated to a binary number. For example, as shown
in figure 8, decimal code 5 is equivalent to the binary number
• Register 6: 101. Therefore bit 2 (code 4) must be addressed and blown, the
Lock (device locking) device power supply cycled, and then bit 0 (code 1) addressed

V+ V+
Code 2n – 2

Code 2n – 1

VP(HIGH) VP(HIGH)
Code 1

Code 2

VP(MID) VP(MID)

VP(LOW) VP(LOW)

tLOW
tACTIVE
0 0

Figure 6. Parameter selection pulse train. This shows the sequence for Figure 7. Bit field addressing pulse train. Addressing the bit field by
selecting the register corresponding to key 1, indicated by a single VP(MID) increasing the code causes the programmable parameter value to change.
pulse. The number of bits available for a given programming code, n, varies
among parameters; for example, the bit field for D(Q) has 8 bits available,
which allows 255 separate codes to be used.

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 Two-Wire High Precision Linear Hall-Effect Sensor IC
A1357
With Pulse Width Modulated Output Current

and blown. An appropriate sequence for blowing code 5 is shown • The application load capacitance, CL , should be used when
in figure 9. The order of blowing bits, however, is not important. measuring the duty cycle during programming. The blowing
Blowing bit 0 first, and then bit 2 is acceptable. capacitor, CBLOW , should be removed during measurement and
should only be applied when blowing fuses.
Note: After blowing, the programming is not reversible, even
after cycling the supply power. Although a register bit field fuse • The blowing capacitor, CBLOW , must be replaced in the final
cannot be reset after it is blown, additional bits within the same application with the load capacitance, CL , for proper operation.
register can be blown at any time until the device is locked. For • The power supply used for programming must be capable of
example, if bit 1 (binary 10) has been blown, it is still possible to delivering at least 26 V and 300 mA.
blow bit 0. The end result would be binary 11 (decimal code 3). • Be careful to observe the tLOW delay time before powering
Locking the Device down the device after blowing each bit.
After the required code for each parameter is programmed, the • The following programming order is recommended:
device can be locked to prevent further programming of any
1. fPWM
parameters.
2. Sens
Additional Guidelines
The additional guidelines presented in this section should be fol- 3. D(Q)
lowed to ensure the proper behavior of these devices: 4. Lock the device (only after all other parameters have been
programmed and validated, because this prevents any further
• A 0.1 μF blowing capacitor, CBLOW , must be mounted between programming of the device)
the VCC pin and the GND pin during programming, to ensure
enough current is available to blow fuses. Programming Modes
Try Mode Try mode allows multiple programmable parameters
to be tested simultaneously without permanently setting any
Bit Field Selection
Address Code Format
(Decimal Equivalent)
Code 5
values. In this mode, each VP(HIGH) pulse will indefinitely loop
the programming logic through the mode, register, and bit field
Code in Binary
(Binary) selection states. There must be no interruptions in the VCC supply.
1 0 1
After powering the VCC supply, select mode key 2, followed
Fuse Blowing
Bit 2 Bit 0 by the parameter register, and then address its bit field. When
Target Bits
addressing the bit field, each VP(MID) pulse increases the value
Fuse Blowing Code 4 Code 1
of the parameter register by one, up to the maximum possible
Address Code Format (Decimal Equivalents) code (see Programming Logic section). The addressed parameter
value is stored in the device even after the programming drive
Figure 8. Example of code 5 broken into its binary components, which are voltage is removed from the VCC pin, allowing its value to be
code 4 and code 1. measured. To test an additional programmable parameter in

V+

VP(HIGH)

VP(MID)

1 1 2 1 2 3 4
VP(LOW)
Mode Parameter Addressing Blow
Selection Selection Bitfield 2 Code 4
(Key 1) (Key 2) (Code 4)
0

Cycle VCC tBLOW Cycle VCC

supply supply
tLow

Figure 9. Example of Blow Mode programming pulses applied to the VCC pin. In this example, D(Q)
(Parameter Key 2) is addressed to code 4 (i.e bit 2) and its value is permanently blown.

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 Two-Wire High Precision Linear Hall-Effect Sensor IC
A1357
With Pulse Width Modulated Output Current

conjunction with the original, enter an additional VP(HIGH) pulse Single parameters can be still addressed in the Blow mode before
on the VCC pin to reenter the parameter selection field. Select a fuse blowing. Simultaneous addressing of multiple parameters,
different parameter register, and address its bit field, without any as in Try mode, is not possible. After powering the VCC supply,
supply interruptions. Both parameter values will be stored and select the desired parameter register and address its bit field.
can be measured after removing the programming drive voltage. When addressing the bit field, each VP(MID) pulse increases
Multiple programming combinations can be tested to achieve the value of the parameter register by one, up to the maximum
optimal application accuracy. See figure 10 for an example of the possible code (see Programming Logic table). The addressed
Try mode pulse train. parameter value is stored in the device even after the program-
ming drive voltage is removed from the VCC pin, allowing its
Registers can be addressed and re-addressed an indefinite number value to be measured. It is not possible to decrease the value of
of times in any order. After the required code is found for each the register without resetting the parameter bit field. To reset the
register, cycle the supply and blow the bit field using Blow mode. bit field, and thus the value of the programmable parameter, cycle
the supply, VCC, voltage.
Blow Mode After the required value of the programmable
parameter is found using Try mode, the corresponding code It is possible to switch between Try and Blow modes in that, after
should be blown to make the value permanent. To do this, first individual programmable parameters have been blown in Blow
select Blow mode as key 1, then the required parameter register, mode, other parameters can be still tested in Try mode.
and address and blow each required bit separately (as described Lock Mode To lock the device, first select Lock mode, then
in the Fuse Blowing section). The supply must be cycled between address the Lock bit and apply a blow pulse with CBLOW in place.
blowing each bit of a given code. After a bit is blown, cycling the After locking the device, no future programming of any param-
supply will not reset its value. eter is possible.

V+

VP(HIGH)

VP(MID)

1 2 1 1 2 3 1 2 1 2
VP(LOW)
Mode Parameter Parameter
Selection Selection Addressing Selection Addressing
(Key 2, Try Mode) (Key 1) (Code 3) (Key 2) (Code 2)
0

Figure 10. Example of Try mode programming pulses applied to the VCC pin. In this example,
Sensitivity (parameter key 1) is addressed to code 3, and D(Q) (parameter key 2) is addressed
to code 2. The values set in the Sensitivity and D(Q) registers will be held in the device until the
supply is cycled. Permanent fuse blowing cannot be accomplished in Try mode.

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 Two-Wire High Precision Linear Hall-Effect Sensor IC
A1357
With Pulse Width Modulated Output Current

Programming State Machine

VP(MID)

VP(HIGH)
VP(HIGH)

VP(MID) VP(MID)
VP(MID)

2 x VP(HIGH)
VP(HIGH)

VP(MID) 1 VP(MID) 2 VP(MID) 3 VP(MID) 6 VP(MID)

(Sens (fPWM/
Range1/ (D(Q)) Calibration (Lock All)
Range2) Test Mode)

VP(HIGH)
VP(HIGH)

VP(MID) VP(MID) VP(MID) VP(MID)

VP(HIGH)

Select Mode

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 Two-Wire High Precision Linear Hall-Effect Sensor IC
A1357
With Pulse Width Modulated Output Current

Programming Logic Table

Mode or Parameter Bit Field Address

Name Description
(Register Key) Binary Format
Decimal Equivalent Code
[MSB → LSB]
Programmable Mode
Lock, Blow
01 1 Entry to Lock or Blow mode
(1)
Try
10 2 Entry to Try mode
(2)
Programmable Parameter
Minimum Sens value in SensRange1, Sens =
0 0000 0000 0
SensPRE 
Sens
(Range1/Range2) 0 1111 1111 255 Maximum Sens value in SensRange1
(1) 1 0000 0000 256 Minimum Sens value in SensRange2
1 1111 1111 511 Maximum Sens value in SensRange2
0 0000 0000 0 Initial value, D(Q) = D(Q)PRE
0 1111 1111 255 Maximum quiescent current duty cycle in range
D(Q)
(2) Switch from programming increasing D(Q) to
1 0000 0000 256
programming decreasing D(Q)
1 1111 1111 511 Minimum quiescent current duty cycle in range
0 0000 0000 0 Initial value; fPWM = fPWMPRE
fPWM /
Calibration Test Mode 0 0000 1111 15 Minimum PWM frequency in range
(3)
0 0001 0000 16 Enable 50% Duty Cycle Calibration Test Mode
Lock All
10 0000 0000 512 Enable blowing Lock fuse to lock device
(6)

D(Q) fPWM
Sens (Hz)
(%)
(%/gauss)
fPWMPRE
D(Q)(max)

Quiescent Current
Duty Cycle Range fPWM(max)
D(Q)PRE

fPWM(min)

D(Q)(min)

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 Two-Wire High Precision Linear Hall-Effect Sensor IC
A1357
With Pulse Width Modulated Output Current

50% Duty Cycle Calibration Test Mode

The calibration mode is provided so that the user can compensate powered via different power and ground circuits. As a result, the
for differences in the ground potential between the A1357 and ground reference for the A1357 may differ from the ground refer-
any interface circuitry used to measure the pulse width of the ence of the system controller. In some customer applications, this
A1357 current. The test mode is optional and must be enabled ground difference can be as large as ±0.5 V.
by blowing programming bits. After the bit for the test mode has
Differences in the ground reference for the A1357 and the system
been blown, the device enters 50% Duty Cycle Calibration Test
controller can result in variations in the threshold voltage used
mode every time the device is powered-up. The bit enabling test
to measure the duty cycle of the A1357. If the PWM conversion
mode is key 3, bit 4.
threshold voltage varies, then the duty cycle will vary because
In customer applications, the PWM interface circuitry (shown there is a finite rise time, tr , and fall time, tf , in the PWM wave-
as the system controller in figure 11) and the A1357 may be form. This problem is shown in figure 12.

1
VCC
VSUPPLY
A1357 System
CBYPASS Controller
0.1 µF
GND
2

RSENSE

GND1 GND2

Figure 11. In many applications the A1357 may be powered using a different ground reference
than the system controller. This may cause the ground reference for the A1357 (GND1) to differ
from the ground reference of the system controller (GND2) by as much as to ± 0.5 V.

PWM period
Threshold Voltage,

Vth (high)
3.5
Vth (centered)
Vth (V)

2.5
Vth (low)
1.5

∆tr ∆tf Time

Duty Cycle
shorter than
expected

Duty Cycle at
expected duration

Duty Cycle longer

than expected
Figure 12. When the threshold voltage, Vth , is correctly centered between Vth (high)  and Vth (low) , the current duty cycle
accurately coincides with the applied magnetic field. If the threshold voltage is raised, the current duty cycle appears shorter
than expected. Conversely, if the threshold voltage is lowered, the current duty cycle is longer than expected.

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 Two-Wire High Precision Linear Hall-Effect Sensor IC
A1357
With Pulse Width Modulated Output Current

The 50% Duty Cycle Calibration Test mode allows end users to pare the measured quiescent duty cycle with an ideal 50% duty
compensate for any threshold errors that result from a difference cycle. After tCAL has elapsed, the duty cycle will correspond to
in system ground potentials. When calibration mode has been an applied magnetic field as expected. The calibration test time
enabled, at power-up the device operates initially in calibration
(tCAL) corresponds with a target PWM frequency of 1 kHz. If the
mode for tCAL , 50 ms, during which the device current waveform
has a fixed 50% duty cycle (the programmed quiescent duty PWM frequency is programmed away from its target of 1 kHz,
cycle, D(Q) , value) regardless of the applied external magnetic the duration of the calibration test time will scale inversely with
field (see figure 13). This allows the system controller to com- the change in PWM frequency.

Calibration sequence PWM proportional to

magnetic field

Figure 13. With calibration mode in effect, after powering-on the A1357 outputs a 50%
duty cycle for the first 50 ms, tCAL , regardless of the applied magnetic field. After tCAL has
elapsed, the output responds to a magnetic field as expected. The example in this figure
assumes that a large +B field is applied to the device after tCAL has elapsed.

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 Two-Wire High Precision Linear Hall-Effect Sensor IC
A1357
With Pulse Width Modulated Output Current

Package KB, 3-Pin SIP

+0.08
5.21 –0.05

45°
B C

2.60 D 1.55 ±0.05

1.33 D Mold Ejector

Pin Indent NNNN
+0.08
3.43 –0.05
YYWW
D Branded 45°
Face
1
2.16 0.84 REF
E Standard Branding Reference View
MAX
N = Device part number
A Y = Last two digits of year of manufacture
W = Week of manufacture

14.73 ±0.51
For Reference Only; not for tooling use (reference DWG-9009)
Dimensions in millimeters
+0.07
0.51 –0.05 +0.06 Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
0.38 –0.03
Exact case and lead configuration at supplier discretion within limits shown

A Dambar removal protrusion (6X)

B Gate and tie bar burr area
C Active Area Depth 0.43 mm REF
1 2 3 D Hall element (not to scale)
E Branding scale and appearance at supplier discretion

1.90 NOM

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 Two-Wire High Precision Linear Hall-Effect Sensor IC
A1357
With Pulse Width Modulated Output Current

Revision History
Number Date Description
– April 23, 2013 Initial release
1 February 19, 2019 Minor editorial updates

Copyright ©2019, Allegro MicroSystems, LLC

Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.

For the latest version of this document, visit our website:

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