DesignWare IP Portfolio

Broad IP Portfolio
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare® IP portfolio includes logic
libraries, embedded memories, PVT sensors, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems. 

To accelerate your product development cycle, Synopsys’ IP Accelerated initiative offers SoC architecture design support, IP subsystems,
signal integrity/power integrity analysis and IP hardening, IP prototyping kits, and comprehensive silicon bring-up support. 

Synopsys’ extensive investment in IP quality, comprehensive technical support and robust IP development methodology enable designers to
reduce integration risk and accelerate time-to-market.

Interface IP

Process Technologies
HS
Controllers/ Verification
USB 14/ Features
Access
IP
55/65 40/45 28 22 20 12nm 10nm 7nm 5/6nm
nm nm nm nm nm 16nm FinFET FinFET FinFET FinFET & Test
FinFET

USB4 ü ü ü Device, Router ü ü

USB 3.2 ü ü Device, Host ü ü
Dual-Role Device
USB 3.1 ü ü ü ü ü ü
(Device & Host)
Dual-Role Device
USB-C 3.1 ü ü ü ü ü ü
(Device & Host)
Device, Host,
USB-C 3.1/
DisplayPort Tx,
DisplayPort ü ü ü ü ü ü ü
Subsystem Solution
1.4
for 16FFC
Dual-Role Device,
USB 3.0 ü ü ü ü ü ü ü ü ü
Device, Host
USB-C 3.0 ü ü ü ü Device, Host ü ü
Device, Host, Dual-
USB 2.0 ü ü ü ü ü ü ü ü ü ü ü ü
Role Device
Device, Host,
USB-C 2.0 ü ü ü ü ü ü ü ü ü ü ü ü
Dual-Role Device
Device, Host,
eUSB2 ü ü ü
Dual-Role Device

Process Technologies Con-

IDE HS Verifi-
PCI fig-
40/45/ 12/14/ Controllers Security Access cation
Express 55/65
28 22 20
16nm
10nm 8nm 7nm 5/6nm ura-
Module & Test IP
nm nm nm FinFET FinFET FinFET FinFET tion
nm FinFET

PCIe 6.0 ü ü ü
Endpoint, Root x1,
Port, Dual x2,
PCIe 5.0 ü ü ü ü Mode, Switch, x4, ü ü ü
Embedded x8,
Endpoint x16
Endpoint, Root x1,
Port, Dual x2,
PCIe 4.0 ü ü ü ü Mode, Switch, x4, ü ü
Embedded x8,
Endpoint x16
Endpoint, Root x1,
Port, Dual x2,
PCIe 3.1 ü ü ü ü ü ü ü Mode, Switch, x4, ü ü
Embedded x8,
Endpoint x16
Endpoint, Root x1,
Port, Dual x2,
PCIe 2.1 ü ü ü ü ü ü Mode, Switch, x4, ü ü
Embedded x8,
Endpoint x16

synopsys.com/designware  2 Q1 2022
 Interface IP

Process Technologies IDE

Configu-
CXL Controllers
rations
Security Verification IP
14/16nm 10nm 7nm 5/6nm
FinFET FinFET FinFET FinFET Module

Device, Host, x1, x2, x4,

CXL 2.0 ü ü ü ü ü ü
Dual Mode, Switch Port x8, x16

Process Technologies
CCIX Controllers Verification IP
14/16nm 12nm FinFET 7nm FinFET 5/6nm FinFET
FinFET

Endpoint, Root Port, Dual Mode,

CCIX 1.0 ü ü ü ü Switch
Endpoint, Root Port, Dual Mode,
CCIX 1.1 ü ü ü ü Switch

Process Technologies
Verification
HDMI Controllers
IP
65 55 40/45 28 14/16nm 12nm 7nm 5nm
nm nm nm nm FinFET FinFET FinFET FinFET

HDMI 2.1 ü ü ü ü ü ü
HDMI 2.0 ü ü ü ü ü ü

Process Technologies Platform

Verification
DDR Controllers Architect
IP
40/45 28 22 14/16nm 12nm 10nm 7nm 5nm
nm nm nm FinFET FinFET FinFET FinFET FinFET Support

Memory
LPDDR5 ü ü ü ü ü ü
controller
Protocol
controller,
LPDDR4 ü ü ü ü ü ü ü ü ü
Memory
controller
Protocol
controller,
LPDDR4X ü ü ü ü ü ü
Memory
controller
Protocol
controller,
LPDDR3 ü ü ü ü ü ü ü ü
Memory
controller
Protocol
controller,
LPDDR2 ü ü ü ü ü
Memory
controller
Memory
DDR5 ü ü ü ü ü ü ü
controller
Protocol
controller,
DDR4 ü ü ü ü ü ü ü ü ü ü
Memory
controller
Protocol
controller,
DDR3 ü ü ü ü ü ü ü ü
Memory
controller
Protocol
controller,
DDR2 ü ü ü ü
Memory
controller

synopsys.com/designware  3 Q1 2022
 Interface IP

Process Technologies
HBM Controllers Verification IP
14/16nm FinFET 7nm FinFET 5nm FinFET

HBM3 ü ü ü
HBM2 ü ü ü
HBM2E ü ü ü ü

Process Technologies
Verification
MIPI Controllers
IP
40/45 28 22 20 14/16nm 12nm 7nm 5nm
nm nm nm nm FinFET FinFET FinFET FinFET

C/D-PHY ü ü ü ü CSI-2, DSI/DSI-2 ü

D-PHY ü ü ü ü ü ü ü CSI-2, DSI/DSI-2 ü
M-PHY ü ü ü ü ü UFS, UniPro ü
CSI-2 Host, Device ü
DSI Host, Device ü
DSC Encoder, Decoder ü
DSI + DSC DSI/DSI-2 + DSC Encoder
UniPro v1.6, v1.8, v2.0 ü
I3C Multi-role, Target-Lite ü

Process Technologies
Verification
Ethernet PCS Controllers
IP
14/16nm 7nm 5nm
28nm FinFET FinFET FinFET

112G Ethernet (100G/200G/400G/800G) ü ü ü ü

56G Ethernet (100G/200G/400G) ü ü ü ü ü
RXAUI/Double XAUI (6.25 G) ü ü ü ü ü ü
1000BASE-KX, Energy Efficient Ethernet, 10GBASE-KR,
10GBASE-KX4
ü ü ü ü ü ü

40GBASE-KR4, 40GBASE-CR4, XLAUI ü ü ü ü ü ü

100GBASE-CR10, CAUI ü ü ü ü ü ü

SGMII ü ü ü ü ü ü
QSGMII ü ü ü ü ü ü
XFI, SFI (SFF-8431) ü ü ü ü ü ü
GMII/MII, RGMII, RTBI, TBI, SMII, RMII, RevMII, XGMII,
XLGMII
ü ü ü

IEEE TSN/AVB Standards: IEEE 802.1AS, 802.1AS-Rev,

802.1Qav, 802.1Qat, 802.1Qbv, 802.1Qbu & 802.3br
ü ü

25G/50G Ethernet Consortium and IEEE specifications ü ü ü ü ü

2.5G/5.0G USXGMII ü ü ü ü ü
Additional Enterprise Protocols
OIF, CEI-6G/11G ü ü ü
CPRI, OBSI, JESD204 A/B ü ü ü ü
SRIO ü ü ü

Process Technologies
Verification
Die-to-Die PCS Controllers
IP
14/16nm 12nm 7nm 5nm
28nm FinFET FinFET FinFET FinFET

Die-to-Die HBI/AIB ü ü NA
Die-to-Die 112G USR/XSR ü ü ü NA ü

synopsys.com/designware  4 Q1 2022
 Interface IP

Process Technologies
Verification
SATA Controllers
IP
14/16nm 7nm
65nm 55nm 40/45nm 28nm 22nm FinFET FinFET

SATA 6G ü ü ü ü ü ü ü Host, Device ü

SATA 3G ü ü ü ü ü ü Host, Device ü

Process Technologies
Bluetooth, Thread, Zigbee Controller (Link Layer / Mac)
55nm 40nm

Bluetooth LE 5.2 ü ü ü
IEEE 802.15.4 (Thread, Zigbee) ü ü ü
Combo Bluetooth LE/IEEE 802.15.4 ü ü ü

Process Technologies
Verification
Mobile Storage Controllers
IP
14/16nm 12nm 10nm 7nm 6nm 5nm
28nm FinFET FinFET FinFET FinFET FinFET FinFET

UFS ü ü
UniPro ü ü
M-PHY ü ü ü ü ü ü ü ü ü
eMMC ü ü ü ü ü ü ü
SD ü ü ü ü ü ü ü
SDIO ü ü ü ü ü ü ü

AMBA Synthesizable IP Verification IP

AXI 3 and AXI 4 Bus Fabric,

Bridges, and Infrastructure IP
ü ü

AHB5 Bus Fabric ü ü

AHB and AXI DMA Controllers ü ü
SSI Controller (SPI/xSPI) ü ü
AMBA Peripherals (I C, I S, UART)
2 2
ü ü
Timers, Interrupt Controllers,
GPIOs, Interconnect Matrices
ü ü

Datapath IP Synthesizable IP Simulation Models (C++, Verilog) Verification Models

Floating Point Functions ü ü ü

Fixed Point Functions ü ü ü
Trigonometric Functions ü ü ü

Analog IP

Process Technologies
Data Channel
Bits MSPS
Converters 90nm 55nm 40nm 28nm 22nm 12/16nm Configuration
FinFET

300-1000 MSPS ADCs ü ü ü 12 320 to 750 Single, Dual

150-300 MSPS ADCs ü ü ü 10, 12 160 to 250 Single, Dual
10-150 MSPS ADCs ü ü ü 10, 12 80 to 125 Single, Dual
<10 MSPS ADCs ü ü ü ü ü ü 10, 12, 14 1 to 5 Single

300-1000 MSPS DACs ü ü ü 12 320 to 1000 Single, Dual

<100 MSPS DACs ü ü ü ü 11, 12 20 Single

synopsys.com/designware  5 Q1 2022
 Foundation IP

Process Technologies
Embedded Memories
40/ 14/16nm 12nm 10nm 8nm 7/6nm 5nm 4nm
65nm 55nm 28nm 22nm
45nm FinFET FinFET FinFET FinFET FinFET FinFET FinFET

Ternary Content-Addressable
Memory (TCAM)
ü ü ü ü ü ü ü ü ü

Multi-port Memories ü
High-Speed Single Port
SRAM
ü ü ü ü ü ü ü ü ü ü ü ü

High-Speed Dual Port SRAM ü ü ü ü ü ü ü ü ü

High-Speed 1P Register File
(RF) (Cache)
ü ü ü ü ü ü ü ü ü ü ü ü

High-Speed Asynchronous
2-Port Register File
ü ü ü

High Performance Core

(HPC) Design Kit
ü ü ü ü ü ü ü ü

High Speed 2P RF ü ü ü
High Speed Pseudo 4P/QP
SRAM
ü ü ü ü

High-Density Single Port

SRAM
ü ü ü ü ü ü ü ü ü ü ü

High-Density Dual Port SRAM ü ü ü ü ü ü ü ü ü

High-Density 1P RF ü ü ü ü ü ü ü ü ü ü ü
High-Density 2P RF ü ü ü ü ü ü ü ü
High-Density 3P RF ü
High-Density ROM ü ü ü ü ü ü ü ü ü ü ü ü
High-Density 2P,3P Async
Latch Based Compiler
ü ü ü

UHD 1P RF ü ü ü
UHD Single Port SRAM ü ü ü ü ü
UHD 2P RF ü ü ü ü ü ü ü ü ü ü ü ü
UHD 2P SRAM ü ü ü ü ü ü

Process Technologies
Logic Libraries
40/ 14/16nm 12nm 8nm 7nm 6nm 5nm 4nm
65nm 55nm 28nm 22nm
45nm FinFET FinFET FinFET FinFET FinFET FinFET FinFET

High-Speed Library ü ü ü ü ü ü ü ü ü ü
High-Speed POK ü ü ü ü ü ü ü ü ü
High-Density Library ü ü ü ü ü ü ü ü ü ü ü
High-Density POK ü ü ü ü ü ü ü ü ü ü ü
UHD Library ü ü ü ü ü ü ü ü ü
UHD POK ü ü ü ü ü ü ü ü ü
Ultra-low leakage (thick
oxide)
ü ü ü ü

High-Performance Core
(HPC) Design Kit
ü ü ü ü ü ü ü ü ü ü

Enhanced Reliability Kit ü

Process Technologies
Process Technologies
I/O Products
22nm 14/16nm FinFET 12nm FinFET 6/7nm FinFET 5nm FinFET 4nm FinFET

General-purpose I/Os ü ü ü ü ü ü
Specialty I/Os ü ü ü ü ü

synopsys.com/designware  6 Q1 2022
 Foundation IP

Process Technologies Endurance

Non-Volatile Memory Bit Counts (Write
150/ 110/ 80/90 55/65 40 28 22 14/16nm 12nm
180nm 130nm nm nm nm nm nm FinFET FinFET Cycles)

16 bit to 1 1 per
One-Time Programmable (OTP) ü ü ü ü ü ü ü ü ü Mbit instance
Multi-Time Programmable (MTP) 16 bit to
180nm Up to 1,000
Medium-Density 512 Kbit
128 bit to Up to
MTP EEPROM 180nm ü ü ü 8 Kbit 1,000,000
Up to
MTP ULP ü 64 bit to 4 Kbit
100,000
Few-Time Programmable (FTP) Trim ü ü 64 bit to 4 Kbit Up to 1,000

Foundation IP

Process Technologies
Embedded In-Chip Sensing &
PVT Monitoring IP 28nm 16nm 12nm 7nm 6nm 5nm
FinFET FinFET FinFET FinFET FinFET

Hard IP

Process Detector ü ü ü ü ü ü

Voltage Monitor ü ü ü ü ü ü
Temperature Sensor ü ü ü ü ü ü
Distributed Thermal Sensor ü ü
Thermal Diode ü ü ü ü
Catastrophic Trip Sensor ü ü
In-Chip PVT Monitoring & Sensing
Subsystem
ü ü ü ü ü ü

Soft IP

PVT Controller ü ü ü ü ü ü
Software Driver ü ü

Security IP

Security Synthesizable IP Software

Cryptography IP ü ü
Security Protocol Accelerators ü ü
Hardware Secure Modules with Root of Trust ü ü
HDMI/DisplayPort/USB Type-C Content
Protection IP
ü ü

PCIe & CXL Integrity and Data Encryption IP ü ü

synopsys.com/designware  7 Q1 2022
Accelerate Development of Performance-Efficient SoCs
Synopsys’ DesignWare ARC® Processors are a family of 32-/64-bit CPUs and DSPs that SoC designers can optimize for a wide range of uses,
from deeply embedded to high-performance host applications in a variety of market segments. Designers can differentiate their products by
using patented configuration technology to tailor each ARC processor instance to meet specific performance, power and area requirements.
The DesignWare ARC processors are also extensible, allowing designers to add their own custom instructions that dramatically increase
performance. Synopsys’ ARC processors have been used by over 250 customers worldwide who collectively ship more than 2.5 billion ARC-
based chips annually.

All DesignWare ARC processors utilize a 16-/32-/64-bit ISA that provides excellent performance and code density for embedded and host
SoC applications. The RISC and DSP processors are synthesizable and can be implemented in any foundry or process, and are supported by
a complete suite of development tools.

DesignWare ARC processors are supported by a broad ecosystem of commercial and open source tools, operating systems and
middleware. This includes offerings from leading industry vendors who are members of the ARC Access Program as well as a
comprehensive suite of free and open source software available through embARC.org.

Processor IP

Max CCM Cache Enhanced

Safety Floating
ARC 32-bit Processors Size Size DSP MPU
Certified
Security MMU
Point
Trace
(I&D) (I&D) Package

EM4 2MB ü ü ü ü
EM6 2MB 64K ü ü ü ü
EM5D 2MB ü ü ü ü ü
EM7D 2MB 64K ü ü ü ü ü
EM9D 2MB ü ü ü ü
EM11D 2MB 64K ü ü ü ü
EM22FS 2MB 64K ü ü ü ü ü
SEM110 2MB ü ü
SEM120D 2MB ü ü ü
SEM130FS 2MB ü ü ü ü
605 LE 512KB ü
710D 512KB ü ü ü ü
725D 512KB 64K ü ü ü ü
770D 512KB 64K ü ü ü ü ü
610D 512KB ü ü ü ü
625D 512KB 32K ü ü ü ü
AS211SFX 512KB 32K ü ü ü ü
512KB ea 32K ea
AS221BD (dual-core) ü ü ü ü
core core

synopsys.com/designware  8 Q1 2022
 ARC HS Max CCM L1 Cache Safety L1 Floating
DSP L2 Cache MMU Trace
32-bit Processors Size (I & D) Certified Coherency Point

HS34, HS34x2, HS34x4 16MB ü ü

HS36, HS36x2, HS36x4 16MB 64K ü ü ü
HS38, HS38x2, HS38x4 16MB 64K ü 8MB ü ü ü
HS44, HS44x2, HS44x4 16MB ü ü
HS46, HS46x2, HS46x4 16MB 64K ü ü ü
HS48, HS48x2, HS48x4 16MB 64K ü 8MB ü ü ü
HS45D, HS45Dx2, HS45Dx4 16MB ü ü ü
HS47D, HS47Dx2, HS47Dx4 16MB 64K ü ü ü ü
HS46FS, HS46FSx4 16MB 64K ü ü ü ü
HS47DFS, HS47DFSx4 16MB 64K ü ü ü ü ü
HS48FS, HS48FSx4  16MB 64K ü ü 8MB ü ü ü
HS56, HS56MP 16MB 64K ü 64MB (MP) SIMD ü
HS57D, HS57DMP 16MB 64K ü ü 64MB (MP) SIMD ü
HS58, HS58MP 16MB 64K ü 64MB ü SIMD ü

ARC HS Max CCM L1 Cache Safety L1 Shared L2 Floating

DSP MMU Trace
64-bit Processors Size (I & D) Certified Coherency Cache/ Cluster Mem. Point

HS66, HS66MP 16MB 64K ü 64MB (MP) SIMD ü

HS68, HS68MP 16MB 64K ü 64MB ü SIMD ü

Processor IP

ARC VPX Dual Dual Floating Floating Point

Scalar Vector
Vector SIMD Point Vector Vector Safety L1 Multicore
DSP Execution Execution
Length Multiply Engine Math Engine Certified Coherency configurations
Processors Unit Unit
Units (optional) (optional)

VPX2 ü 3 128-bit ü ü ü ü 2x

VPX2FS ü 3 128-bit ü ü ü ü ü 2x
VPX3 ü 3 256-bit ü ü ü ü 2x
VPX3FS ü 3 256-bit ü ü ü ü ü 2x
VPX5 ü 3 512-bit ü ü ü ü 2x, 4x
VPX5FS ü 3 512-bit ü ü ü ü ü 2x, 4x

Embedded DNN/CNN Vision # of Vector L1 Floating Vector

32-bit Safety
Vision Accelerator CPU DMA
Scalar
Vector DSP Bit Cache Point Unit Floating
Certified
Processors (MACs) MACs DSPs Width Coherency (FPU) Point Unit

880, 1,760, or
EV71 64 ü 1 1 512 ü ü
3,520
880, 1,760, or
EV72 128 ü 2 2 512 ü ü ü
3,520
880, 1,760, or
EV74 256 ü 4 4 512 ü ü ü
3,520
880, 1,760, or
EV71FS 64 ü 1 1 512 ü ü ü
3,520
880, 1,760, or
EV72FS 128 ü 2 2 512 ü ü ü ü
3,520
880, 1,760, or
EV74FS 256 ü 4 4 512 ü ü ü ü
3,520

synopsys.com/designware  9 Q1 2022
 ARC Processor Supported Hardware Integrated
Included Software
IP Subsystems ARC Processors Accelerators Peripherals

SPI, UART(s), GPIO,

IoT Communications IP DSP library, base communications
EM11D ü Digital Front End (DFE),
Subsystem library, device drivers
PMU and RTC
DSP library, audio processing
EM5D, EM7D, EM9D, SPI, I2C, I2S, UART, PDM,
Data Fusion IP Subsystem ü library, peripheral I/O drivers (bare
EM11D ADC I/F, APB I/F, GPIO
metal), reference designs
DSP library, motor control library,
Sensor and Control IP SPI, I2C, PWM, UART, ADC
EM4, EM6 ü peripheral I/O drivers (bare metal),
Subsystem I/F, DAC I/F, APB I/F, GPIO
reference designs

IP Accelerated Initiative
With IP Accelerated, Synopsys has augmented its broad portfolio of silicon-proven DesignWare IP with SoC architecture design support, IP
subsystems, signal integrity/power integrity analysis and IP hardening, IP prototyping kits, and comprehensive silicon bring-up support to
accelerate your product development cycle.

IP Subsystems support many protocols and deliverables for IP integration including configuration scripts, test environment, test scripts,
linting, CDC checks, RDC checks, synthesis scripts and implementation scripts. The subsystems also include AMBA or native bus, clock
management, reset, DMA, interrupts, memory, power management, debug and test logic.

Hardening and SIPI provide a GDSII for integration in an SoC and include On-chip decoupling capacitance, power and ground pins, PHY &
SDRAM termination strategy, SoC package design, PCB stack-up and trace width/spacing, performance at required data rate, read/write/
address, and command/control timing budgets.

With your vision and our expertise, we can tune IP to your SoC, enabling your team to focus on product differentiation.

IP Subsystems

Multi-Protocol
Interface IP Subsystems Supported IP
Support
Integrated Logic Included Scripts

AMBA or native bus, Configuration scripts, test

USB, PCIe, DDR, Ethernet,
clock management, reset, environment, test scripts,
HDMI, MIPI, AMBA,
IP Protocol-Specific Subsystems ü DMA, interrupts, memory, linting, CDC checks, RDC
Security, MACsec, PCIe
power management, checks, synthesis scripts,
switch, CXL 2.0 switch
debug and test logic implementation scripts

Combo SRAM/
Interface IP Subsystems Subsystems
ASIL-B UVM Spyglass
MBIST
UPF DFT

PCIe-Ethernet, PCIe-USB,
PCIe/CXL
PCIe-SATA PCIe-CCIX, CXL

DDR3/4/5 DDR-LPDDR4/4X/5

HBM ü
Ethernet-PCIe,
Ethernet ü ü ü ü ü ü
Ethernet-USB
USB-DP, USB-DP-HDMI,
USB
USB-PCIe, USB-Ethernet

HDMI HDMI-DP, HDMI-USB-DP

MIPI ü

Combo SRAM/
Configurable IP Subsystems Subsystems
ASIL-B UVM Spyglass
MBIST
UPF DFT

CXL 2.0 switch

PCIe switch ü ü ü ü ü ü ü
MACsec

synopsys.com/designware  10 Q1 2022
 Signal/Power Integrity Analysis & IP Hardening

Supported IP Multi-Protocol Support Consultation Expertise

DDR, LPDDR, On-chip decoupling capacitance, power and ground pins, PHY &
HBM, PCIe, USB, SDRAM termination strategy, SoC package design, PCB stack-up and
MIPI, Ethernet,
ü trace width/spacing, performance at required data rate, read/write/
HDMI address, command/control timing budgets

IP Hardening

Multi- Bump
Synthesis Floor Scan Power Skew RDL IR/EM- DRC/
Supported IP protocol
to GDSII Planning Insertion Grid Balancing Routing
Assign-
Analysis LVS
GLS
Support ment

DDR/LPDDR
HBM2E / HBM3 ü ü ü ü ü ü ü ü ü ü ü
PCIe

Signal/Power Integrity Analysis

Signal
Multi- Pre/Post Decap Cell Power Eye End to Timing
Floorplan Quality PVT Full
Supported IP protocol
Review
Layout Size/ Impedance Quality End Budget
Corner Report
Support Analysis Placement Simulations Analysis Analysis Analysis
Analysis

DDR/LPDDR
HBM2E / HBM3
HBI
PCIe ü ü ü ü ü ü ü ü ü ü
MIPI
Ethernet

IP Prototyping Kits and Software Development Kits

IP Prototyping IP Prototyping
IP Prototyping IP Prototyping
Kit with PCIe Kit with PCIe
Kit with ARC SDP Kit with ARC HSDK
Connection to PC Connection to PC Custom IP
Protocol/Standard Prototyping Kits
Soft Deliverable Soft Deliverable Soft Deliverable Soft Deliverable

HAPS-80 HAPS-80 HAPS-100 HAPS-100

USB 3.1 Host ü

USB 3.1 Device ü
CXL 2.0 EndPoint ü
CXL 2.0 Root Complex ü
PCIe 5.0 Endpoint ü
PCIe 5.0 Root Complex ü
PCIe 4.0 Endpoint ü
PCIe 4.0 Root Complex ü
PCIe 3.0 Endpoint ü ü
PCIe 3.0 Root Complex ü ü

For more information on DesignWare IP, visit synopsys.com/designware.

©2022 Synopsys, Inc. All rights reserved. Synopsys is a trademark of Synopsys, Inc. in the United States and other countries. A list of Synopsys trademarks is
available at synopsys.com/copyright.html . All other names mentioned herein are trademarks or registered trademarks of their respective owners.
02/02/22.CS823979754 SG | DWIP Portfolio Brochure Q1 22-English.