CDC Synchronization Best Practices
CDC Synchronization Best Practices
TM
Synchronization Techniques
• Single-bit CDC solutions
• Multi-bit CDC solutions
– CDC handshake protocols
• Reset synchronizer
Errors in Synchronization
• Common synchronization errors
• CDC errors seen in our silicon
Synchronization Techniques
• Single-bit CDC solutions
• Multi-bit CDC solutions
– CDC handshake protocols
• Reset synchronizer
Errors in Synchronization
• Common synchronization errors
• CDC errors seen in our silicon
in out clk
D Q
(from different
clock domain) in
clk
out
metastable
OR
aclk bclk
What if Q1 still isn’t stable before the pmc_sync_flop
next clock edge? Add another
retiming flop!
aclk
adat
More considerations are
needed to safely pass data
from one clock domain to bclk
another async domain. pmc_sync_flop
_sample
pmc_sync_flop
_retime[0]
Synchronization Techniques
• Single-bit CDC solutions
• Multi-bit CDC solutions
– CDC handshake protocols
• Reset synchronizer
Errors in Synchronization
• Common synchronization errors
• CDC errors seen in our silicon
pmc_sync_flop
• can model metastability in simulation to _retime[0]
busy_w
• Guarantees no pulse level_w
squelching. CDC CDC
clk_r
• Destination domain can delay retiming
the pulse output using stall_r pulse_r
level_r
stall_r
a_en
Could result in incorrect data d q
bq1_en
d q
bq2_en
en
domain. bclk
bq1_load
In both of these scenarios, the CDC signals will require some form of
synchronization into the receiving clock domain.
Gray encoder
Gray decoder
pipeline flop
gray-encoded bus across clock 010 011 010
011 010 011
domains !
100 110 100
Gray-encodes the input bus or optionally 101 111 101
accepts an already gray-encoded input 110 101 110
bus. aclk 111 100 111 bclk
Instantiates multiple pmc_sync_flops for domain domain
transferring the gray-code bus.
models metastability based on Gray- aclk
encoded bus behavior. gc_in[2]
• Scenario #1: gray-code synchronizer gc_in[1]
does not capture every legal value if gc_in[0]
destination clock frequency is less than
source clock frequency. bclk
1
data_B[2]
clkB
1
data_B[1]
clkB
Source data must be held constant clkA
asserted.
1
clkB
clkA
enable_sync
0
data_B[2]
data_A[2] 1
clkB
clkA
0 data_B[1]
data_A[1] 1
clkB
clkA
0
data_B[0]
data_A[0] 1
clkB
clkA
rising edge
pmc_sync_flop detect
enable enable_d
enable_sync
clkA clkB
ack
clkA
Timeout
Timer
rstb_A rstb_B
Handshake controller
start
busy
done
sample
req
ack_sync
clk_B
req_sync
ack
capture
valid
Wait state
ready
A handshake cycle
bus synchronizer 0 D Q 0
D
Q 0
D
Q D Q D Q 0
D
Q
1 1 1 1
(cad_dd_00980). clk_b
sample_b
retime_b_0
loop_b_a
pong
backpressure. rstb_A
pong_w pong_r
rstb_B
rstb_w rstb_r
Suitable for low-bandwidth clk_A
clk_w clk_r
clk_B
channels.
data_A data_B
enqueue_A dequeue_B
full_A empty_B
Asynchronous FIFO
rstb_A rstb_B
clkA clkB
read_req
fifo_clrb fifo_clr_ busy
write_data din
clk wclk clk
rclk
rstb wrstb rrstb rstb
W Clock
R Clock
W Reset
R Reset
LW16_48_06_A/RESET_SYNC_
retiming_flop1 (Q)
retiming_flop2 (Q)
V3 in your depend.txt. retiming_flop3 (Q)
Synchronization Techniques
• Single-bit CDC solutions
• Multi-bit CDC solutions
– CDC handshake protocols
• Reset synchronizer
Errors in Synchronization
• Common synchronization errors
• CDC errors seen in our silicon
• Sending entire multi-bit data buses to the receiving clock domain via
arrays of N-flop synchronizers
• Implementing combinational logic immediately before a synchronizer
• Failing to ensure stable data in the transmitting clock domain
• Divergent and reconvergent paths in synchronization logic
• Not implementing proper CDC handshaking protocols
• Omitting or forgetting synchronization logic completely
dA1
dA1
dA2
dA2
INCORRECT
dA
clkA clkB
clkB
dA S dB
S
dA1
dB
dA2
clkB
dA dA1 S1 dB1
dB1
clkA dB2
dB2
Move point of
divergence after
synchronizer
CORRECT
dA 2 missed first clkB edge
clkB
S1
S2
dA dA1 S1 dB1
dB1
clkA
dB2
dB2
Move point of
divergence after
synchronizer
CORRECT
S 1 settled to new value … causing delayed dB2
clkB
S 2 settled to old value...
clkA clkA
dA2
dA2 Tprop2
dA1 S1
Tprop1
dB1
clkB clkB
dB
dB1 S1
dB2 S2
dB2
dA2 S2
Tprop2 dB dB1
dB2
dB
clkA clkB
dA 2 missed first clkB edge
CDC Freq of Source Freq of Destination Num of Flops in Technology Flop MTBF
Name Clock Domain Clock Domain Synchronizer
(MHz) (MHz)
<reg_bit status="show">
<bit_position>3</bit_position>
aclk <bit_type action="int_sync">R/W</bit_type>
<bit_name>ECC_I3</bit_name>
XCBI <bit_attribute type="int_edge">changing</bit_attribute>
<bit_attribute type="clk">aclk</bit_attribute>
<bit_default>0x00</bit_default>
</reg_bit>
Conclusion: All CDC warnings/errors should be carefully examined! CDC results may need
cross auditing.
adat
INCORRECT
core_clk aclk adat
pmc_sync_flop
missed edge
aclk
pmc_sync_flop
xcbi_attri_tip pmc_sync_flop pmc_sync_flop pmc_sync_flop _sample
_sample _retime[0] _retime[1]
input_tip input_tip_d
pmc_sync_flop
_retime[0]
CORRECT
pmc_sync_flop
core_clk aclk
_retime[1]
pmc_sync_flop
Conclusion: A good practice is to always register signals from the TX domain before passing
into the RX domain.
© 2016 Microsemi Corporation. Company Proprietary Power Matters.TM 36
Outline
Synchronization Techniques
• Single-bit CDC solutions
• Multi-bit CDC solutions
– CDC handshake protocols
• Reset synchronizer
Errors in Synchronization
• Common synchronization errors
• CDC errors seen in our silicon
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