The way we will discuss this concept in the following manner

1. What is Setup and Hold time?

2. Definition of Setup and Hold.
3. Setup and Hold Violation.
4. How to calculate the Setup and Hold violation in a design?

I saw that lots of people are confused with respect to this concept. And the reason of this are

1. They know the definition but don't know the origin or say concept behind Setup and
Hold timing.
2. They know the formula for calculating setup and hold violation but don't know how
this formula come in picture.
3. They become confuse by few of the terminology like capture path delay, launch path
delay, previous clock cycle, current clock cycle, data path delay, slew, setup slew,
hold slew, min and max concept, slowest path and fastest path, min and max corner,
best and worst case etc during the explanation of Setup and Hold Timings/Violation.

I hope I can clarify your confusion. Let me explain this and if you face any problem let me
know.

What is Setup and Hold time?

To understand the origin of the Setup and Hold time concepts first understand it with respect
to a System as shown in the fig. An Input DIN and external clock CLK are buffered and
passes through combinational logic before they reach a synchronous input and a clock input
of a D flipflop (positive edge triggered). Now to capture the data correctly at D flip flop, data
should be present at the time of positive edge of clock signal at the C pin ( to know the detail
just read basis of D flipflop).
Note: here we are assuming D flip flop is ideal so Zero hold and setup time for this.

There may be only 2 condition.

 Tpd DIN > Tpd Clk
o For capture the data at the same time when Clock signal (positive clock
edge) reaches at pin C, you have to apply the input Data at pin DIN
"Ts(in)=(Tpd DIN) - (Tpd Clk)" time before the positive clock edge at pin CLK.
o In other word, at DIN pin, Data should be stable "Ts(in)" time before the
positive clock edge at CLK pin.
o This Time "Ts(in)" is know as Setup time of the System.
Tpd DIN < Tpd Clk
o For capture the data at the same time when clock signal (positive clock edge)
reaches at pin C, input Data at pin DIN should not change before "Th(in)=
(Tpd Clk) - (Tpd DIN)" time. If it will change, positive clock edge at pin C will
capture the next data.
o In other word, at DIN pin, Data should be stable "Th(in)" time after the
positive clock edge at CLK pin.
o This time "Th(in)" is know as Hold Time of the System.

From the above condition it looks like that both the condition can't exist at the same time and
you are right. But we have to consider few more things in this.

Worst case and best case (Max delay and min delay)
o Because of environment condition or because of PVT, we can do this
analysis for the worst case ( max delay) and best case ( min delay) also.
Shortest Path or Longest path ( Min Delay and Max delay)
o If combinational logic has multiple paths, the we have to do this analysis for
the shortest path ( min delay) and longest path ( max delay) also.

So we can say that above condition can be like this.

Tpd DIN (max) > Tpd Clk (min)

o SetUp time == Tpd DIN (max) - Tpd Clk (min)
Tpd DIN (min) < Tpd Clk (max)
o Hold time == Tpd Clk (max) - Tpd DIN (min)

For example for combinational logic delays are

Data path (max, min) = (5ns, 4 ns)
Clock path (max, min) = (4.5ns, 4.1ns)
Then Setup time= 5-4.1=0.9ns
Hold time is = 4.5-4=0.5ns

Now similar type of explanation we can give for a D flip flop. There is a combinational logic
between C and Q , between D and Q of the Flipflop. There are different delays in those
conbinational logic and based on there max and min value , a flipflop has Setup and Hold
time. One circuitry of the positive edge triggered D flip is shown below.
There are different ways for making the D flip flop. Like by JK flipflop, master slave flipflop,
Using 2 D type latches etc. Since the internal circuitry is different for each type of Flipflop, the
Setup and Hold time is different for every Flipflop.

Definition:
Setup Time:

Setup time is the minimum amount of time the data signal should be held steady
before the clock event so that the data are reliably sampled by the clock. This applies
to synchronous circuits such as the flip-flop.
Or In short I can say that the amount of time the Synchronous input (D) must be
stable before the active edge of the Clock.
The Time when input data is available and stable before the clock pulse is applied is
called Setup time.

Hold time:

Hold time is the minimum amount of time the data signal should be held steady after
the clock event so that the data are reliably sampled. This applies to synchronous
circuits such as the flip-flop.
Or in short I can say that the amount of time the synchronous input (D) must be
stable after the active edge of clock.
The Time after clock pulse where data input is held stable is called hold time.

Setup and Hold Violation:

In simple language-
If Setup time is Ts for a flip-flop and if data is not stable before Ts time from active edge of the
clock, there is a Setup violation at that flipflop. So if data is changing in the non-shaded area (
in the above figure) before active clock edge, then it's a Setup violation.
And If hold time is Th for a flip flop and if data is not stable after Th time from active edge of
the clock , there is a hold violation at that flipflop. So if data is changing in the non-shaded
area ( in the above figure) after active clock edge, then it's a Hold violation.

Here we will discuss how to calculate the Setup and Hold Violation for a design.

Till now we have discussed setup and hold violation with respect to the single flipflop, now
lets extend this to 2 flip flop. In the following fig there are 2 flipflops (FF1 and FF2).
Few important things to note down here-

Data is launching from FF1/D to FF1/Q at the positive clock edge at FF1/C.
At FF2/D , input data is coming from FF1/Q through a combinational logic.
Data is capturing at FF2/D, at the positive clock edge at FF2/C.
So I can say that Launching Flip-Flop is FF1 and Capturing Flip-Flop is FF2.
So Data path is FF1/C --> FF1/Q --> FF2/D
For a single cycle circuit- Signal has to be propagate through Data path in one clock
cycle. Means if data is launched at time=0ns from FF1 then it should be captured
at time=10ns by FF2.

So for Setup analysis at FF2, Data should be stable "Ts" time before the positive edge at
FF2/C. Where "Ts" is the Setup time of FF2.

If Ts=0ns, then , data launched from FF1 at time=0ns should arrive at D of FF2
before or at time=10ns. If data takes too long ( greater then 10ns) to arrive (means it
is not stable before clock edge at FF2) , it is reported as Setup Violation.
If Ts=1ns, then, data launched from FF1 at time=0ns should arrive at D of FF2 before
or at time=(10ns-1ns)=9ns. If data takes too long (greater then 9ns) to arrive (means
it is not stable before 1ns of clock edge at FF2), it is reported as Setup Violation.

For Hold Analysis at FF2, Data should be stable "Th" time after the positive edge at FF2/C.
Where "Th" is the Hold time of FF2. Means there should not be any change in the Input data
at FF2/D between positive edge of clock at FF2 at Time=10ns and Time=10ns+Th.

To satisfy the Hold Condition at FF2 for the Data launched by FF1 at 0ns, the data
launched by FF1 at 10ns should not reach at FF2/D before 10ns+Th time.
If Th=0.5ns, then we can say that the data launched from FF1 at time 10ns does not
get propagated so soon that it reaches at FF2 before time (10+0.5)=10.5ns ( Or say it
should reach from FF1 to FF2 with in 0.5ns). If data arrive so soon (means with in
0.5ns from FF1 to FF2, data can't be stable at FF2 for time=0.5ns after the clock
edge at FF2), its reported Hold violation.
With the above explanation I can say 2 important points:

1. Setup is checked at next clock edge.

2. Hold is checked at same clock edge.

Setup Check timing can be more clear for the above Flip-flop combination with the help of
following explanation.

In the above fig you can see that the data launched by FF1/D ( at launch edge) reaches at
FF2/D after a specific delay ( CLK-to-Q delay + Conminational Logic Delay) well before the
setup time requirement of Flip-Flop FF2, so there is no setup violation.
From the Fig its clear that if Slack= Required Time - Arrival time < 0 (-ive) , then there is a
Setup violation at FF2.

Hold Check timing can be more clear with the help of following circuit and explanation.

In the above fig you can see that there is a delay in the CLK and CLKB because of the delay
introduced by the series of buffer in the clock path. Now Flip-flop FF2 has a hold requirement
and as per that data should be constant after the capture edge of CLKB at Flip-flop FF2.
You can see that desired data which suppose to capture by CLKB at FF2.D should be at Zero
(0) logic state and be constant long enough after the CLKB capture edge to meet hold
requirement but because of very short logic delay between FF1/Q and FF1/D, the change in
the FF1/Q propagates very soon. As a result of that there occurs a Hold violation.
This type of violation (Hold Violation) can be fixed by shortening the delay in the clock line or
by increasing the delay in the data path.
Setup and Hold violation calculation for the single clock cycle path is very easy to understand.
But the complexity increases in case of multi-cycle path ,Gated clock, Flip-flop using different
clocks, Latches in place of Flip-Flop. We will discuss all these later sometime.

Till now we have discussed a lot of theory about setup and hold time (with and without
Example). Now its time to discuss the practical implementation of that. Means in a circuit

How will you calculate the setup and hold values?

How will you analyse setup and hold violation in a circuit?
If you have to improve timing of a circuit then what can you do?

There are few formulas to calculate different parameter ( Theory of those I already explained
in my previous blogs). I am not going to explain those right now. First we will solve few
examples which will give you an basic idea about these formulas, then in the last I will
summarize all those in one place.

I saw a lot of confusion with respect to setup and hold timing calculation. Actually there are
two things.

Timing Specification of a Block/Circuit/Library:

o You have a block with input A and output Y. Some combinational logic is
there between A and Y. Now you have to calculate following parameters for
that block

Setup Time Value at input A

Hold Time value at input A.

Maximum operating Clock Frequency or Time Period for that block.

Clock To Y delay value

Input A to Output Y delay value.
Timing Violation of a circuit:
o You have to operate a circuit at a particular clock frequency and now you
have to find out whether this circuit has any setup or Hold Violation.

So in second case all the parameters are given and you have to find out whether this circuit
has any violation or not and In first case you have to find out all the parameters keeping in
mind that there should not be any violation.
Lets Discuss in the reverse order.
**********************************************************************************
**********************************************************************************

Problem1: In the following Circuit, Find out whether there is any Setup Or Hold
Violation?
Solution:
Hold Analysis:
When a hold check is performed, we have to consider two things-

Minimum Delay along the data path.

Maximum Delay along the clock path.

If the difference between the data path and the clock path is negative, then a timing violation
has occurred. ( Note: there are few Exceptions for this- We will discuss that some other time)

Data path is: CLK->FF1/CLK ->FF1/Q ->Inverter ->FF2/D

Delay in Data path

= min(wire delay to the clock input of FF1) + min(Clk-to-Q delay of FF1) +min(cell delay of
inverter) + min(2 wire delay- "Qof FF1-to-inverter" and "inverter-to-D of FF2")
=Td = 1+9+6+(1+1)=18ns

Clock path is: CLK-> buffer -> FF2/CLK

Clock path Delay

= max(wire delay from CLK to Buffer input) + max(cell delay of Buffer) + max(wire delay from
Buffer output to FF2/CLK pin) + (hold time of FF2)
=Tclk = 3+9+3+2 = 17 ns

Hold Slack = Td - Tclk = 18ns -17ns = 1ns

Since Hold Slack is positive-> No hold Violation.

Note: If the hold time had been 4 ns instead of 2 ns, then there would have been a hold
violation.
Td=18ns and Tclk = 3+9+3+4=19ns
So Hold Slack=Td - Tclk = 18ns - 19ns = -1ns (Violation)

Setup Analysis:
When a setup check is performed, we have to consider two things-

Maximum Delay along the data path.

Minimum Delay along the clock path.

If the difference between the clock path and the data path is negative, then a timing violation
has occurred. ( Note: there are few Exceptions for this- We will discuss that some other time)

Data path is: CLK->FF1/CLK ->FF1/Q ->Inverter ->FF2/D

Delay in Data path

= max(wire delay to the clock input of FF1) + max(Clk-to-Q delay of FF1) +max(cell delay of
inverter) + max(2 wire delay- "Qof FF1-to-inverter" and "inverter-to-D of FF2")
=Td = 2+11+9+(2+2) = 26ns

Note: The first part of the clock path delay (during setup calculation) is the clock period, which
has been set to 15 ns. Hope You remember in last blog, I have mentioned very clearly that
Setup is checked at the next clock cycle. That's the reason for clock path delay we have to
include clock period also.

Clock path is: CLK-> buffer -> FF2/CLK

Clock path Delay

= (Clock period) + min(wire delay from CLK to Buffer input) + min(cell delay of Buffer) +
min(wire delay from Buffer output to FF2/CLK pin) - (Setup time of FF2)
=Tclk = 15+2+5+2-4=20ns

Setup Slack = Tclk - Td = 20ns - 26ns = -6ns.

Since Setup Slack is negative -> Setup violation.

Note: A bigger clock period or a less maximum delay of the inverter solve this setup
violations in the circuit.
E.g
If Clock period is 22ns then
Tclk = 22+2+5+2-4=31-4=27ns AND Td = 26ns
Setup Slack = Tclk - Td = 27-26=1ns (No Violation)

**********************************************************************************
**********************************************************************************

Problem2: In order to work correctly, what should be the Setup and Hold time at Input
A in the following Circuit. Also find out the maximum operating frequency for this
circuit. (Note: Ignore Wire delay). Where Tsu- Setup time; Thd-Hold Time; Tc2q- Clock-
to-Q delay

Solution:
Step1: Find out the maximum Register to register Delay.

Max Register to Register Delay

= (clk-to-Q delay of U2) + (cell delay of U3) + (all wire delay) + (setup time of U1)
= 5 + 8 + 3 = 16 ns.

Note:

There are 2 register to register paths

o U2 -> U3 ->U1 (Delay=5+8+3=16ns)
 o U1 -> U4 -> U2 ( Delay=5+7+3=15ns)
We have to pick maximum one.

Step2: Find Out Setup Time:

A setup time = Setup time of Flipflop + Max (Data path Delay) - min(Clock path Delay)
= (Setup time of Flipflop + A2D max delay) - (Clk path min delay)
= Tsu + (Tpd U7 + Tpd U3 + wire delay) - Tpd U8
= 3 + (1+8 ) - 2 = 10 ns

Note:

Here we are not using the Clock period. Because we are not suppose to calculate the
Setup violation. We are calculating Setup time. Please refer the part3a for the
referance.
All the wire dealy is neglected. If Wire delay present, we have to consider those one.
There are 2 Data path
o A -> U7 -> U4 -> D of U2 (Data path Delay = 1+7 =8ns )
o A -> U7 -> U3 -> D of U1 ( Data path Delay = 1+8 =9ns )
Since for Setup calculation we need maximum Data path delay, we have choosen
2nd for our calculation.

Step3: Find Out Hold Time:

A hold time = Hold time of Flipflop + max(Clock path Delay) - min( Data path delay)
=( Hold time of Flipflop + Clk path max delay) - (A2D max delay)
= Thd + Tpd U8 - (Tpd U7 + Tpd U4+wire delay)
= 4 + 2 - (1+7 ) = -2 ns

Note: Same explanation as for Setup time. For hold time we need minimum data path , so we
have picked first Data path.

Step4: Find out Clock to Out Time:

Clock to Out
= Cell delay of U8 + Clk-to-Q delay of FlipFlop+ Cell delay of U5+ Cell delay of U6+ (all wire
delay)
= Tpd U8+ U2 Tc2q + U5 Tpd + U6 Tpd
= 2 + 5 + 9 + 6 = 22 ns

Note:

There are 2 Clock to Out path- one from Flip flop U1 and other from U2.
Since in this case the Clk-to-Q path for both Flipflop is same, we can consider any
path. But in some other Circuit where the delay is different for both the paths, we
should consider Max delay path.

Step5: Find Pin to Pine Combinational Delay (A to Y delay)

Pin to Pin Combinational Delay (A to Y)

= U7 Tpd + U5 Tpd + U6 Tpd
= 1 + 9 + 6 = 16 ns

Step5: Find Out Max Clock Frequency:

Max Clock Freq = 1/ Max (Reg2reg, Clk2Out, Pin2Pin)

= 1/ Max (16, 22, 16)
= 45.5 Mhz
So summery is:

Parameter Description Min Max Units

Tclk Clock Period 22 ns
Fclk Clock 45.5 Mhz
Frequency
Atsu A setup time 10 ns
Athd A hold time -2 ns
A2Y A to Y Tpd 16 ns
Ck2Y Clock to Y tpd 22 ns
Note: Negative hold times are typically specified as 0 ns.

**********************************************************************************
**********************************************************************************

Problem3: In the above Circuit, Try to improve the timing by adding any "buffer" or
"Register".

Solution:
Best way of doing this is Register all Input and Output. We are adding DFF so same
specification (as U2 and U1).

Now follow all those 5 Steps onn by one.

Step1:

Max Register to Register Delay

U2 Tc2q + U5 Tpd + U9 Tsu = 5 + 9 + 3 = 17 ns

Note:

A lot of Register to Register path

o U8 -> U5 -> U9 (Delay = 5+9+3=17ns)
 o U8 -> U4 -> U2 (Delay = 5+7+3=15ns)
o U8 -> U3 -> U1 (Delay = 5+8+3=16ns)
o U1 -> U4 -> U2 (Delay= 5+7+3=15ns)
o U1 -> U5 -> U9 (Delay= 5+9+3=17ns)
o U2 -> U5 -> U9 (Delay = 5+9+3=17ns)
o U2 -> U3 -> U1 (Delay = 5+8+3=16ns)
Maximum delay is 17ns, Just picked anyone.

Step2:
A setup time = Tsu + A2D Tpd max - Clk Tpd min
= Tsu + (Tpd U7) - Tpd U8
= 3 + (1) - 2 = 2 ns

Note: Only One path between A and D of FF(i.e U8)

Step3:
A hold time = Thd + Clk Tpd max - A2D Tpd min
= Thd + Tpd U8 - (Tpd U7)
= 4 + 2 - ( 1) = 5 ns

Note: Only One path between A and D of FF(i.e U8)

Step4:
Clock to out:
=Tpd U8+ U9 Tc2q + U6 Tpd
=2+5+6 = 13 ns

Step5:
No direct link between A and Y. So Not Applicable.

Step6:
Max Clock Freq = 1/ Max (Reg2reg, Clk2Out, Pin2Pin)
= 1/ Max (17, 13)
=58.8 Mhz

Parameter Description Min Max Units

Tclk Clock Period 17 ns
Fclk Clock 58.8 Mhz
Frequency
Atsu A setup time 2 ns
Athd A hold time 5 ns
Ck2Y Clock to Y tpd 13 ns

**********************************************************************************
**********************************************************************************

I hope This much will help you. Now its the time to summarize all the important things
and formulas.

Points to remember:

1. Setup is checked at next clock edge.

2. Hold is checked at same clock edge.
3. For Hold Check ( Checking of hold Violation)
o Minimum Delay along the data path.
o Maximum Delay along the clock path.
 4. For SetUp Check ( Checking of Setup Violation)
1. Maximum Delay along the data path.
2. Minimum Delay along the clock path.

Calculation of Setup Violation Check: Consider above circuit of 2 FF connected to each

other.

Setup Slack = Required time - Arrival time (since we want data to arrive before it is
required)

Where:
Arrival time (max) = clock delay FF1 (max) +clock-to-Q delay FF1 (max) + comb.
Delay( max)
Required time = clock adjust + clock delay FF2 (min) - set up time FF2
Clock adjust = clock period (since setup is analyzed at next edge)

Calculation of Hold Violation Check: Consider above circuit of 2 FF connected to each

other.

Hold Slack = Arrival Time - Required time (since we want data to arrive after it is
required)

Where:
Arrival time (min) = clock delay FF1 (min) +clock-to-Q delay FF1 (min) + comb. Delay(
min)
Required time = clock adjust + clock delay FF2 (max) + hold time FF2
Clock adjust = 0 (since hold is analyzed at same edge)

Calculation of Maximum Clock Frequency:

Max Clock Freq = 1/ Max (Reg2reg delay, Clk2Out delay, Pin2Pin delay)

Where:
Reg2Reg Delay = Clk-to-Q delay of first FF (max) + conb delay (max) + setup time of
2nd FF.
Clk2Out Delay = Clock delay w.r.t FF (max) + clock-to-Q delay of FF1 (max) + comb.
delay (max)
Pin2Pin delay = Comb delay between input pin to output pin (max)