DesignWare IP Portfolio

Broad IP Portfolio
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare® IP portfolio includes logic
libraries, embedded memories, embedded test, analog IP, interface IP, security IP, embedded processors and subsystems.

To accelerate your product development cycle, Synopsys’ IP Accelerated initiative offers SoC architecture design support, IP subsystems,
signal integrity/power integrity analysis and IP hardening, IP prototyping kits, and comprehensive silicon bring-up support.

Synopsys’ extensive investment in IP quality, comprehensive technical support and robust IP development methodology enable designers to
reduce integration risk and accelerate time-to-market.

Interface IP

Process Technologies
Controllers/
USB Features
Verification IP
65 55 40/45 28 22 20 14/16nm 12nm 10nm 7nm
nm nm nm nm nm nm FinFET FinFET FinFET FinFET

USB 3.2 ü Device ü

Dual-Role Device
USB 3.1 ü ü ü ü
(Device & Host)
Dual-Role Device
USB-C 3.1 ü ü ü ü
(Device & Host)
Device, Host,
USB-C 3.1/ DisplayPort Tx,
DisplayPort 1.4
ü ü ü ü Subsystem
ü
Solution for 16FFC
Dual-Role Device
USB-C 3.1/
ü ü ü ü (Device & Host), ü
DisplayPort 1.3
DisplayPort Tx
Dual-Role Device,
USB 3.0 ü ü ü ü ü ü ü ü ü
Device, Host, HSIC

USB-C 3.0 ü ü ü ü Device, Host ü

Device, Host,
USB 2.0 ü ü ü ü ü ü ü ü ü ü HSIC, ü
Dual-Role Device
Device, Host,
USB-C 2.0 ü ü ü ü ü ü ü ü ü ü ü
Dual-Role Device
Device, Host,
eUSB2 ü ü
Dual-Role Device

HSIC ü ü ü ü ü Device, Host ü

Process Technologies
PCI Verification
40/ 14/ Controllers Configuration
Express 65 55 45 28 22 20 16nm 12nm 10nm 7nm IP
nm nm nm nm nm FinFET FinFET FinFET
nm FinFET

Endpoint, Root Port,

x1, x2, x4, x8,
PCIe 5.0 ü ü ü Dual Mode, Switch, ü
x16
Embedded Endpoint
Endpoint, Root Port,
x1, x2, x4, x8,
PCIe 4.0 ü ü ü ü Dual Mode, Switch, ü
x16
Embedded Endpoint
Endpoint, Root Port,
x1, x2, x4, x8,
PCIe 3.1 ü ü ü ü ü ü Dual Mode, Switch, ü
x16
Embedded Endpoint
Endpoint, Root Port,
x1, x2, x4, x8,
PCIe 2.1 ü ü ü ü ü ü ü ü ü Dual Mode, Switch, ü
x16
Embedded Endpoint

Endpoint, Root Port,

x1, x2, x4, x8,
PCIe 1.1 ü ü ü ü ü ü Dual Mode, Switch, ü
x16
Embedded Endpoint

synopsys.com/designware  2 Q3 2019
 Interface IP

Process Technologies
CCIX Controllers Verification IP
65 55 40/45 28 20 14/16nm 12nm 10nm 7nm
nm nm nm nm nm FinFET FinFET FinFET FinFET

Endpoint, Root
CCIX 1.0 ü ü ü Port, Dual Mode, ü
Switch

Process Technologies
HDMI Controllers Verification IP
65 55 40/45 28 14/16nm 12nm 10nm 7nm
nm nm nm nm FinFET FinFET FinFET FinFET

HDMI 2.1 ü ü ü ü
HDMI 2.0 ü ü ü ü ü ü
HDMI 1.4 ü ü ü ü ü ü

Process Technologies Platform

Verifica-
DDR Controllers Architect
tion IP
65 55 40/45 28 20 14/16nm 12nm 10nm 7nm
nm nm nm nm nm FinFET FinFET FinFET FinFET Support

LPDDR5 ü ü ü ü
Protocol
controller,
LPDDR4 ü ü ü ü ü ü ü
Memory
controller
Protocol
controller,
LPDDR4X ü ü ü ü ü
Memory
controller
Protocol
controller,
LPDDR3 ü ü ü ü ü ü ü
Memory
controller
Protocol
controller,
LPDDR2 ü ü ü ü ü ü
Memory
controller
DDR5 ü ü ü
Protocol
controller,
DDR4 ü ü ü ü ü ü ü ü
Memory
controller
Protocol
controller,
DDR3 ü ü ü ü ü ü ü ü ü
Memory
controller
Protocol
controller,
DDR2 ü ü ü ü ü ü
Memory
controller

Process Technologies
HBM Controllers Verification IP
65 55 40/45 28 20 14/16nm 12nm 10nm 7nm
nm nm nm nm nm FinFET FinFET FinFET FinFET

HBM2 ü ü ü

synopsys.com/designware  3 Q3 2019
 Interface IP

Process Technologies
Verification
MIPI Controllers
IP
40/45 28 22 20 14/16nm 12nm 10nm 7nm
nm nm nm nm FinFET FinFET FinFET FinFET

D-PHY ü ü ü ü ü ü ü CSI-2, DSI ü

M-PHY ü ü ü ü ü UFS, UniPro ü
CSI-2 Host, Device ü
DSI Host, Device ü
DSI + DSC
DSI + DSC ü
Encoder
UniPro v1.6, v1.8 ü
Master,
I3C ü
Slave, Slave Lite

Process Technologies
Verification
Ethernet PCS Controllers
IP
14/16nm
28nm 7nm FinFET
FinFET

56G Ethernet (100G/200G/400G) ü ü ü

RXAUI/Double XAUI (6.25 G) ü ü ü ü ü ü
1000BASE-KX, Energy Efficient Ethernet, 10GBASE-KR,
10GBASE-KX4
ü ü ü ü ü ü

40GBASE-KR4, 40GBASE-CR4, XLAUI ü ü ü ü ü ü

100GBASE-CR10, CAUI ü ü ü ü ü ü

SGMII ü ü ü ü ü ü
QSGMII ü ü ü ü ü ü
XFI, SFI (SFF-8431) ü ü ü ü ü ü
GMII/MII, RGMII, RTBI, TBI, SMII, RMII, RevMII, XGMII,
XLGMII
ü ü ü

IEEE TSN/AVB Standards: IEEE 802.1AS, 802.1AS-Rev,

802.1Qav, 802.1Qat, 802.1Qbv, 802.1Qbu & 802.3br
ü ü

25G/50G Ethernet Consortium and IEEE specifications ü ü ü ü ü

2.5G/5.0G USXGMII ü ü ü ü ü
Additional Enterprise Protocols
OIF, CEI-6G/11G ü ü ü
CPRI, OBSI, JESD204 A/B ü ü ü ü
SRIO ü ü ü

Process Technologies
Verification
SATA Controllers
IP
14/16nm 7nm
65nm 55nm 40/45nm 28nm FinFET FinFET

SATA 6G ü ü ü ü ü ü Host, Device ü

SATA 3G ü ü ü ü ü ü Host, Device ü

Process Technologies
Bluetooth, Thread, Zigbee Controller (Link Layer / Mac)
180nm 55nm 40nm 22nm

Bluetooth 5.1 ü ü ü
IEEE 802.15.4 (Thread, Zigbee) ü ü ü
Combo Bluetooth IEEE 802.15.4 ü ü ü

synopsys.com/designware  4 Q3 2019
 Interface IP

Process Technologies
Mobile Storage Controllers Verification IP
14/16nm 12nm 10nm 7nm
28nm 22nm FinFET FinFET FinFET FinFET

UFS ü ü
UniPro ü ü
M-PHY ü ü ü ü ü ü ü
eMMC ü ü ü ü ü ü
SD ü ü ü ü ü ü
SDIO ü ü ü ü ü ü

AMBA Synthesizable IP Verification IP

AXI 3 and AXI 4 bus fabric,

bridges, and infrastructure IP
ü ü

AHB and AXI DMA controllers ü ü

AMBA peripherals (SSI for SPI/
xSPI bus, I2C, I2S, UART)
ü ü

Timers, interrupt controllers,

GPIOs, interconnect matrices
ü ü

Datapath IP Synthesizable IP Simulation Models (C++, Verilog) Verification Models

Floating point functions ü ü ü

Fixed point functions ü ü ü
Trigonometric functions ü ü ü

Analog IP

Process Technologies Channel

Data
Bits MSPS Configura-
Converters 180nm 130nm 90nm 65nm 55nm 40nm 28nm 22nm 12/16nm
tion
FinFET

>1000 MSPS ADCs 12 3000 Single, Dual

300-1000 MSPS
ü ü ü ü 12 320 Single, Dual
ADCs
150-300 MSPS 160 to
ü ü ü ü 10, 12 Single, Dual
ADCs 250
10-150 MSPS 80 to
ü ü ü ü ü 10, 12 Single, Dual
ADCs 125
<10 MSPS ADCs ü ü ü ü ü ü ü ü 10, 12, 14 1 to 5 Single
>1000 MSPS DACs 12 3000 Single, Dual
300-1000 MSPS 320 to
ü ü ü ü 10, 12 Single, Dual
DACs 640
100-300 MSPS Single, Dual,
ü ü ü 10, 12 160, 300
DACs 1 to 6 (VDAC)
<100 MSPS DACs ü ü ü ü ü 11, 12 20 Single

synopsys.com/designware  5 Q3 2019
 Memories and Logic Libraries

Process Technologies
Embedded Memories
14/16nm 12nm 7nm
65nm 55nm 40/45nm 28nm 22nm FinFET FinFET FinFET

Ternary Content-addressable
Memory (TCAM)
ü

High-Density Single Port SRAM,

High-Density Dual Port SRAM
ü ü ü ü ü ü ü ü

High-Density 1P RF,
High-Density 2P RF
ü ü ü ü ü ü ü ü

High-Density ROM ü ü ü ü ü ü ü ü
High-Speed Single Port SRAM ü ü ü ü ü ü ü ü
High-Speed Dual Port SRAM ü ü ü ü ü ü ü
High-Speed 1P RF (Cache) ü ü ü ü ü ü ü ü
High-Speed Asynchronous
2-Port Register File
ü ü ü

UHD 1P RF ü
UHD 2P RF ü ü ü ü ü ü ü
UHD 2P SRAM ü ü ü
STAR Memory System Embedded
Test and Repair
ü ü ü ü ü ü ü ü

STAR Hierarchical System ü ü ü ü ü ü ü ü

Process Technologies
Logic Libraries
14/16nm 12nm 7nm
65nm 55nm 40/45nm 28nm 22nm FinFET FinFET FinFET

High-Speed Library ü ü ü ü ü ü ü ü
High-Speed Multi-channel ü ü ü ü ü ü
High-Speed POK ü ü ü ü ü ü ü
High-Density Library ü ü ü ü ü ü ü
High-Density Multi-channel ü ü ü ü ü
High-Density POK ü ü ü ü ü ü ü
UHD Library, UHD POK ü ü ü ü ü ü ü ü
UHD Multi-channel ü ü ü ü ü ü
Ultra-low leakage (thick oxide) ü ü ü
High-Performance Core Design Kit ü ü ü ü ü ü
Enhanced Reliability Kit ü

Process Technologies Endurance

Non-Volatile Memory Bit Counts (Write
150/ 110/ 80/90 55/65 40 28 22 14/16nm 12
180nm 130nm nm nm nm nm nm FinFET nm Cycles)

16 bit to 1 1 per
One-Time Programmable (OTP) ü ü ü ü ü ü ü ü Mbit instance
Multi-Time Programmable (MTP) 16 bit to 512
180nm ü Up to 1,000
Medium-Density Kbit
128 bit to 8 Up to
MTP EEPROM 180nm ü ü Kbit 1,000,000
64 bit to 4 Up to
MTP ULP ü Kbit 100,000
64 bit to 4
Few-Time Programmable Trim ü ü Up to 1,000
Kbit

synopsys.com/designware  6 Q3 2019
 Security IP

Security Synthesizable IP Software

Cryptography IP ü ü
Security Protocol Accelerators ü ü
Hardware Secure Modules with Root of Trust ü ü
Content Protection IP ü ü

Accelerate Development of Performance-Efficient SoCs

Synopsys’ DesignWare ARC® Processors are a family of 32-bit CPUs that SoC designers can optimize for a wide range of uses, from deeply
embedded to high-performance host applications in a variety of market segments. Designers can differentiate their products by using
patented configuration technology to tailor each ARC processor instance to meet specific performance, power and area requirements.
The DesignWare ARC processors are also extendable, allowing designers to add their own custom instructions that dramatically increase
performance. Synopsys’ ARC processors have been used by over 230 customers worldwide who collectively ship more than 1.9 billion
ARC-based chips annually.

All DesignWare ARC processors utilize a 16-/32-bit ISA that provides excellent performance and code density for embedded and host SoC
applications. The RISC microprocessors are synthesizable and can be implemented in any foundry or process, and are supported by a
complete suite of development tools.

DesignWare ARC processors are supported by a broad ecosystem of commercial and open source tools, operating systems and
middleware. This includes offerings from leading industry vendors who are members of the ARC Access Program as well as a
comprehensive suite of free and open source software available through embARC.org.

Processor IP

Max Safety Enhanced

Cache Floating
ARC 32-bit Processors CCM
Size
DSP MPU Enhancement Security MMU
Point
Trace
Size Package Package

EM4 2MB ü ü ü ü ü
EM6 2MB 32K ü ü ü ü ü
EM5D 2MB ü ü ü ü ü ü
EM7D 2MB 32K ü ü ü ü ü ü
EM9D 2MB ü ü ü ü ü
EM11D 2MB 32K ü ü ü ü ü
EM4SI 2MB ü ü ü ü
EM5DSI 2MB ü ü ü ü ü
SEM110 2MB ü ü
SEM120D 2MB ü ü ü
605 LE 512KB ü
710D 512KB ü ü ü ü
725D 512KB 64K ü ü ü ü
770D 512KB 64K ü ü ü ü ü
610D 512KB ü ü ü ü
625D 512KB 32K ü ü ü ü
AS211SFX 512KB 32K ü ü ü ü
512KB 32K ea
AS221BD (dual-core) ü ü ü ü
ea core core

synopsys.com/designware  7 Q3 2019
 Processor IP

ARC HS Max CCM L1 Floating

Cache Size DSP L2 Cache MMU Trace
32-bit Processors Size Coherency Point

HS34, HS34x2, HS34x4 16MB ü ü

HS36, HS36x2, HS36x4 16MB 64K ü ü ü
HS38, HS38x2, HS38x4 16MB 64K ü 8MB ü ü ü
HS44, HS44x2, HS44x4 16MB ü ü
HS46, HS46x2, HS46x4 16MB 64K ü ü ü
HS48, HS48x2, HS48x4 16MB 64K ü 8MB ü ü ü
HS45D, HS45Dx2,
16MB ü ü ü
HS45Dx4
HS47D, HS47Dx2,
16MB 64K ü ü ü ü
HS47Dx4

CNN Vision 512-bit L1 Floating Vector Safety

Embedded Vision 32-bit
Engine CPU DMA Vector Cache Point Unit Floating Enhancement
Processors (MACs) MACs
Scalar
DSP Coherency (FPU) Point Unit Package
880, 1,760
EV61 64 ü 1 1 ü ü ü
or 3,520
880, 1,760
EV62 128 ü 2 2 ü ü ü ü
or 3,520
880, 1,760
EV64 256 ü 4 4 ü ü ü ü
or 3,520

IP Accelerated Initiative
With IP Accelerated, Synopsys has augmented its broad portfolio of silicon-proven DesignWare IP with SoC architecture design support, IP
subsystems, signal integrity/power integrity analysis and IP hardening, IP prototyping kits, and comprehensive silicon bring-up support to
accelerate your product development cycle.

IP Subsystems

ARC Processor Supported Hardware Integrated

Included Software
IP Subsystems ARC Processors Accelerators Peripherals

DSP library, audio

SPI, I2C, I2S, I3C, UART,
EM5D, EM7D, EM9D, processing library,
Data Fusion IP Subsystem ü PDM, ADC I/F, APB I/F,
EM11D peripheral I/O drivers (bare
GPIO
metal), reference designs
DSP library, motor control
SPI, I2C, PWM, UART, ADC library, peripheral I/O
Sensor and Control IP Subsystem EM4, EM6 ü I/F, DAC I/F, APB I/F, GPIO drivers (bare metal),
reference designs
Multi-core media
I2S, S/PDIF, analog
framework, MM MQX
SoundWave Audio Subsystem AS211SFX, AS221BD ü codec I/F, reset, clock
audio post-processing
management
software

Multi-Protocol
Interface IP Subsystems Supported IP
Support
Integrated Logic Included Scripts

USB, PCIe, DDR, Ethernet, AMBA or native bus, clock Configuration scripts, test
HDMI, MIPI, AMBA, management, reset, DMA, environment, test scripts,
IP Protocol-Specific Subsystems Security, MACsec, IPsec, ü interrupts, memory, power linting, CDC checks, RDC
PCIe switch, Ethernet management, debug and checks, synthesis scripts,
switch test logic implementation scripts

synopsys.com/designware  8 Q3 2019
 Signal/Power Integrity Analysis & IP Hardening

Supported IP Multi-Protocol Support Consultation Expertise

On-chip decoupling capacitance, power and

ground pins, PHY & SDRAM termination strategy,
SoC package design, PCB stack-up and trace
DDR, LPDDR, PCIe, USB, MIPI, Ethernet, HDMI ü width/spacing, performance at required data rate,
read/write/address, command/control timing
budgets

IP Prototyping Kits and Software Development Kits

IP Prototyping Kit with ARC SDP IP Prototyping Kit with PCIe Connection to PC

Protocol/Standard Soft Deliverable Soft Deliverable

HAPS-80 HAPS-80

USB 3.1 Host ü

USB 3.1 Device ü
USB 3.0 Host ü
USB 3.0 Device ü
PCIe 3.1 Endpoint ü
PCIe 3.1 Root Complex ü
PCIe 2.1 Endpoint ü
PCIe 2.1 Root Complex ü
CCIX 1.0 ü
DDR 4/3 ü
LPDDR 4 ü
JEDEC UFS Host ü
MIPI CSI-2 Device ü
MIPI DSI Host ü

For more information on DesignWare IP, visit synopsys.com/designware.

©2019 Synopsys, Inc. All rights reserved. Synopsys is a trademark of Synopsys, Inc. in the United States and other countries. A list of Synopsys trademarks is
available at synopsys.com/copyright.html . All other names mentioned herein are trademarks or registered trademarks of their respective owners.
07/01/19.CS363366173-Q3 IP Brochure Updates.