Resume Deshdeepak
Resume Deshdeepak
Synopsis
VLSI Hardware Engineer with substantial experience of RTL verification for complex ASIC
products. Main areas include,
➢ Experience of development of coverage-driven constrained random test environments at IP,
subsystem and SOC level
➢ Experience in Verification planning, test planning and coverage closure
➢ Sound Understanding and experience in verifying various complex protocols such as ARM
architecture, DDR ,SATA and AMBA ACE ,based ASICs .
➢ Good knowledge of System Verilog (SV), UVM, based component, sequences, cover groups,
checkers.
Work Experience
August 2015 – April 2017: Mentor Graphics India Private Limited, Noida
Senior member of technical staff, Veloce Emulation Transactor Group.
Core Skills
Projects Experience
Description: NSP (Neural signal processor) subsystem is a subsystem made to accelerate server
on pretrained data .This subsystem was built around DSP processor and have capability to
communicate with complex NOC working on 4 QNS4 slave , 4 QNS4 slave ,1 AXI slave and 1 APB
slave .
➢ Understanding specification of all debug component (e.g DAP ,CTI ,TPIU, ETB and ETR ) in
each subsystem and preparing testplan and verification plan
➢ Writing self checking C based tests to verify Trigger network built on ARM Coresight Cross
trigger interface across on SOC
➢ Verifying ATB Trace ,QATB trace ,generic trace ,source to sink verification
➢ Worked on Debug and config access Port (DAP), Interrupts ,Trace ,trigger ,reset and clock
architecture feature verification.
Description: ACE, defined as part of the AMBA 4 specification, extends AXI with additional
signaling introducing system wide coherency. This transactor a behavioral model of ACE master
,was having in built software based cache memory and hardware synthesizable ACE transactor .
Roles & Responsibilities
➢ Understanding Coherency and Cache memory concepts in ARM architecture.
➢ Defining and implementing verification plan and verification environment
architecture
➢ Generating AXI transaction and snoop transaction based test cases ,causing change
in cache states ,coherency .
➢ Developing UVM based self-checking environment for this transactor.
➢ Generate various IP level and system level test suite
➢ Provide customer support for various issues/features
Description: SATA Host Controller Adapter is 1st generation SATA controller which works on 1.5
Gbit/s-150 MB/s .The SATA host adapter supports an Configuration bus and DMA Interface on
CPU side, while a single SATA port on device side. SATA port can plug third party PHY layer and
can be connected via this PHY to the SATA device (optical disk or drive).
Education
Personal Details
Declaration
I hereby declare that all the information furnished above is true to the best of my knowledge
and belief.
Deshdeepak Nautiyal