Class 12 Topics

What is an assertion?
SystemVerilog assertions
Immediate assertions
Concurrent assertions
Collecting functional coverage with assertions
Properties
Sequences

Class 12 Copyright 2009 Greg Tumbush

What is an assertion?

An assertion specifies a behavior of the system.

Assertions can be used for:
Verifying the behavior of a design
Means for functional coverage
Provide input stimulus for verification
Assertions can be written in:
Verilog
SVA SystemVerilog Assertions
PSL Property Specification Language
Does your current project use assertion languages or assertion
libraries? (Yes/No) If yes, which one(s) are you using?
don't use :
31.5%
IBM Sugar/PSL :
14.9%
0-In CheckerWare : 6.8%
System Verilog SVA : 37.8%
Synopsys Vera OVA : 9.6%
Verplex OVL/IAL : 9.3%
VHDL Assertions : 7.0%
homegrown :
8.2% Class 12 Copyright 2009 Greg Tumbush

Where can SVA be used?

SystemVerilog
Verilog 2001
Even VHDL
In RTL
In a testbench
For the testbench
For the RTL

testbench
assertions
assertions
RTL

assertions

Class 12 Copyright 2009 Greg Tumbush

SVA in a Verification Strategy

Provide added white box visibility to the design
Application
Assertions

Interface
Assertions

Structural
Assertions

Arbiter
PCI Bus

FIFO
Processor

FSM

AHB Bus

Useful for both the provider and user of IP

Provides quick feedback if a simulation has gone awry
Continuously running verification checkers in a task
based testbench.
Checkers that would be very difficult in Verilog.
Dr. Meeta Yadiv, ASIC Verification, North Carolina State University Fall 2007

Class 12 Copyright 2009 Greg Tumbush

SystemVerilog Assertions
An assertion written in SVA requires less extra syntax to learn if
your testbench is in SystemVerilog
2 types of assertions
Immediate -> Operates in procedural code
Concurrent -> Operates outside procedural code
Property to check: If request is 1 on the positive edge of the
clock grant must be 1 on the next positive edge of the clock.
always @(posedge clk) begin
if (request) begin
@(posedge clk);
if (grant != 1)
$display("%t: Error, grant != 1", $time);
end
end
Class 12 Copyright 2009 Greg Tumbush

Immediate Assertions
Immediate assertions operate in procedural code
Syntax:
<assertion name> : assert(expression)
<action if true>;
else
<action if false>;
always @(posedge clk) begin
if (request) begin
repeat (1) @(posedge clk);
reg_grnt_assert: assert (grant == 1)
$display("%t: Passed", $time);
else
$display("%t: Failed", $time);
end
end
Class 12 Copyright 2009 Greg Tumbush

Do these Immediate Assertions work?

always @(posedge clk) begin
if (request) begin
@(posedge clk);
if (grant != 1)
$display("%t: Error,.....
end
end

Always block entered

# 250: Error, grant != 1

# 450: Error, grant != 1

always @(posedge clk) begin

if (request) begin
repeat (1) @(posedge clk);
reg_grnt_assert: assert (grant == 1)
$display("%t: Passed", $time);
else
$display("%t: Failed", $time);
end
end

Always block entered

Class 12 Copyright 2009 Greg Tumbush

Immediate Assertions (cont.)

The <action if true> expression is optional
reg_grnt_assert: assert (grant == 1)
else
$display("%t: Failed", $time);

The <action if false> expression is optional

reg_grnt_assert: assert (grant == 1)
$display("%t: Passed", $time);
Do not need <action if false> or <action if true>

reg_grnt_assert: assert (grant == 1)

Class 12 Copyright 2009 Greg Tumbush

Immediate Assertion Severity

By default the severity of an assertion failure is error.

reg_grnt_assert: assert (grant == 1)

else
$error("Failed");
# ** Error: Failed
# Time: 250 ns Scope: test.reg_grnt_assert File: test.sv Line: 33
Other severities are $fatal, $warning or $info.
# ** Info: Failed
# Time: 250 ns Scope: test.reg_grnt_assert
File: test.sv Line: 33
Class 12 Copyright 2009 Greg Tumbush

Exercise 1
Design an immediate assertion that:
1. If the signal branch_inst = 1 on the negative edge of the clock, the
signal jump_done must = 1 two cycles later on the negative edge of
the clock.
2. If a failure occurs specify the severity to be a warning.
3. If a failure does not occur specify the severity to be an info.
4. Name the assertion branch_done

Class 12 Copyright 2009 Greg Tumbush

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Exercise 1
Design an immediate assertion that:
1.
If the signal branch_inst = 1 on the negative edge of the clock, the signal jump_done must = 1 two cycles later on the negative edge of the clock.
2.
If a failure occurs specify the severity to be a warning.
3.
If a failure does not occur specify the severity to be an info.
4.
Name the assertion branch_done

always @(negedge clk) begin

if (branch_inst) begin
repeat (2) @(negedge clk);
branch_done: assert (jump_done == 1)
$info("%t: jump_done = 1 two cycle after branch_inst", $time);
else
$warning("%t: jump_done not= 1 two cycle after branch_inst", $time);
end
end

Class 12 Copyright 2009 Greg Tumbush

11

Concurrent Assertions
Immediate assertions are no more powerful than coding in Verilog
Concurrent assertions can describe behavior that spans time.
Concurrent assertions evaluate on a defined edge.
Defined outside procedural code.
Syntax:
<assertion name> : assert property (expression)
<action if true>;
grant evaluated one cycle later
else
Overlapping: sampled on same cycle
<action if false>;
reg_grnt_assert: assert property (@(posedge clk) (request |-> ##1 grant))
$display("%t: Passed", $time);
else
$display("%t: Failed", $time);
Equivalent to reg_grnt_assert: assert property (@(posedge clk) (request |=> grant));
Class 12 Copyright 2009 Greg Tumbush

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Does this Concurrent Assertion work?

reg_grnt_assert: assert property (@(posedge clk) (request |-> ##1 grant))
$display("%t: Passed", $time);
else
$display("%t: Failed", $time);

Assertion inactive
Assertion begins

Class 12 Copyright 2009 Greg Tumbush

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disabling with disable iff

Continuous assertions can be turned off with disable iff

Typical usage is during reset.
reg_grnt_assert: assert property (@(posedge clk)
disable iff (reset) (request |-> ##1 grant));

Class 12 Copyright 2009 Greg Tumbush

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Exercise 2
Re-write the immediate assertion in exercise 1 so that:
1. It is a concurrent assertion
2. It is disabled if input testmode is asserted.
3. Remove the additional information on success or failure.
branch_done: assert property (@(negedge clk) disable iff (testmode) (branch_inst |-> ##2 jump_done));

Class 12 Copyright 2009 Greg Tumbush

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$rose and $fell

reg_grnt: assert property (@(posedge clk) (request -> ##1 grant));

$rose detects a transition to 1

$fell detects a transition to 0
reg_grnt: assert property (@(posedge clk) ($rose(request) |->
##1 $rose(grant)));

Class 12 Copyright 2009 Greg Tumbush

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Delay Expressions
A ## followed by a number or range specifies the delay from the
current clock to the beginning of the sequence that follows.
A_B_C_D: assert property (@(posedge clk)
(A ##1 B ##1 C ##1 D));

Specify large argument to # to span more clocks

A_D: assert property (@(posedge clk) (A ##3 D));
Class 12 Copyright 2009 Greg Tumbush

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Implication
The implication construct specifies that the checking of a property
is performed conditionally
1. |-> Overlapped implication
2. |=> Non-overlapped implication
request |=> grant

equivalent

request |-> ##1 grant

A_B_C_D: assert property (@(posedge clk) (A |=> B |=> C |=> D));

Class 12 Copyright 2009 Greg Tumbush

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Implication Can Pass Vacuously

antecedent seq_expr |-> / |=> (<conseqent seq_expr>);
If the antecedent matches, the consequent must too.
If the antecedent fails, the consequent is not tested and a true
result is forced.
Such forced results are called vacuous and are usually
filtered out.

Source: Mentor Graphics training

Class 12 Copyright 2009 Greg Tumbush

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Implication Can Pass Vacuously

The implication might never start which means it never can fail
A_B_C_D: assert property (@(posedge clk) (A |=> B |=> C |=> D));

Or it can start and stop but never fail

Class 12 Copyright 2009 Greg Tumbush

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Mixing Implication and Delay

A mix of implication and delay expressions might be required
A_B_C_D: assert property (@(posedge clk) (A |=> (B ##1 C ##1 D)));

Class 12 Copyright 2009 Greg Tumbush

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Coverage and Assertions

Any concurrent assertion can be used to collect coverage.
req_grant: assert property (@(posedge clk) (request |=> grant));

req_grant_cover: cover property (@(posedge clk) (request |=> grant));

Class 12 Copyright 2009 Greg Tumbush

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Exercise 3
Re-write the concurrent assertion in exercise 2 so that:
1. Coverage is collected
2. If you used an overlapped implication operator (|->) use a nonoverlapped implication operator (|=>) or vise versa.
3. Remove the disable
branch_done: cover property (@(negedge clk) (branch_inst |=> ##1 jump_done));
or
branch_done: cover property (@(negedge clk) (branch_inst |-> ##2 jump_done));

Class 12 Copyright 2009 Greg Tumbush

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Viewing SVA Coverage Directives

Class 12 Copyright 2009 Greg Tumbush

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Properties
A property can be defined separate from an assertion.
req_grant: assert property (@(posedge clk) (request |=> grant));

property req_grant;
(request |=> grant);
endproperty
A property can be used in both an assertion and a cover directive
assert property (@(posedge) (req_grant));
cover property (@(posedge) (req_grant));
Class 12 Copyright 2009 Greg Tumbush

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Separating Clock from Assertion

A default clock can be defined separate from an assertion.
req_grant: assert property (@(posedge clk) (request |=> grant));

default clocking cb @(posedge clk); endclocking

req_grnt: assert property (request |=> grant);
A clock can be defined in a property
property req_grant;
@(posedge clk) (request |=> grant);
endproperty
assert property (req_grant);
cover property (req_grant);
Class 12 Copyright 2009 Greg Tumbush

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Sequences
Complex sequential behaviors can be described by a sequence
A sequence is part of a property.

A_B_C_D: assert property (@(posedge clk) (A |=> (B ##1 C ##1 D)));

assertion

property

sequence

sequence B_C_D;
(B ##1 C ##1 D);
endsequence // B_C_D
property A_B_C_D_prop;
@(posedge clk) (A |=>B_C_D);
endproperty
A_B_C_D_assert: assert property
(A_B_C_D_prop);
Class 12 Copyright 2009 Greg Tumbush

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Exercise 4
Re-write the concurrent assertion in exercise 3 to:
1. Specify a default clock
2. Express the sequence, property and assertion separately.
default clocking cb @(negedge clk); endclocking
sequence jump_done_seq;
##2 jump_done; or ##1 jump_done if using |=> on property
endsequence
property branch_done_prop;
(branch_inst |-> jump_done_seq);
endproperty
branch_done: assert property (branch_done_prop);

Class 12 Copyright 2009 Greg Tumbush

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Sequence Range
A sequence range can be expressed
sequence B_C_D;
(B ##1 C ##[1:3] D);
endsequence
A_B_C_D_assert: assert property (@(posedge clk) (A |=> B_C_D));

Class 12 Copyright 2009 Greg Tumbush

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Sequence Repeat
A sequence repeat can be expressed
sequence B_C_D;
(B ##1 C ##1 D[*3]);
endsequence
A_B_C_D_assert: assert property (@(posedge clk) (A |=> B_C_D));

Class 12 Copyright 2009 Greg Tumbush

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Mixing Sequence Range and Repeat

A mix of sequence range and repeat can be expressed
sequence B_C_D;
(B ##1 C ##1 D[*2:3]);
endsequence
A_B_C_D_assert: assert property (@(posedge clk) (A |=> B_C_D));

Class 12 Copyright 2009 Greg Tumbush

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Sequences with 0 Ranges

A 0 range can be used if an event might not occur
sequence B_C_D;
(B ##1 C[*0:2] ##1 D);
endsequence
A_B_C_D_assert: assert property (@(posedge clk) (A |=> B_C_D));

Class 12 Copyright 2009 Greg Tumbush

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Sequences with Infinite Ranges

A $ range can be used if a delay or event can occur infinitely long
sequence B_C_D;
(B ##1 C ##[2:$] D);
endsequence
A_B_C_D_assert: assert property (@(posedge clk) (A |=> B_C_D));

Class 12 Copyright 2009 Greg Tumbush

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Exercise 5
Re-write the assertion in exercise 4 to:
1. Require that jump_done can assert from 2 to 4 cycles after
branch_done asserts for a
A. Non-overlapped (|=> property
B. An overlapped (|->) property

Class 12 Copyright 2009 Greg Tumbush

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Exercise 4
Re-write the concurrent assertion in exercise 3 to:
1. Specify a default clock
2. Express the sequence, property and assertion separately.
default clocking cb @(negedge clk); endclocking
sequence jump_done_seq;
##2 jump_done; or ##1 jump_done if using |=> on property
endsequence
property branch_done_prop;
(branch_inst |-> jump_done_seq);
endproperty
branch_done: assert property (branch_done_prop);

Class 12 Copyright 2009 Greg Tumbush

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Goto Repetition
The [ operator indicates that the sequence is consecutive
(B ##1 C[*3] ##1 D);

The [-> operator indicates that the sequence may not be consecutive
sequence B_C_D;
(B ##1 C[->3] ##1 D);
endsequence
A_B_C_D_assert: assert property (@(posedge clk) (A |=> B_C_D));

Class 12 Copyright 2009 Greg Tumbush

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Non-Consecutive Repetition
[-> indicates that the sequence must continue on the last match
(B ##1 C[->3] ##1 D);

[= indicates that the sequence may not continue consecutively

(B ##1 C[=3] ##1 D);

Class 12 Copyright 2009 Greg Tumbush

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Sequences
SystemVerilog sequence operators
[* ] [= ] [-> ]
##
throughout
within
intersect
and
or
A sequence can be declared in
A module
An interface
A program
A clocking block
A package
A compilation-unit scope
Class 12 Copyright 2009 Greg Tumbush

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Sequences Examples: testbench.in

throughout
The throughout operator requires a Boolean to be true
throughout a sequence

Class 12 Copyright 2009 Greg Tumbush

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Sequences (cont.)
within
One sequence can fully contain another sequence

Class 12 Copyright 2009 Greg Tumbush

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Sequences (cont.)
intersect
Sequences must start at the same tie and end at the same
time. Match done at end time.

Class 12 Copyright 2009 Greg Tumbush

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Sequences (cont.)
and
Sequences must start at same time and end at any time.
Match is done after last sequence has ended.
or
Sequence must start at the same time and can end at any
time. Match done at both sequences ends.

Class 12 Copyright 2009 Greg Tumbush

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Viewing Assertions in QuestaSim

Class 12 Copyright 2009 Greg Tumbush

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