UVM-ML Quick Start Guide: 31 July, 2014

UVM-ML Quick Start Guide
For version 1.4.2
31 July, 2014
UVM-ML Quick Start
31-Jul-14
Copyright 2013 Cadence Design Systems, Inc. (Cadence). All rights reserved.
Cadence Design Systems, Inc., 2655 Seely Ave., San Jose, CA 95134, USA.
Copyright 2013 Advanced Micro Devices, Inc. (AMD). All rights reserved.
Advanced Micro Devices, Inc. , One AMD Place, P.O. Box 3453, Sunnyvale, CA 94088, USA.
This product is licensed under the Apache Software Foundations Apache License, Version 2.0 (the
"License") January 2004. The full license is available at: http://www.apache.org/licenses/LICENSE-2.0.
Unless required by applicable law or agreed to in writing, software distributed under the License is
distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing permissions and limitations under the
License.
Notices
Questions or suggestions relating to this document or product can be sent to

[email protected]
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Contents
Introduction to UVM-ML .............................................................................................................................. 4
The UVM-ML Package ............................................................................................................................... 4
Package Installation .................................................................................................................................. 5
Demos ........................................................................................................................................................... 5
Demo 1: Producer Consumer SC-SV-e ...................................................................................................... 6
SC-SV-e Demo Location ......................................................................................................................... 6
Running the SC-SV-e Demo ................................................................................................................... 7
SC-SV-e Demo Results ........................................................................................................................... 7
Demo 2: Unified hierarchy SC-SV .............................................................................................................. 9
Unified Hierarchy Demo Location ....................................................................................................... 10
Running the Unified Hierarchy SC-SV Demo ....................................................................................... 11
Unified Hierarchy Demo Results ......................................................................................................... 11
Demo 3: Unified hierarchy SV-e .............................................................................................................. 13
Running the Unified Hierarchy SV-e Demo ......................................................................................... 14
Demo 4: Unified hierarchy e-SV .............................................................................................................. 15
Running the Unified Hierarchy e-SV Demo ......................................................................................... 17
Sequence Layering Demos ...................................................................................................................... 18
Additional Examples................................................................................................................................ 18
Conclusion ............................................................................................................................................... 18
Trouble Shooting......................................................................................................................................... 18
Demos do not run ................................................................................................................................... 18
Test or demo fail with error: ncvlog: *E,NOPBIND ................................................................................. 19
setup.sh fails with error message: sc_utils_ids.cpp:110: error: ... ......................................................... 19
Errors during compilation of a demo ...................................................................................................... 19
Elaboration error when running a demo or test ..................................................................................... 20
Multiple uvm_pkg ................................................................................................................................... 20
No components instantiated .................................................................................................................. 20
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No components instantiated .................................................................................................................. 20
Introduction to UVM-ML
UVM-ML enables interoperability in multi-language verification environments. It provides methodology
and tools to integrate verification components into a larger verification environment and enables them
to communicate in a coordinated environment. It is a natural extension of the UVM-SV standard in the
multi-language domain.
The central component is a backplane that enables the control and data communication between the
various components using a well defined API. The various components of the verification environment
are implemented in different frameworks which communicate with the backplane through adapters.
This architecture can support many use cases involving integration of verification components that were
developed in different languages and different methodologies. Just to mention a few:
Incorporating a VIP developed in one language into an environment written in a different
language.
Integrating an SoC verification environment built out of legacy verification components.
Connecting a high level stimulus generator to multiple drivers in different languages.
UVM-ML provides an open architecture that can be extended by new features. This release already
supports TLM communication between the frameworks, unified hierarchy where verification
components from different frameworks can be structured in a logical hierarchy, thus providing central
control of the multi-language environment using hierarchical configuration and hierarchical phase
control.
The UVM-ML release package contains the code and documentation needed to apply the methodology.
Start with installing the package as described in the README_INSTALLATION.txt file at the top
directory of the package.
Once installed, use this QuickStart.pdf for first experience with the methodology using the
various demos.
Further reading is available in the white paper that provides in depth discussion of the
requirements, use cases, leading concepts and terminology in ml/docs/misc_docs/uvm-mlwhitepaper.pdf.
For the testbench integrator there is a User Guide explaining in detail how to integrate a UVMML verification environment in ml/docs/basic_docs/IntegratorUserGuide.pdf.
For developers of adapters there is an Adapter Developer Guide that describes how to develop
an adapter for a new framework in ml/docs/misc_docs/AdapterGuide.pdf.
The UVM-ML Package

The full UVM-ML solution is distributed in the UVM-ML tar file. The main components are:
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Source code for the backplane library

UVM-SV framework and the corresponding ML adapter source code
UVM-SC framework and the corresponding ML adapter source code
UVM-e framework and the corresponding ML adapter source code
Setup script and make files
Examples
Documentation
If you are using the OSCI SystemC simulator you must download and install it from the Accellera
downloads site.
Package Installation
To install the UVM-ML package, untar it in a clean directory and follow the instructions in the
README_INSTALLATION.txt file in the top directory.
In case of issues with the installation consult the trouble shooting section at the end of this document.
Demos
This Quick Start document provides you with the minimal amount of information you need to run, and
explore the results of the demos. Different demos are provided for different use cases. There is
considerable repetition of explanation to enable you to explore just the most appropriate demo for your
needs.
The demos provide sample code demonstrating the use of the main capabilities provided with the
library, which are the UVM-ML Backplane that connects several sample Frameworks written in different
languages.
There are four demos in the examples directory.
Demo 1: Producer Consumer SC-SV-e UVM-ML SC-SV-e multi-language testbench

Demo 2: Unified hierarchy SC-SV demonstrates the unified hierarchy with SC IP in SV
environment
Demo 3: Unified hierarchy SV-e demonstrates the unified hierarchy with e IP in SV environment
Demo 4: Unified hierarchy e-SV demonstrates the unified hierarchy with SV IP in e environment
The demos can be run in several modes:
IES When you are using the Cadence tools

IES_OSCIWhen you are using the Cadence tools with the OSCI SystemC simulator
VCS When you are using the Synopsys tools with the OSCI SystemC simulator
QUESTA when you are using the Mentor tools with the OSCI SystemC simulator
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Demo 1: Producer Consumer SC-SV-e

The SC-SV-e demo connects all three environments using blocking and non-blocking TLM1 and TLM2
interfaces. You can find small focused versions showing single connections between two frameworks
under $UVM_ML_HOME/ml/examples/features/tlm1/prod_cons and
$UVM_ML_HOME/ml/examples/features/tlm2/prod_cons.
Note: This demo requires the Cadence Incisive release: IES12.20-s012 or higher
The following figure illustrates the SC-SV-e architecture.
Figure 2: Demo Architecture (SV+SC+e)

SC-SV-e Demo Location
Before you run the SC-SV-e demo, ensure that the installation and setup steps described in Package
Installation section were successful.
To run the demo, first go to the demo directory using the following command line, and then follow the
instructions in the section Running the SC-SV-e Demo:
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% cd $UVM_ML_HOME/ml/examples/prod_cons/sc_sv_e
The following files can be found in the demo directory:
README.txtInstructions for running the demo

consumer.e e code for the consumer
consumer.h SC code for the consumer
consumer.sv - SV code for the consumer
demo.shA shell script to invoke the demo
packet.e e code for the TLM1 packet
packet.h - SC code for the TLM1 packet
packet.sv SV code for the TLM1 packet
producer.e e code for the producer
producer.h SC code for the producer
producer.sv SV code for the producer
sc.cpp SC code for the top components
test.svSV code for the top components
top.e e code for the top components
MakefileThe makefile to build and run the demo
Makefile.iesA makefile used for IES simulation
Makefile.vcsA makefile used for VCS simulation
Makefile.questa A makefile used for Questa simulation
Running the SC-SV-e Demo

Make sure the installation and setup steps listed in the Package Installation section were successful
before you run the demo.
To run the demo using Cadence tools, use the following command line:
% demo.sh IES
To run the demo with Synopsys tools and OSCI SystemC, use the following command line:
% demo.sh VCS
To run the demo with Mentor tools and OSCI SystemC, use the following command line:
% demo.sh QUESTA
SC-SV-e Demo Results

The demo executes in batch mode, and the output shows eight sections of transactions passing from
producer to consumer, which represent all combinations of blocking/non-blocking, TLM1/TLM2, and
SV/SC and SV/e as either initiator or target, including:
non-blocking TLM2 transactions from SV to e

blocking TLM2 transactions from SV to e
non-blocking TLM1 transactions from SV to e
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blocking TLM1 transactions from SV to e

non-blocking TLM2 transactions from SV to SC
blocking TLM2 transactions from SV to SC
non-blocking TLM1 transactions from SV to SC
blocking TLM1 transactions from SV to SC
non-blocking TLM2 transactions from e to SV
blocking TLM2 transactions from e to SV
non-blocking TLM1 transactions from e to SV
blocking TLM1 transactions from e to SV
blocking TLM1 transactions from e to SC
non-blocking TLM1 transactions from e to SC
blocking TLM2 transactions from e to SC
non-blocking TLM2 transactions from e to SC
non-blocking TLM2 transactions from SC to SV
blocking TLM2 transactions from SC to SV
non-blocking TLM1 transactions from SC to SV
blocking TLM1 transactions from SC to SV
blocking TLM2 transactions from SC to e
non-blocking TLM2 transactions from SC to e
blocking TLM1 transactions from SC to e
non-blocking TLM1 transactions from SC to e
The following listing is a small example from the log file that is generated by the demo.
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Running the test ...

SC sctop::start_of_simulation
*** Starting non-blocking TLM2 transactions from SV to e
UVM_INFO @ 0: uvm_test_top.sv_env.producer_1 [producer_1] SV producer sends
33 cb 67 08
[0] consumer-@7: Received nb_transport_fw WRITE 0x33 0xcb 0x67 0x08
UVM_INFO @ 5: uvm_test_top.sv_env.producer_1 [producer_1] SV producer sends
00 00 00 00
[5] consumer-@7: Received nb_transport_fw READ 0x33 0xcb 0x67 0x08
UVM_INFO @ 5: uvm_test_top.sv_env.producer_1 [producer_1] SV producer received
64: 33 cb 67 08
UVM_INFO @ 10: uvm_test_top.sv_env.producer_1 [producer_1]
*** Starting Blocking TLM1 transactions from SC to SV

[390 ns] SC producer::sending T packet: 17
UVM_INFO @ 390: uvm_test_top.sv_env.consumer_2 [consumer_2]
[391 ns] SC producer::sent T packet: 17
...
64:
64:
SV consumer::put
SV consumer::put returns
17
SV consumer::put
18
SV consumer::put
19
17
18
19
** UVM TEST PASSED **
In each section you can see messages from two language frameworks, including the time stamps
indicating coordinated simulation.
The first section in the listing above, shows non-blocking TLM2 transactions generated in the
SystemVerilog framework, targeted to the e consumer. The transactions containing random address and
data are written to the e framework and then read back, comparing the result to the original
transaction.
Demo 2: Unified hierarchy SC-SV

The SC-SV unified hierarchy demo shows how a UVM-SC verification IP can be incorporated in a UVM-SV
environment.
The following figure illustrates the architecture of this demo.
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Figure 3: Demo Architecture for SC+SV unified hierarchy

Unified Hierarchy Demo Location
Before you run the demo, ensure that the installation and setup steps described in Package Installation
section were successful.
instructions in the section Running the Unified Hierarchy SC-SV Demo:
% cd $UVM_ML_HOME/ml/examples/unified_hierarchy/sc_sv

producer.h SC code for the producer
consumer.sv SV code for the consumer
sctop.cpp SC code for the top components
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test.svSV code for the top components

Running the Unified Hierarchy SC-SV Demo

Make sure the installation and setup steps listed in the Package Installation section were successful
% demo.sh IES
% demo.sh VCS
% demo.sh QUESTA
Unified Hierarchy Demo Results

The demo executes in batch mode, and the output shows the order of construction of the ML
environment and the propagation of phases from the UVM-SV environment into the UVM-SC VIP.
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UVM_INFO @ 0: uvm_test_top [test] SV test::new uvm_test_top

UVM_INFO @ 0: uvm_test_top [test] SV test::build uvm_test_top
UVM_INFO @ 0: uvm_test_top.sv_env [env] SV env::new sv_env
UVM_INFO @ 0: uvm_test_top.testbench [testbench] SV env::new testbench
UVM_INFO @ 0: uvm_test_top.sv_env [env] SV env::build
UVM_INFO @ 0: uvm_test_top.sv_env.consumer [cons_type] SV consumer::new
UVM_INFO @ 0: uvm_test_top.sv_env.producer [prod_type] SV producer::new
UVM_INFO @ 0: uvm_test_top.sv_env.consumer [cons_type] SV consumer::build
UVM_INFO @ 0: uvm_test_top.sv_env.consumer [cons_type] SV consumer::b_target_socket.get_full_name
= uvm_test_top.sv_env.consumer.b_target_socket
UVM_INFO @ 0: uvm_test_top.sv_env.consumer [cons_type] SV
consumer::nb_target_socket.get_full_name = uvm_test_top.sv_env.consumer.nb_target_socket
UVM_INFO @ 0: uvm_test_top.sv_env.producer [prod_type] SV producer::build
UVM_INFO @ 0: uvm_test_top.testbench [testbench] SV testbench::build
SC producer::producer name= uvm_test_top.testbench.sctop.sc_env.prod
SC env::env name= uvm_test_top.testbench.sctop.sc_env
SC sctop::sctop name= uvm_test_top.testbench.sctop type= sctop
SC sctop::build uvm_test_top.testbench.sctop
SC env::build uvm_test_top.testbench.sctop.sc_env
SC producer::build uvm_test_top.testbench.sctop.sc_env.prod
SC consumer::build
UVM_INFO @ 0: uvm_test_top [test] SV test registered uvm_test_top.sv_env.consumer.b_target_socket
UVM_INFO @ 0: uvm_test_top [test] SV test registered
uvm_test_top.sv_env.consumer.nb_target_socket
uvm_test_top.sv_env.producer.b_initiator_socket
uvm_test_top.sv_env.producer.nb_initiator_socket
SC sctop::before_end_of_elaboration uvm_test_top.testbench.sctop
SC env::before_end_of_elaboration uvm_test_top.testbench.sctop.sc_env
SC env registered uvm_test_top.testbench.sctop.sc_env.prod.b_isocket
SC env registered uvm_test_top.testbench.sctop.sc_env.prod.nb_isocket
SC env registered uvm_test_top.testbench.sctop.sc_env.cons.tsocket
SC producer::before_end_of_elaboration uvm_test_top.testbench.sctop.sc_env.prod
UVM_INFO @ 0: uvm_test_top.sv_env.consumer [cons_type] SV consumer::connect
uvm_test_top.sv_env.consumer
UVM_INFO @ 0: uvm_test_top.sv_env.producer [prod_type] SV producer::connect
UVM_INFO @ 0: uvm_test_top.sv_env [env] SV env::connect uvm_test_top.sv_env
SC producer::connect uvm_test_top.testbench.sctop.sc_env.prod
SC env::connect uvm_test_top.testbench.sctop.sc_env
SC sctop::connect uvm_test_top.testbench.sctop
UVM_INFO @ 0: uvm_test_top.testbench [testbench] SV testbench::connect uvm_test_top.testbench
UVM_INFO @ 0: uvm_test_top [test] SV test::connect uvm_test_top
...
UVM_INFO @ 10: uvm_test_top.sv_env.producer [prod_type] SV producer::b_transport
UVM_TLM_WRITE_COMMAND [0x00000000000000bb] = 7a e3 f2 4f (status=INCOMPLETE)
[SC 12 ns] consumer::b_transport TLM_WRITE_COMMAND address = 187 data_length = 4 m_data = 7a e3
f2 4f status= 1
UVM_INFO @ 12: uvm_test_top.sv_env.producer [prod_type] SV producer::b_transport done
UVM_TLM_WRITE_COMMAND [0x00000000000000bb] = 7a e3 f2 4f (status=OK)
UVM_INFO @ 20: uvm_test_top.sv_env.producer [prod_type] SV producer::b_transport
UVM_TLM_READ_COMMAND [0x00000000000000bb] = 00 00 00 00 (status=INCOMPLETE)
[SC 22 ns] consumer::b_transport TLM_READ_COMMAND address = bb data_length = 4 m_data = 7a e3 f2
4f status= 1
UVM_INFO @ 22: uvm_test_top.sv_env.producer [prod_type] SV producer::b_transport done
UVM_TLM_READ_COMMAND [0x00000000000000bb] = 7a e3 f2 4f (status=OK)
[SC 30 ns] producer::b_transport TLM_WRITE_COMMAND address = 7f data_length = 4 m_data = e6 ea 53
fe status= 0
UVM_INFO @ 30: uvm_test_top.sv_env.consumer [cons_type] SV consumer::b_transport
UVM_TLM_WRITE_COMMAND [0x000000000000007f] = e6 ea 53 fe (status=INCOMPLETE)
[SC 32 ns] producer::b_transport done TLM_WRITE_COMMAND address = 7f data_length = 4 m_data = e6
ea 53 fe status= 1
[SC 40 ns] producer::b_transport TLM_READ_COMMAND address = 7f data_length = 4 m_data = 0 0 0 0
status= 0
UVM_INFO @ 40: uvm_test_top.sv_env.consumer [cons_type] SV consumer::b_transport
UVM_TLM_READ_COMMAND [0x000000000000007f] = 00 00 00 00 (status=INCOMPLETE)
[SC 42 ns] producer::b_transport done TLM_READ_COMMAND address = 7f data_length = 4 m_data = e6
ea 53 fe status= 1
UVM_INFO @ 42: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
...
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The first section in the listing above, shows the pre-run phases as they alternate between the SV and SC
frameworks as the environment is constructed and then the ports bound across the frameworks.
Demo 3: Unified hierarchy SV-e

This demo shows how a UVM-e verification IP can be instantiated under a UVM-SV environment and
how to use configuration to control the construction of the UVM-e IP.
Figure 4: Demo Architecture for SV+e unified hierarchy

Before you run the demo, ensure that the installation and setup steps described in Package Installation
section were successful.
instructions in the section Running the Unified Hierarchy SV-e Demo:
% cd $UVM_ML_HOME/ml/examples/unified_hierarchy/sv_e
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env.e e IP environment code
env.sv SV IP environment code
svtop.svSV code for the top component
Running the Unified Hierarchy SV-e Demo

Make sure the installation and setup steps listed in the section Package Installation were successful
% demo.sh IES
% demo.sh VCS
% demo.sh QUESTA

environment and the propagation of phases from the UVM-SV environment into the UVM-SV and UVMe verification IP.
This demo also demonstrates the configuration capability by showing how the UVM-SV test component
controls the construction of the UVM-e VIP. In its build phase, the test component sets a random value
for the address to be used in both producer components. In addition it controls the generation of both
IP using the *_active configuration attribute. When set to FALSE, the IP will not instantiate its producer,
and therefore will not generate transactions.
set_config_int("*producer","address", ($urandom() & 'hffff));
set_config_int("*env","e_active",e_active);
set_config_int("*env","sv_active",sv_active);
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UVM_INFO @ 0: uvm_test_top [svtop] SV svtop::new uvm_test_top
Generating the test with IntelliGen using seed 1...
UVM_INFO @ 0: uvm_test_top [svtop] SV svtop::build
UVM_INFO @ 0: uvm_test_top.sv_env [sv_env] SV sv_env::new sv_env
UVM_INFO @ 0: uvm_test_top.sv_env [sv_env] SV sv_env::build
UVM_INFO @ 0: uvm_test_top.sv_env.producer [prod_type] SV producer::new
UVM_INFO @ 0: uvm_test_top.sv_env.consumer [cons_type] SV consumer::new
UVM_INFO @ 0: uvm_test_top.sv_env.consumer [cons_type] SV consumer::build
UVM_INFO @ 0: uvm_test_top.sv_env.producer [prod_type] SV producer::build
UVM_INFO @ 0: uvm_test_top.sv_env.consumer [cons_type] SV consumer::connect
UVM_INFO @ 0: uvm_test_top [svtop] SV svtop::connect uvm_test_top
UVM_INFO @ 0: uvm_test_top.sv_env.consumer [cons_type] SV consumer::resolve_bindings
UVM_INFO @ 0: uvm_test_top [svtop] SV env::resolve_bindings uvm_test_top
UVM_INFO @ 0: uvm_test_top.sv_env.consumer [cons_type] SV consumer::end_of_elaboration
UVM_INFO @ 0: uvm_test_top [svtop] SV env::end_of_elaboration uvm_test_top
Starting the test ...
Running the test ...
UVM_INFO @ 0: uvm_test_top.sv_env.consumer [cons_type] SV consumer::start_of_simulation
UVM_INFO @ 0: uvm_test_top [svtop] SV env::start_of_simulation uvm_test_top
*** Starting non-blocking TLM2 transactions from e
[10] producer-@6: Calling nb_transport_fw WRITE 0xd0 0xe4 0x59 0x60
UVM_INFO @ 10: uvm_test_top.sv_env.consumer [cons_type] SV consumer::nb_transport_fw
UVM_TLM_WRITE_COMMAND [0x0000000000004123] = d0 e4 59 60 (status=INCOMPLETE)
UVM_INFO @ 15: uvm_test_top.sv_env.consumer [cons_type] SV consumer responds
UVM_TLM_WRITE_COMMAND [0x0000000000004123] = d0 e4 59 60 (status=OK)
[15] producer-@6: Received nb_transport_bw TLM_OK_RESPONSE phase= BEGIN_RESP
[20] producer-@6: Calling nb_transport_fw READ 0x00 0x00 0x00 0x00
UVM_INFO @ 20: uvm_test_top.sv_env.consumer [cons_type] SV consumer::nb_transport_fw
UVM_TLM_READ_COMMAND [0x0000000000004123] = 00 00 00 00 (status=INCOMPLETE)
[20] producer-@6: nb_transport READ returned 0xd0 0xe4 0x59 0x60
UVM_INFO @ 25: uvm_test_top.sv_env.consumer [cons_type] SV consumer responds
UVM_TLM_READ_COMMAND [0x0000000000004123] = d0 e4 59 60 (status=OK)
*** Starting blocking TLM2 transactions from e
...
The output shows the construction of the testbench starting with the UVM-SV test component. Both the
UVM-e IP and the UVM-SV IP are generated from the testbench during the build phase. The test
component controls the construction of both IP using the configuration mechanism.
During the run phase the IP are communicating by passing blocking and non-blocking transactions in
both directions.
Demo 4: Unified hierarchy e-SV

This demo shows how a UVM-SV verification IP can be instantiated under a UVM-e environment and
how to use configuration to control the construction of the UVM-SV IP.
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Figure 5: Demo Architecture for e+SV unified hierarchy

Before you run the demo, ensure that the installation and setup steps described in the Package
Installation section were successful.
instructions in the section Running the Unified Hierarchy e-SV Demo:
% cd $UVM_ML_HOME/ml/examples/unified_hierarchy/e_sv

env.e e IP environment code
svtop.sv SV IP environment code
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Running the Unified Hierarchy e-SV Demo

Make sure the installation and setup steps listed in the section were successful before you run the
demo.
% demo.sh IES
% demo.sh VCS
% demo.sh QUESTA

environment and the propagation of phases from the UVM-e environment into the UVM-SV and UVM-e
verification IP.
This demo also demonstrates the configuration capability by showing how the UVM-e testbench
component controls the construction of the both VIP. The testbench component sets the value for the
address to be used in both producer components.
keep uvm_config_set("*producer", "address", 0x1000);
*** Starting non-blocking TLM2 transactions from e
[10] producer-@7: Calling nb_transport_fw WRITE 0xd0 0xe4 0x59 0x60
UVM_INFO @ 10: sys.testbench.sv_child.consumer [cons_type] SV consumer::nb_transport_fw
UVM_TLM_WRITE_COMMAND [0x0000000000001000] = d0 e4 59 60 (status=INCOMPLETE)
[10] producer-@7: return status TLM_ACCEPTED END_REQ
UVM_INFO @ 10: sys.testbench.sv_child.consumer [cons_type] SV consumer::respond
UVM_TLM_WRITE_COMMAND [0x0000000000001000] = d0 e4 59 60 (status=OK)
[20] producer-@7: Calling nb_transport_fw READ 0x00 0x00 0x00 0x00
UVM_INFO @ 20: sys.testbench.sv_child.consumer [cons_type] SV consumer::nb_transport_fw
UVM_TLM_READ_COMMAND [0x0000000000001000] = 00 00 00 00 (status=INCOMPLETE)
[20] producer-@7: return status TLM_ACCEPTED END_REQ
[20] producer-@7: nb_transport READ returned 0xd0 0xe4 0x59 0x60
UVM_INFO @ 20: sys.testbench.sv_child.consumer [cons_type] SV consumer::respond
UVM_TLM_READ_COMMAND [0x0000000000001000] = d0 e4 59 60 (status=OK)
...
The output shows the IP communicating by passing blocking and non-blocking transactions in both
directions.
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Sequence Layering Demos

Two sequence layering demos are included in the release. They demonstrate how sequencers in one
language can be driven from another language.
These examples can be found in $UVM_ML_HOME/ml/examples/sequence_layering. Each example has
a document describing the example and how to run it.
Additional Examples
Additional small examples are available under the $UVM_ML_HOME/ml/examples/features
directory with makefiles to run each test. These examples check for proper behavior of specific features,
such as ML TLM communication, and synchronized ML testbench construction.
Conclusion
This Quick Start provided you with the basic information you need to install, run, and view the results of
the SC-SV demo and the SV-e demo that are supplied with the UVM Multi-Language package. For more
information about UVM go to UVM World at: http://www.uvmworld.org
Trouble Shooting
It is recommended to clean the work environment and retry the simulation when the error indication
does not make sense. The tools (like irun) are trying to minimize the work by skipping steps that need
not be repeated. This may cause problem especially if you switch simulators or machines.
One way to do this is make clean. If you dont use the makefiles included in the package, make sure to
clean the work directory, remove the INCA_libs for IES or the equivalent in other simulators.
Following are some identified issues users might hit, and the recommended solutions for them:
Demos do not run

Problem: A demo fails in compilation or elaboration.
Explanation: The makefiles and demo scripts use environment variables which are set during setup.
When running in a different environment one must set the values of these variables using the
setup.captured.sh script. In addition there is a test_install.sh script which will print the relevant
environment variables. These can be compared with the content of setup.capture.sh to make sure the
values were not modified.
Solution: Source the script to set the environment where you run the demo
source $UVM_ML_HOME/ml/setup.captured.sh
If this does not solve the problem run the test_install.sh script and attach the output with the content of
the setup.captured.sh script to your support request.
source $UVM_ML_HOME/ml/test_install.sh
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Test or demo fail with error: ncvlog: *E,NOPBIND

Problem: A test or demo fails with the following error:
import uvm_ml::*;
|
ncvlog: *E,NOPBIND (./test.sv,22|12): Package uvm_ml could not be bound.
Explanation: For UVM-ML one must use the ML ready UVM-SV library included in the release. This error
message is received when the UVM_HOME environment variable is set to a different path which does
not contain the ML ready version of UVM-SV.
Solution: Unset the UVM_HOME environment variable
% unsetenv UVM_HOME
setup.sh fails with error message: sc_utils_ids.cpp:110: error: ...

Problem: sourcing the script setup.sh (or compiling the SC library in any other way) fails with the
following (or similar) errors:
... /sc_utils_ids.cpp:110: error: 'getenv' is not a member of 'std'
... /sc_utils_ids.cpp:111: error: 'strcmp' was not declared in this scope
Explanation: This is a known issue with the Accellera SystemC (open source) version systemc-2.2.0 when
compiled with GNU C++ version above 4.3. See http://openesl.org/systemc-wiki/Installation for more
information.
Solution: The suggested solution is to use the patch in the link above or manually modify
sysc/utils/sc_utils_ids.cpp so that it will explicitly include the following files:
#include "string.h"
#include "cstdlib"
Errors during compilation of a demo

Problem: some of the necessary packages are not available or the path is not set properly
... error: tlm_h/tlm_version.h: No such file or directory
... error: sysc/datatypes/bit/sc_lv.h: No such file or directory
Solution: Verify that the environment variables are set properly and the packages are in the place
pointed by the environment variable e.g.
setenv OSCI_INSTALL ... /2.2/g++-4.4.5-pic
setenv OSCI_SRC ... /systemc-2.2.0
setenv TLM2_INSTALL ... /TLM-2009-07-15/include/tlm
UVM-ML Quick Start
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Elaboration error when running a demo or test

Problem: Elaboration using the wrong library or passing the wrong arguments to the linker
ncelab: *F,SCILDD: Could not load SystemC model library...
Solution: irun must pass the appropriate arguments to the linker as shown in irun_uvm_ml.64.f
irun f $UVM_ML_HOME/ml/tests/irun_uvm_ml.64.f ...
Multiple uvm_pkg
Problem: Verilog compilation reports multiple uvm_pkg
ncvlog: *E,MULTPK (...): Multiple (2) packages named "uvm_pkg" were found in
the searched libraries
Explanation: If different parts of the code are compiled with different versions of UVM-SV, a conflict is
detected by the Verilog compiler. This could be a result of creating a snapshot with the default version in
the IES release and then adding on top the UVM-ML OA version.
Solution: Make sure all the code is compiled with the same version included in the UVM-ML OA
installation.
No components instantiated
Problem: The simulator reports that no components were instantiated.
UVM_FATAL @ 0: reporter [NOCOMP] No components instantiated. You must either
instantiate at least one component before calling run_test or use run_test to
do so. To run a test using run_test, use +UVM_TESTNAME or supply the test name
in the argument to run_test(). Exiting simulation.
Explanation: The cause for this may be that the users UVM-SV code includes a call to run_test() despite
the fact that this is a UVM-ML OA environment in which only uvm_ml_run_test() should be called. In
this case there is a conflict between UVM-SV and UVM-ML, both attempting to drive the simulation.
Solution: In UVM-ML OA verification environments use only uvm_ml_run_test() and remove the call to
run_test().
Failing to load Specman library

Problem: The demo fails with incompatible library indication.
rundynlib - failed to load the provided library .../libsn_sn_uvm_ml.so
OS MSG:
.../libsn_sn_uvm_ml.so: undefined symbol: ...
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Explanation: The cause of this failure is the difference between the currently used Specman version and
the one used in installing UVM-ML OA.
Solution: UVM-ML OA must be rebuilt with the current Specman version. Use the clean flag with the
install.csh script.
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What are the demos included in the UVM-ML package?

What are the demos included in the UVM-ML package?

What issues may occur when running UVM-ML demos or tests?

What issues may occur when running UVM-ML demos or tests?

UVM-ML Quick Start Guide

For version 1.4.2

UVM-ML Quick Start

Questions or suggestions relating to this document or product can be sent to

UVM-ML Quick Start

No components instantiated .................................................................................................................. 20

The UVM-ML Package

UVM-ML Quick Start

Source code for the backplane library

Demo 1: Producer Consumer SC-SV-e UVM-ML SC-SV-e multi-language testbench

The demos can be run in several modes:

IES When you are using the Cadence tools

UVM-ML Quick Start

Demo 1: Producer Consumer SC-SV-e

Figure 2: Demo Architecture (SV+SC+e)

UVM-ML Quick Start

The following files can be found in the demo directory:

README.txtInstructions for running the demo

Running the SC-SV-e Demo

SC-SV-e Demo Results

non-blocking TLM2 transactions from SV to e

UVM-ML Quick Start

blocking TLM1 transactions from SV to e

UVM-ML Quick Start

Running the test ...

*** Starting Blocking TLM1 transactions from SC to SV

** UVM TEST PASSED **

Demo 2: Unified hierarchy SC-SV

UVM-ML Quick Start

Figure 3: Demo Architecture for SC+SV unified hierarchy

The following files can be found in the demo directory:

README.txtInstructions for running the demo

UVM-ML Quick Start

test.svSV code for the top components

Running the Unified Hierarchy SC-SV Demo

Unified Hierarchy Demo Results

UVM-ML Quick Start

UVM_INFO @ 0: uvm_test_top [test] SV test::new uvm_test_top

UVM-ML Quick Start

Demo 3: Unified hierarchy SV-e

Figure 4: Demo Architecture for SV+e unified hierarchy

UVM-ML Quick Start

The following files can be found in the demo directory:

README.txtInstructions for running the demo

Running the Unified Hierarchy SV-e Demo

Unified Hierarchy Demo Results

UVM-ML Quick Start

Demo 4: Unified hierarchy e-SV

UVM-ML Quick Start

Figure 5: Demo Architecture for e+SV unified hierarchy

The following files can be found in the demo directory:

README.txtInstructions for running the demo

UVM-ML Quick Start

Makefile.iesA makefile used for IES simulation

Running the Unified Hierarchy e-SV Demo

UVM TEST PASSED