Introduction

The Verilog Hardware Description Language

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Figure 1-0 Example 1-0 Syntax 1-0 Table 1-0

Introduction
This reference manual describes the features of the Verilog-XL digital logic simulator and the Verilog Hardware Description Language you use to model a design for simulation by Verilog-XL. There are three volumes in this reference manual. Section 1.3 consists of brief descriptions of all the chapters and appendices in this reference manual and shows the divisions between volumes. The volumes of the reference manual are not separate documents. The reference manual has a table of contents, located at the front of each volume, and an index, located at the back of each volume.

1.1 The Verilog Hardware Description Language

The Verilog Hardware Description Language (HDL) describes a hardware design or part of a design. Descriptions of designs in the Verilog HDL are Verilog models. The Verilog HDL is both a behavioral and structural language. Models in the Verilog HDL can describe both the function of a design and the components and connections to the components in a design.

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Verilog models can be developed for different levels of abstraction. These levels of abstraction and their corresponding model types are as follows: algorithmic RTL gate-level switch-level a model that implements a design algorithm in high-level language constructs a model that describes the flow of data between registers and how a design processes that data a model that describes the logic gates and the connections between logic gates in a design a model that describes the transistors and storage nodes in a device and the connections between them

The basic building block of the Verilog HDL is the module. The module format facilitates top-down and bottom-up design. A module contains a model of a design or part of a design. Modules can incorporate other modules to establish a model hierarchy that describes how parts of a design are incorporated in an entire design. The constructs of the Verilog HDL, such and its declarations and statements, are enclosed in modules. The Verilog HDL behavioral language is structured and procedural like the C programming language. The behavioral language constructs are for algorithmic and RTL models. The behavioral language provides the following capabilities: structured procedures for sequential or concurrent execution explicit control of the time of procedure activation specified by both delay expressions and by value changes called event expressions explicitly named events to trigger the enabling and disabling of actions in other procedures procedural constructs for conditional, if-else, case, and looping operations procedures called tasks that can have parameters and non-zero time duration procedures called functions that allow the definition of new operators arithmetic, logical, bit-wise, and reduction operators for expressions The Verilog HDL structural language constructs are for gate-level and switch-level models. The structural language provides the following capabilities: a complete set of combinational primitives primitives for bidirectional pass and resistive devices the ability to model dynamic MOS models with charge sharing and charge decay

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The Verilog-XL Logic Simulator

Verilog structural language models can accurately model signal contention. In the Verilog HDL, structural modeling accuracy is enhanced by primitive delay and output strength specification. Signal values can have different strengths and a full range of ambiguous values to reduce the pessimism of unknown conditions.

1.2 The Verilog-XL Logic Simulator

The Verilog-XL digital logic simulator is a software tool that allows you to perform the following tasks in the design process without building a hardware prototype: determine the feasibility of new design ideas try more than one approach to a design problem functional verification identify design errors To use Verilog-XL, you develop models that describe your design and its environment in the Verilog Hardware Description Language (the Verilog HDL) and then supply Verilog-XL with the file names that contain these models. To use Verilog-XL, you also need a Verilog-XL license. This section describes the major features of Verilog-XL and the Verilog-XL license.

1.2.1 Major Features of Verilog-XL

Verilog-XL provides you with the following simulation capabilities: set break points during simulation that stop the simulation and allow you to enter an interactive mode to examine and debug your design display information about the current state of the design and to specify the format of that information apply stimulus during simulation circuit patching during simulation tracing the execution flow of the statements in your model traversing the model hierarchy to various regions of your design to examine the state of the simulation in that region stepping through the statements of a design and executing them one at a time displaying the active statements in a design displaying and disabling the operations you entered in interactive mode

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reading data from a file and writing data to that file saving the current state of a simulation in a file and restoring that simulation at another time investigating the performance ramifications of architectural decisionstochastic modeling

1.2.2 Verilog-XL Licenses

To get permission to simulate with the Verilog-XL logic simulator you need a license. SoftShare handles all licenses for Verilog-XL 1.6c. Highlands FLEXlm (Flexible License Manager) software is the core of SoftShare technology. Licenses for Verilog-XL 1.6c are all floating XL licenses, but it is possible to lock a license to a node. A Verilog-XL invocation causes SoftShare processes to seek a license file, and check out a license for you if one is available.

1.3 The Contents of the Reference Manual

Volume 1
Chapter 1 Introduction This chapter discusses the major features of the Verilog HDL and the Verilog-XL logic simulator. It also discusses the contents of the reference manual. Chapter 2 Lexical Conventions This chapter describes how the language interprets and how to specify lexical tokens. A lexical token is one or more characters. Lexical tokens include white space, comments, numbers, character strings, identifiers, keywords, and operators. The chapter also describes the text macro substitution facility. Chapter 3 Data Types This chapter describes the Verilog HDL data types. The Verilog HDL has two main groups of data types: registers and nets. Registers and nets model storage devices and physical connections. The chapter also discusses the parameter data type for constant values and describes drive and charge strength of the values on nets. Chapter 4 Expressions This chapter describes the operators and operands that can be used in expressions.

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Chapter 5 Assignments This chapter compares the two main types of assignment statements in the Verilog HDL continuous assignments and procedural assignments. It describes the continuous assignment statement that drives values onto nets. Chapter 6 Gate and Switch Level Modeling This chapter describes the gate and switch level primitive and their declarations and specifications. Chapter 7 User-Defined Primitives (UDPs) This chapter describes how a primitive can be defined in the Verilog HDL and how these primitives are included in Verilog models. Chapter 8 Behavioral Modeling This chapter describes procedural assignments and the behavioral language statements. Chapter 9 Tasks and Functions This chapter describes tasks and functions procedures that can be called from more than one place in a behavioral model. It describes how tasks can be used like subroutines and how functions can be used to define new operators. Chapter 10 Disabling of Named Blocks and Tasks This chapter describes how to disable the execution of a task and a block of statements that has a specified name. Chapter 11 Procedural Continuous Assignments This chapter describes a type of procedural assignment called a procedural continuous assignment. Chapter 12 Hierarchical Structures This chapter describes how model hierarchies are created in the Verilog HDL and how parameter values declared in a module can be overridden. The chapter also discusses macro modules a construct that saves memory and port collapsing a technique that improves simulator efficiency.

Volume 2
Chapter 13 Specify Blocks (SDPDs) This chapter describes the Verilog HDL constructs that belong in a construct called a specify block. Specify blocks contain pin-to-pin delays and timing checks. Chapter 14 State-dependent Path Delays This chapter describes pin-to-pin delays whose validity is conditioned by the values at pins. Chapter 15 Module Input Port Delays (MIPDs) This chapter describes modeling delays between certain drivers and their loads with Module Input Port Delays (MIPDs). It discusses the use of PLI access routines to insert MIPDs.

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Chapter 16 Timescales This chapter describes how you can use models that were developed with different time units together in a simulation. Chapter 17 Delay Mode Selection This chapter describes how you use command line options and compiler directives to alter the delay values in your models. Chapter 18 The Behavior Profiler This chapter describes how you can identify the behavioral modules and statements in your design that use the most CPU time during simulation. Chapter 19 Value Change Dump File This chapter describes how you can produce a file that contains information about value changes during simulation nets and registers that you select. Chapter 20 Source Protection This chapter describes how to protect proprietary Verilog HDL source descriptions from being accessed or modified. Chapter 21 System Tasks and Functions This chapter describes the general purpose system tasks and functions that are built into Verilog-XL. Chapter 22 Programmable Logic Arrays This chapter describes the system tasks that you can use to model PLA devices. Chapter 23 Stochastic Analysis This chapter describes the system tasks that you can use for stochastic analysis investigating the performance ramifications of architectural decisions. Chapter 24 Compilation and Execution This chapter describes the compiler directives and command line options that control how Verilog-XL compiles and simulates your model.

Volume 3
Chapter 25 Library Management This chapter describes two different schemes that enable you to save compilation time and memory by controlling what modules, in the source description file or directory, Verilog-XL compiles. The newer of the two schemes provides greater control over library scanning. Chapter 26 Interactive Control and Debugging This chapter describes the how to use the features of Verilog-XL s interactive mode. Chapter 27 XL Usage and Performance This chapter describes the high-speed XL algorithm that accelerates the simulation of gate and switch-level primitives and certain continuous assignments in a model. It discusses how you

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invoke the XL algorithm, the primitives and continuous assignments whose simulation it accelerates, and performance expectations. Chapter 28 Switch-level Simulation This chapter describes three algorithms that simulate channel-connected switch networks, one of which is default. The first non-default algorithm, named the Switch-XL algorithm, employs the XL algorithm to simulate bidirectional switches and a strength model that allows you to specify a wide range of capacitances and conductances. The other non-default algorithm, named the Switch-RC algorithm, enables you to simulate with real resistances and capacitances and to describe the electrical characteristics of manufacturing technologies. Chapter 29 Software Behavior and Recommendations This chapter discusses software behavior that it is helpful to be aware of and some methods for dealing with it. Appendix A Formal Syntax Definition This appendix describes in the Baccus-Naur Format (BNF), the syntax of the Verilog HDL. Appendix B The Switch-RC Algorithm This appendix discusses the equations in the Switch-RC algorithm. Appendix C Switch-RC Technology Characterization This appendix describes how to derive values that describe Switch-RC technologies.

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