M TECH EMBEDDED SYSTEM LAB MANUAL

RTL SIMULATION AND SYNTHESIS WITH PLDS LAB

Department Of
ELECTRONICS & COMMUNICATION ENGINEERING
VIGNAN INSTITUTE OF TECHNOLOGY AND
SCIENCE
VIGNAN HILLS, DESHMUKHI VILLAGE, POCHAMPALLY (MANDAL)
NALGONDA (DISTRICT) - 508284
Sponsored by
Lavu Educational Society
(Approved by AICTE and Affiliated to JNT University, Hyderabad)
 Introduction

Xilinx Tools is a suite of software tools used for the design of digital circuits
implemented using Xilinx Field Programmable Gate Array (FPGA) or Complex
Programmable Logic Device (CPLD). The design procedure consists of (a) design
entry, (b) synthesis and implementation of the design, (c) functional simulation and
(d) testing and verification. Digital designs can be entered in various ways using
the above CAD tools: using a schematic entry tool, using a hardware description
language (HDL) – Verilog or VHDL or a combination of both. In this lab we will
only use the design flow that involves the use of Verilog HDL.

The CAD tools enable you to design combinational and sequential

circuits starting with Verilog HDL design specifications. The steps of this design
procedure are listed below:

1. Create Verilog design input file(s) using template driven editor.

2. Compile and implement the Verilog design file(s).

3. Create the test-vectors and simulate the design (functional simulation)

without using a PLD (FPGA or CPLD).

4. Assign input/output pins to implement the design on a target device.

5. Download bitstream to an FPGA or CPLD device.

6. Test design on FPGA/CPLD device

A Verilog input file in the Xilinx software environment consists of the

following segments:

Header: module name, list of input and output ports.

Declarations: input and output ports, registers and wires.

Logic Descriptions: equations, state machines and logic functions.

 End: endmodule

All your designs for this lab must be specified in the above Verilog input
format. Note that the state diagram segment does not exist for combinational logic
designs.

2. Programmable Logic Device: FPGA

In this lab digital designs will be

implemented in the Basys2 board which has a Xilinx Spartan3E –XC3S250E
FPGA with CP132 package. This FPGA part belongs to the Spartan family of
FPGAs. These devices come in a variety of packages. We will be using devices
that are packaged in 132 pin package with the following part number: XC3S250E-
CP132. This FPGA is a device with about 50K gates.

3. Creating a New Project

Xilinx Tools can be started by clicking on the Project Navigator Icon on the
Windows desktop. This should open up the Project Navigator window on your
screen. This window shows (see Figure 1) the last accessed project.
3.1 Opening a project

Select File->New Project to create a new project. This will bring up a new
project window (Figure 2) on the desktop. Fill up the necessary entries as follows:
 Project Name: Write the name of your new project.

Project Location: The directory where you want to store the new project
(Note: DO NOT specify the project location as a folder on Desktop or a folder in
the Xilinx\bin directory. Your H: drive is the best place to put it. The project
location path is NOT to have any spaces in it eg: C:\Nivash\TA\new lab\sample
exercises\o_gate is NOT to be used)

Leave the top level module type as HDL.

Example: If the project name were “o_gate”, enter “o_gate” as the project name
and then click “Next”. Clicking on NEXT should bring up the following window:
For each of the properties given below, click on the ‘value’ area and select from
the list of values that appear.

Device Family: Family of the FPGA/CPLD used. In this laboratory we will be

using the Spartan3E FPGA’s.

Device: The number of the actual device. For this lab you may enter XC3S500E
(this can be found on the attached prototyping board)

Package o: The type of package with the number of pins. The Spartan FPGA used
in this lab is packaged in FG320 package.

Speed Grade: The Speed grade is “-5”.

Synthesis Tool: XST [VHDL/Verilog].

Simulator: The tool used to simulate and verify the functionality of the design.
Modelsim simulator is integrated in the Xilinx ISE. Hence choose “Modelsim-XE
Verilog” as the simulator or even Xilinx ISE Simulator can be used.

o Then click on NEXT to save the entries.

All project files such as schematics, netlists, Verilog files, VHDL files, etc., will be
stored in a subdirectory with the project name. A project can only have one top
level HDL source file (or schematic). Modules can be added to the project to create
a modular, hierarchical design (see Section 9).

In order to open an existing project in Xilinx Tools, select File->Open Project to

show the list of projects on the machine. Choose the project you want and click
OK.
If creating a new source file, Click on the NEW SOURCE.

3.2 Creating a Verilog HDL input file for a combinational logic design

In this lab we will enter a design using a structural or RTL description using the
Verilog HDL. You can create a Verilog HDL input file (.v file) using the HDL Editor
available in the Xilinx ISE Tools (or any text editor). In the previous
window, click on the NEW SOURCE

A window pops up as shown in Figure 4. (Note: “Add to project” option is

selected by default. If you do not select it then you will have to add the new
source file to the project manually.)
 Select Verilog Module and in the “File Name:” area, enter the name of the
Verilog source file you are going to create. Also make sure that the option Add to
project is selected so that the source need not be added to the project again. Then
click on Next to accept the entries. This pops up the following window (Figure 5).
 Once you click on Finish, the source file will be displayed in the sources
window in the Project Navigator (Figure 1).

If a source has to be removed, just right click on the source file in the
Sources in Project window in the Project Navigator and select Remove in that.
Then select Project -> Delete Implementation Data from the Project Navigator
menu bar to remove any related files.
 3.3 Editing the Verilog source file
The source file will now be displayed in the Project Navigator window
(Figure 8). The source file window can be used as a text editor to make any
necessary changes to the source file. All the input/output pins will be displayed.
Save your Verilog program periodically by selecting the File->Save from the
menu. You can also edit Verilog programs in any text editor and add them to the
project directory using “Add Copy Source”.

Adding Logic in the generated Verilog Source code template:

A brief Verilog Tutorial is available in Appendix-A. Hence, the language
syntax and construction of logic equations can be referred to Appendix-A.

The Verilog source code template generated shows the module name, the list
of ports and also the declarations (input/output) for each port. Combinational logic
code can be added to the verilog code after the declarations and before the
endmodule line.

For example, an output z in an OR gate with inputs a and b can be described

as, assign z = a | b;

Remember that the names are case sensitive.

Other constructs for modeling the logic function:

A given logic function can be modeled in many ways in verilog. Here is
another example in which the logic function, is implemented as a truth table using
a case statement:

module or_gate(a,b,z);

input a;

input b;

output z;

reg z;

always @(a or b)

begin

case ({a,b})

00: z = 1'b0;

01: z = 1'b1;

10: z = 1'b1;

11: z = 1'b1;

endcase
end
endmodule
Suppose we want to describe an OR gate. It can be done using the logic equation as
shown in Figure 9a or using the case statement (describing the truth table) as
shown in Figure 9b. These are just two example constructs to design a logic
function. Verilog offers numerous such constructs to efficiently model designs. A
brief tutorial of Verilog is available in Appendix-A.
4. Synthesis and Implementation of the Design
The design has to be synthesized and implemented before it can be checked
for correctness, by running functional simulation or downloaded onto the
prototyping board. With the top-level Verilog file opened (can be done by double-
clicking that file) in the HDL editor window in the right half of the Project
Navigator, and the view of the project being in the Module view , the implement
design option can be seen in the process view. Design entry utilities and Generate
Programming File options can also be seen in the process view. The former can be
used to include user constraints, if any and the latter will be discussed later.

To synthesize the design, double click on the Synthesize Design option in the
Processes window.

To implement the design, double click the Implement design option in the
Processes window. It will go through steps like Translate, Map and Place & Route.
If any of these steps could not be done or done with errors, it will place a X mark
in front of that, otherwise a tick mark will be placed after each of them to indicate
the successful completion. If everything is done successfully, a tick mark will be
placed before the Implement Design option. If there are warnings, one can see
mark in front of the option indicating that there are some warnings. One can look
at the warnings or errors in the Console window present at the bottom of the
Navigator window. Every time the design file is saved; all these marks disappear
asking for a fresh compilation.

The schematic diagram of the synthesized verilog code can be viewed by

double clicking View RTL Schematic under Synthesize-XST menu in the Process
Window. This would be a handy way to debug the code if the output is not meeting
our specifications in the proto type board.

By double clicking it opens the top level module showing only input(s) and
output(s) as shown below.
 Figure 13: Realized logic by the XilinxISE for the verilog code

5. Functional Simulation of Combinational Designs

5.1 Adding the test vectors
To check the functionality of a design, we have to apply test vectors and simulate
the circuit. In order to apply test vectors, a test bench file is written. Essentially it
will supply all the inputs to the module designed and will check the outputs of the
module. Example: For the 2 input OR Gate, the steps to generate the test bench is
as follows:

In the Sources window (top left corner) right click on the file that you want to
generate the test bench for and select ‘New Source’

Provide a name for the test bench in the file name text box and select ‘Verilog
test fixture’ among the file types in the list on the right side as shown in figure 11.
 module o_gate_tb_v;

// Inputs

reg a;

reg b;

// Outputs

wire z;

// Instantiate the Unit Under Test (UUT)

o_gate uut (

.a(a),

.b(b),

.z(z)

);

initial begin

// Initialize Inputs

a = 0;

b = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

End

endmodule
The Xilinx tool detects the inputs and outputs of the module that you are going to
test and assigns them initial values. In order to test the gate completely we shall
provide all the different input combinations. ‘#100’ is the time delay for which the
input has to maintain the current value. After 100 units of time have elapsed the
next set of values can be assign to the inputs. Complete the test bench as shown
below:

module o_gate_tb_v;

// Inputs

reg a;

reg b;

// Outputs

wire z;

// Instantiate the Unit Under Test (UUT)

o_gate uut (

.a(a),

.b(b),

.z(z)

);

initial begin

// Initialize Inputs

a=0;

b=0;

// Wait 100 ns for global reset to finish

#100;

a = 0;

b = 1;

// Wait 100 ns for global reset to finish

#100;

a = 1;

b = 0;

// Wait 100 ns for global reset to finish

#100;

a=1;

b=1;

// Wait 100 ns for global reset to finish

#100;

End

Endmodule

Save your test bench file using the File menu.

5.2 Simulating and Viewing the Output Waveforms

Now under the Processes window (making sure that the testbench file in the
Sources window is selected) expand the ModelSim simulator Tab by clicking on
the add sign next to it. Double Click on Simulate Behavioral Model. You will
probably receive a complier error. This is nothing to worry about – answer “No”
when asked if you wish to abort simulation. This should cause ModelSim to open.
Wait for it to complete execution. If you wish to not receive the compiler error,
right click on Simulate Behavioral Model and select process properties. Mark the
checkbox next to “Ignore Pre-Complied Library Warning Check”.
5.3 Saving the simulation results
To save the simulation results, Go to the waveform window of the Modelsim
simulator, Click on File -> Print to Postscript -> give desired filename and location

Note that by default, the waveform is “zoomed in” to the nanosecond level.
Use the zoom controls to display the entire waveform..

Else a normal print screen option can be used on the waveform window and
subsequently stored in Paint.
For taking printouts for the lab reports, convert the black background to white in
Tools -> Edit Preferences. Then click Wave Windows -> Wave Background
attribute.

5. Once the program is working properly it is time to create a UCF (user constraint file) and
assign the FPGA pins to the program inputs and outputs. Pin assignments can be found in the
Spartan 3E Starter User Guide.

6. Select “Synthesis/Implementation” from the pull down menu on the Sources window. In
the Processes window expand the “User Constraints” toolbox and double click on “Assign
Package Pins”. Choose “Yes” when Project Navigator asks to add a UCF file to the project.

7. After the Xilinx PACE program starts, resize the Design Object List - I/O Pins window until
the Termination column is visible. Enter the pin assignments in the Loc column. The Spartan
board’s buttons need the “PULLDOWN” constraint to function properly. Enter
“PULLDOWN” in the Termination column for ‘clk’ and ‘reset’

8. Click the save button when the pins assignments have been entered. When the Bus Delimiter
window comes up, make sure “XST Default: <>” is selected and press “OK”. Close the
Xilinx PACE program

9. Plug the Spartan 3E board into your computer and turn the board’s power on. Expand the
 “Generate Programming File” process in the Processes window and double click “Configure
Device (iMPACT).

10. All the processes will run (this may take a minute or two). Ignore the warning on the
“Implement Design” process. When all the processes have finished, iMPACT will start.
Select the top radio button and click “Finish”.

11. iMPACT will run a boundary scan that will appear in the ISE workspace. Assign count.bit to
the FPGA (xc3s500e) and bypass the other two devices.

12. Highlight the FPGA icon, right click the white space inside the ISE workspace, and select
“Program…” Click “OK” on the Programming Properties window

13. The Spartan board should now be programmed. lose iMPACT by closing the “Boundary
Scan” in the ISE workspace (do not save changes when prompted).
 EXPERIEMENT NO. 1
HDL CODE TO REALIZE ALL THE LOGIC GATES

AIM: Perform the Simulation of all the logic gates written in behavioral and dataflow style in
Verilog using a Test bench. then, Synthesize each one of them using EDA tool.

EDA Tools used:

1) Xilinx Project Navigator 9.2i

Block Diagram:
Verilog Code (In different modeling styles):

And Gate (In Dataflow, behavioral Modeling):

Module andg(a,b,c);
input a,b;
output c;
assign c = a & b; endmodule

Module andg1(a,b,c); input a,b;

always(a,b) begin
if (a==1’b0 or b == 1’b0)
c = 1’b0;
else if (a==1’b0 or b == 1’b1)
c = 1’b0;
else if (a==1’b1 or b == 1’b0)
c = 1’b0;
else if (a==1’b1 or b == 1’b1)
c = 1’b1;
end
endmodule

Or gate(Dataflow, behavioral modeling):

Module org (a,b,c);
input a,b;
output c;
assign c = a | b; endmodule

Nand Gate (In Dataflow modeling):

Module nandg (a,b,c);
input a,b;
output c;
assign c = ~(a & b); endmodule
Nor Gate (In Dataflow modeling):

Module norg (a,b,c);

input a,b;
output c;
assign c = ~(a | b); endmodule

Xor gate(In Dataflow modeling):

Module xorg (a,b,c);

input a,b;
output c;
assign c = a ^ b; endmodule
Module xorg2 (a,b,c); input a,b;
output c;
assign c = (~a & b) | (a & ~b); endmodule

Xnor Gate (In Dataflow modeling):

Module xnorg (a,b,c);
input a,b;
output c;
assign c = ~(a ^ b); endmodule

Test Bench (Applicable to all the logic gates):

module nandg_tst_v;
reg a;
reg b;
wire c;
nandg uut (
); initial begin
a = 0; b = 0;
#100 a = 0; b = 1;
#100 a = 1; b = 0;
#100 a = 1; b = 1;
end
endmodule
Simulation Waveform:

AND Gate:

OR Gate:

NAND Gate:

NOR Gate:
XOR Gate:

XNOR Gate:

Result: Thus the OUTPUT‟s of all logic gates are verified by synthesizing and
simulating the VERILOG code
 EXPERIEMENT NO. 2
DESIGN OF 8-TO-1 MULTIPLEXER/DEMULTIPLEXER
Aim: To implement Multiplexer & Demultiplexer using Verilog HDL

APPARATUS REQUIRED:

 PC with Windows XP
. XILINX 9.2i
 FPGA-SPARTAN-3 KIT
 PARALLEL TO JTAG CABLE

Block Diagram:

8:1Multiplexer

8:1
Multiplexer
A[7:0] MUX OUT

SEL[2:0]

VERILOG HDL Code:

module MUX8TO1(sel, A,B,C,D,E,F,G,H, MUX_OUT);

input [2:0] sel;
input A,B,C,D,E,F,G,H;
input reg MUX_OUT;
always@(A,B,C,D,E,F,G,H,sel)
begin
case(sel)
3'd0:MUX_OUT=A;
3'd1:MUX_OUT=B;
3'd2:MUX_OUT=C;
3'd3:MUX_OUT=D;
3'd4:MUX_OUT=E;
3'd5:MUX_OUT=F;
3'd6:MUX_OUT=G;
3'd7:MUX_OUT=H;
default:; // indicates null
endcase
end
endmodule

VERILOG HDL Test Bench:

module mux81_tst_v;
reg [7:0] a;
reg [2:0] s;
wire c;
mux81 uut ( .a(a), .s(s), .c(c) );
initial begin
a = 8'b10100101; s = 3'b000; #100 s = 3'b001; #100 s = 3'b101; #100 s = 3'b101;
#100 s = 3'b111; end
endmodule

Simulation Waveform:

Result: Thus the OUTPUT‟s of Multiplexer is verified by synthesizing

and simulating the VERILOG code

Demultiplexer:
Block diagram:

Truth table:
VERILOG VHDL CODE:

module 1_8_DEMUX(
    input i,
    input s2, s1, s0,
    output [7:0]out 
    );
reg [7:0]out;
always @ (i or s0 or s1 or s2)

case ({s2,s1,s0})
    0: out0 = i;
    1: out1 = i;
    2: out2 = i;
    3: out3 = i;
    4: out4 = i;
    5: out5 = i;
    6: out6 = i;
    7: out7 = i;
    default: out = 8'bxxxxxxx;
endcase
endmodule

//Testbench code for 1 to 8 DEMUX (DeMultiplexer)

Behavioral Modelling using Case Statement

initial begin
// Initialize Inputs 
i = 1;s2 = 0;s1 = 0;s0 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#100; s2=0; s1=0; s0=1;
#100; s2=0; s1=1; s0=0;
#100; s2=0; s1=1; s0=1;
#100; s2=1; s1=0; s0=0; 
#100; s2=1; s1=0; s0=1; 
#100; s2=1; s1=1; s0=0; 
#100; s2=1; s1=1; s0=1;  
end
initial begin 
#100;
$monitor(“I=%b, s2=%b, s1=%b, s0=%b, out=%b”, I, s2,
s1, s0, out);
end
endmodule 
Simulation Waveform:

Result: Thus the OUTPUT‟s of deMultiplexer is verified by

synthesizing and simulating the VERILOG code
 EXPERIEMENT NO. 2
DESIGN AND SIMULATION OF FULL ADDER

AIM: Perform Simulation of 1-bit Full adder written in behavioral, dataflow and
structural modeling style in VERILOG HDL using a Test bench. Then, Synthesize
each one of them using EDA tool.

APPARATUS REQUIRED:

 PC with Windows XP
. XILINX 9.2i
 FPGA-SPARTAN-3 KIT
 PARALLEL TO JTAG CABLE

BLOCK DIAGRAM:

Truth Table for Full Adder:

VERILOG HDL Code:

Full Adder (Using dataflow, Behavioral Modeling, Structural Modeling):

module fa(a, b, cin, sum, cout);

input a,b, cin;
output sum, cout;
assign sum = a ^ b ^ cin;
assign cout = (a& b) |(b & cin) |(a & cin);
endmodule

module fa1(a, b, cin, sum, cout);

input a,b, cin;
output sum,cout;
reg sum,cout;
always @(a or b or cin) begin
({a,b,cin})
3'b000: begin sum = 1'b0; cout = 1'b0; end
3'b001: begin
sum = 1'b1; cout = 1'b0; end
'b010: begin
sum = 1'b1; cout = 1'b0; end
3'b011: begin
sum = 1'b0; cout = 1'b1; end
3'b100: begin
sum = 1'b1; cout = 1'b0; end
3'b101: begin
sum = 1'b0; cout = 1'b1; end
3'b110: begin
sum = 1'b0; cout = 1'b1; end
3'b111: begin
sum = 1'b1; cout = 1'b1; end
default: begin
sum = 1'b0; cout = 1'b0; end
endcase end
endmodule

module fa2(a, b, cin, sum, cout);

input a, b, cin;
output sum,cout;
wire w1, w2, w3;
ha ha1 (.a(a), .b(b), .s(w1), .co(w3) );
ha ha2 (.a(w1), .b(cin), .s(sum), .co(w2) );
org org_i (.a(w2), .b(w3), .c(cout) );
endmodule

VERILOG HDL Test Bench:

Full Adder:

module fa_tst_v;
reg a, b cin;
wire sum, cout;
fa uut ( .a(a), .b(b), .cin(cin), .sum(sum), .cout(cout) );
initial
begin a = 0; b = 0; cin = 0; #100
a = 0; b = 0; cin = 1; #100
a = 0; b = 1; cin = 0; #100
a = 0; b = 1; cin = 1; #100
a = 1; b = 0; cin = 0; #100
a = 1; b = 0; cin = 1; #100
a = 1; b = 1; cin = 0; #100
a = 1; b = 1; cin = 1;
End
endmodule

Simulation Waveform:

Full Adder:

Result:Thus the OUTPUT‟s of Adder circuits are verified by synthesizing and

simulating the VERILOG code
 EXPERIEMENT NO. 3

Aim: : To implement 8 bit magnitude comparator using Verilog HDL

APPARATUS REQUIRED:

 PC with Windows XP
. XILINX 9.2i
 FPGA-SPARTAN-3 KIT
 PARALLEL TO JTAG CABLE

Block diagram:
Truth table:

Verilog module:
Verilog code for 8-bit magnitude comparator:
1. module magComp ( In1,

2. In2,

3. Gt,

4. Lt,

5. Eq

6. );

7. input [7:0] In1,

8. In2; //The two 8-bit Inputs In1 and In2

9. output Gt,

10. Lt,

11. Eq; //The Outputs of comparison

12. reg Gt,

13. Lt,

14. Eq;

15. always @ (In1 or In2) //Check the state of the input lines

16. begin

17. Gt <= ( In1 > In2 )? 1'b1 : 1'b0;

18. Lt <= ( In1 < In2 )? 1'b1 : 1'b0;

19. Eq <= ( In1 == In2)? 1'b1 : 1'b0;

20. end

21. endmodule
 Verilog test bench:
1. timescale 1ns / 1ps

2. module magComp_tb;

3. // Inputs

4. reg [7:0] In1;

5. reg [7:0] In2;

6. // Outputs

7. wire Gt;

8. wire Lt;

9. wire Eq;

10. // Instantiate the Unit Under Test (UUT)

11. magComp uut (

12. .In1(In1),

13. .In2(In2),

14. .Gt(Gt),

15. .Lt(Lt),

16. .Eq(Eq)

17. );

18. initial begin

19. // Initialize Inputs

20. In1 = 8'b0;

21. In2 = 8'b0;

22. // Wait 100 ns for global reset to finish

23. #100;

24.

25. // Add stimulus here

26. In1 = 8'd8;

27. In2 = 8'd7;

28. #20;

29. In1 = 8'd100;

30. In2 = 8'd120;

31. #20;

32. In1 = 8'd250;

33. In2 = 8'd250;

34. #20;

35. In1 = 8'd0;

36. In2 = -8'd5;

37. #20;

38. In1 = -8'd5;

39. In2 = -8'd5;

40. #20;

41. end

42. endmodule
simulation waveform:

Result: Thus the OUTPUT‟s of 8-bit magnitude comparator is verified

by synthesizing and simulating the VERILOG code
 EXPERIEMENT NO. 4

Design of Enoders and Decoders

Aim: Perform Zero Delay Simulation 2:4 Decoder and 8:3 Encoder in Verilog
HDL using a Test bench. Then, Synthesize on two different EDA tools.

APPARATUS REQUIRED:

 PC with Windows XP
. XILINX 9.2i
 FPGA-SPARTAN-3 KIT
 PARALLEL TO JTAG CABLE

2:4 decoder:

Block Diagram:

Truth Table:

A Y
00 0001
01 0010
10 0100
11 1000
VERILOG HDL Code:

module decoder24 (a,b);

input [1:0] a;
output [3:0]b;
reg [3:0] b;
always @(a)
begin
b[3] = a[1] & a[0]; b[2] = !a[1] & a[0]; b[1] = a[1] & !a[0]; b[0] = !a[1] & !a[0];
end
endmodule

VERILOG HDL Test Bench:

module decoder_tst_v;
reg [1:0] a;
wire [3:0] b;
decoder24 uut ( .a(a), .b(b) );
initial
begin
a = 2'b00; #100 a = 2'b01; #100 a = 2'b10; #100 a = 2'b11; end
endmodule

Simulation Waveform:
DESIGN OF 8-TO-3 ENCODER (WITHOUT AND WITH PRIORITY)

Block Diagram:

VERILOG HDL Code:

Without priority

module encoder(Z7,Z6,Z5,Z4,Z3,Z2,Z1,Z0,en,A0,A1,A2);
input Z7,Z6,Z5,Z4,Z3,Z2,Z1,Z0,en;
output A0,A1,A2;
wire A0,A1,A3;
assign A0 = Z1 | Z3 | Z5| Z7|en;
assign A1= Z2 |Z3 | Z6 | Z7|en;
assign A2 = Z4 | Z5 | Z6 |Z7|en;
endmodule

With Priority
Module priority_encoder(din,dout);
output[2:0]dout;
input  [7:0] din;

always @ (din)
begin
casex (din)
8'b1xxxxxxx : dout=7;
8'b01xxxxxx : dout=6;
8'b001xxxxx : dout=5
8'b0001xxxx : dout=4;
8'b00001xxx : dout=3;
8'b000001xx : dout=2;
8'b0000001x : dout=1;
8'b00000001 : dout=0;
dafault     : dout=3'bx;
endcase
 endmodule

VERILOG HDL Test Bench:

module encoder_tst_v;
reg [7:0] Z;
wire [2:0] A;
encoder uut ( .z(z), .A(A) );
initial begin
#100 $stop; Z = 8'b00000001; #100 Z = 8'b00101010; #100 Z = 8'b00000100;
end
endmodule
Simulation Waveform:

Result: Thus the OUTPUT‟s of encoder(with and without priority) are verified by
synthesizing and simulating the VERILOG code

Exp no 6
 DESIGN OF FLIP FLOP

Aim: Perform Zero Delay Simulation of D flip flop in VERILOG HDL using a
Test bench. Then, Synthesize on EDA tool.

Block Diagram:

VERILOG HDL Code:

D-flip flop:

module dff(d, clk, reset, q);

input d;
input clk; input reset; output q; reg q;
always @(posedge clk or posedge reset) begin
if (reset)
q <= 1'b0; else q <= d;
end
endmodule

VERILOG HDL Test Bench:

module dff_tst_v;
reg d;
clk; reg reset; wire q; dff uut ( .d(d), .clk(clk), .reset(reset), .q(q) );
begin
d = 0; clk = 1; reset = 1;
d = 1; end #20 reset = 0;
#10 d = 0; #20 d = 1; #10 d = 0;
always
#5 clk = ~ clk;
endmodule

Simulation Waveform:

Result: Thus the OUTPUT of Flip Flop are verified by synthesizing and simulating
the VERILOG code

EXP NO 6

4 bit shift registers

Aim: Perform Zero Delay Simulation of SISO, SIPO, PISO shift registers in VERILOG
HDL using a Test bench. Then, Synthesize on EDA tools

BLOCK DIAGRAM:
VERILOG HDL Code:

SISO shift register:

module siso(sin, clk, reset, sout);
input sin, clk,reset;
output sout;
wire w1,w2,w3;
dff abc1 (.d(sin), .clk(clk ),.reset(reset), .q(w1) );
dff abc2 (.d(w1), .clk(clk), .reset(reset), .q(w2) );
dff abc3 (.d(w2), .clk(clk), .reset(reset), .q(w3) );
dff abc4 (.d(w3), clk(clk), .reset(reset), .q(sout) );
endmodule

module siso1(sin, clk, reset, sout);

input sin, clk reset;
output sout;
reg sout, r1,r2,r3;
always @(posedge clk or posedge reset)
begin
if (!reset)
begin
sout <= 1'b0; r1 <= 1'b0; r2 <= 1'b0; r3 <= 1'b0;
end
else
begin
r1 <= sin; r2 <= r1; r3 <= r2; sout <= r3;
end
end
endmodule

SIPO shift register:

module sipo(sin, clk, reset, pout);

input sin, clk, reset;
output [3:0] pout;
dff a1 (.d(sin), .clk(clk ), .reset(reset), .q(pout[0]) );
dff a2 (.d(pout[0]), clk(clk), .reset(reset), .q(pout[1]) );
dff a3 (.d(pout[1]), .clk(clk), .reset(reset), .q(pout[2]) );
dff a4 (.d(pout[2]), .clk(clk), .reset(reset), .q(pout[3]) );
endmodule

PISO SHIFT REGISTER:

module piso(clk,rst,a,q);
input clk,rst;
input [3:0]a;
output q;
reg q;
reg [3:0]temp;
always@(posedge clk,posedge rst)
begin
if(rst==1'b1)
begin
q<=1'b0;
temp<=a;
end
 else
begin
q<=temp[0];
temp <= temp>>1'b1;
end
end
endmodule
VERILOG HDL Test Bench:

Test Bench of SISO:

module siso_tst_v;
reg sin; reg clk; reg reset;
wire sout;
siso uut ( .sin(sin), .clk(clk), .reset(reset), .sout(sout) );
initial begin
sin = 0; clk = 1; reset = 1;
#20 reset = 0; sin = 1'b1; #10 sin = 1'b0; #10 sin = 1'b1; #10 sin = 1'b1;
#40;
end
always
#5 clk = ~ clk;
endmodule

Test Bench of SIPO:

module sipo_tst_v;
reg sin;
reg clk; reg reset;
wire [3:0] pout;
sipo uut ( .sin(sin), .clk(clk), .reset(reset), .pout(pout) );
initial begin
sin = 0; clk = 1; reset = 1; #300
reset = 1'b0; sin = 1'b1;
#100 sin = 1'b0; #100 sin = 1'b1; #100 sin = 1'b1; end
always
#50 clk = ~ clk;
endmodule

Test bench of PISO:

TESTBENCH:
initial
clk=1'b1;
always #10 clk=~clk;
initial begin
rst=1'b1; a=4'b1101;
#300 rst=1'b0;
#200 rst=1'b1;
#200 rst=1'b0;
end
initial
#1000 $stop;
     
endmodule

Simulation Waveform:

SISO:

SIPO:
PISO:

Result: Thus the OUTPUT‟s of Shift registers are verified by synthesizing and
simulating the VERILOG code.
 EXP NO 8

3-BIT SYNCHRONOUS COUNTER

Aim: To write verilog code for synchronous counter circuit and its test bench for
verification, observe the waveform and synthesize the code with technological
library with given Constraints.

Apparatus required:

Cadence

Verilog PROGRAM :

module counter(clk,rst,count);

input clk,rst;

output[2:0] count;

reg [2:0] count;

always@(posedge.clk)

begin

if(rst)

count<=3’b000;

else

count<=count+3’b001;

end

endmodule

test bench:
module counter_tb();

reg clk,rst;
wire[3:0]count;

counter counter_ins(clk,rst,count);

initial

begin

clk=0;

forever #5 clk=~clk;

end

initial

begin

rst=1; #10 rst=0; #70 rst=1; #10 rst=0; $finish

end

endmodule

simulation and waveform:

 EXPERIEMENT NO. 6

DESIGN OF 4 BIT BINARY TO GRAY CONVERTER

Aim: Perform Zero Delay Simulation of Binary to Gray Code Converter in

VERILOG HDL using a Test bench..

Logic Diagram:

VERILOG HDL Code:

module b2g(B,G);
input [3:0]B;
output reg [3:0]G;
always@(B)
begin
G[3]<=B[3];
G[2]<=B[3]^B[2];
G[1]<=B[2]^B[1];
G[0]<=B[1]^B[0];
end
endmodule
VERILOG HDL Test Bench:

module tb_b2g_v;
reg [3:0] B;
wire [3:0] G;
b2g uut (.B(B), .G(G));

initial
B =4'd0;
always #2 B=B+4'd1;
endmodule

Simulation Waveform

Result: Thus the OUTPUT‟s of Binary to Gray converter are verified by

synthesizing and simulating the VERILOG code
 Exp no 9

Parity generator
Aim: Perform Simulation of parity generatorwritten in Gate level modeling
style in VERILOG HDL using a Test bench. Then, Synthesize each one of them
using EDA tool.

Apparatus required:

 PC with Windows XP
. XILINX 9.2i
 FPGA-SPARTAN-3 KIT
 PARALLEL TO JTAG CABLE

Block diagram:

A parity bit is used for the purpose of detecting errors during the
transmission of binary information. A parity bit is an extra bit included
with the binary message to make the number of ones either even or odd.
An error is detected if the checked parity doesn’t correspond with the one
transmitted.
Truth table:

The circuit that generates the parity bit is called parity generator. So with
this explanation, let us design an even  parity generator. Here is the truth
table of an even parity generator.

As seen from the truth table, in this even parity generator,  if the number
of 1’s in the input are odd, the output is 1 making the total numbers of
‘1’ be even.  If the number of 1’s in input is even, the output is 0 since
the number of input ‘1’ is already even.  By closely observing the truth
table, it can be understood that the output is a mere XOR of input bits.
The three bits in the message, together with the parity bit are transmitted
to their destination, where they are applied to a parity checker circuit to
check for possible errors.
VERILOG CODE:

module parity(

input x,y,z,

output result);

xor (result,x,y,z);  // SIMPLE XOR OPERATION : Gate Level

Modeling
endmodule

TEST BENCH:
initial begin

// Initialize Inputs

x = 0;

y = 0;

z = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

x = 0;

y = 0;

z = 1;

// Wait 100 ns for global reset to finish

#100;

x = 0;

y = 1;

z = 0;

// Wait 100 ns for global reset to finish

#100;

x = 0;

y = 1;

z = 1;

// Wait 100 ns for global reset to finish

#100;

x = 1;
y = 0;

z = 0;

// Wait 100 ns for global reset to finish

#100;

x = 1;

y = 0;

z = 1;

// Wait 100 ns for global reset to finish

#100;

x = 1;

y = 1;

z = 0;

// Wait 100 ns for global reset to finish

#100;

x = 1;

y = 1;
z = 1;

// Wait 100 ns for global reset to finish

#100;

end

endmodule

OUTPUT:

Result: Thus the OUTPUT‟s of parity generator are verified by synthesizing and
simulating the VERILOG code
 EXPERIEMENT NO. 9
SEQUENCE DETECTOR

Aim: Perform Zero Delay Simulation of Sequence Detector (Moore and Mealy
state machines ) in VERILOG HDL using a Test bench. Then, Synthesize on EDA
tools.

Apparatus required:

 PC with Windows XP
. XILINX 9.2i
 FPGA-SPARTAN-3 KIT
 PARALLEL TO JTAG CABLE
Block diagram:

Moore Machine

VERILOG HDL CODE:

module fsm( clk, rst, inp, outp);
input clk, rst, inp;
output outp;
 reg [1:0] state;
reg outp;

always @( posedge clk, posedge rst )

begin
if( rst )
state <= 2'b00;
else
begin
case( state )
2'b00:
begin
if( inp ) state <= 2'b01;
else state <= 2'b10;
end
2'b01:
begin
if( inp ) state <= 2'b11;
else state <= 2'b10;
end
2'b10:
begin
if( inp ) state <= 2'b01;
else state <= 2'b11;
end
2'b11:
begin
if( inp ) state <= 2'b01;
else state <= 2'b10;
end
endcase
end
end
always @(posedge clk, posedge rst)
begin
 if( rst )
outp <= 0;
else if( state == 2'b11 )
outp <= 1;
else outp <= 0;
end
endmodule

VERILOG HDL TEST BENCH:

module fsm_test;
reg clk, rst, inp;
wire outp;
reg[15:0] sequence;
integer i;
fsm dut( clk, rst, inp, outp);
initial
begin
clk = 0;
rst = 1;
sequence = 16'b0101_0111_0111_0010;
#5 rst = 0;
for( i = 0; i <= 15; i = i + 1)
begin
inp = sequence[i];
#2 clk = 1;
#2 clk = 0;
$display("State = ", dut.state, " Input = ", inp, ", Output = ", outp);

end
test2;
end
task test2;
for( i = 0; i <= 15; i = i + 1)
begin
inp = $random % 2;
 #2 clk = 1;
#2 clk = 0;
$display("State = ", dut.state, " Input = ", inp, ", Output = ", outp);

end
endtask
endmodule

Simulation Wave form:

Mealy Machine:

VERILOG HDL PROGRAM:

module mealy( clk, rst, inp, outp);
input clk, rst, inp;
output outp;
reg [1:0] state;
reg outp;
always @( posedge clk, posedge rst ) begin
if( rst ) begin
state <= 2'b00;
outp <= 0;
end
else begin
case( state )
2'b00: begin
if( inp ) begin
state <= 2'b01;
outp <= 0;
end
else begin
state <= 2'b10;
outp <= 0;
end
 end

2'b01: begin
if( inp ) begin
state <= 2'b00;
outp <= 1;
end
else begin
state <= 2'b10;
outp <= 0;
end
end

2'b10: begin
if( inp ) begin
state <= 2'b01;
outp <= 0;
end
else begin
state <= 2'b00;
outp <= 1;
end
end

default: begin
state <= 2'b00;
outp <= 0;
end
endcase
end
end
endmodule
VERILOG HDL TEST BENCH:

module fsm1_test;
reg clk, rst, inp;
wire outp;
reg[15:0] sequence;
integer i;
mealy dut( clk, rst, inp, outp);
initial
begin
clk = 0;
rst = 1;
sequence = 16'b0101_0111_0111_0010;
#5 rst = 0;

for( i = 0; i <= 15; i = i + 1)

begin
inp = sequence[i];
#2 clk = 1;
#2 clk = 0;
$display("State = ", dut.state, " Input = ", inp, ", Output = ", outp);

end
test2;
end
task test2;
for( i = 0; i <= 15; i = i + 1)
begin
inp = $random % 2;
#2 clk = 1;
#2 clk = 0;
$display("State = ", dut.state, " Input = ", inp, ", Output = ", outp);
end
endtask
endmodule
Simulation Wave form

Result: Thus the OUTPUT‟s of Sequence Detector using Mealy & Moore
Machines are verified by synthesizing and simulating the VERILOG code
EXPERIMENT NO 3