Notes for Digital VLSI Design with Verilog, 2nd edition

Course Notes and Errata

for the Second Edition of

Digital VLSI Design with Verilog

A Silicon Valley Polytechnic Institute Advanced Course

by John Michael Williams

[email protected]
2015-08-08

Copyright 2015, John Michael Williams.

Licensed free to Silicon Valley Polytechnic Institute for training-course use. All
other rights reserved.

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Notes for Digital VLSI Design with Verilog

Standards Cited
The primary verilog references in the Textbook and this Note Book are to IEEE Verilog
Std 1364-2005, with additional references to the IEEE SystemVerilog Std 1800-2012.
Except for (a) inclusion of existing C or C++ code, or (b) complex assertion composition,
SystemVerilog and Verilog 2005 differ very little. In some of the SystemVerilog citations,
the reader will find additional features not present in the Verilog 2005 references.
SystemVerilog is discussed in some detail in the final lecture of the Textbook.

Second Edition Changes

The second edition is available from Springer as of the first day of July 2014:
Digital VLSI Design with Verilog
A Textbook from Silicon Valley Polytechnic Institute

By Williams, John Michael

2nd ed. 2014, xvi + 553 pp. 273 illus., 116 illus. in color.
Available formats: eBook, hardcover
$139.00 (net) price in USA
ISBN 978-3-319-04788-1
Free shipping from Springer for individuals worldwide

Here is a brief summary of the changes made in the second edition, some of which were
posted as errata or supplements to the First Edition version of these Notes:
First of all, all minor typographical errors have been corrected, as have been several
other errors newly discovered in the text and figures.
Major upgrades in the second edition are:
Expanded Day 1 presentation making it more useful to verilog beginners
Dozens of new figures
Expansion or clarification of explanations on almost every page
Upgrade of the simulation figures to be in color
New coverage of the features of SystemVerilog and VerilogA/MS
A new summary introduction to each chapter and lab exercise
IEEE Stds references which include SystemVerilog as well as verilog
A new, optional lab checklist for recording course learning progress.

Course Description
When given in a classroom context, this course of hands-on study is intended to be
presented over a twelve week period, assuming up to twelve hours of lecture, reading,
study, and interactive application per week. The intent is to present the design of digital
integrated circuits, using the verilog digital design language, in its entirety, as described
in IEEE Standard 1364 (2005) and in the SystemVerilog Std 1800 (2012).

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Notes for Digital VLSI Design with Verilog

For independent readers, the Textbook may be read and understood without use of a
logic simulator, but much of the value of the daily exercises depends upon access to one.
Lack of access to a logic synthesizer also is a disadvantage, but it is far less crucial than
simulation to a good learning of verilog.
In this course, by a balanced mixture of lectures and labs, the student is introduced to
language constructs in a progressively more complex project environment. During the
course, classroom students are familiarized with the use of the Synopsys Design
Compiler to synthesize gate-level netlists from behavioral, RTL, and structural Verilog
code. The synthesis constraints most useful for area and speed optimization are
emphasized. Almost all the class project work is done in the synthesizable subset of the
language; logic simulation is treated as a verification method in preparation for
synthesis.
The Synopsys VCS simulator, or optionally [tbd] the Mentor QuestaSim simulator,
will be used in class. The majority of the labs are small enough to be worked with the
demo-limited Silos simulator which comes on the CD-ROM included with the older
Thomas and Moorby or Palnitkar supplementary textbooks cited in the required
Textbook. However, it is recommented that the new user instead obtain a more
functional simulator such as may be available at a place of work or (for students) free
from Aldec.
Classroom instruction in simulation tools will be provided but is minimal in this
course, which is focussed on the verilog language and on those constructs permitting logic
synthesis. As of 2014, the author is not aware of any good synthesis tool other than one
which may be available at very considerable expense or at a place of work.
In addition to the language, its simulation and synthesis, the course topics of the
Textbook include design partitioning, hierarchy decomposition, safe coding styles,
assertions as designer aids, and design for test.

Course Topic List (partial):

Lecture and Lab: Modules and hierarchy; Blocking/nonblocking assignment;
Combinational logic; Sequential logic; Behavioral modelling; RTL modelling;
Gate-level modelling; Hardware timing and delays; Verilog parameters; Basic
system tasks; Timing checks; Generate statement; Simulation event scheduling;
Race conditions; Synthesizer operation; Synthesizable constructs; Netlist
optimization; Synthesis control directives; Verilog influence on optimization; Use
of SDF files; Test structures; Error correction basics; SystemVerilog and
VerilogA/MS summaries.
Hands-on Projects: Shift and scan registers; counters; memory and FIFO
models; digital phase-locked loop (PLL); serial-parallel (and v-v) converter;
serializer-deserializer (serdes); primitive gates; switch-level design; netlist backannotation.

Prerequisites
Best preparation would be a bachelor's degree or equivalent experience in electrical
engineering, including digital design experience, coupled with familiarity with

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Notes for Digital VLSI Design with Verilog

programming in a modern language such as C. Working familiarity with verilog would

be good equivalent -- or supplementary -- experience.

Class Organization and Materials

As given in class, the course is intensively hands-on: There will be 12 weeks of
instruction, two 3-hour lecture meetings per week, for a total of 72 hours in class, plus
another 4 hours per week of mandatory lab. The classroom instructor will be present for
a minimum of 2 of the 4 hours per week of mandatory lab. Attendance will be taken on
all these days, which total more than 110 hours over the twelve weeks of the course.
Many of the lab exercises will be held during lecture meeting time; others will be
scheduled or continued in the dedicated lab time.
A brief quiz will be held on every lecture day except during the first and last weeks;
and, there will be a final exam. Homework will be assigned as described in the Textbook
lectures. During the course, students will be allowed as much additional access to
training computers as they require for course study, homework, or labs.

Required Textbook
The Textbook for this course is Digital VLSI Design with Verilog (see citation below).
The Textbook contains explanations, homework readings, and all the lab instructions.
The Springer Extras web side provides for download of the lab setup and of all problem
and homework solutions.
For instructional reasons, it is not recommended that you purchase only a PDF edition
or eBook of the Textbook for this course; you will want a hard copy anyway, to take
marginal notes; and, viewing it on-screen will make your lab work much more difficult
than if you had the capacity to page through a book independent of what your computer
was doing. If you did get a PDF edition, you could read it on your own laptop computer
during lecture or lab, but you will not be permitted access to any computer during the
(open-book) final exam, so notes or PDF in your computer will be unavailable.

Textbook Extras
Page two of the Textbook briefly suggests how to use the contents of the Extras which
accompany it. The Extras include working setups and answers to all Textbook problems
and additional information about simulation and synthesis. As a suggestion, a good
working environment in which to organize the contents of the Extras would be set up as
shown in the following figure:

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Notes for Digital VLSI Design with Verilog

If you create the DC and VCS directories as suggested in the above figure, you will have
used everything in the Extras misc directory, so you will not need a misc directory in
your working environment.
In the exercise answers, many of the later Labxx subdirectories include a zero-length
file or link named tcbn90ghp_v2001.v. These files were zeroed to reduce the space
occupied by the answer Extras. Whenever you encounter a zero-length file named
tcbn90ghp_v2001.v, you should link it or replace it with a full-length version from your
VCS directory (see above) or from the misc data directory of your Extras.
The _vimrc file in the Extras misc directory is a convenient startup file for the vim
text editor, which is the recommended text editor for verilog. The _vimrc file should be
renamed to .vimrc and moved or copied to your home directory ("~"), if you are running
Linux or Unix. If you are running Windows, _vimrc should be moved or copied to the
startup directory which you have configured for vim.

Course Note Book

The Course Note Book mostly is a hardcopy printout of these Notes provided to each
attendee; it may be used as an aid to the taking of notes during lecture. Bring your
Course Note Book and Textbook to every class and lab. Always read the lab instructions
in the Textbook at least once before the day on which the lab is scheduled. The Note
Book daily data list initially (July 2014) is almost empty but will be updated as necessary
during the course to accommodate additional lecture material or Textbook corrections.

Class Attendance
Commitment to attendance at all lectures and labs is advised: This course is not an
easy one; any missed mandatory session should be made up as soon as possible. The
school provides for as many as three makeup lecture sessions during the course; and, a
total of two missed sessions (lecture or lab), not made up, is allowed. Attendance not
meeting these criteria means that a certificate will not be granted.

Proprietary Information and Licensing Limitations

This Course Note Book and the Textbook include no proprietary information beyond its
copyright by the present author. However, during the classroom presentation of the
course, students will be exposed to features of the Synopsys and Mentor Graphics tools
which may be considered proprietary in other ways. Proprietary information generally

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Notes for Digital VLSI Design with Verilog

may include anything provided to users directly by the manufacturer. In addition,

licensing provisions may limit republication of specific performance details. To avoid
including such information in the Course Note Book, and to make the Course Note Book
as portable among different vendor tools as possible, the following approach has been
adopted:
VCS: Almost all options convenient to run the VCS simulator are entered manually
according to a separately-distributed sheet, or are set up in a shell command alias. The
lab exercise answers and exercises generally are compatible with Aldec's or any other
vendor's simulator. However, the later lab exercises will be too big to be run on the
limited-capacity demo version of Silos provided with the older supplementary textbooks
named in the References.
Design Compiler: Instruction on the operation of the DC synthesizer will be
presented almost entirely in lab; a handout sheet will be provided with a summary of
invocation options and synthesis constraints. Students may use these constraints in
their lab work as will be explained by lab instructions during the course.
QuestaSim: This Mentor Graphics tool, formerly named ModelSim, may be available
in the future upon student request; if so, information on its operation will be provided on
a separate handout sheet.

Proprietary Restrictions
Publishing of operational performance details of VCS, Design Compiler, or QuestaSim
may require written permission from Synopsys or Mentor, and students are advised not
to copy, duplicate, post or publish any of their work showing specific tool properties
without verifying first with the manufacturer that trade secrets and other proprietary
information have been removed. This is a licensing issue unrelated to copyright, fair
use, or patent ownership.
The same applies to the TSMC library files available for viewing by classroom
attendees but not distributed. These front-end libraries are designed for synthesis,
floorplanning, and timing verification and may contain trade secrets of TSMC or
Synopsys. Do not make copies of anything from the TSMC libraries, including TSMC
documentation, without special permission from TSMC and Synopsys.
The verilog simulation models in the files, LibraryName_v2001.v, are copyrighted but
not otherwise proprietary and are available for copying, study, or modification in the
context of this course. These models are simple but somewhat inaccurate; they are
intended for training use, only, and they never should be used for design work.
Verilog netlists produced by the synthesizer are not proprietary, although the Liberty
library models compiled for use by the synthesizer are proprietary and owned by
Synopsys. Evaluations of netlist quality in association with mention of Synopsys or
Design Compiler may be considered proprietary and should not be published or
distributed without special permission. The timing in back-annotated netlists may be
considered proprietary by Synopsys or TSMC.
Bottom line: Use what you know and understand, not what you copy.

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Notes for Digital VLSI Design with Verilog

Textbook
Williams, J. M. Digital VLSI Design with Verilog (2nd edition). Springer, 2014. This is
the required textbook and lab exercise book for the course.
ISBN: 978-3-319-04788-1; eBook ISBN: 978-3-319-04789-8.

Course Grading Policy

Completion of the course with a passing score of 65% or above means award of a
Certificate of Achievement; otherwise, a Certificate of Attendance may be awarded if no
more than 2 of the 36 scheduled meetings were missed. The score is a weighted sum of
quiz score plus final exam score, with quiz weighting as below.

Quizzes
There will be a quiz every scheduled lecture day, except during the first and last weeks
of the course. The total of 20 quizzes primarily are meant to be instructional.
Generally, quizzes will include material presented in the current or most recent lab or
lecture.
Each quiz will be brief, about 15 minutes, and will count 10 points, for a total of 200
points over the whole course. Quizzes are teaching as well as testing instruments, so
poor performance on quizzes need not mean very much for an enrollee's final status.
No makeup will be allowed for any missed quiz.
Quiz weighting rule: Round the quiz average percent up to the next 10%; then, for
every 10% above 50%, or any quiz missed, add 1% to the baseline 5% weight of the
quizzes.
Examples:
1. An enrollee takes every quiz and averages 95%: 95 --> 100. The quizzes
therefore equal 5% + 5 x 1% = 10% of the total course score. The final exam
contributes 90%.
2. Every quiz is missed: 0 --> 0. The 0% quiz average will be weighted as 5% + 20
x 1% = 25% of the total course score. The final exam contributes 75%.
3. Every quiz is taken and the quiz average is 34%: 34 --> 40. The 34% quiz
average then contributes 5% of the total course score.
4. 1 quiz is missed and the quiz average is 65%: 65 --> 70. Then, the 65% counts
as 5% + 2 x 1% + 1 x 1% = 8% of the total course score.

Final Exam
The final exam will be a two-hour, open-book comprehensive exam scheduled after the
final class lecture day of the course. The exam will be paper-and-pen; no electronic
assistance. Enrollees will be expected to answer content-related questions and to code
verilog. More details on the final exam are below, in the Week 12 Class 1 notes. A
makeup may be taken for the final, if the scheduled final exam should be missed for good
reason.

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Notes for Digital VLSI Design with Verilog

Quiz or Exam Information Sharing

All enrollees or others exposed to the course are on their honor not to share any
content (questions or answers) of any quiz or exam with anyone.

Getting Ready for Class Attendance

Before doing anything else,
1. Use the below "Errata" in these Notes to fix all Textbook errors.
2. Use the "Supplementary" material below in these Notes, if any, to update
your reading of the various parts of the Textbook indicated.
Modification of the Textbook may be done with stick-on notes, or by writing corrections
on the Textbook pages.
If you are attending the course, it is strongly recommended to read each
Textbook class lecture and lab at least once before the scheduled day.

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Notes for Digital VLSI Design with Verilog

Textbook Errata (Second Edition)

Updates and additional explanations for content not appearing in the course Textbook.
are among the daily chapter headings below.
----------------------------------------The known Textbook minor errors are as follows (underlines are for error emphasis and
should be omitted from corrected text):
1. p. 27, last sentence in Module Header first paragraph: In "... less repetitive that the
older ...", "that" should be than.
2. p. 46, second to last paragraph, 3rd sentence: In "... being expressable as ...",
"expressable" should be expressible.
3. p. 74, first "Asynchronous controls" code example: All the controls below the first "if"
should be moved one space to the left.
4. p. 102, figure 5-10: The wire between the Clock Comparator and the VFO should be
named "AdjustFreq", not "AdjFreq".
5. p. 130: On the first line of Step 5, the comma (",") after the word port should be a
period (".").
6. p. 180: In the first line of the "Note" following figure 8-10, "... FindPattern , ..." has
its second comma (",") spaced too far. It should be "... FindPattern, ...".
7. p. 228: In the Lab 12 answers, Step 1, The "SchedDelayA: First rise a = t 5" solution
should be "a = t 4", not "5".
8. p. 247: In the line introduced by "repeat.", the comma in "(number_of_times) , "
should not be spaced. The line should be, "(number_of_times), ".
9. p. 293: In the second line on this page, "Week 2 , Class 2" should not include a comma
(",") and should have been written as "Week 2 Class 2".
10. p. 296: In Lab Step 1, second line, the reference to "section 14.1.1.1" should be to
"section 14.1.1".
11. p. 301: In the Today's Agenda Summary, 3rd line, "... and-three-value ...", one "-"
should be a space: Thus, "... and three-value ...".
12. p. 408: The fifth line on this page should be expanded slightly to read, "permit
almost-correct synthesis, which ...".
,

13. p. 478: In the second to last paragraph, "LFSR 's" includes an extraneous comma (' ').
It should be, "LFSR's".
14. p. 495: The final sentence in the bottom paragraph ("Simplification C") is missing a
to: It should read, "... A and B correspond to two distinct ...".

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Notes for Digital VLSI Design with Verilog

10

-------------------------------------------------------------------------------------------------The by-chapter large-scale errata and supplementary information are as follows:

Week 3 Class 2
p. 135, figure 7-2: This figure is incorrect and is just a second copy of the binary upcounter of Fig. 7-1. The correct Fig. 7-2 one-hot counter should be as shown here:

Fig. 7-2. One-hot up-counter. Two bits switch on every

count.

Week 5 Class 2
In general, on pp. 237-238, the descriptions of latching (flip-flop behavior) are reversed
for D = 1 vs. D = 0:
p. 237, figure 11-5 caption: Should say ". . . but only when D is '1'."
p. 237, truth-table just below figure 11-5: The Time 4 value should be "4 1 1 0 1".
p. 237, The second sentence from the bottom should say, ". . . but only when the data
input is at '1'."
p. 237, The last sentence should say, "To make this work for data input '0', . . ."; and, the
final figure caption should say, ". . . when D is '0'."
p. 238, truth-table following figure 11-6: The Time 4 value should be "4 0 1 1 0 1".

Week 12 Class 1
Scope of the Final Exam
Conditions. This will be a two-hour open-book exam held in the lab or class room:
The Course Note Book, Textbook, or any other hardcopy (including handwritten)
materials will be allowed.

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Notes for Digital VLSI Design with Verilog

11

All exam work must be strictly individual. No consultation with anyone, or access to
any electronic device (including a cell phone or other computer) will be permitted. If you
answer 9-1-1 calls on your cell phone in your spare time, get someone to substitute for
you on these calls during the exam.
Subject Matter. This examination is meant to ensure that the student has learned
enough from the course to come up to speed on a verilog-based engineering project with
no ramp-up delay attributable to familiarity with the language.
Topics which may be tested include correct entry of verilog modules in ANSI and
traditional header format, and behavioral or RTL design of simple devices such as
counters, shift registers, decoders, or combinational elements.
Implementation of hierarchical designs, including parameter passing and generate,
may be tested, as may be correct structural connection of simple component instances.
Assignment of delays and understanding of the verilog simulator event queue will be
assumed and may be tested. Use of assertions, timing checks, and assignment of delays
to internal paths in specify blocks may be tested.
A synthesis problem may be presented; and, if so, the student may be required to
provide a solution describing correct use of Design Compiler to improve a result.
The exam may include any other material which has been presented at least on two
occasions during the lectures or labs, or in two or more chapters in the Textbook.
The exam will include questions based on verilog, only: Nothing specific to
SystemVerilog or Verilog A/MS will be included.