Verilog SAP

Verilog HDL -Introduction
Ref: Verilog – HDL by samir palnitkar 2nd Edition

VLSI Companies in India
□ Mentor Graphics India Pvt Ltd (Bengaluru/ Bangalore)
□ Intel Technology India Pvt Ltd (Bengaluru/Bangalore )
□ Cadence Design Systems India Pvt Ltd (Bengaluru/Bangalore )
□ Synopsis
□ Xilinx India Technology Services Pvt Ltd
(Hyderabad/Secunderabad )
□ Qualcomm Inc (Bengaluru/Bangalore )
□ Synaptics Incorporated (Hyderabad/Secunderabad )
□ Nvidia Corporation (Bengaluru/ Bangalore)
□ Cypress Semiconductors India Pvt Ltd (Bengaluru/ Bangalore)
□ Hewlett Packard
□ Infineon Technologies Pvt Ltd (Bengaluru/Bangalore )
□ SEAGATE TECHNOLOGY PLC (Pune )
□ Honeywell International Inc. (Hyderabad/ Secunderabad)
□ QLogic Corporation (Pune)
□ Broadcom Corporation (Bengaluru/Bangalore )
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□ Cisco Systems Inc. (Bengaluru/Bangalore )
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□ Orange Semiconductors Pvt ltd (Bengaluru/ Bangalore)
□ Microchip Technology India Pvt Ltd (KARNATAKA)
Opportunities in VLSI Industry
□ VHDL,Verilog-Digital Design Engineer
□ Dev Solutions (Bengaluru/Bangalore )
□ Architecting/ micro- Architecture of digital design for SOCs and
sub-systems. RTL coding ( Verilog/ VHDL), Working on technologies
like DSL, WLAN,
□ RTL Design Engineer
□ Soft Machines (Hyderabad/Secunderabad )
□ Job Description Participate and own micro-architecture, design,
development state-of-the-art SoC blocks.
□ System Performance Modeling Architect
□ enterprise solutions group (Hyderabad/Secunderabad )
□ Responsibilities:1. Performance modeling and simulation. Requires both
infrastructure development and analysis.
□ IP verification Lead
□ Intel Technology India Pvt Ltd (Bengaluru/Bangalore )
□ IP Logic Design Lead
□ Intel Technology India Pvt Ltd (Bengaluru/Bangalore
□ SENIOR VERIFICATION ENGINEER

□ Nvidia Corporation (Bengaluru/ Bangalore)
□ MINIMUM REQUIREMENTS:- BS / MS with 5+ years of experience-
□ Staff Verification Engineer
□ Synaptics Incorporated (Hyderabad/Secunderabad )
□ Responsibilities:Develop verification testbench components for
chip/module level using System Verilog, C & PerlUse high level
language concepts.
□ R&D Engineer IC Design 3
□ Avago Technologies (Bengaluru/Bangalore )
□ B.E/B.Tech/M.E/M.Tech in Electronics/VLSI Engineering with strong
6-10 years of experience in custom silicon development, deep
submicron place & r...
□ ASIC- Ultra Low Power Architect
□ CLIENT OF ROLAND & ASSOCIATES (Bengaluru/Bangalore )
□ Job DescriptionOur client is looking for ASIC Signal Architect to join
their exclusive team in Bangalore.
□ Synthesis Engineers
□ ONS search (Bengaluru/ Bangalore)
□ Responsibilities:The responsibility of this position is to support ASIC
from RTL to silicon with focus on synthesis and formal verification.
□ Sr Staff Engineer ASIC Verification
□ SEAGATE TECHNOLOGY PLC (Pune )
□ Work with other Seagate engineers across multiple sites to verify IP
and SoCs for use in high-volume storage devicesDevelopment of
random constrained ...
Advantages of Verilog HDL
• Easy to learn and easy to use.

• Allows different levels of abstraction to be mixed in
the same model
• Most of logic synthesis tools support Verilog HDL.
• All fab. vendors provide Verilog HDL libraries for postlogic
synthesis simulation
• PLI – Programming Language Interface.
Module- Basic building block
A module can be an element or collection of low level design

blocks
Levels of Abstraction-1
□ Switch Level: Module implemented
with switches and interconnects.
Lowest level of Abstraction
□ Gate Level: Module implemented in

terms of logic gates like (and ,or) and
interconnection between gates
Levels of Abstraction-2
□ Dataflow Level: Module designed by
specifying dataflow. The designer is aware
of how data flows between hardware
registers and how the data is processed in
the design
□ Behavioral Level :Module can be
implemented in terms of the desired design
algorithm without concern for the hardware
implementation details. Very similar to C
programming
Hierarchical Modeling Concepts
Top level block
Sub-bloc Sub-bloc Sub-bloc Sub-bloc

k1 k1 k1 k1
Leaf Leaf Leaf Leaf Leaf Leaf Leaf Leaf

cell cell cell cell cell cell cell cell
Hierrarchy
Basic Concepts
□ Number is specified as
<size>'<baseformat><number>
Contd.
□ Verilog’s nets and registers hold four-valued data
□ 0, 1
■ Obvious
□ Z
■ Output of an undriven tri-state driver
■ Models case where nothing is setting a wire’s
value
□ X
■ Models when the simulator can’t decide the value
■ Initial state of registers
■ When a wire is being driven to 0 and 1
simultaneously
■ Output of a gate with Z inputs
Basic Conventions
□ Verilog is case sensitive

– Keywords are in lowercase
□ Extra white space is ignored
– But whitespace does separate tokens
□ Comments
– One liners are //
– Multiple lines /* */
– Comments may not be nested
Nets
□ Nets represent connections between
hardware elements. Just as in real circuits,
nets have values continuously driven on
them by the outputs of devices that they
are connected to.
Module
Input
Circuit
X Wire
Y Output
Z
O
Module
Input
Circuit
X Wire
Y Output
Z
O
Module
name
module sample (X,Y,Z,O);
input X,Y,Z;
output O;
// Describe the circuit using logic symbols

assign O = (X^Y)&Z;
endmodule
Registers
□ Registers represent data storage elements.
Registers retain value until another value is
placed onto them.
□ In Verilog, the term register merely means
a variable that can hold a value.
□ Unlike a net, a register does not need a
driver.
Vectors
□ Arrays of Regs and Nets
Integers and Parameters
Ports
□ Ports provide interface for by which a
module can communicate with its
environment
Module
Port connection rules
Illegal Port connection
□ Module top;
//declare connection variables
reg [3:0] A, B;
reg C_in;
reg [3:0] sum;
wire C_out;
//instantiate fulladd4
fulladd4 fa0(SUM,C_OUT,A,B,C_IN);
//illegal connection
.
.
.
.
.
endmodule
Example
Connecting Ports
□ Suppose we have a module
Switch Level Modeling
□ Ability to design at MOS – transistor
(Switches) level.
■ nmos n1 (out, data, control);
■ pmos m1 (out, data, control);
■ cmos c1 (out, data, ncontrol,mcontrol);
□ Bidirectional Switches
■ tran t1 (inout1, inout2);
■ tranif0 t1 (inout1, inout2, control);
■ tranif1 t1 (inout1, inout2, control);
□ Power and Ground
■ Supply1 vdd;
■ Supply0 gnd;
Gate Level Modeling
□ A logic circuit can be designed by use of
logic gates.
□ Verilog supports basic logic gates as
predefined primitives. These primitives are
instantiated like modules except that they
are predefined in Verilog and do not need a
module definition.
Gate gate_name(out,in1,in2…)
Buf/not gates
□ Buflnot gates have one scalar input
and one or more scalar outputs.
Bufif/notif
Instantiation of bufif gates
Design of 4:1 Multiplexer
Contd..
Stimulus
4 bit full adder
Declaration:
Code contd..
4 bit adder using 1 bit adder
Stimulus
Gate Delays:
□ Rise Delay: Delay associated with a
o/p transition to 1 from any value.
Fall Delay: Delay associated with o/p

transition to 0 from any value.
Turn off Delay: Delay associate with
o/p transition to Z from another
value.
Dataflow Modeling
□ In complex designs the number of gates is very large.
□ Dataflow modeling provides a powerful way to implement a

design.
□ Circuit is designed in terms of the data flow between registers

and how a design processes data.
□ Currently, automated tools are used to create a gate-level

circuit from a dataflow design description. This process is called
logic synthesis
Continuous Assignment
Rules:
□ The left hand side of an assignment must always be a scalar or
vector net
□ It cannot be a scalar or vector register.
□ Continuous assignments are always active.
□ The assignment expression is evaluated as soon as one of the

right-hand-side operands changes and the value is assigned to
the left-hand-side net.
□ The operands on the right-hand side can be registers or nets.
□ Delay values can be specified for assignments in terms of time

units. Delay values are used to control the time when a net is
assigned the evaluated value
Operator Types
Conditional Operator
4:1 Multiplexer Example
Behavioral Modelling – Structured Procedures
Initial Statement
module stimulus
reg x,y,a,b,m;
initial
m = 1’b0;
initial
begin
#5 a=1’b1;
#25 b = 1’b0;
end
initial
begin
#10 x=1’b1;
#25 y = 1’b0;
end
initial
#50 $finish;
endmodule
always ststement
module clock_gen (output clock);

initial
clock = 1’b0;
always
#10 clock = ~clock;
initial
#1000 $finish;
endmodule
Procedural assignments - Blocking statement
reg x, y, z
reg [15:0] reg_a, reg_b;
integer count;
initial
begin
x=0; y=1; z=1;
count = 0;
reg_a = 16’b0; reg_b = reg_a;
#15 reg_a[2] = 1’b1;
#10 reg_b[15:13] ={x,y,z};
count = count +1;
end
NON - Blocking statement
reg x, y, z
reg [15:0] reg_a, reg_b;
integer count;
initial
begin
x=0; y=1; z=1;
count = 0;
reg_a = 16’b0; reg_b = reg_a;
reg_a[2] <= #15 1’b1;

reg_b[15:13] <= #10 {x,y,z};
count <= count +1;
end
NON - Blocking statement to
eliminate Race conditions
//2 concurrent always blocks with blocking statement

always@(posedge clock)
a = b;
b = a;
//2 concurrent always blocks with non – blocking

statement
a <= b;
b <= a;
Case statement
case (expn) case ({s1,s0})

Alt1:statement1; 2’d0 : out =i0;
…. Default: $display(invalid control
signals);
….
Default: default statement;
endcase;
casex
casez
While loop
Initial
Begin
count = 0;
while (count <128)
begin
$display (“count = %d”, count);
count = count +1;
end
end
For loop
Initial
for (count=0; count<128; count = cpunt+1)
$display(“count=%d”, count);
Repeat loop
repeat(64)
Forever loop
Initial
begin
clock = 1’b0;
forever #10 clock = ~clock;
end
Tasks and Function
□ Why??
■ To break up large behavioral designs into
smaller pieces.
□ Task
■ May have zero or more arguments of type
input, output or inout.
■ May contain delay, event or timing control
statements
■ Can enable other task and function
■ Donot return with a value, but can pass
multiple values through output and inout
argument
module top;
reg [15:0] A, B, and1,or1, xor1;
always @(A or B)
begin
bitwise_oper(and1,or1,xor1,A,B);
and
task bitwise_oper;
output [15:0] and1, or1, xor1;
input [15:0]a, b,;
begin
and1=a&b;
or1= a|b;
xor1=a^b;
end
endtask
endmodule
Function
□ Must not contain delay, event or timing control
statements
□ Always execute in 0 simuation time
□ Must have at least one input argument. Can
have more than one input.
□ Always return a single value. But can not have
output or inout arguments.
Module parity;
Reg[31:0]addr;
Reg parity;
always @(addr)
begin
parity = calc_parity(addr);
$display(“”);
end
function calc_parity;
input[31:0] address;
begin
calc_parity = ^addrress;
end
endfunction
endmodule
Automatic task & function
□ All items or variables declared inside automatic

tasks are dynamically allocated for each
invocation.
□ Each task call operate in an independent space
□ Task call operate on independent copies of the
task varibles.
□ Each call to automatic function operates in an

independent variable space.

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Verilog HDL -Introduction

Ref: Verilog – HDL by samir palnitkar 2nd Edition

□ SENIOR VERIFICATION ENGINEER

• Easy to learn and easy to use.

A module can be an element or collection of low level design

□ Gate Level: Module implemented in

Sub-bloc Sub-bloc Sub-bloc Sub-bloc

Leaf Leaf Leaf Leaf Leaf Leaf Leaf Leaf

□ Verilog is case sensitive

module sample (X,Y,Z,O);

// Describe the circuit using logic symbols

Fall Delay: Delay associated with o/p

□ Dataflow modeling provides a powerful way to implement a

□ Circuit is designed in terms of the data flow between registers

□ Currently, automated tools are used to create a gate-level

□ It cannot be a scalar or vector register.

□ Continuous assignments are always active.

□ The assignment expression is evaluated as soon as one of the

□ Delay values can be specified for assignments in terms of time

module clock_gen (output clock);

reg_a[2] <= #15 1’b1;

//2 concurrent always blocks with blocking statement

//2 concurrent always blocks with non – blocking

case (expn) case ({s1,s0})

□ All items or variables declared inside automatic

□ Each call to automatic function operates in an

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