Ddr3-Emac40-Queue-Manager Test Bench: - C2sis

Q4 2014
THE BEST PATH FROM IDEAS TO PRODUCTION SILICON

DDR3-EMAC40-QUEUE-MANAGER
TEST BENCH
-c2sis
1
Agenda
Introduction to UVM and UVM Architecture

UVM Phases
DDR3 Queue Manager Tb Architecture
2013 Tabula, Inc.
UVM- Universal Verification Methodology

UVM Universal Verification Methodology
Accellera Standard
System verilog UVM Base class library
Near backward compatible with OVM
Test benches for (system)verilog/VHDL/ SystemC designs

Configurable, flexible test benches
Constrained random, coverage driven verification
Verification IP re-use
Separation of tests/stimulus from test bench
Layered sequential Stimulus
Standardized messaging and reporting
2013 Tabula, Inc.
Layered Test Bench Architecture

Structured Test benches are important for complex DUT verification
Better maintainability and re-usability
2013 Tabula, Inc.
UVM TEST
Test is the top level class that instantiates Environment ENV,
configures the test bench and initiates construction
Individual tests derive from uvm_test
Each test case instantiates uvm_env and configures them
Test bench is activated with a call to run_test() which starts build
phases
2013 Tabula, Inc.
UVM Env
It has collection of Agents like Tx_Agent and Rx_Agent in our case.
Has its own configuration object
Eg. It can control number of agents, env.config can set agent.config
Also contains analysis components like scoreboard and coverage

monitor
Multiple block level env classes can be instantiated to have top level
env
2013 Tabula, Inc.
UVM SCOREBOARD
Connected to monitors through TLM ports eg. Uvm_analysis ports

Receives sequence item from transmission and reception monitors
Contains checkers and comparison logic
Reports the results of test
2013 Tabula, Inc.
UVM Agent
Contains a group of uvm_components ( Driver, Monitor and
Sequencer) focused around a specific pin level interface.
Multiple agents can be used for multiple DUT interfaces which has
different protocol
Agents can be re-used for similar interfaces
Configurable is_active flag indicates whether the agent is active or
passive
If agent is active driver, sequencer and monitor are constructed.
If agent is passive only the monitor is constructed.
2013 Tabula, Inc.
Components of Agent
DRIVER
Converts data inside series of sequence_items into pin level transactions
SEQUENCER
Controls generation of stimulus

Routes sequence_items from sequence where they are generated to the driver
MONITOR
Observes pin level activity and converts its observations into sequence_items
which are sent to analysis component like scoreboard
2013 Tabula, Inc.
Layered Sequential stimulus

Every stimulus drives some transaction as pins on DUT e.g.
read/write transaction
A group of transactions (sequence_items) can be combined to form
a sequence
A test will define what sequences and order of them
2013 Tabula, Inc.
10
UVM Sequences
Sequence is a transient object with limited life time unlike a
uvm_component
Each sequence will have to implement a task called body().

This can be implemented to create other sequences or to generate
sequence_item and send to driver
Sequencer is an intermediate component that implements

communication channel between sequence and driver
Sequence item
Data object that contains all the data that driver needs to drive on DUT.
Most randomization done on this object
2013 Tabula, Inc.
11
Agenda

UVM Phases
2013 Tabula, Inc.
12
UVM PHASES
1) Build Phase:
This phase is used to construct various child components/ports/exports
and configures them.
Ex: function void build_phase (uvm_phase phase)
//- Create agent
//- Create Score board
endfunction: build_phase
2) Connect Phase: This phase is used for connecting the
ports/exports of the components.
Ex: function void connect_phase ( uvm_phase phase);
//- Connect from agent to score board
endfunction: connect_phase
2013 Tabula, Inc.
3) End of eloboration: This phase is used for configuring the components

if required.
Ex: function void end_of_elaboration_phase( uvm_phase phase);
//- Printing Hierarchy
endfunction: end_of_elaboration_phase
4) Start of simulation: This phase is used to print the banners and
topology
Ex: function void start_of_simulation_phase (uvm_phase phase);
super.start_of_simulation();
endfunction : start_of_simulation_phase
5) Run: In this phase , Main body of the test is executed where all threads
are forked off.
virtual task run_phase (uvm_phase phase);
End task : run_phase
.
2013 Tabula, Inc.
6) Extract: In this phase, all the required information is gathered.

7) Check: In this phase, check the results of the extracted information
such as un responded requests in scoreboard, read statistics
registers etc.
8) Report: This phase is used for reporting the pass/fail status
2013 Tabula, Inc.
Agenda

UVM Phases
2013 Tabula, Inc.
16
DDR3 Queue Manager Verification Environment
2013 Tabula, Inc.
17
Description
Test case Library contains the list of all test cases which user can
run.
User calls one of the test present in test case library from the
command line.
The test called by user build the environment and connects all the
components.
The test contains all the sequences and their order which will be
called from sequence library and sequencer will route these
sequences to driver.
2013 Tabula, Inc.
18
Description . . .
Driver will convert these sequences into pin level transactions and
drive the DUT signals. In this case it will drive the tx signals of tb
emac.
Tx_monitor observes pin level activity on tx interface and converts
its observations into sequence_items which are sent to scoreboard.
Rx_monitor observes pin level activity on rx interface and converts
its observations into sequence_items which are sent to scoreboard.
Scoreboard collects sequence items from both tx and rx monitors
and performs different kinds of checks like data integrity check ,
length check, priority check.
2013 Tabula, Inc.
19
THANK YOU
2013 Tabula, Inc.
20

Ddr3-Emac40-Queue-Manager Test Bench: - C2sis

Uploaded by

Copyright:

Available Formats

Ddr3-Emac40-Queue-Manager Test Bench: - C2sis

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Ddr3-Emac40-Queue-Manager Test Bench: - C2sis

Uploaded by

Copyright:

Available Formats

What is UVM and what are its main components?

What is UVM and what are its main components?

What are the different phases in UVM testbench?

What are the different phases in UVM testbench?

Q4 2014

THE BEST PATH FROM IDEAS TO PRODUCTION SILICON

Introduction to UVM and UVM Architecture

2013 Tabula, Inc.

UVM- Universal Verification Methodology

Test benches for (system)verilog/VHDL/ SystemC designs

2013 Tabula, Inc.

Layered Test Bench Architecture

2013 Tabula, Inc.

2013 Tabula, Inc.

Eg. It can control number of agents, env.config can set agent.config

Also contains analysis components like scoreboard and coverage

2013 Tabula, Inc.

Connected to monitors through TLM ports eg. Uvm_analysis ports

2013 Tabula, Inc.

2013 Tabula, Inc.

Converts data inside series of sequence_items into pin level transactions

Controls generation of stimulus

2013 Tabula, Inc.

Layered Sequential stimulus

2013 Tabula, Inc.

Each sequence will have to implement a task called body().

Sequencer is an intermediate component that implements

2013 Tabula, Inc.

Introduction to UVM and UVM Architecture

2013 Tabula, Inc.

2013 Tabula, Inc.

3) End of eloboration: This phase is used for configuring the components

6) Extract: In this phase, all the required information is gathered.

2013 Tabula, Inc.

Introduction to UVM and UVM Architecture

2013 Tabula, Inc.

DDR3 Queue Manager Verification Environment

2013 Tabula, Inc.

2013 Tabula, Inc.

2013 Tabula, Inc.

2013 Tabula, Inc.

You might also like