Samsung Bn44-00439a Power Supply
Samsung Bn44-00439a Power Supply
Samsung Bn44-00439a Power Supply
May 2008
AAT1168/1168A/1168B
Product information presented is current as of publication date. Details are subject to change without notice.
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ORDERING INFORMATION
DEVICE PART TEMP. MARKING
PACKAGE PACKING MARKING
TYPE NUMBER RANGE DESCRIPTION
Device Type
AAT1168
AAT1168 Q5:VQFN32- T: Tape Lot no.(6~9digits)
AAT1168 40 ° C to + 85 ° C XXXXX
-Q5-T 5*5 and Reel Date Code
XXXX
(4digits)
Device Type
AAT1168A
AAT1168A Q5:VQFN32- T: Tape Lot no.(6~9digits)
AAT1168A 40 ° C to + 85 ° C XXXXX
-Q5-T 5*5 and Reel Date Code
XXXX
(4Digits)
Device Type
AAT1168B
AAT1168B Q5:VQFN32- T: Tape Lot no.(6~9digits)
AAT1168B 40 ° C to + 85 ° C XXXXX
-Q5-T 5*5 and Reel Date Code
XXXX
(4Digits)
TYPICAL APPLICATION
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ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL VALUE UNIT
Input Voltage 1 (IN1, IN2, IN3, DLY, CTL) VI1 VDD +0.3 V
Input Voltage 2
VI2 VH1 +0.3 V
(VI1+, VI1 − , VI2+, VI2 − , VI3+, VI3 − , VI4+, VI4 − , VI5+, VI5 − )
Output Voltage 2 (ADJ, VO1, VO2, VO3, VO4, VO5) VO2 VH1 +0.3 V
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ELECTRICAL CHARACTERISTICS
( VDD = 2.6V to 5.5V, TC = –40 ° C to 85 ° C , unless otherwise specified. Typical values are tested at 25 ° C ambient
temperature, VDD = 5V, VDD1 = 10V.)
Reference Voltage
PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT
Reference Voltage VREF IVREF = 100µA 1.231 1.250 1.269 V
IVREF = 100µA,
Line Regulation VRI - 2 5 mV
VDD = 2.6V~5.5V
Oscillator
PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT
Oscillation Frequency fOSC 1.05 1.20 1.35 MHz
Maximum Duty Cycle DMAX 84 87 90 %
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ELECTRICAL CHARACTERISTICS
( VDD = 2.6V to 5.5V, TC = –40 ° C to 85 ° C , unless otherwise specified. Typical values are tested at 25 ° C ambient
temperature, VDD = 5V, VDD1 = 10V.)
AAT1168/AAT1168B 55 ms
During Fault Protect Trigger Time t FP
AAT1168A 165 ms
AAT1168/AAT1168B 1.00 1.05 1.10 V
IN1 Fault Protection Voltage VF1
AAT1168A 1.13 1.17 1.20 V
IN2 Fault Protection Voltage VF2 0.40 0.45 0.50 V
Level to Produce
Feedback-Voltage Line Regulation VRI1 VEO = 1.233V 0.05 0.15 %/V
2.6V < VDD < 5.5V
Transconductance Gm ∆I = 5 µ A 105 µS
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ELECTRICAL CHARACTERISTICS
( VDD = 2.6V to 5.5V, TC = –40 ° C to 85 ° C , unless otherwise specified. Typical values are tested at 25 ° C ambient
temperature, VDD = 5V, VDD1 = 10V.)
OUT2 Leakage Current IOFF2 VIN2 = 0V, OUT2 = –12V −20 −50 µA
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ELECTRICAL CHARACTERISTICS
( VDD = 2.6V to 5.5V, TC = –40 ° C to 85 ° C , unless otherwise specified. Typical values are tested at 25 ° C ambient
temperature, VDD = 5V, VDD1 = 10V.)
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ELECTRICAL CHARACTERISTICS
( VDD = 2.6V to 5.5V, TC = –40 ° C to 85 ° C , unless otherwise specified. Typical values are tested at 25 ° C ambient
temperature, VDD = 5V, VDD1 = 10V.)
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PIN DESCRIPTION
PIN NO. NAME I/O DESCRIPTION
QFN-32
1 VOUT3 - Channel 3 Output Voltage (gate high voltage input)
3 GND - Ground
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25 IN3 OUT3 26
1. 25V
6 VI1--
VO1 5
7 VI1+
9 VI2-- VO2 8
VI2+
10
12 VI3+ VO3
13
16 VI4- VO4
17
15 VI4+
19 VI5- VO5 20
18
VI5+
29 DLY VDD1
14
Ω
2.5kΩ
ADJ VOUT3
31 1
VGH
32
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TYPICAL APPLICATION CIRCUIT
Vin
R1
3.3V To 5V C1 10Ω
10µF C2 L
0.1µF 6.8µH
22
VADD VDD SW 21
D
R10 DFLS220L
7 VI1+
VOUT1
R11
AAT1168/A/B
10 VI2+ C3
R2
13.3V/300mA
R12
GND1 4
47µF
97.6k Ω
12 VI3+
IN1 23
R13
R3
15 VI4+ 10k Ω
R14
18 VI5+ VDD1 14
R15
C4 SW
0.1µF
C5
GND2 11 1µF
6 VI1- C6
C13 U1
R16 1µF
1µF 10Ω 5 VO1
BAT54S
R4
C14
9 VI2-
OUT3 26
6.8kΩ Q1
R17
VGAMMA 1µF 10Ω 8 VO2
MMBT4403
C7
16 VI4- 1µF
C15 R18 U2
1µF 10Ω 17 VO4 SW
R5
BAT54S
19 VI5- 200k Ω
C16 R19 IN3 25 VOUT3
1µF 10Ω 20 VO5
R6
C8
25V/30mA
10k Ω 1µF
R20
VCOM 10Ω VOUT3 1
13 VO3 C9
0.1µF C10
C17
0.1µF
10µF SW
U3
BAT54S
CTL 30 CTL
R7
29 DLY
6.8kΩ Q2
OUT2 28
C18 R21 MMBT4401
R8
31 ADJ 62k Ω
IN2 27 VOUT2
R9 -6V/30mA
VGH
R22
32 VGH 10kΩ C11
1µF
57.6k Ω VREF 2
C12
24 EO 0.1µF
GND
C19
1.8nF 3
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TYPICAL OPERATING CHARACTERISTICS
( VIN = 5V, VOUT1 = 12V, VOUT2 = −7V, VOUT3 = 27V, TC = +25 C , unless otherwise noted.)
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TYPICAL OPERATING CHARACTERISTICS
( VIN = 5V, VOUT1 = 12V, VOUT2 = −7V, VOUT3 = 27V, TC = +25 C , unless otherwise noted.)
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ILpeak
DESIGN PROCEDURE κ=
IIN
Boost Converter Design
η : Boost converter efficiency
Setting the Output Voltage and Selecting
κ : The ratio of the inductor peak to peak ripple current
the Lead Compensation Capacitor to the input DC current
The output voltage of boost converter is set by the
VIN : Input voltage
resistor divider from the output (VOUT1) to GND with the
VO : Output voltage
center tap connected to the IN1. Where VIN1 , the boost
IO : Output load current
converter feedback regulation voltage is 1.233V.
fS : Switching frequency
Choose R2 (Figure 2) between 5.1kΩ to 51kΩ and
D : Duty cycle
calculate R1 to satisfy the following equation.
ILPEAK : Inductor peak to peak ripple current
IIN : Input DC current
V
R1 = R2 OUT1 − 1
VIN1 The AAT1168 SW current limit ( ILIM ) and inductor’
saturation current rating ( ILSAT ) should exceed IL(peak ) ,
VOUT1
and the inductor's DC current rating should exceed IIN .
For the best efficiency, choose an inductor with less
EO VREF R1 DC series resistance ( rL ).
24 gm
IN1
23 VIN1
RC ILIM and ILSAT > IL ( peak )
CP R2
ILDC > IIN
CC AAT1168/A/B VIND
IL (peak ) = IIN + ,
2Lfs
IO
IIN = ,
Figure 2. Feedback Circuit η(1 − D)
2
IO
PDCR ≈ rL
Inductor Selection η(1 − D)
The minimum inductance value is selected to make
ILDC : DC current rating of inductor
sure that the system operates in continuous conduction
PDCR : Power loss of inductor series resistance
mode (CCM) for high efficiency and to prevent EMI.
The equation of inductor used a parameter κ , which is Table 1.Inductor Data List
the ratio of the inductor peak to peak ripple current to C6-K1.8L rL DC CURRENT RATING
the input DC current. The best trade-off between 3.9 µ H 41 m Ω 2.5A
voltage ripple of transient output current and
6.8 µ H 68 m Ω 2.2A
permanent output current has a κ between 0.4 and
10 µ H 81 m Ω 1.8A
0.5.
ηVO MITSUMI Product-Max Height: 1.9mm
L≥ D(1 − D)2 ,
κIOfs
Example 1: In the typical application circuit (Figure 1)
VIN
D = 1− , the output load current is 300mA with 13.3V output
VO
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voltage and input voltage of 5V. Choose a κ of 0.465 Input Capacitor Selection
and efficiency of 90%. The input capacitors have two important functions in
0.9 * 13.3 PWM controller. First, an input capacitor provides the
L≥ 0.624(0.376 )2 ≈ 6.8 µ H
0.465 * 0.3 * 1.16 power for soft start procedure and supply the current
IO for the gate-driving circuit. A 10 µ F ceramic capacitor
IIN = = 0.89A
η(1 − D)
is used in typical circuit. Second, an input bypass
V D
IL (peak ) = IIN + IN = 1.095A capacitor reduces the current peaks, the input voltage
2Lf s
drop, and noise injection into the IC. A low ESR
PDCR = 0.043W or 1% power loss ceramics capacitor 0.1 µ F is used in typical circuit. To
ensure the low noise supply at VDD , VDD is decoupled
Schottky Diode Selection from input capacitor using an RC low pass filter.
Schottky has to be able to dissipate power. The
dissipated power is the forward voltage and input DC
current. To achieve the best efficiency, choose a
Schottky diode with less recovery capacitor (CT) for
fast recovery time and low forward voltage (VF).
For boost converter, the reverse voltage rating (VR)
should be higher than the maximum output voltage,
and current rating should exceed the input DC current.
PDIODE : Total power loss of diode for boost converter Output Capacitor
PDSW : Switching loss of diode for boost converter The output capacitor maintains the DC output voltage.
PDCOM : Conduction loss of diode for boost converter A Low ESR ( rC ) ceramic capacitor can reduce the
output ripple and power loss. There are two
parameters which can affect the output voltage ripple:
Table 2. Schottky Data List
1. the voltage drops when the inductor current flows
SMA VF VR CT through the ESR of output capacitor; 2. charging and
B220A 0.24V 14V 150pF discharging of the output capacitor also affect the
output voltage ripple.
B240A 0.24V 28V 150pF
VRIPPLE = VRIPPLE (COUT ) + VRIPPLE (ESR )
DIODES Product, Max-Height: 2.3mm IOD
VRIPPLE (COUT ) ≈
fS COUT
For example, VRIPPLE (ESR) ≈ IL(peak) rC
PDIODE = PDSW + PDCOM = 0.203W or 5.1% power loss.
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2
(
PESR = ILpeak ) .rC
+
+
ESR: Equivalent Series Resistance −
−
VRIPPLE = 26mV +
PESR = 0.023W or 0.6% power loss
β r = rL + DrDS + (1 − D)RF
VO (RL + 2rC ) 1
Where Tpi0 = , w zi =
Figure 4. Closed-current Loop for Boost with PCM L (RL + rC ) C (RL / 2 + rC )
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Current Sampling Transfer Function V
Where β = FB
Error voltage to duty transfer function Fm is: VO
Fm (s) =
d
=
(
2fs2 s2 + 2ξw ns + w n2 ) The compensator transfer function
v ei Tpi0RCSs ( s + w zi ) ( s + w sh ) VC s + wc
TC (s) = = gmRC
v fb s
3w s 1 − α M − Ma Where
Where w sh = ,α = 2
π 1+ α M1 + Ma 1
wc =
RCCC
w s = 2πfs
The closed-current loop transfer function Ticl is: Figure 6. Voltage Loop Compensator
Compensator design guide:
Ticl (s) =
12fs 2
x
s ( 2
+ 2ξw n s + w n2 ) 1. Crossover frequency fci <
1
fs
2
zi (
RCS Tpi0 ( s + w ) s2 + w s +12f 2
sh s )
2. Gain margin>10dB
AAT1168/1168A/1168B
Table 3 K factor Table
Best Corner Positive and Negative LDO driver
C Frequency K factor Output Voltage Selection
21.533µF 23.740 kHz 4.692 The output voltage of positive LDO driver is set by a
25.079µF 21.842 kHz 5.083 resistive divider from the output (Vout3) to GND with
32.587µF 20.095 kHz 6.042 the center tap connected to the IN3, where VIN3, the
positive LDO driver feedback regulation voltage, is
36.312µF 15.649 kHz 5.230
1.25V. Choose R6 (Figure 8) between 10k Ω and
38.469µF 13.247 kHz 4.703
51k Ω . And calculate R5 with the following equation.
Bode Diagram
60
40
Magnitude (dB)
20
-20
-40
-90
-135
Phase (deg)
-180
-225
Figure 8. The Positive LDO Driver
-270
2 3 4 5 6
10 10 10 10 10
Frequency (Hz)
®
Figure 7. Bode Plot of Loop Gain Using Matlab
Simulation
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C9
0.1µF C10
0.1µF
Table 4 Pass Transistor Specifications
SW
U3 MMBT4401 MMBT4403
BAT 54 S
OUT2 28
6.8k Ω
Q2 hfe(min) 130 90
MMBT4401
R8
62kΩ
IN 2 27 DIODES Product, Case: SOT23
R9 C11
VOUT2
10k Ω 1µF -6V/30mA
VREF 2
C12
Example 5:
0.1µF
Output current of VOUT3 and VOUT2 are 30mA, the
minimum base-emitter resistor can be calculated as
Figure 9. The Negative LDO Driver
Example 4: R 4 (min) ≥ 0.5 /(( 1mA − 30mA ) / 90) ≥ 750 Ω
For system design R 7(min) ≥ 0.65 /(( 1mA − 30mA ) / 130) ≥ 845 Ω
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Operational Amplifier Table 5. Recommended Components
The AAT1168 have five amplifiers independent. The DESIGNATION DESCRIPTION
operational amplifiers are usually used to drive VCOM 6.8 µH, 1.8A,
L
and the gamma correction divider string for TFT-LCD. MITSUMI C6-K1.8L 6R8
The output resistors and capacitors of amplifiers are as 200mA 30V Schottky barrier
low pass filter and compensator for unity GAIN stable. U1, U2, U3 diode (SOT-23),
DIODES BAT54S
2A 20V rectifier diode
D
DIODES DFLS220L
10 µF, 25V X5R ceramic
C3
capacitor
C5, C6, C7 1 µF, 25V X5R ceramic capacitor
C2, C4, C9, 0.1 µF, 50V X5R ceramic
C10, C12 capacitor
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LAYOUT CONSIDERATION plane on the PCB. This will reduce noise and ground
loop errors as well as absorb more of the EMI radiated
Layout Guide by the inductor. For boards with more than two layers,
The system’s performances including switching noise,
a ground plane can be used to separate the power
transient response, and PWM feedback loop stability
plane and the signal plane for improved performance.
are greatly affected by the PC board layout and
grounding. There are some general guidelines for PC Board Layout
layout:
Inductor
Always try to use a low EMI inductor with a ferrite core.
Filter Capacitors
Place low ESR ceramics filter capacitors (between
0.1µF and 0.22µF) close to VDD and VREF pins. This
will eliminate as much trace inductance effects as
possible and give the internal IC rail a cleaner voltage
supply. The ground connection of the VDD and VREF
bypass capacitor should be connected to the analog
ground pin (GND) with a wide trace.
Output Capacitors
Place output capacitors as close as possible to the IC.
Minimize the length and maximize the width of traces to
get the best transient response and reduce the ripple
noise. We choose 10µF ceramics capacitor to reduce
the ripple voltage, and use 0.1µF ceramics capacitor to
reduce the ripple noise.
Feedback
If external compensation components are needed for
stability, they should also be placed close to the IC.
Take care to avoid the feedback voltage-divider
resistors’ trace near the SW. Minimize feedback track
lengths to avoid the digital signal noise of TFT control
board.
Ground Plane
The grounds of the IC, input capacitors, and output
capacitors should be connected close to a ground
plane. It would be a good design rule to have a ground
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PACKAGE DIMENSION
VQFN32
C
PIN 1 INDENT
E E2
A1
D A D2
L
DIMENSIONS IN MILLIMETERS
SYMBOL
MIN TYP MAX
A 0.8 0.9 1.0
A1 0.00 0.02 0.05
b 0.18 0.25 0.30
C ------ 0.2 ------
D 4.9 5.0 5.1
D2 3.05 3.10 3.15
E 4.9 5.0 5.1
E2 3.05 3.10 3.15
e ------ 0.5 ------
L 0.35 0.40 0.45
y 0.000 ------ 0.075
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