Printed Circuit Board Design Techniques for DS40MB200

Printed Circuit Board Design Techniques for DS40MB200

1.0 Introduction
The DS40MB200 is a high speed 2:1 multiplexer and 1:2 fan-out repeater designed to support redundancy and extend copper backplanes up to 4 Gb/s. The output driver features fast edge rates, typically about 80 ps. Each input stage features fixed equalizer, followed by a high-gain limiting amplifier that re-shapes the output waveforms. The DS40MB200 accepts input signal as low as 100 mV (peakto-peak). The high speed, high gain and fast edge rate attributes of any high-speed circuit require users to use high speed printed circuit board techniques to achieve good performance. This application note outlines the techniques to achieve this goal.

National Semiconductor Application Note 1398 TK Chin October 2005

choice for high speed communication designs. The high speed differential IOs are assigned to the center portion of the package such that each differential pair is sandwiched by a power or ground pin, providing isolation and ground shielding. Coupled microstrip board traces are the preferred transmission line structures for best signal fidelity. The optimum trace width is 10 mils, being equal to the 10-mil landing pad of the LLP-48 package. Finer trace width, such as 5 mils, can also be used with slightly higher impedance mismatch caused by changes in trace width between the traces and the pads. The differential board traces should be routed with constant spacing to ensure impedance uniformity along the length of the traces. Figure 1 shows a partial layout arrangement with 5-mil trace width.

2.0 Differential Pairs

The DS40MB200 uses a 48-lead lead-less LLP package. The LLP offers low package parasitics and is the package of

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FIGURE 1. DS40MB200 Routing Example Using Coupled Microstrips

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2.0 Differential Pairs

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In high routing density boards, coupled striplines are commonly used, but requires the use of plated through holes. These plated through holes introduce parasitic capacitance and may degrade signal fidelity. Small via, with less than 8

mils hole size, should be used to minimize mutual capacitive coupling between the via and nearby ground or power planes. Differential via structure with shared oval-shaped anti-pad can further reduce parasitic capacitance. Figure 2 shows a pair of differential vias with shared oval anti-pad.

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FIGURE 2. Differential Vias with Oval Anti-Pad The electrical length of each differential pair should be well matched. As a rule of thumb, the delay skew of the complimentary signals are matched within a small fraction of the signals edge rate. With an edge rate of about 80 ps, it is acceptable to have a delay skew within 10 ps. For a FR4 board, matching trace lengths within 50 mils achieves less than 10 ps skew between the complimentary signals of the differential pair. It is important to note that it is the matched electrical length instead of matched physical length that matters. Identical geometries should be used for the complimentary signals, and their trace widths in each signal layer should be matched. In adjusting the trace lengths of a pair of coupled board traces, never disrupt the uniform spacing of the differential pair. Figure 3 shows a bad example of matching trace lengths. Disrupting the uniform spacing of the coupled differential pair will create impedance discontinuity and impact signal quality. Figure 4 shows a good example of matching trace lengths. In this example, the lengths of the uncoupled segments of the differential pair are adjusted to achieve the desired match lengths. The coupled board traces maintain their uniform spacing, while the trace width of the uncoupled traces are slightly widened to maintain the same characteristic impedance.

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FIGURE 3. Bad Example Of Matching Trace Length Of Coupled Board Traces

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2.0 Differential Pairs

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FIGURE 4. Good Example Of Matching Trace Length Of Coupled Board Traces

3.0 Components Landing Pads

AC coupling capacitors should be placed on the receive inputs of the DS40MB200. The transition time of the bit stream at the receive side is significantly slowed down by interconnect, making it more tolerant to impedance mismatch caused by the AC coupling capacitors and the parasitic capacitance caused by their landing pads. Small physi-

cal size, surface mount capacitors, such as 0402, should be used to reduce impedance mismatch caused by the landing pads of the capacitors. When fine trace width is used with large components, the landing pads of the components are huge relative to the trace width. Figure 5 shows an example of 5-mil traces routing to an edge connector with 20 mil pads.

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FIGURE 5. Fine Board Traces Used With Large Component Landing Pads
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3.0 Components Landing Pads

(Continued) below it. Figure 6 depicts the cross-sectional view of the board showing the effect of impedance drop from landing pads.

The huge landing pads of the edge connector effectively form a short segment of wide trace, significantly lowering the impedance and introduce relatively large excess capacitance between the pad and the ground plane immediately

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FIGURE 6. Cross-Section Of Board Trace And Component Pad We can use anti-pads on the power and ground planes below the landing pads. This technique is used to reduce the parasitic capacitance formed between the pad and the nearby power or ground plane. Figure 5 illustrates anti-pads used with an edge connector to minimize excess capacitance. A 3-D electromagnetic field solver is usually used to determine the size of the anti-pad to optimize compensation. be used to connect a power or ground pin to nearby power or ground plane. Ideally, vias are placed tangent to the IC pads to avoid adding trace inductance. Placing power planes closer to the top of the board reduces the length and inductance of the vias.

4.0 Power Pins

Each power or ground lead of the DS40MB200 should be connected to the power or ground plane through a low impedance path. For best results, one or more vias should

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4.0 Power Pins

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FIGURE 7. VCC and GND Hook-Up For The DS40MB200 Bypass capacitors should be placed close to VCC pins. They can be conveniently placed at four corners of the LLP package. Small physical size capacitors, such as 0402, X7R, surface mount capacitors should be used to minimize body inductance of capacitors. Each bypass capacitor is connected to the power and ground plane through vias tangent to the pads of the capacitor. Figure 7 shows VCC and GND hook-up for the DS40MB200 and placement of bypass capacitors. An X7R surface mount capacitor of size 0402 has about 0.5 nH of body inductance. At frequencies above 2030 MHz, X7R capacitors behave as low impedance inductors. To extend the operating frequency range of these capacitors to
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a few hundred MHz, an array of different capacitance ranging from 100 pF, 1 nF, 0.01 F, 0.1 F are commonly used in parallel. A more effective bypass capacitor can be built using sandwiched layers of power and ground planes at a separation of 23 mils. An ideal high frequency bypass capacitor is formed. With a 2-mil FR4 dielectric, there is about 500 pF capacitance per square inch. Figure 8 depicts a PCB stack-up with VCC-GND planes placed on the top side of the board. This stack-up arrangement provides a high frequency buried capacitor, and lowers the inductance of power and ground via by reducing the lengths of the vias. The center dap of the package should be connected to ground plane through an array of vias. The array of via
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Printed Circuit Board Design Techniques for DS40MB200

4.0 Power Pins

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reduces the effective inductance to ground, and also offer enhanced thermal performance for the package.

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FIGURE 8. PCB Stack-Up With Buried Capacitor And Short VCC/GND Vias

5.0 Conclusion
High speed printed circuit boards require designers to go beyond connectivity. Multi-gigabit boards require attention to board geometry details. These details include dimensions of trace width, component pads, plated-through holes, antipads, board thickness and board stack-up. Board material properties such as dielectric constant and loss tangent are important considerations in choosing proper board structures. The techquies described in this application notes apply to multi-gigabit board design, with examples illustrated for DS40MB200 mux/buffer. In a multi-gigabit board design, board designers have to find the unwanted Ls and Cs and devise geometries to overcome their impacts. Very often, a 2-D electromagnetic field solver is used to predict the elec-

trical behavior of board traces, and a 3-D field solver is needed to deal with 3-dimensional geometries such as via and anti-pad. With a little extra time spent on attention to details, the reward is a high performance board running at multi-gigabit and beyond.

Reference
Datasheet of DS40MB200 Dual 4Gb/s mux/buffer, www.national.com AN-1389Setting Pre-Emphasis Level for DS40MB200 Dual 4 Gb/s Mux/Buffer AN-1187Leadless Leadframe Package (LLP)

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