Clock and Data Recovery for Serial

Digital Communication
(plus a tutorial on bang-bang Phase-Locked-Loops )

Rick Walker
Hewlett-Packard Company
Palo Alto, California
[email protected]
 Agenda
• Overview of serial data communications
• Degradation mechanisms, data coding
• Clock recovery methods and components
• Jitter measurements
• Break
• BB PLL Theory
• Simulation techniques
• 1st, 2nd order loops
• Key design parameters

2
 Diversity of CDR applications
• Clock and Data Recovery (CDR) applications span the
range from ultra-high-volume, low cost datacom
applications to very high precision, long-haul telecom
applications
• Many different trade-offs tailor each circuit to the target
application area

1.25Gb/s Gigabit 2.488Gb/s SONET

Ethernet Transceiver CDR ~$400 (telecom
<$6 in volume application)
(datacom application) 1cm
3
 Basic Idea
Serial data transmission sends binary bits of
information as a series of optical or electrical pulses:

0111011000111110011010010000101011101100011111..

The transmission channel (coax, radio, fiber) generally

distorts the signal in various ways:

From this signal we must recover both clock and data

4
 Bit Error Rate (BER) Testing
• Pseudo-Random-Bit-Sequence (PRBS) is used to
simulate random data for transmission across the link
• PRBS pattern 2N-1 Bits long contains all N-bit patterns
• Number of errored-bits divided by total bits = BER.
• Typical links are designed for BERs better than 10-12

PRBS PRBS
data TX RX data
generator link receiver

clock in synth clock in

5
 Eye diagram construction
random scope
data TX RX
link
synth trigger

symbol cell (UI)

Y
Use a precise clock to chop the data
into equal periods
X X

overlay each period onto one plot

jitter Y
amplitude
distribution at Y-Y

6
Some Signal Degradation Mechanisms

• Multiplex Jitter
• AC Coupling
• Optical Pulse Dispersion
• Skin Loss
• Random Noise
• E+O Crosstalk
• Intersymbol Interference

7
 Multiplex Jitter
bit stuffing events

high speed data

sub-rate data

phase error
[in UI]
time

Multiplex jitter is not a problem on the high rate channel

itself - it only occurs on non-synchronous, lower speed
tributaries that have been sent over the high-speed
channel (e.g.: DS3 over SONET OC-48).
8
Time/Voltage aberrations from AC-coupling
∆t
V
V t

t=0 t=t
1

V – Vt t1
Percent AC coupled droop is P ≡ ---------------- × 100 ≈ -------- × 100 .
V RC
Jitter is introduced by finite slope of pulse rise/fall time:
tr t1
∆t = ----------------
( 2RC )
9
 Quantized Feedback
AC-Coupled Transmission Link

TX H (ω) RX

Feedback voltage models missing DC information

1 – H (ω)
Output Data
D Q (models ideal
TX waveform)

clock
10
 Skin Loss and Dielectric Loss
Nearly all cables are well modelled by a product of Skin Loss
( –k ) f ( –l ) f
S ( f ) = 10 , and Dielectric Loss D ( f ) = 10 with
appropriate k,l factors. Dielectric Loss dominates in the multi-
GHz range. Both plot as straight lines on log(dB) vs log(f) graph.

1.0 Ring 3
k=.001 Ring 2
linear amplitude

Ring 1
k=.0001 L3
R3 L2
k=.00001 R2
R1
0.0 Three-element equivalent
1k freq (log scale) 10G
circuit of a conductor with
[YFW82] skin loss 11
 Skin Loss Equalization at Receiver
transmission (linear scale)

1.4
3dB boost
1.0 1
equalized
0.5 pure skin
loss
0.0 0
1k freq (log) 10G

2x improvement in
maximum usable [WWS92]
bit-rate
12
Skin Loss Equalization at Transmitter
boost the first pulse after every transition

Error at sampling pt.

usable signal

[FMW97]

before after
13
 Decision Threshold Generation
• To minimize bit-error rate, the decision threshold X-X
must centered in the signal swing. Two common ways of
automatically generating threshold voltage are:
• Peak detection of signal extremes, limited run-length
required

Signal positive peak detector Decision

negative peak detector Threshold

• Decision threshold = signal average, balanced signal

required

Signal Decision
Low-Pass Filter
Threshold
After Tom Hornak: “Interface Electronics for Fiber Optic Computer Links”, (see bibliography for full citation) 14
 Code Disparity
Disparity is defined as Nhigh - Nlow in past transmitted signal

+5 encoded data signal

0
signal disparity
-5

• In an unbalanced code the disparity can grow

without limit. e.g.: 4B5B code of FDDI
• In a balanced code, the disparity is limited to a
finite worst case value. e.g.: 8B10B of
FibreChannel
After Tom Hornak: “Interface Electronics for Fiber Optic Computer Links”, (see bibliography for full citation) 15
 Coding for Desirable Properties

• DC balance, low disparity

• Bounded run length
• High Coding Efficiency
• Spectral Properties (decrease HF and/or DC
component)
• Many Variations are Possible!
• Manchester [San82]
• mB/nB [Gri69][Rou76][WiF83] [YKI84] [Pet88]
• Scrambling [CCI90]
• CIMT [WHY91], Conservative Code [Ofe89]
16
 Simple 3B/4B code example

4B Output Data Maximum Runlength is 6

3B Input Data
Even Words Odd Words Coding Efficiency is 4/3
000 0011
Sending Sync Sequence:
001 0101
SyncA(even), SyncA(odd),
010 0110
SyncB(even), SyncB(odd)
011 1001
allows the unambiguous
100 1010
alignment of 4-bit frame
101 1100

110 0100 1011

111 0010 1101

SyncA 0111 1110

SyncB 1000 0001

17
 Scrambling
• Uses a feedback shift register to randomize data -
reversing process at receiver restores original data
Data Input Scrambled Data
Data Output

XOR
Shift Register
n j 2 1 1 2 j n
Clk
PRBS Generators

Caveat: Only guarantees balance and run-

length under very specific data conditions!
After Tom Hornak: “Interface Electronics for Fiber Optic Computer Links”, (see bibliography for full citation) 18
 Definition of Jitter
unit
interval

-3T -2T -T 0 T 2T 3T 4T time

Impulses spaced equally in time (jitter free signal)

-3T -2T -T 0 T 2T 3T 4T
Impulses spaced irregularly in time (jittered signal)

Errors treated as discrete samples of continuous time jitter

After Trischitta and Varma: “Jitter in Digital Transmission Systems” 19
 Spectrum of NRZ data
variations due to DC balance strategy

sin ( 2πfT )
-------------------------
2π fT
power in dB

missing clock
frequency

f = 0 1 ⁄ 2T 1⁄T 3 ⁄ 2T 2⁄T
20
 NRZ and RZ signalling
NRZ = “non return to zero” data

neither clock nor

+ + data frequency in
+ + + spectrum

data frequency
RZ = “return to zero” data clock frequency
clock, but no data
+ + frequency in
+ + + spectrum

T
NRZ signalling is almost universally used.
21
 Filter Method Examples
2 bandpass
d ⁄ dt X filter

Recovered Clock Output

non-linear element e.g.: SAW filter
NRZ Data Input

delay
bandpass
filter

LC tank

[Yam80][YTY80]
[RFC84][Ros84]
[FHH84][AFK87]

(this last circuit can be thought of as an NRZ-RZ converter)

22
 Summary of Filter Method
Jittered NRZ Data Signal Retimed Data
τ D Q

2 bandpass
d ⁄ dt X filter/limiter
Pro: Con:
Very simple to implement Temperature and frequency variation
Can be built with of filter group delay makes sampling
microwave “tinkertoys” time difficult to control
using coax to very high Narrow pulses imply high fT
frequencies
Hi-Q filter difficult to integrate
23
 Q-Factor in resonant circuits
Voltage envelope of ringing circuit falls to 1/sqrt(e) in Q
radians.

1.0 1.0/sqrt(e)

Q/2*PI cycles

amplitude
Q also equals the center
frequency of a filter divided by
the full-width of the resonance
measured at the half power Fcenter
points: Fcenter/

High-Q filter can be emulated by PLL with low loop B.W.

24
 Data Recovery with simple PLL
Jittered Data Retimed
Signal Data
D Q

Phase
Detector
PLL
Voltage
Low-pass Controlled
Loop Filter Oscillator

25
 Analytic Treatment of Jitter
Perfect Clock:
x ( t ) = A cos ω c t

Jittered Clock:
x ( t ) = A cos [ ω c t + φ ( t ) ]

φ ( t ) is then treated as a continuous time signal

After Behzad Razavi: “Monolithic Phase-Locked Loops, ISSCC96 Tutorial” 26

 Model of Loop

Phase Loop
Detector Filter VCO

Kφ Kv 1
---
s

1
β + -------------------
( 1 + sτ )

Warning: Extra Integration in loop makes for tricky design!

See Floyd M. Gardner, “Phaselock Techniques”, John Wiley and Sons, for good introduction to PLL theory 27
 Loop frequency response

1 Kv
a Kφ β + ------------------- c
( 1 + sτ ) ------
s
(input
data jitter) b

80dB
open loop gain
40dB

0dB
c/a c/b
-40dB

-80dB

1k 10k 100k 1M 10M 100M 1G 10G

28
 Phase Detectors
• Phase detectors generate a DC component proportional
to deviation of the sampling point from center of bit-cell
• Phase detectors are:

Continuous
90° 180°
– 180 ° – 90 ° 0°
Binary Quantized

• Binary quantized phase detectors are also called “Bang-

bang” phase detectors
After Tom Hornak: “Interface Electronics for Fiber Optic Computer Links”, (see bibliography for full citation) 29
 “Self-Correcting Phase Detector”
UP

Data DOWN
D Q D Q
Data [Hog85][Shi87]
Clock

1 = Data.................
2= Clock (Early).....
3 = 1 retimed..........
4 = Clock.................
5 = 3 retimed..........
6 = 1 xor 3 (UP).....
7 = 3xor 5 (DOWN)

30
 Binary Quantized Phase Detector
• NRZ data is sampled at each bit cell and near the
transitions of each bit cell
• The sign of the transition sample is compared with the
preceeding and following bit cell sample to deduce the
phase error
B A T B Output

Data
D Q D Q A 0 0 0 tristate
0 0 1 vco fast
0 1 0 ?
0 1 1 vco slow
Clock
A T B 1 0 0 vco slow
D Q D Q T 1 0 1 ?
1 1 0 vco fast
1 1 1 tristate
[Ale75][WHY91][LaW91][ReG73]
31
 Decision Circuit
• Quantizes amplitude at precise sample instant
• Typically uses positive feedback to resolve small input
signals
• A master/slave D-flip-flop carefully optimized for input
sensitivity and clock phase margin is a common choice
• Latches data on the rising edge of clock signal

simplified schematic symbol: D Q

clock
32
 Example Bipolar Decision Circuit
master latch slave latch

gnd
data in
data out

clock in
Vbias
-5V

• many clever optimizations are possible

[OhT83][Con84][Lai90][Run91][Hau91][Run91]
33
 Loop Filters
[Den88] [Dev91]
[LaW91] [WuW92]

VOUT UP DOWN VOUT

0 0 tristate

0 1 ramp DOWN
UP DOWN 1 0 ramp UP

1 1 tristate

• should have provision for holding value constant (tri-

stating) under long run-length conditions
• may be analog (integrator) or digital (up-down
counter) - but watch out for metastability!
34
 Metastability

slope = dv/dt

ε ∆V
D Q

∆T

For uniform clock jitter, and a latch “danger zone” of ε ,

ε dt
the metastability probability p metastability , is ------- ⋅ ------ .
∆T dv
35
 Regeneration time constant τ
0.5 v=ε
volts

vdiff
0.0
vdiff
0.0
log10(volts)

log10(vdiff)
-8.0
-1.0 0.0 1.0 2.0 3.0
time [ns]

A small voltage ε is forced on latch, until t=0. Differential

t⁄τ
voltage V diff grows as ε ⋅ e . For a given V min and ε ,
V min
the regeneration time required is τ ⋅ log  ------------- .
 ε  36
SPICE tip: current-controlled R/switch
# SPICE time variable resistor.
# the resistance between %in and %out is numerically
# equal to the current pulled out of %ic

.SUBCKT tvres %in %out %ic

h1 %inx %outx poly(2) vx vc 0 0 0 0 1
rdamp %out %outx 0.001
vx %inx %in 0
vc %ic 0 0
.ENDS

R = iin * 1 Ω/Α v(h1)=i(vx)*i(vc)*1 Ω/Α

in out in vx h1 out

ic iin ic vc

36a
 VCO alternatives

LC Oscillator Multivibrator Ring Oscillator

Speed Technology Dependent 1-10’s of GHz, CMOS 1-2 GHz

Phase Noise Good Poor

Integration Poor Excellent

(L, Varactor)

Tunability Narrow/Slow Wide/Fast

Stability Good Poor

(needs acquisition aid)

Other Multi-Phase
Clocks

• [Cor79, Ena87, Wal89, DeV91, Lam93, WKG94]

After Todd Weigandt, B. Kim, P.Gray, “Timing Jitter Analysis for High-Frequency CMOS Ring Oscillators”, March 10, 1994 37
 Multivibrator VCO
Capacitor is alternately charged and
discharged by constant current
Tuned by varying Itune in current source
Diode clamps keep output voltage
constant independent of frequency
Relies on non-linear switching for
oscillation behavior, and so is limited to
moderate frequencies.
Itune
I tune
Frequency = -----------------
4CV be

After Alan B. Grebene, “Analog Integrated Circuit Design”, Van Nostrand Reinhold, 1972, pp 313-315 38
 Example Ring Oscillator VCO
[SyA86]
Input 1 [EnA87]
Output [Wal89]
Tune Input 2

Input 1
Output

Inpu
t2
Input 1 Input 2
Output
Tune

39
 VCO injection locking (problem)
Vcc Noise coupling back to VCO Noise glitch

propagation delay
τ
Vtune

most VCO’s sample the tune

high VCO voltage once per cycle - down
converting the system noise.
nom VCO
•PLL: Fosc α Vtune α θerror
slow VCO •ILO: Fosc α Vtune α θerror
delayed
VCO can injection lock to its own
glitch delayed signal more rapidly than
τ to input data!
40
 VCO injection locking (a solution)
Decompose the
loopfilter pole/zero
into two separate Σ
tuning inputs:
• a wide range input
with very low
bandwidth low gain, wide BW

• a narrow tuning
range input with VCO
wide BW.
this greatly reduces high gain, low BW
effect of VCO noise
on tuning curve.
41
 False or Harmonic Locking to Data

data
clock
1/2 clock
2x clock
4/3 clock

early/late indications
cancel in loop filter,
leaving an attenuated,
but possibly stable lock
signal.
correct early late correct 42
 Aided Acquistion
• Tricky task due to Nyquist sampling constraints caused
by stuttering data transitions

PD loop filter 1
Input Data
VCO

FD loop filter 2

• Still subject to false lock if VCO range is too wide

After Behzad Razavi: “Monolithic Phase-Locked Loops, ISSCC96 Tutorial” 43

 Training Loops
retimed data Data

bang-bang drive
Input
Clock
PDET SEL charge
VCO
pump

dlock
LOS
dtrans State
Reference Clock flock Machine
2.488GHz/256
FDET
[WSY97]
Clock/256 1/256
divider

An increasingly common technique is to provide a

reference clock to the CDR circuit. This allows the VCO
process-variation to be dynamically trimmed out, avoiding
false locking problems.
44
 Phasor Diagram
• Graph of relative phase between clock and data
• Each complete rotation is 1 unit interval of phase slip
• Rotations/second = frequency error (in Hz)
0° Plot of data transitions
versus VCO clock phase.
Data at 1/2, or VCO at 2x,
270° 90° the proper frequency look
locked. This puts a limit on
dθ/dt = ∆F VCO tolerance to prevent
180° false locking.

= missing transitions
= actual transitions
45
 Example Lock Detector
0° [WSY97] ideal data eye

270° 90°

noisy data eye

180°
clock a,b

DQ
data
Raw out-of lock
DQ indication
46
 Communication Trends

20G ? 20M
10G CDR 4X 10M
only nt

Internet Host Count

Serial Link Speed

5G o u 5M
5 - 0 .4 f T) tC
(0.0 os
2G r Tr end H 2M
pola t
Si Bi r ne 10X
e 2X
1G nt
I 1M
8X
500M 8x c t i ve f T) 500K
.4 effe
. 0 5 -0
( 0
200M
S Trend 200K
C MO
100M 100K
Si Bipolar
50M 50K
CMOS
20M 20K
1988 1990 1992 1994 1996 1998
Year of Publication (ISSCC) 47
 Multiphase Receiver Block Diagram
0 1 2 3 multi-phase clock generator
(VCO + interpolator)

0o 90o 180o 270o 45o 22o 67o

Data input D D D D D D D
Q Q Q Q Q Q Q

fT -doubler
data amplifier phase- loop
detector/ filter
Reference Clock state
2.5GHz/128 machine
16
data
4:16 demultiplexer
clock
LOS
[WHK98] 48
 DLL vs PLL which is “best”?
• DLLs do not filter input reference jitter, but do not
accumulate VCO phase errors - best for clock
synthesizers running from clean reference.
• PLLs can have higher phase noise because of multiple
passes through the delay gates of VCO, however is able
to filter noisy input signals.

1 2 3 4 ck
ck τ delayline 1 2 3 4

1 2 3

[KWG94] Degraded clock period

49
 Jitter Measurements

• SONET has the most complete set of jitter

measurement standards, but the techniques are
useful and relevant for datacom applications also

• Jitter Tolerance
• Jitter Transfer
• Jitter Generation

50
 Jitter Tolerance Test Setup
laser optical
transmitter receiver

data xamp + decision bit error

generator limiter circuit rate tester

optical
FM attenuator retiming
modulated circuit
clock

At each frequency, the sinewave

sine wave modulation amplitude is increased until
generator the BER penalty is equal to that
caused by 1dB optical attentuation

After Trischitta and Varma: “Jitter in Digital Transmission Systems” 51

 SONET Jitter Tolerance Mask
15 UI acceptable
range
1.5 UI

0.15 UI

f0 f1 f2 f3 ft

Data Rate f0[Hz] f1[Hz] f2 [Hz] f3 [kHz] ft [kHz]

155 Mb 10 30 300 6.5 65

622 Mb 10 30 300 25 250

2.488 Gb 10 600 6000 100 1000

10 Gb ? ? ? 400 4000

from SONET SPEC: TA-NWT-000253 Issue 6, Sept. 1990, fig 5-13 52

 Jitter Transfer Measurement
Signal
data decision
Generator
generator circuit Phase
detector
clock

retiming
Phase
circuit
D.U.T. modulator
ϕ

[TrV89] [RaO91]
IN OUT
network
analyzer

53
 Jitter Transfer Specification
P[dB] slope = -20 dB/decade
acceptable
range

f c

Data Rate fc[kHz] P[dB] This specification is

155 Mb 130 0.1 intended to control
622 Mb 500 0.1 jitter peaking in long
2.488 Gb 2000 0.1
repeater chains

54
Jitter Generation

decision computer
circuit

spectrum
retiming analyzer
circuit

S.U.T. recovered
clock

55
 Jitter Generation (cont.)

1) Measure Jitter Sidebands around Clock sideband

 V sideband

clock amplitude
Jitter pp ( rads ) = 2∆Θ ≅ 2 atan  --------------------------
 V clock  ∆Θ

nt
ulta
2) Multiply Jitter components by Filter Mask

res
3) RMS sum total noise voltages over band
4) Convert RMS noise voltage to RMS jitter

OC-48 (2.488 Gb/s SONET) specifies 12 kHz hipass filter,

and maximum 0.01 UI RMS integrated jitter.
56
 Why bother with a BB loop?
• it may be difficult to maintain optimum sampling point
with traditional PD/PLL or with filter method over
process, temperature and supply variation
• Narrow pulses of linear PD’s may not work well at
extremely high bit rates
• for monolithic implementation, BB PD has excellent
match between retiming latch and PD latch - allows
for operation at highest latch toggle frequency

B
data
D Q DQ DQ A
data

PD
clk
filter VCO
DQ DQ T 57
 Simple first-order BB loop
VCO

D Q

tupdate

• VCO runs at two discrete frequencies: f nom ± f bb .

• Phase error is evaluated at a discrete time interval
t update . In the general case, this can be considered
approximately equal to mean transition time of the
data.
58
 How to simulate a loop?
• SPICE (boolean & polynomial)
• timestep simulator [FLS63]
• event driven simulator [Mac87]
• actual hardware

The need for fast simulation

• understand the design space
• check corner cases
• build intuition
59
 Efficient Simulation Strategy

• Simulating VCO waveform is unnecessary to accurately

model ideal PLL behavior.
• Only frequency and phase is needed.
• Model all circuit time-varying state variables as voltages.
• Convert between frequency and phase variables with
explicit integration block.

60
 Model of First-order Loop

φmod
Fin
Σ ∫ v dt Σ Kvco

fsample

node: Fin ∆F ∆θ1 Θerror bbtune Fvco

unit: Hz Hz UI UI V Hz

61
 The simulator main loop

for (simtime=STARTTIME; simtime<=STOPTIME; simtime+=stepsize) {

update(); /* update nodes each tstep */
if (simtime-SAVETIME >= savestep*points_plotted) {
output();
points_plotted++;
}
/* swap pointers to avoid copying data arrays */
temp = nodeold;
nodeold = node;
node = nodenew;
nodenew = temp;
}

0 1 2 N 2N 3N

nodeold node nodenew

62
 The update() routine
void update() /* this routine responsible for updating node[] */
{
fin(1,FIN,FSTEP,STEPTIME); /* vo, f, fs, t0 */
difference(1,8,2); /* plus, minus, out */
freq_to_phase(2,3); /* in, out */
sing(11,PHIFREQ,180.0*PHIDEV); /* phase modulation input */
difference(3,11,4); /* in+, in-, output */
sample(4,6,UTIME,VPHI,0.0); /* in, out, utime, swing, err */
rcfilter(6,7,TAU1); /* in, out, tau */
vco(7,8,FVCO,FDEL); /* in, out, nom, del */
}

• notice similiarity to SPICE deck (numbered nodes)

• input “deck” parsing done by C-compiler
• user must assign nodes manually
63
 difference() and sine generator code

void difference(plus, minus, out) /* output node = plus - minus */

int plus, minus, out;
{
nodenew[out] = node[plus] - node[minus];
}

void sing(out, freq, ampl) /* a sinusoidal voltage source */

int out;
double freq,ampl;
{
nodenew[out] = ampl*sin(2.0*M_PI*simtime*freq);
}

64
 RC-filter implementation

void rcfilter(in, out, tau) /* a single pole rc filter */

int in, out; R
double tau; vin vout
{
double temp1, temp2; I = C dv/dt

/* Implements discrete diff. eqn:

Vout = Vin - (tau * dVout/dt)
where dVout = nodenew[out]-node[out] */

temp1 = node[in] + tau*(node[out])/stepsize;

temp2 = 1 + tau/stepsize;
nodenew[out] = (temp1/temp2);
}

65
 The freq_to_phase() block

void freq_to_phase(in, out) /* performs true integral of input */

int in, out; /* scaled by factor of 360. This */
/* gives output of 1 volt/degree */
{
double chunk; /* new integrated portion of signal */

chunk = (180.0 * (nodeold[in] + node[in]) * stepsize);

nodenew[out] = node[out] + chunk;

# now wrap it into the range of -180 to +180 degrees

if (nodenew[out] > 180)
nodenew[out] = nodenew[out]-360;
if (nodenew[out] < -180)
nodenew[out] = nodenew[out]+360;
}

66
 Lock Range for 1st-order loop
06:52Aug 1998
vcofreq
2490.0
MHz

fin
2484.0
200.0
Degrees

0.0
phierr

-200.0
5.0 10.0 15.0
time (µseconds)

67
 1st-order loop: locked region
06:52Aug 1998
2490.0
vcofreq
fin
MHz

2485.0
40.0

phierr
Degrees

0.0

-40.0
8.0 10.0 12.0
time (µseconds)

68
 1st-order loop: slew-rate limiting
2490.0 05:32Jul 1998
MHz

vcofreq
fin
2486.0
Degrees

0.0 phimod
dphi1

-200.0
Degrees

0.0 phierr

-100.0
5.0 6.0 7.0 8.0
time (µseconds)

69
 Summary of 1st-order loop
• Lock range: ( f nom + f bb ) < f c < ( f nom – f bb ) .
• Jitter (peak to peak): J pp ≈ 2 ⋅ 360 ⋅ t update ⋅ f bb .
• Maximum amplitude of phase modulation at frequency
f mod before onset of slew-rate limiting:

• If locked, then the duty cycle C ,

must result in the
average loop frequency being equal to the input
frequency f c ,
f c = f nom + ∆f = C ( f nom + f bb ) + ( 1 – C ) ( f nom – f bb )

• Phase detector average duty cycle C , given by

∆f 
 1--- + --------------------
- (proportional to ∆f ).
 2 ( 2 ⋅ f )
bb 70
 Observations
• Jitter generation, Lock range, and Jitter tolerance are all
inconveniently controlled by one parameter, f bb .
• Phase detector average duty-cycle is proportional to
frequency error.
• Strategy: Use the average duty cycle to control loop
center frequency. This decouples the lock range from
jitter tolerance/generation giving more design freedom.

71
 2nd-order BB loop
Proportional (BB) branch

β VCO

D Q Vφ Σ
Kvco
∫
1
--- v dt
τ

Integral branch

72
 2nd-order loop step response
tupdate

Vφ pd output

VφβKv BB frequency change

VφβKvt BB phase phase change

VφKvt/τ Integrator path frequency change

VφKvt2/2τ Integrator path phase change

73
 Stability Factor ξ

tupdate

phase change from BB path

phase change from integral path

To quantify the relative independance of the two feedback

loops, take ratio of phase change from BB path to the
phase change of the integral path:

∆θ bb βV φ K v t 2βτ
ξ ≡ ------------- = ---------------------------------- = ------------------
∆θ int 2 t update
V φ K v t ⁄ ( 2τ )
74
 structural evolution of 2nd-order loop
φmod
β
Fin
Σ ∫ v dt Σ Σ Kv
∫
1
--- v dt
τ
fsample

φmod
∫
βK v v dt
Fint θbb
Fin
∫
1
Σ ∫ v dt Σ Σ
Vφ
--- v dt
τ
Kv
∆F
∆θ1 ∆θ2 ∆θ3 fsample 75
 2nd-order loop: small step in F

2490.0 Fin
MHz

Fint
2487.0
40.0
degrees

∆θ1
∆θ3 θbb
0.0 3 3

2.0
1 1 1 1 1 1
volts

0.0 Vφ
1 1 1 1 1 1

-2.0
4.0 5.0 6.0 7.0
time (µseconds)
76
 2nd-order loop: large step in F

2500.0 Fin
MHz

Fint
2480.0
400.0
∆θ1 θbb
degrees

0.0
∆θ3
2.0
volts

0.0 Vφ
-2.0
4.0 5.0 6.0 7.0
time (µseconds)
77
 2nd-order loop: phase jitter tracking
100.0
∆θ1
2
1 2 1
degrees

2 3 2
0.0 3
1
3
2

∆θ2 1
φmod 1
-100.0 2

50.0
θbb ∆θ3
degrees

0.0

-50.0
∆θ2 2

2.0
volts

0.0 Vφ
-2.0
4.0 5.0 6.0 7.0
time (µseconds)

78
 2nd-order loop: slope overload
200.0
∆θ1
degrees

0.0
∆θ2 φmod
-200.0
100.0
θbb
degrees

0.0
1 ∆θ2 ∆θ3
-100.0
2.0
volts

0.0 Vφ
-2.0
4.0 5.0 6.0 7.0
time (µseconds)

79
 normalized ∆Σ form of 2nd-order loop
• pull integrators through the summing node
• normalize update interval to 1
• let βKvVφ = fbb
• substitute in definition for ξ

f bb

Fin ∆F ∆θ 2 f bb
Σ Σ ∫ v dt ±1 ∫ v dt ------------
ξ

t=0,1,2...
1st-order ∆Σ on ∆F 80
∆Σ linear system analogy for bb-loop

Σ H(z) Σ [Hau91b]
X(z) Y(z) [Gal95]
(integration)
Q(z)

H (z) 1
Y (z) = --------------------
- X (z) + - Q(z)
--------------------
1 + H (z) 1 + H (z)
gain

gain
freq freq 81
 solve for slope overload

f bb

Fin ∆F 1 ∆θ 1 2 f bb
Σ Σ --- --- ------------
s s ξ

• Slew rate limiting occurs when ∆F > fbb

• Maximum input phase modulation in UI, normalized
to ∆θbb is  s 2 + s + 2--- ⁄ ( s 3 + s 2 ) .
 ξ

82
 slope overload limit vs ξ
100G
max jitter before S.R.L [normalized to ∆θBB]

ξ=0.1  s 2 + s + 2--- ⁄ ( s 3 + s 2 )
1G  ξ
ξ=1
10M ξ=10
points shown
100k are from numerical
ξ=100 simulation

1k ξ=1000

10

0.1
1µ 10µ 100µ 1m 10m 0.1 1 10
jitter frequency * tupdate 83
 jitter generation in frequency-domain
• ∆Σ approximation justifies replacing BB phase detector
with a noise source.
• Combine total loop phase noise by combining each
phase noise source in RMS fashion.

source 1 Kv
phase Σ Σ β + ----- ------ Σ
output
sτ s
noise

BB phase noise VCO open loop phase noise

of form: Asin(x)/x

Kv
 1
H ( s ) = ------ β + -----
s  sτ 84
 example jitter generation calculation
0
-20
-40
dB

-60
-80 1 H (s)
--------------------- ---------------------
-100 1 + H (s) 1 + H (s)
-120
-80
dBc/Hz

-90 vco phase noise

-100
-110
-120 bb phase noise
source
-130 phase noise
-140
-80
dBc/Hz

-90 computed phase noise

-100
-110
-120 measured phase noise
-130
-140
1k 10k 100k 1M 10M 100M 1G
see [WSY97]: fvco=2.488 GHz, fbb = 6 MHz, ξ=32000, tupdate=400ps.
85
 The ultimate in simulator speed
• Compute precise transient response of system at
discrete update times with Laplace transforms.

f bb
2 f bb fv
±1 Σ ------------ ------
------
s 2 f bb vc ξs s
------------ -----
ξs s

t
bb bb
Φ ( t + 1 ) = Φ ( t ) ± b b + 2 ------ ∑ ( earlylate ) ± ------
ξ ξ
0
86
 simulator core loop
for (cycle=1; cycle<=numpoints; cycle++) {

data_phase = gauss()*jitter;

vco_phase += direction*bangbang;
vco_phase += 2.0*loop_filter*bangbang/psi;
vco_phase += direction*bangbang/psi;

printf(“%d %g\n”, cycle, vco_phase); fflush(stdout);

direction = (vco_phase >= data_phase) ? (-1) : (1);

loop_filter += direction;
}

87
 gaussian jitter generation & gain vs ξ
10M
RMS output jitter [normalized to θBB]

ξ = 1e-06
1M
ξ = 1e-05
100k
ξ = 1e-04
10k
ξ = 0.001
1k
ξ = 0.01
100
ξ = 0.1
10
ξ=1 Jidle = 0.6+(1.65/ξ)
Jlin = 2*Jin/(1+sqrt(ξ))
1 ξ = 10 Jwalk = 0.7*sqrt(Jin)
Jtot = Jidle + Jlin +Jwalk
0.1
1m 10m 0.1 1 10 100 1k 10k 100k 1M
RMS input jitter [normalized to θBB]
88
( non-tristated loop , ptransition = 100% , 10 timesteps simulated per point)
8
 Stability with run-length & latency
Slope(t=0) = S
∆1 ε2/ξ - Sε

0 ∆0 ε
For bounded convergence and stable operation, the
overshoot ∆1 must be less than or equal to the
undershoot ∆0. This condition is guaranteed if
ξ > 2ε
(ε is the loop update latency normalized to tupdate)
89
 Effect of BB/charge-pump tristating
jitter [normalized to θBB]

15
10 tristated loop
5
0
-5
-10 non-tristated
-15
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
timestep [normalized to bit time]

•tristating doesn’t change 12

vco frequency when no
8
transition in the data.
4
•Untristated loop has peak 0
jitter run-length times -4
worse than tristated loop
(simulated with ξ=100, ptransition = 50% )
8880 8920 8960 9000 90
 Public Domain Tools
Linux (a free UNIX clone for INTEL x86 platforms) - Excellent
platform for creative circuit design and simulation. See
www.cheapbytes.com for a $1.95 distribution CD.
•Homepage: http://www.linux.org/
•Documentation: http://sunsite.unc.edu/mdw/LDP
•Scientific Apps: http://SAL.KachinaTech.COM/index.shtml
• ACS Circuit simulator
• EOS Electronic Object Simulator
• Berkeley SPICE 3f5 (bsim3 models)
• SCEPTRE
91
 Summary
A lot of complexity for a “simple” system...
It’s more of an art than a science
After understanding:
• the components,
• the block diagrams,
• the problems and the attempted solutions,
• and the unique needs for your application,
Then it’s time to have fun!

92
 CDR Application Space

Telecom 7% Datacom 26%

Fiber 3% Copper 3%
Radio
coax 23% tp

pcb 0.5%
IR
Other (disk 3%)
numbers estimated from ~250 attendees at February 1997 ISSCC CDR tutorial
 CDR Design Checklist
RCW 01/15/97, updated 9/18/98
1) Eye Margin
• how much noise can be added to the input signal while maintaining target BER?
(voltage margin)
• How far can clock phase alignment be varied while maintaining target BER? (phase
margin)
• how much does the static phase error vary versus frequency, temperature and
process variation?
• Is input amplifier gain, noise and offset sufficient?
2) Jitter Characteristics
• what is the jitter generation? (VCO phase noise, etc)
• what is the jitter transfer function? (peaking and bandwidth)
• what is the jitter tracking tolerance versus frequency?
3) Pattern Dependency
• how do long runlengths affect system performance?
• is bandwidth sufficient for individual isolated bit pulses?
 • are there other problematic data patterns? (resonances)
• does PLL bandwidth, jitter, and stability change versus transition density?
4) Acquisition Time
• what is the initial, power-on lock time?
• what is the phase-lock aquisition time when input source is changed?
5) How is precision achieved?
• are external capacitors, inductors needed?
• does the CDR need an external reference frequency?
• are laser-trimming or highly precise IC processes required?
6) Input/output impedance
• Is S11/S22 (input/output impedance) maintained across the frequency band?
• are reflections large enough to lead to eye closure and pattern dependency?
• is >15 dB return loss maintained across the band?
7) Power Supply
• does the CDR create power supply noise?
• how sensitive is the CDR to supply noise?
• Is the VCO self-modulated through its own supply noise? (can be “deadly”)
 • what is the total static power dissipation?
• what is the die temperature under worse case conditions?
8) False lock susceptibility
• can false lock occur with particular data patterns?
• are false lock conditions be detected and eliminated?
• does the phase detector have VCO frequency leakage that can cause injection
locking?
• can the VCO run faster than the phase/frequency detector can operate? (another
“killer”)
• have all latchup/deadly embrace conditions been considered and eliminated?
 References
[Ale75] Alexander, J. D. H., Clock Recovery from Random Binary Signals, Electronics Letters 11, 22 (30th October 1975), 541-542. {binary
quantized phase detector}.
[AFD87] Andrews, G. E., D. C. Farley, S. H. Dravitz, A. W. Schelling, P. C. Davis and L. G. McAfee, A 300Mb/s Clock Recovery and Data
Retiming System, ISSCC Digest of Technical Papers, 1987, 188-189. {SAW Filter Clock Recovery with emphasis on phase alignment
problem}.
[Arm83] Armitage, C. B., SAW Filter Retiming in the AT&T 432 Mb/s Lightwave Regenerator, Conference Proceedings: AT&T Bell Labs.,
Holmdel, NJ, USA, September 3-6, 1984, 102-103. {matches tempco of SAW to tempco of electronics.}.
[Baa86] Baack, C., Optical Wide Band Transmission Systems, CRC Press Inc., 1986. {example of PLL for clock recovery}.
[Buc92] Buchwald et al., A., A 6GHz Integrated Phase-Locked Loop using AlGaAs/GaAs Heterojunction Bipolar Transistors, ISSCC Digest
of Technical Papers, 1992, 98,99,253. {Frequency multiplying ring oscillator}.
[Byr63] Byrne et al., C. J., Systematic Jitter in Chain of Digital Regenerators, The Bell System Technical Journal, November 1963, 2679.
{clock extraction by filtering}.
[CCI90] CCITT, Digital Line systems based on the synchronous digital hierarchy for use on optical fiber cables, CCITT G.958, 1990.
{SONET Payload test patterns regenerator scrambling}.
[Car56] Carter, R. O., Low-Disparity Binary Coding System, Electronics Letters 1, 3 (May, 1956), 67-68. {conditional inversion data encod-
ing disparity}.
[Cho92] Chona, F. M. R., Draft Standard, SONET inter-office and intra-office line jitter re., T1X1.3, May 11, 1992. {Standards SONET jitter}.
[Con84] Connor et al., P. O., A Monolithic Multigigabit/Second DCFL GaAs Decision Circuit, IEEE Electron Device Letters EDL-5, 7 (July
1984), 226-227. {GaAs Fet decision circuit example}.
[Cor79] Cordell et al., R. R., A 50MHz Phase and Frequency Locked Loop, IEEE Journal of Solid State Circuits SC-14, 6 (December 1979),
1003-1009. {quadricorrellator phase detector, Tunable LC Oscillator}.
[DR78] D’Andrea, N. A. and F. Russo, A Binary Quantized Digital Phase Locked Loop: A Graphical Analysis, IEEE Transactions on Com-
munications COM-26, 9 (September 1978), 1355-1364. {Analysis of BB loop}.
[DeV91] DeVito et al., L., A 52 MHz and 155MHz Clock-Recovery PLL, ISSCC Digest of Technical Papers, February 13-15, 1991, 142, 143,
306. {multivibrator example, Negative resistor chargepump, rotational freq.det.}.
[Den88] Den Dulk, R. C., Digital Fast Acquisition Method for Phase-Lock Loops, Electronics Letters 24, 17 (18th August 1988), 1079-1080.
{2 order of magnitude locking speed-up with fancy slip detector & charge pump}.
[EnA87] Enam, S. K. and A. A. Abidi, Decision and clock Recovery Circuits for Gigahertz Optical Fiber Receivers in Silicon NMOS, Journal
of Lightwave Technology LT-5, 3 (March 1987), 367-372. {MOS tunable monolithic ring oscillator example - Some clever circuit
ideas for gigabit rates}.
[EnA92] Enam, S. K. and A. A. Abidi, MOS Decision and Clock Recovery Circuits for Gb/s Optical-Fiber Receivers, ISSCC Digest of Techni-
cal Papers, 1992, 96,97,253. {quadratic phase detector} {MOS decision circuit example}.
[FHH84] Faulkner, D. W., I. Hawker, R. J. Hawkins and A. Stevenson, An Integrated Regenerator for High Speed Optical Fiber Transmission
Systems, IEE Conference Proceedings (November 30 - December 1, 1983) 8-13. {uses rectifier/SAW combo}.
[FLS63] Feynman, R., R. B. Leighton and M. Sands, The Feynman Lectures on Physics, Addison-Wesley Publishing Company, 1963. {Short,
simple presentation of timestep analysis for planetary motion}.
[FMW97] Fiedler, A., R. Mactaggart, J. Welch and S. Krishnan, A 1.0625Gbps Transceiver with 2x-Oversampling and Transmit Signal Pre-
Emphasis, ISSCC Digest of Technical Papers 40 (February 6-8 1997), 238,239,464. {transmit pre-emphasis, skin loss equalizer}.
[Gal94] Galton, I., Higher-order Delta-Sigma Frequency-to-Digital Conversion, Proceedings of IEEE International Symposium on Circuits
and Systems (May 30 - June 2, 1994) 441-444 {Delta-Sigma BB loops phase tracking frequency digitalization PLL}.
[Gal95] Galton, I., Analog-Input Digital Phase-Locked Loops for Precise Frequency and Phase Demodulation, Transactions on Circuits and
Systems-II: Analog and Digital Signal Processing 42, 10 (October 1995), 621-630. {good discussion of delta-sigma analysis of BB
PLL’s}.
[Gar79] Gardner, F. M., Phaselock Techniques, Second Edition, John Wiley and Sons, Inc., 1979. {example of using exor-gate to generate
clock component from NRZ data}.
[Gla85] Glance, B. S., New Phase-Lock Loop Circuit Providing Very Fast Acquistion Time, IEEE Transactions on Microwave Theory and
Techniques MTT-33, 9 (September 1985), 747-754. {adds non-linear time constant to speed PLL acquisition by 2 orders of mag.}.
[Gri69] Griffiths, J. M., Binary Code Suitable for Line Transmission, Electronics Letters 5, 4 (February 20, 1969), 79-81. {5b/6b encoding
example}.
[GMP78] Gruber, J., P. Marten, R. Petschacher and P. Russer, Electronic Circuits for High Bit Rate Digital Fiber Optic Communication Sys-
tems, IEEE Transactions on Communications COM-26, 7 (July 1978), 1088-1098.
[Gup75] Gupta, S. C., Phase-Locked Loops, Proceedings of the IEEE 63, 2 (February 1975), 291-306. {Good systematic outline survey of
communication-type PLL’s}.
[Hau91a] Hauenschild et al., J., A Silicon Bipolar Decision Circuit Operating up to 15Gb/s, IEEE Journal of Solid State Circuits 26, No.11
(November 1991), 1734-1736. {Si bipolar decision circuit example}.
[Hau91b] Hauser, M. W., Principles of Oversampling A/D Conversion, J. Audio Eng. So. Vol 39, 1/2 (Jan/February 1991), 3-26. {excellent tuto-
rial on Delta Sigma AD, Oversampling, noiseshaping}.
[HeS88] Hein, J. P. and J. W. Scott, z-Domain Model for Discrete-Time PLL’s, IEEE Transactions on Circuits and Systems 35, 11 (November
1988), 1393-1400. {good discussion of using z-transforms in PLL analysis}.
[Hog85] Hogge, Jr., C. R., A Self Correcting Clock Recovery Circuit, IEEE Transactions on Electron Devices ED-32, 12 (December 1985),
2704-2706. {Original Hogge detector, interesting phase detector idea...}.
[Hor92] Hornak, T., Interface Electronics for Fiber Optic Computer Links, Intensive Course on Practical Aspects in Analog IC Design, Lau-
sanne, Switzerland, June 29-July 10, 1992. {Excellent overview of components for serial optical data transmission}.
[Hu93] Hu, T. and P. Gray, A Monolithic 480 Mb/s AGC/Decision/Clock Recovery Circuit in 1.2 um CMOS, IEEE Journal of Solid State
Circuits 28, 12 (Dec. 1993) 1314-20 {CMOS parallel signal paths multiphase sampling CDR mux}.
[Kas85] Kasper et al., B. L., SAGM Avalanche Photodiode Optical Receiver for 2 Gbit/s and 4 Gbit/s, Electronic Letters 21, 21 (10th October
1985), 982-984. {eye diagram}.
[KWG94] Kim, B., T. C. Weigandt and P. R. Gray, PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design, ISCAS proceed-
ings, May 30 - June 2, 1994, 31-34. {Excellent and Intuitive discussion of Jitter in Ring Oscillators}.
[Lai90] Lai, B., Decision Circuit Lowers Transmission Bit Error Rates, Microwaves and RF, July 1990, 118- 122. {Si bipolar decision circuit
example}.
[LaW91] Lai, B. and R. C. Walker, A Monolithic 622Mb/s Clock Extraction Data Retiming Circuit, ISSCC Digest of Technical Papers 34 (Feb-
ruary 13-15, 1991), 144,145. {binary quantized phase detector}.
[Lam93] Lam, V. M. T., Microwave Oscillator Phase Noise Reduction Using Negative Resistance Compensation, Electronics Letters 29, 4
(February 18th, 1993), 379-340. {Leeson negative resistance phase noise second harmonic IC}.
[LiC81] Lindsey, W. C. and C. M. Chie, A Survey of Digital Phase-Locked Loops, Proceeding of the IEEE 69, 4 (April 1981), 410-431. {Pre-
sents a good taxonomy of digital PLLs}.
[Mac87] MacDougall, M. H., Simulating Computer Systems - Techniques and Tools, The MIT Press, Cambridge, Massachusetts, 1987.
{description and source code for event driven simulator}.
[McG90] McGaughey, J. T., Convert NRZ format to Biphase, Electronic Design, April 12, 1990, 86. {biphase example}.
[OFC84] O’Connor, P., P. G. Flahive, W. Clemetson, R. L. Panock, S. H. Wemple, S. C. Shunk and D. P. Takahashi, A Monolithic Multigigabit/
Second DCFL GaAs Decision Circuit, IEEE Electron Device Letters EDL-5, 7 (July 1984),. {2.4 GHz ED GaAs Mesfet Flip-flop w/
input buffer amp}.
[Ofe89] Ofek, Y., The Conservative Code for Bit Synchronization, IEEE Transactions on Communications, 1989. {conserves transition num-
ber uses divider for clock recovery}.
[OhT83] Ohta, N. and T. Takada, High Speed GaAs SCFL Monolithic Integrated Decision Circuit for Gb/s Optical Repeaters, Electronics Let-
ters, September 1983. {GaAs Decision Circuit}.
[Par89] Park et al., M. S., Novel Regeneration Having Simple Clock Extraction and Automatic Phase Controlled Retiming Circuit, Electronic
Letters 25 (January 1989), 83-84. {clock extraction by filtering}.
[Pet88] Petrovic, R., Low Redundancy Optical Fiber Line Code, Journal of Optical Communication 9, 3 (1988), 108-111. {13B/14B code
design}.
[RaO91] Ransijn, H. and P. O’Connor, A PLL-Based 2.5-Gb/s GaAs Clock and Data Regenerator IC, JSSC 26, 10 (October 1991), 1345-1353.
{Rotational frequency detector, Limiting Amp, Jitter Transfer Measurement}.
[Raz96a] B. Razavi, ed., Monolithic phase-locked loops and clock recovery circuits: theory and design, IEEE Press, 1996. {A volume of
selected reprints with bibliography}.
[Raz96b] Razavi, B., Monolithic Phase-Locked Loops, ISSCC Tutorial, San Francisco, CA, February 7, 1996. {Good overview of non-data-
driven PLL theory}.
[ReG73] Reddy, C. P. and S. C. Gupta, A Class of All-Digital Phase Locked Loops: Modeling and Analysis, IEEE Transactions on industrial
Electronics and Control Instrumentation IECI-20, 4 (November 1973), 239-251. {discusses of binary-quantized phase detection}.
[RCF84] Rosenberg, R. L., C. Chamzas and D. A. Fishman, Timing Recovery with SAW Transversal Filters in the Regenerators of Undersea
Long-Haul Fiber Transmission Systems, Journal of Lightwave Technology LT-2, 6 (December 1984), 917-925. {discusses jitter accu-
mulation}.
[Ros84] Rosenberg et al., R. L., Timing Recovery with SAW Transversal filters in the Regenerators of Undersea Long-haul Fiber Transmis-
sion Systems, IEEE Journal of Lightwave Technology LT-2, 6 (December 1984), 917-925. {clock extraction by SAW}.
[Ros85] Ross, F. E., An Overview of FDDI: the Fiber Distributed Data Interface, IEEE Journal on Selected Areas in Communications 7, 7
(September 1985), 1046, Table 1. {4b/5b encoding example, example of frame synch characters}.
[RHF90] Ross, F. E., J. R. Hamstra and R. L. Fink, FDDI - A LAN among MANs, ACM Computer Communications Review, July 1990, 16-31.
{4b/5b encoding example}.
[Rou76] Rousseau, M., Block Codes for Optical-Fibre Communication, Electronics Letters 12, 18 (2nd September 1976), 478-479. {mBnB
code discussion, run length limits, power spectra, 5b6b recommended}.
[RoM77] Roza, E. and P. W. Millenaar, An Experimental 560 MBit/s Repeater with Integrated Circuits, IEEE Transactions on Communications
COM-25, 9 (September 1977),. {coax-based. good comparison of PLL vs filter-type clock extraction}.
[RuG91] Runge, K. and J. L. Gimlett, 20Gb/s AlGaAs HBT Decision Circuit IC, Electronics Letters 27, 25 (5th December 1991), 2376-2378.
{GaAs HBT decision circuit example}.
[Run91] Runge et al., K., Silicon Bipolar Integrated Circuits for Multi-Gb/s Optical Communication Systems, IEEE Journal on Selected Areas
in Communications 9, 5 (June 1991), 640. {Si bipolar decision circuit example}.
[San82] Sandera, L., Improve Datacomm Links by Using Manchester Code, EDN, February 17, 1982, 155-162. {manchester coding exam-
ple}.
[Shi87] Shin et al., D., Selfcorrecting Clock Recovery Circuit with Improved Jitter Performance, Electronics Letters 23, 3 (29th January
1987), 110-111. {Improved Hogge detector}.
[SyA86] Syed, K. E. and A. A. Abidi, Gigahertz Voltage Controlled Oscillator, Electronics Letters 22 (June 5, 1986), 677-679. {MOS tunable
monolithic ring oscillator example}.
[TrV89] Trischitta, P. R. and E. L. Varma, Jitter in digital transmission systems, Artech House, Inc., 1989. {good overview of jitter (textbook)
ISBN 0-89006-248-X}.
[Wal89] Walker, R. C., Fully Integrated High Speed Voltage Controlled Ring Oscillator, U.S. Patent 4,884,041, Granted Nov. 28, 1989. {Si
bipolar tunable monolithic ring oscillator example}.
[WHY91] Walker, R. C., T. Hornak, C. Yen, J. Doernberg and K. H. Springer, A 1.5Gb/s Link Interface Chipset for Computer Data Transmis-
sion, IEEE Journal on Selected Areas in Communications 9, 5 (June 1991), 698-703. {binary quantized phase detector with master
transition}.
[WWS92] Walker, R., J. Wu, C. Stout, B. Lai, C. Yen, T. Hornak and P. Petruno, A 2-Chip 1.5Gb/s Bus-Oriented Serial Link Interface, ISSCC
Digest of Technical Papers 35 (February 19-21 1992), 226,227,291. {MT Code, Ring Osc} binary quantized phase detector with mas-
ter transition}.
[WSY97] Walker, R., C. Stout and C. Yen, A 2.488Gb/s Si-Bipolar Cloc k and Data Recovery IC with Robust Loss of Signal Detection, ISSCC
Digest of Technical Papers 40 (February 6-8 1997), 246,247,466. {training loop, loss of signal detection, bb-loop, ring oscillator}.
[WHK98] Walker, R. C., K. Hsieh, T. A. Knotts and C. Yen, A 10Gb/s Si-Bipolar TX/RX Chipset for Computer Data Transmission, ISSCC
Digest of Technical Papers 41 (February 5-7 1998), 302,303,450. {multi-phase architecture, 8-phase VCO, ft-doubler amplifier, bb-
loop}.
[WKG94] Weigandt, T. C., B. Kim and P. R. Gray, Analysis of Timing Jitter in CMOS Ring Oscillators, ISCAS proceedings, May 30 - June 2,
1994. {Excellent and Intuitive discussion of Jitter in Ring Oscillators}.
[WiF83] Widmar, A. X. and P. A. Franaszek, A DC Balanced, partitioned-Block 8B/10B Transmission Code, IBM Journal of Research and
Development 27, 5 (September 1983), 440-451. {8b/10b encoding example - Precursor to Fiber Channel’s 8B/10B code}.
[Wu92] Wu, J. and R. C. Walker, A Bipolar 1.5Gb/s Monolithic Phase Locked Loop for Clock and Data Extraction, VLSI Circuit Symposium,
Seattle, June 3-5, 1992. {positive feedback PLL loop filter}.
[YTY80] Yamada, J., J. Temmyo, S. Yoshikawa and T. Kimura, 1.6 Gbit/s Optical Receiver at 1.3um with SAW Timing Retrieval Circuit, Elec-
tronics Letters, 1980, 57-58. {basic SAW system, with discussion of power penalty for SAW phase shifts}.
[Yam80] Yamada et al., J., 1.6Gb/s Optical Receiver at 1.3um with SAW Timing Retrieval Circuit, Electronics Letters 16, 2 (17th January
1980), 57- 58. {clock extraction by SAW}.
[YFW82] Yen, C., Z. Fazarinc and R. Wheeler, Time-domain skin-effect model for transient analysis of lossy transmission lines., Proceedings
of the IEEE 70, 7 (July 1982), 750-757. {skin-effect lossy transmission line transient simulation modelling}.
[YKI84] Yoshikai, N., K. Katagiri and T. Ito, mB1C Code and its Performance in an Optical Communication System, IEEE Transactions on
Communications COM-32, 2 (February 1984). {uses m binary bits + one complementary bit stuffed to break runs}.