Clock and Data Recovery for Serial Digital Communication

focusing on bang-bang loop CDR design methodology ISSCC Short Course, February 2002

Rick Walker Agilent Laboratories Palo Alto, California

[email protected]

Outline

Overview of serial data communications

Degradation mechanisms, data coding Jitter measurements

Clock recovery methods Linear PLL review and components BB PLL theory

Diversity of CDR applications

Network Interface cards 7-12

CPU

CPU

CPU

CPU

Network Interface cards 1-6

10G

10G

10G

10G

10G

Crossbar Switch

I/O
CPU packet processor

MEM

MEM

MEM

MEM
Backplane

Crossbar Switch Board

Linecard to Router

CPU-CPU/Memory

Clock and Data Recovery applications span the range

from high-volume, low-cost datacom applications to high-performance, long-haul telecom applications

Many different trade-offs tailor each circuit to the target

3

CDR data rates over time

50G 20G RDP01(4x) 50M 20M

5G 2G 1G 500M 200M 100M 50M 20M

His

~PCB skinloss limit

SoA93

nd WWS92 r Tre ipola f T) Si B -0.4 WaL91 EWS95(2x) 0.05 ( d HuG93(8x) Tren d iGe ren S S T DNG91 MO C IsA94
LeB92 LeS88

MSS99 UWK01 GSS00a YaH96(8x) WSY97 GTL99(10x) ChB97(10x) Lar99 WaN99 FMW97(10x) LYK96(8x)

5M 2M 1M 500k 200k

GHW94

CMOS Si Bipolar SiGe

100k 50k 20k

number of CDR retiming phases givien in () 1988 1990 1992 1994 1996 1998 2000 2002

Year of Publication (ISSCC)

Internet Host Count 4

Serial Link Speed

10G

al toric

lim CDR

it

HDW96(2x) PoL94

WHK98(4x)_ MPA00

10M

TX/RX Gb/W and

Link speed per unit Power [Gb/Watt] 20
1Tb/s in 40W

2 Gb/mm
GTL99
1Tb/s in 1.8cm2

10 8 6 4
ChB97

UWK01 FMW97

2 1 0.8 0.6 0.4 0.2

10m

WHK98
EWS95 GHW94 WWS92
CMOS Si Bipolar SiGe

20m 50m 0.1 0.2 0.5 1 2 Link speed per unit diesize [Gb/square-mm]

Circuit power and die size can be system-limiting factors. Gb/W and Gb/mm2 are plotted for complete TX/RX designs published between ISSCC92 and 2001. Dashed lines represent an agressive chip supporting 1Tb/s in a total of 40W and 1.8cm2. 5

Basic Idea
Serial data transmission sends binary bits of information as a series of optical or electrical pulses:
0111011000111110011010010000101011101100011111..

The transmission channel (coax, radio, ber) generally distorts the signal in various ways:

From this signal we must recover both clock and data 6

Some Signal Degradation Mechanisms

AC coupling droop, baseline wander Optical pulse dispersion Skin / dielectric loss Random noise E+O crosstalk Intersymbol interference Connector discontinuities
[YFW82, WWS92, FMW97]

Coding for Desirable Properties

DC balance, low disparity Bounded run length High Coding Efciency Spectral Shaping (eg: reduce BW or DC component)

Many Variations are Possible!

Manchester [San82] mB/nB [Gri69][Rou76][WiF83] [YKI84] [Pet88] Scrambling: SONET, 64b/66b [CCI90] CIMT [WHY91], Conservative Code [Ofe89] 8

Bit Error Rate (BER) Testing

Pseudo-Random-Bit-Sequence (PRBS) is used to simulate random data for transmission across the link PRBS pattern 2N-1 Bits long contains all N-bit patterns Number of errored-bits divided by total bits = BER. Typical links are designed for BERs better than 10-12 PRBS data receiver clock in 9

PRBS data generator clock in

TX link synth

RX

Eye diagram construction

random data scope TX link synth trigger
symbol cell (UI) Y
Use a precise clock to chop the data into equal periods

RX

overlay each period onto one plot

jitter

Y amplitude distribution at Y-Y

10

Denition of Jitter
unit interval

-3T -2T -T 0 T 2T 3T 4T Impulses spaced equally in time (jitter free signal)

time

-3T -2T -T 0 T 2T 3T 4T Impulses spaced irregularly in time (jittered signal)

Errors treated as discrete samples of continuous time jitter

After Trischitta and Varma: Jitter in Digital Transmission Systems

11

Jitter Measurements

12

Jitter Measurements

Datacom Style: Ethernet + Fiber Channel based on time-domain eye diagrams

Deterministic Jitter Random Jitter

Telecom Style: SONET based on frequency-domain jitter spectrums

Jitter Tolerance Jitter Transfer Jitter Generation 13

Deterministic and Random Jitter

Random Jitter (RJ) data source is simple repetitive clock-like pattern. RMS jitter is measured at zero crossings of eye-diagram measured jitter is mostly due to clock noise Deterministic Jitter (DJ) data source is complex scrambled data pk/pk jitter is measured at zero crossings of eye-diagram RJ contribution is subtracted from the measurement measured jitter is mostly due to bandwidth limitations in the
data path. 14

Jitter Tolerance Test Setup

laser transmitter data generator optical attenuator optical receiver xamp + limiter decision circuit retiming circuit bit error rate tester

FM modulated clock

sine wave generator

At each frequency, the sinewave modulation amplitude is increased until the BER penalty is equal to that caused by 1dB optical attentuation 15

After Trischitta and Varma: Jitter in Digital Transmission Systems

SONET Jitter Tolerance Mask

15 UI 1.5 UI 0.15 UI f0
Data Rate OC-3 OC-12 OC-48 OC-192 155 Mb 622 Mb 2.488 Gb 10 Gb Typical measurement data This point is usually the most difcult for many designs

f1

f2
f0[Hz] 10 10 10 10

f3
f1[Hz] 30 30 600 2400

ft
f2 [Hz] 300 300 6000 24000 f3 [kHz] 6.5 25 100 400 ft [kHz] 65 250 1000 4000

from SONET SPEC: TA-NWT-000253 Issue 6, Sept. 1990, g 5-13

16

Jitter Transfer Measurement

data generator decision circuit clock retiming circuit D.U.T.
OutputJitter ( f ) JTF ( f ) = 20 log ----------------------------------------- InputJitter ( f )

Phase detector

Signal Generator

Phase modulator

IN

OUT

[TrV89] [RaO91]

network analyzer 17

Jitter Transfer Specication

P[dB] slope = -20 dB/decade 0dB acceptable range

fc
Data Rate 155 Mb 622 Mb 2.488 Gb fc[kHz] 130 500 2000 P[dB] 0.1 0.1 0.1

This specication is intended to control jitter peaking in long repeater chains 18

Jitter Generation

output stage

computer

clock circuit D.U.T.

spectrum analyzer

generated clock 19

Jitter Generation (cont.)

1) Measure Jitter Sidebands around Clock
V sideband Jitter pp ( rads ) = 2 2 atan ------------------------- V clock

sideband clock amplitude

2) Multiply Jitter components by Filter Mask 3) RMS sum total noise voltages over band 4) Convert RMS noise voltage to RMS jitter

OC-48 (2.488 Gb/s SONET) species 12 kHz hipass lter, and maximum 0.01 UI RMS integrated jitter. 20

res

ulta

nt

Clock Recovery Concepts

21

NRZ and RZ signalling

NRZ = non return to zero data no clock frequency in spectrum clock frequency clock frequency appears in spectrum

RZ = return to zero data

T NRZ signalling is almost universally used.

22

Spectrum of NRZ data

variations due to DC balance strategy

missing clock frequency power in dB

sin ( 2fT ) -----------------------2 fT

Fc- Fc+

f = 0

1T

2T

23

Filter Method Examples

d dt X
2

bandpass lter e.g.: SAW lter bandpass lter LC tank Recovered Clock Output

NRZ Data Input

non-linear element delay

[Yam80][YTY80] [RFC84][Ros84] [FHH84][AFK87]

(this last circuit can be thought of as an NRZ-RZ converter) 24

Summary of Filter Method

Jittered NRZ Data Signal

Retimed Data D Q

d dt

bandpass lter/limiter Con: Temperature and frequency variation of lter group delay makes sampling time difcult to control Narrow pulses imply high fT Hi-Q lter difcult to integrate 25

Pro: Very simple to implement Can be built with microwave tinkertoys using coax to very high frequencies

Q-Factor in resonant circuits

Voltage envelope of ringing circuit falls to 1/sqrt(e) in Q radians. 1.0 1.0/sqrt(e)

Q also equals the center frequency of a lter divided by the full-width of the resonance measured at the half power points: Fcenter/

amplitude

Q/2*PI cycles

Fcenter

High-Q lter can be emulated by PLL with low loop B.W.

26

Data recovery with simple PLL

D Jittered Data Signal Phase Detector PLL Low-pass Loop Filter Voltage Controlled Oscillator Q Retimed Data

Everything in the simple PLL is easily integrable. The remaining problem is to match the recovered clock phase to the middle of the data eye. This can be difcult to achieve over all process variation at very high datarate/ft ratios.

27

Analytic Treatment of Jitter

Perfect Clock: x ( t ) = A cos c t

Jittered Clock: x ( t ) = A cos [ c t + ( t ) ]

plot of the zero crossing arrival time phase error

Jitter Signal: x(t ) = (t ) Practically, ( t ) is only measured at zero crossings, but is treated as a continuous time signal.
After Behzad Razavi: Monolithic Phase-Locked Loops, ISSCC96 Tutorial

28

Model of linear phase-locked loop

Phase Detector Loop Filter

VCO

K
( 1 + s ) ---------------------( 1 + s )

Kv

1 -s

Warning: Extra integration in VCO complicates the design!

See Floyd M. Gardner, Phaselock Techniques, John Wiley and Sons, for good introduction to PLL theory

29

Linear loop frequency response a

(input jitter)
K
( 1 + s ) ---------------------( 1 + s ) Kv -----s

c b

80dB 40dB 0dB -40dB -80dB 1k 10k 100k

open loop gain

(c/a, with loop broken at X)

c/a

c/b

1M

10M

100M

1G

10G

30

Decision Circuit
Quantizes amplitude at precise sample instant and
typically uses positive feedback to resolve small input signals

A common choice in bipolar processes is a master/slave

D-ip-op carefully optimized for input sensitivity and clock phase margin

To avoid hysteresis in CMOS processes, it is common to

use a sense amp which is reset prior to each data sample

simplied schematic symbol:

D Q clock

31

Example Bipolar Decision Circuit

master latch slave latch gnd data in data out clock in Vbias -5V

many clever optimizations are possible

[OhT83][Con84][Lai90][Run91][Hau91]

32

VCO alternatives
LC Oscillator Speed Phase Noise Integration Multivibrator Ring Oscillator

Technology Dependent 1-10s of GHz Good Poor (L, Varactor) Narrow/Slow Good Poor Excellent

Tunability Stability

Wide/Fast Poor (needs acquisition aid) Multi-Phase Clocks

Other

[Cor79, Ena87, Wal89, DeV91, Lam93, WKG94] 33

After Todd Weigandt, B. Kim, P.Gray, Timing Jitter Analysis for High-Frequency CMOS Ring Oscillators, March 10, 1994

Multivibrator VCO
Capacitor is alternately charged and discharged by constant current Tuned by varying Itune in current source Diode clamps keep output voltage constant independent of frequency Relies on non-linear switching for oscillation behavior, and so is limited to moderate frequencies. Itune Frequency =
I tune ---------------4CV be

After Alan B. Grebene, Analog Integrated Circuit Design, Van Nostrand Reinhold, 1972, pp 313-315

34

Example Ring Oscillator VCO

Input 1 Output Tune Input 2 Input 1 Output [SyA86] [EnA87] [Wal89]

Inpu
Input 1 Tune Input 2 Output

t2

35

False or Harmonic Locking to Data

data clock 1/2 clock 2x clock 4/3 clock early/late indications cancel in loop lter, leaving an attenuated, but possibly stable lock signal. correct early late correct 36

Aided Acquistion

Tricky task due to Nyquist sampling constraints caused by stuttering data transitions PD Input Data VCO FD loop lter 2 loop lter 1

Still subject to false lock if VCO range is too wide 37

After Behzad Razavi: Monolithic Phase-Locked Loops, ISSCC96 Tutorial

Training Loops
retimed data Input PDET SEL bang-bang drive
charge pump

Data

Clock
VCO

Reference Clock 2.488GHz/256 FDET

dlock dtrans ock

State Machine

LOS

[WSY97]
Clock/256
1/256 divider

An increasingly common technique is to provide a reference clock to the CDR circuit. This allows the VCO process-variation to be dynamically trimmed out, avoiding false locking problems. 38

Phase Detectors

Phase detectors generate a DC component proportional to deviation of the sampling point from center of bit-cell Phase detectors are:

Continuous
90 180 90 0 180

Binary Quantized

After [Hor92].

Binary quantized phase detectors are also called Bangbang, or early-late phase detectors 39

Self-Correcting Phase Detector

Data Clock
1 = Data................. 2= Clock (Early)..... 3 = 1 retimed.......... 4 = Clock................. 5 = 3 retimed.......... 6 = 1 xor 3 (UP)..... 7 = 3xor 5 (DOWN)

UP DOWN
D Q D Q

[Hog85][Shi87]

Data

The Hogge detector is typical of linear phase detectors. It operates by creating pulses whose widths are equal to the phase error of the incoming data. These pulses may be difcult to produce at high speeds.

40

Early-Late Phase Detector

NRZ data is sampled at each bit cell and near the transitions of each bit cell Transition sample polarity is compared with preceeding and following bits to deduce the phase error. Output is binary quantized, early-late phase indications, or ternary quantized if a hold-state is implemented.
D Q D Q

Data Clock

B A A T B

D Q

D Q

T
latch

[Ale75][WHY91] [LaW91][ReG73]

ipop

A 0 0 0 0 1 1 1 1

T 0 0 1 1 0 0 1 1

B 0 1 0 1 0 1 0 1

Output hold vco fast ? vco slow vco slow ? vco fast hold

41

BB/charge-pump w/wo hold state

jitter [normalized to BB] 15 10 5 0 -5 -10 -15
0

loop with hold

w/o hold mode

1000 2000 3000 4000 5000 6000 7000 8000 9000 10000

timestep [normalized to bit time]

hold-mode maintains VCO

frequency when transitions are absent in the data.

12 8 4 0 -4 8880 8920 8960 9000

loop w/o hold has peak

jitter run-length times worse than loop w/hold
(simulated with =100, ptransition = 50%)

42

Loop Filters
[Den88] [Dev91] [LaW91] [WuW92] VOUT
UP 0 0 DOWN 0 1 0 1 VOUT hold ramp DOWN ramp UP hold

UP

DOWN

1 1

should have provision for holding value constant under long run-length conditions may be analog (integrator) or digital (up-down counter) - but watch out for metastability!

43

Bang-bang PLL Theory

44

Why bother with a BB loop?

it may be difcult to maintain optimum sampling point
with traditional PD/PLL or with lter method over process, temperature and supply variation

Narrow pulses of linear PDs may not work well at

extremely high bit rates

for monolithic implementation, BB PD has excellent

match between retiming latch and PD latch - allows for operation at highest latch toggle frequency
data B D Q data PD clk lter VCO DQ DQ T DQ DQ A

45

ratio of link speed to effective transit frequency

CDR PLL design style over time

0.8 0.6 0.4 0.2 0.1 80m 60m 40m DNG91 LeB92 LeS88 20m 10m 8m IsA94 1988 1990 1992 GHW94 YaH96(8x) RDP01(4x) HDM96(2x) WHK98(4x) WBS94 GTL99(10x) MPA00 ChB97(10x) PoL94 MSS99 GSS00 HuG93(8x) WaN99 EWS95(2x) FMW97(2x) Lar99 SoA93 LYK96(8x) WBS90 UWK01 WSY97 LaW91 WWS92

Linear PLL BB PLL

1994 1996 1998 2000 2002 year BB PLLs have the advantage of precise sample point alignment based on layout symmetry. This makes BB PLLs predominate as designs push data rate towards the process transit frequency limit. (number of retiming phases shown in ()). 46

Simple First Order BB loop

VCO

D Q
tupdate

VCO runs at two discrete frequencies: f nom f bb . Phase error is evaluated at a discrete time interval
In general, this can be approximated by the mean transition time of the data.
t update .

A simple D-ip-op serves as a bb-phase detector if

locking to a clock rather than to a data signal. 47

Efcient Simulation Strategy

Simulating the VCO waveform is unnecessary to
accurately model ideal PLL behavior.

Only frequency and phase is needed. Model all circuit time-varying state variables as voltages. Convert between frequency and phase variables with
explicit integration block.

48

Model of First-order Loop

mod Fin

vdt
F Hz

fsample

Kvco

node: unit:

Fin Hz

1 UI

error UI

bbtune V

Fvco Hz

The tricky bit is to dene the loop in terms of an input frequency rather than an input phase by pulling the VCO integral through the input summation. This allows easy simulation of both frequency and phase steps.

49

Lock Range for 1st-order loop

vcofreq
2490.0
F nom + f bb F nom

MHz

n
2484.0 out of lock 200.0 Jpp in lock out of lock

F nom f bb

Degrees

0.0

phierr
-200.0

5.0

time (seconds)

15.0

The loop is locked whenever the input frequency is bracketed by the two VCO frequencies. The rapid alternation between frequencies slightly too high and slightly too low create a hunting jitter (Jpp).

50

1st-order loop: locked region

2490.0 vcofreq MHz n
F nom F nom f bb F nom + f bb

2485.0 40.0 Degrees phierr 0.0

-40.0 8.0

time (seconds)

12.0

The phase detector duty-cycle is proportional to the average frequency error.

51

1st-order loop: slew-rate limiting

2490.0

MHz

vcofreq n
2486.0

Degrees

0.0

phimod

dphi1

-200.0

Degrees

0.0

phierr time (seconds)

-100.0 5.0

8.0

Although the average input frequency (n) lies within the lock range of the loop, the added sinusoidal jitter (phimod) causes the instantaneous input frequency to exceed the VCO range. The loop phase (dphi1) stops toggling and goes into slew rate limiting, leading to a phase error (phierr).

52

Summary of 1st-order loop

Lock range: ( f nom f bb ) < f c < ( f nom + f bb ) . Jitter (pk/pk in UI): J pp = 2 t update f bb . Bang-bang loop tracking is slew-rate limited.
output jitter input is 1UI jitter 0.1UI 0.01UI frequency

The effective loop bandwidth is amplitude dependent.

The maximum amplitude of phase modulation at

frequency f mod before onset of slew-rate limiting: A UI = f bb f mod . 53

Summary of 1st-order loop, cont.

If locked, then the duty cycle C , must result in the
average loop frequency being equal to the input frequency f c ,
f c = f nom + f = C ( f nom + f bb ) + ( 1 C ) ( f nom f bb )

Phase detector average duty cycle C , given by

f 1 + -------------------- - 2 ( 2 f )
bb

(proportional to

).

54

Observations
Jitter generation, Jitter transfer bandwidth, Jitter
tolerance and frequency lock range are all inconveniently controlled by one parameter, f bb .

Phase detector average duty-cycle is proportional to

frequency error.

Strategy: Use the average duty cycle to control loop

center frequency. This decouples the lock range from jitter tolerance/generation giving more design freedom.

If the center frequency control loop is slow enough, the

resulting loop behavior will be very similar to a simple rst order loop, but with extended frequency lock capability. 55

2nd-order BB loop
Proportional (BB) branch VCO Kvco

D Q V
1 -

vdt
pd output

Integral branch
tupdate V VKv VKvt VKvt/ VKvt2/2

BB path frequency change BB path phase change Integrator path frequency change Integrator path phase change

56

Stability Factor
tupdate
VKvt

(phase change from BB path)

VKvt2/2 (phase change from integral path)

To quantify the relative independence of the two feedback loops, take ratio of phase change from BB path to the phase change of the integral path:
bb V K v t ------------- = --------------------------------2 int V K v t ( 2 ) 2 = ----------------t update
t = t update

57

redrawing the 2nd-order loop

mod Fin
1 -

vdt
Fint

fsample mod bb
K v

vdt

Kv

vdt
1 -

Fin

v dt

vdt

Kv

1 2 3

fsample

Noticing that V is proportional to F, the system can be transformed into an inner rst order bb-loop PLL (in blue) surrounded by an outer lowbandwidth frequency tracking loop (in red).

58

2nd-order loop: small step in F

2490.0 MHz

Fin Fint

degrees

2487.0 40.0 0.0 2.0

bb
3 3

volts

0.0
1 1 1 1 1 1

V
4.0

-2.0

time (seconds)

7.0

A step change in input frequency Fin produces a slow response Fint in the outer, integral loop. The resulting phase error 1 is tracked by the inner bang-bang loop bb to produce the nal sampler phase error 3. Notice that, unlike a linear PLL, there is no jitter accumulation at the sampler.

59

2nd-order loop: large step in F

2500.0 MHz 2480.0 400.0 degrees 0.0 2.0 volts 0.0 -2.0 4.0

Fin Fint 1 3 V time (seconds)

7.0

bb

In this simulation, the input frequency step is bigger than fbb, so the loop goes into slew rate limiting, leading to a transient phase error 3 at the sampler. A fancier loop could detect slew rate limiting by the lack of PD transitions, and adaptively increase the loop frequency step size.

60

2nd-order loop: phase jitter tracking

100.0 degrees 0.0 -100.0 50.0 0.0 -50.0 2.0 0.0 -2.0 4.0
2 1 2 2 3

1
3 1 2

2 3 2

mod bb

degrees

3
2

volts

V time (seconds)
7.0

Sinusoidal phase jitter mod is tracked at 1 with a phase lag by the outer, integral loop. The resulting phase error 2 is tracked by the inner bang-bang loop bb to produce the nal sampler phase error 3. The PD output V varies with the slope of 2 which is proportional to the instantaneous frequency error 61 of the outer loop.

2nd-order loop: slope overload

degrees 200.0 0.0 -200.0 100.0 0.0 -100.0 2.0 volts 0.0 -2.0 4.0
1

1 2 mod bb
A

degrees

2 V time (seconds)

7.0

The phase modulation is increased until the instantaneous frequency error exceeds the inner loops ability to track. Slew-rate limiting at point A in the inner loop bb produces a tracking error at the sampler 3. The loop is designed so that this situation never occurs under normal jitter tolerance conditions.

62

redrawing the 2nd-order loop (again)

mod Fint Fin bb
A

K v

vdt
1 -

v dt

vdt

Kv
[Gal94,95]

fsample
f bb
Fin F 1st-order on F

vdt

vdt

2 f bb ----------

t=0,1,2...
Transform the loop by pulling the integrators through the summing node A. Normalize update interval to 1. Let KvV = fbb Substitute in denition for stability factor . Notice that structure in blue box is a 1st order on F.

63

 linear system analogy for bb-loop

X(z)

H(z)
(integration)

Y(z) Q(z)

[Hau91b] [Gal95]

H (z) 1 -Q Y ( z ) = -------------------- X ( z ) + -------------------- ( z ) 1 + H (z) 1 + H (z)

gain

gain

freq

freq

64

solve for slope overload

f bb

Fin

1 -s

1 -s

2 f bb ----------

Slew rate limiting occurs when |F| > fbb Maximum input phase modulation in UI, normalized
to bb is
s 2 + s + 2 ( s 3 + s 2 ) -

. 65

Can be used to compute jitter tolerance.

slope overload limit vs

100G max jitter before S.R.L [normalized to BB] 1G 10M 100k 1k 10 0.1 1 10 100 1m 10m 0.1 1 10

=0.1 s 2 + s + 2 ( s 3 + s 2 ) - =1 =10 =100 =1000

points shown are from numerical simulation

jitter frequency * tupdate

66

jitter generation in frequency-domain

approximation justies replacing BB phase detector
with a noise source.

Combine total loop phase noise by combining each

phase noise source in RMS fashion.

source phase noise

1 + ---s

Kv -----s

output

BB phase noise of form: Asin(x)/x

VCO open loop phase noise

Kv 1 H ( s ) = ------ + ---- s s

67

example jitter generation calculation

0 -20 -40 -60 -80 -100 -120 -80 -90 -100 -110 -120 -130 -140 -80 -90 -100 -110 -120 -130 -140
1k

dB

1 -------------------1 + H (s)

H (s) -------------------1 + H (s)

vco phase noise

dBc/Hz

source phase noise

bb phase noise

dBc/Hz

computed phase noise measured phase noise

10k 100k 1M 10M 100M 1G

see [WSY97]: fvco=2.488 GHz, fbb = 6 MHz, =32000, tupdate=400ps.

68

gaussian jitter generation & gain vs

RMS output jitter [normalized to BB] 10M 1M 100k 10k 1k 100 10 1 0.1 1m
= 1e-06 = 1e-05 = 1e-04 = 0.001 = 0.01 = 0.1 =1 = 10 Jidle = 0.6+(1.65/ ) Jlin = 2*Jin/(1+sqrt()) Jwalk = 0.7*sqrt(Jin) Jtot = Jidle + Jlin +Jwalk

10m 0.1 1 10 100 1k 10k 100k RMS input jitter [normalized to BB]

1M

Simulation is for a non-tristated loop, ptransition = 100%, with 108 timesteps per point. High stability-factor loops have RMS output jitter equal to the square root of the input jitter!

69

Start

BB PLL CDR design owchart

yes you have the option of using a loop w/o hold mode, set tupdate = max runlength

Are you using a run-length limited code? no

use a looplter and VCO with hold mode, set tupdate = tbit

Compute based on Kvco, V, tupdate, and the jitter generation spec. Check that your chosen will meet the jitter tolerance spec. There is a direct tradeoff between jitter generation and jitter tolerance.

Set the loop-lter time constant such that the loop stability factor is >> 1 over all process variation. = (tupdate * ) / (2) Typical values of are in the range of 100-10,000, based on hold capacitor size. Done

70

Summary
A lot of complexity for a simple system... Its more of an art than a science After understanding:

the components, the block diagrams, the problems and the attempted solutions, and the unique needs for your application,

youll be well equipped to craft an artful solution.

71

References
Clock and data recovery is a complex eld. Any single presentation can only act as an introduction to the eld. This eclectic collection of serial data communication references includes papers on signal degradation mechanisms, jitter measurement, phase locked loop design, simulation techniques, multiplexers and demultiplexers, and coding theory. Every new application comes with a unique set of constraints and requirements, requiring an artful combination of techniques to be optimally addressed. I cant recommend anything better to the newcomer to this eld than to read through the literature and internalize the many different techniques that exist. Keywords appear in curly braces {}. Papers in Boldface appear on the short course CDROM in PDF format.

[AFD87]

[Ale75] [Arm83] [Baa86] [BaD93] [BBI94] [Buc92] [Byr63] [Car56]

Andrews, G. E., D. C. Farley, S. H. Dravitz, A. W. Schelling, P. C. Davis and L. G. McAfee, A 300Mb/s Clock Recovery and Data Retiming System, ISSCC Digest of Technical Papers, 1987, 188-189. {SAW Filter Clock Recovery with emphasis on phase alignment problem}. Alexander, J. D. H., Clock Recovery from Random Binary Signals, Electronics Letters 11, 22 (30th October 1975), 541-542. {binary quantized phase detector}. Armitage, C. B., SAW Filter Retiming in the AT&T 432 Mb/s Lightwave Regenerator, Conference Proceedings: AT&T Bell Labs., Holmdel, NJ, USA, September 3-6, 1984, 102-103. {matches tempco of SAW to tempco of electronics.}. Baack, C., Optical Wide Band Transmission Systems, CRC Press Inc., 1986. {example of PLL for clock recovery}. Banu, M. and A. Dunlop, A 660Mb/s CMOS Clock Recovery Circuit with Instantaneous Locking for NRZ data and BurstMode Transmission, ISSCC Digest of Technical Papers, February 1993, 102-103. {burst-mode gated VCO}. Boudreau, P. E., W. C. Bergman and D. R. Irvin, Performance of a cyclic redundancy check and its interaction with a data scrambler, IBM J. Res. Develop. 38, 6 (November 1994), 651-658. {CRC theory Scrambler Error multiplication} Buchwald et al., A., A 6GHz Integrated Phase-Locked Loop using AlGaAs/GaAs Heterojunction Bipolar Transistors, ISSCC Digest of Technical Papers, 1992, 98,99,253. {Frequency multiplying ring oscillator}. Byrne et al., C. J., Systematic Jitter in Chain of Digital Regenerators, The Bell System Technical Journal, November 1963, 2679. {clock extraction by ltering}. Carter, R. O., Low-Disparity Binary Coding System, Electronics Letters 1, 3 (May, 1956), 67-68. {conditional inversion data encoding disparity}.

[CCI90] [ChB97]

[Cho92] [Co94] [Con84] [Cor79] [Den88] [DeV91] [DNG91]

[Dra92] [DR78] [EnA87]

[EnA92] [EWS95]

[FHH84] [FLS63]

CCITT, Digital Line systems based on the synchronous digital hierarchy for use on optical ber cables, CCITT G.958, 1990. {SONET Payload test patterns regenerator scrambling}. Chen, D. and M. O. Baker, A 1.25 Gb/s, 460mW CMOS Transceiver for Serial Data Communication, ISSCC Digest of Technical Papers, February 1997, 242- 243,465. {CDR only, 10-phase bang-bang ATB loop, in 6e9 Ft 0.5um CMOS, 12.25 mm^2 0.460 Watts}. Chona, F. M. R., Draft Standard, SONET inter-ofce and intra-ofce line jitter re., T1X1.3, May 11, 1992. {Standards SONET jitter}. Co, R. S. and J. H. M. Jr., Optimization of Phase-Locked Loop Performance in Data Recovery Systems, IEEE Journal of Solid State Circuits 29, 9 (September 1994), 1022-1034. {optimum design of CDR loops with linear PD}. Connor et al., P. O., A Monolithic Multigigabit/Second DCFL GaAs Decision Circuit, IEEE Electron Device Letters EDL-5, 7 (July 1984), 226-227. {GaAs Fet decision circuit example}. Cordell et al., R. R., A 50MHz Phase and Frequency Locked Loop, IEEE Journal of Solid State Circuits SC-14, 6 (December 1979), 1003-1009. {quadricorrellator phase detector, Tunable LC Oscillator}. Den Dulk, R. C., Digital Fast Acquisition Method for Phase-Lock Loops, Electronics Letters 24, 17 (18th August 1988), 1079-1080. {2 order of magnitude locking speed-up with fancy slip detector & charge pump}. DeVito et al., L., A 52 MHz and 155MHz Clock-Recovery PLL, ISSCC Digest of Technical Papers, February 13-15, 1991, 142, 143, 306. {multivibrator example, Negative resistor chargepump, rotational freq.det.}. DeVito, L., J. Newton, R. Goughwell, J. Bulzacchelli and F.Benkley, A 52MHz and 155 MHz Clock-Recovery PLL, ISSCC Digest of Technical Papers, February 1991, 142-143,306. {CDR only, 1-phase rotational linear loop, in 3.5e9 Ft Bipolar, 15.028 mm^2 0.575 Watts}. Dravida, S., Error Control Aspects of High Speed Networks, Infocom, 1992, 272-281. {CRC performance with SONET self-synchronous scrambler}. DAndrea, N. A. and F. Russo, A Binary Quantized Digital Phase Locked Loop: A Graphical Analysis, IEEE Transactions on Communications COM-26, 9 (September 1978), 1355-1364. {Analysis of BB loop}. Enam, S. K. and A. A. Abidi, Decision and clock Recovery Circuits for Gigahertz Optical Fiber Receivers in Silicon NMOS, Journal of Lightwave Technology LT-5, 3 (March 1987), 367-372. {MOS tunable monolithic ring oscillator example - Some clever circuit ideas for gigabit rates}. Enam, S. K. and A. A. Abidi, MOS Decision and Clock Recovery Circuits for Gb/s Optical-Fiber Receivers, ISSCC Digest of Technical Papers, 1992, 96,97,253. {quadratic phase detector} {MOS decision circuit example}. Ewen, J. F., A. X. Widmer, M. Soyuer, K. R. Wrenner, B. Parker and H. A. Ainspan, Single-Chip 1062Mbaud CMOS Transceiver for Serial Data Communication, ISSCC Digest of Technical Papers, February 1995, 32-33,336. {TX/RX Mux/demux, 2phase bang-bang, data samples clock loop, in 6.6e9 Ft 0.45um CMOS, 17.55 mm^2 1.2 Watts}. Faulkner, D. W., I. Hawker, R. J. Hawkins and A. Stevenson, An Integrated Regenerator for High Speed Optical Fiber Transmission Systems, IEE Conference Proceedings (November 30 - December 1, 1983) 8-13. {uses rectier/SAW combo}. Feynman, R., R. B. Leighton and M. Sands, The Feynman Lectures on Physics, Addison-Wesley Publishing Company, 1963. {Short, simple presentation of timestep simulator for planetary motion, same principles can be used to write a simple pll simulator}.

[FMW97]

[Gal94] [Gal95]

[Gar79] [GHW94]

[Gla85] [GMP78] [Gol82] [Gri69] [GSS00a]

[GSS00b]

[GTL99]

[Gup75] [Hau91a] [Hau91b]

Fiedler, A., R. Mactaggart, J. Welch and S. Krishnan, A 1.0625Gbps Transceiver with 2x-Oversampling and Transmit Signal Pre-Emphasis, ISSCC Digest of Technical Papers 40 (February 6-8 1997), 238,239,464. {transmit pre-emphasis, skin loss equalizer, CDR 1:10 DEMUX, 10-phase bang-bang ATB loop, in 6e9 Ft 0.5um CMOS, 4 mm^2 0.45 Watts}.}. Galton, I., Higher-order Delta-Sigma Frequency-to-Digital Conversion, Proceedings of IEEE International Symposium on Circuits and Systems (May 30 - June 2, 1994) 441-444 {Delta-Sigma BB loops phase tracking frequency digitalization PLL}. Galton, I., Analog-Input Digital Phase-Locked Loops for Precise Frequency and Phase Demodulation, Transactions on Circuits and Systems-II: Analog and Digital Signal Processing 42, 10 (October 1995), 621-630. {good discussion of delta-sigma analysis of BB PLLs}. Gardner, F. M., Phaselock Techniques, Second Edition, John Wiley and Sons, Inc., 1979. {example of using exor-gate to generate clock component from NRZ data}. Guo, B., A. Hsu, Y. Wang and J. Kubinec, 125Mb/s CMOS All-Digital Data Transceiver Using Synchronous Uniform Sampling, ISSCC Digest of Technical Papers, February 1994, 112-113. {TX/RX, 1-phase ATB with digital phase adjustment loop, in 3.75e9 Ft 0.8um CMOS, 6.38 mm^2 0.175 Watts}. Glance, B. S., New Phase-Lock Loop Circuit Providing Very Fast Acquistion Time, IEEE Transactions on Microwave Theory and Techniques MTT-33, 9 (September 1985), 747-754. {adds non-linear time constant to speed PLL acquisition by 2 orders of mag.}. Gruber, J., P. Marten, R. Petschacher and P. Russer, Electronic Circuits for High Bit Rate Digital Fiber Optic Communication Systems, IEEE Transactions on Communications COM-26, 7 (July 1978), 1088-1098. Golomb, S. W., Shift Register Sequences, Aegean Park Press, 1982. {classic text on Pseudo-Random sequence generation, ISBN:089412-048-4} Grifths, J. M., Binary Code Suitable for Line Transmission, Electronics Letters 5, 4 (February 20, 1969), 79-81. {5b/6b encoding example}. Greshishchev, Y. M., P. Schvan, J. L.Showell, M. Xu, J. J.Ojha and J. E. Rogers, A Fully Integrated SiGe Receiver IC for 10Gb/s Data Rate, ISSCC Digest of Technical Papers, February 2000, 52-53,447. {CDR DEMUX BIST, 1-phase bang-bang loop, in 50e9 Ft SiGe, 20.25 mm^2 4.5 Watts}. Greshishchev, Y. M., P. Schvan, J. L. Showell, M. Xu, J. J. Ojha and J. E. Rogers, A Fully Integrated SiGe Receiver IC for 10Gb/s Data Rate, IEEE Journal of Solid State Circuits 35, 12 (December 2000), 1949-1957. {CDR DEMUX BIST, 1- phase bangbang loop, in 50e9 Ft SiGe, 20.25 mm^2 4.5 Watts}. Gu, R., J. M. Tran, H. Lin, A. Yee and M. Izzard, A 0.5-3.5Gb/s Low-Power Low-Jitter Serial Data CMOS Transceiver, ISSCC Digest of Technical Papers, February 1999, 352-353,478. {TX/RX MUX/DEMUX BIST, 10-phase bang-bang ATB loop, in 10.7e9 Ft 0.28um CMOS, 1 mm^2 0.250 Watts}. Gupta, S. C., Phase-Locked Loops, Proceedings of the IEEE 63, 2 (February 1975), 291-306. {Good systematic outline survey of communication-type PLLs}. Hauenschild et al., J., A Silicon Bipolar Decision Circuit Operating up to 15Gb/s, IEEE Journal of Solid State Circuits 26, No.11 (November 1991), 1734-1736. {Si bipolar decision circuit example}. Hauser, M. W., Principles of Oversampling A/D Conversion, J. Audio Eng. So. Vol 39, 1/2 (Jan/February 1991), 3-26. {excellent tutorial on Delta Sigma AD, Oversampling, noiseshaping}.

[HDM96]

[HeS88] [Hog85] [Hor92] [HuG93] [IsA94a]

[IsA94b]

[Kas85] [KWG94] [Lai90] [Lam93] [Lar99]

[LaW91] [LeB92a] [LeB92b

Hauenschild, J., C. Dorshcky, T. W. Mohrenfels and R. Seitz, A 10Gb/s BiCMOS Clock and Data Recovery 1:4-Demultiplexer in a Standard Plastic Package with External VCO, ISSCC Digest of Technical Papers, February 1996, 202-203,445. {CDR 4:1 DEMUX, 2-phase bang-bang ATB loop, in 16e9 Ft BiCMOS, 5.29 mm^2.450 Watts}. Hein, J. P. and J. W. Scott, z-Domain Model for Discrete-Time PLLs, IEEE Transactions on Circuits and Systems 35, 11 (November 1988), 1393-1400. {good discussion of using z-transforms in PLL analysis}. Hogge, Jr., C. R., A Self Correcting Clock Recovery Circuit, IEEE Transactions on Electron Devices ED-32, 12 (December 1985), 2704-2706. {Original Hogge detector, interesting phase detector idea...}. Hornak, T., Interface Electronics for Fiber Optic Computer Links, Intensive Course on Practical Aspects in Analog IC Design, Lausanne, Switzerland, June 29-July 10, 1992. {Excellent overview of components for serial optical data transmission}. He, T. and P. Gray, A Monolithic 480 Mb/s AGC/Decision/Clock Recovery Circuit in 1.2 um CMOS, IEEE Journal of Solid State Circuits 28, 12 (Dec. 1993) 1314-20 {CDR only, 8-phase linear ATB loop, in 2.4e9 Ft 1.2um CMOS, 9 mm^2 0.9 Watts}. Ishihara, N. and Y. Akazawa, A Monolithic 156Mb/s Clock and Data-Recovery PLL Circuit using the Sample-and-Hold Technique, IEEE Journal of Solid State Circuits 29, 12 (December 1994), 1566-1571. {CDR only, 1-phase linear 90-degree delayed data + narrow pulses loop, in 16e9 Ft Bipolar, 8.4 mm^2 0.320 Watts}. Ishihara, N. and Y. Akazawa, A Monolithic 156Mb/s Clock and Data-Recovery PLL Circuit using the Sample-and-Hold Technique, ISSCC Digest of Technical Papers, February 1994, 110-111,318. {CDR only, 1-phase linear 90-degree delayed data + narrow pulses loop, in 16e9 Ft Bipolar, 8.4 mm^2 0.320 Watts}. Kasper et al., B. L., SAGM Avalanche Photodiode Optical Receiver for 2 Gbit/s and 4 Gbit/s, Electronic Letters 21, 21 (10th October 1985), 982-984. {eye diagram}. Kim, B., T. C. Weigandt and P. R. Gray, PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design, ISCAS proceedings, May 30 - June 2, 1994, 31-34. {Excellent and Intuitive discussion of Jitter in Ring Oscillators}. Lai, B., Decision Circuit Lowers Transmission Bit Error Rates, Microwaves and RF, July 1990, 118- 122. {Si bipolar decision circuit example}. Lam, V. M. T., Microwave Oscillator Phase Noise Reduction Using Negative Resistance Compensation, Electronics Letters 29, 4 (February 18th, 1993), 379-340. {Leeson negative resistance phase noise second harmonic IC}. Larsson, P., A 2-1600MHz 1.2-2.5V CMOS Clock- Recovery PLL with Feedback Phase-Selection and Averaging Phase-Interpolation for Jitter Reduction, ISSCC Digest of Technical Papers, February 1999, 356-357. {CDR only, 1-phase bang- bang with digital phase shifter loop, in 12e9 Ft 0.25um CMOS, 0.036 mm^2 0.072 Watts}. Lai, B. and R. C. Walker, A Monolithic 622Mb/s Clock Extraction Data Retiming Circuit, ISSCC Digest of Technical Papers 34 (February 13-15, 1991), 144,145. {binary quantized phase detector}. Lee, T. H. and J. F. Bulzacchelli, A 155MHz Clock Recovery Delay- and Phase-Locked Loop, ISSCC Digest of Technical Papers, February 1992, 160- 161,272. {CDR only, 1-phase rotational linear loop, in 3.5e9 Ft Bipolar, 10.75 mm^2 0.364 Watts}. Lee, T. H. and J. F. Bulzacchelli, A 155MHz Clock Recovery Delay- and Phase-Locked Loop, IEEE Journal of Solid State Circuits 27, 12 (December 1992), 1736-1746. {CDR only, 1-phase linear 90- degree delayed data + narrow pulses loop, in 16e9 Ft Bipolar, 8.4 mm^2 0.320 Watts}.

[LeS88]

[LiC81] [LYK96]

[Mac87] [MCC01]

[McG90] [MPA00]

[MSS99]

[OFC84]

[Ofe89] [OhT83] [Par89] [Pet88] [PLS92]

Leonowich, R. H. and J. M. Steininger, A 45-MHz CMOS phase/frequency-locked loop timing recovery circuit, ISSCC Digest of Technical Papers, February 1988, 14. {CDR only, 1-phase linear (narrow pulse), rotation frequency detector loop, in 1.65e9 Ft 1.75um CMOS, 3 mm^2.250 Watts}. Lindsey, W. C. and C. M. Chie, A Survey of Digital Phase-Locked Loops, Proceeding of the IEEE 69, 4 (April 1981), 410-431. {Presents a good taxonomy of digital PLLs}. Lee, I., C. Yoo, W. Kim, S. Chai and W. Song, A 622Mb/s CMOS Clock Recovery PLL with Time- Interleaved Phase Detector Array, ISSCC Digest of Technical Papers, February 1996, 198-199,444. {CDR DEMUX, 8-phase bang-bang ATB loop, in 3.75e9 Ft 0.8um CMOS, 0.72 mm^2 0.200 Watts}. MacDougall, M. H., Simulating Computer Systems - Techniques and Tools, The MIT Press, Cambridge, Massachusetts, 1987. {description and source code for event driven simulator}. Momtaz, A., J. Cao, M. Caresosa, A. Hairapitian, D. Chung, K. Vakilian, M. Green, B. Tan, K. Jen, I. Fujimori, G. Gutierrez, Y. Cai, S. Ueno, K. Watanabe, T. Kato, T. Shinohara, K. Mikami, T. Hashimoto, A. Takai, K. Washio, R. Takeyar and T. Harada, A Single-Chip 10Gb/s Transceiver LSI using SiGe SOI/BiCMOS, ISSCC Digest of Technical Papers, February 2001, 82-83,435. {TX/RX MUX/DEMUX BIST, 1-phase linear rotational sample-hold loop, in 90e9 Ft SiGe CMOS, 29.68 mm^2 2.6 Watts}. McGaughey, J. T., Convert NRZ format to Biphase, Electronic Design, April 12, 1990, 86. {biphase example}. Meghelli, M., B. Parker, H. Ainspan and M. Soyuer, A SiGe BiCMOS 3.3V Clock and Data Recovery Circuit for 10Gb/s Serial Transmission Systems, ISSCC Digest of Technical Papers, February 2000, 56-57. {CDR only, 1-phase bang-bang loop, in 45e9 Ft, 6 mm^2 0.42 Watts}. Morikawa, T., M. Soda, S. Shiori, T. Hashimoto, F. Sato and K. Emura, A SiGe Single-Chip 3.3V Receiver IC for 10Gb/s Optical Communication System, ISSCC Digest of Technical Papers, February 1999, 380-381,481. {CDR TIA only, 1-phase linear Hogge loop, in 60e9 Ft SiGe, 6 mm^2 0.66 Watts}. OConnor, P., P. G. Flahive, W. Clemetson, R. L. Panock, S. H. Wemple, S. C. Shunk and D. P. Takahashi, A Monolithic Multigigabit/ Second DCFL GaAs Decision Circuit, IEEE Electron Device Letters EDL-5, 7 (July 1984),. {2.4 GHz ED GaAs Mesfet Flip-op w/ input buffer amp}. Ofek, Y., The Conservative Code for Bit Synchronization, IEEE Transactions on Communications, 1989. {conserves transition number, uses divider for clock recovery}. Ohta, N. and T. Takada, High Speed GaAs SCFL Monolithic Integrated Decision Circuit for Gb/s Optical Repeaters, Electronics Letters, September 1983. {GaAs Decision Circuit}. Park et al., M. S., Novel Regeneration Having Simple Clock Extraction and Automatic Phase Controlled Retiming Circuit, Electronic Letters 25 (January 1989), 83-84. {clock extraction by ltering}. Petrovic, R., Low Redundancy Optical Fiber Line Code, Journal of Optical Communication 9, 3 (1988), 108-111. {13B/14B code design}. Pottbacker, A., U. Langmann and H. Schreiber, A Si bipolar phase and frequency detector IC for clock extraction up to 8Gb/s, IEEE Journal of Solid State Circuits 27, 12 (December 1992), 1747-1751. {linear quadrature phase/frequency detector}.

[PoL94a] [PoL94b] [RaO91] [Raz96a] [Raz96b] [Raz96c] [RCF84]

[RDP01]

[ReG73] [RHF90] [RoM77] [Ros84] [Ros85] [Rou76] [RuG91] [Run91] [San82]

Pottbacker, A. and U. Langmann, An 8GHz Silicon Bipolar Clock-Recovery and Data-Regenerator IC, IEEE Journal of Solid State Circuits 29, 12 (December 1994), 1572-1576. {CDR only, 1-phase linear loop, in 25e9 Ft Bipolar, 3.06 mm^2 2.25 Watts}. Pottbacker, A. and U. Langmann, An 8GHz Silicon Bipolar Clock-Recovery and Data-Regenerator IC, ISSCC Digest of Technical Papers, February 1994, 116-117,320. {CDR only, 1-phase linear loop, in 25e9 Ft Bipolar, 3.06 mm^2 2.25 Watts}. Ransijn, H. and P. OConnor, A PLL-Based 2.5-Gb/s GaAs Clock and Data Regenerator IC, JSSC 26, 10 (October 1991), 1345-1353. {Rotational frequency detector, Limiting Amp, Jitter Transfer Measurement}. B. Razavi, ed., Monolithic phase-locked loops and clock recovery circuits: theory and design, IEEE Press, 1996. {A volume of selected reprints with bibliography}. Razavi, B., Monolithic Phase-Locked Loops, ISSCC Tutorial, San Francisco, CA, February 7, 1996. {Good overview of non-datadriven PLL theory}. Razavi, B., A 2.5-Gb/s 15-mW Clock Recovery Circuit, IEEE Journal of Solid State Circuits 31, 4 (April 1996), 472-480. {dual loop phase frequency quadricorrelator}. Rosenberg, R. L., C. Chamzas and D. A. Fishman, Timing Recovery with SAW Transversal Filters in the Regenerators of Undersea Long-Haul Fiber Transmission Systems, Journal of Lightwave Technology LT-2, 6 (December 1984), 917-925. {discusses jitter accumulation}. Reinhold, M., C. Dorschky, F. Pullela, E. Rose, P. Mayer, P. Paschke, Y. Baeyens, J. Mattia and F. Kunz, A Fully-Integrated 40Gb/s Clock and Data Recovery / 1:4 DEMUX IC in SiGe Technology, ISSCC Digest of Technical Papers, February 2001, 8485,435. {CDR DEMUX, 4-phase ATB loop, in 72e9 Ft SiGe HBT, 9 mm^2 5.4 Watts}. Reddy, C. P. and S. C. Gupta, A Class of All-Digital Phase Locked Loops: Modeling and Analysis, IEEE Transactions on industrial Electronics and Control Instrumentation IECI-20, 4 (November 1973), 239-251. {discusses of binary-quantized phase detection}. Ross, F. E., J. R. Hamstra and R. L. Fink, FDDI - A LAN among MANs, ACM Computer Communications Review, July 1990, 16-31. {4b/5b encoding example}. Roza, E. and P. W. Millenaar, An Experimental 560 MBit/s Repeater with Integrated Circuits, IEEE Transactions on Communications COM-25, 9 (September 1977),. {coax-based. good comparison of PLL vs lter-type clock extraction}. Rosenberg et al., R. L., Timing Recovery with SAW Transversal lters in the Regenerators of Undersea Long-haul Fiber Transmission Systems, IEEE Journal of Lightwave Technology LT-2, 6 (December 1984), 917-925. {clock extraction by SAW}. Ross, F. E., An Overview of FDDI: the Fiber Distributed Data Interface, IEEE Journal on Selected Areas in Communications 7, 7 (September 1985), 1046, Table 1. {4b/5b encoding example, example of frame synch characters}. Rousseau, M., Block Codes for Optical-Fibre Communication, Electronics Letters 12, 18 (2nd September 1976), 478-479. {mBnB code discussion, run length limits, power spectra, 5b6b recommended}. Runge, K. and J. L. Gimlett, 20Gb/s AlGaAs HBT Decision Circuit IC, Electronics Letters 27, 25 (5th December 1991), 2376-2378. {GaAs HBT decision circuit example}. Runge et al., K., Silicon Bipolar Integrated Circuits for Multi-Gb/s Optical Communication Systems, IEEE Journal on Selected Areas in Communications 9, 5 (June 1991), 640. {Si bipolar decision circuit example}. Sandera, L., Improve Datacomm Links by Using Manchester Code, EDN, February 17, 1982, 155-162. {manchester coding example}.

[Shi87] [SHL99]

[SoA93]

[SyA86] [TrV89] [UWK01]

[Wal89] [WaN99]

[WBS90]

[WBS94]

[WHK98]

[WHY91]

[WiF83]

Shin et al., D., Selfcorrecting Clock Recovery Circuit with Improved Jitter Performance, Electronics Letters 23, 3 (29th January 1987), 110-111. {Improved Hogge detector}. Scheytt, C., G. Hanke and U. Langmann, A 0.155-, 0.622-, and 2.488-Gb/s Automatic Bit-Rate Selecting Clock and Data Recovery IC for Bit-Rate Transparent SDH Systems, IEEE Journal of Solid State Circuits 34, 12 (December 1999), 1935-1943. {quadrature p/f detector, delay-interpolated ring oscillator). Soyuer, M. and H. A. Ainspan, A Monolithic 2.3 Gb/s 100mW Clock and Data Recovery Circuit, ISSCC Digest of Technical Papers, February 1993, 158- 159,282. {CDR only, 1-phase bang-bang data triggered loop, in 30e9 Ft Bipolar, 1.3 mm^2 0.100 Watts}. Syed, K. E. and A. A. Abidi, Gigahertz Voltage Controlled Oscillator, Electronics Letters 22 (June 5, 1986), 677-679. {MOS tunable monolithic ring oscillator example}. Trischitta, P. R. and E. L. Varma, Jitter in digital transmission systems, Artech House, Inc., 1989. {good overview of jitter (textbook) ISBN 0-89006-248-X}. Ueno, S., K. Watanabe, T. Kato, T. Shinohara, K. Mikami, T. Hashimoto, A. Takai, K. Washio, R. Takeyar and T. Harada, A Single-Chip 10Gb/s Transceiver LSI using SiGe SOI/BiCMOS, ISSCC Digest of Technical Papers, February 2001, 8283,435. {TX/RX MUX/DEMUX BIST, 1-phase linear rotational sample-hold loop, in 90e9 Ft SiGe CMOS, 29.68 mm^2 2.6 Watts}. Walker, R. C., Fully Integrated High Speed Voltage Controlled Ring Oscillator, U.S. Patent 4,884,041, Granted Nov. 28, 1989. {Si bipolar tunable monolithic ring oscillator example}. Wang, H. and R. Nottenburg, A 1Gb/s CMOS Clock and Data Recovery Circuit, ISSCC Digest of Technical Papers, February 1999, 354-355,477. {CDR only, 1-phase analog track-hold + rotational fd loop, in 6e9 Ft 0.5um CMOS, 7.29 mm^2 0.300 Watts}. Wallace, P., R. Bayruns, J. Smith, T. Laverick and R. Shuster, A GaAs 1.5Gb/s Clock Recovery and Data Retiming Circuit, ISSCC Digest of Technical Papers, February 1990, 192-193. {CDR only, 1-phase delay & multiply w/SAW loop, in 20e9 Ft 0.5um GaAs MESFET, 2 mm^2 0.75 Watts}. Wang, Z., M. Berroth, J. Seibel, P. Hofmann, A. Hulsmann, Kohler, B. Raynor and J. Schneider, 19GHz Monolithic Integrated Clock Recovery Using PLL and 0.3um Gate-Length Quantum-Well HEMTs, ISSCC Digest of Technical Papers, February 1994, 118-119. {CDR only, 1-phase linear xor of data and clock pulses loop, in 50e9 Ft 0.3um HEMT, 1.5 mm^2 0.350 Watts}. Walker, R. C., K. Hsieh, T. A. Knotts and C. Yen, A 10Gb/s Si-Bipolar TX/RX Chipset for Computer Data Transmission, ISSCC Digest of Technical Papers 41 (February 5-7 1998), 302,303,450. {multi-phase architecture, 8-phase VCO, ft-doubler amplier, bb-loop CDR MUX/DEMUX, 4-phase BB/ATB loop, in 25e9 Ft Bipolar, 28.6 mm^2 8.5 Watts}.}. Walker, R. C., T. Hornak, C. Yen, J. Doernberg and K. H. Springer, A 1.5Gb/s Link Interface Chipset for Computer Data Transmission, IEEE Journal on Selected Areas in Communications 9, 5 (June 1991), 698-703. {binary quantized phase detector with master transition}. Widmar, A. X. and P. A. Franaszek, A DC Balanced, partitioned-Block 8B/10B Transmission Code, IBM Journal of Research and Development 27, 5 (September 1983), 440-451. {8b/10b encoding example - Precursor to Fiber Channels 8B/10B code}.

[WKG94] [WSY97]

[WuW92] [WWS92]

[YaH96a]

[YaH96b]

[Yam80] [YFW82] [YKI84] [YTY80]

Weigandt, T. C., B. Kim and P. R. Gray, Analysis of Timing Jitter in CMOS Ring Oscillators, ISCAS proceedings, May 30 June 2, 1994. {Excellent and Intuitive discussion of Jitter in Ring Oscillators}. Walker, R., C. Stout and C. Yen, A 2.488Gb/s Si-Bipolar Clock and Data Recovery IC with Robust Loss of Signal Detection, ISSCC Digest of Technical Papers 40 (February 6-8 1997), 246,247,466. {training loop, loss of signal detection, bb-loop, ring oscillator}. Wu, J. and R. C. Walker, A Bipolar 1.5Gb/s Monolithic Phase Locked Loop for Clock and Data Extraction, VLSI Circuit Symposium, Seattle, June 3-5, 1992. {positive feedback PLL loop lter}. Walker, R., J. Wu, C. Stout, B. Lai, C. Yen, T. Hornak and P. Petruno, A 2-Chip 1.5Gb/s Bus-Oriented Serial Link Interface, ISSCC Digest of Technical Papers 35 (February 19-21 1992), 226,227,291. {MT Code, Ring Osc binary quantized phase detector with master transition TX/RX MUX/DEMUX, 1-phase bang-bang loop, in 25e9 Ft Bipolar, 24.5 mm^2 3.8 Watts}.}. Yang, C. K. and M. A. Horowitz, 0.8um CMOS 2.5Gb/s Oversampled Receiver for Serial Links, ISSCC Digest of Technical Papers, February 1996, 200- 201,444. {CDR DEMUX, 8-phase digital 3x oversampled loop, in 3.75e9 Ft 0.8um CMOS, 9 mm^2 2.25 Watts}. Yang, C. K. and M. A. Horowitz, 0.8um CMOS 2.5Gb/s Oversampled Receiver for Serial Links, IEEE Journal of Solid State Circuits 31, 12 (December 1996), 2015-2023. {CDR DEMUX, 8-phase digital 3x oversampled loop, in 3.75e9 Ft 0.8um CMOS, 9 mm^2 2.25 Watts}. Yamada et al., J., 1.6Gb/s Optical Receiver at 1.3um with SAW Timing Retrieval Circuit, Electronics Letters 16, 2 (17th January 1980), 57- 58. {clock extraction by SAW}. Yen, C., Z. Fazarinc and R. Wheeler, Time-domain skin-effect model for transient analysis of lossy transmission lines., Proceedings of the IEEE 70, 7 (July 1982), 750-757. {skin-effect lossy transmission line transient simulation modelling}. Yoshikai, N., K. Katagiri and T. Ito, mB1C Code and its Performance in an Optical Communication System, IEEE Transactions on Communications COM-32, 2 (February 1984). {uses m binary bits + one complementary bit stuffed to break runs}. Yamada, J., J. Temmyo, S. Yoshikawa and T. Kimura, 1.6 Gbit/s Optical Receiver at 1.3um with SAW Timing Retrieval Circuit, Electronics Letters, 1980, 57-58. {basic SAW system, with discussion of power penalty for SAW phase shifts}.