RV_DM Checklist

This checklist is for Hardware Stage transitions for the RV_DM peripheral. All checklist items refer to the content in the Checklist.

Design Checklist

Type	Item	Resolution	Note/Collaterals
Documentation	SPEC_COMPLETE	Done	RV_DM Design Spec
Documentation	CSR_DEFINED	Done
RTL	CLKRST_CONNECTED	Done
RTL	IP_TOP	Done
RTL	IP_INSTANTIABLE	Done
RTL	PHYSICAL_MACROS_DEFINED_80	N/A	Debug ROM implemented using sea of gates
RTL	FUNC_IMPLEMENTED	Done
RTL	ASSERT_KNOWN_ADDED	Done
Code Quality	LINT_SETUP	Done

Type	Item	Resolution	Note/Collaterals
Documentation	NEW_FEATURES	Done
Documentation	BLOCK_DIAGRAM	Done	Available in external PULP RISC-V Debug System Documentation
Documentation	DOC_INTERFACE	Done
Documentation	DOC_INTERFACE	Done
Documentation	DOC_INTEGRATION_GUIDE	Waived	This checklist item has been added retrospectively.
Documentation	MISSING_FUNC	Done
Documentation	FEATURE_FROZEN	Done
RTL	FEATURE_COMPLETE	Done
RTL	PORT_FROZEN	Done
RTL	ARCHITECTURE_FROZEN	Done
RTL	REVIEW_TODO	Done
RTL	STYLE_X	Waived	Waiving as RTL is from a third-party
RTL	CDC_SYNCMACRO	Done
Code Quality	LINT_PASS	Done
Code Quality	CDC_SETUP	Waived	No block-level flow available - waived to top-level signoff.
Code Quality	RDC_SETUP	Waived	No block-level flow available - waived to top-level signoff.
Code Quality	AREA_CHECK	Done
Code Quality	TIMING_CHECK	Done
Security	SEC_CM_DOCUMENTED	N/A

Type	Item	Resolution
Security	SEC_CM_ASSETS_LISTED	Done
Security	SEC_CM_IMPLEMENTED	Done
Security	SEC_CM_RND_CNST	N/A
Security	SEC_CM_NON_RESET_FLOPS	Done
Security	SEC_CM_SHADOW_REGS	Done
Security	SEC_CM_RTL_REVIEWED	Done
Security	SEC_CM_COUNCIL_REVIEWED	Done

Type	Item	Resolution
Documentation	NEW_FEATURES_D3	Not Started
RTL	TODO_COMPLETE	Not Started
Code Quality	LINT_COMPLETE	Not Started
Code Quality	CDC_COMPLETE	Not Started
Code Quality	RDC_COMPLETE	Not Started
Review	REVIEW_RTL	Not Started
Review	REVIEW_DELETED_FF	Not Started
Review	REVIEW_SW_CHANGE	Not Started
Review	REVIEW_SW_ERRATA	Not Started
Review	Reviewer(s)	Not Started
Review	Signoff date	Not Started

Type	Item	Resolution	Note/Collaterals
Documentation	DV_DOC_DRAFT_COMPLETED	Done	RV_DM DV document
Documentation	TESTPLAN_COMPLETED	Done	RV_DM Testplan
Testbench	TB_TOP_CREATED	Done
Testbench	PRELIMINARY_ASSERTION_CHECKS_ADDED	Done
Testbench	SIM_TB_ENV_CREATED	Done
Testbench	SIM_RAL_MODEL_GEN_AUTOMATED	Done	Done for both, regs and debug mem RAL. JTAG DTM and DMI RAL models are hand-written.
Testbench	CSR_CHECK_GEN_AUTOMATED	Done	Done for both, regs and debug mem RAL.
Testbench	TB_GEN_AUTOMATED	N.A.	Design is not parameterized into multiple variants.
Tests	SIM_SMOKE_TEST_PASSING	Done
Tests	SIM_CSR_MEM_TEST_SUITE_PASSING	Done	CSR tests run on all 4 RAL models.
Tests	FPV_MAIN_ASSERTIONS_PROVEN	N.A.
Tool Setup	SIM_ALT_TOOL_SETUP	Done	Primary: VCS, Alt: Xcelium
Regression	SIM_SMOKE_REGRESSION_SETUP	Done
Regression	SIM_NIGHTLY_REGRESSION_SETUP	Done
Regression	FPV_REGRESSION_SETUP	N.A.
Coverage	SIM_COVERAGE_MODEL_ADDED	Done
Code Quality	TB_LINT_SETUP	Done
Integration	PRE_VERIFIED_SUB_MODULES_V1	Done	Standard pre-verified sub-modules. Third party PULP DM modules will be fully coverage-closed.
Review	DESIGN_SPEC_REVIEWED	Done
Review	TESTPLAN_REVIEWED	Done
Review	STD_TEST_CATEGORIES_PLANNED	Done	Security, debug, stress, error test cases planned.
Review	V2_CHECKLIST_SCOPED	Done

Type	Item	Resolution
Documentation	DESIGN_DELTAS_CAPTURED_V2	Not Started
Documentation	DV_DOC_COMPLETED	Not Started
Testbench	FUNCTIONAL_COVERAGE_IMPLEMENTED	Not Started
Testbench	ALL_INTERFACES_EXERCISED	Not Started
Testbench	ALL_ASSERTION_CHECKS_ADDED	Not Started
Testbench	SIM_TB_ENV_COMPLETED	Not Started
Tests	SIM_ALL_TESTS_PASSING	Not Started
Tests	FPV_ALL_ASSERTIONS_WRITTEN	Not Started
Tests	FPV_ALL_ASSUMPTIONS_REVIEWED	Not Started
Tests	SIM_FW_SIMULATED	Not Started
Regression	SIM_NIGHTLY_REGRESSION_V2	Not Started
Coverage	SIM_CODE_COVERAGE_V2	Not Started
Coverage	SIM_FUNCTIONAL_COVERAGE_V2	Not Started
Coverage	FPV_CODE_COVERAGE_V2	Not Started
Coverage	FPV_COI_COVERAGE_V2	Not Started
Integration	PRE_VERIFIED_SUB_MODULES_V2	Not Started
Issues	NO_HIGH_PRIORITY_ISSUES_PENDING	Not Started
Issues	ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED	Not Started
Review	DV_DOC_TESTPLAN_REVIEWED	Not Started
Review	V3_CHECKLIST_SCOPED	Not Started

Type	Item	Resolution
Documentation	SEC_CM_TESTPLAN_COMPLETED	Not Started
Tests	FPV_SEC_CM_VERIFIED	Not Started
Tests	SIM_SEC_CM_VERIFIED	Not Started
Coverage	SIM_COVERAGE_REVIEWED	Not Started
Review	SEC_CM_DV_REVIEWED	Not Started

Type	Item	Resolution
Documentation	DESIGN_DELTAS_CAPTURED_V3	Not Started
Tests	X_PROP_ANALYSIS_COMPLETED	Not Started
Tests	FPV_ASSERTIONS_PROVEN_AT_V3	Not Started
Regression	SIM_NIGHTLY_REGRESSION_AT_V3	Not Started
Coverage	SIM_CODE_COVERAGE_AT_100	Not Started
Coverage	SIM_FUNCTIONAL_COVERAGE_AT_100	Not Started
Coverage	FPV_CODE_COVERAGE_AT_100	Not Started
Coverage	FPV_COI_COVERAGE_AT_100	Not Started
Code Quality	ALL_TODOS_RESOLVED	Not Started
Code Quality	NO_TOOL_WARNINGS_THROWN	Not Started
Code Quality	TB_LINT_COMPLETE	Not Started
Integration	PRE_VERIFIED_SUB_MODULES_V3	Not Started
Issues	NO_ISSUES_PENDING	Not Started
Review	Reviewer(s)	Not Started
Review	Signoff date	Not Started