Registers

Summary of the core interface’s registers

INTR_STATE

Interrupt State Register

• Offset: 0x0
• Reset default: 0x0
• Reset mask: 0x3

Fields

{"reg": [{"name": "otp_operation_done", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "otp_error", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}

INTR_ENABLE

Interrupt Enable Register

• Offset: 0x4
• Reset default: 0x0
• Reset mask: 0x3

Fields

{"reg": [{"name": "otp_operation_done", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "otp_error", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}

INTR_TEST

Interrupt Test Register

• Offset: 0x8
• Reset default: 0x0
• Reset mask: 0x3

Fields

{"reg": [{"name": "otp_operation_done", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "otp_error", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}

ALERT_TEST

Alert Test Register

• Offset: 0xc
• Reset default: 0x0
• Reset mask: 0x1f

Fields

{"reg": [{"name": "fatal_macro_error", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_check_error", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_bus_integ_error", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_prim_otp_alert", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "recov_prim_otp_alert", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}

STATUS

OTP status register.

• Offset: 0x10
• Reset default: 0x0
• Reset mask: 0xfffff

Fields

{"reg": [{"name": "VENDOR_TEST_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CREATOR_SW_CFG_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "OWNER_SW_CFG_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ROT_CREATOR_AUTH_CODESIGN_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ROT_CREATOR_AUTH_STATE_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "HW_CFG0_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "HW_CFG1_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SECRET0_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SECRET1_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SECRET2_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "LIFE_CYCLE_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DAI_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "LCI_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TIMEOUT_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "LFSR_FSM_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SCRAMBLING_FSM_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "KEY_DERIV_FSM_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "BUS_INTEG_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DAI_IDLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CHECK_PENDING", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 330}}

ERR_CODE

This register holds information about error conditions that occurred in the agents interacting with the OTP macro via the internal bus. The error codes should be checked if the partitions, DAI or LCI flag an error in the STATUS register, or when an INTR_STATE.otp_error has been triggered. Note that all errors trigger an otp_error interrupt, and in addition some errors may trigger either an fatal_macro_error or an fatal_check_error alert.

• Reset default: 0x0
• Reset mask: 0x7

Instances

Fields

{"reg": [{"name": "ERR_CODE", "bits": 3, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}

ERR_CODE . ERR_CODE

DIRECT_ACCESS_REGWEN

Register write enable for all direct access interface registers.

• Offset: 0x48
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "DIRECT_ACCESS_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

DIRECT_ACCESS_REGWEN . DIRECT_ACCESS_REGWEN

This bit controls whether the DAI registers can be written. Write 0 to it in order to clear the bit.

Note that the hardware also modulates this bit and sets it to 0 temporarily during an OTP operation such that the corresponding address and data registers cannot be modified while an operation is pending. The DAI_IDLE status bit will also be set to 0 in such a case.

DIRECT_ACCESS_CMD

Command register for direct accesses.

• Offset: 0x4c
• Reset default: 0x0
• Reset mask: 0x7
• Register enable: DIRECT_ACCESS_REGWEN

Fields

{"reg": [{"name": "RD", "bits": 1, "attr": ["r0w1c"], "rotate": -90}, {"name": "WR", "bits": 1, "attr": ["r0w1c"], "rotate": -90}, {"name": "DIGEST", "bits": 1, "attr": ["r0w1c"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

DIRECT_ACCESS_ADDRESS

Address register for direct accesses.

• Offset: 0x50
• Reset default: 0x0
• Reset mask: 0x7ff
• Register enable: DIRECT_ACCESS_REGWEN

Fields

{"reg": [{"name": "DIRECT_ACCESS_ADDRESS", "bits": 11, "attr": ["rw"], "rotate": -90}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}

DIRECT_ACCESS_ADDRESS . DIRECT_ACCESS_ADDRESS

This is the address for the OTP word to be read or written through the direct access interface. Note that the address is aligned to the access size internally, hence bits 1:0 are ignored for 32bit accesses, and bits 2:0 are ignored for 64bit accesses.

For the digest calculation command, set this register to the partition base offset.

DIRECT_ACCESS_WDATA

Write data for direct accesses. Hardware automatically determines the access granule (32bit or 64bit) based on which partition is being written to.

• Reset default: 0x0
• Reset mask: 0xffffffff

Instances

Fields

{"reg": [{"name": "DIRECT_ACCESS_WDATA", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

DIRECT_ACCESS_RDATA

Read data for direct accesses. Hardware automatically determines the access granule (32bit or 64bit) based on which partition is read from.

• Reset default: 0x0
• Reset mask: 0xffffffff

Instances

Fields

{"reg": [{"name": "DIRECT_ACCESS_RDATA", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CHECK_TRIGGER_REGWEN

Register write enable for CHECK_TRIGGER.

• Offset: 0x64
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "CHECK_TRIGGER_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

CHECK_TRIGGER

Command register for direct accesses.

• Offset: 0x68
• Reset default: 0x0
• Reset mask: 0x3
• Register enable: CHECK_TRIGGER_REGWEN

Fields

{"reg": [{"name": "INTEGRITY", "bits": 1, "attr": ["r0w1c"], "rotate": -90}, {"name": "CONSISTENCY", "bits": 1, "attr": ["r0w1c"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

CHECK_TRIGGER . CONSISTENCY

Writing 1 to this bit triggers a consistency check. SW should monitor STATUS.CHECK_PENDING and wait until the check has been completed. If there are any errors, those will be flagged in the STATUS and ERR_CODE registers, and via interrupts and alerts.

CHECK_TRIGGER . INTEGRITY

Writing 1 to this bit triggers an integrity check. SW should monitor STATUS.CHECK_PENDING and wait until the check has been completed. If there are any errors, those will be flagged in the STATUS and ERR_CODE registers, and via the interrupts and alerts.

CHECK_REGWEN

Register write enable for INTEGRITY_CHECK_PERIOD and CONSISTENCY_CHECK_PERIOD.

• Offset: 0x6c
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "CHECK_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 140}}

CHECK_TIMEOUT

Timeout value for the integrity and consistency checks.

• Offset: 0x70
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CHECK_REGWEN

Fields

{"reg": [{"name": "CHECK_TIMEOUT", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CHECK_TIMEOUT . CHECK_TIMEOUT

Timeout value in cycles for the for the integrity and consistency checks. If an integrity or consistency check does not complete within the timeout window, an error will be flagged in the STATUS register, an otp_error interrupt will be raised, and an fatal_check_error alert will be sent out. The timeout should be set to a large value to stay on the safe side. The maximum check time can be upper bounded by the number of cycles it takes to readout, scramble and digest the entire OTP array. Since this amounts to roughly 25k cycles, it is recommended to set this value to at least 100’000 cycles in order to stay on the safe side. A value of zero disables the timeout mechanism (default).

INTEGRITY_CHECK_PERIOD

This value specifies the maximum period that can be generated pseudo-randomly. Only applies to the HW_CFG* and SECRET* partitions once they are locked.

• Offset: 0x74
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CHECK_REGWEN

Fields

{"reg": [{"name": "INTEGRITY_CHECK_PERIOD", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INTEGRITY_CHECK_PERIOD . INTEGRITY_CHECK_PERIOD

The pseudo-random period is generated using a 40bit LFSR internally, and this register defines the bit mask to be applied to the LFSR output in order to limit its range. The value of this register is left shifted by 8bits and the lower bits are set to 8’hFF in order to form the 40bit mask. A recommended value is 0x3_FFFF, corresponding to a maximum period of ~2.8s at 24MHz. A value of zero disables the timer (default). Note that a one-off check can always be triggered via CHECK_TRIGGER.INTEGRITY.

CONSISTENCY_CHECK_PERIOD

This value specifies the maximum period that can be generated pseudo-randomly. This applies to the LIFE_CYCLE partition and the HW_CFG* and SECRET* partitions once they are locked.

• Offset: 0x78
• Reset default: 0x0
• Reset mask: 0xffffffff
• Register enable: CHECK_REGWEN

Fields

{"reg": [{"name": "CONSISTENCY_CHECK_PERIOD", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CONSISTENCY_CHECK_PERIOD . CONSISTENCY_CHECK_PERIOD

The pseudo-random period is generated using a 40bit LFSR internally, and this register defines the bit mask to be applied to the LFSR output in order to limit its range. The value of this register is left shifted by 8bits and the lower bits are set to 8’hFF in order to form the 40bit mask. A recommended value is 0x3FF_FFFF, corresponding to a maximum period of ~716s at 24MHz. A value of zero disables the timer (default). Note that a one-off check can always be triggered via CHECK_TRIGGER.CONSISTENCY.

VENDOR_TEST_READ_LOCK

Runtime read lock for the VENDOR_TEST partition.

• Offset: 0x7c
• Reset default: 0x1
• Reset mask: 0x1
• Register enable: DIRECT_ACCESS_REGWEN

Fields

{"reg": [{"name": "VENDOR_TEST_READ_LOCK", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}

CREATOR_SW_CFG_READ_LOCK

Runtime read lock for the CREATOR_SW_CFG partition.

• Offset: 0x80
• Reset default: 0x1
• Reset mask: 0x1
• Register enable: DIRECT_ACCESS_REGWEN

Fields

{"reg": [{"name": "CREATOR_SW_CFG_READ_LOCK", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 260}}

OWNER_SW_CFG_READ_LOCK

Runtime read lock for the OWNER_SW_CFG partition.

• Offset: 0x84
• Reset default: 0x1
• Reset mask: 0x1
• Register enable: DIRECT_ACCESS_REGWEN

Fields

{"reg": [{"name": "OWNER_SW_CFG_READ_LOCK", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}}

ROT_CREATOR_AUTH_CODESIGN_READ_LOCK

Runtime read lock for the ROT_CREATOR_AUTH_CODESIGN partition.

• Offset: 0x88
• Reset default: 0x1
• Reset mask: 0x1
• Register enable: DIRECT_ACCESS_REGWEN

Fields

{"reg": [{"name": "ROT_CREATOR_AUTH_CODESIGN_READ_LOCK", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 370}}

ROT_CREATOR_AUTH_STATE_READ_LOCK

Runtime read lock for the ROT_CREATOR_AUTH_STATE partition.

• Offset: 0x8c
• Reset default: 0x1
• Reset mask: 0x1
• Register enable: DIRECT_ACCESS_REGWEN

Fields

{"reg": [{"name": "ROT_CREATOR_AUTH_STATE_READ_LOCK", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 340}}

VENDOR_TEST_DIGEST

Integrity digest for the VENDOR_TEST partition. The integrity digest is 0 by default. Software must write this digest value via the direct access interface in order to lock the partition. After a reset, write access to the VENDOR_TEST partition is locked and the digest becomes visible in this CSR.

• Reset default: 0x0
• Reset mask: 0xffffffff

Instances

Fields

{"reg": [{"name": "VENDOR_TEST_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CREATOR_SW_CFG_DIGEST

Integrity digest for the CREATOR_SW_CFG partition. The integrity digest is 0 by default. Software must write this digest value via the direct access interface in order to lock the partition. After a reset, write access to the CREATOR_SW_CFG partition is locked and the digest becomes visible in this CSR.

• Reset default: 0x0
• Reset mask: 0xffffffff

Instances

Fields

{"reg": [{"name": "CREATOR_SW_CFG_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

OWNER_SW_CFG_DIGEST

Integrity digest for the OWNER_SW_CFG partition. The integrity digest is 0 by default. Software must write this digest value via the direct access interface in order to lock the partition. After a reset, write access to the OWNER_SW_CFG partition is locked and the digest becomes visible in this CSR.

• Reset default: 0x0
• Reset mask: 0xffffffff

Instances

Fields

{"reg": [{"name": "OWNER_SW_CFG_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ROT_CREATOR_AUTH_CODESIGN_DIGEST

Integrity digest for the ROT_CREATOR_AUTH_CODESIGN partition. The integrity digest is 0 by default. Software must write this digest value via the direct access interface in order to lock the partition. After a reset, write access to the ROT_CREATOR_AUTH_CODESIGN partition is locked and the digest becomes visible in this CSR.

• Reset default: 0x0
• Reset mask: 0xffffffff

Instances

Fields

{"reg": [{"name": "ROT_CREATOR_AUTH_CODESIGN_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ROT_CREATOR_AUTH_STATE_DIGEST

Integrity digest for the ROT_CREATOR_AUTH_STATE partition. The integrity digest is 0 by default. Software must write this digest value via the direct access interface in order to lock the partition. After a reset, write access to the ROT_CREATOR_AUTH_STATE partition is locked and the digest becomes visible in this CSR.

• Reset default: 0x0
• Reset mask: 0xffffffff

Instances

Fields

{"reg": [{"name": "ROT_CREATOR_AUTH_STATE_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

HW_CFG0_DIGEST

Integrity digest for the HW_CFG0 partition. The integrity digest is 0 by default. The digest calculation can be triggered via the DIRECT_ACCESS_CMD. After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.

• Reset default: 0x0
• Reset mask: 0xffffffff

Instances

Fields

{"reg": [{"name": "HW_CFG0_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

HW_CFG1_DIGEST

Integrity digest for the HW_CFG1 partition. The integrity digest is 0 by default. The digest calculation can be triggered via the DIRECT_ACCESS_CMD. After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.

• Reset default: 0x0
• Reset mask: 0xffffffff

Instances

Fields

{"reg": [{"name": "HW_CFG1_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

SECRET0_DIGEST

Integrity digest for the SECRET0 partition. The integrity digest is 0 by default. The digest calculation can be triggered via the DIRECT_ACCESS_CMD. After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.

• Reset default: 0x0
• Reset mask: 0xffffffff

Instances

Fields

{"reg": [{"name": "SECRET0_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

SECRET1_DIGEST

Integrity digest for the SECRET1 partition. The integrity digest is 0 by default. The digest calculation can be triggered via the DIRECT_ACCESS_CMD. After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.

• Reset default: 0x0
• Reset mask: 0xffffffff

Instances

Fields

{"reg": [{"name": "SECRET1_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

SECRET2_DIGEST

Integrity digest for the SECRET2 partition. The integrity digest is 0 by default. The digest calculation can be triggered via the DIRECT_ACCESS_CMD. After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.

• Reset default: 0x0
• Reset mask: 0xffffffff

Instances

Fields

{"reg": [{"name": "SECRET2_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

SW_CFG_WINDOW

Any read to this window directly maps to the corresponding offset in the creator and owner software config partitions, and triggers an OTP readout of the bytes requested. Note that the transaction will block until OTP readout has completed.

• Word Aligned Offset Range: 0x800to0xffc
• Size (words): 512
• Access: ro
• Byte writes are not supported.

Summary of the prim interface’s registers

CSR0

• Offset: 0x0
• Reset default: 0x0
• Reset mask: 0x7ff3ff7

Fields

{"reg": [{"name": "field0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "field1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "field2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "field3", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 2}, {"name": "field4", "bits": 11, "attr": ["rw"], "rotate": 0}, {"bits": 5}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR1

• Offset: 0x4
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "field0", "bits": 7, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "field2", "bits": 7, "attr": ["rw"], "rotate": 0}, {"name": "field3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "field4", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR2

• Offset: 0x8
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "field0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR3

• Offset: 0xc
• Reset default: 0x0
• Reset mask: 0x7f3ff7

Fields

{"reg": [{"name": "field0", "bits": 3, "attr": ["rw1c"], "rotate": -90}, {"bits": 1}, {"name": "field1", "bits": 10, "attr": ["rw1c"], "rotate": 0}, {"bits": 2}, {"name": "field2", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field3", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "field4", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "field5", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "field6", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "field7", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "field8", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 9}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR4

• Offset: 0x10
• Reset default: 0x0
• Reset mask: 0x73ff

Fields

{"reg": [{"name": "field0", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 2}, {"name": "field1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "field2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "field3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 17}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR5

• Offset: 0x14
• Reset default: 0x0
• Reset mask: 0xffff3fff

Fields

{"reg": [{"name": "field0", "bits": 6, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "field2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "field3", "bits": 3, "attr": ["ro"], "rotate": -90}, {"name": "field4", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "field5", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 2}, {"name": "field6", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR6

• Offset: 0x18
• Reset default: 0x0
• Reset mask: 0xffff1bff

Fields

{"reg": [{"name": "field0", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 1}, {"name": "field1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "field2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "field3", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CSR7

• Offset: 0x1c
• Reset default: 0x0
• Reset mask: 0xc73f

Fields

{"reg": [{"name": "field0", "bits": 6, "attr": ["ro"], "rotate": 0}, {"bits": 2}, {"name": "field1", "bits": 3, "attr": ["ro"], "rotate": -90}, {"bits": 3}, {"name": "field2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "field3", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}