Registers

Summary

INTR_STATE

Interrupt State Register

• Offset: 0x0
• Reset default: 0x0
• Reset mask: 0x7fff

Fields

{"reg": [{"name": "fmt_threshold", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rx_threshold", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "acq_threshold", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "controller_halt", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "scl_interference", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "sda_interference", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "stretch_timeout", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "sda_unstable", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "cmd_complete", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "tx_stretch", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "tx_threshold", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "acq_stretch", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "unexp_stop", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "host_timeout", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 17}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}

INTR_ENABLE

Interrupt Enable Register

• Offset: 0x4
• Reset default: 0x0
• Reset mask: 0x7fff

Fields

{"reg": [{"name": "fmt_threshold", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_threshold", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "acq_threshold", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "controller_halt", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "scl_interference", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "sda_interference", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "stretch_timeout", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "sda_unstable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "cmd_complete", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "tx_stretch", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "tx_threshold", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "acq_stretch", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "unexp_stop", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "host_timeout", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 17}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}

INTR_TEST

Interrupt Test Register

• Offset: 0x8
• Reset default: 0x0
• Reset mask: 0x7fff

Fields

{"reg": [{"name": "fmt_threshold", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_threshold", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "acq_threshold", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "controller_halt", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "scl_interference", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "sda_interference", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "stretch_timeout", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "sda_unstable", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "cmd_complete", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "tx_stretch", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "tx_threshold", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "acq_stretch", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "unexp_stop", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "host_timeout", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 17}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}

ALERT_TEST

Alert Test Register

• Offset: 0xc
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

CTRL

I2C Control Register

• Offset: 0x10
• Reset default: 0x0
• Reset mask: 0x7f

Fields

{"reg": [{"name": "ENABLEHOST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ENABLETARGET", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "LLPBK", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "NACK_ADDR_AFTER_TIMEOUT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ACK_CTRL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MULTI_CONTROLLER_MONITOR_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "TX_STRETCH_CTRL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 25}], "config": {"lanes": 1, "fontsize": 10, "vspace": 290}}

CTRL . TX_STRETCH_CTRL_EN

If set to 1, this bit causes a read transfer addressed to this target to set the corresponding bit in TARGET_EVENTS.

While TARGET_EVENTS.TX_PENDING is 1, subsequent read transactions will stretch the clock, even if there is data in the TX FIFO.

If enabled, this function allows software to confirm the data in the TX FIFO should be released for the current read. This may be useful for cases where the TX FIFO has data that does not apply to the current transfer. For example, the transaction could’ve targeted an alternate function via another address.

CTRL . MULTI_CONTROLLER_MONITOR_EN

Enable the bus monitor in multi-controller mode.

If a 0->1 transition happens while CTRL.ENABLEHOST and CTRL.ENABLETARGET are both 0, the bus monitor will enable and begin in the “bus busy” state. To transition to a bus free state, HOST_TIMEOUT_CTRL must be nonzero, so the bus monitor may count out idle cycles to confirm the freedom to transmit. In addition, the bus monitor will track whether the bus is free based on the enabled timeouts and detected Stop symbols. For multi-controller mode, ensure CTRL.MULTI_CONTROLLER_MONITOR_EN becomes 1 no later than CTRL.ENABLEHOST or CTRL.ENABLETARGET. This bit can be set at the same time as either or both of the other two, though.

Note that if CTRL.MULTI_CONTROLLER_MONITOR_EN is set after CTRL.ENABLEHOST or CTRL.ENABLETARGET, the bus monitor will begin in the “bus free” state instead. This would violate the proper protocol for a controller to join a multi-controller environment. However, if this controller is known to be the first to join, this ordering will enable skipping the idle wait.

When 0, the bus monitor will report that the bus is always free, so the controller FSM is never blocked from transmitting.

CTRL . ACK_CTRL_EN

Enable I2C Target ACK Control Mode.

ACK Control Mode works together with TARGET_ACK_CTRL.NBYTES to allow software to control upper-layer protocol (N)ACKing (e.g. as in SMBus). This bit enables the mode when 1, and TARGET_ACK_CTRL.NBYTES limits how many bytes may be automatically ACK’d while the ACQ FIFO has space. If it is 0, the decision to ACK or NACK is made only from stretching timeouts and CTRL.NACK_ADDR_AFTER_TIMEOUT.

CTRL . NACK_ADDR_AFTER_TIMEOUT

Enable NACKing the address on a stretch timeout.

This is a Target mode feature. If enabled (1), a stretch timeout will cause the device to NACK the address byte. If disabled (0), a stretch timeout will cause the device to ACK the address byte. SMBus requires that devices always ACK their address, even for read commands. However, non-SMBus protocols may have a different approach and can choose to NACK instead.

Note that both cases handle data bytes the same way. For writes, the Target module will NACK all subsequent data bytes until it receives a Stop. For reads, the Target module will release SDA, causing 0xff to be returned for all data bytes until it receives a Stop.

CTRL . LLPBK

Enable I2C line loopback test If line loopback is enabled, the internal design sees ACQ and RX data as “1”

CTRL . ENABLETARGET

Enable Target I2C functionality

CTRL . ENABLEHOST

Enable Host I2C functionality

STATUS

I2C Live Status Register for Host and Target modes

• Offset: 0x14
• Reset default: 0x33c
• Reset mask: 0x7ff

Fields

{"reg": [{"name": "FMTFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FMTEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "HOSTIDLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TARGETIDLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ACQFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ACQEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ACK_CTRL_STRETCH", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}

RDATA

I2C Read Data

• Offset: 0x18
• Reset default: 0x0
• Reset mask: 0xff

Fields

{"reg": [{"name": "RDATA", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

FDATA

I2C Host Format Data

Writes to this register are used to define and drive Controller-Mode transactions.

• Offset: 0x1c
• Reset default: 0x0
• Reset mask: 0x1fff

Fields

{"reg": [{"name": "FBYTE", "bits": 8, "attr": ["wo"], "rotate": 0}, {"name": "START", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "STOP", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "READB", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RCONT", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "NAKOK", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 19}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

FDATA . NAKOK

For the currrent controller-transmitter byte (WRITE), do not halt via CONTROLLER_EVENTS or assert the ‘controller_halt’ interrupt if the current byte is not ACK’d.

FDATA . RCONT

Do not NACK the last byte read, let the read operation continue.

FDATA . READB

Transfer Direction Indicator.

If unset, this write to FDATA defines a controller-transmitter operation (WRITE). A single byte of data (FBYTE) is written to the bus.

If set, this write to FDATA defines a controller-receiver operation (READ). The value of FBYTE defines the number of bytes read from the bus. (256 if FBYTE==0)“ After this number of bytes are read, the final byte will be NACKed to end the transfer unless RCONT is also set.

FDATA . STOP

Issue a STOP condition after transmitting FBYTE.

FDATA . START

Issue a START condition before transmitting FBYTE.

FDATA . FBYTE

Format Byte.

If no flags are set, hardware will transmit this byte directly.

If READB is set, this field becomes the number of bytes hardware will automatically read from the bus.

FIFO_CTRL

I2C FIFO control register

• Offset: 0x20
• Reset default: 0x0
• Reset mask: 0x183

Fields

{"reg": [{"name": "RXRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "FMTRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 5}, {"name": "ACQRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "TXRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

HOST_FIFO_CONFIG

Host mode FIFO configuration

• Offset: 0x24
• Reset default: 0x0
• Reset mask: 0xfff0fff

Fields

{"reg": [{"name": "RX_THRESH", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 4}, {"name": "FMT_THRESH", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TARGET_FIFO_CONFIG

Target mode FIFO configuration

• Offset: 0x28
• Reset default: 0x0
• Reset mask: 0xfff0fff

Fields

{"reg": [{"name": "TX_THRESH", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 4}, {"name": "ACQ_THRESH", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

HOST_FIFO_STATUS

Host mode FIFO status register

• Offset: 0x2c
• Reset default: 0x0
• Reset mask: 0xfff0fff

Fields

{"reg": [{"name": "FMTLVL", "bits": 12, "attr": ["ro"], "rotate": 0}, {"bits": 4}, {"name": "RXLVL", "bits": 12, "attr": ["ro"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TARGET_FIFO_STATUS

Target mode FIFO status register

• Offset: 0x30
• Reset default: 0x0
• Reset mask: 0xfff0fff

Fields

{"reg": [{"name": "TXLVL", "bits": 12, "attr": ["ro"], "rotate": 0}, {"bits": 4}, {"name": "ACQLVL", "bits": 12, "attr": ["ro"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

OVRD

I2C Override Control Register

• Offset: 0x34
• Reset default: 0x0
• Reset mask: 0x7

Fields

{"reg": [{"name": "TXOVRDEN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "SCLVAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "SDAVAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}

VAL

Oversampled RX values

• Offset: 0x38
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "SCL_RX", "bits": 16, "attr": ["ro"], "rotate": 0}, {"name": "SDA_RX", "bits": 16, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TIMING0

Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification). All values are expressed in units of the input clock period. These must be greater than 2 in order for the change in SCL to propagate to the input of the FSM so that acknowledgements are detected correctly.

• Offset: 0x3c
• Reset default: 0x0
• Reset mask: 0x1fff1fff

Fields

{"reg": [{"name": "THIGH", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}, {"name": "TLOW", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TIMING1

Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification). All values are expressed in units of the input clock period.

• Offset: 0x40
• Reset default: 0x0
• Reset mask: 0x1ff03ff

Fields

{"reg": [{"name": "T_R", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}, {"name": "T_F", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 7}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TIMING2

Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification). All values are expressed in units of the input clock period.

• Offset: 0x44
• Reset default: 0x0
• Reset mask: 0x1fff1fff

Fields

{"reg": [{"name": "TSU_STA", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}, {"name": "THD_STA", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TIMING3

Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification). All values are expressed in units of the input clock period.

• Offset: 0x48
• Reset default: 0x0
• Reset mask: 0x1fff01ff

Fields

{"reg": [{"name": "TSU_DAT", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 7}, {"name": "THD_DAT", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TIMING3 . THD_DAT

Actual hold time for data (or ack) bits. (Note, where required, the parameters TVD_DAT is taken to be THD_DAT+T_F) This field is sized to have a range that accommodates Standard Mode’s 3.45 us max for TVD_DAT with a core clock at 1 GHz. However, this field is generally expected to represent a time substantially shorter than that. It should be long enough to cover the maximum round-trip latency from output pins, through pads and voltage transitions on the board, and back to the input pins, but it should not be substantially greater.

TIMING3 . TSU_DAT

Actual setup time for data (or ack) bits. This field is sized to have a range of at least Standard Mode’s 250 ns max with a core clock at 1 GHz.

TIMING4

Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification). All values are expressed in units of the input clock period.

• Offset: 0x4c
• Reset default: 0x0
• Reset mask: 0x1fff1fff

Fields

{"reg": [{"name": "TSU_STO", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}, {"name": "T_BUF", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TIMEOUT_CTRL

I2C clock stretching and bus timeout control.

This timeout must be enabled by setting TIMEOUT_CTRL.EN to 1, and the behavior of this feature depends on the value of TIMEOUT_CTRL.MODE.

If the mode is “STRETCH_TIMEOUT”, this is used in I2C controller mode to detect whether a connected target is stretching a single low time beyond the timeout value. Configured as such, this timeout is more informative and doesn’t do more than assert the “stretch_timeout” interrupt.

If the mode is “BUS_TIMEOUT”, it is used to detect whether the clock has been held low for too long instead, inclusive of the controller’s clock low time. This is useful for an SMBus context, where the VAL programmed should be tTIMEOUT:MIN.

• Offset: 0x50
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "VAL", "bits": 30, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TIMEOUT_CTRL . EN

Enable stretch timeout or bus timeout feature

TIMEOUT_CTRL . MODE

Selects the timeout mode, between a stretch timeout and a bus timeout.

Between the two modes, the primary difference is how much of the clock low period is counted. For a stretch timeout, only the time that another device holds the clock low will be counted. For a bus timeout, the entire clock low time is counted, consistent with the SMBus tTIMEOUT type.

TIMEOUT_CTRL.EN must be 1 for either of these features to be enabled.

TIMEOUT_CTRL . VAL

Clock stretching timeout value (in units of input clock frequency)

TARGET_ID

I2C target address and mask pairs

• Offset: 0x54
• Reset default: 0x0
• Reset mask: 0xfffffff

Fields

{"reg": [{"name": "ADDRESS0", "bits": 7, "attr": ["rw"], "rotate": 0}, {"name": "MASK0", "bits": 7, "attr": ["rw"], "rotate": 0}, {"name": "ADDRESS1", "bits": 7, "attr": ["rw"], "rotate": 0}, {"name": "MASK1", "bits": 7, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ACQDATA

I2C target acquired data

• Offset: 0x58
• Reset default: 0x0
• Reset mask: 0x7ff

Fields

{"reg": [{"name": "ABYTE", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "SIGNAL", "bits": 3, "attr": ["ro"], "rotate": -90}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ACQDATA . SIGNAL

Indicates any control symbols associated with the ABYTE.

For the STOP symbol, a stretch timeout or other unexpected events will cause a NACK_STOP to appear in the ACQ FIFO. If the ACQ FIFO doesn’t have enough space to record a START and a STOP, the transaction will be dropped entirely on a stretch timeout. In that case, the START byte will not appear (neither as START nor NACK_START), but a standalone NACK_STOP may, if there was space. Software can discard any standalone NACK_STOP that appears.

See the associated values for more information about the contents.

Other values are reserved.

ACQDATA . ABYTE

Address for accepted transaction or acquired byte

TXDATA

I2C target transmit data

• Offset: 0x5c
• Reset default: 0x0
• Reset mask: 0xff

Fields

{"reg": [{"name": "TXDATA", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

HOST_TIMEOUT_CTRL

I2C host clock generation timeout value (in units of input clock frequency).

In an active transaction in Target-Mode, if the Controller ceases to send SCL pulses for this number of cycles then the “host_timeout” interrupt will be asserted.

In multi-controller monitoring mode, HOST_TIMEOUT_CTRL is required to be nonzero to transition out of the initial busy state. Set this CSR to 0 to disable this behaviour.

• Offset: 0x60
• Reset default: 0x0
• Reset mask: 0xfffff

Fields

{"reg": [{"name": "HOST_TIMEOUT_CTRL", "bits": 20, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TARGET_TIMEOUT_CTRL

I2C target internal stretching timeout control. When the target has stretched beyond this time it will send a NACK for incoming data bytes or release SDA for outgoing data bytes. The behavior for the address byte is configurable via CTRL.ACK_ADDR_AFTER_TIMEOUT. Note that the count accumulates stretching time over the course of a transaction. In other words, this is equivalent to the SMBus cumulative target clock extension time.

• Offset: 0x64
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "VAL", "bits": 31, "attr": ["rw"], "rotate": 0}, {"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TARGET_NACK_COUNT

Number of times the I2C target has NACK’ed a new transaction since the last read of this register. Reading this register clears it. This is useful because when the ACQ FIFO is full the software know that a NACK has occurred, but without this register would not know how many transactions it missed. When it reaches its maximum value it will stay at that value.

• Offset: 0x68
• Reset default: 0x0
• Reset mask: 0xff

Fields

{"reg": [{"name": "TARGET_NACK_COUNT", "bits": 8, "attr": ["rc"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}

TARGET_ACK_CTRL

Controls for mid-transfer (N)ACK phase handling

• Offset: 0x6c
• Reset default: 0x0
• Reset mask: 0x800001ff

Fields

{"reg": [{"name": "NBYTES", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 22}, {"name": "NACK", "bits": 1, "attr": ["wo"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TARGET_ACK_CTRL . NACK

When the Target module stretches on the (N)ACK phase of a Write due to TARGET_ACK_CTRL.NBYTES being 0, writing a 1 here will cause it to send a NACK.

If software chooses to NACK, note that the NACKing behavior is the same as if a stretch timeout occurred. The rest of the transaction will be NACK’d, including subsequent transfers. For the address byte, the (N)ACK phase of subsequent transfers will follow the behavior specified by CTRL.NACK_ADDR_AFTER_TIMEOUT.

Automatically clears to 0.

TARGET_ACK_CTRL . NBYTES

Remaining number of bytes the Target module may ACK automatically.

If CTRL.ACK_CTRL_EN is set to 1, the Target module will stretch the clock at the (N)ACK phase of a byte if this CSR is 0, awaiting software’s instructions.

At the beginning of each Write transfer, this byte count is reset to 0. Writes to this CSR also are only accepted while the Target module is stretching the clock. The Target module will always ACK its address if the ACQ FIFO has space. For data bytes afterwards, it will stop at the (N)ACK phase and stretch the clock when this CSR is 0. For each data byte that is ACK’d in a transaction, the byte count will decrease by 1.

Note that a full ACQ FIFO can still cause the Target module to halt at the beginning of a new byte. The ACK Control Mode provides an additional synchronization point, during the (N)ACK phase instead of after. For both cases, TARGET_TIMEOUT_CTRL applies, and stretching past the timeout will produce an automatic NACK.

This mode can be used to implement the mid-transfer (N)ACK responses required by various SMBus protocols.

ACQ_FIFO_NEXT_DATA

The data byte pending to be written to the ACQ FIFO.

This CSR is only valid while the Target module is stretching in the (N)ACK phase, indicated by STATUS.ACK_CTRL_STRETCH . It is intended to be used with ACK Control Mode, so software may check the current byte.

• Offset: 0x70
• Reset default: 0x0
• Reset mask: 0xff

Fields

{"reg": [{"name": "ACQ_FIFO_NEXT_DATA", "bits": 8, "attr": ["ro"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}

HOST_NACK_HANDLER_TIMEOUT

Timeout in Host-Mode for an unhandled NACK before hardware automatically ends the transaction. (in units of input clock frequency)

If an active Controller-Transmitter transfer receives a NACK from the Target, the CONTROLLER_EVENTS.NACK bit is set. In turn, this causes the Controller FSM to halt awaiting software intervention, and the ‘controller_halt’ interrupt may assert. Software must clear the CONTROLLER_EVENTS.NACK bit to allow the state machine to continue, typically after clearing out the FMTFIFO to start a new transfer. While halted, the active transaction is not ended (no STOP (P) condition is created), and the block asserts SCL and leaves SDA released.

This timeout can be used to automatically produce a STOP condition, whether as a backstop for slow software responses (longer timeout) or as a convenience (short timeout). If the timeout expires, the Controller FSM will issue a STOP (P) condition on the bus to end the active transaction. Additionally, the CONTROLLER_EVENTS.UNHANDLED_NACK_TIMEOUT bit is set to alert software, and the FSM will return to the idle state and halt until the bit is cleared.

The enable bit must be set for this feature to operate.

• Offset: 0x74
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "VAL", "bits": 31, "attr": ["rw"], "rotate": 0}, {"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CONTROLLER_EVENTS

Latched events that explain why the controller halted.

Any bits that are set must be written (with a 1) to clear the CONTROLLER_HALT interrupt.

• Offset: 0x78
• Reset default: 0x0
• Reset mask: 0xf

Fields

{"reg": [{"name": "NACK", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "UNHANDLED_NACK_TIMEOUT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "BUS_TIMEOUT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "ARBITRATION_LOST", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}}

TARGET_EVENTS

Latched events that can cause the target module to stretch the clock at the beginning of a read transfer.

These events cause TX FIFO-related stretching even when the TX FIFO has data available. Any bits that are set must be written (with a 1) to clear the tx_stretch interrupt.

This CSR serves as a gate to prevent the Target module from responding to a read command with unrelated, leftover data.

• Offset: 0x7c
• Reset default: 0x0
• Reset mask: 0x7

Fields

{"reg": [{"name": "TX_PENDING", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "BUS_TIMEOUT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "ARBITRATION_LOST", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}

TARGET_EVENTS . ARBITRATION_LOST

A Target-Mode read transfer has terminated due to lost arbitration.

TARGET_EVENTS . BUS_TIMEOUT

A Target-Mode read transfer has terminated due to a bus timeout activated by TIMEOUT_CTRL.

TARGET_EVENTS . TX_PENDING

A new Target-Mode read transfer has arrived that addressed this target.

This bit is used by software to confirm the release of the contents in the TX FIFO. If the contents do not apply, software should first reset the TX FIFO, then load it with the correct data, then clear this bit.

Optionally enabled by CTRL.TX_STRETCH_CTRL_EN.