DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING SAINTGITS COLLEGE OF ENGINEERING

OUR GUIDE ASWIN P.V ASSISTANT PROFFESSOR ELECTRONICS &COMMUNICATION DEPT SAINTGITS COLLEGE OF ENGINEERING

PRESENTED BY Bipin S Vineeth P Sanil Moncy Mohammed Shafeeq A

FOCUZ INFOTECH MAMANGALAM ERNAKULAM

INTRODUCTION BLOCK DIAGRAM EXPLANATION

DESIGN
FIXED POINT FLOATING POINT

ADVANTAGES
LIMITATIONS FUTURE ENHANCEMENT CONCLUSION REFERENCE

INTRODUCTION
A low cost 32bit RISC Processor has been designed and synthesized The design has been described using Verilog, and synthesis have been implemented and tested on Xilinx FPGA. Spartan 3E have been used for the hardware implementation. It has mainly two modules which are fixed point unit and floating point unit.

Contd

VLSI Basics
VLSI stands for "Very Large Scale Integration"

It is the process of creating integrated circuits by combining thousands of transistors into a single chip.
This has opened up a big opportunity to do things that were not possible before, The microprocessor is a VLSI device.

Cont

MOST OF TODAYS VLSI DESIGNS ARE CLASSIFIED INTO THREE CATEGORIES: 1. Analog: Small transistor count precision circuits such as Amplifiers, Data converters, filters...etc. 2. ASIC (Application Specific Integrated Circuits): These are IC's that are created for specific purposes - each device is created to do a particular job, The most common application area for this is DSP - signal filters, image compression, etc. 3. SoC (Systems on a chip): These are highly complex mixed signal circuits (digital and analog all on the same chip). e.g:-A network processor chip or a wireless radio chip.

What is RISC?
Reduced Instruction Set Computer Fastest instruction execution. Instructions are of same size and execute within a single cycle. Efficient way of completing a operation. Reduces hardware space complexity.

Properties
Smaller number of instruction commands. Single word standard length. Large general purpose CPU registers. Less cost to design, test and manufacture. Fixed length and easy decoder format.

RISC Vs CISC
RISC Simple instruction taking one cycle Very few instruction refer memory Instructions are executed by hardware Few addressing modes & Most instructions have Register to Register addressing modes Complexity is in the compiler CISC Complex instruction taking multiple cycle Most of the instruction may refer memory Instructions are executed by microprogram Many addressing modes Complexity is in the microprogram

FPGA
An FPGA is a silicon wafer, which can have up to several hundred thousand digital Cells FPGAs are programmable, and their interconnection will shaped based on your design. They must be programmed each time on startup, since most of them cannot retain their configuration after power-down, as they use RAM technology. Ability to perform unlimited tasks in parallel, something that cannot be achieved in processors, as they can execute instructions one-byone in a sequential manner.

Block Diagram Explanation

DESIGN
RISC PROCESSOR WITH DEDICATED FPU

Verilog HDL

Verilog HDL is similar to C language, a hardware descriptor language Invented mainly for digital hardware designers developing FPGA (Field programmable Gate Arrays) and ASICs (Application-specific Integrated Circuit). Allows different levels of abstraction like switches, gates, RTL etc Behavioural, Dataflow models ,Gate Level Model, Switch Model. Popular synthesis tools support Verilog HDL, which makes popular among designers

Verilog Contd..Used Models

Used only Behavioral and Dataflow models. Behavioral Model-High level data abstraction, doesnt consider hardware implementation. Dataflow Models-Designed based on flow of data. A user must aware about flow of data through hardware registers and processing.

Program Flow

CONTROL LOGIC

Fixed Point Modules

ADDER

SUBSTRACTOR

BIT OPERATIONS

SHIFT LEFT SHIFT LEFT ROTATE LEFT ROTATE RIGHT

LOGIC FUNCTION

NOT (INVERTER) LOGIC

AND LOGIC

OR LOGIC

NAND LOGIC

NOR LOGIC

XOR LOGIC

FLOATING POINT
Floating-point numbers and operations are like scientific notation Number has sign, mantissa, exponent Example - -1.453*10-4 Addition and subtraction have similar stages Align small number to larger (in absolute value) Add/subtract Renormalize if needed (so mantissa is smaller than base and >=1) Consequences Number has sign, exponent, and magnitude fields S&M used for magnitudes since absolute value is needed Separate ALUs are needed than for fixed point operations

IEEE SPECIFICATIONS

type short Sign bit Exponent Mantissa

MSB implicit

Exp size 8

Mant. size

Total 32

23

long
extended

implicit
explicit

11
15

52
64

64
80

Algorithm
Step 1 : Choose the number with smaller exponent and shift its mantissa right a number of steps equal to the difference in exponents. Step 2 : Set the exponent of result equal to the larger exponent. Step 3 : Perform add/sub on the mantissas and determine the sign of the result. Step 4 : Normalize the resulting value if necessary.

Flow diagram FPU

EXAMPLE
+1.5= 0 01111111 10000000000000000000000 299.25= 0 10000111 00101011010000000000000 N= (-1)s 2E-127 (1.M)

General form of a FPU for addition

Sign comparison Since mantissas are in S&M, second argument sign is flipped for subtraction, then S&M addition rules are followed Exponent comparison Normal complement subtraction of exponents cancels out the excess in the representation. The operands are swapped if the second operand has the larger exponent difference Addition This is a standard S&M addition, but it must include the extra bits normalization This shift can be from one place right to many places left if the difference is small. Rounding decisions are made here and not earlier

EXAMPLE WITH VALUES

X=0 01111111 10000000000000000000000 Y=0 10000111 00101011010000000000000

X+Y=0 10000111 00101100110000000000000

Contd..

INSTRUCTION SET

MODELSIM
ModelSim provides an Integrated Debug Environment that facilitates efficient design debug for SoC and FPGA based designs. This environment is trilingual supporting designs based on VHDL, Verilog (all standards including SystemVerilog, Verilog 2001 and Verilog 1995), and SystemC

Contd.

Consistent look and feel for all languages Root cause isolation Coverage analysis and reporting

Common control & behavior for all windows

Any window can form a tab group with any other window
32

SYNTHESIZING SOFTWARE:XILINX

this tool is used for hardwire implementation it supports both verilog and VHDL it shows the RTL schematic using this we assign the pin config: by this tool the programs are dubbed to the kit

THE XILINX SPARTAN 3E

The Spartan-3E family of Field-Programmable Gate Arrays (FPGAs) is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. Features It has Five Lakh gates Has 16 I/O pins. Operates at 3.3,2.5,1.8,1.2 volt Very low cost, high-performance logic solution for high-volume, consumer-oriented applications Proven advanced 90-nanometer process technology

ADVANTAGES
Instruction set is simpler. 32-bit floating Point

RISC-based designs is better in speed and ability than CISC design.

RISC has fewer than 100 instructions.

Single cycle execution.

LIMITATIONS

Can implement only up to 5 lakh gates. Provides no inbuilt memory on current Spartan 3E device. Limited number of pin. Volatile device.

FUTURE ENHANCEMENTS

The designed arithmetic unit operates on 32-bit operends. It can be designed for 64-bit operands to enhance precision. It can be extended to have more mathematical operations like trigonometric, logarithmic and exponential functions.
The features of RISC processor can be extended by including Generic Statement, Load and Store instructions. This facilitate running the program continuously, increasing the number of bits. Sony Computer Entertainment Inc. (SCEI) has long relied on the RISC architecture, most notably for its PlayStation family of products.

Contd
Currently developing a RISC processor with 1000 cores By creating more than 1,000 mini-circuits within the FPGA chip, the researchers effectively turned the chip into a 1,000-core processor - each core working on its own instructions. .

CONCLUSION
RISC is an evolution in computer architecture. Emphasizes on speed and cost-effectiveness over the ease of assembly-language programming and conservation of memory. RISC-based designs will continue to grow in speed and ability, more rapidly than CISC design.

REFERENCE

WWW.XILINX.COM WWW.IEEEXPLORE.ORG

WWW.WIKIPEDIA.COM
WWW.MEMEC.COM