TUGAS ELEKTRONIKA – 1

DISUSUN OLEH :
KELOMPOK 2:
 Yufiltro Simamora (14S18006)
 Rut Sahayana Hutasoit (14S18013)
 Christine Sibarani (14S18038)

5.2. For a 0.8-μm process technology for which t ox = 15 nm and μn = 550 cm2/V⋅s, find Cox,krn
, and the overdrive voltage VOV required to operate a transistor having in W/L=20 in
saturation with ID=0.2 mA. What is the minimum value of VDS needed?
Penyelesain:
є𝑜𝑥
Cox=𝑡𝑜𝑥 =2.3fF/ μm2
μn =550 cm2/V⋅s
Krn = μn Cox =1265 μA/V2
1 𝑊 𝑊
ID =2krn 𝐿 v2OV =0,2mA, 𝐿 =20
Vov =0,40 V
VDS ,min = Vov=0,40 V,for saturasion.
5.6. An NMOS transistor is fabricated in a 0.4-μm process having μnCox = 200 μA/ V2 and
VIA =50 V/ μm of channel length. If L = 0.8 μm and W = 16 μm, find VA and λ . Find the
value of ID that results when the device is operated with an overdrive voltage Vov = 0.5 V
and VDS = 1 V. Also, find the value of ro at this operating point. If VDS is increased by 2
V, what is the corresponding change in ID?
Penyelesaian:
VA = VIA L=50×0.8=40 V
1
Λ= n 𝑉𝐴 =0,025V-1
VDS = 1V> Vov= =0.5 V
1 𝑊
⇒Saturation ID =2krn 𝐿 v2OV (1 + λ VDS )
1 16
ID =2 × 200 × 0.8 ×0.52 (1 + 0,025×1 )=0,51mA
𝑉𝐴 40
ro = ID = 0,5 = 80 kΩ
where ID is the value of ID without channel-length modulation taken into account.
Δ𝑉𝐷𝑆 2𝑉
ro = Δ𝐼0 ⇒ Δ𝐼0 =80 𝑘Ω =0.025 mA
5.7. The PMOS transistor shown in Fig. E5.7 has Vtp =-1 V, ktp =60 μA/V2 and W/L=10
(a)Find the range of VG for which the transistor conducts.
(b)In terms of VG, find the range of VD for which the transistor operates in the triode
region.
(c)In terms of VG, find the range of VD for which the transistor operates in saturation.
(d)Neglecting channel-length modulation (i.e., assuming λ = 0), find the values of |V OV
|and and VG the corresponding range of VD to operate the transistor in the saturation
mode with ID = 75 μA.
(e) If λ = −0.02 V−1, find the value of ro corresponding to the overdrive voltage
determined in (d)
(f) For λ = −0.02 V-1 and for the value of VOV determined in (d), find ID at VD= +3 V and
at VD = 0 V; hence, calculate the value of the apparent output resistance in saturation.
Compare to the value found in (e).
Penyelesaian:
Vtp =-1 V
ktp =60 μA/V |
𝑊
=10⇒kp =600 μA/V2
𝐿

(a)condution occurs for VSG ≥| Vtp |=1 V

⇒ VG ≤5-1=4
(b)triode region occurs for VDG≥| Vtp |=1 V
⇒ VD ≥ VG +1
(c) Conversely, for saturation
VDG≥| Vtp |=1 V
⇒ VD ≤VG +1
(d).Given λ ≡0
1 𝑊
ID =2kp |vOV |2 =75 μA
𝐿

|VOV|=0.5 V=VSG −|VTP|

⇒ VSG =| VOV|+| VTP|=1.5 V
VG=5−|GVS|=3.5 V
VD ≤VG +1=4.5 V
(e) For λ =−0.02 V-1 and| VOV |=0.5 V,
1
ID =75 μA and r0 =|λ|ID =667 kΩ
(f) At VD=3 V, VSD =2V
1 𝑊
ID =2kp |vOV |2 =(1 +| λ|| VSD |)
𝐿

= 75 μA(1.04) =78 μA
At VD =0 V, VSD=5 V
ID =75 μA (1.10)=82.5
Δ𝑉𝐷𝑆 3V
r0 = = =667 k Ω
Δ𝐼0 4,5 μA
 which is the same value found in (c).
5.14. For the circuit in Fig. E5.14, find the value of R that results in the PMOS transistor
operating with an overdrive voltage |Vov |=0.6 V.The threshold voltage is Vtp,=-0,4 V, the
process transconductance parameter ktp =0.1 mA/V2, and W/L = 10 μm/0.18 μm.
Penyelesaian:

Vtp=−0.4 V
ktp =0.1 mA/V2
𝑊 10 μm
=0,18 μm ⇒ kp= 5.56 mA/V2
𝐿

VSG =| Vtp |+| Vov| =0.4+0.6=1 V

VS = +1 V
Since Vdg =0, the transistor is operating in saturation, and
1
ID =2kpvOV 2 =1 Ma
1.8−1
R= =0.8 kΩ =800 Ω
1

5.15. The NMOS and PMOS transistors in the circuit of Fig. E5.15 are matched with ktn
(Wn/Ln )= ktp = Wp/Lp ) and Vtn =-Vtp =1 V.Assuming λ=0 for both devices, find the drain
currents iDn and iDp and the voltage V0 for vI +2.5 V, and −2.5 V.
Penyelesaian:
Vt=0: since the circuit is perfectly symmetrical, v0 =0 and therefore VGS =0, which implies
that the transistors are turned off and IDN = I0P =0. vt =2.5 V: if we assume that the NMOS
is turned on, then V0 would be less than 2.5 V, and this implies that PMOS is off (VGSP<
0).
1 𝑊
ID =2 ktp 𝐿 (VGS – Vt )2
 1
IDN =2 ×1(2.5−, v0 −1)2

IDN = 0.5(1.5− v0)2

Also: v0 = RL IDN =10 IDN
⇒100 I 2DN −32 IDN +2.25=0⇒ IDN =0.104 mA
IDP =0, V0 =10×0.104=1.04V

Vt=−2.5 V:Again if we assume that QP is turned on, then v0 > −2.5 V and vGST < 0,
which implies that the NMOS QP is turned off.
IDN =0
Because of the symmetry:
IDP=0.104, V0=− IDP ×10 k Ω=1,23 V
5.18. Consider the amplifier circuit of Fig. 5.39(a) without the load resistance RL and with
channel length modulation neglected. Let VDD =5V, Vt =0,7 V, and kn mA/V2. Find ,
VOV, ID , RD and RG to obtain a voltage gain of 25 V/V and an input resistance of 0.5
MΩ . What is the maximum allowable input signal,vi?
Penyelesaian:
𝑣𝑜
𝐴𝑣 = = −25, 𝑅𝑖𝑛 = 500 𝑘Ω
𝑣𝑡
∴ 𝑅𝑖𝑛 𝑅𝐷 = 25 = 𝑘𝑛 𝑉𝑂𝑉 𝑅𝐷
𝑣𝑖 𝑣𝑖
𝑅𝑖𝑛 = = 𝑅
𝑖𝑖 𝑣𝑖 − 𝑣𝑜 𝐺
⇒ 𝑅𝐺 = 26𝑅𝑖𝑛 = 13 𝑀Ω
1
𝐼𝐷 𝑅𝐷 = ( 𝑘𝑛 𝑉𝑂𝑉 2 ) 𝑅𝐷
2
1
= 𝑔 𝑅 𝑉 = 12.5 𝑉𝑂𝑉
2 𝑚 𝐷 𝑂𝑉

𝑉𝑂𝑉 = 𝑉𝐷𝐷 − 𝑉𝑡 − 𝐼𝐷 𝑅𝐷 = 4.3 − 12.5 𝑉𝑂𝑉

∴ 𝑉𝑂𝑉 = 0.319 𝑉
𝑔𝑚 = 319 𝜇𝐴/𝑉
 𝑅𝐷 = 78.5 𝑘Ω
𝑉𝐷𝑆 = 𝑉𝑂𝑉 + 𝑉𝑡
𝑣̂
𝐺𝐷 = 0 + 26𝑣
̂𝑖 ≤ 𝑉𝑡
𝑉𝑡
∴ |𝑣̂𝑖 | < = 27 𝑚𝑉
26

1.1. We applied an input signal Vsig of 50 mV peak and obtained an output signal of
approximately 1 V peak. Assume that for some reason we now have an input signal Vsig
that is 0.2 V peak and that we wish to modify the circuit to keep unchanged, and thus
keep the nonlinear distortion from increasing. What value should we use for Ri ? What
value of Gv will result? What will the peak signal at the output become? Assume r0 =∞
Penyelesaian:
𝑔𝑚 = 2 𝑚𝑆
𝑣𝑔𝑠 1 50 𝑚𝑉
= = ⇒ 𝑔𝑚 𝑅𝑆 = 3
𝑉𝐷𝑖𝑔 1 + 𝑔𝑚 𝑅𝑆 200 𝑚𝑉
∴ 𝑅𝑆 = 1.5 𝑘Ω
−𝑔𝑚 (𝑅𝐷 ||𝑅𝐿 ) −20
𝐺𝑉 = 𝐴𝑉 = = = −5
1 + 𝑔𝑚 𝑅𝑆 4
̂𝑜 = |𝐺𝑉 𝑣̂
𝑣 𝑠𝑖𝑔 | = 1 𝑉

5.29. A CG amplifier is required to match a signal source with Rsig . At what current ID
should the MOSFET be biased if it is operated at an overdrive voltage of 0.20 V? If the
total resistance in the drain circuit is 2 k Ω , what overall voltage gain is realized?
Penyelesaian:

5.33. Consider the MOSFET in Example 5.12 when fixed-vGS bias is used. Find the required
value of vGS to establish a dc bias current ID = 0.5 mA. Recall that the device
parameters are Vt = 1 V, ktn W/L = 1 ma/V2 and λ = 0. What is the percentage change in
ID obtained when the transistor is replaced with another having Vt = 1.5 V?
Penyelesaian:

1 𝑊
𝐼𝐷 = 𝑘𝑛 (𝑉𝐺𝑆 − 𝑉𝑡 )2 ⇒ 0.5 𝑚𝐴
2 𝐿
1
= × 1(𝑉𝐺𝑆 − 1)2
2
𝑉𝐺𝑆 = 2 𝑉
If 𝑉𝑡 = 1.5 𝑉 then :
1
𝐼𝐷 = × 1 × (2 − 1.5)2 = 0.125 𝑚𝐴
2
 ∆𝐼𝐷 0.5 − 0.125
⇒ = = 0.75 = 75%
𝐼𝑜 0.5

9.1. The amplifier in Fig. P9.1 is biased to operate at gm= 1 mA/V. Neglecting ro, find the
midband gain. Find the value of CS that places fL at 20 Hz.
Penyelesaian :
−𝑅𝐺
𝐴𝑀 = × 𝑔𝑚 (𝑅𝐿 ||𝑅𝐷 )
𝑅𝐺 + 𝑅𝑠𝑖𝑔
10 10 𝐾
=− ×2×
10 + 0.1 2
𝐴𝑀 = −9.9 𝑉 ⁄𝑉
1
𝑓𝑃1 =
2𝜋𝐶𝐶1 (𝑅𝐺 + 𝑅𝑠𝑖𝑔 )
1
= = 0.016 𝐻𝑧
2𝜋 × 1 𝜇 × (10 + 0.1 𝑀 )
1 1
𝑓𝑃2 = = = 318 𝐻𝑧
2𝜋𝐶𝑆 /𝑔𝑚 2𝜋 × 1 𝜇/2𝑚
1 1
𝑓𝑃3 = =
2𝜋𝐶𝐶2 (𝑅𝐿 + 𝑅𝐷 ) 2𝜋 × 1 𝜇 × (10 + 10)
= 8 𝐻𝑧
𝑓𝐿 ≃ 𝑓𝑃2 = 318 𝐻𝑧

9.2. Consider the amplifier of Fig. 9.2(a). Let RD = 10 kΩ, ro= 100 kΩ, and RL = 10 kΩ.
Find the value of CC2, specified to one significant digit, to ensure that the associated
break frequency is at, or below, 10 Hz. If a higher-power design results in doubling ID,
with both RD and ro reduced by a factor of 2, what does the corner frequency (due to
CC2) become? For

increasingly higher-power designs, what is the highest corner

frequency that can be associated with CC2?
Penyelesaian :
𝐶𝐶1 = 𝐶𝐸 = 𝐶𝐶2 = 1 𝜇𝐹
𝑔𝑚 = 40 𝑚𝐴⁄𝑉 → 𝐼𝐶 = 40 𝑚 × 25 𝑚 = 1 𝑚𝐴
 𝛽
𝑟𝜋 = 2.5 𝑘Ω = ⇒ 𝛽 = 100
𝑔𝑚
𝑉𝑇 25 𝑚𝑉
𝑟𝑒 = = = 25 Ω
𝐼𝐸 1 𝑚𝐴
1
𝑓𝑃1 =
2𝜋𝐶𝐶1 [𝑅𝐵 ∥ 𝑟𝜋 + 𝑅𝑠𝑖𝑔 ]
1
=
2𝜋 × 1 𝜇 [100 𝐾 ∥ 2.5 𝐾 + 5 𝐾 ]
𝑓𝑃1 = 21.4 𝐻𝑧
1
𝑓𝑃2 =
𝑅𝐵 ∥ 𝑅𝑠𝑖𝑔
2𝜋𝐶𝐸 [𝑟𝑒 + 𝛽 + 1 ]

1
𝑓𝑃2 =
100 𝐾 ∥ 5 𝐾
2𝜋 × 1 𝜇 [25 + ]
101
𝑓𝑃2 = 2.2 𝐾𝐻𝑧
1
𝑓𝑃3 =
2𝜋𝐶𝐶2 (𝑅𝐶 + 𝑅𝐿 )
1
=
2𝜋 × 1 𝜇(8 𝐾 + 5 𝐾 )
𝑓𝑃3 = 12.2 𝐻𝑧
9.8. Repeat Exercise 9.2 for the situation in which CE = 50μF and Cc1 = Cc2 = 2μF. Find the
three break frequencies and estimate .
Penyelesaian :
𝑅𝑔
a. AM =− 𝑅𝑔+𝑅𝑠𝑖𝑔 ∗ (𝐺𝑚𝑅′ 𝑙)
4.7∗106
AM = − 4.7∗106 +10∗103 ∗ (7.14)
4.7
AM = − 4.71 ∗ (7.14)
AM = -0.99787 * (7.14)
𝑉
AM = -7.12 𝑉

1
b. FH = 2𝜋𝐶𝑖𝑛𝑅′𝑠𝑖𝑔
R’sig = Rsig || RG
𝑅𝑠𝑖𝑔𝑅𝑔
FH = 𝑅𝑠𝑖𝑔+𝑅𝑔
𝑅𝑠𝑖𝑔+𝑅𝑔
FH = 2𝜋𝐶𝑖𝑛𝑅𝑠𝑖𝑔𝑅𝑔
104 +4.7∗10^6
FH = 2∗3.14∗4.26∗10−12 ∗104 ∗4.7∗10^6
FH = 3.747 * 106
FH = 3.7 MHz
9.10. A particular current-biased CE amplifier operating at 100 from -V power supplies
employs k , k ; it operates between a 20-k source and a 10-k load. The transistor . Select
first for a minimum value specified to one significant digit and providing up to 90% of .
Then choose and , each specified to one significant digit, with the goal of minimizing
the total capacitance used. What results? What total capacitance is needed?
Penyelesaian :
a. R’L = ro || RC || RL
𝑟𝑜∗𝑅𝑐∗𝑅𝑙
R’L = 𝑟𝑜∗𝑅𝑐+𝑅𝑙∗(𝑟𝑜+𝑅𝑐)
𝑟𝑜∗𝑅𝑐∗𝑅𝑙
R’L = 𝑟𝑜∗𝑅𝑐+𝑅𝑙∗𝑟𝑜+𝑅𝑙∗ 𝑅𝑐)
100𝐾∗8𝐾∗𝑅𝑙
R’L = 100𝐾∗8𝐾+𝑅𝑙∗100𝐾+𝑅𝑙∗ 8𝐾)
100𝐾∗8∗𝑅𝑙
R’L = 100𝐾∗8+𝑅𝑙∗100+𝑅𝑙∗ 8)
800𝐾∗𝑅𝑙
R’L = 800𝐾+𝑅𝑙∗108
800𝐾∗𝑅𝑙
1.5K = 800𝐾+𝑅𝑙∗108
800∗𝑅𝑙
1.5 = 800𝐾+𝑅𝑙∗108
1.5 * (800K +RL * 108) = 800 * RL
1200K + RL * 162 = 800 * RL
RL * 162 = 800 * RL – 1200K
RL * 162 – 800 * RL = -1200K
-638 * RL = -1200K
638 * RL = 1200K
1200𝐾
RL = 638
RL = 1.88K
1
b. FH = 2𝜋𝐶𝑖𝑛𝑅′𝑠𝑖𝑔
Cin = Cπ + Cµ (1+gmR’L)
= 7p + 1p (1+ 0.04 * R’L)
= 7p + 1p (1 + 0.04 * 1.5k)
= 7p + 1p (1 + 0.04 *1.5 * 1000)
= 7p + 1p (1 + 60)
= 7p + 61p
= 68pF
1
FH = 2𝜋𝐶𝑖𝑛𝑅′𝑠𝑖𝑔
1
FH = 2𝜋68∗10−12 ∗ 𝑅′𝑠𝑖𝑔
1
FH = 2𝜋68∗10−12 ∗ 1.65∗10^3
1
FH = 2𝜋68∗10^−9∗ 1.65
10^9
FH = 2𝜋68∗ 1.65
10^9
FH = 704.97
FH = 0.00142 * 109
FH = 1.42 * 106
FH = 1.42 MHz
1.42
c. fH ratio =
0.754
fHratio = 1.9
13.1 Design Design the inverter in Fig. 13.2(a) to provide VOL = 0.1 V and to draw a supply
current of 50 µAin the low-output state Let the transistor be specified to have Vt = 0.5V,µn
Cox = 125µA/,and λ = 0. The power supply VDD = 2.5V . Specify the required values
of W/L and RD . How much power is drawn from when the switch is open? Closed?
Hint: Recall that for small VDS
Pertama kita tentukan nilai 𝑟𝐷𝑠
𝑉
𝑟𝐷𝑠 = 𝐼 𝑜𝑙
𝐷𝐷
0,1
𝑟𝐷𝑠 = 50 𝑥 10−6
= 2 𝑥 103
= 2 𝑘Ω
Tentukan nilai W/L
1
𝑟𝐷𝑠 = 𝑊
C𝑂𝑋 𝑉𝐷𝐷 −𝑉𝑡
𝐿
3 1
2 𝑥 10 = 𝑊
125 𝑥 10−6 2,5−0,5
𝐿
𝑊 1
=
𝐿 (250 𝑥 10 ) (2 𝑥 103 )
−6
𝑊 1
=
𝐿 0,5
𝑊
=2
𝐿
Selanjutnya kita cari nilai dari 𝑅𝐷
𝑟
𝑉0𝐿 = 𝑉𝐷𝐷 𝑅 +𝐷𝑠𝑟
𝐷 𝐷𝑠
2 𝑥 103
0,1 = (2,5) 𝑅𝐷 + 2 𝑥 103
0,1𝑅𝐷 +(2,5)=500
500 − 200
𝑅𝐷 =
0,1
= 48 𝑥 103
=48kΩ
Selanjut nya mencari daya pada saat switch open
Pada saat switch open tidak ada tidak ada arus megalir pada loop sehingga daya pada
saat switch open adalah 0 atau 𝑃𝑜𝑝𝑒𝑛 = 0
Mencari daya pada saat switch close
𝑃𝑐𝑙𝑜𝑠𝑒 = 𝑉𝐷𝐷 𝐼𝐷𝐷
𝑃𝑐𝑙𝑜𝑠𝑒 = (2,5)( 50 𝑥 10−6
=1,25 𝑥 10−4
=125µW
13.2 For the current-steering circuit in Fig. 13.9, let and let 𝑉𝑐𝑐 = 5 V, 𝑉𝐸𝐸 =1mA ,and 𝑅𝐶1
=𝑅𝐶2 = 2kΩ.. What are the high and low logic levels obtained at the outputs?
Jawab

Saat input hight output low sama dengan 𝑉𝑜𝐻 pada kasus ini switch terhubung dengan
𝑅𝐶2 .dimana arus pada 𝑅𝐶1 adalah 0,oleh sebab itu maka 𝑉𝑜𝐻 = 𝑉𝑂𝐿 =5 volt

Ketika input hight ,output low dan sama dengan vout ,dimana switch terhubung ke 𝑅𝐶1
oleh Karena itu 𝑉𝑂𝐿 =𝑉𝑐𝑐 - 𝑅𝐶1 . 𝐼𝐸𝐸
 𝑉𝑂𝐿 = 5 − (2𝑥1)
=3

13.3 In an attempt to reduce the required value of 𝑅𝐷 to 10 kΩ the designer of the inverter
in Example13.1 decides to keep the parameter 𝑉𝑥 unchanged but increases W/L. What
is the new value required for W/L? Do the noise margins change? What does the power
dissipation become?
𝑉
To determine 𝑉𝑥 at 𝑉𝑀 = 𝐷𝐷 2
𝑉
( 𝐷𝐷 −𝑉𝑡 )2
2
𝑉𝑥 |𝑉𝑀 = 𝑉𝐷𝐷
1,8
( −0,5𝑡 )2
2
= 1,8
0,16
= 1.8
=0,0889 v
𝑘𝑛 = 300 µ
1
𝑘𝑛 𝑅𝐷 = substitusi v diatas
𝑉
𝑊 1
300 x 300 𝑥 10−6 x 𝐿
x 10 x 103 =0.089
𝑊
Sehingga 𝐿 = 3,75
Noise margins stay unchanged, because V ot.,V 011 • V JL· V 111 only depend on V
110, V,, and V,. Since V, bas not changed, noise margins stay the same.Inorder to
calculate the power dissipation, we need to llrst recalculate.
𝑉𝐷𝐷 −𝑉𝑂𝐿 1,8−0,12
𝐼𝐷𝐷 = = =168 µA
𝑅𝐷 10𝐾Ω
𝑃𝐷 𝑎𝑣𝑒𝑟𝑎𝑛𝑔𝑒 =1/2 𝑃𝐷𝐷 =151 µW

𝑊 𝑊 1
13.6. Conside the inverter in Fig 13.11 with ( 𝐿 )1 = 3 and( 𝐿 )2 = 3, show that if the
minimum dimension (i.e length or each of the two transistor is denoted d1, the inverter
silicon areas in 2𝐾𝑟 𝑑 3
𝑤1
A = 𝑤1 𝐿1 + 𝑤2 𝐿2 since = 𝐾𝑃
𝐿1
𝑤2 1
= , we have 𝑤1 = 𝐾𝑃 𝐿1 , and
𝐿2 𝐾𝑃
𝐿2 = 𝐾𝑃 𝑤2 . We Assuming 𝑡ℎ𝑎𝑡 𝐾𝑃 > 1, we have 𝐿1 – d and 𝑤2 – L
jadi
A = 𝐾𝑃 𝐿1 𝐿1 + 𝑤2 𝑤2 𝐾𝑟 = 𝐾𝑟 L2 1 + 𝐾𝑟 W 2 𝐿2
= k,d2 + 𝐾𝑟 d2 = 2𝐾𝑟 d2