DSP Lab 21-09-2021

Digital Signal Processing Lab IV B.
Tech I Semester
DADI INSTITUTE OF ENGINEERING & TECHNOLOGY

(Approved by A.I.C.T.E., New Delhi & Affiliated to JNTUK, Kakinada)
An ISO 9001:2008, ISO 14001:2004 & OHSAS 18001:2007 Certified Institute. NAAC
ACCREDIATED INSTITUTENH-5, Anakapalle – 531002, Visakhapatnam, A.P.
Phone: 08924-221111 / 221122/9963981111, www.diet.edu.in
DIGITAL SIGNAL PROCESSING

LABORATARY MANUAL
(R16 Regulation)
PREPARED BY
MALLA KISHORE
KUMAR ASSISTANT
PROFESSIR ECE
DEPARTMENT
Department of ECE, Dadi Institute of Engineering and

Digital Signal Processing Lab IV B.Tech I Semester
DIGITAL SIGNAL PROCESSING LABORATORY
List of the Experiments / programs

To Student has to perform at least FOUR Experiments in each part
PART-1( SIGNALS )
1) Generation of discrete time signals for discrete signals
2) To verify the Linear Convolution
a) Using MATLAB
b) Using Code Composer Studio(CCS)
3) To verify the Circular Convolution for discrete signals
a) Using MATLAB
4) To Find the addition of Sinusoidal Signals
5) To verify Discrete Fourier Transform(DFT) and Inverse Discrete Fourier Transform(IDFT)
a) Using MATLAB
6) Transfer Function Stability Analysis: using pole-zero plot, bode plot, Nyquist plot, z-plane plot.
PART-2 ( FILTERS )
7) Frequency Response of IIR low pass Butterworth Filter
8) Frequency Response of IIR high pass Butterworth Filter
9) Frequency Response of IIR low pass Chebyshev Filter
10) Frequency Response of IIR high pass Chebyshev Filter
11) Frequency Response of FIR low pass Filter using Rectangle Window
12) Frequency Response of FIR low pass Filter using Triangle Window
PART – 3( IMAGE PROCESSING )
13) An image processing in a false contouring system
14) To generate the histogram equalization to the image
15) To verify the Normalized Cross Correlation to the addition of noise and removal of noise
using filters to an image.
16) Compute the edge of an image using spatial filters.
17) Perform the image motion blur and calculate PSNR to the noise image and also noise free image.
18) To verify the PSNR to the Second order Decomposition of Discrete Wavelet transforms and to the
reconstructed image using inverse Discrete Wavelet transform

:
Expt No: Date
ARCHITECTURE OF DSP CHIP TMS 320 C6713
AIM: To study the architecture of DSP processor TMS 320 6713 (a floating point DSP)
TMS320C6713 DSK ARCHITECTURE (FLOATING POINT DSP)
TMS320C6713 DSP
The DSK supports a TMS320C6713 DSP which can operate at a clock frequency of up
to 225 MHz. The DSP core is designed for high performance floating point operation. Beyond
the DSP core, the ‘6713 integrate a number of on-chip resources that improve functionality and
minimize hardware development complexity. Features of the processor include:
VLIW Core – VLIW is a processor architecture that allows many instructions to be

issued (8 on the 6713 DSP) in a single clock while still allowing for very high clock rates.
VLIW architectures can achieve extremely high processing rates but put more burdens on the
compiler to schedule concurrently executed instructions. The code generation tools that come
with Code Composer are heavily optimized for this architecture to relieve as much of the
optimization burden from the programmer as possible.

. 192Kbytes Internal Memory – high-speed internal memory for maximum performance.
· 64Kbytes L2 Cache/RAM – four 16Kbyte blocks of internal RAM that can be

configured as RAM or cache.
· 4Kb Program/Data Caches – separate caches for program code and data.
· On-chip PLL – generates processor clock rate from slower external clock reference.
· 2 Timers – generates periodic timer events as a function of the processor clock. Used
by DSP/BIOS to create time slices for multitasking.
· EDMA Controller – Enhanced DMA controller allows high speed data transfers
without intervention from the DSP.
· 2 McBSPs – Multichannel buffered serial ports. Each McBSP can be used for high-
speed serial data transmission with external devices or reprogrammed as general purpose I/Os.
McBSP1 is used to transmit and receive audio data from the AIC23 stereo codec. McBSP0 is
used to control the codec through its serial control port. The MISC register in the CPLD is
used to select whether McBSP0 and McBSP1 are routed to the AIC23 or the expansion
connectors.
· 2 McASPs – Multichannel audio serial ports. Used for multi-channel and professional
audio applications. Not used on the DSK, but brought out to the expansion connectors.
· 2 I2C Interfaces – Inter-Integrated Circuit Bus. An I2C bus is a serial bus format that
can support several standard devices per bus.
· EMIF – External Memory Interface. A 32-bit bus on which external memories and
other devices can be connected. It included features like internal wait state generation and
SDRAM control. The EMIF can interface to both synchronous and asynchronous memories.
For more detailed information on the ‘6713, please see the TMS320C6713 Data Sheet.
CPLD
The C6713 DSK uses an Altera EPM3128TC100-10 Complex Programmable Logic Device
(CPLD) device to implement:
· 4 Memory-mapped control/status registers that allow software control of various board

features.
· Control of the daughter card interface and signals.
· Assorted "glue" logic that ties the board components together.

The CPLD logic is specific to the functionality on the DSK. Your own hardware designs will
likely implement a completely different set of functions or take advantage of the DSPs high
level of integration for system design and avoid the use of external logic completely.
Memory-Mapped Registers
The 4 CPLD memory-mapped registers allow users to control CPLD functions in
software. On the 6713 DSK the registers are primarily used to access the LEDs and DIP
switches and control the daughter card interface. The registers are mapped into the EMIF
CE1 data space at byte address 0x90080000 with a data width of 8 bits. The following table
gives a high level overview of the CPLD registers and their bit fields:
Glue Logic
The CPLD implements simple random logic functions that eliminate the need for
additional discrete devices. In particular, the CPLD aggregates the various reset signals
coming from the reset button and power supervisors and generates a global reset. It is also
used to divide the 24MHz reference clock in half to provide a 12MHz clock to the AIC23.
Device Specifics
The EPM3128TC100-10 is a 3.3V (5V tolerant), 100-pin QFP device that provides 128 macro
cells and up to 80 I/O pins with a 10ns pin-to-pin delay. The device is EEPROM-based and is
in-system programmable via a dedicated JTAG interface (a 10-pin header on the DSK). The
CPLD source files are written in the industry-standard VHDL (Hardware Design Language)
and are included with the DSK on the installation CD-ROM.

EXTERNAL SDRAM
The DSK uses a 64 megabit Synchronous DRAM (SDRAM) on the 32-bit EMIF. The
SDRAM is mapped at the beginning of CE0 (address 0x80000000). Total available memory is
16 megabytes.
The integrated SDRAM controller is part of the EMIF and must be configured in
software for proper operation. Some of the most important parameters are listed below:
Parameter: Value
CE0 Memory Type: 32-bit wide SDRAM
Num. Banks: 4
Num. Row Address Lines: 12
Num. Column Address Lines:8
Refresh Period: 1400
One of the key SDRAM parameters is the refresh period. SDRAMs must be
continuously refreshed or they will become unstable and lose their contents. The DRAM used
on the 6713 DSK must refresh one row every 15.6 microseconds. The configuration shown
above uses a value of 1400 (0x578 in hex notation) to specify a refresh period (1400 x 11.11ns,
the clock period at 90MHz).
EXTERNAL FLASH
Flash is a type of memory, which does not lose its contents when the power is turned
off. When read it looks like a simple asynchronous read-only memory (ROM). Flash can be
erased in large blocks commonly referred to as sectors or pages. Once a block has been erased
each word can be programmed once through a special command sequence. After than the
entire block must be erased again to change the contents.
The DSK uses a 512Kbyte external flash as a boot option. It is visible at the
beginning of CE1 (address 0x90000000). The Flash is wired as a 256K by 16 bit device to
support the DSK's 16-bit boot option. However, the software that ships with the DSK treats
the Flash as an 8-bit device (ignoring the top 8 bits) to match the 6713's default 8-bit boot
mode. In this configuration, only 256Kbytes are readily usable without software changes.
The Flash requires 70ns for both reads and writes. The general settings used with the
DSK use 8 cycles for both read and write strobes (80ns) to leave a little extra margin. The
DSK default is to add two write hold cycles for all asynchronous memories to account for
address propagation delay through the CPLD.

AIC23 CODEC
The DSK uses a Texas Instruments AIC23 (part #TLV320AIC23) stereo codec for
input and output of audio signals. The codec samples analog signals on the microphone or line
inputs and converts them into digital data that can be processed by the DSP. When the DSP
is finished with the data it uses the codec to convert the samples back into analog signals on
the line and headphone outputs so the user can hear the output.
The codec communicates using two serial channels, one to control the codec’s internal
configuration registers and one to send and receive digital audio samples. The AIC23 supports
a variety of configurations that affect the data formats of the control and data channels, the
following summarizes the preferred setup for the 6713 DSK, more detailed descriptions are
given below.
Preferred AIC23 Setup

Control Channel McBSP0, SPI mode with internal clocks and frame syncs.
Data Channel McBSP1, AIC23 in master mode with 12MHz system clock. Data in
codec’s DSP format with each sample consisting of one frame with two 16-bit elements
corresponding to left and right. Clocks and frame syncs generated by the AIC23 external to the
DSP.
4 USER LED
The DSK has eight LEDs made up of four status indicators and four user defined LEDs.
The user-defined indicators are the green LEDs next to the DIPswitches.
User LEDs
The four user controllable LEDs allow for user feedback and display of simple status
information. Writing to the CPLD USER_REG register controls them. They can also be set or
cleared through the LED Module of the Board Support Library.
Status Indicators
The status indicators monitor the following functions. The PWR LED is hardwired on
the +5V supply and will illuminate whenever the power is connected. The RESET LED
illuminates when the RESET event occurs. The USB_IN_USE LED is on when USB
emulation is used and goes off when an external emulator is applied. The USB BUSY LED
indicates that the USB emulator transaction is in progress.
DIP SWITCHES
The four Dipswitches allow simple feedback from the user. The DIP switches can be
read through the CPLD USER_REG registers. They can also be read using the DIP Switch
module of the Board Support Library.
CONFIGURATION SWITCHES
The 6713 DSK has 4 configuration switches that allow users to control the
operational state of the DSP when it is released from reset. The configuration switch block is
labeled SW3 on the DSK board, next to the reset switch.

Configuration switch 1 controls the endianness of the DSP while switches 2 and 3 configure
the boot mode that will be used when the DSP starts executing. Switch 4 determines whether
the HPI or McASP signals come out on shared pins.
Default Settings
The default configuration settings are to have all switches off. This configures the DSK
to boot from the on-board Flash in little endian mode.
DAUGHTER CARD EXTERNAL INTERFACE:

The DSK provides three expansion connectors that can be used to accept a plug-in
daughter card. The daughter card allows users to build on their DSK platform to extend its
capabilities and provide custom and application specific I/O. The expansion connectors are
for memory, peripherals and the Host Port Interface (HPI). For more information on the
expansion interface, please see the 6713 DSK Technical Reference.
Memory, Peripheral and Host Port Interfaces

The memory connector provides access to the DSP’s asynchronous EMIF to interface
with memories and memory-mapped devices. The peripheral connector brings out the DSP’s
peripheral signals like McBSPs, timers and clocks. Both connectors provide power and ground
to the daughter card.
The HPI is a high speed interface that can be used to allow multiple DSP’s to
communicate and cooperate on a given task. The HPI signals are multiplexed with McASP1.
Most of the expansion connector signals are buffered so that the daughter-card cannot
directly influence the operation of the DSK board. The use of TI low-voltage, 5-V tolerant
buffers and CBT interface devices allows the use of either +5V or +3.3V devices to be used
on the daughter-card.
Onboard Connector and Mating Connector:
The three expansion connectors are all 80-pin 0.050 x 0.050 inches low-profile
connectors from Samtec or AMP. The Samtec SFM-series (surface-mount) connectors are
designed for high-speed interconnections because they have low propagation delay,
capacitance, and cross-talk. The connectors present a small footprint on the DSK. Each
connector includes multiple ground, +5V, and +3.3V power signals so that the daughter-card
can obtain power directly from the DSK. The peripheral expansion connector additionally
provides both +12V and -12V to the daughter-card. The recommended

mating connector, whose part number is TFM-140-32-S-D-LC, is a surface-mount

connector that provides a 0.465" mated height.
HPI EXTERNAL INTERFACE
Memory, Peripheral and Host Port Interfaces

The memory connector provides access to the DSP’s asynchronous EMIF to interface
with memories and memory-mapped devices. The peripheral connector brings out the DSP’s
peripheral signals like McBSPs, timers and clocks. Both connectors provide power and ground
to the daughter card.
The HPI is a high-speed interface that can be used to allow multiple DSPs to
communicate and cooperate on a given task. The HPI signals are multiplexed with McASP1.
Most of the expansion connector signals are buffered so that the daughter-card cannot
directly influence the operation of the DSK board. The use of TI low-voltage, 5-V tolerant
buffers and CBT interface devices allows the use of either +5V or +3.3V devices to be used on
the daughter-card.
Onboard Connector and Mating Connector
The three expansion connectors are all 80-pin 0.050 x 0.050 inches low-profile
connectors from Samtec or AMP. The Samtec SFM-series (surface-mount) connectors are
designed for high-speed interconnections because they have low propagation delay,
capacitance, and cross-talk. The connectors present a small footprint on the DSK. Each
connector includes multiple ground, +5V, and +3.3V power signals so that the daughter-card
can obtain power directly from the DSK. The peripheral expansion connector additionally
provides both +12V and -12V to the daughter-card. The recommended mating connector,
whose part number is TFM-140-32-S-D-LC, is a surface-mount connector that provides a
0.465" mated height.
EMBEDDED JTAG EMULATOR

JTAG refers to a set of design rules that encompass testing, programming and
debugging of chips. The JTAG interface allows a user to examine signals and registers on a
chip through an external interface that only uses five extra pins on the chip. In a TI DSP
development environment Code Composer uses the JTAG interface to debug programs

Non-intrusively through hardware device called a JTAG emulator. Benefits of JTAG based
debug include:
· Your target hardware can be debugged in just as if it were a finished product. You
don’t need a special version of your hardware with debug features such as chip test clips or test
points to expose signals or EEPROM sockets to hold code while you try it out.
· You don’t need any special software running on your target hardware. Many systems
use a ROM monitor to transfer debug information from the host to the target. But since the
monitor itself uses resources like memory, interrupt vectors and things like serial ports, your
application must be written with the ROM monitor in mind so it doesn’t conflict with the
monitor and kill your debug session.
· It is much faster and more flexible. You have full access to all of the internal chip
state at the same time, not just what your debug output happens to monitor. You can load
code directly into memory as soon as you have your hardware and immediately take a look at
the internal state. It is much faster than the old "burn and learn technique" where you burn a
program you think will work into an EEPROM, put the EEPROM into a socket on the board
and see what the program does. If it doesn’t work you stare at the code until you figure out
what’s wrong and keep trying.
· On TI DSP platforms you have a high degree of tool re-use across different DSPs and
hardware targets. TI DSPs use a standard 14 pin header across their C2000, C5400, C5500,
C6400, C6200, C6400, C6700 and ARM chips so you can use the same JTAG emulator across
processor families (provided you have the correct emulation drivers and Code Composer for
that family).

Procedure used for running code composer studio:
1. Click on the code composer studio. And create the project your own. i.e is shown below
2.To create the new file. NEW-> Source file

3. Write the program in programming window and save the file in your project.i.e *.c
4.Project ->Add files to Project-> click your file.

5. Project ->Add files to Project->C:\CC Studio\C6000\cgtools\lib\rts6700.lib (file type is

object and library file*.O,*.l*
6. Project ->Add files to Project-> C:\CC Studio \Tutorial->dsk6713->hello1->hello.cmd. (File

type is linker command file)

7.Project -> compile your file.
8. Project-> Build your File.

9.File-> Load the project
Disassembly file is available in the below Window.

10.Debug -> Run (see the result in the Output window.)
RESULT:

SIMULATION RESULT:
1.5
1
u
0.5
0
-10 -8 -6 -4 -2 0 2 4 6 8 10
t
2
1
delta(
0
-10 -8 -6 -4 -2 0 2 4 6 8 10
t
5
r
0
-10 -8 -6 -4 -2 0 2 4 6 8 10
t

Expt No: Date:
GENERATION OF BASIC SIGNALS
AIM: To generate Basic signals using MATLAB
SOFTWARE USED: MATLAB s/w
MATLAB CODE:
%function for generating a unit step

function u=stp_fn(t)
u=0.5*(sign(t+eps)+1);
%a function generating rectangular approximation for the unit impulse

%function; width is delta
function imp=impls_fn(t,delta)
imp=(stp_fn(t+delta/2)-stp_fn(t-delta/2))/delta;
%function for generating a unit ramp

function r=rmp_fn(t)
r=0.5*t.*(sign(t)+1);
%Generate the Unit step, unit impulse and unit ramp functions and plot these functions;
t=-10:0.005:10;
x=stp_fn(t);
subplot(3,1,1),plot(t,x),axis([-10 10 0 1.5]),xlabel('t'),ylabel('u(t)');
y=impls_fn(t);
subplot(3,1,2),plot(t,y),axis([-10 10 0 2]),xlabel('t'),ylabel('delta(t)');
z=rmp_fn(t);
subplot(3,1,3),plot(t,z),axis([-10 10 0 5]),xlabel('t'),ylabel('r(t)');
%Generate the following functions and plot these functions;
%1. A step starting at t=2and going to the right;
%2. A unit impulse at t=-3;
%3. A ramp of slope 2 going backward from t=4;
t=-10:0.005:10;
x=stp_fn(t-2);
y=impls_fn(t+3.5,0.05);
z=2*rmp_fn(4-t);
subplot(3,1,1),plot(t,x),axis([-10 10 0 1.5]),xlabel('t'),ylabel('u(t-2)')
subplot(3,1,2),plot(t,y),axis([-10 10 0 25]),xlabel('t'),ylabel('delta(t+3)')
subplot(3,1,3),plot(t,z),axis([-10 10 0 30]),xlabel('t'),ylabel('2r(4-t)')

SIMULATION RESULT:
1.5
1
u(t-
0.5
0
-10 -8 -6 -4 -2 0 2 4 6 8 10
t
20
delta(t+3
10
0
-10 -8 -6 -4 -2 0 2 4 6 8 10
t
30
20
2r(4
10
0
-10 -8 -6 -4 -2 0 2 4 6 8 10
t

% Generate the following functions and plot these functions;
%1.function generating sine wave;
T=0.2;
t=-1:0.01:1;
x1=sin(2*pi*t/T);
subplot(2,2,1);
plot(t,x1);
xlabel(‘time’);
ylabel(‘Amplitude’);
title(‘Sine Wave’);
%function generating exponential wave;
x2=exp(-2*t);
subplot(2,2,2);
plot(t,x2);
xlabel(‘time’);
title(‘Exponential Wave’);
%1.function generating saw tooth wave;
t1=-20:0.01:+20;
x3=sawtooth(t1);
subplot(2,2,3);
plot(t1,x3);
xlabel(‘time’);
title(‘Sawtooth Wave’);
% function generating square wave;
x4=square(t1);
subplot(2,2,4);
plot(t1,x4);
xlabel(‘time’);
title(‘Square Wave’);
RESULT:

Digital Signal Processing IV B.Tech I
UNDER MODULATION(M<1)
enter the value of mu.5

Expt No: Date:
MATLAB PROGRAM TO GENERATE SUM OF SINUSOIDALS

Aim: To generate amplitude modulation with the following specifications:
Carrier amplitude,AC =1, carrier frequency wc=0.8nc, modulation frequency CO0=0.1TIc with modulation
index mu=0.5,1,2 (-10n < CG < 10n)
Software Used: MATLAB s/w,
MATLAB Program:
clc;
Close all;
clear all;
Ac=1;
wc=.8*pi;
w0=.1*pi;
mu=input('enter the value of mu');
t=0:0.1:199.9;
m= cos(w0*t);
subplot(4,1,1);
plot(t,m);
xlabel('Time(sec)'); ylabel('Amplitude'); title('modulating signal');
c= cos(wc*t);
subplot(4,1,2);
plot(t,c);
xlabel('Time(sec)');
ylabel('Amplitude'); title('Carrier Signal');
s=Ac*(1+mu*m).*c;
subplot(4,1,3);
plot(t,s);
xlabel('Time(s)'); ylabel('Amplitude');
title(['AM modulated signal for mu=',num2str(mu)]);
smag = abs(fftshift(fft(s,2000)))/2000;
%Smag denotes magnitude spectrum of the AM Wave
w=10*(-1000:999)*2*pi/2000;
subplot(4,1,4);
plot(w,smag);

CRITICAL MODULATION(M=1)
enter the value of mu1
OVER MODULATION(M>1)
enter the value of mu2

ylabel('Amplitude');
xlabel('Frequency(rad/s)');
title('Frequency Domain of AM signal');
RESULT:

FREQUENCY RESPONSE OF BUTTERWORTH HIGH PASS FILTER

Expt No: Date:
FREQUENCY RESPONSE OF ANALOG LP/HP FILTERS
AIM: MATLAB Program to find frequency response of analog LP/HP Filters.
SOFTWARE USED: MATLAB s/w.

1. Design an Analog butter worth highpass filter with rp=0.2 dB of ripple in the passband, , and
at least rs=40 dB of attenuation in the stopband, with ws=0.5 and wp=0.875. Plot the filter's
frequency response:
MATLAB PROGRAM FOR ANALOG BUTTERWORTH HIGH PASS FILTER:
ws=0.5;
wp=0.875;
rp=0.2;
rs=40;
[N,WN]=buttord(wp,ws,rp,rs,'s');
[B,A]=butter(N,WN,'high','s');
w=0:0.01:pi;
[H1,om]=freqs(B,A,w);
m=20*log10(abs(H1));
an=angle(H1);
subplot(2,1,1);
plot(om/pi,m);
xlabel(' (a) Normalised frequency');
ylabel(' Gain in dB');
title('BUTTERWORTH HIGH PASS FILTER');
grid;
subplot(2,1,2);
plot(om/pi,an);
xlabel(' (b) Normalised frequency'); ylabel(' Phase in radians'); grid;

FREQUENCY RESPONSE OF CHEBYSHEV HIGH PASS FILTER(TYPE-1)

Aim:Design an Analog CHEBYSHEV TYPE-1 highpass filter with rp=0.29 dB of ripple in the
passband, , and at least rs=29 dB of attenuation in the stopband, with ws=0.24 and wp=0.35.
Plot the filter's frequency response
MATLAB PROGRAM FOR ANALOG CHEBYSHEV TYPE-1 HIGH PASS FILTER:
ws=0.24;
wp=0.35;
rp=0.29;
rs=29;
[N,WN]=cheb1ord(wp,ws,rp,rs,'s');
[B,A]=cheby1(N,rp,WN,'high','s');
w=0:0.01:pi;
[H,om]=freqs(B,A,w);
m=20*log10(abs(H));
an=angle(H);
subplot(2,1,1);
plot(om/pi,m);

title('CHEBYSHEV TYPE-1 HIGH PASS FILTER');
grid;
subplot(2,1,2);
plot(om/pi,an);
xlabel(' (b) Normalised frequency');
ylabel(' Phase in radians');
grid;

FREQUENCY RESPONSE OF CHEBYSHEV HIGH PASS FILTER(TYPE-2)

Aim:Design an Analog CHEBYSHEV TYPE-2 highpass filter with rp=0.34 dB of ripple in the
passband,, and at least rs=34 dB of attenuation in the stopband, with ws=0.28 and wp=0.32.
MATLAB PROGRAM FOR ANALOG CHEBYSHEV TYPE-2 HIGH PASS FILTER:
ws=0.28;
wp=0.32;
rp=0.34;
rs=34;
[B,A]=cheby2(N,rs,WN,'high','s');
w=0:0.01:pi;
m=20*log10(abs(H));
an=angle(H);
subplot(2,1,1);
plot(om/pi,m);
title('CHEBYSHEV TYPE-2 HIGH PASS FILTER');
grid;
subplot(2,1,2);
plot(om/pi,an);
grid;

FREQUENCY RESPONSE OF BUTTERWORTH LOW PASS FILTER

Aim:Design an Analog BUTTERWORTH LOW PASS filter with rp=0.2 dB of ripple in the
passband, , and at least rs=40 dB of attenuation in the stopband, with ws=0.875 and wp=0.5.
MATLAB PROGRAM FOR ANALOG BUTTERWORTH LOW PASS FILTER:
ws=0.875;
wp=0.5;
rp=0.2;
rs=40;
[N,WN]=buttord(wp,ws,rp,rs,'s');
[B,A]=butter(N,WN,'low','s');
w=0:0.01:pi;
[H1,om]=freqs(B,A,w);
m=20*log10(abs(H1));
an=angle(H1);
subplot(2,1,1);
plot(om/pi,m);
title('BUTTERWORTH LOW PASS FILTER');
grid;
subplot(2,1,2);
plot(om/pi,an);
grid;

FREQUENCY RESPONSE OF CHEBYSHEV LOW PASS FILTER(TYPE-1)

Aim:Design an Analog CHEBYSHEV TYPE-1 LOW PASS filter with rp=0.29 dB of ripple
in the passband, , and at least rs=29dB of attenuation in the stopband, with ws=0.35 and
wp=0.24. Plot the filter's frequency response
MATLAB PROGRAM FOR ANALOG CHEBYSHEV TYPE-1 LOW PASS FILTER:
wp=0.24;
ws=0.35;
rp=0.29;
rs=29;
[B,A]=cheby1(N,rp,WN,'low','s');
w=0:0.01:pi;
m=20*log10(abs(H));
an=angle(H);
subplot(2,1,1);
plot(om/pi,m);
title('CHEBYSHEV TYPE-1 LOW PASS FILTER');
grid;
subplot(2,1,2);
plot(om/pi,an);
grid;

FREQUENCY RESPONSE OF CHEBYSHEV LOW PASS FILTER(TYPE-2)

Aim:Design an Analog CHEBYSHEV TYPE-2 LOW PASS filter with rp=0.34 dB of ripple in
the passband, , and at least rs=34 dB of attenuation in the stopband, with ws=0.32 and wp=0.28
MATLAB PROGRAM FOR ANALOG CHEBYSHEV TYPE-2 LOW PASS FILTER:
wp=0.28;
ws=0.32;
rp=0.34;
rs=34;
[B,A]=cheby2(N,rs,WN,'low','s');
w=0:0.01:pi;
m=20*log10(abs(H));
an=angle(H);
subplot(2,1,1);
plot(om/pi,m);
title('CHEBYSHEV TYPE-2 LOW PASS FILTER');
grid;
subplot(2,1,2);
plot(om/pi,an);
grid;
RESULT:

Expt No: Date:
DESIGN OF FIR FILTERS
(Rectangular,Triangular and Kaiser windows)
Aim: To design FIR(LPF/HPF) filters using Rectangular, Triangular and Kaiser windows with 0.04 dB
of ripple in the passband, defined from 0 to 1500 Hz, and at least 0.02 dB of attenuation in the
stopband, defined from 2000 Hz to the Nyquist frequency (8000 Hz). Plot the frequency response of
each filter.(Design a Kaiser Window with P=5.8)
Software Used: MATLAB s/w.
MATLAB PROGRAM FOR FIR FILTERS USING RECTANGULAR WINDOW:
clc;
clear all;
close
all;
rp=0.04;
rs=0.02;
fp=1500;
fs=2000;
f=8000;
wp=2*fp/f;
ws=2*fs/f;
wp
ws
num=-20*log10(sqrt(rp*rs))-13;
dem=14.6*(fs-fp)/f;
n=ceil(num/dem);
n1=n+1;
if (rem(n,2)~=0)
n1=n;
n=n-1;
end
n1

SIMULATION RESULTS:
DESIGN OF FIR FILTERS USING RECTANGULAR WINDOW
50 50
0 0
Gain in dB --
Gain in dB --
-50 -50
-100 -100
0 0.5 1 0 0.5 1
Normalised frequency Normalised frequency
50 20
0
Gain in dB --
Gain in dB -->
0 -20
-40
-50
-60
0 0.5 1
-100
0 0.5 1 Normalised frequency
Normalised frequency

%low pass filter
y=boxcar(n1);
b=fir1(n,wp,y);
[h,o]=freqz(b,1,256);
m=20*log10(abs(h));
subplot(2,2,1);
plot(o/pi,m);
ylabel('Gain in dB -->');
xlabel('Normalised frequency');
%high pass filter
y=boxcar(n1);
n1
b=fir1(n,wp,'high',y);
[h,o]=freqz(b,1,256);
m=20*log10(abs(h));
subplot(2,2,2);
plot(o/pi,m);
%band pass filter
wn=[wp ws];
y=boxcar(n1);
wn
n1
b=fir1(n,wn,y);
[h,o]=freqz(b,1,256);
m=20*log10(abs(h));
subplot(2,2,3);
plot(o/pi,m);

%band stop filter
wn=[wp ws];
y=boxcar(n1);
n1
b=fir1(n,wn,'stop',y);
[h,o]=freqz(b,1,256);
m=20*log10(abs(h));
subplot(2,2,4);
plot(o/pi,m);
MATLAB PROGRAM FOR FIR FILTERS USING TRIANGULAR WINDOW:
clc;
clear all;
close
all;
rp=0.04;
rs=0.02;
fp=1500;
fs=2000;
f=8000;
wp=2*fp/f;
ws=2*fs/f;
num=-20*log10(sqrt(rp*rs))-13;
dem=14.6*(fs-fp)/f;
n=ceil(num/dem);
n1=n+1;
if (rem(n,2)~=0)

SIMULATION RESULTS:
DESIGN OF FIR FILTERS USING TRAINGULAR WINDOW
20 10
0
Gain in dB --
Gain in dB --
0
-10
-20 -20
-40 -30
0 0.5 1 0 0.5 1
20 5
0 0
Gain in dB -->
Gain in dB -->
-20 -5
-40 -10
0 0.5 1 0 0.5 1

n1=n;
n=n-1;
end
%low pass filter

y=triang(n1);
n1
b=fir1(n,wp,y);
[h,o]=freqz(b,1,256);
m=20*log10(abs(h));
subplot(2,2,1);
plot(o/pi,m);
%high pass filter

y=triang(n1);
n1
[h,o]=freqz(b,1,256);
m=20*log10(abs(h));
subplot(2,2,2);
plot(o/pi,m);
%band pass filter

wn=[wp ws];
y=triang(n1);
n1
b=fir1(n,wn,y);
[h,o]=freqz(b,1,256);
m=20*log10(abs(h));

subplot(2,2,3);
plot(o/pi,m);
%band stop filter
wn=[wp ws];
y=triang(n1);
n1
[h,o]=freqz(b,1,256);
m=20*log10(abs(h));
subplot(2,2,4);
plot(o/pi,m);
MATLAB PROGRAM FOR FIR FILTERS USING KAISER WINDOW:
clc;
clear all;
close all;
rp=0.02;
rs=0.01;
fp=1000;
fs=1500;
f=10000;
beta=5.8;
wp=2*fp/f;
ws=2*fs/f;
num=-20*log10(sqrt(rp*rs))-13; dem=14.6*(fs-fp)/f;

SIMULATION RESULTS:
DESIGN OF FIR FILTERS USING KAISER WINDOW
50 50
0
0
Gain in dB --
-50
Gain in dB --
-50
-100
-100
-150
-150
0 0.5 1
0 0.5 1
50
5
0
0
Gain in dB -->
Gain in dB -->
-50
-5
-100
-10
-150
-15
0 0.5 1
0 0.5 1

n=ceil(num/dem);
n1=n+1;
if (rem(n,2)~=0)
n1=n;
n=n-1;
end
%low pass
y=kaiser(n1,beta);
b=fir1(n,wp,y);
[h,o]=freqz(b,1,256);
m=20*log10(abs(h));
subplot(2,2,1);
plot(o/pi,m);
%high pass
y=kaiser(n1,beta);
[h,o]=freqz(b,1,256);
m=20*log10(abs(h));
subplot(2,2,2);
plot(o/pi,m);
%band pass
y=kaiser(n1,beta);
wn=[wp ws];
wn

n1
b=fir1(n,wn,y);
[h,o]=freqz(b,1,256);
m=20*log10(abs(h));
subplot(2,2,3);
plot(o/pi,m);
%band stop
y=kaiser(n1,beta);
wn=[wp ws];
[h,o]=freqz(b,1,256);
m=20*log10(abs(h));
subplot(2,2,4);
plot(o/pi,m);
RESULT:

Expt No: Date:
DESIGN OF IIR FILTERS

Aim: To design Butterworth low pass filter satisfying the constraints
0.707≤ IH(e jm)l ≤1 for 0 < m< π/2
IH(e jm)l ≤0.2 for 3π/4 < m< π

With T=1 sec using (a) bilinear transformation (b) impulse invariance method. Plot the magnitude
response of the filter and compare the two methods by means of order and filter coefficients.
Software Used: MATLAB s/w
MATLAB Code:
% Bilinear transformation:
clc;
clear all;
close all;
wp = 0.5*pi; % digital passband frequency in Hz (normalized)
ws = 0.75*pi; % digital stopband frequency in Hz (normalized)
Rp=20*log10(1/sqrt(2)); % passband ripple in dB
Rp=-Rp;
As = 20*log10(0.2); % stopband attenuation in dB
As=-As;
% Analog Prototype Specifications:
Fs = 1; T = 1/Fs;
OmegaP = wp/T; % prewarp prototype passband frequency
OmegaS = ws/T; % prewarp prototype stopband frequency
% Analog butterworth Prototype Filter Calculation:
[n omegac]=buttord(OmegaP, OmegaS, Rp, As,'s');
[c d] = butter(n,omegac,'s');
% Bilinear Transformation:
[b, a] = bilinear(c, d, Fs);
[h db] = freqz(b,a); plot(db/pi,20*log10(abs(h)));
Axis ([0 1 -20 1]) ;
grid;
xlabel('frequency (Hz)');
ylabel('decibels');
title('Magnitude in dB');

DESIGN OF IIR LOWPASS FILTER
1.USING BILINEAR TRANSFORMATION METHOD
2. 1.USING IMPULSE INVARIANT METHOD

%IMPULSE INVARIENCE METHOD
clc;
clear all;
close all;
Rp=-Rp;
As=-As;
Fs = 1; T = 1/Fs;
[c d] = butter(n,omegac,'s');
[b, a] = impinvar(c, d, Fs);
%
[h db] = freqz(b,a); plot(db/pi,20*log10(abs(h)));
Axis ([0 1 -20 1])
grid
ylabel('decibels');

DESIGN OF IIR HIGH PASS FILTER
1. USING BILINEAR TRANSFORMATION METHOD

IIR FILTER (HIGH PASS)
% Bilinear transformation:
clc;;
clear all;
close all;
Rp=-Rp;
As=-As;
Fs = 1;
T = 1/Fs;
OmegaP = (2/T)*tan(wp/2); % prewarp prototype passband frequency
OmegaS = (2/T)*tan(ws/2); % prewarp prototype stopband frequency
[c d] = butter(n,omegac,'high','s');
[b, a] = bilinear(c, d, Fs);
[h db] = freqz(b,a);
plot(db/pi,20*log10(abs(h)));
axis([0 1 -20 1])
grid
ylabel('decibels');

2. USING IMPULSE INVARIANT METHOD

%IMPULSE INVARIENCE METHOD
clc;;
clear all;
close all;
Rp=-Rp;
As=-As;
Fs = 1;
T = 1/Fs;
[c d] = butter(n,omegac,'high','s');
[b, a] = impinvar(c, d, Fs);
[h db] = freqz(b,a);
plot(db/pi,20*log10(abs(h)));
grid
ylabel('decibels');
RESULT:

SIMULATION RESULTS:
60
40
20
real
-20
0 1 2 3 4 5 6 7 8 9
k
20
10
0
imaginery
-10
-20
0 1 2 3 4 5 6 7 8 9
k

Expt No: Date :
FFT OF A GIVEN 1- D SIGNAL
AIM: To find FFT of a given 1-D signal and plot
SOFTWARE USED :
MATLAB s/w.
MATLAB PROGRAM:
clc;
x =input ('enter the sequence');
n =length(x)
y = fft(x,n);
k=0:n-1;
subplot(2,1,1)
stem(k,real(y));
xlabel('k');
ylabel('real value');
stem(k,imag(y));
xlabel('k');
ylabel('imaginery value');
RESULT:

Expt No: Date:
LINEAR CONVOLUTION
AIM: To Write a program to compute the response of a discrete LTI system with input sequence
x(n)={1,1,2,2} and impulse response h(n)={1,1,2, 2} by using linear convolution on TMS320C6713
DSP kit.
TOOLS REQUIRED:
TMS 320 C6713Kit,
Full version CCS s/w,
DSK 6713 s/w,
THEORY:
Convolution is a special operation, operated between two signals and which includes
the following operations.
❖ Folding.
❖ Shifting.
❖ Multiplication.
❖ Addition
Convolution sum is useful to obtain the response of discrete LTI system with input x(n)
and impulse response h(n).
h(n)
x(n) y(n)
∞
y(n) = x(n) … h(n) = Σx(m)h(n – m)

m=–∞
To obtain the response, we have two types of convolutions.
❖ Linear Convolution.
❖ Circular Convolution.
Linear convoluted sequence y(n) between x(n) with duration N1and h(n) with
duration N2 is defined as

y(n) = N –1
Σ x(m)h(n – m)
m=0
Where N = N1+N2 –1 is the duration of convoluted sequence y(n).
DFT does not support linear convolution, because of x(n) and h(n) are of different
durations. That’s why we can go for circular convolution.
PROCEDURE:
1. Create a Project in CCS

2. Create a source code in C for Linear Convolution
3. Add both hello.cmd & rts6700.lib files to the current project folder from necessary
locations
4. Compile c file for debugging errors.
5. Build the project.
6. Load Program (.out file) into DSK from file menu.
7. Run the program from Debug menu.
8. Plot the Graph of linear convolution from view – graph menu.
C-PROGRAM FOR LINEAR CONVOLUTION:
#include<stdio.h>
int x[20],h[20],y[20],N1,N2,n,m;
main()
printf("Enter the length of input sequence x(n)\t:N1=");
scanf("%d",&N1);
printf("Enter the length of impulse response h(n)\t:N2=");
scanf("%d",&N2);
printf("Enter %d samples for input sequence x(n):\n",N1);

INPUT:
Enter the length of input sequence x(n) :N1= 4
Enter the length of impulse response h(n) :N2=4
Enter 4 samples for input sequence x(n):1 1 2 2
Enter 4 samples for impulse response h(n):1 1 2 2
Response of LT1 system is

y(n) = 1 2 5 8 8 8 4
MODEL GRAPH:
THEORETICAL VALIDATION:

for(n=0;n<N1;n++)
scanf("%d",&x[n]);
printf("Enter %d samples for impulse response h(n):\n",N2);
for(n=0;n<N2;n++)
scanf("%d",&h[n]);
printf("Input sequence \nx(n)=");
for(n=0;n<N1;n++) printf("\t
%d",x[n]);
printf("\nImpulse Response \nh(n)=");
for(n=0;n<N2;n++) printf("\t
%d",h[n]); for(n=0;n<N1+N2-1;n++)
y[n]=0;
for(m=0;m<=n;m++)
y[n]=y[n]+x[m]*h[n-m];
printf("\n Response of LT1 system is\ny(n)=");
for(n=0;n<N1+N2-1;n++)
printf("\t%d",y[n]) ;
RESULT:

Expt No: Date:
CIRCULAR CONVOLUTION
AIM: To Write a program to compute the response of a discrete LTI system with input sequence
x(n)={1,2,3,4} and impulse response h(n)={1,2,3,4} by using Circular convolution on TMS320C6713
DSP kit.
TOOLS REQUIRED:
TMS 320 C6713Kit,
DSK 6713 s/w,
THEORY:
Let h (n) and x (n) be finite-length sequences of length N with N-point DFTs H (k) and
X(k) respectively. The sequence that has a DFT equal to the product Y(k)=H(k)X(k) is
「N –1 ~ ~ º 「 N –1 ~ ~ º
y(n) = |Σ h (k )x (n – k )| R N (n) = |Σ h (n – k)x (k ) | R N (n)
¬k =0 ] ¬k =0 ]
Where ~ ~
x (n) h (n) are the periodic extensions of the sequences x(n) and h(n),respectively.
and
~
Because h (n) =h(n) for 0 ≤ n ≤ N, the sum in equation may also be written as
「 N –1 ~ º
y(n) = |Σ h(k )x (n – k ) | R N (N )
¬k =0 ]
The sequence y(n) in the above equation is the C-point circular convolution of h(n) with
x(n), and it is written as
y(n) = h(n) x(n) = x(n) h(n)
The circular convolution of two finite-length sequences h(n) and x(n) is equivalent to one
~
period of the periodic convolution of the periodic sequences h ~
and x (n),
(n)
~
y(n) = h(n) x(n) = ~ N
[h( … x(n)]R (n)

In general, circular convolution is not the same as linear convolution, and N-point
circular convolution is difference, in general, from M-point circular convolution when M≠N.
CIRCULAR VERSUS LINEAR CONVOLUTION:
In general, circular convolution is not the same as linear convolution. However, there is
a sample relationship between circular and linear convolution that illustrates what steps must
be taken in order to ensure that they are the same. Specially, let x(n) and h(n) be finite-length
sequences and let y(n) be the linear convolution
y(n) = x(n)* h(n)
The N-point circular convolution of x(n) with h(n) is related to y(n) as follows:
「∞
º
h(n) x(n) = Σ kN ) R (n)
| y(n + |N
¬k =–∞ ]
In other words, the circular convolution of two sequences is found by performing the linear
convolution and aliasing the result.
An important property that follows from above eq. is that if y(n) is of the length N or
less,y(n-kN)RN(n)=0 for k≠0 and
h(n) x(n) = h(n) * x(n)
that is, circular convolution is equivalent to linear convolution. Thus, if h(n) and x(n) are finite-
length sequences of length N1 and N2, respectively, y(n)=h(n)*x(n) is of length N1+N2-1, and
the C-point circular convolution is equivalent to linear convolution provided N ≥ N1+ N2 –1.
PROCEDURE:
1. Create a Project in CCS

2. Create a source code in C for Circular Convolution
3. Add both hello.cmd & rts6700.lib files to the current project folder from
necessary locations
4. Compile c file for debugging errors.
5. Build the project.
6. Load Program (.out file) into DSK from file menu.

Enter the length of input sequence x(n) :N1= 4
Enter the length of impulse response h(n) :N2= 4
Enter 4 samples for input sequence x(n): 1 2 3 4

Enter 4 samples for impulse response h(n):1 2 3 4
Response of LT1 system is

y(n)= 26 28 26 20
MODEL GRAPH:
THEORETICAL VALIDATION:

7.Run the program from Debug menu.
8.Plot the Graph of circular convolution from view – graph menu.
C-PROGRAM FOR CIRCULAR CONVOLUTION:

#include<stdio.h>
int m,n,x[30],h[30],y[30],i,j,temp[30],k,x2[30],a[30];
void main()
{
printf("Enter the length of the first sequence:\n");
scanf("%d",&m);
printf("Enter the length of the second sequence:\n");
scanf("%d",&n);
printf("Enter the first sequence:\n");
for(i=0;i<m;i++)
scanf("%d",&x[i]);
printf("Enter the second sequence:\n");
for(j=0;j<n;j++)
scanf("%d",&h[j]);
if(m-n!=0)
{
if(m>n)
{
for(i=n;i<m;i++)
h[i]=0;
n=m;
}
for(i=m;i<n;i++)
x[i]=0;
m=n;
}
y[0]=0;
a[0]=h[0];
for(j=1;j<n;j++) /*folding h(n) to h(-n)*/
a[j]=h[n-j];
/*circular convolution*/
for(i=0;i<n;i++)
y[0]+=x[i]*a[i];
for(k=1;k<n;k++)
{ y[k]=
0;
/*circular shift*/
for(j=1;j<n;j++)
x2[j]=a[j-1];
x2[0]=a[n-1];
for(i=0;i<n;i++)
{
a[i]=x2[i];
y[k]+=x[i]*x2[i];

}
}
/*displaying the result*/
printf("The circular convolution\n");
for(i=0;i<n;i++) printf("%d\
t",y[i]);
}
RESULT:

Expt No: Date:
N-POINT FFT ALGORITHM

AIM: To obtain the frequency spectrum of the given sampled data (input signal) by using Fast
Fourier Transform on TMS320C6713 DSK Kit (or Simulator).
SOFTWARE USED:
TMS 320 C6713Kit,
DSK 6713 s/w.
FFT ALGORITHM:
1. Pad input sequence of N samples with ZERO’s until the number of samples is the nearest
power of two e.g. 500 samples are padded to 512.
2. Bit reverse the input sequence
Ex: 3 = 011 goes to 110 = 6.
3. Compute (N/2) two sample DFT’s from the shuffled inputs
4. Compute (N/4) four sample DFT’s from the two sample DFT’s
5. Compute (N/2) eight sample DFT’s from the four sample DFT’s
6. Until all the samples combine into one N-sample DFT.
PROCEDURE:
1. Open CCS, make sure the DSP kit is turned on

2. Start a new project using ‘Project – new’ menu, save it in a separate directory
3. Add the source files “FFT256.C” and FFT.C in the project
4. Add hello.cmd and rts6700.lib files to the current project.
5. Compile and build the program
6. Load the program into to DSP Kit and run and observe the output using graph utility

C – SOURCE CODE FOR FFT.C
#define PTS 256 //# of points for FFT

typedef struct {float real,imag;} COMPLEX;
extern COMPLEX w[PTS]; //twiddle constants stored in w
void FFT(COMPLEX *Y, int N) //input sample array, # of points

{
COMPLEX temp1,temp2; //temporary storage variables
int i,j,k; //loop counter variables
int upper_leg, lower_leg; //index of upper/lower butterfly leg
int leg_diff; //difference between upper/lower leg
int num_stages = 0; //number of FFT stages (iterations)
int index, step; //index/step through twiddle constant
i = 1; //log(base2) of N points= # of stages
do
{
num_stages +=1;
i = i*2;
}while (i!=N);
leg_diff = N/2; //difference between upper&lower legs
step = (PTS*2)/N; //step between values in twiddle.h // 512
for (i = 0;i < num_stages; i++) //for N-point FFT
{
index = 0;
for (j = 0; j < leg_diff; j++)
{
for (upper_leg = j; upper_leg < N; upper_leg += (2*leg_diff))
{
lower_leg = upper_leg+leg_diff;
temp1.real = (Y[upper_leg]).real + (Y[lower_leg]).real;
temp1.imag = (Y[upper_leg]).imag + (Y[lower_leg]).imag;
temp2.real = (Y[upper_leg]).real - (Y[lower_leg]).real;
temp2.imag = (Y[upper_leg]).imag - (Y[lower_leg]).imag;
(Y[lower_leg]).real = temp2.real*(w[index]).real -temp2.imag*(w[index]).imag;
(Y[lower_leg]).imag = temp2.real*(w[index]).imag +temp2.imag*(w[index]).real;
(Y[upper_leg]).real = temp1.real;
(Y[upper_leg]).imag = temp1.imag;
}
index += step;
}
leg_diff = leg_diff/2;
step *= 2;

}
j = 0;
for (i = 1; i < (N-1); i++) //bit reversal for resequencing data
{
k = N/2;
while (k <= j)
{
j=j-
k; k =
k/2;
}
j=j+
k; if
(i<j)
{
temp1.real = (Y[j]).real;
temp1.imag = (Y[j]).imag;
(Y[j]).real = (Y[i]).real;
(Y[j]).imag = (Y[i]).imag;
(Y[i]).real = temp1.real;
(Y[i]).imag = temp1.imag;
}
}
return;
}
C – SOURCE CODE FOR MAIN.C
#include <math.h>
#define PI 3.14159265358979
void FFT(COMPLEX *Y, int n); //FFT prototype
float iobuffer[PTS]; //as input and output buffer
float x1[PTS]; //intermediate buffer
short i; //general purpose index variable
short buffercount = 0; //number of new samples in io buffer
short flag = 0; //set to 1 by ISR when iobuffer full
COMPLEX w[PTS]; //twiddle constants stored in w
COMPLEX samples[PTS]; //primary working buffer
main()
{
for (i = 0 ; i<PTS ; i++) // set up twiddle constants in w
{
w[i].real = cos(2*PI*i/(PTS*2.0)); //Re component of twiddle constants
w[i].imag =-sin(2*PI*i/(PTS*2.0)); //Im component of twiddle constants
}
for (i = 0 ; i < PTS ; i++) //swap buffers
{
iobuffer[i] = sin(2*PI*30*i/PTS);/*10- > freq,100 -> sampling freq*/

MODEL GRAPH:

samples[i].real=0.0;
samples[i].imag=0.0;
}
{
samples[i].real=iobuffer[i]; //buffer with new data
/* iobuffer[i] = x1[i]; //processed frame to iobuffer*/
}
for (i = 0 ; i < PTS ; i++)
samples[i].imag = 0.0; //imag components = 0
FFT(samples,PTS); //call function FFT.c
for (i = 0 ; i < PTS ; i++) //compute magnitude
{
x1[i] = sqrt(samples[i].real*samples[i].real
+ samples[i].imag*samples[i].imag);///32;
}
}
RESULT:

Expt No: Date:
POWER DENSITY SPECTRUM OF A SEQUENCE
AIM: Design a Program to compute power density spectrum of a sequence.

SOFTWARE USED:
TMS 320 C6713Kit,
DSK 6713 s/w.
C-SOURCE CODE FOR FFT.C

extern COMPLEX w[PTS]; //twiddle constants stored in w
void FFT(COMPLEX *Y, int N) //input sample array, # of points
COMPLEX temp1,temp2; //temporary storage variables
int i,j,k; //loop counter variables
int upper_leg, lower_leg; //index of upper/lower butterfly leg
int leg_diff; //difference between upper/lower leg
int num_stages = 0; //number of FFT stages (iterations)
int index, step; //index/step through twiddle constant
i = 1; //log(base2) of N points= # of stages
do
num_stages +=1;
i = i*2;
}while (i!=N);

leg_diff = N/2; //difference between upper&lower legs
step = (PTS*2)/N; //step between values in twiddle.h // 512
for (i = 0;i < num_stages; i++) //for N-point FFT
index = 0;
for (j = 0; j < leg_diff; j++)
for (upper_leg = j; upper_leg < N; upper_leg += (2*leg_diff))
lower_leg = upper_leg+leg_diff;
temp1.real = (Y[upper_leg]).real + (Y[lower_leg]).real;
temp1.imag = (Y[upper_leg]).imag + (Y[lower_leg]).imag;
temp2.real = (Y[upper_leg]).real - (Y[lower_leg]).real;
temp2.imag = (Y[upper_leg]).imag - (Y[lower_leg]).imag;
(Y[lower_leg]).real = temp2.real*(w[index]).real
-temp2.imag*(w[index]).imag;
(Y[lower_leg]).imag = temp2.real*(w[index]).imag
+temp2.imag*(w[index]).real;
(Y[upper_leg]).real = temp1.real;
(Y[upper_leg]).imag = temp1.imag;
index += step;
leg_diff = leg_diff/2;
step *= 2;
j = 0;
for (i = 1; i < (N-1); i++) //bit reversal for resequencing data

k = N/2;
while (k <= j)
j=j-
k; k =
k/2;
j=j+
k; if
(i<j)
temp1.real = (Y[j]).real;
temp1.imag = (Y[j]).imag;
(Y[j]).real = (Y[i]).real;
(Y[j]).imag = (Y[i]).imag;
(Y[i]).real = temp1.real;
(Y[i]).imag = temp1.imag;
return;
C-SOURCE CODE FOR PSD.C

#include <math.h>
#define PI 3.14159265358979
void FFT(COMPLEX *Y, int n); //FFT prototype

float iobuffer[PTS]; //as input and output buffer
float x1[PTS],x[PTS]; //intermediate buffer

short i; //general purpose index variable
short buffercount = 0; //number of new samples in iobuffer
short flag = 0; //set to 1 by ISR when iobuffer full
float y[128];
COMPLEX w[PTS]; //twiddle constants stored in w
COMPLEX samples[PTS]; //primary working buffer
main()
float j,sum=0.0 ;
int n,k,i,a;
for (i = 0 ; i<PTS ; i++) // set up twiddle constants in w
w[i].real = cos(2*PI*i/(PTS*2.0)); //Re component of twiddle constants
w[i].imag =-sin(2*PI*i/(PTS*2.0)); /*Im component of twiddle constants*/
/****************Input Signal X(n)

********************************************************/
for(i=0,j=0;i<PTS;i++)
{ x[i] = sin(2*PI*5*i/PTS); // Signal x(Fs)=sin(2*pi*f*i/Fs);
samples[i].real=0.0;
samples[i].imag=0.0;
/********************Auto Correlation of X(n)=R(t)

*********************************/
for(n=0;n<PTS;n++)
sum=0;
for(k=0;k<PTS-n;k++)

MODEL GRAPH:

sum=sum+(x[k]*x[n+k]); // Auto Correlation R(t)
iobuffer[n] = sum;
/********************** FFT of R(t) *****************************/
samples[i].real=iobuffer[i]; //buffer with new data
for (i = 0 ; i < PTS ; i++)
samples[i].imag = 0.0; //imag components = 0
FFT(samples,PTS); //call function FFT.c
/******************** PSD *******************************************/
for (i = 0 ; i < PTS ; i++) //compute magnitude
x1[i] = sqrt(samples[i].real*samples[i].real
+ samples[i].imag*samples[i].imag);
RESULT:

10
d[
5
n]
amplitud
0 s[
-5 time index
0 5
8
6 y[n]
s[n]
4
amplitud
2
0
time index
0 5101520253035404550

Expt.No: Date:
MATLAB PROGRAM FOR SIGNAL SMOOTHING
AIM: Write a program for signal smoothing using MATLAB

TOOLS REQUIRED:
MATLAB Software,
Personal Computer.
PROGRAM:
clc;
clear all;
close all;
R = 51;
d = 0.8*(rand(R,1) - 0.5);
m = 0:R-1;
s = 2*m.*(0.9.^m);
x = s+d';
subplot(2,1,1);
plot(m,d','r-',m,s,'g-',m,x,'b-.');
xlabel('time index');
ylabel('amplitude');
legend('d[n]','s[n]','x[n]');
grid;
x1 = [0 0 x];
x2 = [0 x 0];
x3 = [x 0 0];
y = (x1 + x2 + x3)/3;
subplot(2,1,2);
plot(m,y(2:R+1),'r-',m,s,'g-.');
legend('y[n]','s[n]');
xlabel('time index');
ylabel('amplitude');
grid;
RESULT:

DSP Lab 21-09-2021

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Digital Signal Processing Lab IV B.

DADI INSTITUTE OF ENGINEERING & TECHNOLOGY

DIGITAL SIGNAL PROCESSING

Department of ECE, Dadi Institute of Engineering and

DIGITAL SIGNAL PROCESSING LABORATORY

List of the Experiments / programs

Department of ECE, Dadi Institute of Engineering and

Expt No: Date

ARCHITECTURE OF DSP CHIP TMS 320 C6713

TMS320C6713 DSK ARCHITECTURE (FLOATING POINT DSP)

VLIW Core – VLIW is a processor architecture that allows many instructions to be

Department of ECE, Dadi Institute of Engineering and

. 192Kbytes Internal Memory – high-speed internal memory for maximum performance.

· 64Kbytes L2 Cache/RAM – four 16Kbyte blocks of internal RAM that can be

· 4 Memory-mapped control/status registers that allow software control of various board

· Control of the daughter card interface and signals.

· Assorted "glue" logic that ties the board components together.

Department of ECE, Dadi Institute of Engineering and

Department of ECE, Dadi Institute of Engineering and

CE0 Memory Type: 32-bit wide SDRAM

Num. Row Address Lines: 12

Num. Column Address Lines:8

Refresh Period: 1400

Department of ECE, Dadi Institute of Engineering and

Preferred AIC23 Setup

Department of ECE, Dadi Institute of Engineering and

DAUGHTER CARD EXTERNAL INTERFACE:

Memory, Peripheral and Host Port Interfaces

Department of ECE, Dadi Institute of Engineering and

mating connector, whose part number is TFM-140-32-S-D-LC, is a surface-mount

Memory, Peripheral and Host Port Interfaces

Onboard Connector and Mating Connector

EMBEDDED JTAG EMULATOR

Department of ECE, Dadi Institute of Engineering and

Department of ECE, Dadi Institute of Engineering and

Procedure used for running code composer studio:

2.To create the new file. NEW-> Source file

Department of ECE, Dadi Institute of Engineering and

4.Project ->Add files to Project-> click your file.

Department of ECE, Dadi Institute of Engineering and

5. Project ->Add files to Project->C:\CC Studio\C6000\cgtools\lib\rts6700.lib (file type is

6. Project ->Add files to Project-> C:\CC Studio \Tutorial->dsk6713->hello1->hello.cmd. (File

Department of ECE, Dadi Institute of Engineering and

7.Project -> compile your file.

8. Project-> Build your File.

Department of ECE, Dadi Institute of Engineering and

9.File-> Load the project

Disassembly file is available in the below Window.

Department of ECE, Dadi Institute of Engineering and

10.Debug -> Run (see the result in the Output window.)

Department of ECE, Dadi Institute of Engineering and

Department of ECE, Dadi Institute of Engineering and

GENERATION OF BASIC SIGNALS

AIM: To generate Basic signals using MATLAB

SOFTWARE USED: MATLAB s/w

%function for generating a unit step

%a function generating rectangular approximation for the unit impulse

%function for generating a unit ramp

Department of ECE, Dadi Institute of Engineering and